blob: 49f4cafce148d618f1ee6d7b3d202e81a5770aff [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
Jiri Pirko6cf3c972016-07-05 11:27:39 +020042#include <linux/rhashtable.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020043#include <linux/bitops.h>
44#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010045#include <linux/list.h>
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020046#include <linux/dcbnl.h>
Jiri Pirko5e9c16c2016-07-04 08:23:04 +020047#include <linux/in6.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020048#include <net/switchdev.h>
49
Elad Raz3a49b4f2016-01-10 21:06:28 +010050#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020051#include "core.h"
52
53#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel99724c12016-07-04 08:23:14 +020054#define MLXSW_SP_VFID_MAX 6656 /* Bridged VLAN interfaces */
55
56#define MLXSW_SP_RFID_BASE 15360
57#define MLXSW_SP_RIF_MAX 800
Ido Schimmel7f71eb42015-12-15 16:03:37 +010058
Jiri Pirko0d65fc12015-12-03 12:12:28 +010059#define MLXSW_SP_LAG_MAX 64
60#define MLXSW_SP_PORT_PER_LAG_MAX 16
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
Elad Raz53ae6282016-01-10 21:06:26 +010062#define MLXSW_SP_MID_MAX 7000
63
Ido Schimmel18f1e702016-02-26 17:32:31 +010064#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
65
Jiri Pirko53342022016-07-04 08:23:08 +020066#define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
67#define MLXSW_SP_LPM_TREE_MAX 22
68#define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
69
Jiri Pirko6b75c482016-07-04 08:23:09 +020070#define MLXSW_SP_VIRTUAL_ROUTER_MAX 256
71
Ido Schimmel18f1e702016-02-26 17:32:31 +010072#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
73
Ido Schimmel1a198442016-04-06 17:10:02 +020074#define MLXSW_SP_BYTES_PER_CELL 96
75
76#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
Jiri Pirko0f433fa2016-04-14 18:19:24 +020077#define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
Ido Schimmel1a198442016-04-06 17:10:02 +020078
Jiri Pirkoc6022422016-07-05 11:27:46 +020079#define MLXSW_SP_KVD_LINEAR_SIZE 65536 /* entries */
80#define MLXSW_SP_KVD_HASH_SINGLE_SIZE 163840 /* entries */
81#define MLXSW_SP_KVD_HASH_DOUBLE_SIZE 32768 /* entries */
82
Ido Schimmel9f7ec052016-04-06 17:10:14 +020083/* Maximum delay buffer needed in case of PAUSE frames, in cells.
84 * Assumes 100m cable and maximum MTU.
85 */
86#define MLXSW_SP_PAUSE_DELAY 612
87
Ido Schimmeld81a6bd2016-04-06 17:10:16 +020088#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
89
90static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
91{
92 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
93 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
94}
95
Jiri Pirko56ade8f2015-10-16 14:01:37 +020096struct mlxsw_sp_port;
97
Jiri Pirko0d65fc12015-12-03 12:12:28 +010098struct mlxsw_sp_upper {
99 struct net_device *dev;
100 unsigned int ref_count;
101};
102
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200103struct mlxsw_sp_fid {
Ido Schimmel1c800752016-06-20 23:04:20 +0200104 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100105 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200106 unsigned int ref_count;
107 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200108 struct mlxsw_sp_rif *r;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200109 u16 fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100110};
111
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200112struct mlxsw_sp_rif {
113 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200114 unsigned int ref_count;
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200115 struct mlxsw_sp_fid *f;
116 unsigned char addr[ETH_ALEN];
117 int mtu;
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200118 u16 rif;
119};
120
Elad Raz3a49b4f2016-01-10 21:06:28 +0100121struct mlxsw_sp_mid {
122 struct list_head list;
123 unsigned char addr[ETH_ALEN];
124 u16 vid;
125 u16 mid;
126 unsigned int ref_count;
127};
128
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100129static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
130{
131 return MLXSW_SP_VFID_BASE + vfid;
132}
133
Ido Schimmelaac78a42015-12-15 16:03:42 +0100134static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
135{
136 return fid - MLXSW_SP_VFID_BASE;
137}
138
139static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
140{
Ido Schimmel99724c12016-07-04 08:23:14 +0200141 return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE;
142}
143
144static inline bool mlxsw_sp_fid_is_rfid(u16 fid)
145{
146 return fid >= MLXSW_SP_RFID_BASE;
147}
148
149static inline u16 mlxsw_sp_rif_sp_to_fid(u16 rif)
150{
151 return MLXSW_SP_RFID_BASE + rif;
Ido Schimmelaac78a42015-12-15 16:03:42 +0100152}
153
Jiri Pirko078f9c72016-04-14 18:19:19 +0200154struct mlxsw_sp_sb_pr {
155 enum mlxsw_reg_sbpr_mode mode;
156 u32 size;
157};
158
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200159struct mlxsw_cp_sb_occ {
160 u32 cur;
161 u32 max;
162};
163
Jiri Pirko078f9c72016-04-14 18:19:19 +0200164struct mlxsw_sp_sb_cm {
165 u32 min_buff;
166 u32 max_buff;
167 u8 pool;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200168 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200169};
170
171struct mlxsw_sp_sb_pm {
172 u32 min_buff;
173 u32 max_buff;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200174 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200175};
176
177#define MLXSW_SP_SB_POOL_COUNT 4
178#define MLXSW_SP_SB_TC_COUNT 8
179
180struct mlxsw_sp_sb {
181 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
182 struct {
183 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
184 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
185 } ports[MLXSW_PORT_MAX_PORTS];
186};
187
Jiri Pirko5e9c16c2016-07-04 08:23:04 +0200188#define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
189
190struct mlxsw_sp_prefix_usage {
191 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
192};
193
Jiri Pirko53342022016-07-04 08:23:08 +0200194enum mlxsw_sp_l3proto {
195 MLXSW_SP_L3_PROTO_IPV4,
196 MLXSW_SP_L3_PROTO_IPV6,
197};
198
199struct mlxsw_sp_lpm_tree {
200 u8 id; /* tree ID */
201 unsigned int ref_count;
202 enum mlxsw_sp_l3proto proto;
203 struct mlxsw_sp_prefix_usage prefix_usage;
204};
205
Jiri Pirko6b75c482016-07-04 08:23:09 +0200206struct mlxsw_sp_fib;
207
208struct mlxsw_sp_vr {
209 u16 id; /* virtual router ID */
210 bool used;
211 enum mlxsw_sp_l3proto proto;
212 u32 tb_id; /* kernel fib table id */
213 struct mlxsw_sp_lpm_tree *lpm_tree;
214 struct mlxsw_sp_fib *fib;
215};
216
Yotam Gigi763b4b72016-07-21 12:03:17 +0200217enum mlxsw_sp_span_type {
218 MLXSW_SP_SPAN_EGRESS,
219 MLXSW_SP_SPAN_INGRESS
220};
221
222struct mlxsw_sp_span_inspected_port {
223 struct list_head list;
224 enum mlxsw_sp_span_type type;
225 u8 local_port;
226};
227
228struct mlxsw_sp_span_entry {
229 u8 local_port;
230 bool used;
231 struct list_head bound_ports_list;
232 int ref_count;
233 int id;
234};
235
236enum mlxsw_sp_port_mall_action_type {
237 MLXSW_SP_PORT_MALL_MIRROR,
238};
239
240struct mlxsw_sp_port_mall_mirror_tc_entry {
241 u8 to_local_port;
242 bool ingress;
243};
244
245struct mlxsw_sp_port_mall_tc_entry {
246 struct list_head list;
247 unsigned long cookie;
248 enum mlxsw_sp_port_mall_action_type type;
249 union {
250 struct mlxsw_sp_port_mall_mirror_tc_entry mirror;
251 };
252};
253
Jiri Pirko53342022016-07-04 08:23:08 +0200254struct mlxsw_sp_router {
255 struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT];
Jiri Pirko6b75c482016-07-04 08:23:09 +0200256 struct mlxsw_sp_vr vrs[MLXSW_SP_VIRTUAL_ROUTER_MAX];
Jiri Pirko6cf3c972016-07-05 11:27:39 +0200257 struct rhashtable neigh_ht;
Yotam Gigic723c7352016-07-05 11:27:43 +0200258 struct {
259 struct delayed_work dw;
260 unsigned long interval; /* ms */
261 } neighs_update;
Yotam Gigi0b2361d2016-07-05 11:27:52 +0200262 struct delayed_work nexthop_probe_dw;
263#define MLXSW_SP_UNRESOLVED_NH_PROBE_INTERVAL 5000 /* ms */
Jiri Pirkoa7ff87a2016-07-05 11:27:50 +0200264 struct list_head nexthop_group_list;
Yotam Gigib2157142016-07-05 11:27:51 +0200265 struct list_head nexthop_neighs_list;
Jiri Pirko53342022016-07-04 08:23:08 +0200266};
267
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200268struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100269 struct {
270 struct list_head list;
Ido Schimmel99724c12016-07-04 08:23:14 +0200271 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +0200272 } vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100273 struct {
274 struct list_head list;
Ido Schimmeld8651fd2016-06-20 23:04:07 +0200275 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
Elad Raz3a49b4f2016-01-10 21:06:28 +0100276 } br_mids;
Ido Schimmel14d39462016-06-20 23:04:15 +0200277 struct list_head fids; /* VLAN-aware bridge FIDs */
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200278 struct mlxsw_sp_rif *rifs[MLXSW_SP_RIF_MAX];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200279 struct mlxsw_sp_port **ports;
280 struct mlxsw_core *core;
281 const struct mlxsw_bus_info *bus_info;
282 unsigned char base_mac[ETH_ALEN];
283 struct {
284 struct delayed_work dw;
285#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
286 unsigned int interval; /* ms */
287 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800288#define MLXSW_SP_MIN_AGEING_TIME 10
289#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200290#define MLXSW_SP_DEFAULT_AGEING_TIME 300
291 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100292 struct mlxsw_sp_upper master_bridge;
293 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
Ido Schimmel558c2d52016-02-26 17:32:29 +0100294 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko078f9c72016-04-14 18:19:19 +0200295 struct mlxsw_sp_sb sb;
Jiri Pirko53342022016-07-04 08:23:08 +0200296 struct mlxsw_sp_router router;
Jiri Pirkob090ef02016-07-05 11:27:47 +0200297 struct {
298 DECLARE_BITMAP(usage, MLXSW_SP_KVD_LINEAR_SIZE);
299 } kvdl;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200300
301 struct {
302 struct mlxsw_sp_span_entry *entries;
303 int entries_count;
304 } span;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200305};
306
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100307static inline struct mlxsw_sp_upper *
308mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
309{
310 return &mlxsw_sp->lags[lag_id];
311}
312
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200313struct mlxsw_sp_port_pcpu_stats {
314 u64 rx_packets;
315 u64 rx_bytes;
316 u64 tx_packets;
317 u64 tx_bytes;
318 struct u64_stats_sync syncp;
319 u32 tx_dropped;
320};
321
322struct mlxsw_sp_port {
Jiri Pirko932762b2016-04-08 19:11:21 +0200323 struct mlxsw_core_port core_port; /* must be first */
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200324 struct net_device *dev;
325 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
326 struct mlxsw_sp *mlxsw_sp;
327 u8 local_port;
328 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100329 u8 learning:1,
330 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100331 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100332 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100333 lagged:1,
334 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200335 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100336 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100337 struct {
338 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200339 struct mlxsw_sp_fid *f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100340 u16 vid;
341 } vport;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200342 struct {
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200343 u8 tx_pause:1,
Ido Schimmel0c83f882016-09-12 13:26:23 +0200344 rx_pause:1,
345 autoneg:1;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200346 } link;
347 struct {
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200348 struct ieee_ets *ets;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200349 struct ieee_maxrate *maxrate;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200350 struct ieee_pfc *pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200351 } dcb;
Ido Schimmeld664b412016-06-09 09:51:40 +0200352 struct {
353 u8 module;
354 u8 width;
355 u8 lane;
356 } mapping;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200357 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100358 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100359 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200360 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100361 struct list_head vports_list;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200362 /* TC handles */
363 struct list_head mall_tc_list;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200364 struct {
365 #define MLXSW_HW_STATS_UPDATE_TIME HZ
366 struct rtnl_link_stats64 *cache;
367 struct delayed_work update_dw;
368 } hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200369};
370
Jiri Pirko7ce856a2016-07-04 08:23:12 +0200371struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev);
372void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port);
373
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200374static inline bool
375mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
376{
377 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
378}
379
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100380static inline struct mlxsw_sp_port *
381mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
382{
383 struct mlxsw_sp_port *mlxsw_sp_port;
384 u8 local_port;
385
386 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
387 lag_id, port_index);
388 mlxsw_sp_port = mlxsw_sp->ports[local_port];
389 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
390}
391
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100392static inline u16
393mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
394{
395 return mlxsw_sp_vport->vport.vid;
396}
397
Ido Schimmel6381b3a2016-06-20 23:04:16 +0200398static inline bool
399mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
400{
401 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
402
403 return vid != 0;
404}
405
Ido Schimmel41b996c2016-06-20 23:04:17 +0200406static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
407 struct mlxsw_sp_fid *f)
408{
409 mlxsw_sp_vport->vport.f = f;
410}
411
412static inline struct mlxsw_sp_fid *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200413mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100414{
Ido Schimmel41b996c2016-06-20 23:04:17 +0200415 return mlxsw_sp_vport->vport.f;
416}
417
418static inline struct net_device *
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +0200419mlxsw_sp_vport_dev_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel41b996c2016-06-20 23:04:17 +0200420{
421 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
422
Ido Schimmel56918b62016-06-20 23:04:18 +0200423 return f ? f->dev : NULL;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100424}
425
426static inline struct mlxsw_sp_port *
427mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
428{
429 struct mlxsw_sp_port *mlxsw_sp_vport;
430
431 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
432 vport.list) {
433 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
434 return mlxsw_sp_vport;
435 }
436
437 return NULL;
438}
439
Ido Schimmelaac78a42015-12-15 16:03:42 +0100440static inline struct mlxsw_sp_port *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200441mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
442 u16 fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100443{
444 struct mlxsw_sp_port *mlxsw_sp_vport;
445
446 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
447 vport.list) {
Ido Schimmel41b996c2016-06-20 23:04:17 +0200448 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
449
Ido Schimmel56918b62016-06-20 23:04:18 +0200450 if (f && f->fid == fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100451 return mlxsw_sp_vport;
452 }
453
454 return NULL;
455}
456
Ido Schimmel701b1862016-07-04 08:23:16 +0200457static inline struct mlxsw_sp_fid *mlxsw_sp_fid_find(struct mlxsw_sp *mlxsw_sp,
458 u16 fid)
459{
460 struct mlxsw_sp_fid *f;
461
462 list_for_each_entry(f, &mlxsw_sp->fids, list)
463 if (f->fid == fid)
464 return f;
465
466 return NULL;
467}
468
469static inline struct mlxsw_sp_fid *
470mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp,
471 const struct net_device *br_dev)
472{
473 struct mlxsw_sp_fid *f;
474
475 list_for_each_entry(f, &mlxsw_sp->vfids.list, list)
476 if (f->dev == br_dev)
477 return f;
478
479 return NULL;
480}
481
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200482static inline struct mlxsw_sp_rif *
483mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
484 const struct net_device *dev)
485{
486 int i;
487
488 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
489 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
490 return mlxsw_sp->rifs[i];
491
492 return NULL;
493}
494
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200495enum mlxsw_sp_flood_table {
496 MLXSW_SP_FLOOD_TABLE_UC,
497 MLXSW_SP_FLOOD_TABLE_BM,
498};
499
500int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200501void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200502int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200503int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
504 unsigned int sb_index, u16 pool_index,
505 struct devlink_sb_pool_info *pool_info);
506int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
507 unsigned int sb_index, u16 pool_index, u32 size,
508 enum devlink_sb_threshold_type threshold_type);
509int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
510 unsigned int sb_index, u16 pool_index,
511 u32 *p_threshold);
512int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
513 unsigned int sb_index, u16 pool_index,
514 u32 threshold);
515int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
516 unsigned int sb_index, u16 tc_index,
517 enum devlink_sb_pool_type pool_type,
518 u16 *p_pool_index, u32 *p_threshold);
519int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
520 unsigned int sb_index, u16 tc_index,
521 enum devlink_sb_pool_type pool_type,
522 u16 pool_index, u32 threshold);
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200523int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
524 unsigned int sb_index);
525int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
526 unsigned int sb_index);
527int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
528 unsigned int sb_index, u16 pool_index,
529 u32 *p_cur, u32 *p_max);
530int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
531 unsigned int sb_index, u16 tc_index,
532 enum devlink_sb_pool_type pool_type,
533 u32 *p_cur, u32 *p_max);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534
535int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
536void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
537int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
538void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
539void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
540int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
541 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
542 u16 vid);
543int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
544 u16 vid_end, bool is_member, bool untagged);
Ido Schimmele6060022016-06-20 23:04:11 +0200545int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
Ido Schimmel47a0a9e2016-06-20 23:04:08 +0200546 bool set);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100547void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100548int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +0200549int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200550int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid,
551 bool adding);
Ido Schimmel701b1862016-07-04 08:23:16 +0200552struct mlxsw_sp_fid *mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid);
553void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fid *f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +0200554void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
555 struct mlxsw_sp_rif *r);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200556int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
557 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
558 bool dwrr, u8 dwrr_weight);
559int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
560 u8 switch_prio, u8 tclass);
561int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200562 u8 *prio_tc, bool pause_en,
563 struct ieee_pfc *my_pfc);
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200564int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
565 enum mlxsw_reg_qeec_hr hr, u8 index,
566 u8 next_index, u32 maxrate);
Ido Schimmel584d73d2016-08-24 12:00:26 +0200567int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
568 u16 vid_begin, u16 vid_end,
569 bool learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200570
Ido Schimmelf00817d2016-04-06 17:10:09 +0200571#ifdef CONFIG_MLXSW_SPECTRUM_DCB
572
573int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
574void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
575
576#else
577
578static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
579{
580 return 0;
581}
582
583static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
584{}
585
586#endif
587
Ido Schimmel464dce12016-07-02 11:00:15 +0200588int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
589void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko61c503f2016-07-04 08:23:11 +0200590int mlxsw_sp_router_fib4_add(struct mlxsw_sp_port *mlxsw_sp_port,
591 const struct switchdev_obj_ipv4_fib *fib4,
592 struct switchdev_trans *trans);
593int mlxsw_sp_router_fib4_del(struct mlxsw_sp_port *mlxsw_sp_port,
594 const struct switchdev_obj_ipv4_fib *fib4);
Jiri Pirko6cf3c972016-07-05 11:27:39 +0200595int mlxsw_sp_router_neigh_construct(struct net_device *dev,
596 struct neighbour *n);
597void mlxsw_sp_router_neigh_destroy(struct net_device *dev,
598 struct neighbour *n);
Jiri Pirkoe7322632016-09-01 10:37:43 +0200599int mlxsw_sp_router_netevent_event(struct notifier_block *unused,
600 unsigned long event, void *ptr);
Ido Schimmel464dce12016-07-02 11:00:15 +0200601
Jiri Pirkob090ef02016-07-05 11:27:47 +0200602int mlxsw_sp_kvdl_alloc(struct mlxsw_sp *mlxsw_sp, unsigned int entry_count);
603void mlxsw_sp_kvdl_free(struct mlxsw_sp *mlxsw_sp, int entry_index);
604
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200605#endif