blob: 21b901cfa2d65fbf5e5ece47114140d38d0693e7 [file] [log] [blame]
oulijun9a443532016-07-21 19:06:38 +08001/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
Salil528f1de2016-08-24 04:44:50 +080033#include <linux/acpi.h>
oulijun9a443532016-07-21 19:06:38 +080034#include <linux/of_platform.h>
Arnd Bergmann3ecc16c2017-02-17 15:38:26 +010035#include <linux/module.h>
oulijun9a443532016-07-21 19:06:38 +080036#include <rdma/ib_addr.h>
37#include <rdma/ib_smi.h>
38#include <rdma/ib_user_verbs.h>
Shaobo Xu82547462016-11-23 19:41:08 +000039#include <rdma/ib_cache.h>
oulijun9a443532016-07-21 19:06:38 +080040#include "hns_roce_common.h"
41#include "hns_roce_device.h"
Leon Romanovsky4d409952016-10-19 20:13:07 +030042#include <rdma/hns-abi.h>
oulijun9a443532016-07-21 19:06:38 +080043#include "hns_roce_hem.h"
44
45/**
oulijun9a443532016-07-21 19:06:38 +080046 * hns_get_gid_index - Get gid index.
47 * @hr_dev: pointer to structure hns_roce_dev.
48 * @port: port, value range: 0 ~ MAX
49 * @gid_index: gid_index, value range: 0 ~ MAX
50 * Description:
51 * N ports shared gids, allocation method as follow:
52 * GID[0][0], GID[1][0],.....GID[N - 1][0],
53 * GID[0][0], GID[1][0],.....GID[N - 1][0],
54 * And so on
55 */
56int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
57{
58 return gid_index * hr_dev->caps.num_ports + port;
59}
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +080060EXPORT_SYMBOL_GPL(hns_get_gid_index);
oulijun9a443532016-07-21 19:06:38 +080061
Wei Hu(Xavier)a74dc412017-09-29 23:10:09 +080062static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
oulijun9a443532016-07-21 19:06:38 +080063{
64 u8 phy_port;
65 u32 i = 0;
66
67 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
Wei Hu(Xavier)a74dc412017-09-29 23:10:09 +080068 return 0;
oulijun9a443532016-07-21 19:06:38 +080069
70 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
71 hr_dev->dev_addr[port][i] = addr[i];
72
73 phy_port = hr_dev->iboe.phy_port[port];
Wei Hu(Xavier)a74dc412017-09-29 23:10:09 +080074 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
oulijun9a443532016-07-21 19:06:38 +080075}
76
Parav Pandit414448d2018-04-01 15:08:24 +030077static int hns_roce_add_gid(const union ib_gid *gid,
Shaobo Xu82547462016-11-23 19:41:08 +000078 const struct ib_gid_attr *attr, void **context)
oulijun9a443532016-07-21 19:06:38 +080079{
Parav Pandit414448d2018-04-01 15:08:24 +030080 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
81 u8 port = attr->port_num - 1;
Shaobo Xu82547462016-11-23 19:41:08 +000082 unsigned long flags;
Wei Hu(Xavier)b5ff0f62017-10-26 17:10:25 +080083 int ret;
oulijun9a443532016-07-21 19:06:38 +080084
Shaobo Xu82547462016-11-23 19:41:08 +000085 if (port >= hr_dev->caps.num_ports)
86 return -EINVAL;
87
88 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
89
Parav Pandit414448d2018-04-01 15:08:24 +030090 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index,
91 (union ib_gid *)gid, attr);
Shaobo Xu82547462016-11-23 19:41:08 +000092
93 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
94
Wei Hu(Xavier)b5ff0f62017-10-26 17:10:25 +080095 return ret;
Shaobo Xu82547462016-11-23 19:41:08 +000096}
97
Parav Pandit414448d2018-04-01 15:08:24 +030098static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
Shaobo Xu82547462016-11-23 19:41:08 +000099{
Parav Pandit414448d2018-04-01 15:08:24 +0300100 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
oulijun173bc6b2018-02-07 17:49:28 +0800101 struct ib_gid_attr zattr = { };
Parav Pandit414448d2018-04-01 15:08:24 +0300102 u8 port = attr->port_num - 1;
Shaobo Xu82547462016-11-23 19:41:08 +0000103 unsigned long flags;
Wei Hu(Xavier)b5ff0f62017-10-26 17:10:25 +0800104 int ret;
Shaobo Xu82547462016-11-23 19:41:08 +0000105
106 if (port >= hr_dev->caps.num_ports)
107 return -EINVAL;
108
109 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
110
Parav Pandit414448d2018-04-01 15:08:24 +0300111 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
Shaobo Xu82547462016-11-23 19:41:08 +0000112
113 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
114
Wei Hu(Xavier)b5ff0f62017-10-26 17:10:25 +0800115 return ret;
oulijun9a443532016-07-21 19:06:38 +0800116}
117
118static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
119 unsigned long event)
120{
Wei Hu(Xavier)13ca9702017-08-30 17:23:02 +0800121 struct device *dev = hr_dev->dev;
oulijun9a443532016-07-21 19:06:38 +0800122 struct net_device *netdev;
Wei Hu(Xavier)a74dc412017-09-29 23:10:09 +0800123 int ret = 0;
oulijun9a443532016-07-21 19:06:38 +0800124
125 netdev = hr_dev->iboe.netdevs[port];
126 if (!netdev) {
127 dev_err(dev, "port(%d) can't find netdev\n", port);
128 return -ENODEV;
129 }
130
oulijun9a443532016-07-21 19:06:38 +0800131 switch (event) {
132 case NETDEV_UP:
133 case NETDEV_CHANGE:
134 case NETDEV_REGISTER:
135 case NETDEV_CHANGEADDR:
Wei Hu(Xavier)a74dc412017-09-29 23:10:09 +0800136 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
oulijun9a443532016-07-21 19:06:38 +0800137 break;
138 case NETDEV_DOWN:
139 /*
Salile84e40be2016-11-23 19:41:09 +0000140 * In v1 engine, only support all ports closed together.
141 */
oulijun9a443532016-07-21 19:06:38 +0800142 break;
143 default:
144 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
145 break;
146 }
147
Wei Hu(Xavier)a74dc412017-09-29 23:10:09 +0800148 return ret;
oulijun9a443532016-07-21 19:06:38 +0800149}
150
151static int hns_roce_netdev_event(struct notifier_block *self,
152 unsigned long event, void *ptr)
153{
154 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
155 struct hns_roce_ib_iboe *iboe = NULL;
156 struct hns_roce_dev *hr_dev = NULL;
157 u8 port = 0;
158 int ret = 0;
159
160 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
161 iboe = &hr_dev->iboe;
162
163 for (port = 0; port < hr_dev->caps.num_ports; port++) {
164 if (dev == iboe->netdevs[port]) {
165 ret = handle_en_event(hr_dev, port, event);
166 if (ret)
167 return NOTIFY_DONE;
168 break;
169 }
170 }
171
172 return NOTIFY_DONE;
173}
174
Shaobo Xu82547462016-11-23 19:41:08 +0000175static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
oulijun9a443532016-07-21 19:06:38 +0800176{
Wei Hu(Xavier)a74dc412017-09-29 23:10:09 +0800177 int ret;
Shaobo Xu82547462016-11-23 19:41:08 +0000178 u8 i;
oulijun9a443532016-07-21 19:06:38 +0800179
180 for (i = 0; i < hr_dev->caps.num_ports; i++) {
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800181 if (hr_dev->hw->set_mtu)
182 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
183 hr_dev->caps.max_mtu);
Wei Hu(Xavier)a74dc412017-09-29 23:10:09 +0800184 ret = hns_roce_set_mac(hr_dev, i,
185 hr_dev->iboe.netdevs[i]->dev_addr);
186 if (ret)
187 return ret;
oulijun9a443532016-07-21 19:06:38 +0800188 }
189
Shaobo Xu82547462016-11-23 19:41:08 +0000190 return 0;
oulijun9a443532016-07-21 19:06:38 +0800191}
192
193static int hns_roce_query_device(struct ib_device *ib_dev,
194 struct ib_device_attr *props,
195 struct ib_udata *uhw)
196{
197 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
198
199 memset(props, 0, sizeof(*props));
200
oulijunad18e202018-05-04 10:57:06 +0800201 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
oulijun9a443532016-07-21 19:06:38 +0800202 props->max_mr_size = (u64)(~(0ULL));
203 props->page_size_cap = hr_dev->caps.page_size_cap;
204 props->vendor_id = hr_dev->vendor_id;
205 props->vendor_part_id = hr_dev->vendor_part_id;
206 props->hw_ver = hr_dev->hw_rev;
207 props->max_qp = hr_dev->caps.num_qps;
208 props->max_qp_wr = hr_dev->caps.max_wqes;
209 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
Lijun Oua74aab62016-09-15 23:48:08 +0100210 IB_DEVICE_RC_RNR_NAK_GEN;
Wei Hu(Xavier)cfc85f32017-08-30 17:23:04 +0800211 props->max_sge = max(hr_dev->caps.max_sq_sg, hr_dev->caps.max_rq_sg);
oulijun9a443532016-07-21 19:06:38 +0800212 props->max_sge_rd = 1;
213 props->max_cq = hr_dev->caps.num_cqs;
214 props->max_cqe = hr_dev->caps.max_cqes;
215 props->max_mr = hr_dev->caps.num_mtpts;
216 props->max_pd = hr_dev->caps.num_pds;
217 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
218 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
219 props->atomic_cap = IB_ATOMIC_NONE;
220 props->max_pkeys = 1;
221 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
222
223 return 0;
224}
225
Lijun Ou2eefca22016-09-15 23:48:06 +0100226static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
227 u8 port_num)
228{
229 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
230 struct net_device *ndev;
231
232 if (port_num < 1 || port_num > hr_dev->caps.num_ports)
233 return NULL;
234
235 rcu_read_lock();
236
237 ndev = hr_dev->iboe.netdevs[port_num - 1];
238 if (ndev)
239 dev_hold(ndev);
240
241 rcu_read_unlock();
242 return ndev;
243}
244
oulijun9a443532016-07-21 19:06:38 +0800245static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
246 struct ib_port_attr *props)
247{
248 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
Wei Hu(Xavier)13ca9702017-08-30 17:23:02 +0800249 struct device *dev = hr_dev->dev;
oulijun9a443532016-07-21 19:06:38 +0800250 struct net_device *net_dev;
251 unsigned long flags;
252 enum ib_mtu mtu;
253 u8 port;
254
255 assert(port_num > 0);
256 port = port_num - 1;
257
Or Gerlitzc4550c62017-01-24 13:02:39 +0200258 /* props being zeroed by the caller, avoid zeroing it here */
oulijun9a443532016-07-21 19:06:38 +0800259
260 props->max_mtu = hr_dev->caps.max_mtu;
261 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
262 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
263 IB_PORT_VENDOR_CLASS_SUP |
264 IB_PORT_BOOT_MGMT_SUP;
265 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
266 props->pkey_tbl_len = 1;
267 props->active_width = IB_WIDTH_4X;
268 props->active_speed = 1;
269
270 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
271
272 net_dev = hr_dev->iboe.netdevs[port];
273 if (!net_dev) {
274 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
275 dev_err(dev, "find netdev %d failed!\r\n", port);
276 return -EINVAL;
277 }
278
279 mtu = iboe_get_mtu(net_dev->mtu);
280 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
281 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
282 IB_PORT_ACTIVE : IB_PORT_DOWN;
283 props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
284
285 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
286
287 return 0;
288}
289
290static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
291 u8 port_num)
292{
293 return IB_LINK_LAYER_ETHERNET;
294}
295
oulijun9a443532016-07-21 19:06:38 +0800296static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
297 u16 *pkey)
298{
299 *pkey = PKEY_ID;
300
301 return 0;
302}
303
304static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
305 struct ib_device_modify *props)
306{
307 unsigned long flags;
308
309 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
310 return -EOPNOTSUPP;
311
312 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
313 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
314 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
315 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
316 }
317
318 return 0;
319}
320
321static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
322 struct ib_port_modify *props)
323{
324 return 0;
325}
326
327static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
328 struct ib_udata *udata)
329{
330 int ret = 0;
331 struct hns_roce_ucontext *context;
Yixian Liudf7e4042018-03-19 21:36:07 +0800332 struct hns_roce_ib_alloc_ucontext_resp resp = {};
oulijun9a443532016-07-21 19:06:38 +0800333 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
334
Wei Hu(Xavier)cb7a94c2018-05-28 19:39:24 +0800335 if (!hr_dev->active)
336 return ERR_PTR(-EAGAIN);
337
oulijun9a443532016-07-21 19:06:38 +0800338 resp.qp_tab_size = hr_dev->caps.num_qps;
339
340 context = kmalloc(sizeof(*context), GFP_KERNEL);
341 if (!context)
342 return ERR_PTR(-ENOMEM);
343
344 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
345 if (ret)
346 goto error_fail_uar_alloc;
347
Wei Hu(Xavier)fedc3ab2018-05-28 19:39:27 +0800348 INIT_LIST_HEAD(&context->vma_list);
349 mutex_init(&context->vma_list_mutex);
Yixian Liue088a682018-03-09 18:36:29 +0800350 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
351 INIT_LIST_HEAD(&context->page_list);
352 mutex_init(&context->page_mutex);
353 }
354
oulijun9a443532016-07-21 19:06:38 +0800355 ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
356 if (ret)
357 goto error_fail_copy_to_udata;
358
359 return &context->ibucontext;
360
361error_fail_copy_to_udata:
362 hns_roce_uar_free(hr_dev, &context->uar);
363
364error_fail_uar_alloc:
365 kfree(context);
366
367 return ERR_PTR(ret);
368}
369
370static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
371{
372 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
373
374 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
375 kfree(context);
376
377 return 0;
378}
379
Wei Hu(Xavier)fedc3ab2018-05-28 19:39:27 +0800380static void hns_roce_vma_open(struct vm_area_struct *vma)
381{
382 vma->vm_ops = NULL;
383}
384
385static void hns_roce_vma_close(struct vm_area_struct *vma)
386{
387 struct hns_roce_vma_data *vma_data;
388
389 vma_data = (struct hns_roce_vma_data *)vma->vm_private_data;
390 vma_data->vma = NULL;
391 mutex_lock(vma_data->vma_list_mutex);
392 list_del(&vma_data->list);
393 mutex_unlock(vma_data->vma_list_mutex);
394 kfree(vma_data);
395}
396
397static const struct vm_operations_struct hns_roce_vm_ops = {
398 .open = hns_roce_vma_open,
399 .close = hns_roce_vma_close,
400};
401
402static int hns_roce_set_vma_data(struct vm_area_struct *vma,
403 struct hns_roce_ucontext *context)
404{
405 struct list_head *vma_head = &context->vma_list;
406 struct hns_roce_vma_data *vma_data;
407
408 vma_data = kzalloc(sizeof(*vma_data), GFP_KERNEL);
409 if (!vma_data)
410 return -ENOMEM;
411
412 vma_data->vma = vma;
413 vma_data->vma_list_mutex = &context->vma_list_mutex;
414 vma->vm_private_data = vma_data;
415 vma->vm_ops = &hns_roce_vm_ops;
416
417 mutex_lock(&context->vma_list_mutex);
418 list_add(&vma_data->list, vma_head);
419 mutex_unlock(&context->vma_list_mutex);
420
421 return 0;
422}
423
oulijun9a443532016-07-21 19:06:38 +0800424static int hns_roce_mmap(struct ib_ucontext *context,
425 struct vm_area_struct *vma)
426{
Wei Hu (Xavier)8f3e9f32016-11-23 19:41:00 +0000427 struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
428
oulijun9a443532016-07-21 19:06:38 +0800429 if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
430 return -EINVAL;
431
432 if (vma->vm_pgoff == 0) {
433 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
434 if (io_remap_pfn_range(vma, vma->vm_start,
435 to_hr_ucontext(context)->uar.pfn,
436 PAGE_SIZE, vma->vm_page_prot))
437 return -EAGAIN;
Wei Hu(Xavier)5caad672017-08-30 17:23:17 +0800438 } else if (vma->vm_pgoff == 1 && hr_dev->tptr_dma_addr &&
439 hr_dev->tptr_size) {
Wei Hu (Xavier)8f3e9f32016-11-23 19:41:00 +0000440 /* vm_pgoff: 1 -- TPTR */
441 if (io_remap_pfn_range(vma, vma->vm_start,
442 hr_dev->tptr_dma_addr >> PAGE_SHIFT,
443 hr_dev->tptr_size,
444 vma->vm_page_prot))
445 return -EAGAIN;
446 } else
oulijun9a443532016-07-21 19:06:38 +0800447 return -EINVAL;
oulijun9a443532016-07-21 19:06:38 +0800448
Wei Hu(Xavier)fedc3ab2018-05-28 19:39:27 +0800449 return hns_roce_set_vma_data(vma, to_hr_ucontext(context));
oulijun9a443532016-07-21 19:06:38 +0800450}
451
452static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
453 struct ib_port_immutable *immutable)
454{
455 struct ib_port_attr attr;
456 int ret;
457
Or Gerlitzc4550c62017-01-24 13:02:39 +0200458 ret = ib_query_port(ib_dev, port_num, &attr);
oulijun9a443532016-07-21 19:06:38 +0800459 if (ret)
460 return ret;
461
462 immutable->pkey_tbl_len = attr.pkey_tbl_len;
463 immutable->gid_tbl_len = attr.gid_tbl_len;
464
oulijun9a443532016-07-21 19:06:38 +0800465 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
Wei Hu(Xavier)023c1472017-10-26 17:10:24 +0800466 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
467 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
468 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
oulijun9a443532016-07-21 19:06:38 +0800469
470 return 0;
471}
472
Wei Hu(Xavier)fedc3ab2018-05-28 19:39:27 +0800473static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
474{
475 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
476 struct hns_roce_vma_data *vma_data, *n;
477 struct vm_area_struct *vma;
Wei Hu(Xavier)fedc3ab2018-05-28 19:39:27 +0800478
479 mutex_lock(&context->vma_list_mutex);
480 list_for_each_entry_safe(vma_data, n, &context->vma_list, list) {
481 vma = vma_data->vma;
Doug Ledford008fba42018-06-01 11:19:19 -0400482 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
Wei Hu(Xavier)fedc3ab2018-05-28 19:39:27 +0800483
484 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
485 vma->vm_ops = NULL;
486 list_del(&vma_data->list);
487 kfree(vma_data);
488 }
489 mutex_unlock(&context->vma_list_mutex);
490}
491
oulijun9a443532016-07-21 19:06:38 +0800492static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
493{
494 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
495
Wei Hu(Xavier)cb7a94c2018-05-28 19:39:24 +0800496 hr_dev->active = false;
oulijun9a443532016-07-21 19:06:38 +0800497 unregister_netdevice_notifier(&iboe->nb);
498 ib_unregister_device(&hr_dev->ib_dev);
499}
500
501static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
502{
503 int ret;
504 struct hns_roce_ib_iboe *iboe = NULL;
505 struct ib_device *ib_dev = NULL;
Wei Hu(Xavier)13ca9702017-08-30 17:23:02 +0800506 struct device *dev = hr_dev->dev;
oulijun9a443532016-07-21 19:06:38 +0800507
508 iboe = &hr_dev->iboe;
Lijun Ou49fdf6b2016-09-20 17:07:02 +0100509 spin_lock_init(&iboe->lock);
oulijun9a443532016-07-21 19:06:38 +0800510
511 ib_dev = &hr_dev->ib_dev;
Lijun Ou3b5184b2016-11-29 23:10:30 +0000512 strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
oulijun9a443532016-07-21 19:06:38 +0800513
514 ib_dev->owner = THIS_MODULE;
515 ib_dev->node_type = RDMA_NODE_IB_CA;
Bart Van Asschefecd02e2017-01-20 13:04:18 -0800516 ib_dev->dev.parent = dev;
oulijun9a443532016-07-21 19:06:38 +0800517
518 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
519 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
520 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
521 ib_dev->uverbs_abi_ver = 1;
522 ib_dev->uverbs_cmd_mask =
523 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
524 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
525 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
526 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
527 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
528 (1ULL << IB_USER_VERBS_CMD_REG_MR) |
529 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
530 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
531 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
532 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
533 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
534 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
535 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
536 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
537
538 /* HCA||device||port */
539 ib_dev->modify_device = hns_roce_modify_device;
540 ib_dev->query_device = hns_roce_query_device;
541 ib_dev->query_port = hns_roce_query_port;
542 ib_dev->modify_port = hns_roce_modify_port;
543 ib_dev->get_link_layer = hns_roce_get_link_layer;
Lijun Ou2eefca22016-09-15 23:48:06 +0100544 ib_dev->get_netdev = hns_roce_get_netdev;
Shaobo Xu82547462016-11-23 19:41:08 +0000545 ib_dev->add_gid = hns_roce_add_gid;
546 ib_dev->del_gid = hns_roce_del_gid;
oulijun9a443532016-07-21 19:06:38 +0800547 ib_dev->query_pkey = hns_roce_query_pkey;
548 ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
549 ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
550 ib_dev->mmap = hns_roce_mmap;
551
552 /* PD */
553 ib_dev->alloc_pd = hns_roce_alloc_pd;
554 ib_dev->dealloc_pd = hns_roce_dealloc_pd;
555
556 /* AH */
557 ib_dev->create_ah = hns_roce_create_ah;
558 ib_dev->query_ah = hns_roce_query_ah;
559 ib_dev->destroy_ah = hns_roce_destroy_ah;
560
561 /* QP */
562 ib_dev->create_qp = hns_roce_create_qp;
563 ib_dev->modify_qp = hns_roce_modify_qp;
564 ib_dev->query_qp = hr_dev->hw->query_qp;
565 ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
566 ib_dev->post_send = hr_dev->hw->post_send;
567 ib_dev->post_recv = hr_dev->hw->post_recv;
568
569 /* CQ */
570 ib_dev->create_cq = hns_roce_ib_create_cq;
oulijunb1562692017-10-19 11:52:40 +0800571 ib_dev->modify_cq = hr_dev->hw->modify_cq;
oulijun9a443532016-07-21 19:06:38 +0800572 ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
573 ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
574 ib_dev->poll_cq = hr_dev->hw->poll_cq;
575
576 /* MR */
577 ib_dev->get_dma_mr = hns_roce_get_dma_mr;
578 ib_dev->reg_user_mr = hns_roce_reg_user_mr;
579 ib_dev->dereg_mr = hns_roce_dereg_mr;
Wei Hu(Xavier)a2c80b72017-10-26 17:10:23 +0800580 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
581 ib_dev->rereg_user_mr = hns_roce_rereg_user_mr;
582 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
583 }
oulijun9a443532016-07-21 19:06:38 +0800584
585 /* OTHERS */
586 ib_dev->get_port_immutable = hns_roce_port_immutable;
Wei Hu(Xavier)fedc3ab2018-05-28 19:39:27 +0800587 ib_dev->disassociate_ucontext = hns_roce_disassociate_ucontext;
oulijun9a443532016-07-21 19:06:38 +0800588
Matan Barak0ede73b2018-03-19 15:02:34 +0200589 ib_dev->driver_id = RDMA_DRIVER_HNS;
oulijun9a443532016-07-21 19:06:38 +0800590 ret = ib_register_device(ib_dev, NULL);
591 if (ret) {
592 dev_err(dev, "ib_register_device failed!\n");
593 return ret;
594 }
595
Shaobo Xu82547462016-11-23 19:41:08 +0000596 ret = hns_roce_setup_mtu_mac(hr_dev);
oulijun9a443532016-07-21 19:06:38 +0800597 if (ret) {
Shaobo Xu82547462016-11-23 19:41:08 +0000598 dev_err(dev, "setup_mtu_mac failed!\n");
599 goto error_failed_setup_mtu_mac;
oulijun9a443532016-07-21 19:06:38 +0800600 }
601
oulijun9a443532016-07-21 19:06:38 +0800602 iboe->nb.notifier_call = hns_roce_netdev_event;
603 ret = register_netdevice_notifier(&iboe->nb);
604 if (ret) {
605 dev_err(dev, "register_netdevice_notifier failed!\n");
Shaobo Xu82547462016-11-23 19:41:08 +0000606 goto error_failed_setup_mtu_mac;
oulijun9a443532016-07-21 19:06:38 +0800607 }
608
Wei Hu(Xavier)cb7a94c2018-05-28 19:39:24 +0800609 hr_dev->active = true;
oulijun9a443532016-07-21 19:06:38 +0800610 return 0;
611
Shaobo Xu82547462016-11-23 19:41:08 +0000612error_failed_setup_mtu_mac:
oulijun9a443532016-07-21 19:06:38 +0800613 ib_unregister_device(ib_dev);
614
615 return ret;
616}
617
oulijun9a443532016-07-21 19:06:38 +0800618static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
619{
620 int ret;
Wei Hu(Xavier)13ca9702017-08-30 17:23:02 +0800621 struct device *dev = hr_dev->dev;
oulijun9a443532016-07-21 19:06:38 +0800622
623 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
624 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
625 hr_dev->caps.num_mtt_segs, 1);
626 if (ret) {
627 dev_err(dev, "Failed to init MTT context memory, aborting.\n");
628 return ret;
629 }
630
Shaobo Xu9766edc2017-08-30 17:23:09 +0800631 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
632 ret = hns_roce_init_hem_table(hr_dev,
633 &hr_dev->mr_table.mtt_cqe_table,
634 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
635 hr_dev->caps.num_cqe_segs, 1);
636 if (ret) {
637 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
638 goto err_unmap_cqe;
639 }
640 }
641
oulijun9a443532016-07-21 19:06:38 +0800642 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
643 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
644 hr_dev->caps.num_mtpts, 1);
645 if (ret) {
646 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
647 goto err_unmap_mtt;
648 }
649
650 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
651 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
652 hr_dev->caps.num_qps, 1);
653 if (ret) {
654 dev_err(dev, "Failed to init QP context memory, aborting.\n");
655 goto err_unmap_dmpt;
656 }
657
658 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
659 HEM_TYPE_IRRL,
660 hr_dev->caps.irrl_entry_sz *
661 hr_dev->caps.max_qp_init_rdma,
662 hr_dev->caps.num_qps, 1);
663 if (ret) {
664 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
665 goto err_unmap_qp;
666 }
667
oulijune92f2c12017-11-10 16:55:44 +0800668 if (hr_dev->caps.trrl_entry_sz) {
669 ret = hns_roce_init_hem_table(hr_dev,
670 &hr_dev->qp_table.trrl_table,
671 HEM_TYPE_TRRL,
672 hr_dev->caps.trrl_entry_sz *
673 hr_dev->caps.max_qp_dest_rdma,
674 hr_dev->caps.num_qps, 1);
675 if (ret) {
676 dev_err(dev,
677 "Failed to init trrl_table memory, aborting.\n");
678 goto err_unmap_irrl;
679 }
680 }
681
oulijun9a443532016-07-21 19:06:38 +0800682 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
683 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
684 hr_dev->caps.num_cqs, 1);
685 if (ret) {
686 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
oulijune92f2c12017-11-10 16:55:44 +0800687 goto err_unmap_trrl;
oulijun9a443532016-07-21 19:06:38 +0800688 }
689
690 return 0;
691
oulijune92f2c12017-11-10 16:55:44 +0800692err_unmap_trrl:
693 if (hr_dev->caps.trrl_entry_sz)
694 hns_roce_cleanup_hem_table(hr_dev,
695 &hr_dev->qp_table.trrl_table);
696
oulijun9a443532016-07-21 19:06:38 +0800697err_unmap_irrl:
698 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
699
700err_unmap_qp:
701 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
702
703err_unmap_dmpt:
704 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
705
706err_unmap_mtt:
Shaobo Xu9766edc2017-08-30 17:23:09 +0800707 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
708 hns_roce_cleanup_hem_table(hr_dev,
709 &hr_dev->mr_table.mtt_cqe_table);
710
711err_unmap_cqe:
712 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
oulijun9a443532016-07-21 19:06:38 +0800713
714 return ret;
715}
716
717/**
Salile84e40be2016-11-23 19:41:09 +0000718 * hns_roce_setup_hca - setup host channel adapter
719 * @hr_dev: pointer to hns roce device
720 * Return : int
721 */
oulijun9a443532016-07-21 19:06:38 +0800722static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
723{
724 int ret;
Wei Hu(Xavier)13ca9702017-08-30 17:23:02 +0800725 struct device *dev = hr_dev->dev;
oulijun9a443532016-07-21 19:06:38 +0800726
727 spin_lock_init(&hr_dev->sm_lock);
oulijun9a443532016-07-21 19:06:38 +0800728 spin_lock_init(&hr_dev->bt_cmd_lock);
729
Yixian Liu472bc0f2018-03-09 18:36:31 +0800730 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
731 INIT_LIST_HEAD(&hr_dev->pgdir_list);
732 mutex_init(&hr_dev->pgdir_mutex);
733 }
734
oulijun9a443532016-07-21 19:06:38 +0800735 ret = hns_roce_init_uar_table(hr_dev);
736 if (ret) {
737 dev_err(dev, "Failed to initialize uar table. aborting\n");
738 return ret;
739 }
740
741 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
742 if (ret) {
743 dev_err(dev, "Failed to allocate priv_uar.\n");
744 goto err_uar_table_free;
745 }
746
747 ret = hns_roce_init_pd_table(hr_dev);
748 if (ret) {
749 dev_err(dev, "Failed to init protected domain table.\n");
750 goto err_uar_alloc_free;
751 }
752
753 ret = hns_roce_init_mr_table(hr_dev);
754 if (ret) {
755 dev_err(dev, "Failed to init memory region table.\n");
756 goto err_pd_table_free;
757 }
758
759 ret = hns_roce_init_cq_table(hr_dev);
760 if (ret) {
761 dev_err(dev, "Failed to init completion queue table.\n");
762 goto err_mr_table_free;
763 }
764
765 ret = hns_roce_init_qp_table(hr_dev);
766 if (ret) {
767 dev_err(dev, "Failed to init queue pair table.\n");
768 goto err_cq_table_free;
769 }
770
771 return 0;
772
773err_cq_table_free:
774 hns_roce_cleanup_cq_table(hr_dev);
775
776err_mr_table_free:
777 hns_roce_cleanup_mr_table(hr_dev);
778
779err_pd_table_free:
780 hns_roce_cleanup_pd_table(hr_dev);
781
782err_uar_alloc_free:
783 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
784
785err_uar_table_free:
786 hns_roce_cleanup_uar_table(hr_dev);
787 return ret;
788}
789
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800790int hns_roce_init(struct hns_roce_dev *hr_dev)
oulijun9a443532016-07-21 19:06:38 +0800791{
792 int ret;
Wei Hu(Xavier)13ca9702017-08-30 17:23:02 +0800793 struct device *dev = hr_dev->dev;
oulijun9a443532016-07-21 19:06:38 +0800794
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800795 if (hr_dev->hw->reset) {
796 ret = hr_dev->hw->reset(hr_dev, true);
797 if (ret) {
798 dev_err(dev, "Reset RoCE engine failed!\n");
799 return ret;
800 }
oulijun9a443532016-07-21 19:06:38 +0800801 }
Wei Hu(Xavier)cb7a94c2018-05-28 19:39:24 +0800802 hr_dev->is_reset = false;
oulijun9a443532016-07-21 19:06:38 +0800803
Wei Hu(Xavier)a04ff732017-08-30 17:23:03 +0800804 if (hr_dev->hw->cmq_init) {
805 ret = hr_dev->hw->cmq_init(hr_dev);
806 if (ret) {
807 dev_err(dev, "Init RoCE Command Queue failed!\n");
808 goto error_failed_cmq_init;
809 }
810 }
811
Wei Hu(Xavier)cfc85f32017-08-30 17:23:04 +0800812 ret = hr_dev->hw->hw_profile(hr_dev);
813 if (ret) {
814 dev_err(dev, "Get RoCE engine profile failed!\n");
815 goto error_failed_cmd_init;
816 }
oulijun9a443532016-07-21 19:06:38 +0800817
818 ret = hns_roce_cmd_init(hr_dev);
819 if (ret) {
820 dev_err(dev, "cmd init failed!\n");
821 goto error_failed_cmd_init;
822 }
823
Yixian Liub16f8182017-11-14 17:26:16 +0800824 ret = hr_dev->hw->init_eq(hr_dev);
825 if (ret) {
826 dev_err(dev, "eq init failed!\n");
827 goto error_failed_eq_table;
oulijun9a443532016-07-21 19:06:38 +0800828 }
829
830 if (hr_dev->cmd_mod) {
831 ret = hns_roce_cmd_use_events(hr_dev);
832 if (ret) {
833 dev_err(dev, "Switch to event-driven cmd failed!\n");
834 goto error_failed_use_event;
835 }
836 }
837
838 ret = hns_roce_init_hem(hr_dev);
839 if (ret) {
840 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
841 goto error_failed_init_hem;
842 }
843
844 ret = hns_roce_setup_hca(hr_dev);
845 if (ret) {
846 dev_err(dev, "setup hca failed!\n");
847 goto error_failed_setup_hca;
848 }
849
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800850 if (hr_dev->hw->hw_init) {
851 ret = hr_dev->hw->hw_init(hr_dev);
852 if (ret) {
853 dev_err(dev, "hw_init failed!\n");
854 goto error_failed_engine_init;
855 }
oulijun9a443532016-07-21 19:06:38 +0800856 }
857
858 ret = hns_roce_register_device(hr_dev);
859 if (ret)
860 goto error_failed_register_device;
861
862 return 0;
863
864error_failed_register_device:
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800865 if (hr_dev->hw->hw_exit)
866 hr_dev->hw->hw_exit(hr_dev);
oulijun9a443532016-07-21 19:06:38 +0800867
868error_failed_engine_init:
869 hns_roce_cleanup_bitmap(hr_dev);
870
871error_failed_setup_hca:
872 hns_roce_cleanup_hem(hr_dev);
873
874error_failed_init_hem:
875 if (hr_dev->cmd_mod)
876 hns_roce_cmd_use_polling(hr_dev);
877
878error_failed_use_event:
Yixian Liub16f8182017-11-14 17:26:16 +0800879 hr_dev->hw->cleanup_eq(hr_dev);
oulijun9a443532016-07-21 19:06:38 +0800880
881error_failed_eq_table:
882 hns_roce_cmd_cleanup(hr_dev);
883
884error_failed_cmd_init:
Wei Hu(Xavier)a04ff732017-08-30 17:23:03 +0800885 if (hr_dev->hw->cmq_exit)
886 hr_dev->hw->cmq_exit(hr_dev);
887
888error_failed_cmq_init:
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800889 if (hr_dev->hw->reset) {
890 ret = hr_dev->hw->reset(hr_dev, false);
891 if (ret)
892 dev_err(dev, "Dereset RoCE engine failed!\n");
893 }
oulijun9a443532016-07-21 19:06:38 +0800894
895 return ret;
896}
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800897EXPORT_SYMBOL_GPL(hns_roce_init);
oulijun9a443532016-07-21 19:06:38 +0800898
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800899void hns_roce_exit(struct hns_roce_dev *hr_dev)
oulijun9a443532016-07-21 19:06:38 +0800900{
oulijun9a443532016-07-21 19:06:38 +0800901 hns_roce_unregister_device(hr_dev);
Wei Hu(Xavier)cb7a94c2018-05-28 19:39:24 +0800902
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800903 if (hr_dev->hw->hw_exit)
904 hr_dev->hw->hw_exit(hr_dev);
oulijun9a443532016-07-21 19:06:38 +0800905 hns_roce_cleanup_bitmap(hr_dev);
906 hns_roce_cleanup_hem(hr_dev);
907
908 if (hr_dev->cmd_mod)
909 hns_roce_cmd_use_polling(hr_dev);
910
Yixian Liub16f8182017-11-14 17:26:16 +0800911 hr_dev->hw->cleanup_eq(hr_dev);
oulijun9a443532016-07-21 19:06:38 +0800912 hns_roce_cmd_cleanup(hr_dev);
Wei Hu(Xavier)a04ff732017-08-30 17:23:03 +0800913 if (hr_dev->hw->cmq_exit)
914 hr_dev->hw->cmq_exit(hr_dev);
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800915 if (hr_dev->hw->reset)
916 hr_dev->hw->reset(hr_dev, false);
oulijun9a443532016-07-21 19:06:38 +0800917}
Wei Hu(Xavier)08805fd2017-08-30 17:22:59 +0800918EXPORT_SYMBOL_GPL(hns_roce_exit);
oulijun9a443532016-07-21 19:06:38 +0800919
920MODULE_LICENSE("Dual BSD/GPL");
921MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
922MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
923MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
924MODULE_DESCRIPTION("HNS RoCE Driver");