blob: a3576dbefa0faf1277c58e5b4bd0d37d05f33553 [file] [log] [blame]
Alex Deucher97b2e202015-04-20 16:51:00 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
Christian Königa9f87f62017-03-30 14:03:59 +020035#include <linux/rbtree.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040036#include <linux/hashtable.h>
Chris Wilsonf54d1862016-10-25 13:00:45 +010037#include <linux/dma-fence.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040038
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
Chunming Zhoud03846a2015-07-28 14:20:03 -040045#include <drm/drmP.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040046#include <drm/drm_gem.h>
Chunming Zhou7e5a5472015-04-24 17:37:30 +080047#include <drm/amdgpu_drm.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040048
yanyang15fc3aee2015-05-22 14:39:35 -040049#include "amd_shared.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040050#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
Flora Cuic632d792016-08-02 11:32:41 +080054#include "amdgpu_ttm.h"
Huang Rui0e5ca0d2017-03-03 18:37:23 -050055#include "amdgpu_psp.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040056#include "amdgpu_gds.h"
Christian König56113502016-09-28 12:36:44 +020057#include "amdgpu_sync.h"
Christian König78023012016-09-28 15:33:18 +020058#include "amdgpu_ring.h"
Christian König073440d2016-09-28 15:41:50 +020059#include "amdgpu_vm.h"
Alex Deucher1f7371b2015-12-02 17:46:21 -050060#include "amd_powerplay.h"
Alex Deuchercf0978812016-10-07 11:40:09 -040061#include "amdgpu_dpm.h"
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -040062#include "amdgpu_acp.h"
Leo Liu4df654d2017-01-02 10:07:33 -050063#include "amdgpu_uvd.h"
Leo Liu5e568172017-01-10 11:02:58 -050064#include "amdgpu_vce.h"
Leo Liu95aa13f2017-05-11 16:27:33 -040065#include "amdgpu_vcn.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040066
Alex Deucherb80d8472015-08-16 22:55:02 -040067#include "gpu_scheduler.h"
Monk Liuceeb50e2016-09-19 12:13:58 +080068#include "amdgpu_virt.h"
Alex Deucherb80d8472015-08-16 22:55:02 -040069
Alex Deucher97b2e202015-04-20 16:51:00 -040070/*
71 * Modules parameters.
72 */
73extern int amdgpu_modeset;
74extern int amdgpu_vram_limit;
75extern int amdgpu_gart_size;
Marek Olšák95844d22016-08-17 23:49:27 +020076extern int amdgpu_moverate;
Alex Deucher97b2e202015-04-20 16:51:00 -040077extern int amdgpu_benchmarking;
78extern int amdgpu_testing;
79extern int amdgpu_audio;
80extern int amdgpu_disp_priority;
81extern int amdgpu_hw_i2c;
82extern int amdgpu_pcie_gen2;
83extern int amdgpu_msi;
84extern int amdgpu_lockup_timeout;
85extern int amdgpu_dpm;
Huang Ruie635ee02016-11-01 15:35:38 +080086extern int amdgpu_fw_load_type;
Alex Deucher97b2e202015-04-20 16:51:00 -040087extern int amdgpu_aspm;
88extern int amdgpu_runtime_pm;
Alex Deucher97b2e202015-04-20 16:51:00 -040089extern unsigned amdgpu_ip_block_mask;
90extern int amdgpu_bapm;
91extern int amdgpu_deep_color;
92extern int amdgpu_vm_size;
93extern int amdgpu_vm_block_size;
Christian Königd9c13152015-09-28 12:31:26 +020094extern int amdgpu_vm_fault_stop;
Christian Königb495bd32015-09-10 14:00:35 +020095extern int amdgpu_vm_debug;
Jammy Zhou1333f722015-07-30 16:36:58 +080096extern int amdgpu_sched_jobs;
Jammy Zhou4afcb302015-07-30 16:44:05 +080097extern int amdgpu_sched_hw_submission;
Rex Zhu3ca67302016-11-02 13:38:37 +080098extern int amdgpu_no_evict;
99extern int amdgpu_direct_gma_size;
Alex Deuchercd474ba2016-02-04 10:21:23 -0500100extern unsigned amdgpu_pcie_gen_cap;
101extern unsigned amdgpu_pcie_lane_cap;
Nicolai Hähnle395d1fb2016-06-02 12:32:07 +0200102extern unsigned amdgpu_cg_mask;
103extern unsigned amdgpu_pg_mask;
Nicolai Hähnle6f8941a2016-06-17 19:31:33 +0200104extern char *amdgpu_disable_cu;
Emily Deng9accf2f2016-08-10 16:01:25 +0800105extern char *amdgpu_virtual_display;
Rex Zhu5141e9d2016-09-06 16:34:37 +0800106extern unsigned amdgpu_pp_feature_mask;
Christian König6a7f76e2016-08-24 15:51:49 +0200107extern int amdgpu_vram_page_split;
Alex Deucherbce23e02017-03-28 12:52:08 -0400108extern int amdgpu_ngg;
109extern int amdgpu_prim_buf_per_se;
110extern int amdgpu_pos_buf_per_se;
111extern int amdgpu_cntl_sb_buf_per_se;
112extern int amdgpu_param_buf_per_se;
Monk Liu65781c72017-05-11 13:36:44 +0800113extern int amdgpu_job_hang_limit;
Hawking Zhange8835e02017-05-26 14:40:36 +0800114extern int amdgpu_lbpw;
Alex Deucher97b2e202015-04-20 16:51:00 -0400115
Chunming Zhou55ed8caf2017-04-21 16:40:00 +0800116#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
Chunming Zhou4b559c92015-07-21 15:53:04 +0800117#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
Alex Deucher97b2e202015-04-20 16:51:00 -0400118#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
119#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
120/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
121#define AMDGPU_IB_POOL_SIZE 16
122#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
123#define AMDGPUFB_CONN_LIMIT 4
Alex Deuchera5bde2f2016-09-23 16:23:41 -0400124#define AMDGPU_BIOS_NUM_SCRATCH 16
Alex Deucher97b2e202015-04-20 16:51:00 -0400125
Jammy Zhou36f523a2015-09-01 12:54:27 +0800126/* max number of IP instances */
127#define AMDGPU_MAX_SDMA_INSTANCES 2
128
Alex Deucher97b2e202015-04-20 16:51:00 -0400129/* hard reset data */
130#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
131
132/* reset flags */
133#define AMDGPU_RESET_GFX (1 << 0)
134#define AMDGPU_RESET_COMPUTE (1 << 1)
135#define AMDGPU_RESET_DMA (1 << 2)
136#define AMDGPU_RESET_CP (1 << 3)
137#define AMDGPU_RESET_GRBM (1 << 4)
138#define AMDGPU_RESET_DMA1 (1 << 5)
139#define AMDGPU_RESET_RLC (1 << 6)
140#define AMDGPU_RESET_SEM (1 << 7)
141#define AMDGPU_RESET_IH (1 << 8)
142#define AMDGPU_RESET_VMC (1 << 9)
143#define AMDGPU_RESET_MC (1 << 10)
144#define AMDGPU_RESET_DISPLAY (1 << 11)
145#define AMDGPU_RESET_UVD (1 << 12)
146#define AMDGPU_RESET_VCE (1 << 13)
147#define AMDGPU_RESET_VCE1 (1 << 14)
148
Alex Deucher97b2e202015-04-20 16:51:00 -0400149/* GFX current status */
150#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
151#define AMDGPU_GFX_SAFE_MODE 0x00000001L
152#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
153#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
154#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
155
156/* max cursor sizes (in pixels) */
157#define CIK_CURSOR_WIDTH 128
158#define CIK_CURSOR_HEIGHT 128
159
160struct amdgpu_device;
Alex Deucher97b2e202015-04-20 16:51:00 -0400161struct amdgpu_ib;
Alex Deucher97b2e202015-04-20 16:51:00 -0400162struct amdgpu_cs_parser;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800163struct amdgpu_job;
Alex Deucher97b2e202015-04-20 16:51:00 -0400164struct amdgpu_irq_src;
Alex Deucher0b492a42015-08-16 22:48:26 -0400165struct amdgpu_fpriv;
Alex Deucher97b2e202015-04-20 16:51:00 -0400166
167enum amdgpu_cp_irq {
168 AMDGPU_CP_IRQ_GFX_EOP = 0,
169 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
170 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
171 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
172 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
173 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
174 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
175 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
176 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
177
178 AMDGPU_CP_IRQ_LAST
179};
180
181enum amdgpu_sdma_irq {
182 AMDGPU_SDMA_IRQ_TRAP0 = 0,
183 AMDGPU_SDMA_IRQ_TRAP1,
184
185 AMDGPU_SDMA_IRQ_LAST
186};
187
188enum amdgpu_thermal_irq {
189 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
190 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
191
192 AMDGPU_THERMAL_IRQ_LAST
193};
194
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800195enum amdgpu_kiq_irq {
196 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
197 AMDGPU_CP_KIQ_IRQ_LAST
198};
199
Alex Deucher97b2e202015-04-20 16:51:00 -0400200int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400201 enum amd_ip_block_type block_type,
202 enum amd_clockgating_state state);
Alex Deucher97b2e202015-04-20 16:51:00 -0400203int amdgpu_set_powergating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400204 enum amd_ip_block_type block_type,
205 enum amd_powergating_state state);
Huang Rui6cb2d4e2017-01-05 18:44:41 +0800206void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
Alex Deucher5dbbb602016-06-23 11:41:04 -0400207int amdgpu_wait_for_idle(struct amdgpu_device *adev,
208 enum amd_ip_block_type block_type);
209bool amdgpu_is_idle(struct amdgpu_device *adev,
210 enum amd_ip_block_type block_type);
Alex Deucher97b2e202015-04-20 16:51:00 -0400211
Alex Deuchera1255102016-10-13 17:41:13 -0400212#define AMDGPU_MAX_IP_NUM 16
213
214struct amdgpu_ip_block_status {
215 bool valid;
216 bool sw;
217 bool hw;
218 bool late_initialized;
219 bool hang;
220};
221
Alex Deucher97b2e202015-04-20 16:51:00 -0400222struct amdgpu_ip_block_version {
Alex Deuchera1255102016-10-13 17:41:13 -0400223 const enum amd_ip_block_type type;
224 const u32 major;
225 const u32 minor;
226 const u32 rev;
yanyang15fc3aee2015-05-22 14:39:35 -0400227 const struct amd_ip_funcs *funcs;
Alex Deucher97b2e202015-04-20 16:51:00 -0400228};
229
Alex Deuchera1255102016-10-13 17:41:13 -0400230struct amdgpu_ip_block {
231 struct amdgpu_ip_block_status status;
232 const struct amdgpu_ip_block_version *version;
233};
234
Alex Deucher97b2e202015-04-20 16:51:00 -0400235int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400236 enum amd_ip_block_type type,
Alex Deucher97b2e202015-04-20 16:51:00 -0400237 u32 major, u32 minor);
238
Alex Deuchera1255102016-10-13 17:41:13 -0400239struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
240 enum amd_ip_block_type type);
241
242int amdgpu_ip_block_add(struct amdgpu_device *adev,
243 const struct amdgpu_ip_block_version *ip_block_version);
Alex Deucher97b2e202015-04-20 16:51:00 -0400244
245/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
246struct amdgpu_buffer_funcs {
247 /* maximum bytes in a single operation */
248 uint32_t copy_max_bytes;
249
250 /* number of dw to reserve per operation */
251 unsigned copy_num_dw;
252
253 /* used for buffer migration */
Chunming Zhouc7ae72c2015-08-25 17:23:45 +0800254 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400255 /* src addr in bytes */
256 uint64_t src_offset,
257 /* dst addr in bytes */
258 uint64_t dst_offset,
259 /* number of byte to transfer */
260 uint32_t byte_count);
261
262 /* maximum bytes in a single operation */
263 uint32_t fill_max_bytes;
264
265 /* number of dw to reserve per operation */
266 unsigned fill_num_dw;
267
268 /* used for buffer clearing */
Chunming Zhou6e7a3842015-08-27 13:46:09 +0800269 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400270 /* value to write to memory */
271 uint32_t src_data,
272 /* dst addr in bytes */
273 uint64_t dst_offset,
274 /* number of byte to fill */
275 uint32_t byte_count);
276};
277
278/* provided by hw blocks that can write ptes, e.g., sdma */
279struct amdgpu_vm_pte_funcs {
280 /* copy pte entries from GART */
281 void (*copy_pte)(struct amdgpu_ib *ib,
282 uint64_t pe, uint64_t src,
283 unsigned count);
284 /* write pte one entry at a time with addr mapping */
Christian Königde9ea7b2016-08-12 11:33:30 +0200285 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
286 uint64_t value, unsigned count,
287 uint32_t incr);
Alex Deucher97b2e202015-04-20 16:51:00 -0400288 /* for linear pte/pde updates without addr mapping */
289 void (*set_pte_pde)(struct amdgpu_ib *ib,
290 uint64_t pe,
291 uint64_t addr, unsigned count,
Chunming Zhou6b777602016-09-21 16:19:19 +0800292 uint32_t incr, uint64_t flags);
Alex Deucher97b2e202015-04-20 16:51:00 -0400293};
294
295/* provided by the gmc block */
296struct amdgpu_gart_funcs {
297 /* flush the vm tlb via mmio */
298 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
299 uint32_t vmid);
300 /* write pte/pde updates using the cpu */
301 int (*set_pte_pde)(struct amdgpu_device *adev,
302 void *cpu_pt_addr, /* cpu addr of page table */
303 uint32_t gpu_page_idx, /* pte/pde to update */
304 uint64_t addr, /* addr to write into pte/pde */
Chunming Zhou6b777602016-09-21 16:19:19 +0800305 uint64_t flags); /* access flags */
Christian König284710f2017-01-30 11:09:31 +0100306 /* enable/disable PRT support */
307 void (*set_prt)(struct amdgpu_device *adev, bool enable);
Alex Xie54635452017-02-14 12:22:57 -0500308 /* set pte flags based per asic */
309 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
310 uint32_t flags);
Alex Xiee60f8db2017-03-09 11:36:26 -0500311 /* adjust mc addr in fb for APU case */
312 u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
Christian König03f89fe2017-04-04 16:07:45 +0200313 uint32_t (*get_invalidate_req)(unsigned int vm_id);
Alex Xiee60f8db2017-03-09 11:36:26 -0500314};
315
Alex Deucher97b2e202015-04-20 16:51:00 -0400316/* provided by the ih block */
317struct amdgpu_ih_funcs {
318 /* ring read/write ptr handling, called from interrupt context */
319 u32 (*get_wptr)(struct amdgpu_device *adev);
320 void (*decode_iv)(struct amdgpu_device *adev,
321 struct amdgpu_iv_entry *entry);
322 void (*set_rptr)(struct amdgpu_device *adev);
323};
324
Alex Deucher97b2e202015-04-20 16:51:00 -0400325/*
326 * BIOS.
327 */
328bool amdgpu_get_bios(struct amdgpu_device *adev);
329bool amdgpu_read_bios(struct amdgpu_device *adev);
330
331/*
332 * Dummy page
333 */
334struct amdgpu_dummy_page {
335 struct page *page;
336 dma_addr_t addr;
337};
338int amdgpu_dummy_page_init(struct amdgpu_device *adev);
339void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
340
341
342/*
343 * Clocks
344 */
345
346#define AMDGPU_MAX_PPLL 3
347
348struct amdgpu_clock {
349 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
350 struct amdgpu_pll spll;
351 struct amdgpu_pll mpll;
352 /* 10 Khz units */
353 uint32_t default_mclk;
354 uint32_t default_sclk;
355 uint32_t default_dispclk;
356 uint32_t current_dispclk;
357 uint32_t dp_extclk;
358 uint32_t max_pixel_clock;
359};
360
361/*
Flora Cuic632d792016-08-02 11:32:41 +0800362 * BO.
Alex Deucher97b2e202015-04-20 16:51:00 -0400363 */
Alex Deucher97b2e202015-04-20 16:51:00 -0400364struct amdgpu_bo_list_entry {
365 struct amdgpu_bo *robj;
366 struct ttm_validate_buffer tv;
367 struct amdgpu_bo_va *bo_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400368 uint32_t priority;
Christian König2f568db2016-02-23 12:36:59 +0100369 struct page **user_pages;
370 int user_invalidated;
Alex Deucher97b2e202015-04-20 16:51:00 -0400371};
372
373struct amdgpu_bo_va_mapping {
374 struct list_head list;
Christian Königa9f87f62017-03-30 14:03:59 +0200375 struct rb_node rb;
376 uint64_t start;
377 uint64_t last;
378 uint64_t __subtree_last;
Alex Deucher97b2e202015-04-20 16:51:00 -0400379 uint64_t offset;
Christian König268c3002017-01-18 14:49:43 +0100380 uint64_t flags;
Alex Deucher97b2e202015-04-20 16:51:00 -0400381};
382
383/* bo virtual addresses in a specific vm */
384struct amdgpu_bo_va {
385 /* protected by bo being reserved */
386 struct list_head bo_list;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100387 struct dma_fence *last_pt_update;
Alex Deucher97b2e202015-04-20 16:51:00 -0400388 unsigned ref_count;
389
Christian König7fc11952015-07-30 11:53:42 +0200390 /* protected by vm mutex and spinlock */
Alex Deucher97b2e202015-04-20 16:51:00 -0400391 struct list_head vm_status;
392
Christian König7fc11952015-07-30 11:53:42 +0200393 /* mappings for this bo_va */
394 struct list_head invalids;
395 struct list_head valids;
396
Alex Deucher97b2e202015-04-20 16:51:00 -0400397 /* constant after initialization */
398 struct amdgpu_vm *vm;
399 struct amdgpu_bo *bo;
400};
401
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800402#define AMDGPU_GEM_DOMAIN_MAX 0x3
403
Alex Deucher97b2e202015-04-20 16:51:00 -0400404struct amdgpu_bo {
Alex Deucher97b2e202015-04-20 16:51:00 -0400405 /* Protected by tbo.reserved */
Christian König1ea863f2015-12-18 22:13:12 +0100406 u32 prefered_domains;
407 u32 allowed_domains;
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800408 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
Alex Deucher97b2e202015-04-20 16:51:00 -0400409 struct ttm_placement placement;
410 struct ttm_buffer_object tbo;
411 struct ttm_bo_kmap_obj kmap;
412 u64 flags;
413 unsigned pin_count;
414 void *kptr;
415 u64 tiling_flags;
416 u64 metadata_flags;
417 void *metadata;
418 u32 metadata_size;
Mario Kleiner8e94a462016-11-09 02:25:15 +0100419 unsigned prime_shared_count;
Alex Deucher97b2e202015-04-20 16:51:00 -0400420 /* list of all virtual address to which this bo
421 * is associated to
422 */
423 struct list_head va;
424 /* Constant after initialization */
Alex Deucher97b2e202015-04-20 16:51:00 -0400425 struct drm_gem_object gem_base;
Christian König82b9c552015-11-27 16:49:00 +0100426 struct amdgpu_bo *parent;
Chunming Zhoue7893c42016-07-26 14:13:21 +0800427 struct amdgpu_bo *shadow;
Alex Deucher97b2e202015-04-20 16:51:00 -0400428
429 struct ttm_bo_kmap_obj dma_buf_vmap;
Alex Deucher97b2e202015-04-20 16:51:00 -0400430 struct amdgpu_mn *mn;
431 struct list_head mn_list;
Chunming Zhou0c4e7fa2016-08-17 11:41:30 +0800432 struct list_head shadow_list;
Alex Deucher97b2e202015-04-20 16:51:00 -0400433};
434#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
435
436void amdgpu_gem_object_free(struct drm_gem_object *obj);
437int amdgpu_gem_object_open(struct drm_gem_object *obj,
438 struct drm_file *file_priv);
439void amdgpu_gem_object_close(struct drm_gem_object *obj,
440 struct drm_file *file_priv);
441unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
442struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
Christian König4d9c5142016-05-03 18:46:19 +0200443struct drm_gem_object *
444amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
445 struct dma_buf_attachment *attach,
446 struct sg_table *sg);
Alex Deucher97b2e202015-04-20 16:51:00 -0400447struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
448 struct drm_gem_object *gobj,
449 int flags);
450int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
451void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
452struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
453void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
454void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
455int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
456
457/* sub-allocation manager, it has to be protected by another lock.
458 * By conception this is an helper for other part of the driver
459 * like the indirect buffer or semaphore, which both have their
460 * locking.
461 *
462 * Principe is simple, we keep a list of sub allocation in offset
463 * order (first entry has offset == 0, last entry has the highest
464 * offset).
465 *
466 * When allocating new object we first check if there is room at
467 * the end total_size - (last_object_offset + last_object_size) >=
468 * alloc_size. If so we allocate new object there.
469 *
470 * When there is not enough room at the end, we start waiting for
471 * each sub object until we reach object_offset+object_size >=
472 * alloc_size, this object then become the sub object we return.
473 *
474 * Alignment can't be bigger than page size.
475 *
476 * Hole are not considered for allocation to keep things simple.
477 * Assumption is that there won't be hole (all object on same
478 * alignment).
479 */
Christian König6ba60b82016-03-11 14:50:08 +0100480
481#define AMDGPU_SA_NUM_FENCE_LISTS 32
482
Alex Deucher97b2e202015-04-20 16:51:00 -0400483struct amdgpu_sa_manager {
484 wait_queue_head_t wq;
485 struct amdgpu_bo *bo;
486 struct list_head *hole;
Christian König6ba60b82016-03-11 14:50:08 +0100487 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
Alex Deucher97b2e202015-04-20 16:51:00 -0400488 struct list_head olist;
489 unsigned size;
490 uint64_t gpu_addr;
491 void *cpu_ptr;
492 uint32_t domain;
493 uint32_t align;
494};
495
Alex Deucher97b2e202015-04-20 16:51:00 -0400496/* sub-allocation buffer */
497struct amdgpu_sa_bo {
498 struct list_head olist;
499 struct list_head flist;
500 struct amdgpu_sa_manager *manager;
501 unsigned soffset;
502 unsigned eoffset;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100503 struct dma_fence *fence;
Alex Deucher97b2e202015-04-20 16:51:00 -0400504};
505
506/*
507 * GEM objects.
508 */
Christian König418aa0c2016-02-15 16:59:57 +0100509void amdgpu_gem_force_release(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400510int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
511 int alignment, u32 initial_domain,
512 u64 flags, bool kernel,
513 struct drm_gem_object **obj);
514
515int amdgpu_mode_dumb_create(struct drm_file *file_priv,
516 struct drm_device *dev,
517 struct drm_mode_create_dumb *args);
518int amdgpu_mode_dumb_mmap(struct drm_file *filp,
519 struct drm_device *dev,
520 uint32_t handle, uint64_t *offset_p);
Rex Zhud573de22016-05-12 13:27:28 +0800521int amdgpu_fence_slab_init(void);
522void amdgpu_fence_slab_fini(void);
Alex Deucher97b2e202015-04-20 16:51:00 -0400523
524/*
525 * GART structures, functions & helpers
526 */
527struct amdgpu_mc;
528
529#define AMDGPU_GPU_PAGE_SIZE 4096
530#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
531#define AMDGPU_GPU_PAGE_SHIFT 12
532#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
533
534struct amdgpu_gart {
535 dma_addr_t table_addr;
536 struct amdgpu_bo *robj;
537 void *ptr;
538 unsigned num_gpu_pages;
539 unsigned num_cpu_pages;
540 unsigned table_size;
Christian Königa1d29472016-03-30 14:42:57 +0200541#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
Alex Deucher97b2e202015-04-20 16:51:00 -0400542 struct page **pages;
Christian Königa1d29472016-03-30 14:42:57 +0200543#endif
Alex Deucher97b2e202015-04-20 16:51:00 -0400544 bool ready;
Alex Xie4b98e0c2017-02-14 12:31:36 -0500545
546 /* Asic default pte flags */
547 uint64_t gart_pte_flags;
548
Alex Deucher97b2e202015-04-20 16:51:00 -0400549 const struct amdgpu_gart_funcs *gart_funcs;
550};
551
552int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
553void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
554int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
555void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
556int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
557void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
558int amdgpu_gart_init(struct amdgpu_device *adev);
559void amdgpu_gart_fini(struct amdgpu_device *adev);
Roger.He738f64c2017-05-05 13:27:10 +0800560int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
Alex Deucher97b2e202015-04-20 16:51:00 -0400561 int pages);
Felix Kuehlingcab0b8d2016-08-12 19:25:21 -0400562int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
Alex Deucher97b2e202015-04-20 16:51:00 -0400563 int pages, struct page **pagelist,
Chunming Zhou6b777602016-09-21 16:19:19 +0800564 dma_addr_t *dma_addr, uint64_t flags);
Chunming Zhou2c0d7312016-08-30 16:36:25 +0800565int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400566
567/*
Alex Xiee60f8db2017-03-09 11:36:26 -0500568 * VMHUB structures, functions & helpers
569 */
570struct amdgpu_vmhub {
571 uint32_t ctx0_ptb_addr_lo32;
572 uint32_t ctx0_ptb_addr_hi32;
573 uint32_t vm_inv_eng0_req;
574 uint32_t vm_inv_eng0_ack;
575 uint32_t vm_context0_cntl;
576 uint32_t vm_l2_pro_fault_status;
577 uint32_t vm_l2_pro_fault_cntl;
Alex Xiee60f8db2017-03-09 11:36:26 -0500578};
579
580/*
Alex Deucher97b2e202015-04-20 16:51:00 -0400581 * GPU MC structures, functions & helpers
582 */
583struct amdgpu_mc {
584 resource_size_t aper_size;
585 resource_size_t aper_base;
586 resource_size_t agp_base;
587 /* for some chips with <= 32MB we need to lie
588 * about vram size near mc fb location */
589 u64 mc_vram_size;
590 u64 visible_vram_size;
591 u64 gtt_size;
592 u64 gtt_start;
593 u64 gtt_end;
594 u64 vram_start;
595 u64 vram_end;
596 unsigned vram_width;
597 u64 real_vram_size;
598 int vram_mtrr;
599 u64 gtt_base_align;
600 u64 mc_mask;
601 const struct firmware *fw; /* MC firmware */
602 uint32_t fw_version;
603 struct amdgpu_irq_src vm_fault;
Ken Wang81c59f52015-06-03 21:02:01 +0800604 uint32_t vram_type;
Chunming Zhou50b01972016-07-18 16:59:24 +0800605 uint32_t srbm_soft_reset;
606 struct amdgpu_mode_mc_save save;
Christian Königf7c35ab2017-01-27 11:56:05 +0100607 bool prt_warning;
Junwei Zhang8fe73322016-03-10 14:20:39 +0800608 /* apertures */
609 u64 shared_aperture_start;
610 u64 shared_aperture_end;
611 u64 private_aperture_start;
612 u64 private_aperture_end;
Alex Xiee60f8db2017-03-09 11:36:26 -0500613 /* protects concurrent invalidation */
614 spinlock_t invalidate_lock;
Alex Deucher97b2e202015-04-20 16:51:00 -0400615};
616
617/*
618 * GPU doorbell structures, functions & helpers
619 */
620typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
621{
622 AMDGPU_DOORBELL_KIQ = 0x000,
623 AMDGPU_DOORBELL_HIQ = 0x001,
624 AMDGPU_DOORBELL_DIQ = 0x002,
625 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
626 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
627 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
628 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
629 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
630 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
631 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
632 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
633 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
634 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
635 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
636 AMDGPU_DOORBELL_IH = 0x1E8,
637 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
638 AMDGPU_DOORBELL_INVALID = 0xFFFF
639} AMDGPU_DOORBELL_ASSIGNMENT;
640
641struct amdgpu_doorbell {
642 /* doorbell mmio */
643 resource_size_t base;
644 resource_size_t size;
645 u32 __iomem *ptr;
646 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
647};
648
Ken Wang39807b92016-03-18 15:41:42 +0800649/*
650 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
651 */
652typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
653{
654 /*
655 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
656 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
657 * Compute related doorbells are allocated from 0x00 to 0x8a
658 */
659
660
661 /* kernel scheduling */
662 AMDGPU_DOORBELL64_KIQ = 0x00,
663
664 /* HSA interface queue and debug queue */
665 AMDGPU_DOORBELL64_HIQ = 0x01,
666 AMDGPU_DOORBELL64_DIQ = 0x02,
667
668 /* Compute engines */
669 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
670 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
671 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
672 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
673 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
674 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
675 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
676 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
677
678 /* User queue doorbell range (128 doorbells) */
679 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
680 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
681
682 /* Graphics engine */
683 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
684
685 /*
686 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
687 * Graphics voltage island aperture 1
688 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
689 */
690
691 /* sDMA engines */
692 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
693 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
694 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
695 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
696
697 /* Interrupt handler */
698 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
699 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
700 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
701
Monk Liue6b3ecb2016-12-30 16:18:56 +0800702 /* VCN engine use 32 bits doorbell */
703 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
704 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
705 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
706 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
707
708 /* overlap the doorbell assignment with VCN as they are mutually exclusive
709 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
710 */
711 AMDGPU_DOORBELL64_RING0_1 = 0xF8,
712 AMDGPU_DOORBELL64_RING2_3 = 0xF9,
713 AMDGPU_DOORBELL64_RING4_5 = 0xFA,
714 AMDGPU_DOORBELL64_RING6_7 = 0xFB,
715
716 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
717 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
718 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
719 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
Ken Wang39807b92016-03-18 15:41:42 +0800720
721 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
722 AMDGPU_DOORBELL64_INVALID = 0xFFFF
723} AMDGPU_DOORBELL64_ASSIGNMENT;
724
725
Alex Deucher97b2e202015-04-20 16:51:00 -0400726void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
727 phys_addr_t *aperture_base,
728 size_t *aperture_size,
729 size_t *start_offset);
730
731/*
732 * IRQS.
733 */
734
735struct amdgpu_flip_work {
Michel Dänzer325cbba2016-08-04 12:39:37 +0900736 struct delayed_work flip_work;
Alex Deucher97b2e202015-04-20 16:51:00 -0400737 struct work_struct unpin_work;
738 struct amdgpu_device *adev;
739 int crtc_id;
Michel Dänzer325cbba2016-08-04 12:39:37 +0900740 u32 target_vblank;
Alex Deucher97b2e202015-04-20 16:51:00 -0400741 uint64_t base;
742 struct drm_pending_vblank_event *event;
Christian König765e7fb2016-09-15 15:06:50 +0200743 struct amdgpu_bo *old_abo;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100744 struct dma_fence *excl;
Christian König1ffd2652015-08-11 17:29:52 +0200745 unsigned shared_count;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100746 struct dma_fence **shared;
747 struct dma_fence_cb cb;
Alex Deuchercb9e59d2016-05-05 16:03:57 -0400748 bool async;
Alex Deucher97b2e202015-04-20 16:51:00 -0400749};
750
751
752/*
753 * CP & rings.
754 */
755
756struct amdgpu_ib {
757 struct amdgpu_sa_bo *sa_bo;
758 uint32_t length_dw;
759 uint64_t gpu_addr;
760 uint32_t *ptr;
Jammy Zhoude807f82015-05-11 23:41:41 +0800761 uint32_t flags;
Alex Deucher97b2e202015-04-20 16:51:00 -0400762};
763
Nils Wallménius62250a92016-04-10 16:30:00 +0200764extern const struct amd_sched_backend_ops amdgpu_sched_ops;
Chunming Zhouc1b69ed2015-07-21 13:45:14 +0800765
Christian König50838c82016-02-03 13:44:52 +0100766int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
Monk Liuc5637832016-04-19 20:11:32 +0800767 struct amdgpu_job **job, struct amdgpu_vm *vm);
Christian Königd71518b2016-02-01 12:20:25 +0100768int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
769 struct amdgpu_job **job);
Monk Liub6723c82016-03-10 12:14:44 +0800770
Christian Königa5fb4ec2016-06-29 15:10:31 +0200771void amdgpu_job_free_resources(struct amdgpu_job *job);
Christian König50838c82016-02-03 13:44:52 +0100772void amdgpu_job_free(struct amdgpu_job *job);
Christian Königd71518b2016-02-01 12:20:25 +0100773int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
Christian König2bd9ccf2016-02-01 12:53:58 +0100774 struct amd_sched_entity *entity, void *owner,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100775 struct dma_fence **f);
Christian König8b4fb002015-11-15 16:04:16 +0100776
Alex Deucher97b2e202015-04-20 16:51:00 -0400777/*
778 * context related structures
779 */
780
Christian König21c16bf2015-07-07 17:24:49 +0200781struct amdgpu_ctx_ring {
Christian König91404fb2015-08-05 18:33:21 +0200782 uint64_t sequence;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100783 struct dma_fence **fences;
Christian König91404fb2015-08-05 18:33:21 +0200784 struct amd_sched_entity entity;
Christian König21c16bf2015-07-07 17:24:49 +0200785};
786
Alex Deucher97b2e202015-04-20 16:51:00 -0400787struct amdgpu_ctx {
Alex Deucher0b492a42015-08-16 22:48:26 -0400788 struct kref refcount;
Chunming Zhou9cb7e5a2015-07-21 13:17:19 +0800789 struct amdgpu_device *adev;
Alex Deucher0b492a42015-08-16 22:48:26 -0400790 unsigned reset_counter;
Christian König21c16bf2015-07-07 17:24:49 +0200791 spinlock_t ring_lock;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100792 struct dma_fence **fences;
Christian König21c16bf2015-07-07 17:24:49 +0200793 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
Monk Liu753ad492016-08-26 13:28:28 +0800794 bool preamble_presented;
Alex Deucher97b2e202015-04-20 16:51:00 -0400795};
796
797struct amdgpu_ctx_mgr {
Alex Deucher0b492a42015-08-16 22:48:26 -0400798 struct amdgpu_device *adev;
799 struct mutex lock;
800 /* protected by lock */
801 struct idr ctx_handles;
Alex Deucher97b2e202015-04-20 16:51:00 -0400802};
803
Alex Deucher0b492a42015-08-16 22:48:26 -0400804struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
805int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
806
Christian König21c16bf2015-07-07 17:24:49 +0200807uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100808 struct dma_fence *fence);
809struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
Christian König21c16bf2015-07-07 17:24:49 +0200810 struct amdgpu_ring *ring, uint64_t seq);
811
Alex Deucher0b492a42015-08-16 22:48:26 -0400812int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
813 struct drm_file *filp);
814
Christian Königefd4ccb2015-08-04 16:20:31 +0200815void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
816void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
Alex Deucher0b492a42015-08-16 22:48:26 -0400817
Alex Deucher97b2e202015-04-20 16:51:00 -0400818/*
819 * file private structure
820 */
821
822struct amdgpu_fpriv {
823 struct amdgpu_vm vm;
Junwei Zhangb85891b2017-01-16 13:59:01 +0800824 struct amdgpu_bo_va *prt_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400825 struct mutex bo_list_lock;
826 struct idr bo_list_handles;
Alex Deucher0b492a42015-08-16 22:48:26 -0400827 struct amdgpu_ctx_mgr ctx_mgr;
Chunming Zhouf1892132017-05-15 16:48:27 +0800828 u32 vram_lost_counter;
Alex Deucher97b2e202015-04-20 16:51:00 -0400829};
830
831/*
832 * residency list
833 */
834
835struct amdgpu_bo_list {
836 struct mutex lock;
837 struct amdgpu_bo *gds_obj;
838 struct amdgpu_bo *gws_obj;
839 struct amdgpu_bo *oa_obj;
Christian König211dff52016-02-22 15:40:59 +0100840 unsigned first_userptr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400841 unsigned num_entries;
842 struct amdgpu_bo_list_entry *array;
843};
844
845struct amdgpu_bo_list *
846amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
Christian König636ce252015-12-18 21:26:47 +0100847void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
848 struct list_head *validated);
Alex Deucher97b2e202015-04-20 16:51:00 -0400849void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
850void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
851
852/*
853 * GFX stuff
854 */
855#include "clearstate_defs.h"
856
Alex Deucher79e54122016-04-08 15:45:13 -0400857struct amdgpu_rlc_funcs {
858 void (*enter_safe_mode)(struct amdgpu_device *adev);
859 void (*exit_safe_mode)(struct amdgpu_device *adev);
860};
861
Alex Deucher97b2e202015-04-20 16:51:00 -0400862struct amdgpu_rlc {
863 /* for power gating */
864 struct amdgpu_bo *save_restore_obj;
865 uint64_t save_restore_gpu_addr;
866 volatile uint32_t *sr_ptr;
867 const u32 *reg_list;
868 u32 reg_list_size;
869 /* for clear state */
870 struct amdgpu_bo *clear_state_obj;
871 uint64_t clear_state_gpu_addr;
872 volatile uint32_t *cs_ptr;
873 const struct cs_section_def *cs_data;
874 u32 clear_state_size;
875 /* for cp tables */
876 struct amdgpu_bo *cp_table_obj;
877 uint64_t cp_table_gpu_addr;
878 volatile uint32_t *cp_table_ptr;
879 u32 cp_table_size;
Alex Deucher79e54122016-04-08 15:45:13 -0400880
881 /* safe mode for updating CG/PG state */
882 bool in_safe_mode;
883 const struct amdgpu_rlc_funcs *funcs;
Eric Huang2b6cd972016-04-14 17:26:07 -0400884
885 /* for firmware data */
886 u32 save_and_restore_offset;
887 u32 clear_state_descriptor_offset;
888 u32 avail_scratch_ram_locations;
889 u32 reg_restore_list_size;
890 u32 reg_list_format_start;
891 u32 reg_list_format_separate_start;
892 u32 starting_offsets_start;
893 u32 reg_list_format_size_bytes;
894 u32 reg_list_size_bytes;
895
896 u32 *register_list_format;
897 u32 *register_restore;
Alex Deucher97b2e202015-04-20 16:51:00 -0400898};
899
900struct amdgpu_mec {
901 struct amdgpu_bo *hpd_eop_obj;
902 u64 hpd_eop_gpu_addr;
Ken Wangb1023572017-03-03 17:59:39 -0500903 struct amdgpu_bo *mec_fw_obj;
904 u64 mec_fw_gpu_addr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400905 u32 num_pipe;
906 u32 num_mec;
907 u32 num_queue;
Xiangliang Yu59a82d72017-02-17 16:03:10 +0800908 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
Alex Deucher97b2e202015-04-20 16:51:00 -0400909};
910
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800911struct amdgpu_kiq {
912 u64 eop_gpu_addr;
913 struct amdgpu_bo *eop_obj;
Shaoyun Liucdf6adb2017-04-28 17:18:26 -0400914 struct mutex ring_mutex;
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800915 struct amdgpu_ring ring;
916 struct amdgpu_irq_src irq;
917};
918
Alex Deucher97b2e202015-04-20 16:51:00 -0400919/*
920 * GPU scratch registers structures, functions & helpers
921 */
922struct amdgpu_scratch {
923 unsigned num_reg;
924 uint32_t reg_base;
Nils Wallménius50261152017-01-16 21:56:48 +0100925 uint32_t free_mask;
Alex Deucher97b2e202015-04-20 16:51:00 -0400926};
927
928/*
929 * GFX configurations
930 */
Alex Deuchere3fa7632016-10-10 10:56:21 -0400931#define AMDGPU_GFX_MAX_SE 4
932#define AMDGPU_GFX_MAX_SH_PER_SE 2
933
934struct amdgpu_rb_config {
935 uint32_t rb_backend_disable;
936 uint32_t user_rb_backend_disable;
937 uint32_t raster_config;
938 uint32_t raster_config_1;
939};
940
Andrey Grodzovskyd0e95752016-12-12 13:40:37 -0500941struct gb_addr_config {
942 uint16_t pipe_interleave_size;
943 uint8_t num_pipes;
944 uint8_t max_compress_frags;
945 uint8_t num_banks;
946 uint8_t num_se;
947 uint8_t num_rb_per_se;
948};
949
Junwei Zhangea323f82017-02-21 10:32:37 +0800950struct amdgpu_gfx_config {
Alex Deucher97b2e202015-04-20 16:51:00 -0400951 unsigned max_shader_engines;
952 unsigned max_tile_pipes;
953 unsigned max_cu_per_sh;
954 unsigned max_sh_per_se;
955 unsigned max_backends_per_se;
956 unsigned max_texture_channel_caches;
957 unsigned max_gprs;
958 unsigned max_gs_threads;
959 unsigned max_hw_contexts;
960 unsigned sc_prim_fifo_size_frontend;
961 unsigned sc_prim_fifo_size_backend;
962 unsigned sc_hiz_tile_fifo_size;
963 unsigned sc_earlyz_tile_fifo_size;
964
965 unsigned num_tile_pipes;
966 unsigned backend_enable_mask;
967 unsigned mem_max_burst_length_bytes;
968 unsigned mem_row_size_in_kb;
969 unsigned shader_engine_tile_size;
970 unsigned num_gpus;
971 unsigned multi_gpu_tile_size;
972 unsigned mc_arb_ramcfg;
973 unsigned gb_addr_config;
Alex Deucher8f8e00c2016-02-12 00:39:13 -0500974 unsigned num_rbs;
Junwei Zhang408bfe72017-04-27 11:12:07 +0800975 unsigned gs_vgt_table_depth;
976 unsigned gs_prim_buffer_depth;
Alex Deucher97b2e202015-04-20 16:51:00 -0400977
978 uint32_t tile_mode_array[32];
979 uint32_t macrotile_mode_array[16];
Alex Deuchere3fa7632016-10-10 10:56:21 -0400980
Andrey Grodzovskyd0e95752016-12-12 13:40:37 -0500981 struct gb_addr_config gb_addr_config_fields;
Alex Deuchere3fa7632016-10-10 10:56:21 -0400982 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
Junwei Zhangdf6e2c42017-02-17 11:05:49 +0800983
984 /* gfx configure feature */
985 uint32_t double_offchip_lds_buf;
Alex Deucher97b2e202015-04-20 16:51:00 -0400986};
987
Alex Deucher7dae69a2016-05-03 16:25:53 -0400988struct amdgpu_cu_info {
989 uint32_t number; /* total active CU number */
990 uint32_t ao_cu_mask;
Junwei Zhang408bfe72017-04-27 11:12:07 +0800991 uint32_t wave_front_size;
Alex Deucher7dae69a2016-05-03 16:25:53 -0400992 uint32_t bitmap[4][4];
993};
994
Alex Deucherb95e31f2016-07-07 15:01:42 -0400995struct amdgpu_gfx_funcs {
996 /* get the gpu clock counter */
997 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
Tom St Denis9559ef52016-06-28 10:26:48 -0400998 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
Tom St Denis472259f2016-10-14 09:49:09 -0400999 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
Tom St Denisc5a60ce2016-12-05 11:39:19 -05001000 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
1001 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
Alex Deucherb95e31f2016-07-07 15:01:42 -04001002};
1003
Alex Deucherbce23e02017-03-28 12:52:08 -04001004struct amdgpu_ngg_buf {
1005 struct amdgpu_bo *bo;
1006 uint64_t gpu_addr;
1007 uint32_t size;
1008 uint32_t bo_size;
1009};
1010
1011enum {
Guenter Roeckaf8baf12017-05-03 23:49:18 -07001012 NGG_PRIM = 0,
1013 NGG_POS,
1014 NGG_CNTL,
1015 NGG_PARAM,
Alex Deucherbce23e02017-03-28 12:52:08 -04001016 NGG_BUF_MAX
1017};
1018
1019struct amdgpu_ngg {
1020 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1021 uint32_t gds_reserve_addr;
1022 uint32_t gds_reserve_size;
1023 bool init;
1024};
1025
Alex Deucher97b2e202015-04-20 16:51:00 -04001026struct amdgpu_gfx {
1027 struct mutex gpu_clock_mutex;
Junwei Zhangea323f82017-02-21 10:32:37 +08001028 struct amdgpu_gfx_config config;
Alex Deucher97b2e202015-04-20 16:51:00 -04001029 struct amdgpu_rlc rlc;
1030 struct amdgpu_mec mec;
Xiangliang Yu4e638ae2016-12-23 15:00:01 +08001031 struct amdgpu_kiq kiq;
Alex Deucher97b2e202015-04-20 16:51:00 -04001032 struct amdgpu_scratch scratch;
1033 const struct firmware *me_fw; /* ME firmware */
1034 uint32_t me_fw_version;
1035 const struct firmware *pfp_fw; /* PFP firmware */
1036 uint32_t pfp_fw_version;
1037 const struct firmware *ce_fw; /* CE firmware */
1038 uint32_t ce_fw_version;
1039 const struct firmware *rlc_fw; /* RLC firmware */
1040 uint32_t rlc_fw_version;
1041 const struct firmware *mec_fw; /* MEC firmware */
1042 uint32_t mec_fw_version;
1043 const struct firmware *mec2_fw; /* MEC2 firmware */
1044 uint32_t mec2_fw_version;
Ken Wang02558a02015-06-03 19:52:06 +08001045 uint32_t me_feature_version;
1046 uint32_t ce_feature_version;
1047 uint32_t pfp_feature_version;
Jammy Zhou351643d2015-08-04 10:43:50 +08001048 uint32_t rlc_feature_version;
1049 uint32_t mec_feature_version;
1050 uint32_t mec2_feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001051 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1052 unsigned num_gfx_rings;
1053 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1054 unsigned num_compute_rings;
1055 struct amdgpu_irq_src eop_irq;
1056 struct amdgpu_irq_src priv_reg_irq;
1057 struct amdgpu_irq_src priv_inst_irq;
1058 /* gfx status */
Alex Deucher7dae69a2016-05-03 16:25:53 -04001059 uint32_t gfx_current_status;
Ken Wanga101a892015-06-03 17:47:54 +08001060 /* ce ram size*/
Alex Deucher7dae69a2016-05-03 16:25:53 -04001061 unsigned ce_ram_size;
1062 struct amdgpu_cu_info cu_info;
Alex Deucherb95e31f2016-07-07 15:01:42 -04001063 const struct amdgpu_gfx_funcs *funcs;
Chunming Zhou3d7c6382016-07-15 11:28:30 +08001064
1065 /* reset mask */
1066 uint32_t grbm_soft_reset;
1067 uint32_t srbm_soft_reset;
Monk Liu223049c2017-01-26 15:32:16 +08001068 bool in_reset;
David Panaritib4e40672017-03-28 12:57:31 -04001069 /* s3/s4 mask */
1070 bool in_suspend;
Alex Deucherbce23e02017-03-28 12:52:08 -04001071 /* NGG */
1072 struct amdgpu_ngg ngg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001073};
1074
Christian Königb07c60c2016-01-31 12:29:04 +01001075int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
Alex Deucher97b2e202015-04-20 16:51:00 -04001076 unsigned size, struct amdgpu_ib *ib);
Christian König4d9c5142016-05-03 18:46:19 +02001077void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
Chris Wilsonf54d1862016-10-25 13:00:45 +01001078 struct dma_fence *f);
Christian Königb07c60c2016-01-31 12:29:04 +01001079int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
Junwei Zhang50ddc752017-01-23 16:30:38 +08001080 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1081 struct dma_fence **f);
Alex Deucher97b2e202015-04-20 16:51:00 -04001082int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1083void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1084int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001085
1086/*
1087 * CS.
1088 */
1089struct amdgpu_cs_chunk {
1090 uint32_t chunk_id;
1091 uint32_t length_dw;
Christian König758ac172016-05-06 22:14:00 +02001092 void *kdata;
Alex Deucher97b2e202015-04-20 16:51:00 -04001093};
1094
1095struct amdgpu_cs_parser {
1096 struct amdgpu_device *adev;
1097 struct drm_file *filp;
Christian König3cb485f2015-05-11 15:34:59 +02001098 struct amdgpu_ctx *ctx;
Christian Königc3cca412015-12-15 14:41:33 +01001099
Alex Deucher97b2e202015-04-20 16:51:00 -04001100 /* chunks */
1101 unsigned nchunks;
1102 struct amdgpu_cs_chunk *chunks;
Alex Deucher97b2e202015-04-20 16:51:00 -04001103
Christian König50838c82016-02-03 13:44:52 +01001104 /* scheduler job object */
1105 struct amdgpu_job *job;
Alex Deucher97b2e202015-04-20 16:51:00 -04001106
Christian Königc3cca412015-12-15 14:41:33 +01001107 /* buffer objects */
1108 struct ww_acquire_ctx ticket;
1109 struct amdgpu_bo_list *bo_list;
1110 struct amdgpu_bo_list_entry vm_pd;
1111 struct list_head validated;
Chris Wilsonf54d1862016-10-25 13:00:45 +01001112 struct dma_fence *fence;
Christian Königc3cca412015-12-15 14:41:33 +01001113 uint64_t bytes_moved_threshold;
1114 uint64_t bytes_moved;
Christian König662bfa62016-09-01 12:13:18 +02001115 struct amdgpu_bo_list_entry *evictable;
Alex Deucher97b2e202015-04-20 16:51:00 -04001116
1117 /* user fence */
Christian König91acbeb2015-12-14 16:42:31 +01001118 struct amdgpu_bo_list_entry uf_entry;
Alex Deucher97b2e202015-04-20 16:51:00 -04001119};
1120
Monk Liu753ad492016-08-26 13:28:28 +08001121#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1122#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1123#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1124
Chunming Zhoubb977d32015-08-18 15:16:40 +08001125struct amdgpu_job {
1126 struct amd_sched_job base;
1127 struct amdgpu_device *adev;
Christian Königedf600d2016-05-03 15:54:54 +02001128 struct amdgpu_vm *vm;
Christian Königb07c60c2016-01-31 12:29:04 +01001129 struct amdgpu_ring *ring;
Christian Könige86f9ce2016-02-08 12:13:05 +01001130 struct amdgpu_sync sync;
Chunming Zhoua340c7b2017-05-18 15:19:03 +08001131 struct amdgpu_sync dep_sync;
Chunming Zhoudf83d1e2017-05-09 15:50:22 +08001132 struct amdgpu_sync sched_sync;
Chunming Zhoubb977d32015-08-18 15:16:40 +08001133 struct amdgpu_ib *ibs;
Chris Wilsonf54d1862016-10-25 13:00:45 +01001134 struct dma_fence *fence; /* the hw fence */
Monk Liu753ad492016-08-26 13:28:28 +08001135 uint32_t preamble_status;
Chunming Zhoubb977d32015-08-18 15:16:40 +08001136 uint32_t num_ibs;
Christian Könige2840222015-11-05 19:49:48 +01001137 void *owner;
Monk Liu3aecd242016-08-25 15:40:48 +08001138 uint64_t fence_ctx; /* the fence_context this job uses */
Chunming Zhoufd53be32016-07-01 17:59:01 +08001139 bool vm_needs_flush;
Christian Königd88bf582016-05-06 17:50:03 +02001140 unsigned vm_id;
1141 uint64_t vm_pd_addr;
1142 uint32_t gds_base, gds_size;
1143 uint32_t gws_base, gws_size;
1144 uint32_t oa_base, oa_size;
Christian König758ac172016-05-06 22:14:00 +02001145
1146 /* user fence handling */
Christian Königb5f5acb2016-06-29 13:26:41 +02001147 uint64_t uf_addr;
Christian König758ac172016-05-06 22:14:00 +02001148 uint64_t uf_sequence;
1149
Chunming Zhoubb977d32015-08-18 15:16:40 +08001150};
Junwei Zhanga6db8a32015-09-09 09:21:19 +08001151#define to_amdgpu_job(sched_job) \
1152 container_of((sched_job), struct amdgpu_job, base)
Chunming Zhoubb977d32015-08-18 15:16:40 +08001153
Christian König7270f832016-01-31 11:00:41 +01001154static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1155 uint32_t ib_idx, int idx)
Alex Deucher97b2e202015-04-20 16:51:00 -04001156{
Christian König50838c82016-02-03 13:44:52 +01001157 return p->job->ibs[ib_idx].ptr[idx];
Alex Deucher97b2e202015-04-20 16:51:00 -04001158}
1159
Christian König7270f832016-01-31 11:00:41 +01001160static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1161 uint32_t ib_idx, int idx,
1162 uint32_t value)
1163{
Christian König50838c82016-02-03 13:44:52 +01001164 p->job->ibs[ib_idx].ptr[idx] = value;
Christian König7270f832016-01-31 11:00:41 +01001165}
1166
Alex Deucher97b2e202015-04-20 16:51:00 -04001167/*
1168 * Writeback
1169 */
1170#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1171
1172struct amdgpu_wb {
1173 struct amdgpu_bo *wb_obj;
1174 volatile uint32_t *wb;
1175 uint64_t gpu_addr;
1176 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1177 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1178};
1179
1180int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1181void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
Ken Wang70142852016-03-18 15:08:49 +08001182int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
1183void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
Alex Deucher97b2e202015-04-20 16:51:00 -04001184
Alex Deucherd0dd7f02015-11-11 19:45:06 -05001185void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1186
Alex Deucher97b2e202015-04-20 16:51:00 -04001187/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001188 * SDMA
1189 */
Alex Deucherc113ea12015-10-08 16:30:37 -04001190struct amdgpu_sdma_instance {
Alex Deucher97b2e202015-04-20 16:51:00 -04001191 /* SDMA firmware */
1192 const struct firmware *fw;
1193 uint32_t fw_version;
Jammy Zhoucfa21042015-08-04 10:50:47 +08001194 uint32_t feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001195
1196 struct amdgpu_ring ring;
Jammy Zhou18111de2015-08-31 14:06:39 +08001197 bool burst_nop;
Alex Deucher97b2e202015-04-20 16:51:00 -04001198};
1199
Alex Deucherc113ea12015-10-08 16:30:37 -04001200struct amdgpu_sdma {
1201 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
Ken Wang30d15742016-01-19 14:05:23 +08001202#ifdef CONFIG_DRM_AMDGPU_SI
1203 //SI DMA has a difference trap irq number for the second engine
1204 struct amdgpu_irq_src trap_irq_1;
1205#endif
Alex Deucherc113ea12015-10-08 16:30:37 -04001206 struct amdgpu_irq_src trap_irq;
1207 struct amdgpu_irq_src illegal_inst_irq;
Christian Königedf600d2016-05-03 15:54:54 +02001208 int num_instances;
Chunming Zhoue702a682016-07-13 10:28:56 +08001209 uint32_t srbm_soft_reset;
Alex Deucherc113ea12015-10-08 16:30:37 -04001210};
1211
Alex Deucher97b2e202015-04-20 16:51:00 -04001212/*
1213 * Firmware
1214 */
Huang Ruie635ee02016-11-01 15:35:38 +08001215enum amdgpu_firmware_load_type {
1216 AMDGPU_FW_LOAD_DIRECT = 0,
1217 AMDGPU_FW_LOAD_SMU,
1218 AMDGPU_FW_LOAD_PSP,
1219};
1220
Alex Deucher97b2e202015-04-20 16:51:00 -04001221struct amdgpu_firmware {
1222 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
Huang Ruie635ee02016-11-01 15:35:38 +08001223 enum amdgpu_firmware_load_type load_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001224 struct amdgpu_bo *fw_buf;
1225 unsigned int fw_size;
Huang Rui2445b222017-03-03 16:20:35 -05001226 unsigned int max_ucodes;
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001227 /* firmwares are loaded by psp instead of smu from vega10 */
1228 const struct amdgpu_psp_funcs *funcs;
1229 struct amdgpu_bo *rbuf;
1230 struct mutex mutex;
Alex Deucher97b2e202015-04-20 16:51:00 -04001231};
1232
1233/*
1234 * Benchmarking
1235 */
1236void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1237
1238
1239/*
1240 * Testing
1241 */
1242void amdgpu_test_moves(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001243
1244/*
1245 * MMU Notifier
1246 */
1247#if defined(CONFIG_MMU_NOTIFIER)
1248int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1249void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1250#else
Harry Wentland1d1106b2015-07-15 07:10:41 -04001251static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
Alex Deucher97b2e202015-04-20 16:51:00 -04001252{
1253 return -ENODEV;
1254}
Harry Wentland1d1106b2015-07-15 07:10:41 -04001255static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
Alex Deucher97b2e202015-04-20 16:51:00 -04001256#endif
1257
1258/*
1259 * Debugfs
1260 */
1261struct amdgpu_debugfs {
Nils Wallménius06ab6832016-05-02 12:46:15 -04001262 const struct drm_info_list *files;
Alex Deucher97b2e202015-04-20 16:51:00 -04001263 unsigned num_files;
1264};
1265
1266int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
Nils Wallménius06ab6832016-05-02 12:46:15 -04001267 const struct drm_info_list *files,
Alex Deucher97b2e202015-04-20 16:51:00 -04001268 unsigned nfiles);
1269int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1270
1271#if defined(CONFIG_DEBUG_FS)
1272int amdgpu_debugfs_init(struct drm_minor *minor);
Alex Deucher97b2e202015-04-20 16:51:00 -04001273#endif
1274
Huang Rui50ab2532016-06-12 15:51:09 +08001275int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1276
Alex Deucher97b2e202015-04-20 16:51:00 -04001277/*
1278 * amdgpu smumgr functions
1279 */
1280struct amdgpu_smumgr_funcs {
1281 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1282 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1283 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1284};
1285
1286/*
1287 * amdgpu smumgr
1288 */
1289struct amdgpu_smumgr {
1290 struct amdgpu_bo *toc_buf;
1291 struct amdgpu_bo *smu_buf;
1292 /* asic priv smu data */
1293 void *priv;
1294 spinlock_t smu_lock;
1295 /* smumgr functions */
1296 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1297 /* ucode loading complete flag */
1298 uint32_t fw_flags;
1299};
1300
1301/*
1302 * ASIC specific register table accessible by UMD
1303 */
1304struct amdgpu_allowed_register_entry {
1305 uint32_t reg_offset;
Alex Deucher97b2e202015-04-20 16:51:00 -04001306 bool grbm_indexed;
1307};
1308
Alex Deucher97b2e202015-04-20 16:51:00 -04001309/*
1310 * ASIC specific functions.
1311 */
1312struct amdgpu_asic_funcs {
1313 bool (*read_disabled_bios)(struct amdgpu_device *adev);
Alex Deucher7946b872015-11-24 10:14:28 -05001314 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1315 u8 *bios, u32 length_bytes);
Alex Deucher97b2e202015-04-20 16:51:00 -04001316 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1317 u32 sh_num, u32 reg_offset, u32 *value);
1318 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1319 int (*reset)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001320 /* get the reference clock */
1321 u32 (*get_xclk)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001322 /* MM block clocks */
1323 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1324 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -04001325 /* static power management */
1326 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1327 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
Alex Deucherbbf282d2017-03-03 17:26:10 -05001328 /* get config memsize register */
1329 u32 (*get_config_memsize)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001330};
1331
1332/*
1333 * IOCTL.
1334 */
1335int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1336 struct drm_file *filp);
1337int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1338 struct drm_file *filp);
1339
1340int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1341 struct drm_file *filp);
1342int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1343 struct drm_file *filp);
1344int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1345 struct drm_file *filp);
1346int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1347 struct drm_file *filp);
1348int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1349 struct drm_file *filp);
1350int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1351 struct drm_file *filp);
1352int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1353int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Junwei Zhangeef18a82016-11-04 16:16:10 -04001354int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1355 struct drm_file *filp);
Alex Deucher97b2e202015-04-20 16:51:00 -04001356
1357int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1358 struct drm_file *filp);
1359
1360/* VRAM scratch page for HDP bug, default vram page */
1361struct amdgpu_vram_scratch {
1362 struct amdgpu_bo *robj;
1363 volatile uint32_t *ptr;
1364 u64 gpu_addr;
1365};
1366
1367/*
1368 * ACPI
1369 */
1370struct amdgpu_atif_notification_cfg {
1371 bool enabled;
1372 int command_code;
1373};
1374
1375struct amdgpu_atif_notifications {
1376 bool display_switch;
1377 bool expansion_mode_change;
1378 bool thermal_state;
1379 bool forced_power_state;
1380 bool system_power_state;
1381 bool display_conf_change;
1382 bool px_gfx_switch;
1383 bool brightness_change;
1384 bool dgpu_display_event;
1385};
1386
1387struct amdgpu_atif_functions {
1388 bool system_params;
1389 bool sbios_requests;
1390 bool select_active_disp;
1391 bool lid_state;
1392 bool get_tv_standard;
1393 bool set_tv_standard;
1394 bool get_panel_expansion_mode;
1395 bool set_panel_expansion_mode;
1396 bool temperature_change;
1397 bool graphics_device_types;
1398};
1399
1400struct amdgpu_atif {
1401 struct amdgpu_atif_notifications notifications;
1402 struct amdgpu_atif_functions functions;
1403 struct amdgpu_atif_notification_cfg notification_cfg;
1404 struct amdgpu_encoder *encoder_for_bl;
1405};
1406
1407struct amdgpu_atcs_functions {
1408 bool get_ext_state;
1409 bool pcie_perf_req;
1410 bool pcie_dev_rdy;
1411 bool pcie_bus_width;
1412};
1413
1414struct amdgpu_atcs {
1415 struct amdgpu_atcs_functions functions;
1416};
1417
Alex Deucher97b2e202015-04-20 16:51:00 -04001418/*
Chunming Zhoud03846a2015-07-28 14:20:03 -04001419 * CGS
1420 */
Dave Airlie110e6f22016-04-12 13:25:48 +10001421struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1422void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001423
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001424/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001425 * Core structure, functions and helpers.
1426 */
1427typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1428typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1429
1430typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1431typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1432
Chunming Zhou0c49e0b2017-05-15 14:20:00 +08001433#define AMDGPU_RESET_MAGIC_NUM 64
Alex Deucher97b2e202015-04-20 16:51:00 -04001434struct amdgpu_device {
1435 struct device *dev;
1436 struct drm_device *ddev;
1437 struct pci_dev *pdev;
Alex Deucher97b2e202015-04-20 16:51:00 -04001438
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001439#ifdef CONFIG_DRM_AMD_ACP
1440 struct amdgpu_acp acp;
1441#endif
1442
Alex Deucher97b2e202015-04-20 16:51:00 -04001443 /* ASIC */
Jammy Zhou2f7d10b2015-07-22 11:29:01 +08001444 enum amd_asic_type asic_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001445 uint32_t family;
1446 uint32_t rev_id;
1447 uint32_t external_rev_id;
1448 unsigned long flags;
1449 int usec_timeout;
1450 const struct amdgpu_asic_funcs *asic_funcs;
1451 bool shutdown;
Alex Deucher97b2e202015-04-20 16:51:00 -04001452 bool need_dma32;
1453 bool accel_working;
Christian Königedf600d2016-05-03 15:54:54 +02001454 struct work_struct reset_work;
Alex Deucher97b2e202015-04-20 16:51:00 -04001455 struct notifier_block acpi_nb;
1456 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1457 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
Christian Königedf600d2016-05-03 15:54:54 +02001458 unsigned debugfs_count;
Alex Deucher97b2e202015-04-20 16:51:00 -04001459#if defined(CONFIG_DEBUG_FS)
Tom St Denisadcec282016-04-15 13:08:44 -04001460 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
Alex Deucher97b2e202015-04-20 16:51:00 -04001461#endif
1462 struct amdgpu_atif atif;
1463 struct amdgpu_atcs atcs;
1464 struct mutex srbm_mutex;
1465 /* GRBM index mutex. Protects concurrent access to GRBM index */
1466 struct mutex grbm_idx_mutex;
1467 struct dev_pm_domain vga_pm_domain;
1468 bool have_disp_power_ref;
1469
1470 /* BIOS */
Alex Deucher0cdd5002017-02-13 16:01:58 -05001471 bool is_atom_fw;
Alex Deucher97b2e202015-04-20 16:51:00 -04001472 uint8_t *bios;
Evan Quana9f5db92016-12-07 09:56:46 +08001473 uint32_t bios_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001474 struct amdgpu_bo *stollen_vga_memory;
Alex Deuchera5bde2f2016-09-23 16:23:41 -04001475 uint32_t bios_scratch_reg_offset;
Alex Deucher97b2e202015-04-20 16:51:00 -04001476 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1477
1478 /* Register/doorbell mmio */
1479 resource_size_t rmmio_base;
1480 resource_size_t rmmio_size;
1481 void __iomem *rmmio;
1482 /* protects concurrent MM_INDEX/DATA based register access */
1483 spinlock_t mmio_idx_lock;
1484 /* protects concurrent SMC based register access */
1485 spinlock_t smc_idx_lock;
1486 amdgpu_rreg_t smc_rreg;
1487 amdgpu_wreg_t smc_wreg;
1488 /* protects concurrent PCIE register access */
1489 spinlock_t pcie_idx_lock;
1490 amdgpu_rreg_t pcie_rreg;
1491 amdgpu_wreg_t pcie_wreg;
Huang Rui36b9a952016-08-31 13:23:25 +08001492 amdgpu_rreg_t pciep_rreg;
1493 amdgpu_wreg_t pciep_wreg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001494 /* protects concurrent UVD register access */
1495 spinlock_t uvd_ctx_idx_lock;
1496 amdgpu_rreg_t uvd_ctx_rreg;
1497 amdgpu_wreg_t uvd_ctx_wreg;
1498 /* protects concurrent DIDT register access */
1499 spinlock_t didt_idx_lock;
1500 amdgpu_rreg_t didt_rreg;
1501 amdgpu_wreg_t didt_wreg;
Rex Zhuccdbb202016-06-08 12:47:41 +08001502 /* protects concurrent gc_cac register access */
1503 spinlock_t gc_cac_idx_lock;
1504 amdgpu_rreg_t gc_cac_rreg;
1505 amdgpu_wreg_t gc_cac_wreg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001506 /* protects concurrent ENDPOINT (audio) register access */
1507 spinlock_t audio_endpt_idx_lock;
1508 amdgpu_block_rreg_t audio_endpt_rreg;
1509 amdgpu_block_wreg_t audio_endpt_wreg;
1510 void __iomem *rio_mem;
1511 resource_size_t rio_mem_size;
1512 struct amdgpu_doorbell doorbell;
1513
1514 /* clock/pll info */
1515 struct amdgpu_clock clock;
1516
1517 /* MC */
1518 struct amdgpu_mc mc;
1519 struct amdgpu_gart gart;
1520 struct amdgpu_dummy_page dummy_page;
1521 struct amdgpu_vm_manager vm_manager;
Alex Xiee60f8db2017-03-09 11:36:26 -05001522 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
Alex Deucher97b2e202015-04-20 16:51:00 -04001523
1524 /* memory management */
1525 struct amdgpu_mman mman;
Alex Deucher97b2e202015-04-20 16:51:00 -04001526 struct amdgpu_vram_scratch vram_scratch;
1527 struct amdgpu_wb wb;
1528 atomic64_t vram_usage;
1529 atomic64_t vram_vis_usage;
1530 atomic64_t gtt_usage;
1531 atomic64_t num_bytes_moved;
Christian Königdbd5ed62016-06-21 16:28:14 +02001532 atomic64_t num_evictions;
Marek Olšák68e2c5f2017-05-17 20:05:08 +02001533 atomic64_t num_vram_cpu_page_faults;
Marek Olšákd94aed52015-05-05 21:13:49 +02001534 atomic_t gpu_reset_counter;
Chunming Zhouf1892132017-05-15 16:48:27 +08001535 atomic_t vram_lost_counter;
Alex Deucher97b2e202015-04-20 16:51:00 -04001536
Marek Olšák95844d22016-08-17 23:49:27 +02001537 /* data for buffer migration throttling */
1538 struct {
1539 spinlock_t lock;
1540 s64 last_update_us;
1541 s64 accum_us; /* accumulated microseconds */
1542 u32 log2_max_MBps;
1543 } mm_stats;
1544
Alex Deucher97b2e202015-04-20 16:51:00 -04001545 /* display */
Emily Deng9accf2f2016-08-10 16:01:25 +08001546 bool enable_virtual_display;
Alex Deucher97b2e202015-04-20 16:51:00 -04001547 struct amdgpu_mode_info mode_info;
1548 struct work_struct hotplug_work;
1549 struct amdgpu_irq_src crtc_irq;
1550 struct amdgpu_irq_src pageflip_irq;
1551 struct amdgpu_irq_src hpd_irq;
1552
1553 /* rings */
Christian König76bf0db2016-06-01 15:10:02 +02001554 u64 fence_context;
Alex Deucher97b2e202015-04-20 16:51:00 -04001555 unsigned num_rings;
1556 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1557 bool ib_pool_ready;
1558 struct amdgpu_sa_manager ring_tmp_bo;
1559
1560 /* interrupts */
1561 struct amdgpu_irq irq;
1562
Alex Deucher1f7371b2015-12-02 17:46:21 -05001563 /* powerplay */
1564 struct amd_powerplay powerplay;
Jammy Zhoue61710c2015-11-10 18:31:08 -05001565 bool pp_enabled;
Eric Huangf3898ea2015-12-11 16:24:34 -05001566 bool pp_force_state_enabled;
Alex Deucher1f7371b2015-12-02 17:46:21 -05001567
Alex Deucher97b2e202015-04-20 16:51:00 -04001568 /* dpm */
1569 struct amdgpu_pm pm;
1570 u32 cg_flags;
1571 u32 pg_flags;
1572
1573 /* amdgpu smumgr */
1574 struct amdgpu_smumgr smu;
1575
1576 /* gfx */
1577 struct amdgpu_gfx gfx;
1578
1579 /* sdma */
Alex Deucherc113ea12015-10-08 16:30:37 -04001580 struct amdgpu_sdma sdma;
Alex Deucher97b2e202015-04-20 16:51:00 -04001581
Leo Liu95d09062016-12-21 13:21:52 -05001582 union {
1583 struct {
1584 /* uvd */
1585 struct amdgpu_uvd uvd;
Alex Deucher97b2e202015-04-20 16:51:00 -04001586
Leo Liu95d09062016-12-21 13:21:52 -05001587 /* vce */
1588 struct amdgpu_vce vce;
1589 };
1590
1591 /* vcn */
1592 struct amdgpu_vcn vcn;
1593 };
Alex Deucher97b2e202015-04-20 16:51:00 -04001594
1595 /* firmwares */
1596 struct amdgpu_firmware firmware;
1597
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001598 /* PSP */
1599 struct psp_context psp;
1600
Alex Deucher97b2e202015-04-20 16:51:00 -04001601 /* GDS */
1602 struct amdgpu_gds gds;
1603
Alex Deuchera1255102016-10-13 17:41:13 -04001604 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
Alex Deucher97b2e202015-04-20 16:51:00 -04001605 int num_ip_blocks;
Alex Deucher97b2e202015-04-20 16:51:00 -04001606 struct mutex mn_lock;
1607 DECLARE_HASHTABLE(mn_hash, 7);
1608
1609 /* tracking pinned memory */
1610 u64 vram_pin_size;
Chunming Zhoue131b912016-04-05 10:48:48 +08001611 u64 invisible_pin_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001612 u64 gart_pin_size;
Oded Gabbay130e0372015-06-12 21:35:14 +03001613
1614 /* amdkfd interface */
1615 struct kfd_dev *kfd;
Chunming Zhou23ca0e42015-07-06 13:42:58 +08001616
Shirish S2dc80b02017-05-25 10:05:25 +05301617 /* delayed work_func for deferring clockgating during resume */
1618 struct delayed_work late_init_work;
1619
Xiangliang Yu5a5099c2017-01-09 18:06:57 -05001620 struct amdgpu_virt virt;
Chunming Zhou0c4e7fa2016-08-17 11:41:30 +08001621
1622 /* link all shadow bo */
1623 struct list_head shadow_list;
1624 struct mutex shadow_list_lock;
Chunming Zhou5c1354b2016-08-30 16:13:10 +08001625 /* link all gtt */
1626 spinlock_t gtt_list_lock;
1627 struct list_head gtt_list;
1628
Jim Quc836fec2017-02-10 15:59:59 +08001629 /* record hw reset is performed */
1630 bool has_hw_reset;
Chunming Zhou0c49e0b2017-05-15 14:20:00 +08001631 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
Jim Quc836fec2017-02-10 15:59:59 +08001632
Alex Deucher97b2e202015-04-20 16:51:00 -04001633};
1634
Christian Königa7d64de2016-09-15 14:58:48 +02001635static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1636{
1637 return container_of(bdev, struct amdgpu_device, mman.bdev);
1638}
1639
Alex Deucher97b2e202015-04-20 16:51:00 -04001640bool amdgpu_device_is_px(struct drm_device *dev);
1641int amdgpu_device_init(struct amdgpu_device *adev,
1642 struct drm_device *ddev,
1643 struct pci_dev *pdev,
1644 uint32_t flags);
1645void amdgpu_device_fini(struct amdgpu_device *adev);
1646int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1647
1648uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
Monk Liu15d72fd2017-01-25 15:07:40 +08001649 uint32_t acc_flags);
Alex Deucher97b2e202015-04-20 16:51:00 -04001650void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
Monk Liu15d72fd2017-01-25 15:07:40 +08001651 uint32_t acc_flags);
Alex Deucher97b2e202015-04-20 16:51:00 -04001652u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1653void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1654
1655u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1656void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
Ken Wang832be402016-03-18 15:23:08 +08001657u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1658void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
Alex Deucher97b2e202015-04-20 16:51:00 -04001659
1660/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001661 * Registers read & write functions.
1662 */
Monk Liu15d72fd2017-01-25 15:07:40 +08001663
1664#define AMDGPU_REGS_IDX (1<<0)
1665#define AMDGPU_REGS_NO_KIQ (1<<1)
1666
1667#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1668#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1669
1670#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1671#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1672#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1673#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1674#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
Alex Deucher97b2e202015-04-20 16:51:00 -04001675#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1676#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1677#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1678#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
Huang Rui36b9a952016-08-31 13:23:25 +08001679#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1680#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001681#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1682#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1683#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1684#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1685#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1686#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
Rex Zhuccdbb202016-06-08 12:47:41 +08001687#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1688#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001689#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1690#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1691#define WREG32_P(reg, val, mask) \
1692 do { \
1693 uint32_t tmp_ = RREG32(reg); \
1694 tmp_ &= (mask); \
1695 tmp_ |= ((val) & ~(mask)); \
1696 WREG32(reg, tmp_); \
1697 } while (0)
1698#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1699#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1700#define WREG32_PLL_P(reg, val, mask) \
1701 do { \
1702 uint32_t tmp_ = RREG32_PLL(reg); \
1703 tmp_ &= (mask); \
1704 tmp_ |= ((val) & ~(mask)); \
1705 WREG32_PLL(reg, tmp_); \
1706 } while (0)
1707#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1708#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1709#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1710
1711#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1712#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
Ken Wang832be402016-03-18 15:23:08 +08001713#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1714#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001715
1716#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1717#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1718
1719#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1720 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1721 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1722
1723#define REG_GET_FIELD(value, reg, field) \
1724 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1725
Tom St Denis61cb8ce2016-08-09 10:13:21 -04001726#define WREG32_FIELD(reg, field, val) \
1727 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1728
Tom St Denisccaf3572017-04-04 09:14:13 -04001729#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1730 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1731
Alex Deucher97b2e202015-04-20 16:51:00 -04001732/*
1733 * BIOS helpers.
1734 */
1735#define RBIOS8(i) (adev->bios[i])
1736#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1737#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1738
1739/*
1740 * RING helpers.
1741 */
1742static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
1743{
1744 if (ring->count_dw <= 0)
Jammy Zhou86c2b792015-05-13 22:52:42 +08001745 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
Ken Wang536fbf92016-03-12 09:32:30 +08001746 ring->ring[ring->wptr++ & ring->buf_mask] = v;
Alex Deucher97b2e202015-04-20 16:51:00 -04001747 ring->wptr &= ring->ptr_mask;
1748 ring->count_dw--;
Alex Deucher97b2e202015-04-20 16:51:00 -04001749}
1750
Monk Liu0a8e1472017-01-17 10:52:33 +08001751static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)
1752{
1753 unsigned occupied, chunk1, chunk2;
1754 void *dst;
1755
Nikola Pajkovsky5b9c58f2017-05-04 12:39:50 -04001756 if (unlikely(ring->count_dw < count_dw)) {
Monk Liu0a8e1472017-01-17 10:52:33 +08001757 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
Nikola Pajkovsky5b9c58f2017-05-04 12:39:50 -04001758 return;
Monk Liu0a8e1472017-01-17 10:52:33 +08001759 }
Nikola Pajkovsky5b9c58f2017-05-04 12:39:50 -04001760
1761 occupied = ring->wptr & ring->buf_mask;
1762 dst = (void *)&ring->ring[occupied];
1763 chunk1 = ring->buf_mask + 1 - occupied;
1764 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
1765 chunk2 = count_dw - chunk1;
1766 chunk1 <<= 2;
1767 chunk2 <<= 2;
1768
1769 if (chunk1)
1770 memcpy(dst, src, chunk1);
1771
1772 if (chunk2) {
1773 src += chunk1;
1774 dst = (void *)ring->ring;
1775 memcpy(dst, src, chunk2);
1776 }
1777
1778 ring->wptr += count_dw;
1779 ring->wptr &= ring->ptr_mask;
1780 ring->count_dw -= count_dw;
Monk Liu0a8e1472017-01-17 10:52:33 +08001781}
1782
Alex Deucherc113ea12015-10-08 16:30:37 -04001783static inline struct amdgpu_sdma_instance *
1784amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001785{
1786 struct amdgpu_device *adev = ring->adev;
1787 int i;
1788
Alex Deucherc113ea12015-10-08 16:30:37 -04001789 for (i = 0; i < adev->sdma.num_instances; i++)
1790 if (&adev->sdma.instance[i].ring == ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001791 break;
1792
1793 if (i < AMDGPU_MAX_SDMA_INSTANCES)
Alex Deucherc113ea12015-10-08 16:30:37 -04001794 return &adev->sdma.instance[i];
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001795 else
1796 return NULL;
1797}
1798
Alex Deucher97b2e202015-04-20 16:51:00 -04001799/*
1800 * ASICs macro.
1801 */
1802#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1803#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001804#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1805#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1806#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -04001807#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1808#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1809#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001810#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
Alex Deucher7946b872015-11-24 10:14:28 -05001811#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
Alex Deucher97b2e202015-04-20 16:51:00 -04001812#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
Alex Deucherbbf282d2017-03-03 17:26:10 -05001813#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001814#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1815#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1816#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
Christian Königde9ea7b2016-08-12 11:33:30 +02001817#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
Alex Deucher97b2e202015-04-20 16:51:00 -04001818#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
Alex Xie54635452017-02-14 12:22:57 -05001819#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04001820#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1821#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
Christian Königbbec97a2016-07-05 21:07:17 +02001822#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
Alex Deucher97b2e202015-04-20 16:51:00 -04001823#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1824#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1825#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
Christian Königd88bf582016-05-06 17:50:03 +02001826#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
Christian Königb8c7b392016-03-01 15:42:52 +01001827#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
Alex Deucher97b2e202015-04-20 16:51:00 -04001828#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
Chunming Zhou890ee232015-06-01 14:35:03 +08001829#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04001830#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
Christian Königd2edb072015-05-11 14:10:34 +02001831#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
Chunming Zhou11afbde2016-03-03 11:38:48 +08001832#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
Monk Liuc2167a62016-08-26 14:12:37 +08001833#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
Monk Liu753ad492016-08-26 13:28:28 +08001834#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
Xiangliang Yub6091c12017-01-10 12:53:52 +08001835#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1836#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
Monk Liu3b4d68e2017-05-01 18:09:22 +08001837#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
Christian König9e5d53092016-01-31 12:20:55 +01001838#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
Monk Liu03ccf482016-01-14 19:07:38 +08001839#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1840#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
Alex Deucher97b2e202015-04-20 16:51:00 -04001841#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1842#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1843#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1844#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1845#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1846#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
Alex Deucher97b2e202015-04-20 16:51:00 -04001847#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1848#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1849#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1850#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1851#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1852#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
Alex Deuchercb9e59d2016-05-05 16:03:57 -04001853#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
Alex Deucher97b2e202015-04-20 16:51:00 -04001854#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1855#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1856#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1857#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1858#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
Chunming Zhouc7ae72c2015-08-25 17:23:45 +08001859#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
Chunming Zhou6e7a3842015-08-27 13:46:09 +08001860#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
Alex Deucherb95e31f2016-07-07 15:01:42 -04001861#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
Tom St Denis9559ef52016-06-28 10:26:48 -04001862#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
Alex Deucher97b2e202015-04-20 16:51:00 -04001863#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001864#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
Alex Deucher97b2e202015-04-20 16:51:00 -04001865
1866/* Common functions */
1867int amdgpu_gpu_reset(struct amdgpu_device *adev);
Chunming Zhou3ad81f12016-08-05 17:30:17 +08001868bool amdgpu_need_backup(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001869void amdgpu_pci_config_reset(struct amdgpu_device *adev);
Jim Quc836fec2017-02-10 15:59:59 +08001870bool amdgpu_need_post(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001871void amdgpu_update_display_priority(struct amdgpu_device *adev);
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001872
Alex Deucher97b2e202015-04-20 16:51:00 -04001873int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
1874int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
1875 u32 ip_instance, u32 ring,
1876 struct amdgpu_ring **out_ring);
Samuel Pitoisetfad06122017-02-09 11:33:37 +01001877void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
Christian König765e7fb2016-09-15 15:06:50 +02001878void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
Alex Deucher97b2e202015-04-20 16:51:00 -04001879bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
Christian König2f568db2016-02-23 12:36:59 +01001880int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
Alex Deucher97b2e202015-04-20 16:51:00 -04001881int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1882 uint32_t flags);
1883bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
Christian Königcc325d12016-02-08 11:08:35 +01001884struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
Christian Königd7006962016-02-08 10:57:22 +01001885bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1886 unsigned long end);
Christian König2f568db2016-02-23 12:36:59 +01001887bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1888 int *last_invalidated);
Alex Deucher97b2e202015-04-20 16:51:00 -04001889bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
Chunming Zhou6b777602016-09-21 16:19:19 +08001890uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
Alex Deucher97b2e202015-04-20 16:51:00 -04001891 struct ttm_mem_reg *mem);
1892void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1893void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1894void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
Baoyou Xie9f31a0b02016-09-15 21:43:26 +08001895int amdgpu_ttm_init(struct amdgpu_device *adev);
1896void amdgpu_ttm_fini(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001897void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1898 const u32 *registers,
1899 const u32 array_size);
1900
1901bool amdgpu_device_is_px(struct drm_device *dev);
1902/* atpx handler */
1903#if defined(CONFIG_VGA_SWITCHEROO)
1904void amdgpu_register_atpx_handler(void);
1905void amdgpu_unregister_atpx_handler(void);
Alex Deuchera78fe132016-06-01 13:08:21 -04001906bool amdgpu_has_atpx_dgpu_power_cntl(void);
Alex Deucher2f5af822016-06-02 09:04:01 -04001907bool amdgpu_is_atpx_hybrid(void);
Alex Deucherefc83cf2016-09-14 14:01:41 -04001908bool amdgpu_atpx_dgpu_req_power_for_displays(void);
Alex Xie714f88e2017-04-05 11:07:13 -04001909bool amdgpu_has_atpx(void);
Alex Deucher97b2e202015-04-20 16:51:00 -04001910#else
1911static inline void amdgpu_register_atpx_handler(void) {}
1912static inline void amdgpu_unregister_atpx_handler(void) {}
Alex Deuchera78fe132016-06-01 13:08:21 -04001913static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
Alex Deucher2f5af822016-06-02 09:04:01 -04001914static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
Alex Deucherefc83cf2016-09-14 14:01:41 -04001915static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
Alex Xie714f88e2017-04-05 11:07:13 -04001916static inline bool amdgpu_has_atpx(void) { return false; }
Alex Deucher97b2e202015-04-20 16:51:00 -04001917#endif
1918
1919/*
1920 * KMS
1921 */
1922extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
Nils Wallméniusf498d9e2016-04-10 16:29:59 +02001923extern const int amdgpu_max_kms_ioctl;
Alex Deucher97b2e202015-04-20 16:51:00 -04001924
Chunming Zhouf1892132017-05-15 16:48:27 +08001925bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
1926 struct amdgpu_fpriv *fpriv);
Alex Deucher97b2e202015-04-20 16:51:00 -04001927int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -02001928void amdgpu_driver_unload_kms(struct drm_device *dev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001929void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1930int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1931void amdgpu_driver_postclose_kms(struct drm_device *dev,
1932 struct drm_file *file_priv);
Alex Deucherfaefba92016-12-06 10:38:29 -05001933int amdgpu_suspend(struct amdgpu_device *adev);
Alex Deucher810ddc32016-08-23 13:25:49 -04001934int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1935int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
Thierry Reding88e72712015-09-24 18:35:31 +02001936u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1937int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1938void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
Alex Deucher97b2e202015-04-20 16:51:00 -04001939long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1940 unsigned long arg);
1941
1942/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001943 * functions used by amdgpu_encoder.c
1944 */
1945struct amdgpu_afmt_acr {
1946 u32 clock;
1947
1948 int n_32khz;
1949 int cts_32khz;
1950
1951 int n_44_1khz;
1952 int cts_44_1khz;
1953
1954 int n_48khz;
1955 int cts_48khz;
1956
1957};
1958
1959struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1960
1961/* amdgpu_acpi.c */
1962#if defined(CONFIG_ACPI)
1963int amdgpu_acpi_init(struct amdgpu_device *adev);
1964void amdgpu_acpi_fini(struct amdgpu_device *adev);
1965bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1966int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1967 u8 perf_req, bool advertise);
1968int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1969#else
1970static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1971static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1972#endif
1973
1974struct amdgpu_bo_va_mapping *
1975amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1976 uint64_t addr, struct amdgpu_bo **bo);
Christian Königc855e252016-09-05 17:00:57 +02001977int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
Alex Deucher97b2e202015-04-20 16:51:00 -04001978
1979#include "amdgpu_object.h"
Alex Deucher97b2e202015-04-20 16:51:00 -04001980#endif