blob: dc9a4ee28bc84c5db6f75c8dc4e466eaa6b06619 [file] [log] [blame]
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +02001/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9G45 family SoC";
16 compatible = "atmel,at91sam9g45";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 serial4 = &usart3;
Nicolas Ferre21f81872012-02-11 15:41:40 +010025 gpio0 = &pioA;
26 gpio1 = &pioB;
27 gpio2 = &pioC;
28 gpio3 = &pioD;
29 gpio4 = &pioE;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010030 tcb0 = &tcb0;
31 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020032 i2c0 = &i2c0;
33 i2c1 = &i2c1;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020034 };
35 cpus {
36 cpu@0 {
37 compatible = "arm,arm926ejs";
38 };
39 };
40
Ludovic Desrochesdcce6ce2012-04-02 20:44:20 +020041 memory {
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020042 reg = <0x70000000 0x10000000>;
43 };
44
45 ahb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
51 apb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020058 #interrupt-cells = <3>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020059 compatible = "atmel,at91rm9200-aic";
60 interrupt-controller;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020061 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080062 atmel,external-irqs = <31>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020063 };
64
Jean-Christophe PLAGNIOL-VILLARDa7776ec2012-03-02 20:54:37 +080065 ramc0: ramc@ffffe400 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe400 0x200
68 0xffffe600 0x200>;
69 };
70
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080071 pmc: pmc@fffffc00 {
72 compatible = "atmel,at91rm9200-pmc";
73 reg = <0xfffffc00 0x100>;
74 };
75
Jean-Christophe PLAGNIOL-VILLARDc8082d32012-03-03 03:16:27 +080076 rstc@fffffd00 {
77 compatible = "atmel,at91sam9g45-rstc";
78 reg = <0xfffffd00 0x10>;
79 };
80
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +010081 pit: timer@fffffd30 {
82 compatible = "atmel,at91sam9260-pit";
83 reg = <0xfffffd30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020084 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +010085 };
86
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010087
Jean-Christophe PLAGNIOL-VILLARD82015c42012-03-02 21:01:00 +080088 shdwc@fffffd10 {
89 compatible = "atmel,at91sam9rl-shdwc";
90 reg = <0xfffffd10 0x10>;
91 };
92
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010093 tcb0: timer@fff7c000 {
94 compatible = "atmel,at91rm9200-tcb";
95 reg = <0xfff7c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020096 interrupts = <18 4 0>;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010097 };
98
99 tcb1: timer@fffd4000 {
100 compatible = "atmel,at91rm9200-tcb";
101 reg = <0xfffd4000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200102 interrupts = <18 4 0>;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +0100103 };
104
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200105 dma: dma-controller@ffffec00 {
106 compatible = "atmel,at91sam9g45-dma";
107 reg = <0xffffec00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200108 interrupts = <21 4 0>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200109 };
110
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800111 pinctrl@fffff200 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
115 ranges = <0xfffff200 0xfffff200 0xa00>;
Nicolas Ferre21f81872012-02-11 15:41:40 +0100116
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800117 atmel,mux-mask = <
118 /* A B */
119 0xffffffff 0xffc003ff /* pioA */
120 0xffffffff 0x800f8f00 /* pioB */
121 0xffffffff 0x00000e00 /* pioC */
122 0xffffffff 0xff0c1381 /* pioD */
123 0xffffffff 0x81ffff81 /* pioE */
124 >;
125
126 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800127 dbgu {
128 pinctrl_dbgu: dbgu-0 {
129 atmel,pins =
130 <1 12 0x1 0x0 /* PB12 periph A */
131 1 13 0x1 0x0>; /* PB13 periph A */
132 };
133 };
134
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800135 usart0 {
136 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800137 atmel,pins =
138 <1 19 0x1 0x1 /* PB19 periph A with pullup */
139 1 18 0x1 0x0>; /* PB18 periph A */
140 };
141
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800142 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800143 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800144 <1 17 0x2 0x0>; /* PB17 periph B */
145 };
146
147 pinctrl_usart0_cts: usart0_cts-0 {
148 atmel,pins =
149 <1 15 0x2 0x0>; /* PB15 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800150 };
151 };
152
153 uart1 {
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800154 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800155 atmel,pins =
156 <1 4 0x1 0x1 /* PB4 periph A with pullup */
157 1 5 0x1 0x0>; /* PB5 periph A */
158 };
159
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800160 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800161 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800162 <3 16 0x1 0x0>; /* PD16 periph A */
163 };
164
165 pinctrl_usart1_cts: usart1_cts-0 {
166 atmel,pins =
167 <3 17 0x1 0x0>; /* PD17 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800168 };
169 };
170
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800171 usart2 {
172 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800173 atmel,pins =
174 <1 6 0x1 0x1 /* PB6 periph A with pullup */
175 1 7 0x1 0x0>; /* PB7 periph A */
176 };
177
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800178 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800179 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800180 <2 9 0x2 0x0>; /* PC9 periph B */
181 };
182
183 pinctrl_usart2_cts: usart2_cts-0 {
184 atmel,pins =
185 <2 11 0x2 0x0>; /* PC11 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800186 };
187 };
188
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800189 usart3 {
190 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800191 atmel,pins =
192 <1 8 0x1 0x1 /* PB9 periph A with pullup */
193 1 9 0x1 0x0>; /* PB8 periph A */
194 };
195
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800196 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800197 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800198 <0 23 0x2 0x0>; /* PA23 periph B */
199 };
200
201 pinctrl_usart3_cts: usart3_cts-0 {
202 atmel,pins =
203 <0 24 0x2 0x0>; /* PA24 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800204 };
205 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800206
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800207 nand {
208 pinctrl_nand: nand-0 {
209 atmel,pins =
210 <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
211 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
212 };
213 };
214
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800215 macb {
216 pinctrl_macb_rmii: macb_rmii-0 {
217 atmel,pins =
218 <0 10 0x1 0x0 /* PA10 periph A */
219 0 11 0x1 0x0 /* PA11 periph A */
220 0 12 0x1 0x0 /* PA12 periph A */
221 0 13 0x1 0x0 /* PA13 periph A */
222 0 14 0x1 0x0 /* PA14 periph A */
223 0 15 0x1 0x0 /* PA15 periph A */
224 0 16 0x1 0x0 /* PA16 periph A */
225 0 17 0x1 0x0 /* PA17 periph A */
226 0 18 0x1 0x0 /* PA18 periph A */
227 0 19 0x1 0x0>; /* PA19 periph A */
228 };
229
230 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
231 atmel,pins =
232 <0 6 0x2 0x0 /* PA6 periph B */
233 0 7 0x2 0x0 /* PA7 periph B */
234 0 8 0x2 0x0 /* PA8 periph B */
235 0 9 0x2 0x0 /* PA9 periph B */
236 0 27 0x2 0x0 /* PA27 periph B */
237 0 28 0x2 0x0 /* PA28 periph B */
238 0 29 0x2 0x0 /* PA29 periph B */
239 0 30 0x2 0x0>; /* PA30 periph B */
240 };
241 };
242
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800243 pioA: gpio@fffff200 {
244 compatible = "atmel,at91rm9200-gpio";
245 reg = <0xfffff200 0x200>;
246 interrupts = <2 4 1>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100252
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800253 pioB: gpio@fffff400 {
254 compatible = "atmel,at91rm9200-gpio";
255 reg = <0xfffff400 0x200>;
256 interrupts = <3 4 1>;
257 #gpio-cells = <2>;
258 gpio-controller;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100262
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800263 pioC: gpio@fffff600 {
264 compatible = "atmel,at91rm9200-gpio";
265 reg = <0xfffff600 0x200>;
266 interrupts = <4 4 1>;
267 #gpio-cells = <2>;
268 gpio-controller;
269 interrupt-controller;
270 #interrupt-cells = <2>;
271 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100272
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800273 pioD: gpio@fffff800 {
274 compatible = "atmel,at91rm9200-gpio";
275 reg = <0xfffff800 0x200>;
276 interrupts = <5 4 1>;
277 #gpio-cells = <2>;
278 gpio-controller;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 };
282
283 pioE: gpio@fffffa00 {
284 compatible = "atmel,at91rm9200-gpio";
285 reg = <0xfffffa00 0x200>;
286 interrupts = <5 4 1>;
287 #gpio-cells = <2>;
288 gpio-controller;
289 interrupt-controller;
290 #interrupt-cells = <2>;
291 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100292 };
293
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200294 dbgu: serial@ffffee00 {
295 compatible = "atmel,at91sam9260-usart";
296 reg = <0xffffee00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200297 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_dbgu>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200300 status = "disabled";
301 };
302
303 usart0: serial@fff8c000 {
304 compatible = "atmel,at91sam9260-usart";
305 reg = <0xfff8c000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200306 interrupts = <7 4 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200307 atmel,use-dma-rx;
308 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800309 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800310 pinctrl-0 = <&pinctrl_usart0>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200311 status = "disabled";
312 };
313
314 usart1: serial@fff90000 {
315 compatible = "atmel,at91sam9260-usart";
316 reg = <0xfff90000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200317 interrupts = <8 4 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200318 atmel,use-dma-rx;
319 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800320 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800321 pinctrl-0 = <&pinctrl_usart1>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200322 status = "disabled";
323 };
324
325 usart2: serial@fff94000 {
326 compatible = "atmel,at91sam9260-usart";
327 reg = <0xfff94000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200328 interrupts = <9 4 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200329 atmel,use-dma-rx;
330 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800331 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800332 pinctrl-0 = <&pinctrl_usart2>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200333 status = "disabled";
334 };
335
336 usart3: serial@fff98000 {
337 compatible = "atmel,at91sam9260-usart";
338 reg = <0xfff98000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200339 interrupts = <10 4 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200340 atmel,use-dma-rx;
341 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800342 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800343 pinctrl-0 = <&pinctrl_usart3>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200344 status = "disabled";
345 };
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +0100346
347 macb0: ethernet@fffbc000 {
348 compatible = "cdns,at32ap7000-macb", "cdns,macb";
349 reg = <0xfffbc000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200350 interrupts = <25 4 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_macb_rmii>;
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +0100353 status = "disabled";
354 };
Maxime Ripard93b298b2012-05-11 15:35:38 +0200355
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200356 i2c0: i2c@fff84000 {
357 compatible = "atmel,at91sam9g10-i2c";
358 reg = <0xfff84000 0x100>;
359 interrupts = <12 4 6>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362 status = "disabled";
363 };
364
365 i2c1: i2c@fff88000 {
366 compatible = "atmel,at91sam9g10-i2c";
367 reg = <0xfff88000 0x100>;
368 interrupts = <13 4 6>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
372 };
373
Maxime Ripard93b298b2012-05-11 15:35:38 +0200374 adc0: adc@fffb0000 {
375 compatible = "atmel,at91sam9260-adc";
376 reg = <0xfffb0000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200377 interrupts = <20 4 0>;
Maxime Ripard93b298b2012-05-11 15:35:38 +0200378 atmel,adc-use-external-triggers;
379 atmel,adc-channels-used = <0xff>;
380 atmel,adc-vref = <3300>;
381 atmel,adc-num-channels = <8>;
382 atmel,adc-startup-time = <40>;
383 atmel,adc-channel-base = <0x30>;
384 atmel,adc-drdy-mask = <0x10000>;
385 atmel,adc-status-register = <0x1c>;
386 atmel,adc-trigger-register = <0x08>;
387
388 trigger@0 {
389 trigger-name = "external-rising";
390 trigger-value = <0x1>;
391 trigger-external;
392 };
393 trigger@1 {
394 trigger-name = "external-falling";
395 trigger-value = <0x2>;
396 trigger-external;
397 };
398
399 trigger@2 {
400 trigger-name = "external-any";
401 trigger-value = <0x3>;
402 trigger-external;
403 };
404
405 trigger@3 {
406 trigger-name = "continuous";
407 trigger-value = <0x6>;
408 };
409 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200410 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800411
412 nand0: nand@40000000 {
413 compatible = "atmel,at91rm9200-nand";
414 #address-cells = <1>;
415 #size-cells = <1>;
416 reg = <0x40000000 0x10000000
417 0xffffe200 0x200
418 >;
419 atmel,nand-addr-offset = <21>;
420 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800423 gpios = <&pioC 8 0
424 &pioC 14 0
425 0
426 >;
427 status = "disabled";
428 };
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800429
430 usb0: ohci@00700000 {
431 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
432 reg = <0x00700000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200433 interrupts = <22 4 2>;
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800434 status = "disabled";
435 };
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800436
437 usb1: ehci@00800000 {
438 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
439 reg = <0x00800000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200440 interrupts = <22 4 2>;
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800441 status = "disabled";
442 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200443 };
Jean-Christophe PLAGNIOL-VILLARD8f24bda2012-02-05 18:32:37 +0800444
445 i2c@0 {
446 compatible = "i2c-gpio";
447 gpios = <&pioA 20 0 /* sda */
448 &pioA 21 0 /* scl */
449 >;
450 i2c-gpio,sda-open-drain;
451 i2c-gpio,scl-open-drain;
452 i2c-gpio,delay-us = <5>; /* ~100 kHz */
453 #address-cells = <1>;
454 #size-cells = <0>;
455 status = "disabled";
456 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200457};