blob: 74eea2fbb4fe4776c02150b9f2fb8a9765f37373 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
Matt Carlson9e056c02012-02-13 15:20:17 +00007 * Copyright (C) 2005-2012 Broadcom Corporation.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * Firmware is:
Michael Chan49cabf42005-06-06 15:15:17 -070010 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
19#include <linux/module.h>
20#include <linux/moduleparam.h>
Matt Carlson6867c842010-07-11 09:31:44 +000021#include <linux/stringify.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
Arnaldo Carvalho de Melo14c85022005-12-27 02:43:12 -020027#include <linux/in.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/init.h>
Alexey Dobriyana6b7a402011-06-06 10:43:46 +000029#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
Matt Carlson3110f5f52010-12-06 08:28:50 +000036#include <linux/mdio.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <linux/mii.h>
Matt Carlson158d7ab2008-05-29 01:37:54 -070038#include <linux/phy.h>
Matt Carlsona9daf362008-05-25 23:49:44 -070039#include <linux/brcmphy.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
Michael Chan61487482005-09-05 17:53:19 -070044#include <linux/prefetch.h>
Tobias Klauserf9a5f7d2005-10-29 15:09:26 +020045#include <linux/dma-mapping.h>
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080046#include <linux/firmware.h>
Michael Chanaed93e02012-07-16 16:24:02 +000047#if IS_ENABLED(CONFIG_HWMON)
48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
50#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52#include <net/checksum.h>
Arnaldo Carvalho de Meloc9bdd4b2007-03-12 20:09:15 -030053#include <net/ip.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070054
Javier Martinez Canillas27fd9de2011-03-26 16:42:31 +000055#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056#include <asm/byteorder.h>
Javier Martinez Canillas27fd9de2011-03-26 16:42:31 +000057#include <linux/uaccess.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
David S. Miller49b6e95f2007-03-29 01:38:42 -070059#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070060#include <asm/idprom.h>
David S. Miller49b6e95f2007-03-29 01:38:42 -070061#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070062#endif
63
Matt Carlson63532392008-11-03 16:49:57 -080064#define BAR_0 0
65#define BAR_2 2
66
Linus Torvalds1da177e2005-04-16 15:20:36 -070067#include "tg3.h"
68
Joe Perches63c3a662011-04-26 08:12:10 +000069/* Functions & macros to verify TG3_FLAGS types */
70
71static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
72{
73 return test_bit(flag, bits);
74}
75
76static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
77{
78 set_bit(flag, bits);
79}
80
81static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
82{
83 clear_bit(flag, bits);
84}
85
86#define tg3_flag(tp, flag) \
87 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
88#define tg3_flag_set(tp, flag) \
89 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_clear(tp, flag) \
91 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
92
Linus Torvalds1da177e2005-04-16 15:20:36 -070093#define DRV_MODULE_NAME "tg3"
Matt Carlson6867c842010-07-11 09:31:44 +000094#define TG3_MAJ_NUM 3
Michael Chancac83e52012-07-29 19:15:45 +000095#define TG3_MIN_NUM 124
Matt Carlson6867c842010-07-11 09:31:44 +000096#define DRV_MODULE_VERSION \
97 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
Michael Chan7ae52892012-03-21 15:38:33 +000098#define DRV_MODULE_RELDATE "March 21, 2012"
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000100#define RESET_KIND_SHUTDOWN 0
101#define RESET_KIND_INIT 1
102#define RESET_KIND_SUSPEND 2
103
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104#define TG3_DEF_RX_MODE 0
105#define TG3_DEF_TX_MODE 0
106#define TG3_DEF_MSG_ENABLE \
107 (NETIF_MSG_DRV | \
108 NETIF_MSG_PROBE | \
109 NETIF_MSG_LINK | \
110 NETIF_MSG_TIMER | \
111 NETIF_MSG_IFDOWN | \
112 NETIF_MSG_IFUP | \
113 NETIF_MSG_RX_ERR | \
114 NETIF_MSG_TX_ERR)
115
Matt Carlson520b2752011-06-13 13:39:02 +0000116#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
117
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118/* length of time before we decide the hardware is borked,
119 * and dev->tx_timeout() should be called to fix the problem
120 */
Joe Perches63c3a662011-04-26 08:12:10 +0000121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122#define TG3_TX_TIMEOUT (5 * HZ)
123
124/* hardware minimum and maximum for a single frame's data payload */
125#define TG3_MIN_MTU 60
126#define TG3_MAX_MTU(tp) \
Joe Perches63c3a662011-04-26 08:12:10 +0000127 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
129/* These numbers seem to be hard coded in the NIC firmware somehow.
130 * You can't change the ring sizes, but you can change where you place
131 * them in the NIC onboard memory.
132 */
Matt Carlson7cb32cf2010-09-30 10:34:36 +0000133#define TG3_RX_STD_RING_SIZE(tp) \
Joe Perches63c3a662011-04-26 08:12:10 +0000134 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
Matt Carlsonde9f5232011-04-05 14:22:43 +0000135 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136#define TG3_DEF_RX_RING_PENDING 200
Matt Carlson7cb32cf2010-09-30 10:34:36 +0000137#define TG3_RX_JMB_RING_SIZE(tp) \
Joe Perches63c3a662011-04-26 08:12:10 +0000138 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
Matt Carlsonde9f5232011-04-05 14:22:43 +0000139 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140#define TG3_DEF_RX_JUMBO_RING_PENDING 100
141
142/* Do not place this n-ring entries value into the tp struct itself,
143 * we really want to expose these constants to GCC so that modulo et
144 * al. operations are done with shifts and masks instead of with
145 * hw multiply/modulo instructions. Another solution would be to
146 * replace things like '% foo' with '& (foo - 1)'.
147 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148
149#define TG3_TX_RING_SIZE 512
150#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
151
Matt Carlson2c49a442010-09-30 10:34:35 +0000152#define TG3_RX_STD_RING_BYTES(tp) \
153 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
154#define TG3_RX_JMB_RING_BYTES(tp) \
155 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
156#define TG3_RX_RCB_RING_BYTES(tp) \
Matt Carlson7cb32cf2010-09-30 10:34:36 +0000157 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
159 TG3_TX_RING_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
161
Matt Carlson287be122009-08-28 13:58:46 +0000162#define TG3_DMA_BYTE_ENAB 64
163
164#define TG3_RX_STD_DMA_SZ 1536
165#define TG3_RX_JMB_DMA_SZ 9046
166
167#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
168
169#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
170#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171
Matt Carlson2c49a442010-09-30 10:34:35 +0000172#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
173 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
Matt Carlson2b2cdb62009-11-13 13:03:48 +0000174
Matt Carlson2c49a442010-09-30 10:34:35 +0000175#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
176 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
Matt Carlson2b2cdb62009-11-13 13:03:48 +0000177
Matt Carlsond2757fc2010-04-12 06:58:27 +0000178/* Due to a hardware bug, the 5701 can only DMA to memory addresses
179 * that are at least dword aligned when used in PCIX mode. The driver
180 * works around this bug by double copying the packet. This workaround
181 * is built into the normal double copy length check for efficiency.
182 *
183 * However, the double copy is only necessary on those architectures
184 * where unaligned memory accesses are inefficient. For those architectures
185 * where unaligned memory accesses incur little penalty, we can reintegrate
186 * the 5701 in the normal rx path. Doing so saves a device structure
187 * dereference by hardcoding the double copy threshold in place.
188 */
189#define TG3_RX_COPY_THRESHOLD 256
190#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
191 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
192#else
193 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
194#endif
195
Matt Carlson81389f52011-08-31 11:44:49 +0000196#if (NET_IP_ALIGN != 0)
197#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
198#else
Eric Dumazet9205fd92011-11-18 06:47:01 +0000199#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
Matt Carlson81389f52011-08-31 11:44:49 +0000200#endif
201
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202/* minimum number of free TX descriptors required to wake up TX process */
Matt Carlsonf3f3f272009-08-28 14:03:21 +0000203#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
Matt Carlson55086ad2011-12-14 11:09:59 +0000204#define TG3_TX_BD_DMA_MAX_2K 2048
Matt Carlsona4cb4282011-12-14 11:09:58 +0000205#define TG3_TX_BD_DMA_MAX_4K 4096
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206
Matt Carlsonad829262008-11-21 17:16:16 -0800207#define TG3_RAW_IP_ALIGN 2
208
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000209#define TG3_FW_UPDATE_TIMEOUT_SEC 5
Matt Carlson21f76382012-02-22 12:35:21 +0000210#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000211
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -0800212#define FIRMWARE_TG3 "tigon/tg3.bin"
213#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
214#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
215
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216static char version[] __devinitdata =
Joe Perches05dbe002010-02-17 19:44:19 +0000217 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218
219MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
220MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
221MODULE_LICENSE("GPL");
222MODULE_VERSION(DRV_MODULE_VERSION);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -0800223MODULE_FIRMWARE(FIRMWARE_TG3);
224MODULE_FIRMWARE(FIRMWARE_TG3TSO);
225MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
226
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
228module_param(tg3_debug, int, 0);
229MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
230
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000231static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
Michael Chan126a3362006-09-27 16:03:07 -0700255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
Michael Chan126a3362006-09-27 16:03:07 -0700268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
Michael Chan676917d2006-12-07 00:20:22 -0800272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
Michael Chanb5d37722006-09-27 16:06:21 -0700280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
Matt Carlsond30cdd22007-10-07 23:28:35 -0700282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
Matt Carlson6c7af272007-10-21 16:12:02 -0700284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
Matt Carlson9936bcf2007-10-10 18:03:07 -0700285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
Matt Carlsonc88e6682008-11-03 16:49:18 -0800287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
Matt Carlson2befdce2009-08-28 12:28:45 +0000289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
Matt Carlson321d32a2008-11-21 17:22:19 -0800291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
Matt Carlson5e7ccf22009-08-25 10:08:42 +0000294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
Matt Carlson5001e2f2009-11-13 13:03:51 +0000295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
Matt Carlsonb0f75222010-01-20 16:58:11 +0000297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
Matt Carlson302b5002010-06-05 17:24:38 +0000303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
Matt Carlsonba1f3c72011-04-05 14:22:50 +0000304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
Greg KH02eca3f2012-07-12 15:39:44 +0000305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700306 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
307 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
308 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
309 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
310 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
311 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
312 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
Meelis Roos1dcb14d2011-05-25 05:43:47 +0000313 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700314 {}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315};
316
317MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
318
Andreas Mohr50da8592006-08-14 23:54:30 -0700319static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 const char string[ETH_GSTRING_LEN];
Matt Carlson48fa55a2011-04-13 11:05:06 +0000321} ethtool_stats_keys[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 { "rx_octets" },
323 { "rx_fragments" },
324 { "rx_ucast_packets" },
325 { "rx_mcast_packets" },
326 { "rx_bcast_packets" },
327 { "rx_fcs_errors" },
328 { "rx_align_errors" },
329 { "rx_xon_pause_rcvd" },
330 { "rx_xoff_pause_rcvd" },
331 { "rx_mac_ctrl_rcvd" },
332 { "rx_xoff_entered" },
333 { "rx_frame_too_long_errors" },
334 { "rx_jabbers" },
335 { "rx_undersize_packets" },
336 { "rx_in_length_errors" },
337 { "rx_out_length_errors" },
338 { "rx_64_or_less_octet_packets" },
339 { "rx_65_to_127_octet_packets" },
340 { "rx_128_to_255_octet_packets" },
341 { "rx_256_to_511_octet_packets" },
342 { "rx_512_to_1023_octet_packets" },
343 { "rx_1024_to_1522_octet_packets" },
344 { "rx_1523_to_2047_octet_packets" },
345 { "rx_2048_to_4095_octet_packets" },
346 { "rx_4096_to_8191_octet_packets" },
347 { "rx_8192_to_9022_octet_packets" },
348
349 { "tx_octets" },
350 { "tx_collisions" },
351
352 { "tx_xon_sent" },
353 { "tx_xoff_sent" },
354 { "tx_flow_control" },
355 { "tx_mac_errors" },
356 { "tx_single_collisions" },
357 { "tx_mult_collisions" },
358 { "tx_deferred" },
359 { "tx_excessive_collisions" },
360 { "tx_late_collisions" },
361 { "tx_collide_2times" },
362 { "tx_collide_3times" },
363 { "tx_collide_4times" },
364 { "tx_collide_5times" },
365 { "tx_collide_6times" },
366 { "tx_collide_7times" },
367 { "tx_collide_8times" },
368 { "tx_collide_9times" },
369 { "tx_collide_10times" },
370 { "tx_collide_11times" },
371 { "tx_collide_12times" },
372 { "tx_collide_13times" },
373 { "tx_collide_14times" },
374 { "tx_collide_15times" },
375 { "tx_ucast_packets" },
376 { "tx_mcast_packets" },
377 { "tx_bcast_packets" },
378 { "tx_carrier_sense_errors" },
379 { "tx_discards" },
380 { "tx_errors" },
381
382 { "dma_writeq_full" },
383 { "dma_write_prioq_full" },
384 { "rxbds_empty" },
385 { "rx_discards" },
386 { "rx_errors" },
387 { "rx_threshold_hit" },
388
389 { "dma_readq_full" },
390 { "dma_read_prioq_full" },
391 { "tx_comp_queue_full" },
392
393 { "ring_set_send_prod_index" },
394 { "ring_status_update" },
395 { "nic_irqs" },
396 { "nic_avoided_irqs" },
Matt Carlson4452d092011-05-19 12:12:51 +0000397 { "nic_tx_threshold_hit" },
398
399 { "mbuf_lwm_thresh_hit" },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400};
401
Matt Carlson48fa55a2011-04-13 11:05:06 +0000402#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
403
404
Andreas Mohr50da8592006-08-14 23:54:30 -0700405static const struct {
Michael Chan4cafd3f2005-05-29 14:56:34 -0700406 const char string[ETH_GSTRING_LEN];
Matt Carlson48fa55a2011-04-13 11:05:06 +0000407} ethtool_test_keys[] = {
Matt Carlson28a45952011-08-19 13:58:22 +0000408 { "nvram test (online) " },
409 { "link test (online) " },
410 { "register test (offline)" },
411 { "memory test (offline)" },
412 { "mac loopback test (offline)" },
413 { "phy loopback test (offline)" },
Matt Carlson941ec902011-08-19 13:58:23 +0000414 { "ext loopback test (offline)" },
Matt Carlson28a45952011-08-19 13:58:22 +0000415 { "interrupt test (offline)" },
Michael Chan4cafd3f2005-05-29 14:56:34 -0700416};
417
Matt Carlson48fa55a2011-04-13 11:05:06 +0000418#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
419
420
Michael Chanb401e9e2005-12-19 16:27:04 -0800421static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
422{
423 writel(val, tp->regs + off);
424}
425
426static u32 tg3_read32(struct tg3 *tp, u32 off)
427{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000428 return readl(tp->regs + off);
Michael Chanb401e9e2005-12-19 16:27:04 -0800429}
430
Matt Carlson0d3031d2007-10-10 18:02:43 -0700431static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
432{
433 writel(val, tp->aperegs + off);
434}
435
436static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
437{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000438 return readl(tp->aperegs + off);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700439}
440
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
442{
Michael Chan68929142005-08-09 20:17:14 -0700443 unsigned long flags;
444
445 spin_lock_irqsave(&tp->indirect_lock, flags);
Michael Chan1ee582d2005-08-09 20:16:46 -0700446 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
447 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
Michael Chan68929142005-08-09 20:17:14 -0700448 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Michael Chan1ee582d2005-08-09 20:16:46 -0700449}
450
451static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
452{
453 writel(val, tp->regs + off);
454 readl(tp->regs + off);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455}
456
Michael Chan68929142005-08-09 20:17:14 -0700457static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
458{
459 unsigned long flags;
460 u32 val;
461
462 spin_lock_irqsave(&tp->indirect_lock, flags);
463 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
464 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
465 spin_unlock_irqrestore(&tp->indirect_lock, flags);
466 return val;
467}
468
469static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
470{
471 unsigned long flags;
472
473 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
474 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
475 TG3_64BIT_REG_LOW, val);
476 return;
477 }
Matt Carlson66711e62009-11-13 13:03:49 +0000478 if (off == TG3_RX_STD_PROD_IDX_REG) {
Michael Chan68929142005-08-09 20:17:14 -0700479 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
480 TG3_64BIT_REG_LOW, val);
481 return;
482 }
483
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
486 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
487 spin_unlock_irqrestore(&tp->indirect_lock, flags);
488
489 /* In indirect mode when disabling interrupts, we also need
490 * to clear the interrupt bit in the GRC local ctrl register.
491 */
492 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
493 (val == 0x1)) {
494 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
495 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
496 }
497}
498
499static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
500{
501 unsigned long flags;
502 u32 val;
503
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
506 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 return val;
509}
510
Michael Chanb401e9e2005-12-19 16:27:04 -0800511/* usec_wait specifies the wait time in usec when writing to certain registers
512 * where it is unsafe to read back the register without some delay.
513 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
514 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
515 */
516static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517{
Joe Perches63c3a662011-04-26 08:12:10 +0000518 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
Michael Chanb401e9e2005-12-19 16:27:04 -0800519 /* Non-posted methods */
520 tp->write32(tp, off, val);
521 else {
522 /* Posted method */
523 tg3_write32(tp, off, val);
524 if (usec_wait)
525 udelay(usec_wait);
526 tp->read32(tp, off);
527 }
528 /* Wait again after the read for the posted method to guarantee that
529 * the wait time is met.
530 */
531 if (usec_wait)
532 udelay(usec_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533}
534
Michael Chan09ee9292005-08-09 20:17:00 -0700535static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
536{
537 tp->write32_mbox(tp, off, val);
Joe Perches63c3a662011-04-26 08:12:10 +0000538 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
Michael Chan68929142005-08-09 20:17:14 -0700539 tp->read32_mbox(tp, off);
Michael Chan09ee9292005-08-09 20:17:00 -0700540}
541
Michael Chan20094932005-08-09 20:16:32 -0700542static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543{
544 void __iomem *mbox = tp->regs + off;
545 writel(val, mbox);
Joe Perches63c3a662011-04-26 08:12:10 +0000546 if (tg3_flag(tp, TXD_MBOX_HWBUG))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 writel(val, mbox);
Joe Perches63c3a662011-04-26 08:12:10 +0000548 if (tg3_flag(tp, MBOX_WRITE_REORDER))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549 readl(mbox);
550}
551
Michael Chanb5d37722006-09-27 16:06:21 -0700552static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
553{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000554 return readl(tp->regs + off + GRCMBOX_BASE);
Michael Chanb5d37722006-09-27 16:06:21 -0700555}
556
557static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
558{
559 writel(val, tp->regs + off + GRCMBOX_BASE);
560}
561
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000562#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
Michael Chan09ee9292005-08-09 20:17:00 -0700563#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000564#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
565#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
566#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
Michael Chan20094932005-08-09 20:16:32 -0700567
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000568#define tw32(reg, val) tp->write32(tp, reg, val)
569#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
570#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
571#define tr32(reg) tp->read32(tp, reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572
573static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
574{
Michael Chan68929142005-08-09 20:17:14 -0700575 unsigned long flags;
576
Matt Carlson6ff6f812011-05-19 12:12:54 +0000577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
Michael Chanb5d37722006-09-27 16:06:21 -0700578 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
579 return;
580
Michael Chan68929142005-08-09 20:17:14 -0700581 spin_lock_irqsave(&tp->indirect_lock, flags);
Joe Perches63c3a662011-04-26 08:12:10 +0000582 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
Michael Chanbbadf502006-04-06 21:46:34 -0700583 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
584 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585
Michael Chanbbadf502006-04-06 21:46:34 -0700586 /* Always leave this as zero. */
587 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
588 } else {
589 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
590 tw32_f(TG3PCI_MEM_WIN_DATA, val);
591
592 /* Always leave this as zero. */
593 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
594 }
Michael Chan68929142005-08-09 20:17:14 -0700595 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596}
597
598static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
599{
Michael Chan68929142005-08-09 20:17:14 -0700600 unsigned long flags;
601
Matt Carlson6ff6f812011-05-19 12:12:54 +0000602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
Michael Chanb5d37722006-09-27 16:06:21 -0700603 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
604 *val = 0;
605 return;
606 }
607
Michael Chan68929142005-08-09 20:17:14 -0700608 spin_lock_irqsave(&tp->indirect_lock, flags);
Joe Perches63c3a662011-04-26 08:12:10 +0000609 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
Michael Chanbbadf502006-04-06 21:46:34 -0700610 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
611 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612
Michael Chanbbadf502006-04-06 21:46:34 -0700613 /* Always leave this as zero. */
614 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
615 } else {
616 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
617 *val = tr32(TG3PCI_MEM_WIN_DATA);
618
619 /* Always leave this as zero. */
620 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
621 }
Michael Chan68929142005-08-09 20:17:14 -0700622 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623}
624
Matt Carlson0d3031d2007-10-10 18:02:43 -0700625static void tg3_ape_lock_init(struct tg3 *tp)
626{
627 int i;
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000628 u32 regbase, bit;
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000629
630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
631 regbase = TG3_APE_LOCK_GRANT;
632 else
633 regbase = TG3_APE_PER_LOCK_GRANT;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700634
635 /* Make sure the driver hasn't any stale locks. */
Matt Carlson78f94dc2011-11-04 09:14:58 +0000636 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
637 switch (i) {
638 case TG3_APE_LOCK_PHY0:
639 case TG3_APE_LOCK_PHY1:
640 case TG3_APE_LOCK_PHY2:
641 case TG3_APE_LOCK_PHY3:
642 bit = APE_LOCK_GRANT_DRIVER;
643 break;
644 default:
645 if (!tp->pci_fn)
646 bit = APE_LOCK_GRANT_DRIVER;
647 else
648 bit = 1 << tp->pci_fn;
649 }
650 tg3_ape_write32(tp, regbase + 4 * i, bit);
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000651 }
652
Matt Carlson0d3031d2007-10-10 18:02:43 -0700653}
654
655static int tg3_ape_lock(struct tg3 *tp, int locknum)
656{
657 int i, off;
658 int ret = 0;
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000659 u32 status, req, gnt, bit;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700660
Joe Perches63c3a662011-04-26 08:12:10 +0000661 if (!tg3_flag(tp, ENABLE_APE))
Matt Carlson0d3031d2007-10-10 18:02:43 -0700662 return 0;
663
664 switch (locknum) {
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000665 case TG3_APE_LOCK_GPIO:
666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
667 return 0;
Matt Carlson33f401a2010-04-05 10:19:27 +0000668 case TG3_APE_LOCK_GRC:
669 case TG3_APE_LOCK_MEM:
Matt Carlson78f94dc2011-11-04 09:14:58 +0000670 if (!tp->pci_fn)
671 bit = APE_LOCK_REQ_DRIVER;
672 else
673 bit = 1 << tp->pci_fn;
Matt Carlson33f401a2010-04-05 10:19:27 +0000674 break;
Michael Chan8151ad52012-07-29 19:15:41 +0000675 case TG3_APE_LOCK_PHY0:
676 case TG3_APE_LOCK_PHY1:
677 case TG3_APE_LOCK_PHY2:
678 case TG3_APE_LOCK_PHY3:
679 bit = APE_LOCK_REQ_DRIVER;
680 break;
Matt Carlson33f401a2010-04-05 10:19:27 +0000681 default:
682 return -EINVAL;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700683 }
684
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
686 req = TG3_APE_LOCK_REQ;
687 gnt = TG3_APE_LOCK_GRANT;
688 } else {
689 req = TG3_APE_PER_LOCK_REQ;
690 gnt = TG3_APE_PER_LOCK_GRANT;
691 }
692
Matt Carlson0d3031d2007-10-10 18:02:43 -0700693 off = 4 * locknum;
694
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000695 tg3_ape_write32(tp, req + off, bit);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700696
697 /* Wait for up to 1 millisecond to acquire lock. */
698 for (i = 0; i < 100; i++) {
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000699 status = tg3_ape_read32(tp, gnt + off);
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000700 if (status == bit)
Matt Carlson0d3031d2007-10-10 18:02:43 -0700701 break;
702 udelay(10);
703 }
704
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000705 if (status != bit) {
Matt Carlson0d3031d2007-10-10 18:02:43 -0700706 /* Revoke the lock request. */
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000707 tg3_ape_write32(tp, gnt + off, bit);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700708 ret = -EBUSY;
709 }
710
711 return ret;
712}
713
714static void tg3_ape_unlock(struct tg3 *tp, int locknum)
715{
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000716 u32 gnt, bit;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700717
Joe Perches63c3a662011-04-26 08:12:10 +0000718 if (!tg3_flag(tp, ENABLE_APE))
Matt Carlson0d3031d2007-10-10 18:02:43 -0700719 return;
720
721 switch (locknum) {
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000722 case TG3_APE_LOCK_GPIO:
723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
724 return;
Matt Carlson33f401a2010-04-05 10:19:27 +0000725 case TG3_APE_LOCK_GRC:
726 case TG3_APE_LOCK_MEM:
Matt Carlson78f94dc2011-11-04 09:14:58 +0000727 if (!tp->pci_fn)
728 bit = APE_LOCK_GRANT_DRIVER;
729 else
730 bit = 1 << tp->pci_fn;
Matt Carlson33f401a2010-04-05 10:19:27 +0000731 break;
Michael Chan8151ad52012-07-29 19:15:41 +0000732 case TG3_APE_LOCK_PHY0:
733 case TG3_APE_LOCK_PHY1:
734 case TG3_APE_LOCK_PHY2:
735 case TG3_APE_LOCK_PHY3:
736 bit = APE_LOCK_GRANT_DRIVER;
737 break;
Matt Carlson33f401a2010-04-05 10:19:27 +0000738 default:
739 return;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700740 }
741
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000742 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
743 gnt = TG3_APE_LOCK_GRANT;
744 else
745 gnt = TG3_APE_PER_LOCK_GRANT;
746
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000747 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700748}
749
Matt Carlsonb65a3722012-07-16 16:24:00 +0000750static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000751{
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000752 u32 apedata;
753
Matt Carlsonb65a3722012-07-16 16:24:00 +0000754 while (timeout_us) {
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000755 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
Matt Carlsonb65a3722012-07-16 16:24:00 +0000756 return -EBUSY;
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000757
758 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000759 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
760 break;
761
Matt Carlsonb65a3722012-07-16 16:24:00 +0000762 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763
764 udelay(10);
765 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000766 }
767
Matt Carlsonb65a3722012-07-16 16:24:00 +0000768 return timeout_us ? 0 : -EBUSY;
769}
770
Matt Carlsoncf8d55a2012-07-16 16:24:01 +0000771static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
772{
773 u32 i, apedata;
774
775 for (i = 0; i < timeout_us / 10; i++) {
776 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
777
778 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
779 break;
780
781 udelay(10);
782 }
783
784 return i == timeout_us / 10;
785}
786
787int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, u32 len)
788{
789 int err;
790 u32 i, bufoff, msgoff, maxlen, apedata;
791
792 if (!tg3_flag(tp, APE_HAS_NCSI))
793 return 0;
794
795 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
796 if (apedata != APE_SEG_SIG_MAGIC)
797 return -ENODEV;
798
799 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
800 if (!(apedata & APE_FW_STATUS_READY))
801 return -EAGAIN;
802
803 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
804 TG3_APE_SHMEM_BASE;
805 msgoff = bufoff + 2 * sizeof(u32);
806 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
807
808 while (len) {
809 u32 length;
810
811 /* Cap xfer sizes to scratchpad limits. */
812 length = (len > maxlen) ? maxlen : len;
813 len -= length;
814
815 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
816 if (!(apedata & APE_FW_STATUS_READY))
817 return -EAGAIN;
818
819 /* Wait for up to 1 msec for APE to service previous event. */
820 err = tg3_ape_event_lock(tp, 1000);
821 if (err)
822 return err;
823
824 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
825 APE_EVENT_STATUS_SCRTCHPD_READ |
826 APE_EVENT_STATUS_EVENT_PENDING;
827 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
828
829 tg3_ape_write32(tp, bufoff, base_off);
830 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
831
832 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
833 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
834
835 base_off += length;
836
837 if (tg3_ape_wait_for_event(tp, 30000))
838 return -EAGAIN;
839
840 for (i = 0; length; i += 4, length -= 4) {
841 u32 val = tg3_ape_read32(tp, msgoff + i);
842 memcpy(data, &val, sizeof(u32));
843 data++;
844 }
845 }
846
847 return 0;
848}
849
Matt Carlsonb65a3722012-07-16 16:24:00 +0000850static int tg3_ape_send_event(struct tg3 *tp, u32 event)
851{
852 int err;
853 u32 apedata;
854
855 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
856 if (apedata != APE_SEG_SIG_MAGIC)
857 return -EAGAIN;
858
859 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
860 if (!(apedata & APE_FW_STATUS_READY))
861 return -EAGAIN;
862
863 /* Wait for up to 1 millisecond for APE to service previous event. */
864 err = tg3_ape_event_lock(tp, 1000);
865 if (err)
866 return err;
867
868 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
869 event | APE_EVENT_STATUS_EVENT_PENDING);
870
871 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
872 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
873
874 return 0;
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000875}
876
877static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
878{
879 u32 event;
880 u32 apedata;
881
882 if (!tg3_flag(tp, ENABLE_APE))
883 return;
884
885 switch (kind) {
886 case RESET_KIND_INIT:
887 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
888 APE_HOST_SEG_SIG_MAGIC);
889 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
890 APE_HOST_SEG_LEN_MAGIC);
891 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
892 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
893 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
894 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
895 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
896 APE_HOST_BEHAV_NO_PHYLOCK);
897 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
898 TG3_APE_HOST_DRVR_STATE_START);
899
900 event = APE_EVENT_STATUS_STATE_START;
901 break;
902 case RESET_KIND_SHUTDOWN:
903 /* With the interface we are currently using,
904 * APE does not track driver state. Wiping
905 * out the HOST SEGMENT SIGNATURE forces
906 * the APE to assume OS absent status.
907 */
908 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
909
910 if (device_may_wakeup(&tp->pdev->dev) &&
911 tg3_flag(tp, WOL_ENABLE)) {
912 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
913 TG3_APE_HOST_WOL_SPEED_AUTO);
914 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
915 } else
916 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
917
918 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
919
920 event = APE_EVENT_STATUS_STATE_UNLOAD;
921 break;
922 case RESET_KIND_SUSPEND:
923 event = APE_EVENT_STATUS_STATE_SUSPEND;
924 break;
925 default:
926 return;
927 }
928
929 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
930
931 tg3_ape_send_event(tp, event);
932}
933
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934static void tg3_disable_ints(struct tg3 *tp)
935{
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000936 int i;
937
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 tw32(TG3PCI_MISC_HOST_CTRL,
939 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000940 for (i = 0; i < tp->irq_max; i++)
941 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942}
943
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944static void tg3_enable_ints(struct tg3 *tp)
945{
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000946 int i;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000947
Michael Chanbbe832c2005-06-24 20:20:04 -0700948 tp->irq_sync = 0;
949 wmb();
950
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951 tw32(TG3PCI_MISC_HOST_CTRL,
952 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000953
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000954 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000955 for (i = 0; i < tp->irq_cnt; i++) {
956 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000957
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000958 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
Joe Perches63c3a662011-04-26 08:12:10 +0000959 if (tg3_flag(tp, 1SHOT_MSI))
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000960 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
961
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000962 tp->coal_now |= tnapi->coal_now;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000963 }
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000964
965 /* Force an initial interrupt */
Joe Perches63c3a662011-04-26 08:12:10 +0000966 if (!tg3_flag(tp, TAGGED_STATUS) &&
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000967 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
968 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
969 else
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000970 tw32(HOSTCC_MODE, tp->coal_now);
971
972 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973}
974
Matt Carlson17375d22009-08-28 14:02:18 +0000975static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
Michael Chan04237dd2005-04-25 15:17:17 -0700976{
Matt Carlson17375d22009-08-28 14:02:18 +0000977 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +0000978 struct tg3_hw_status *sblk = tnapi->hw_status;
Michael Chan04237dd2005-04-25 15:17:17 -0700979 unsigned int work_exists = 0;
980
981 /* check for phy events */
Joe Perches63c3a662011-04-26 08:12:10 +0000982 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
Michael Chan04237dd2005-04-25 15:17:17 -0700983 if (sblk->status & SD_STATUS_LINK_CHG)
984 work_exists = 1;
985 }
Matt Carlsonf891ea12012-04-24 13:37:01 +0000986
987 /* check for TX work to do */
988 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
989 work_exists = 1;
990
991 /* check for RX work to do */
992 if (tnapi->rx_rcb_prod_idx &&
Matt Carlson8d9d7cf2009-09-01 13:19:05 +0000993 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
Michael Chan04237dd2005-04-25 15:17:17 -0700994 work_exists = 1;
995
996 return work_exists;
997}
998
Matt Carlson17375d22009-08-28 14:02:18 +0000999/* tg3_int_reenable
Michael Chan04237dd2005-04-25 15:17:17 -07001000 * similar to tg3_enable_ints, but it accurately determines whether there
1001 * is new work pending and can return without flushing the PIO write
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001002 * which reenables interrupts
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 */
Matt Carlson17375d22009-08-28 14:02:18 +00001004static void tg3_int_reenable(struct tg3_napi *tnapi)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005{
Matt Carlson17375d22009-08-28 14:02:18 +00001006 struct tg3 *tp = tnapi->tp;
1007
Matt Carlson898a56f2009-08-28 14:02:40 +00001008 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 mmiowb();
1010
David S. Millerfac9b832005-05-18 22:46:34 -07001011 /* When doing tagged status, this work check is unnecessary.
1012 * The last_tag we write above tells the chip which piece of
1013 * work we've completed.
1014 */
Joe Perches63c3a662011-04-26 08:12:10 +00001015 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
Michael Chan04237dd2005-04-25 15:17:17 -07001016 tw32(HOSTCC_MODE, tp->coalesce_mode |
Matt Carlsonfd2ce372009-09-01 12:51:13 +00001017 HOSTCC_MODE_ENABLE | tnapi->coal_now);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018}
1019
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020static void tg3_switch_clocks(struct tg3 *tp)
1021{
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00001022 u32 clock_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001023 u32 orig_clock_ctrl;
1024
Joe Perches63c3a662011-04-26 08:12:10 +00001025 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
Michael Chan4cf78e42005-07-25 12:29:19 -07001026 return;
1027
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00001028 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1029
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030 orig_clock_ctrl = clock_ctrl;
1031 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1032 CLOCK_CTRL_CLKRUN_OENABLE |
1033 0x1f);
1034 tp->pci_clock_ctrl = clock_ctrl;
1035
Joe Perches63c3a662011-04-26 08:12:10 +00001036 if (tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
Michael Chanb401e9e2005-12-19 16:27:04 -08001038 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1039 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040 }
1041 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
Michael Chanb401e9e2005-12-19 16:27:04 -08001042 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1043 clock_ctrl |
1044 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1045 40);
1046 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1047 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1048 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049 }
Michael Chanb401e9e2005-12-19 16:27:04 -08001050 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051}
1052
1053#define PHY_BUSY_LOOPS 5000
1054
1055static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1056{
1057 u32 frame_val;
1058 unsigned int loops;
1059 int ret;
1060
1061 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1062 tw32_f(MAC_MI_MODE,
1063 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1064 udelay(80);
1065 }
1066
Michael Chan8151ad52012-07-29 19:15:41 +00001067 tg3_ape_lock(tp, tp->phy_ape_lock);
1068
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069 *val = 0x0;
1070
Matt Carlson882e9792009-09-01 13:21:36 +00001071 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072 MI_COM_PHY_ADDR_MASK);
1073 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1074 MI_COM_REG_ADDR_MASK);
1075 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001076
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 tw32_f(MAC_MI_COM, frame_val);
1078
1079 loops = PHY_BUSY_LOOPS;
1080 while (loops != 0) {
1081 udelay(10);
1082 frame_val = tr32(MAC_MI_COM);
1083
1084 if ((frame_val & MI_COM_BUSY) == 0) {
1085 udelay(5);
1086 frame_val = tr32(MAC_MI_COM);
1087 break;
1088 }
1089 loops -= 1;
1090 }
1091
1092 ret = -EBUSY;
1093 if (loops != 0) {
1094 *val = frame_val & MI_COM_DATA_MASK;
1095 ret = 0;
1096 }
1097
1098 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1099 tw32_f(MAC_MI_MODE, tp->mi_mode);
1100 udelay(80);
1101 }
1102
Michael Chan8151ad52012-07-29 19:15:41 +00001103 tg3_ape_unlock(tp, tp->phy_ape_lock);
1104
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 return ret;
1106}
1107
1108static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1109{
1110 u32 frame_val;
1111 unsigned int loops;
1112 int ret;
1113
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001114 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
Matt Carlson221c5632011-06-13 13:39:01 +00001115 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
Michael Chanb5d37722006-09-27 16:06:21 -07001116 return 0;
1117
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1119 tw32_f(MAC_MI_MODE,
1120 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1121 udelay(80);
1122 }
1123
Michael Chan8151ad52012-07-29 19:15:41 +00001124 tg3_ape_lock(tp, tp->phy_ape_lock);
1125
Matt Carlson882e9792009-09-01 13:21:36 +00001126 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
Linus Torvalds1da177e2005-04-16 15:20:36 -07001127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (val & MI_COM_DATA_MASK);
1131 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001132
Linus Torvalds1da177e2005-04-16 15:20:36 -07001133 tw32_f(MAC_MI_COM, frame_val);
1134
1135 loops = PHY_BUSY_LOOPS;
1136 while (loops != 0) {
1137 udelay(10);
1138 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1140 udelay(5);
1141 frame_val = tr32(MAC_MI_COM);
1142 break;
1143 }
1144 loops -= 1;
1145 }
1146
1147 ret = -EBUSY;
1148 if (loops != 0)
1149 ret = 0;
1150
1151 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1152 tw32_f(MAC_MI_MODE, tp->mi_mode);
1153 udelay(80);
1154 }
1155
Michael Chan8151ad52012-07-29 19:15:41 +00001156 tg3_ape_unlock(tp, tp->phy_ape_lock);
1157
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158 return ret;
1159}
1160
Matt Carlsonb0988c12011-04-20 07:57:39 +00001161static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1162{
1163 int err;
1164
1165 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1166 if (err)
1167 goto done;
1168
1169 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1170 if (err)
1171 goto done;
1172
1173 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1174 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1175 if (err)
1176 goto done;
1177
1178 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1179
1180done:
1181 return err;
1182}
1183
1184static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1185{
1186 int err;
1187
1188 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1189 if (err)
1190 goto done;
1191
1192 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1193 if (err)
1194 goto done;
1195
1196 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1197 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1198 if (err)
1199 goto done;
1200
1201 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1202
1203done:
1204 return err;
1205}
1206
1207static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1208{
1209 int err;
1210
1211 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1212 if (!err)
1213 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1214
1215 return err;
1216}
1217
1218static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1219{
1220 int err;
1221
1222 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1223 if (!err)
1224 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1225
1226 return err;
1227}
1228
Matt Carlson15ee95c2011-04-20 07:57:40 +00001229static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1230{
1231 int err;
1232
1233 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1234 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1235 MII_TG3_AUXCTL_SHDWSEL_MISC);
1236 if (!err)
1237 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1238
1239 return err;
1240}
1241
Matt Carlsonb4bd2922011-04-20 07:57:41 +00001242static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1243{
1244 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1245 set |= MII_TG3_AUXCTL_MISC_WREN;
1246
1247 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1248}
1249
Matt Carlson1d36ba42011-04-20 07:57:42 +00001250#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1251 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1252 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1253 MII_TG3_AUXCTL_ACTL_TX_6DB)
1254
1255#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1256 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1257 MII_TG3_AUXCTL_ACTL_TX_6DB);
1258
Matt Carlson95e28692008-05-25 23:44:14 -07001259static int tg3_bmcr_reset(struct tg3 *tp)
1260{
1261 u32 phy_control;
1262 int limit, err;
1263
1264 /* OK, reset it, and poll the BMCR_RESET bit until it
1265 * clears or we time out.
1266 */
1267 phy_control = BMCR_RESET;
1268 err = tg3_writephy(tp, MII_BMCR, phy_control);
1269 if (err != 0)
1270 return -EBUSY;
1271
1272 limit = 5000;
1273 while (limit--) {
1274 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1275 if (err != 0)
1276 return -EBUSY;
1277
1278 if ((phy_control & BMCR_RESET) == 0) {
1279 udelay(40);
1280 break;
1281 }
1282 udelay(10);
1283 }
Roel Kluind4675b52009-02-12 16:33:27 -08001284 if (limit < 0)
Matt Carlson95e28692008-05-25 23:44:14 -07001285 return -EBUSY;
1286
1287 return 0;
1288}
1289
Matt Carlson158d7ab2008-05-29 01:37:54 -07001290static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1291{
Francois Romieu3d165432009-01-19 16:56:50 -08001292 struct tg3 *tp = bp->priv;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001293 u32 val;
1294
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001295 spin_lock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001296
1297 if (tg3_readphy(tp, reg, &val))
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001298 val = -EIO;
1299
1300 spin_unlock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001301
1302 return val;
1303}
1304
1305static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1306{
Francois Romieu3d165432009-01-19 16:56:50 -08001307 struct tg3 *tp = bp->priv;
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001308 u32 ret = 0;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001309
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001310 spin_lock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001311
1312 if (tg3_writephy(tp, reg, val))
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001313 ret = -EIO;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001314
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001315 spin_unlock_bh(&tp->lock);
1316
1317 return ret;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001318}
1319
1320static int tg3_mdio_reset(struct mii_bus *bp)
1321{
1322 return 0;
1323}
1324
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001325static void tg3_mdio_config_5785(struct tg3 *tp)
Matt Carlsona9daf362008-05-25 23:49:44 -07001326{
1327 u32 val;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001328 struct phy_device *phydev;
Matt Carlsona9daf362008-05-25 23:49:44 -07001329
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001330 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001331 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
Matt Carlson6a443a02010-02-17 15:17:04 +00001332 case PHY_ID_BCM50610:
1333 case PHY_ID_BCM50610M:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001334 val = MAC_PHYCFG2_50610_LED_MODES;
1335 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001336 case PHY_ID_BCMAC131:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001337 val = MAC_PHYCFG2_AC131_LED_MODES;
1338 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001339 case PHY_ID_RTL8211C:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001340 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1341 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001342 case PHY_ID_RTL8201E:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001343 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1344 break;
1345 default:
Matt Carlsona9daf362008-05-25 23:49:44 -07001346 return;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001347 }
1348
1349 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1350 tw32(MAC_PHYCFG2, val);
1351
1352 val = tr32(MAC_PHYCFG1);
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001353 val &= ~(MAC_PHYCFG1_RGMII_INT |
1354 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1355 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001356 tw32(MAC_PHYCFG1, val);
1357
1358 return;
1359 }
1360
Joe Perches63c3a662011-04-26 08:12:10 +00001361 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001362 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1363 MAC_PHYCFG2_FMODE_MASK_MASK |
1364 MAC_PHYCFG2_GMODE_MASK_MASK |
1365 MAC_PHYCFG2_ACT_MASK_MASK |
1366 MAC_PHYCFG2_QUAL_MASK_MASK |
1367 MAC_PHYCFG2_INBAND_ENABLE;
1368
1369 tw32(MAC_PHYCFG2, val);
Matt Carlsona9daf362008-05-25 23:49:44 -07001370
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001371 val = tr32(MAC_PHYCFG1);
1372 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1373 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
Joe Perches63c3a662011-04-26 08:12:10 +00001374 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1375 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001376 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
Joe Perches63c3a662011-04-26 08:12:10 +00001377 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001378 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1379 }
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001380 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1381 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1382 tw32(MAC_PHYCFG1, val);
Matt Carlsona9daf362008-05-25 23:49:44 -07001383
Matt Carlsona9daf362008-05-25 23:49:44 -07001384 val = tr32(MAC_EXT_RGMII_MODE);
1385 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1386 MAC_RGMII_MODE_RX_QUALITY |
1387 MAC_RGMII_MODE_RX_ACTIVITY |
1388 MAC_RGMII_MODE_RX_ENG_DET |
1389 MAC_RGMII_MODE_TX_ENABLE |
1390 MAC_RGMII_MODE_TX_LOWPWR |
1391 MAC_RGMII_MODE_TX_RESET);
Joe Perches63c3a662011-04-26 08:12:10 +00001392 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1393 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001394 val |= MAC_RGMII_MODE_RX_INT_B |
1395 MAC_RGMII_MODE_RX_QUALITY |
1396 MAC_RGMII_MODE_RX_ACTIVITY |
1397 MAC_RGMII_MODE_RX_ENG_DET;
Joe Perches63c3a662011-04-26 08:12:10 +00001398 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001399 val |= MAC_RGMII_MODE_TX_ENABLE |
1400 MAC_RGMII_MODE_TX_LOWPWR |
1401 MAC_RGMII_MODE_TX_RESET;
1402 }
1403 tw32(MAC_EXT_RGMII_MODE, val);
1404}
1405
Matt Carlson158d7ab2008-05-29 01:37:54 -07001406static void tg3_mdio_start(struct tg3 *tp)
1407{
Matt Carlson158d7ab2008-05-29 01:37:54 -07001408 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1409 tw32_f(MAC_MI_MODE, tp->mi_mode);
1410 udelay(80);
Matt Carlsona9daf362008-05-25 23:49:44 -07001411
Joe Perches63c3a662011-04-26 08:12:10 +00001412 if (tg3_flag(tp, MDIOBUS_INITED) &&
Matt Carlson9ea48182010-02-17 15:17:01 +00001413 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1414 tg3_mdio_config_5785(tp);
1415}
1416
1417static int tg3_mdio_init(struct tg3 *tp)
1418{
1419 int i;
1420 u32 reg;
1421 struct phy_device *phydev;
1422
Joe Perches63c3a662011-04-26 08:12:10 +00001423 if (tg3_flag(tp, 5717_PLUS)) {
Matt Carlson9c7df912010-06-05 17:24:36 +00001424 u32 is_serdes;
Matt Carlson882e9792009-09-01 13:21:36 +00001425
Matt Carlson69f11c92011-07-13 09:27:30 +00001426 tp->phy_addr = tp->pci_fn + 1;
Matt Carlson882e9792009-09-01 13:21:36 +00001427
Matt Carlsond1ec96a2010-01-12 10:11:38 +00001428 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1429 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1430 else
1431 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1432 TG3_CPMU_PHY_STRAP_IS_SERDES;
Matt Carlson882e9792009-09-01 13:21:36 +00001433 if (is_serdes)
1434 tp->phy_addr += 7;
1435 } else
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001436 tp->phy_addr = TG3_PHY_MII_ADDR;
Matt Carlson882e9792009-09-01 13:21:36 +00001437
Matt Carlson158d7ab2008-05-29 01:37:54 -07001438 tg3_mdio_start(tp);
1439
Joe Perches63c3a662011-04-26 08:12:10 +00001440 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
Matt Carlson158d7ab2008-05-29 01:37:54 -07001441 return 0;
1442
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001443 tp->mdio_bus = mdiobus_alloc();
1444 if (tp->mdio_bus == NULL)
1445 return -ENOMEM;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001446
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001447 tp->mdio_bus->name = "tg3 mdio bus";
1448 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
Matt Carlson158d7ab2008-05-29 01:37:54 -07001449 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001450 tp->mdio_bus->priv = tp;
1451 tp->mdio_bus->parent = &tp->pdev->dev;
1452 tp->mdio_bus->read = &tg3_mdio_read;
1453 tp->mdio_bus->write = &tg3_mdio_write;
1454 tp->mdio_bus->reset = &tg3_mdio_reset;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001455 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001456 tp->mdio_bus->irq = &tp->mdio_irq[0];
Matt Carlson158d7ab2008-05-29 01:37:54 -07001457
1458 for (i = 0; i < PHY_MAX_ADDR; i++)
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001459 tp->mdio_bus->irq[i] = PHY_POLL;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001460
1461 /* The bus registration will look for all the PHYs on the mdio bus.
1462 * Unfortunately, it does not ensure the PHY is powered up before
1463 * accessing the PHY ID registers. A chip reset is the
1464 * quickest way to bring the device back to an operational state..
1465 */
1466 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1467 tg3_bmcr_reset(tp);
1468
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001469 i = mdiobus_register(tp->mdio_bus);
Matt Carlsona9daf362008-05-25 23:49:44 -07001470 if (i) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001471 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001472 mdiobus_free(tp->mdio_bus);
Matt Carlsona9daf362008-05-25 23:49:44 -07001473 return i;
1474 }
Matt Carlson158d7ab2008-05-29 01:37:54 -07001475
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001476 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsona9daf362008-05-25 23:49:44 -07001477
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001478 if (!phydev || !phydev->drv) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001479 dev_warn(&tp->pdev->dev, "No PHY devices\n");
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001480 mdiobus_unregister(tp->mdio_bus);
1481 mdiobus_free(tp->mdio_bus);
1482 return -ENODEV;
1483 }
1484
1485 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
Matt Carlson6a443a02010-02-17 15:17:04 +00001486 case PHY_ID_BCM57780:
Matt Carlson321d32a2008-11-21 17:22:19 -08001487 phydev->interface = PHY_INTERFACE_MODE_GMII;
Matt Carlsonc704dc22009-11-02 14:32:12 +00001488 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlson321d32a2008-11-21 17:22:19 -08001489 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001490 case PHY_ID_BCM50610:
1491 case PHY_ID_BCM50610M:
Matt Carlson32e5a8d2009-11-02 14:31:39 +00001492 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
Matt Carlsonc704dc22009-11-02 14:32:12 +00001493 PHY_BRCM_RX_REFCLK_UNUSED |
Matt Carlson52fae082009-11-02 14:32:38 +00001494 PHY_BRCM_DIS_TXCRXC_NOENRGY |
Matt Carlsonc704dc22009-11-02 14:32:12 +00001495 PHY_BRCM_AUTO_PWRDWN_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00001496 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
Matt Carlsona9daf362008-05-25 23:49:44 -07001497 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00001498 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001499 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00001500 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001501 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001502 /* fallthru */
Matt Carlson6a443a02010-02-17 15:17:04 +00001503 case PHY_ID_RTL8211C:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001504 phydev->interface = PHY_INTERFACE_MODE_RGMII;
Matt Carlsona9daf362008-05-25 23:49:44 -07001505 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001506 case PHY_ID_RTL8201E:
1507 case PHY_ID_BCMAC131:
Matt Carlsona9daf362008-05-25 23:49:44 -07001508 phydev->interface = PHY_INTERFACE_MODE_MII;
Matt Carlsoncdd4e09d2009-11-02 14:31:11 +00001509 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001510 tp->phy_flags |= TG3_PHYFLG_IS_FET;
Matt Carlsona9daf362008-05-25 23:49:44 -07001511 break;
1512 }
1513
Joe Perches63c3a662011-04-26 08:12:10 +00001514 tg3_flag_set(tp, MDIOBUS_INITED);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001515
1516 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1517 tg3_mdio_config_5785(tp);
Matt Carlsona9daf362008-05-25 23:49:44 -07001518
1519 return 0;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001520}
1521
1522static void tg3_mdio_fini(struct tg3 *tp)
1523{
Joe Perches63c3a662011-04-26 08:12:10 +00001524 if (tg3_flag(tp, MDIOBUS_INITED)) {
1525 tg3_flag_clear(tp, MDIOBUS_INITED);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001526 mdiobus_unregister(tp->mdio_bus);
1527 mdiobus_free(tp->mdio_bus);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001528 }
1529}
1530
Matt Carlson95e28692008-05-25 23:44:14 -07001531/* tp->lock is held. */
Matt Carlson4ba526c2008-08-15 14:10:04 -07001532static inline void tg3_generate_fw_event(struct tg3 *tp)
1533{
1534 u32 val;
1535
1536 val = tr32(GRC_RX_CPU_EVENT);
1537 val |= GRC_RX_CPU_DRIVER_EVENT;
1538 tw32_f(GRC_RX_CPU_EVENT, val);
1539
1540 tp->last_event_jiffies = jiffies;
1541}
1542
1543#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1544
1545/* tp->lock is held. */
Matt Carlson95e28692008-05-25 23:44:14 -07001546static void tg3_wait_for_event_ack(struct tg3 *tp)
1547{
1548 int i;
Matt Carlson4ba526c2008-08-15 14:10:04 -07001549 unsigned int delay_cnt;
1550 long time_remain;
Matt Carlson95e28692008-05-25 23:44:14 -07001551
Matt Carlson4ba526c2008-08-15 14:10:04 -07001552 /* If enough time has passed, no wait is necessary. */
1553 time_remain = (long)(tp->last_event_jiffies + 1 +
1554 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1555 (long)jiffies;
1556 if (time_remain < 0)
1557 return;
1558
1559 /* Check if we can shorten the wait time. */
1560 delay_cnt = jiffies_to_usecs(time_remain);
1561 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1562 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1563 delay_cnt = (delay_cnt >> 3) + 1;
1564
1565 for (i = 0; i < delay_cnt; i++) {
Matt Carlson95e28692008-05-25 23:44:14 -07001566 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1567 break;
Matt Carlson4ba526c2008-08-15 14:10:04 -07001568 udelay(8);
Matt Carlson95e28692008-05-25 23:44:14 -07001569 }
1570}
1571
1572/* tp->lock is held. */
Matt Carlsonb28f3892012-02-13 15:20:12 +00001573static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
Matt Carlson95e28692008-05-25 23:44:14 -07001574{
Matt Carlsonb28f3892012-02-13 15:20:12 +00001575 u32 reg, val;
Matt Carlson95e28692008-05-25 23:44:14 -07001576
1577 val = 0;
1578 if (!tg3_readphy(tp, MII_BMCR, &reg))
1579 val = reg << 16;
1580 if (!tg3_readphy(tp, MII_BMSR, &reg))
1581 val |= (reg & 0xffff);
Matt Carlsonb28f3892012-02-13 15:20:12 +00001582 *data++ = val;
Matt Carlson95e28692008-05-25 23:44:14 -07001583
1584 val = 0;
1585 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1586 val = reg << 16;
1587 if (!tg3_readphy(tp, MII_LPA, &reg))
1588 val |= (reg & 0xffff);
Matt Carlsonb28f3892012-02-13 15:20:12 +00001589 *data++ = val;
Matt Carlson95e28692008-05-25 23:44:14 -07001590
1591 val = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001592 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
Matt Carlson95e28692008-05-25 23:44:14 -07001593 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1594 val = reg << 16;
1595 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1596 val |= (reg & 0xffff);
1597 }
Matt Carlsonb28f3892012-02-13 15:20:12 +00001598 *data++ = val;
Matt Carlson95e28692008-05-25 23:44:14 -07001599
1600 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1601 val = reg << 16;
1602 else
1603 val = 0;
Matt Carlsonb28f3892012-02-13 15:20:12 +00001604 *data++ = val;
1605}
1606
1607/* tp->lock is held. */
1608static void tg3_ump_link_report(struct tg3 *tp)
1609{
1610 u32 data[4];
1611
1612 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1613 return;
1614
1615 tg3_phy_gather_ump_data(tp, data);
1616
1617 tg3_wait_for_event_ack(tp);
1618
1619 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1620 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1621 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1622 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1623 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1624 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
Matt Carlson95e28692008-05-25 23:44:14 -07001625
Matt Carlson4ba526c2008-08-15 14:10:04 -07001626 tg3_generate_fw_event(tp);
Matt Carlson95e28692008-05-25 23:44:14 -07001627}
1628
Matt Carlson8d5a89b2011-08-31 11:44:51 +00001629/* tp->lock is held. */
1630static void tg3_stop_fw(struct tg3 *tp)
1631{
1632 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1633 /* Wait for RX cpu to ACK the previous event. */
1634 tg3_wait_for_event_ack(tp);
1635
1636 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1637
1638 tg3_generate_fw_event(tp);
1639
1640 /* Wait for RX cpu to ACK this event. */
1641 tg3_wait_for_event_ack(tp);
1642 }
1643}
1644
Matt Carlsonfd6d3f02011-08-31 11:44:52 +00001645/* tp->lock is held. */
1646static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1647{
1648 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1649 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1650
1651 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1652 switch (kind) {
1653 case RESET_KIND_INIT:
1654 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1655 DRV_STATE_START);
1656 break;
1657
1658 case RESET_KIND_SHUTDOWN:
1659 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1660 DRV_STATE_UNLOAD);
1661 break;
1662
1663 case RESET_KIND_SUSPEND:
1664 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1665 DRV_STATE_SUSPEND);
1666 break;
1667
1668 default:
1669 break;
1670 }
1671 }
1672
1673 if (kind == RESET_KIND_INIT ||
1674 kind == RESET_KIND_SUSPEND)
1675 tg3_ape_driver_state_change(tp, kind);
1676}
1677
1678/* tp->lock is held. */
1679static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1680{
1681 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1682 switch (kind) {
1683 case RESET_KIND_INIT:
1684 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1685 DRV_STATE_START_DONE);
1686 break;
1687
1688 case RESET_KIND_SHUTDOWN:
1689 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1690 DRV_STATE_UNLOAD_DONE);
1691 break;
1692
1693 default:
1694 break;
1695 }
1696 }
1697
1698 if (kind == RESET_KIND_SHUTDOWN)
1699 tg3_ape_driver_state_change(tp, kind);
1700}
1701
1702/* tp->lock is held. */
1703static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1704{
1705 if (tg3_flag(tp, ENABLE_ASF)) {
1706 switch (kind) {
1707 case RESET_KIND_INIT:
1708 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1709 DRV_STATE_START);
1710 break;
1711
1712 case RESET_KIND_SHUTDOWN:
1713 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1714 DRV_STATE_UNLOAD);
1715 break;
1716
1717 case RESET_KIND_SUSPEND:
1718 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1719 DRV_STATE_SUSPEND);
1720 break;
1721
1722 default:
1723 break;
1724 }
1725 }
1726}
1727
1728static int tg3_poll_fw(struct tg3 *tp)
1729{
1730 int i;
1731 u32 val;
1732
1733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1734 /* Wait up to 20ms for init done. */
1735 for (i = 0; i < 200; i++) {
1736 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1737 return 0;
1738 udelay(100);
1739 }
1740 return -ENODEV;
1741 }
1742
1743 /* Wait for firmware initialization to complete. */
1744 for (i = 0; i < 100000; i++) {
1745 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1746 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1747 break;
1748 udelay(10);
1749 }
1750
1751 /* Chip might not be fitted with firmware. Some Sun onboard
1752 * parts are configured like that. So don't signal the timeout
1753 * of the above loop as an error, but do report the lack of
1754 * running firmware once.
1755 */
1756 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1757 tg3_flag_set(tp, NO_FWARE_REPORTED);
1758
1759 netdev_info(tp->dev, "No firmware running\n");
1760 }
1761
1762 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1763 /* The 57765 A0 needs a little more
1764 * time to do some important work.
1765 */
1766 mdelay(10);
1767 }
1768
1769 return 0;
1770}
1771
Matt Carlson95e28692008-05-25 23:44:14 -07001772static void tg3_link_report(struct tg3 *tp)
1773{
1774 if (!netif_carrier_ok(tp->dev)) {
Joe Perches05dbe002010-02-17 19:44:19 +00001775 netif_info(tp, link, tp->dev, "Link is down\n");
Matt Carlson95e28692008-05-25 23:44:14 -07001776 tg3_ump_link_report(tp);
1777 } else if (netif_msg_link(tp)) {
Joe Perches05dbe002010-02-17 19:44:19 +00001778 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1779 (tp->link_config.active_speed == SPEED_1000 ?
1780 1000 :
1781 (tp->link_config.active_speed == SPEED_100 ?
1782 100 : 10)),
1783 (tp->link_config.active_duplex == DUPLEX_FULL ?
1784 "full" : "half"));
Matt Carlson95e28692008-05-25 23:44:14 -07001785
Joe Perches05dbe002010-02-17 19:44:19 +00001786 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1787 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1788 "on" : "off",
1789 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1790 "on" : "off");
Matt Carlson47007832011-04-20 07:57:43 +00001791
1792 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1793 netdev_info(tp->dev, "EEE is %s\n",
1794 tp->setlpicnt ? "enabled" : "disabled");
1795
Matt Carlson95e28692008-05-25 23:44:14 -07001796 tg3_ump_link_report(tp);
1797 }
1798}
1799
Matt Carlson95e28692008-05-25 23:44:14 -07001800static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1801{
1802 u16 miireg;
1803
Steve Glendinninge18ce342008-12-16 02:00:00 -08001804 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
Matt Carlson95e28692008-05-25 23:44:14 -07001805 miireg = ADVERTISE_1000XPAUSE;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001806 else if (flow_ctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001807 miireg = ADVERTISE_1000XPSE_ASYM;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001808 else if (flow_ctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001809 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1810 else
1811 miireg = 0;
1812
1813 return miireg;
1814}
1815
Matt Carlson95e28692008-05-25 23:44:14 -07001816static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1817{
1818 u8 cap = 0;
1819
Matt Carlsonf3791cd2011-11-21 15:01:17 +00001820 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1821 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1822 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1823 if (lcladv & ADVERTISE_1000XPAUSE)
1824 cap = FLOW_CTRL_RX;
1825 if (rmtadv & ADVERTISE_1000XPAUSE)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001826 cap = FLOW_CTRL_TX;
Matt Carlson95e28692008-05-25 23:44:14 -07001827 }
1828
1829 return cap;
1830}
1831
Matt Carlsonf51f3562008-05-25 23:45:08 -07001832static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
Matt Carlson95e28692008-05-25 23:44:14 -07001833{
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001834 u8 autoneg;
Matt Carlsonf51f3562008-05-25 23:45:08 -07001835 u8 flowctrl = 0;
Matt Carlson95e28692008-05-25 23:44:14 -07001836 u32 old_rx_mode = tp->rx_mode;
1837 u32 old_tx_mode = tp->tx_mode;
1838
Joe Perches63c3a662011-04-26 08:12:10 +00001839 if (tg3_flag(tp, USE_PHYLIB))
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001840 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001841 else
1842 autoneg = tp->link_config.autoneg;
1843
Joe Perches63c3a662011-04-26 08:12:10 +00001844 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001845 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Matt Carlsonf51f3562008-05-25 23:45:08 -07001846 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
Matt Carlson95e28692008-05-25 23:44:14 -07001847 else
Steve Glendinningbc02ff92008-12-16 02:00:48 -08001848 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
Matt Carlsonf51f3562008-05-25 23:45:08 -07001849 } else
1850 flowctrl = tp->link_config.flowctrl;
Matt Carlson95e28692008-05-25 23:44:14 -07001851
Matt Carlsonf51f3562008-05-25 23:45:08 -07001852 tp->link_config.active_flowctrl = flowctrl;
Matt Carlson95e28692008-05-25 23:44:14 -07001853
Steve Glendinninge18ce342008-12-16 02:00:00 -08001854 if (flowctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001855 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1856 else
1857 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1858
Matt Carlsonf51f3562008-05-25 23:45:08 -07001859 if (old_rx_mode != tp->rx_mode)
Matt Carlson95e28692008-05-25 23:44:14 -07001860 tw32_f(MAC_RX_MODE, tp->rx_mode);
Matt Carlson95e28692008-05-25 23:44:14 -07001861
Steve Glendinninge18ce342008-12-16 02:00:00 -08001862 if (flowctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001863 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1864 else
1865 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1866
Matt Carlsonf51f3562008-05-25 23:45:08 -07001867 if (old_tx_mode != tp->tx_mode)
Matt Carlson95e28692008-05-25 23:44:14 -07001868 tw32_f(MAC_TX_MODE, tp->tx_mode);
Matt Carlson95e28692008-05-25 23:44:14 -07001869}
1870
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001871static void tg3_adjust_link(struct net_device *dev)
1872{
1873 u8 oldflowctrl, linkmesg = 0;
1874 u32 mac_mode, lcl_adv, rmt_adv;
1875 struct tg3 *tp = netdev_priv(dev);
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001876 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001877
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001878 spin_lock_bh(&tp->lock);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001879
1880 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1881 MAC_MODE_HALF_DUPLEX);
1882
1883 oldflowctrl = tp->link_config.active_flowctrl;
1884
1885 if (phydev->link) {
1886 lcl_adv = 0;
1887 rmt_adv = 0;
1888
1889 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1890 mac_mode |= MAC_MODE_PORT_MODE_MII;
Matt Carlsonc3df0742009-11-02 14:27:02 +00001891 else if (phydev->speed == SPEED_1000 ||
1892 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001893 mac_mode |= MAC_MODE_PORT_MODE_GMII;
Matt Carlsonc3df0742009-11-02 14:27:02 +00001894 else
1895 mac_mode |= MAC_MODE_PORT_MODE_MII;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001896
1897 if (phydev->duplex == DUPLEX_HALF)
1898 mac_mode |= MAC_MODE_HALF_DUPLEX;
1899 else {
Matt Carlsonf88788f2011-12-14 11:10:00 +00001900 lcl_adv = mii_advertise_flowctrl(
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001901 tp->link_config.flowctrl);
1902
1903 if (phydev->pause)
1904 rmt_adv = LPA_PAUSE_CAP;
1905 if (phydev->asym_pause)
1906 rmt_adv |= LPA_PAUSE_ASYM;
1907 }
1908
1909 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1910 } else
1911 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1912
1913 if (mac_mode != tp->mac_mode) {
1914 tp->mac_mode = mac_mode;
1915 tw32_f(MAC_MODE, tp->mac_mode);
1916 udelay(40);
1917 }
1918
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1920 if (phydev->speed == SPEED_10)
1921 tw32(MAC_MI_STAT,
1922 MAC_MI_STAT_10MBPS_MODE |
1923 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1924 else
1925 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1926 }
1927
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001928 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1929 tw32(MAC_TX_LENGTHS,
1930 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1931 (6 << TX_LENGTHS_IPG_SHIFT) |
1932 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1933 else
1934 tw32(MAC_TX_LENGTHS,
1935 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1936 (6 << TX_LENGTHS_IPG_SHIFT) |
1937 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1938
Matt Carlson34655ad2012-02-22 12:35:18 +00001939 if (phydev->link != tp->old_link ||
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001940 phydev->speed != tp->link_config.active_speed ||
1941 phydev->duplex != tp->link_config.active_duplex ||
1942 oldflowctrl != tp->link_config.active_flowctrl)
Matt Carlsonc6cdf432010-04-05 10:19:26 +00001943 linkmesg = 1;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001944
Matt Carlson34655ad2012-02-22 12:35:18 +00001945 tp->old_link = phydev->link;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001946 tp->link_config.active_speed = phydev->speed;
1947 tp->link_config.active_duplex = phydev->duplex;
1948
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001949 spin_unlock_bh(&tp->lock);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001950
1951 if (linkmesg)
1952 tg3_link_report(tp);
1953}
1954
1955static int tg3_phy_init(struct tg3 *tp)
1956{
1957 struct phy_device *phydev;
1958
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001959 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001960 return 0;
1961
1962 /* Bring the PHY back to a known state. */
1963 tg3_bmcr_reset(tp);
1964
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001965 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001966
1967 /* Attach the MAC to the PHY. */
Kay Sieversfb28ad352008-11-10 13:55:14 -08001968 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
Matt Carlsona9daf362008-05-25 23:49:44 -07001969 phydev->dev_flags, phydev->interface);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001970 if (IS_ERR(phydev)) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001971 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001972 return PTR_ERR(phydev);
1973 }
1974
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001975 /* Mask with MAC supported features. */
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001976 switch (phydev->interface) {
1977 case PHY_INTERFACE_MODE_GMII:
1978 case PHY_INTERFACE_MODE_RGMII:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001979 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Matt Carlson321d32a2008-11-21 17:22:19 -08001980 phydev->supported &= (PHY_GBIT_FEATURES |
1981 SUPPORTED_Pause |
1982 SUPPORTED_Asym_Pause);
1983 break;
1984 }
1985 /* fallthru */
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001986 case PHY_INTERFACE_MODE_MII:
1987 phydev->supported &= (PHY_BASIC_FEATURES |
1988 SUPPORTED_Pause |
1989 SUPPORTED_Asym_Pause);
1990 break;
1991 default:
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001992 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001993 return -EINVAL;
1994 }
1995
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001996 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001997
1998 phydev->advertising = phydev->supported;
1999
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002000 return 0;
2001}
2002
2003static void tg3_phy_start(struct tg3 *tp)
2004{
2005 struct phy_device *phydev;
2006
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002007 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002008 return;
2009
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00002010 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002011
Matt Carlson80096062010-08-02 11:26:06 +00002012 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2013 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsonc6700ce2012-02-13 15:20:15 +00002014 phydev->speed = tp->link_config.speed;
2015 phydev->duplex = tp->link_config.duplex;
2016 phydev->autoneg = tp->link_config.autoneg;
2017 phydev->advertising = tp->link_config.advertising;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002018 }
2019
2020 phy_start(phydev);
2021
2022 phy_start_aneg(phydev);
2023}
2024
2025static void tg3_phy_stop(struct tg3 *tp)
2026{
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002027 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002028 return;
2029
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00002030 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002031}
2032
2033static void tg3_phy_fini(struct tg3 *tp)
2034{
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002035 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00002036 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002037 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002038 }
2039}
2040
Matt Carlson941ec902011-08-19 13:58:23 +00002041static int tg3_phy_set_extloopbk(struct tg3 *tp)
2042{
2043 int err;
2044 u32 val;
2045
2046 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2047 return 0;
2048
2049 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2050 /* Cannot do read-modify-write on 5401 */
2051 err = tg3_phy_auxctl_write(tp,
2052 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2053 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2054 0x4c20);
2055 goto done;
2056 }
2057
2058 err = tg3_phy_auxctl_read(tp,
2059 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2060 if (err)
2061 return err;
2062
2063 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2064 err = tg3_phy_auxctl_write(tp,
2065 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2066
2067done:
2068 return err;
2069}
2070
Matt Carlson7f97a4b2009-08-25 10:10:03 +00002071static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2072{
2073 u32 phytest;
2074
2075 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2076 u32 phy;
2077
2078 tg3_writephy(tp, MII_TG3_FET_TEST,
2079 phytest | MII_TG3_FET_SHADOW_EN);
2080 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2081 if (enable)
2082 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2083 else
2084 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2085 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2086 }
2087 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2088 }
2089}
2090
Matt Carlson6833c042008-11-21 17:18:59 -08002091static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2092{
2093 u32 reg;
2094
Joe Perches63c3a662011-04-26 08:12:10 +00002095 if (!tg3_flag(tp, 5705_PLUS) ||
2096 (tg3_flag(tp, 5717_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002097 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
Matt Carlson6833c042008-11-21 17:18:59 -08002098 return;
2099
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002100 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson7f97a4b2009-08-25 10:10:03 +00002101 tg3_phy_fet_toggle_apd(tp, enable);
2102 return;
2103 }
2104
Matt Carlson6833c042008-11-21 17:18:59 -08002105 reg = MII_TG3_MISC_SHDW_WREN |
2106 MII_TG3_MISC_SHDW_SCR5_SEL |
2107 MII_TG3_MISC_SHDW_SCR5_LPED |
2108 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2109 MII_TG3_MISC_SHDW_SCR5_SDTL |
2110 MII_TG3_MISC_SHDW_SCR5_C125OE;
2111 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2112 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2113
2114 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2115
2116
2117 reg = MII_TG3_MISC_SHDW_WREN |
2118 MII_TG3_MISC_SHDW_APD_SEL |
2119 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2120 if (enable)
2121 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2122
2123 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2124}
2125
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002126static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2127{
2128 u32 phy;
2129
Joe Perches63c3a662011-04-26 08:12:10 +00002130 if (!tg3_flag(tp, 5705_PLUS) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002131 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002132 return;
2133
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002134 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002135 u32 ephy;
2136
Matt Carlson535ef6e2009-08-25 10:09:36 +00002137 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2138 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2139
2140 tg3_writephy(tp, MII_TG3_FET_TEST,
2141 ephy | MII_TG3_FET_SHADOW_EN);
2142 if (!tg3_readphy(tp, reg, &phy)) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002143 if (enable)
Matt Carlson535ef6e2009-08-25 10:09:36 +00002144 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002145 else
Matt Carlson535ef6e2009-08-25 10:09:36 +00002146 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2147 tg3_writephy(tp, reg, phy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002148 }
Matt Carlson535ef6e2009-08-25 10:09:36 +00002149 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002150 }
2151 } else {
Matt Carlson15ee95c2011-04-20 07:57:40 +00002152 int ret;
2153
2154 ret = tg3_phy_auxctl_read(tp,
2155 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2156 if (!ret) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002157 if (enable)
2158 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2159 else
2160 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002161 tg3_phy_auxctl_write(tp,
2162 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002163 }
2164 }
2165}
2166
Linus Torvalds1da177e2005-04-16 15:20:36 -07002167static void tg3_phy_set_wirespeed(struct tg3 *tp)
2168{
Matt Carlson15ee95c2011-04-20 07:57:40 +00002169 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002170 u32 val;
2171
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002172 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002173 return;
2174
Matt Carlson15ee95c2011-04-20 07:57:40 +00002175 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2176 if (!ret)
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002177 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2178 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002179}
2180
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002181static void tg3_phy_apply_otp(struct tg3 *tp)
2182{
2183 u32 otp, phy;
2184
2185 if (!tp->phy_otp)
2186 return;
2187
2188 otp = tp->phy_otp;
2189
Matt Carlson1d36ba42011-04-20 07:57:42 +00002190 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2191 return;
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002192
2193 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2194 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2195 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2196
2197 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2198 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2199 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2200
2201 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2202 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2203 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2204
2205 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2206 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2207
2208 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2209 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2210
2211 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2212 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2213 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2214
Matt Carlson1d36ba42011-04-20 07:57:42 +00002215 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002216}
2217
Matt Carlson52b02d02010-10-14 10:37:41 +00002218static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2219{
2220 u32 val;
2221
2222 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2223 return;
2224
2225 tp->setlpicnt = 0;
2226
2227 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2228 current_link_up == 1 &&
Matt Carlsona6b68da2010-12-06 08:28:52 +00002229 tp->link_config.active_duplex == DUPLEX_FULL &&
2230 (tp->link_config.active_speed == SPEED_100 ||
2231 tp->link_config.active_speed == SPEED_1000)) {
Matt Carlson52b02d02010-10-14 10:37:41 +00002232 u32 eeectl;
2233
2234 if (tp->link_config.active_speed == SPEED_1000)
2235 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2236 else
2237 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2238
2239 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2240
Matt Carlson3110f5f52010-12-06 08:28:50 +00002241 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2242 TG3_CL45_D7_EEERES_STAT, &val);
Matt Carlson52b02d02010-10-14 10:37:41 +00002243
Matt Carlsonb0c59432011-05-19 12:12:48 +00002244 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2245 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
Matt Carlson52b02d02010-10-14 10:37:41 +00002246 tp->setlpicnt = 2;
2247 }
2248
2249 if (!tp->setlpicnt) {
Matt Carlsonb715ce92011-07-20 10:20:52 +00002250 if (current_link_up == 1 &&
2251 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2252 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2253 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2254 }
2255
Matt Carlson52b02d02010-10-14 10:37:41 +00002256 val = tr32(TG3_CPMU_EEE_MODE);
2257 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2258 }
2259}
2260
Matt Carlsonb0c59432011-05-19 12:12:48 +00002261static void tg3_phy_eee_enable(struct tg3 *tp)
2262{
2263 u32 val;
2264
2265 if (tp->link_config.active_speed == SPEED_1000 &&
2266 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2267 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
Matt Carlson55086ad2011-12-14 11:09:59 +00002268 tg3_flag(tp, 57765_CLASS)) &&
Matt Carlsonb0c59432011-05-19 12:12:48 +00002269 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
Matt Carlsonb715ce92011-07-20 10:20:52 +00002270 val = MII_TG3_DSP_TAP26_ALNOKO |
2271 MII_TG3_DSP_TAP26_RMRXSTO;
2272 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
Matt Carlsonb0c59432011-05-19 12:12:48 +00002273 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2274 }
2275
2276 val = tr32(TG3_CPMU_EEE_MODE);
2277 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2278}
2279
Linus Torvalds1da177e2005-04-16 15:20:36 -07002280static int tg3_wait_macro_done(struct tg3 *tp)
2281{
2282 int limit = 100;
2283
2284 while (limit--) {
2285 u32 tmp32;
2286
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002287 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002288 if ((tmp32 & 0x1000) == 0)
2289 break;
2290 }
2291 }
Roel Kluind4675b52009-02-12 16:33:27 -08002292 if (limit < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002293 return -EBUSY;
2294
2295 return 0;
2296}
2297
2298static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2299{
2300 static const u32 test_pat[4][6] = {
2301 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2302 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2303 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2304 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2305 };
2306 int chan;
2307
2308 for (chan = 0; chan < 4; chan++) {
2309 int i;
2310
2311 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2312 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002313 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002314
2315 for (i = 0; i < 6; i++)
2316 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2317 test_pat[chan][i]);
2318
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002319 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002320 if (tg3_wait_macro_done(tp)) {
2321 *resetp = 1;
2322 return -EBUSY;
2323 }
2324
2325 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2326 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002327 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002328 if (tg3_wait_macro_done(tp)) {
2329 *resetp = 1;
2330 return -EBUSY;
2331 }
2332
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002333 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002334 if (tg3_wait_macro_done(tp)) {
2335 *resetp = 1;
2336 return -EBUSY;
2337 }
2338
2339 for (i = 0; i < 6; i += 2) {
2340 u32 low, high;
2341
2342 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2343 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2344 tg3_wait_macro_done(tp)) {
2345 *resetp = 1;
2346 return -EBUSY;
2347 }
2348 low &= 0x7fff;
2349 high &= 0x000f;
2350 if (low != test_pat[chan][i] ||
2351 high != test_pat[chan][i+1]) {
2352 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2353 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2354 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2355
2356 return -EBUSY;
2357 }
2358 }
2359 }
2360
2361 return 0;
2362}
2363
2364static int tg3_phy_reset_chanpat(struct tg3 *tp)
2365{
2366 int chan;
2367
2368 for (chan = 0; chan < 4; chan++) {
2369 int i;
2370
2371 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2372 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002373 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002374 for (i = 0; i < 6; i++)
2375 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002376 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002377 if (tg3_wait_macro_done(tp))
2378 return -EBUSY;
2379 }
2380
2381 return 0;
2382}
2383
2384static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2385{
2386 u32 reg32, phy9_orig;
2387 int retries, do_phy_reset, err;
2388
2389 retries = 10;
2390 do_phy_reset = 1;
2391 do {
2392 if (do_phy_reset) {
2393 err = tg3_bmcr_reset(tp);
2394 if (err)
2395 return err;
2396 do_phy_reset = 0;
2397 }
2398
2399 /* Disable transmitter and interrupt. */
2400 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2401 continue;
2402
2403 reg32 |= 0x3000;
2404 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2405
2406 /* Set full-duplex, 1000 mbps. */
2407 tg3_writephy(tp, MII_BMCR,
Matt Carlson221c5632011-06-13 13:39:01 +00002408 BMCR_FULLDPLX | BMCR_SPEED1000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002409
2410 /* Set to master mode. */
Matt Carlson221c5632011-06-13 13:39:01 +00002411 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002412 continue;
2413
Matt Carlson221c5632011-06-13 13:39:01 +00002414 tg3_writephy(tp, MII_CTRL1000,
2415 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002416
Matt Carlson1d36ba42011-04-20 07:57:42 +00002417 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2418 if (err)
2419 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002420
2421 /* Block the PHY control access. */
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002422 tg3_phydsp_write(tp, 0x8005, 0x0800);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002423
2424 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2425 if (!err)
2426 break;
2427 } while (--retries);
2428
2429 err = tg3_phy_reset_chanpat(tp);
2430 if (err)
2431 return err;
2432
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002433 tg3_phydsp_write(tp, 0x8005, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002434
2435 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002436 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002437
Matt Carlson1d36ba42011-04-20 07:57:42 +00002438 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002439
Matt Carlson221c5632011-06-13 13:39:01 +00002440 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002441
2442 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2443 reg32 &= ~0x3000;
2444 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2445 } else if (!err)
2446 err = -EBUSY;
2447
2448 return err;
2449}
2450
2451/* This will reset the tigon3 PHY if there is no valid
2452 * link unless the FORCE argument is non-zero.
2453 */
2454static int tg3_phy_reset(struct tg3 *tp)
2455{
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002456 u32 val, cpmuctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002457 int err;
2458
Michael Chan60189dd2006-12-17 17:08:07 -08002459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan60189dd2006-12-17 17:08:07 -08002460 val = tr32(GRC_MISC_CFG);
2461 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2462 udelay(40);
2463 }
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002464 err = tg3_readphy(tp, MII_BMSR, &val);
2465 err |= tg3_readphy(tp, MII_BMSR, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002466 if (err != 0)
2467 return -EBUSY;
2468
Michael Chanc8e1e822006-04-29 18:55:17 -07002469 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2470 netif_carrier_off(tp->dev);
2471 tg3_link_report(tp);
2472 }
2473
Linus Torvalds1da177e2005-04-16 15:20:36 -07002474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2477 err = tg3_phy_reset_5703_4_5(tp);
2478 if (err)
2479 return err;
2480 goto out;
2481 }
2482
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002483 cpmuctrl = 0;
2484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2485 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2486 cpmuctrl = tr32(TG3_CPMU_CTRL);
2487 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2488 tw32(TG3_CPMU_CTRL,
2489 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2490 }
2491
Linus Torvalds1da177e2005-04-16 15:20:36 -07002492 err = tg3_bmcr_reset(tp);
2493 if (err)
2494 return err;
2495
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002496 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002497 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2498 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002499
2500 tw32(TG3_CPMU_CTRL, cpmuctrl);
2501 }
2502
Matt Carlsonbcb37f62008-11-03 16:52:09 -08002503 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2504 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
Matt Carlsonce057f02007-11-12 21:08:03 -08002505 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2506 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2507 CPMU_LSPD_1000MB_MACCLK_12_5) {
2508 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2509 udelay(40);
2510 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2511 }
2512 }
2513
Joe Perches63c3a662011-04-26 08:12:10 +00002514 if (tg3_flag(tp, 5717_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002515 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
Matt Carlsonecf14102010-01-20 16:58:05 +00002516 return 0;
2517
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002518 tg3_phy_apply_otp(tp);
2519
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002520 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
Matt Carlson6833c042008-11-21 17:18:59 -08002521 tg3_phy_toggle_apd(tp, true);
2522 else
2523 tg3_phy_toggle_apd(tp, false);
2524
Linus Torvalds1da177e2005-04-16 15:20:36 -07002525out:
Matt Carlson1d36ba42011-04-20 07:57:42 +00002526 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2527 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002528 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2529 tg3_phydsp_write(tp, 0x000a, 0x0323);
Matt Carlson1d36ba42011-04-20 07:57:42 +00002530 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002531 }
Matt Carlson1d36ba42011-04-20 07:57:42 +00002532
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002533 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002534 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2535 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002536 }
Matt Carlson1d36ba42011-04-20 07:57:42 +00002537
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002538 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
Matt Carlson1d36ba42011-04-20 07:57:42 +00002539 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2540 tg3_phydsp_write(tp, 0x000a, 0x310b);
2541 tg3_phydsp_write(tp, 0x201f, 0x9506);
2542 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2543 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2544 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002545 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
Matt Carlson1d36ba42011-04-20 07:57:42 +00002546 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2547 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2548 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2549 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2550 tg3_writephy(tp, MII_TG3_TEST1,
2551 MII_TG3_TEST1_TRIM_EN | 0x4);
2552 } else
2553 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2554
2555 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2556 }
Michael Chanc424cb22006-04-29 18:56:34 -07002557 }
Matt Carlson1d36ba42011-04-20 07:57:42 +00002558
Linus Torvalds1da177e2005-04-16 15:20:36 -07002559 /* Set Extended packet length bit (bit 14) on all chips that */
2560 /* support jumbo frames */
Matt Carlson79eb6902010-02-17 15:17:03 +00002561 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002562 /* Cannot do read-modify-write on 5401 */
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002563 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
Joe Perches63c3a662011-04-26 08:12:10 +00002564 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002565 /* Set bit 14 with read-modify-write to preserve other bits */
Matt Carlson15ee95c2011-04-20 07:57:40 +00002566 err = tg3_phy_auxctl_read(tp,
2567 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2568 if (!err)
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002569 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2570 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002571 }
2572
2573 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2574 * jumbo frames transmission.
2575 */
Joe Perches63c3a662011-04-26 08:12:10 +00002576 if (tg3_flag(tp, JUMBO_CAPABLE)) {
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002577 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
Matt Carlsonc6cdf432010-04-05 10:19:26 +00002578 tg3_writephy(tp, MII_TG3_EXT_CTRL,
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002579 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002580 }
2581
Michael Chan715116a2006-09-27 16:09:25 -07002582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan715116a2006-09-27 16:09:25 -07002583 /* adjust output voltage */
Matt Carlson535ef6e2009-08-25 10:09:36 +00002584 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
Michael Chan715116a2006-09-27 16:09:25 -07002585 }
2586
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002587 tg3_phy_toggle_automdix(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002588 tg3_phy_set_wirespeed(tp);
2589 return 0;
2590}
2591
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002592#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2593#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2594#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2595 TG3_GPIO_MSG_NEED_VAUX)
2596#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2597 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2598 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2599 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2600 (TG3_GPIO_MSG_DRVR_PRES << 12))
2601
2602#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2603 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2604 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2605 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2606 (TG3_GPIO_MSG_NEED_VAUX << 12))
2607
2608static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2609{
2610 u32 status, shift;
2611
2612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2614 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2615 else
2616 status = tr32(TG3_CPMU_DRV_STATUS);
2617
2618 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2619 status &= ~(TG3_GPIO_MSG_MASK << shift);
2620 status |= (newstat << shift);
2621
2622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2624 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2625 else
2626 tw32(TG3_CPMU_DRV_STATUS, status);
2627
2628 return status >> TG3_APE_GPIO_MSG_SHIFT;
2629}
2630
Matt Carlson520b2752011-06-13 13:39:02 +00002631static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2632{
2633 if (!tg3_flag(tp, IS_NIC))
2634 return 0;
2635
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2639 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2640 return -EIO;
Matt Carlson520b2752011-06-13 13:39:02 +00002641
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002642 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2643
2644 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2645 TG3_GRC_LCLCTL_PWRSW_DELAY);
2646
2647 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2648 } else {
2649 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2650 TG3_GRC_LCLCTL_PWRSW_DELAY);
2651 }
Matt Carlson6f5c8f832011-07-13 09:27:31 +00002652
Matt Carlson520b2752011-06-13 13:39:02 +00002653 return 0;
2654}
2655
2656static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2657{
2658 u32 grc_local_ctrl;
2659
2660 if (!tg3_flag(tp, IS_NIC) ||
2661 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2663 return;
2664
2665 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2666
2667 tw32_wait_f(GRC_LOCAL_CTRL,
2668 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2669 TG3_GRC_LCLCTL_PWRSW_DELAY);
2670
2671 tw32_wait_f(GRC_LOCAL_CTRL,
2672 grc_local_ctrl,
2673 TG3_GRC_LCLCTL_PWRSW_DELAY);
2674
2675 tw32_wait_f(GRC_LOCAL_CTRL,
2676 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2677 TG3_GRC_LCLCTL_PWRSW_DELAY);
2678}
2679
2680static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2681{
2682 if (!tg3_flag(tp, IS_NIC))
2683 return;
2684
2685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2686 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2687 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2688 (GRC_LCLCTRL_GPIO_OE0 |
2689 GRC_LCLCTRL_GPIO_OE1 |
2690 GRC_LCLCTRL_GPIO_OE2 |
2691 GRC_LCLCTRL_GPIO_OUTPUT0 |
2692 GRC_LCLCTRL_GPIO_OUTPUT1),
2693 TG3_GRC_LCLCTL_PWRSW_DELAY);
2694 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2695 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2696 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2697 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2698 GRC_LCLCTRL_GPIO_OE1 |
2699 GRC_LCLCTRL_GPIO_OE2 |
2700 GRC_LCLCTRL_GPIO_OUTPUT0 |
2701 GRC_LCLCTRL_GPIO_OUTPUT1 |
2702 tp->grc_local_ctrl;
2703 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2704 TG3_GRC_LCLCTL_PWRSW_DELAY);
2705
2706 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2707 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2708 TG3_GRC_LCLCTL_PWRSW_DELAY);
2709
2710 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2711 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2712 TG3_GRC_LCLCTL_PWRSW_DELAY);
2713 } else {
2714 u32 no_gpio2;
2715 u32 grc_local_ctrl = 0;
2716
2717 /* Workaround to prevent overdrawing Amps. */
2718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2719 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2720 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2721 grc_local_ctrl,
2722 TG3_GRC_LCLCTL_PWRSW_DELAY);
2723 }
2724
2725 /* On 5753 and variants, GPIO2 cannot be used. */
2726 no_gpio2 = tp->nic_sram_data_cfg &
2727 NIC_SRAM_DATA_CFG_NO_GPIO2;
2728
2729 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2730 GRC_LCLCTRL_GPIO_OE1 |
2731 GRC_LCLCTRL_GPIO_OE2 |
2732 GRC_LCLCTRL_GPIO_OUTPUT1 |
2733 GRC_LCLCTRL_GPIO_OUTPUT2;
2734 if (no_gpio2) {
2735 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2736 GRC_LCLCTRL_GPIO_OUTPUT2);
2737 }
2738 tw32_wait_f(GRC_LOCAL_CTRL,
2739 tp->grc_local_ctrl | grc_local_ctrl,
2740 TG3_GRC_LCLCTL_PWRSW_DELAY);
2741
2742 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2743
2744 tw32_wait_f(GRC_LOCAL_CTRL,
2745 tp->grc_local_ctrl | grc_local_ctrl,
2746 TG3_GRC_LCLCTL_PWRSW_DELAY);
2747
2748 if (!no_gpio2) {
2749 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2750 tw32_wait_f(GRC_LOCAL_CTRL,
2751 tp->grc_local_ctrl | grc_local_ctrl,
2752 TG3_GRC_LCLCTL_PWRSW_DELAY);
2753 }
2754 }
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002755}
Matt Carlson6f5c8f832011-07-13 09:27:31 +00002756
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002757static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002758{
2759 u32 msg = 0;
2760
2761 /* Serialize power state transitions */
2762 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2763 return;
2764
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002765 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002766 msg = TG3_GPIO_MSG_NEED_VAUX;
2767
2768 msg = tg3_set_function_status(tp, msg);
2769
2770 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2771 goto done;
2772
2773 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2774 tg3_pwrsrc_switch_to_vaux(tp);
2775 else
2776 tg3_pwrsrc_die_with_vmain(tp);
2777
2778done:
Matt Carlson6f5c8f832011-07-13 09:27:31 +00002779 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
Matt Carlson520b2752011-06-13 13:39:02 +00002780}
2781
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002782static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002783{
Matt Carlson683644b2011-03-09 16:58:23 +00002784 bool need_vaux = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002785
Matt Carlson334355a2010-01-20 16:58:10 +00002786 /* The GPIOs do something completely different on 57765. */
Matt Carlson55086ad2011-12-14 11:09:59 +00002787 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002788 return;
2789
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2791 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002793 tg3_frob_aux_power_5717(tp, include_wol ?
2794 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002795 return;
2796 }
2797
2798 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002799 struct net_device *dev_peer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002800
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002801 dev_peer = pci_get_drvdata(tp->pdev_peer);
Matt Carlson683644b2011-03-09 16:58:23 +00002802
Michael Chanbc1c7562006-03-20 17:48:03 -08002803 /* remove_one() may have been run on the peer. */
Matt Carlson683644b2011-03-09 16:58:23 +00002804 if (dev_peer) {
2805 struct tg3 *tp_peer = netdev_priv(dev_peer);
2806
Joe Perches63c3a662011-04-26 08:12:10 +00002807 if (tg3_flag(tp_peer, INIT_COMPLETE))
Matt Carlson683644b2011-03-09 16:58:23 +00002808 return;
2809
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002810 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
Joe Perches63c3a662011-04-26 08:12:10 +00002811 tg3_flag(tp_peer, ENABLE_ASF))
Matt Carlson683644b2011-03-09 16:58:23 +00002812 need_vaux = true;
2813 }
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002814 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002815
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002816 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2817 tg3_flag(tp, ENABLE_ASF))
Matt Carlson683644b2011-03-09 16:58:23 +00002818 need_vaux = true;
2819
Matt Carlson520b2752011-06-13 13:39:02 +00002820 if (need_vaux)
2821 tg3_pwrsrc_switch_to_vaux(tp);
2822 else
2823 tg3_pwrsrc_die_with_vmain(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002824}
2825
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002826static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2827{
2828 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2829 return 1;
Matt Carlson79eb6902010-02-17 15:17:03 +00002830 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002831 if (speed != SPEED_10)
2832 return 1;
2833 } else if (speed == SPEED_10)
2834 return 1;
2835
2836 return 0;
2837}
2838
Matt Carlson0a459aa2008-11-03 16:54:15 -08002839static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
Michael Chan15c3b692006-03-22 01:06:52 -08002840{
Matt Carlsonce057f02007-11-12 21:08:03 -08002841 u32 val;
2842
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002843 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Michael Chan51297242007-02-13 12:17:57 -08002844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2845 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2846 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2847
2848 sg_dig_ctrl |=
2849 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2850 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2851 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2852 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002853 return;
Michael Chan51297242007-02-13 12:17:57 -08002854 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002855
Michael Chan60189dd2006-12-17 17:08:07 -08002856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan60189dd2006-12-17 17:08:07 -08002857 tg3_bmcr_reset(tp);
2858 val = tr32(GRC_MISC_CFG);
2859 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2860 udelay(40);
2861 return;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002862 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson0e5f7842009-11-02 14:26:38 +00002863 u32 phytest;
2864 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2865 u32 phy;
2866
2867 tg3_writephy(tp, MII_ADVERTISE, 0);
2868 tg3_writephy(tp, MII_BMCR,
2869 BMCR_ANENABLE | BMCR_ANRESTART);
2870
2871 tg3_writephy(tp, MII_TG3_FET_TEST,
2872 phytest | MII_TG3_FET_SHADOW_EN);
2873 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2874 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2875 tg3_writephy(tp,
2876 MII_TG3_FET_SHDW_AUXMODE4,
2877 phy);
2878 }
2879 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2880 }
2881 return;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002882 } else if (do_low_power) {
Michael Chan715116a2006-09-27 16:09:25 -07002883 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2884 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
Matt Carlson0a459aa2008-11-03 16:54:15 -08002885
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002886 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2887 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2888 MII_TG3_AUXCTL_PCTL_VREG_11V;
2889 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
Michael Chan715116a2006-09-27 16:09:25 -07002890 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002891
Michael Chan15c3b692006-03-22 01:06:52 -08002892 /* The PHY should not be powered down on some chips because
2893 * of bugs.
2894 */
2895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2897 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
Matt Carlson085f1af2012-04-02 09:01:40 +00002898 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2899 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2900 !tp->pci_fn))
Michael Chan15c3b692006-03-22 01:06:52 -08002901 return;
Matt Carlsonce057f02007-11-12 21:08:03 -08002902
Matt Carlsonbcb37f62008-11-03 16:52:09 -08002903 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2904 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
Matt Carlsonce057f02007-11-12 21:08:03 -08002905 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2906 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2907 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2908 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2909 }
2910
Michael Chan15c3b692006-03-22 01:06:52 -08002911 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2912}
2913
Matt Carlson3f007892008-11-03 16:51:36 -08002914/* tp->lock is held. */
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002915static int tg3_nvram_lock(struct tg3 *tp)
2916{
Joe Perches63c3a662011-04-26 08:12:10 +00002917 if (tg3_flag(tp, NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002918 int i;
2919
2920 if (tp->nvram_lock_cnt == 0) {
2921 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2922 for (i = 0; i < 8000; i++) {
2923 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2924 break;
2925 udelay(20);
2926 }
2927 if (i == 8000) {
2928 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2929 return -ENODEV;
2930 }
2931 }
2932 tp->nvram_lock_cnt++;
2933 }
2934 return 0;
2935}
2936
2937/* tp->lock is held. */
2938static void tg3_nvram_unlock(struct tg3 *tp)
2939{
Joe Perches63c3a662011-04-26 08:12:10 +00002940 if (tg3_flag(tp, NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002941 if (tp->nvram_lock_cnt > 0)
2942 tp->nvram_lock_cnt--;
2943 if (tp->nvram_lock_cnt == 0)
2944 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2945 }
2946}
2947
2948/* tp->lock is held. */
2949static void tg3_enable_nvram_access(struct tg3 *tp)
2950{
Joe Perches63c3a662011-04-26 08:12:10 +00002951 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002952 u32 nvaccess = tr32(NVRAM_ACCESS);
2953
2954 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2955 }
2956}
2957
2958/* tp->lock is held. */
2959static void tg3_disable_nvram_access(struct tg3 *tp)
2960{
Joe Perches63c3a662011-04-26 08:12:10 +00002961 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002962 u32 nvaccess = tr32(NVRAM_ACCESS);
2963
2964 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2965 }
2966}
2967
2968static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2969 u32 offset, u32 *val)
2970{
2971 u32 tmp;
2972 int i;
2973
2974 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2975 return -EINVAL;
2976
2977 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2978 EEPROM_ADDR_DEVID_MASK |
2979 EEPROM_ADDR_READ);
2980 tw32(GRC_EEPROM_ADDR,
2981 tmp |
2982 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2983 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2984 EEPROM_ADDR_ADDR_MASK) |
2985 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2986
2987 for (i = 0; i < 1000; i++) {
2988 tmp = tr32(GRC_EEPROM_ADDR);
2989
2990 if (tmp & EEPROM_ADDR_COMPLETE)
2991 break;
2992 msleep(1);
2993 }
2994 if (!(tmp & EEPROM_ADDR_COMPLETE))
2995 return -EBUSY;
2996
Matt Carlson62cedd12009-04-20 14:52:29 -07002997 tmp = tr32(GRC_EEPROM_DATA);
2998
2999 /*
3000 * The data will always be opposite the native endian
3001 * format. Perform a blind byteswap to compensate.
3002 */
3003 *val = swab32(tmp);
3004
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003005 return 0;
3006}
3007
3008#define NVRAM_CMD_TIMEOUT 10000
3009
3010static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3011{
3012 int i;
3013
3014 tw32(NVRAM_CMD, nvram_cmd);
3015 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3016 udelay(10);
3017 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3018 udelay(10);
3019 break;
3020 }
3021 }
3022
3023 if (i == NVRAM_CMD_TIMEOUT)
3024 return -EBUSY;
3025
3026 return 0;
3027}
3028
3029static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3030{
Joe Perches63c3a662011-04-26 08:12:10 +00003031 if (tg3_flag(tp, NVRAM) &&
3032 tg3_flag(tp, NVRAM_BUFFERED) &&
3033 tg3_flag(tp, FLASH) &&
3034 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003035 (tp->nvram_jedecnum == JEDEC_ATMEL))
3036
3037 addr = ((addr / tp->nvram_pagesize) <<
3038 ATMEL_AT45DB0X1B_PAGE_POS) +
3039 (addr % tp->nvram_pagesize);
3040
3041 return addr;
3042}
3043
3044static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3045{
Joe Perches63c3a662011-04-26 08:12:10 +00003046 if (tg3_flag(tp, NVRAM) &&
3047 tg3_flag(tp, NVRAM_BUFFERED) &&
3048 tg3_flag(tp, FLASH) &&
3049 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003050 (tp->nvram_jedecnum == JEDEC_ATMEL))
3051
3052 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3053 tp->nvram_pagesize) +
3054 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3055
3056 return addr;
3057}
3058
Matt Carlsone4f34112009-02-25 14:25:00 +00003059/* NOTE: Data read in from NVRAM is byteswapped according to
3060 * the byteswapping settings for all other register accesses.
3061 * tg3 devices are BE devices, so on a BE machine, the data
3062 * returned will be exactly as it is seen in NVRAM. On a LE
3063 * machine, the 32-bit value will be byteswapped.
3064 */
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003065static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3066{
3067 int ret;
3068
Joe Perches63c3a662011-04-26 08:12:10 +00003069 if (!tg3_flag(tp, NVRAM))
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003070 return tg3_nvram_read_using_eeprom(tp, offset, val);
3071
3072 offset = tg3_nvram_phys_addr(tp, offset);
3073
3074 if (offset > NVRAM_ADDR_MSK)
3075 return -EINVAL;
3076
3077 ret = tg3_nvram_lock(tp);
3078 if (ret)
3079 return ret;
3080
3081 tg3_enable_nvram_access(tp);
3082
3083 tw32(NVRAM_ADDR, offset);
3084 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3085 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3086
3087 if (ret == 0)
Matt Carlsone4f34112009-02-25 14:25:00 +00003088 *val = tr32(NVRAM_RDDATA);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003089
3090 tg3_disable_nvram_access(tp);
3091
3092 tg3_nvram_unlock(tp);
3093
3094 return ret;
3095}
3096
Matt Carlsona9dc5292009-02-25 14:25:30 +00003097/* Ensures NVRAM data is in bytestream format. */
3098static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003099{
3100 u32 v;
Matt Carlsona9dc5292009-02-25 14:25:30 +00003101 int res = tg3_nvram_read(tp, offset, &v);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003102 if (!res)
Matt Carlsona9dc5292009-02-25 14:25:30 +00003103 *val = cpu_to_be32(v);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003104 return res;
3105}
3106
Matt Carlsondbe9b922012-02-13 10:20:09 +00003107static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3108 u32 offset, u32 len, u8 *buf)
3109{
3110 int i, j, rc = 0;
3111 u32 val;
3112
3113 for (i = 0; i < len; i += 4) {
3114 u32 addr;
3115 __be32 data;
3116
3117 addr = offset + i;
3118
3119 memcpy(&data, buf + i, 4);
3120
3121 /*
3122 * The SEEPROM interface expects the data to always be opposite
3123 * the native endian format. We accomplish this by reversing
3124 * all the operations that would have been performed on the
3125 * data from a call to tg3_nvram_read_be32().
3126 */
3127 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3128
3129 val = tr32(GRC_EEPROM_ADDR);
3130 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3131
3132 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3133 EEPROM_ADDR_READ);
3134 tw32(GRC_EEPROM_ADDR, val |
3135 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3136 (addr & EEPROM_ADDR_ADDR_MASK) |
3137 EEPROM_ADDR_START |
3138 EEPROM_ADDR_WRITE);
3139
3140 for (j = 0; j < 1000; j++) {
3141 val = tr32(GRC_EEPROM_ADDR);
3142
3143 if (val & EEPROM_ADDR_COMPLETE)
3144 break;
3145 msleep(1);
3146 }
3147 if (!(val & EEPROM_ADDR_COMPLETE)) {
3148 rc = -EBUSY;
3149 break;
3150 }
3151 }
3152
3153 return rc;
3154}
3155
3156/* offset and length are dword aligned */
3157static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3158 u8 *buf)
3159{
3160 int ret = 0;
3161 u32 pagesize = tp->nvram_pagesize;
3162 u32 pagemask = pagesize - 1;
3163 u32 nvram_cmd;
3164 u8 *tmp;
3165
3166 tmp = kmalloc(pagesize, GFP_KERNEL);
3167 if (tmp == NULL)
3168 return -ENOMEM;
3169
3170 while (len) {
3171 int j;
3172 u32 phy_addr, page_off, size;
3173
3174 phy_addr = offset & ~pagemask;
3175
3176 for (j = 0; j < pagesize; j += 4) {
3177 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3178 (__be32 *) (tmp + j));
3179 if (ret)
3180 break;
3181 }
3182 if (ret)
3183 break;
3184
3185 page_off = offset & pagemask;
3186 size = pagesize;
3187 if (len < size)
3188 size = len;
3189
3190 len -= size;
3191
3192 memcpy(tmp + page_off, buf, size);
3193
3194 offset = offset + (pagesize - page_off);
3195
3196 tg3_enable_nvram_access(tp);
3197
3198 /*
3199 * Before we can erase the flash page, we need
3200 * to issue a special "write enable" command.
3201 */
3202 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3203
3204 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3205 break;
3206
3207 /* Erase the target page */
3208 tw32(NVRAM_ADDR, phy_addr);
3209
3210 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3211 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3212
3213 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3214 break;
3215
3216 /* Issue another write enable to start the write. */
3217 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3218
3219 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3220 break;
3221
3222 for (j = 0; j < pagesize; j += 4) {
3223 __be32 data;
3224
3225 data = *((__be32 *) (tmp + j));
3226
3227 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3228
3229 tw32(NVRAM_ADDR, phy_addr + j);
3230
3231 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3232 NVRAM_CMD_WR;
3233
3234 if (j == 0)
3235 nvram_cmd |= NVRAM_CMD_FIRST;
3236 else if (j == (pagesize - 4))
3237 nvram_cmd |= NVRAM_CMD_LAST;
3238
3239 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3240 if (ret)
3241 break;
3242 }
3243 if (ret)
3244 break;
3245 }
3246
3247 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3248 tg3_nvram_exec_cmd(tp, nvram_cmd);
3249
3250 kfree(tmp);
3251
3252 return ret;
3253}
3254
3255/* offset and length are dword aligned */
3256static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3257 u8 *buf)
3258{
3259 int i, ret = 0;
3260
3261 for (i = 0; i < len; i += 4, offset += 4) {
3262 u32 page_off, phy_addr, nvram_cmd;
3263 __be32 data;
3264
3265 memcpy(&data, buf + i, 4);
3266 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3267
3268 page_off = offset % tp->nvram_pagesize;
3269
3270 phy_addr = tg3_nvram_phys_addr(tp, offset);
3271
Matt Carlsondbe9b922012-02-13 10:20:09 +00003272 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3273
3274 if (page_off == 0 || i == 0)
3275 nvram_cmd |= NVRAM_CMD_FIRST;
3276 if (page_off == (tp->nvram_pagesize - 4))
3277 nvram_cmd |= NVRAM_CMD_LAST;
3278
3279 if (i == (len - 4))
3280 nvram_cmd |= NVRAM_CMD_LAST;
3281
Matt Carlson42278222012-02-13 15:20:11 +00003282 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3283 !tg3_flag(tp, FLASH) ||
3284 !tg3_flag(tp, 57765_PLUS))
3285 tw32(NVRAM_ADDR, phy_addr);
3286
Matt Carlsondbe9b922012-02-13 10:20:09 +00003287 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
3288 !tg3_flag(tp, 5755_PLUS) &&
3289 (tp->nvram_jedecnum == JEDEC_ST) &&
3290 (nvram_cmd & NVRAM_CMD_FIRST)) {
3291 u32 cmd;
3292
3293 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3294 ret = tg3_nvram_exec_cmd(tp, cmd);
3295 if (ret)
3296 break;
3297 }
3298 if (!tg3_flag(tp, FLASH)) {
3299 /* We always do complete word writes to eeprom. */
3300 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3301 }
3302
3303 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3304 if (ret)
3305 break;
3306 }
3307 return ret;
3308}
3309
3310/* offset and length are dword aligned */
3311static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3312{
3313 int ret;
3314
3315 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3316 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3317 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3318 udelay(40);
3319 }
3320
3321 if (!tg3_flag(tp, NVRAM)) {
3322 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3323 } else {
3324 u32 grc_mode;
3325
3326 ret = tg3_nvram_lock(tp);
3327 if (ret)
3328 return ret;
3329
3330 tg3_enable_nvram_access(tp);
3331 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3332 tw32(NVRAM_WRITE1, 0x406);
3333
3334 grc_mode = tr32(GRC_MODE);
3335 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3336
3337 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3338 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3339 buf);
3340 } else {
3341 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3342 buf);
3343 }
3344
3345 grc_mode = tr32(GRC_MODE);
3346 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3347
3348 tg3_disable_nvram_access(tp);
3349 tg3_nvram_unlock(tp);
3350 }
3351
3352 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3353 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3354 udelay(40);
3355 }
3356
3357 return ret;
3358}
3359
Matt Carlson997b4f12011-08-31 11:44:53 +00003360#define RX_CPU_SCRATCH_BASE 0x30000
3361#define RX_CPU_SCRATCH_SIZE 0x04000
3362#define TX_CPU_SCRATCH_BASE 0x34000
3363#define TX_CPU_SCRATCH_SIZE 0x04000
3364
3365/* tp->lock is held. */
3366static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3367{
3368 int i;
3369
3370 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3371
3372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3373 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3374
3375 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3376 return 0;
3377 }
3378 if (offset == RX_CPU_BASE) {
3379 for (i = 0; i < 10000; i++) {
3380 tw32(offset + CPU_STATE, 0xffffffff);
3381 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3382 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3383 break;
3384 }
3385
3386 tw32(offset + CPU_STATE, 0xffffffff);
3387 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3388 udelay(10);
3389 } else {
3390 for (i = 0; i < 10000; i++) {
3391 tw32(offset + CPU_STATE, 0xffffffff);
3392 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3393 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3394 break;
3395 }
3396 }
3397
3398 if (i >= 10000) {
3399 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3400 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3401 return -ENODEV;
3402 }
3403
3404 /* Clear firmware's nvram arbitration. */
3405 if (tg3_flag(tp, NVRAM))
3406 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3407 return 0;
3408}
3409
3410struct fw_info {
3411 unsigned int fw_base;
3412 unsigned int fw_len;
3413 const __be32 *fw_data;
3414};
3415
3416/* tp->lock is held. */
3417static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3418 u32 cpu_scratch_base, int cpu_scratch_size,
3419 struct fw_info *info)
3420{
3421 int err, lock_err, i;
3422 void (*write_op)(struct tg3 *, u32, u32);
3423
3424 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3425 netdev_err(tp->dev,
3426 "%s: Trying to load TX cpu firmware which is 5705\n",
3427 __func__);
3428 return -EINVAL;
3429 }
3430
3431 if (tg3_flag(tp, 5705_PLUS))
3432 write_op = tg3_write_mem;
3433 else
3434 write_op = tg3_write_indirect_reg32;
3435
3436 /* It is possible that bootcode is still loading at this point.
3437 * Get the nvram lock first before halting the cpu.
3438 */
3439 lock_err = tg3_nvram_lock(tp);
3440 err = tg3_halt_cpu(tp, cpu_base);
3441 if (!lock_err)
3442 tg3_nvram_unlock(tp);
3443 if (err)
3444 goto out;
3445
3446 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3447 write_op(tp, cpu_scratch_base + i, 0);
3448 tw32(cpu_base + CPU_STATE, 0xffffffff);
3449 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3450 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3451 write_op(tp, (cpu_scratch_base +
3452 (info->fw_base & 0xffff) +
3453 (i * sizeof(u32))),
3454 be32_to_cpu(info->fw_data[i]));
3455
3456 err = 0;
3457
3458out:
3459 return err;
3460}
3461
3462/* tp->lock is held. */
3463static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3464{
3465 struct fw_info info;
3466 const __be32 *fw_data;
3467 int err, i;
3468
3469 fw_data = (void *)tp->fw->data;
3470
3471 /* Firmware blob starts with version numbers, followed by
3472 start address and length. We are setting complete length.
3473 length = end_address_of_bss - start_address_of_text.
3474 Remainder is the blob to be loaded contiguously
3475 from start address. */
3476
3477 info.fw_base = be32_to_cpu(fw_data[1]);
3478 info.fw_len = tp->fw->size - 12;
3479 info.fw_data = &fw_data[3];
3480
3481 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3482 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3483 &info);
3484 if (err)
3485 return err;
3486
3487 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3488 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3489 &info);
3490 if (err)
3491 return err;
3492
3493 /* Now startup only the RX cpu. */
3494 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3495 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3496
3497 for (i = 0; i < 5; i++) {
3498 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3499 break;
3500 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3501 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3502 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3503 udelay(1000);
3504 }
3505 if (i >= 5) {
3506 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3507 "should be %08x\n", __func__,
3508 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3509 return -ENODEV;
3510 }
3511 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3512 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3513
3514 return 0;
3515}
3516
3517/* tp->lock is held. */
3518static int tg3_load_tso_firmware(struct tg3 *tp)
3519{
3520 struct fw_info info;
3521 const __be32 *fw_data;
3522 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3523 int err, i;
3524
3525 if (tg3_flag(tp, HW_TSO_1) ||
3526 tg3_flag(tp, HW_TSO_2) ||
3527 tg3_flag(tp, HW_TSO_3))
3528 return 0;
3529
3530 fw_data = (void *)tp->fw->data;
3531
3532 /* Firmware blob starts with version numbers, followed by
3533 start address and length. We are setting complete length.
3534 length = end_address_of_bss - start_address_of_text.
3535 Remainder is the blob to be loaded contiguously
3536 from start address. */
3537
3538 info.fw_base = be32_to_cpu(fw_data[1]);
3539 cpu_scratch_size = tp->fw_len;
3540 info.fw_len = tp->fw->size - 12;
3541 info.fw_data = &fw_data[3];
3542
3543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3544 cpu_base = RX_CPU_BASE;
3545 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3546 } else {
3547 cpu_base = TX_CPU_BASE;
3548 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3549 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3550 }
3551
3552 err = tg3_load_firmware_cpu(tp, cpu_base,
3553 cpu_scratch_base, cpu_scratch_size,
3554 &info);
3555 if (err)
3556 return err;
3557
3558 /* Now startup the cpu. */
3559 tw32(cpu_base + CPU_STATE, 0xffffffff);
3560 tw32_f(cpu_base + CPU_PC, info.fw_base);
3561
3562 for (i = 0; i < 5; i++) {
3563 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3564 break;
3565 tw32(cpu_base + CPU_STATE, 0xffffffff);
3566 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3567 tw32_f(cpu_base + CPU_PC, info.fw_base);
3568 udelay(1000);
3569 }
3570 if (i >= 5) {
3571 netdev_err(tp->dev,
3572 "%s fails to set CPU PC, is %08x should be %08x\n",
3573 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3574 return -ENODEV;
3575 }
3576 tw32(cpu_base + CPU_STATE, 0xffffffff);
3577 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3578 return 0;
3579}
3580
3581
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003582/* tp->lock is held. */
Matt Carlson3f007892008-11-03 16:51:36 -08003583static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3584{
3585 u32 addr_high, addr_low;
3586 int i;
3587
3588 addr_high = ((tp->dev->dev_addr[0] << 8) |
3589 tp->dev->dev_addr[1]);
3590 addr_low = ((tp->dev->dev_addr[2] << 24) |
3591 (tp->dev->dev_addr[3] << 16) |
3592 (tp->dev->dev_addr[4] << 8) |
3593 (tp->dev->dev_addr[5] << 0));
3594 for (i = 0; i < 4; i++) {
3595 if (i == 1 && skip_mac_1)
3596 continue;
3597 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3598 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3599 }
3600
3601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3602 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3603 for (i = 0; i < 12; i++) {
3604 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3605 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3606 }
3607 }
3608
3609 addr_high = (tp->dev->dev_addr[0] +
3610 tp->dev->dev_addr[1] +
3611 tp->dev->dev_addr[2] +
3612 tp->dev->dev_addr[3] +
3613 tp->dev->dev_addr[4] +
3614 tp->dev->dev_addr[5]) &
3615 TX_BACKOFF_SEED_MASK;
3616 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3617}
3618
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003619static void tg3_enable_register_access(struct tg3 *tp)
3620{
3621 /*
3622 * Make sure register accesses (indirect or otherwise) will function
3623 * correctly.
3624 */
3625 pci_write_config_dword(tp->pdev,
3626 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3627}
3628
3629static int tg3_power_up(struct tg3 *tp)
3630{
Matt Carlsonbed98292011-07-13 09:27:29 +00003631 int err;
3632
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003633 tg3_enable_register_access(tp);
3634
Matt Carlsonbed98292011-07-13 09:27:29 +00003635 err = pci_set_power_state(tp->pdev, PCI_D0);
3636 if (!err) {
3637 /* Switch out of Vaux if it is a NIC */
3638 tg3_pwrsrc_switch_to_vmain(tp);
3639 } else {
3640 netdev_err(tp->dev, "Transition to D0 failed\n");
3641 }
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003642
Matt Carlsonbed98292011-07-13 09:27:29 +00003643 return err;
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003644}
3645
Matt Carlson4b409522012-02-13 10:20:11 +00003646static int tg3_setup_phy(struct tg3 *, int);
3647
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003648static int tg3_power_down_prepare(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003649{
3650 u32 misc_host_ctrl;
Matt Carlson0a459aa2008-11-03 16:54:15 -08003651 bool device_should_wake, do_low_power;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003652
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003653 tg3_enable_register_access(tp);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003654
3655 /* Restore the CLKREQ setting. */
Joe Perches63c3a662011-04-26 08:12:10 +00003656 if (tg3_flag(tp, CLKREQ_BUG)) {
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003657 u16 lnkctl;
3658
3659 pci_read_config_word(tp->pdev,
Jon Mason708ebb3a2011-06-27 12:56:50 +00003660 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003661 &lnkctl);
3662 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3663 pci_write_config_word(tp->pdev,
Jon Mason708ebb3a2011-06-27 12:56:50 +00003664 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003665 lnkctl);
3666 }
3667
Linus Torvalds1da177e2005-04-16 15:20:36 -07003668 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3669 tw32(TG3PCI_MISC_HOST_CTRL,
3670 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3671
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003672 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
Joe Perches63c3a662011-04-26 08:12:10 +00003673 tg3_flag(tp, WOL_ENABLE);
Matt Carlson05ac4cb2008-11-03 16:53:46 -08003674
Joe Perches63c3a662011-04-26 08:12:10 +00003675 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson0a459aa2008-11-03 16:54:15 -08003676 do_low_power = false;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003677 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
Matt Carlson80096062010-08-02 11:26:06 +00003678 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003679 struct phy_device *phydev;
Matt Carlson0a459aa2008-11-03 16:54:15 -08003680 u32 phyid, advertising;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003681
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00003682 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003683
Matt Carlson80096062010-08-02 11:26:06 +00003684 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003685
Matt Carlsonc6700ce2012-02-13 15:20:15 +00003686 tp->link_config.speed = phydev->speed;
3687 tp->link_config.duplex = phydev->duplex;
3688 tp->link_config.autoneg = phydev->autoneg;
3689 tp->link_config.advertising = phydev->advertising;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003690
3691 advertising = ADVERTISED_TP |
3692 ADVERTISED_Pause |
3693 ADVERTISED_Autoneg |
3694 ADVERTISED_10baseT_Half;
3695
Joe Perches63c3a662011-04-26 08:12:10 +00003696 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3697 if (tg3_flag(tp, WOL_SPEED_100MB))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003698 advertising |=
3699 ADVERTISED_100baseT_Half |
3700 ADVERTISED_100baseT_Full |
3701 ADVERTISED_10baseT_Full;
3702 else
3703 advertising |= ADVERTISED_10baseT_Full;
3704 }
3705
3706 phydev->advertising = advertising;
3707
3708 phy_start_aneg(phydev);
Matt Carlson0a459aa2008-11-03 16:54:15 -08003709
3710 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
Matt Carlson6a443a02010-02-17 15:17:04 +00003711 if (phyid != PHY_ID_BCMAC131) {
3712 phyid &= PHY_BCM_OUI_MASK;
3713 if (phyid == PHY_BCM_OUI_1 ||
3714 phyid == PHY_BCM_OUI_2 ||
3715 phyid == PHY_BCM_OUI_3)
Matt Carlson0a459aa2008-11-03 16:54:15 -08003716 do_low_power = true;
3717 }
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003718 }
Matt Carlsondd477002008-05-25 23:45:58 -07003719 } else {
Matt Carlson20232762008-12-21 20:18:56 -08003720 do_low_power = true;
Matt Carlson0a459aa2008-11-03 16:54:15 -08003721
Matt Carlsonc6700ce2012-02-13 15:20:15 +00003722 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
Matt Carlson80096062010-08-02 11:26:06 +00003723 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003724
Matt Carlson2855b9f2012-02-13 15:20:14 +00003725 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlsondd477002008-05-25 23:45:58 -07003726 tg3_setup_phy(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003727 }
3728
Michael Chanb5d37722006-09-27 16:06:21 -07003729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3730 u32 val;
3731
3732 val = tr32(GRC_VCPU_EXT_CTRL);
3733 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
Joe Perches63c3a662011-04-26 08:12:10 +00003734 } else if (!tg3_flag(tp, ENABLE_ASF)) {
Michael Chan6921d202005-12-13 21:15:53 -08003735 int i;
3736 u32 val;
3737
3738 for (i = 0; i < 200; i++) {
3739 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3740 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3741 break;
3742 msleep(1);
3743 }
3744 }
Joe Perches63c3a662011-04-26 08:12:10 +00003745 if (tg3_flag(tp, WOL_CAP))
Gary Zambranoa85feb82007-05-05 11:52:19 -07003746 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3747 WOL_DRV_STATE_SHUTDOWN |
3748 WOL_DRV_WOL |
3749 WOL_SET_MAGIC_PKT);
Michael Chan6921d202005-12-13 21:15:53 -08003750
Matt Carlson05ac4cb2008-11-03 16:53:46 -08003751 if (device_should_wake) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003752 u32 mac_mode;
3753
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003754 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
Matt Carlsonb4bd2922011-04-20 07:57:41 +00003755 if (do_low_power &&
3756 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3757 tg3_phy_auxctl_write(tp,
3758 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3759 MII_TG3_AUXCTL_PCTL_WOL_EN |
3760 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3761 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
Matt Carlsondd477002008-05-25 23:45:58 -07003762 udelay(40);
3763 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003764
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003765 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chan3f7045c2006-09-27 16:02:29 -07003766 mac_mode = MAC_MODE_PORT_MODE_GMII;
3767 else
3768 mac_mode = MAC_MODE_PORT_MODE_MII;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003769
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003770 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3771 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3772 ASIC_REV_5700) {
Joe Perches63c3a662011-04-26 08:12:10 +00003773 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003774 SPEED_100 : SPEED_10;
3775 if (tg3_5700_link_polarity(tp, speed))
3776 mac_mode |= MAC_MODE_LINK_POLARITY;
3777 else
3778 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3779 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003780 } else {
3781 mac_mode = MAC_MODE_PORT_MODE_TBI;
3782 }
3783
Joe Perches63c3a662011-04-26 08:12:10 +00003784 if (!tg3_flag(tp, 5750_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003785 tw32(MAC_LED_CTRL, tp->led_ctrl);
3786
Matt Carlson05ac4cb2008-11-03 16:53:46 -08003787 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00003788 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3789 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
Matt Carlson05ac4cb2008-11-03 16:53:46 -08003790 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003791
Joe Perches63c3a662011-04-26 08:12:10 +00003792 if (tg3_flag(tp, ENABLE_APE))
Matt Carlsond2394e6b2010-11-24 08:31:47 +00003793 mac_mode |= MAC_MODE_APE_TX_EN |
3794 MAC_MODE_APE_RX_EN |
3795 MAC_MODE_TDE_ENABLE;
Matt Carlson3bda1252008-08-15 14:08:22 -07003796
Linus Torvalds1da177e2005-04-16 15:20:36 -07003797 tw32_f(MAC_MODE, mac_mode);
3798 udelay(100);
3799
3800 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3801 udelay(10);
3802 }
3803
Joe Perches63c3a662011-04-26 08:12:10 +00003804 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003805 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3807 u32 base_val;
3808
3809 base_val = tp->pci_clock_ctrl;
3810 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3811 CLOCK_CTRL_TXCLK_DISABLE);
3812
Michael Chanb401e9e2005-12-19 16:27:04 -08003813 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3814 CLOCK_CTRL_PWRDOWN_PLL133, 40);
Joe Perches63c3a662011-04-26 08:12:10 +00003815 } else if (tg3_flag(tp, 5780_CLASS) ||
3816 tg3_flag(tp, CPMU_PRESENT) ||
Matt Carlson6ff6f812011-05-19 12:12:54 +00003817 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan4cf78e42005-07-25 12:29:19 -07003818 /* do nothing */
Joe Perches63c3a662011-04-26 08:12:10 +00003819 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003820 u32 newbits1, newbits2;
3821
3822 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3823 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3824 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3825 CLOCK_CTRL_TXCLK_DISABLE |
3826 CLOCK_CTRL_ALTCLK);
3827 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
Joe Perches63c3a662011-04-26 08:12:10 +00003828 } else if (tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003829 newbits1 = CLOCK_CTRL_625_CORE;
3830 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3831 } else {
3832 newbits1 = CLOCK_CTRL_ALTCLK;
3833 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3834 }
3835
Michael Chanb401e9e2005-12-19 16:27:04 -08003836 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3837 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003838
Michael Chanb401e9e2005-12-19 16:27:04 -08003839 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3840 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003841
Joe Perches63c3a662011-04-26 08:12:10 +00003842 if (!tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003843 u32 newbits3;
3844
3845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3847 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3848 CLOCK_CTRL_TXCLK_DISABLE |
3849 CLOCK_CTRL_44MHZ_CORE);
3850 } else {
3851 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3852 }
3853
Michael Chanb401e9e2005-12-19 16:27:04 -08003854 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3855 tp->pci_clock_ctrl | newbits3, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003856 }
3857 }
3858
Joe Perches63c3a662011-04-26 08:12:10 +00003859 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
Matt Carlson0a459aa2008-11-03 16:54:15 -08003860 tg3_power_down_phy(tp, do_low_power);
Michael Chan6921d202005-12-13 21:15:53 -08003861
Matt Carlsoncd0d7222011-07-13 09:27:33 +00003862 tg3_frob_aux_power(tp, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003863
3864 /* Workaround for unstable PLL clock */
3865 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3866 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3867 u32 val = tr32(0x7d00);
3868
3869 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3870 tw32(0x7d00, val);
Joe Perches63c3a662011-04-26 08:12:10 +00003871 if (!tg3_flag(tp, ENABLE_ASF)) {
Michael Chanec41c7d2006-01-17 02:40:55 -08003872 int err;
3873
3874 err = tg3_nvram_lock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003875 tg3_halt_cpu(tp, RX_CPU_BASE);
Michael Chanec41c7d2006-01-17 02:40:55 -08003876 if (!err)
3877 tg3_nvram_unlock(tp);
Michael Chan6921d202005-12-13 21:15:53 -08003878 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003879 }
3880
Michael Chanbbadf502006-04-06 21:46:34 -07003881 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3882
Linus Torvalds1da177e2005-04-16 15:20:36 -07003883 return 0;
3884}
3885
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003886static void tg3_power_down(struct tg3 *tp)
3887{
3888 tg3_power_down_prepare(tp);
3889
Joe Perches63c3a662011-04-26 08:12:10 +00003890 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003891 pci_set_power_state(tp->pdev, PCI_D3hot);
3892}
3893
Linus Torvalds1da177e2005-04-16 15:20:36 -07003894static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3895{
3896 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3897 case MII_TG3_AUX_STAT_10HALF:
3898 *speed = SPEED_10;
3899 *duplex = DUPLEX_HALF;
3900 break;
3901
3902 case MII_TG3_AUX_STAT_10FULL:
3903 *speed = SPEED_10;
3904 *duplex = DUPLEX_FULL;
3905 break;
3906
3907 case MII_TG3_AUX_STAT_100HALF:
3908 *speed = SPEED_100;
3909 *duplex = DUPLEX_HALF;
3910 break;
3911
3912 case MII_TG3_AUX_STAT_100FULL:
3913 *speed = SPEED_100;
3914 *duplex = DUPLEX_FULL;
3915 break;
3916
3917 case MII_TG3_AUX_STAT_1000HALF:
3918 *speed = SPEED_1000;
3919 *duplex = DUPLEX_HALF;
3920 break;
3921
3922 case MII_TG3_AUX_STAT_1000FULL:
3923 *speed = SPEED_1000;
3924 *duplex = DUPLEX_FULL;
3925 break;
3926
3927 default:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003928 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Michael Chan715116a2006-09-27 16:09:25 -07003929 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3930 SPEED_10;
3931 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3932 DUPLEX_HALF;
3933 break;
3934 }
Matt Carlsone7405222012-02-13 15:20:16 +00003935 *speed = SPEED_UNKNOWN;
3936 *duplex = DUPLEX_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003937 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07003938 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003939}
3940
Matt Carlson42b64a42011-05-19 12:12:49 +00003941static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003942{
Matt Carlson42b64a42011-05-19 12:12:49 +00003943 int err = 0;
3944 u32 val, new_adv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003945
Matt Carlson42b64a42011-05-19 12:12:49 +00003946 new_adv = ADVERTISE_CSMA;
Hiroaki SHIMODA202ff1c2011-11-22 04:05:41 +00003947 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
Matt Carlsonf88788f2011-12-14 11:10:00 +00003948 new_adv |= mii_advertise_flowctrl(flowctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003949
Matt Carlson42b64a42011-05-19 12:12:49 +00003950 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3951 if (err)
3952 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003953
Matt Carlson4f272092011-12-14 11:09:57 +00003954 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3955 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003956
Matt Carlson4f272092011-12-14 11:09:57 +00003957 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3958 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3959 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003960
Matt Carlson4f272092011-12-14 11:09:57 +00003961 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3962 if (err)
3963 goto done;
3964 }
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003965
Matt Carlson42b64a42011-05-19 12:12:49 +00003966 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3967 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003968
Matt Carlson42b64a42011-05-19 12:12:49 +00003969 tw32(TG3_CPMU_EEE_MODE,
3970 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003971
Matt Carlson42b64a42011-05-19 12:12:49 +00003972 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3973 if (!err) {
3974 u32 err2;
Matt Carlson52b02d02010-10-14 10:37:41 +00003975
Matt Carlsona6b68da2010-12-06 08:28:52 +00003976 val = 0;
Matt Carlson42b64a42011-05-19 12:12:49 +00003977 /* Advertise 100-BaseTX EEE ability */
3978 if (advertise & ADVERTISED_100baseT_Full)
3979 val |= MDIO_AN_EEE_ADV_100TX;
3980 /* Advertise 1000-BaseT EEE ability */
3981 if (advertise & ADVERTISED_1000baseT_Full)
3982 val |= MDIO_AN_EEE_ADV_1000T;
3983 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
Matt Carlsonb715ce92011-07-20 10:20:52 +00003984 if (err)
3985 val = 0;
3986
3987 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3988 case ASIC_REV_5717:
3989 case ASIC_REV_57765:
Matt Carlson55086ad2011-12-14 11:09:59 +00003990 case ASIC_REV_57766:
Matt Carlsonb715ce92011-07-20 10:20:52 +00003991 case ASIC_REV_5719:
3992 /* If we advertised any eee advertisements above... */
3993 if (val)
3994 val = MII_TG3_DSP_TAP26_ALNOKO |
3995 MII_TG3_DSP_TAP26_RMRXSTO |
3996 MII_TG3_DSP_TAP26_OPCSINPT;
3997 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3998 /* Fall through */
3999 case ASIC_REV_5720:
4000 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4001 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4002 MII_TG3_DSP_CH34TP2_HIBW01);
4003 }
Matt Carlson52b02d02010-10-14 10:37:41 +00004004
Matt Carlson42b64a42011-05-19 12:12:49 +00004005 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
4006 if (!err)
4007 err = err2;
4008 }
4009
4010done:
4011 return err;
4012}
4013
4014static void tg3_phy_copper_begin(struct tg3 *tp)
4015{
Matt Carlsond13ba512012-02-22 12:35:19 +00004016 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4017 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4018 u32 adv, fc;
Matt Carlson42b64a42011-05-19 12:12:49 +00004019
Matt Carlsond13ba512012-02-22 12:35:19 +00004020 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
4021 adv = ADVERTISED_10baseT_Half |
4022 ADVERTISED_10baseT_Full;
4023 if (tg3_flag(tp, WOL_SPEED_100MB))
4024 adv |= ADVERTISED_100baseT_Half |
4025 ADVERTISED_100baseT_Full;
Matt Carlson42b64a42011-05-19 12:12:49 +00004026
Matt Carlsond13ba512012-02-22 12:35:19 +00004027 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
Matt Carlson42b64a42011-05-19 12:12:49 +00004028 } else {
Matt Carlsond13ba512012-02-22 12:35:19 +00004029 adv = tp->link_config.advertising;
4030 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4031 adv &= ~(ADVERTISED_1000baseT_Half |
4032 ADVERTISED_1000baseT_Full);
4033
4034 fc = tp->link_config.flowctrl;
Matt Carlson42b64a42011-05-19 12:12:49 +00004035 }
4036
Matt Carlsond13ba512012-02-22 12:35:19 +00004037 tg3_phy_autoneg_cfg(tp, adv, fc);
Matt Carlson52b02d02010-10-14 10:37:41 +00004038
Matt Carlsond13ba512012-02-22 12:35:19 +00004039 tg3_writephy(tp, MII_BMCR,
4040 BMCR_ANENABLE | BMCR_ANRESTART);
4041 } else {
4042 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004043 u32 bmcr, orig_bmcr;
4044
4045 tp->link_config.active_speed = tp->link_config.speed;
4046 tp->link_config.active_duplex = tp->link_config.duplex;
4047
4048 bmcr = 0;
4049 switch (tp->link_config.speed) {
4050 default:
4051 case SPEED_10:
4052 break;
4053
4054 case SPEED_100:
4055 bmcr |= BMCR_SPEED100;
4056 break;
4057
4058 case SPEED_1000:
Matt Carlson221c5632011-06-13 13:39:01 +00004059 bmcr |= BMCR_SPEED1000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004060 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07004061 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004062
4063 if (tp->link_config.duplex == DUPLEX_FULL)
4064 bmcr |= BMCR_FULLDPLX;
4065
4066 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4067 (bmcr != orig_bmcr)) {
4068 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4069 for (i = 0; i < 1500; i++) {
4070 u32 tmp;
4071
4072 udelay(10);
4073 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4074 tg3_readphy(tp, MII_BMSR, &tmp))
4075 continue;
4076 if (!(tmp & BMSR_LSTATUS)) {
4077 udelay(40);
4078 break;
4079 }
4080 }
4081 tg3_writephy(tp, MII_BMCR, bmcr);
4082 udelay(40);
4083 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004084 }
4085}
4086
4087static int tg3_init_5401phy_dsp(struct tg3 *tp)
4088{
4089 int err;
4090
4091 /* Turn off tap power management. */
4092 /* Set Extended packet length bit */
Matt Carlsonb4bd2922011-04-20 07:57:41 +00004093 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004094
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00004095 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4096 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4097 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4098 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4099 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004100
4101 udelay(40);
4102
4103 return err;
4104}
4105
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004106static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004107{
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004108 u32 advmsk, tgtadv, advertising;
Michael Chan3600d912006-12-07 00:21:48 -08004109
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004110 advertising = tp->link_config.advertising;
4111 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004112
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004113 advmsk = ADVERTISE_ALL;
4114 if (tp->link_config.active_duplex == DUPLEX_FULL) {
Matt Carlsonf88788f2011-12-14 11:10:00 +00004115 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004116 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4117 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004118
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004119 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4120 return false;
4121
4122 if ((*lcladv & advmsk) != tgtadv)
4123 return false;
Matt Carlsonb99d2a52011-08-31 11:44:47 +00004124
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004125 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004126 u32 tg3_ctrl;
4127
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004128 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
Michael Chan3600d912006-12-07 00:21:48 -08004129
Matt Carlson221c5632011-06-13 13:39:01 +00004130 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004131 return false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004132
Matt Carlson3198e072012-02-13 15:20:10 +00004133 if (tgtadv &&
4134 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4135 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
4136 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4137 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4138 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4139 } else {
4140 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4141 }
4142
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004143 if (tg3_ctrl != tgtadv)
4144 return false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004145 }
Matt Carlson93a700a2011-08-31 11:44:54 +00004146
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004147 return true;
Matt Carlsonef167e22007-12-20 20:10:01 -08004148}
4149
Matt Carlson859edb22011-12-08 14:40:16 +00004150static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4151{
4152 u32 lpeth = 0;
4153
4154 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4155 u32 val;
4156
4157 if (tg3_readphy(tp, MII_STAT1000, &val))
4158 return false;
4159
4160 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4161 }
4162
4163 if (tg3_readphy(tp, MII_LPA, rmtadv))
4164 return false;
4165
4166 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4167 tp->link_config.rmt_adv = lpeth;
4168
4169 return true;
4170}
4171
Linus Torvalds1da177e2005-04-16 15:20:36 -07004172static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4173{
4174 int current_link_up;
Matt Carlsonf833c4c2010-09-15 09:00:01 +00004175 u32 bmsr, val;
Matt Carlsonef167e22007-12-20 20:10:01 -08004176 u32 lcl_adv, rmt_adv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004177 u16 current_speed;
4178 u8 current_duplex;
4179 int i, err;
4180
4181 tw32(MAC_EVENT, 0);
4182
4183 tw32_f(MAC_STATUS,
4184 (MAC_STATUS_SYNC_CHANGED |
4185 MAC_STATUS_CFG_CHANGED |
4186 MAC_STATUS_MI_COMPLETION |
4187 MAC_STATUS_LNKSTATE_CHANGED));
4188 udelay(40);
4189
Matt Carlson8ef21422008-05-02 16:47:53 -07004190 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4191 tw32_f(MAC_MI_MODE,
4192 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4193 udelay(80);
4194 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004195
Matt Carlsonb4bd2922011-04-20 07:57:41 +00004196 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004197
4198 /* Some third-party PHYs need to be reset on link going
4199 * down.
4200 */
4201 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
4203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
4204 netif_carrier_ok(tp->dev)) {
4205 tg3_readphy(tp, MII_BMSR, &bmsr);
4206 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4207 !(bmsr & BMSR_LSTATUS))
4208 force_reset = 1;
4209 }
4210 if (force_reset)
4211 tg3_phy_reset(tp);
4212
Matt Carlson79eb6902010-02-17 15:17:03 +00004213 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004214 tg3_readphy(tp, MII_BMSR, &bmsr);
4215 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
Joe Perches63c3a662011-04-26 08:12:10 +00004216 !tg3_flag(tp, INIT_COMPLETE))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004217 bmsr = 0;
4218
4219 if (!(bmsr & BMSR_LSTATUS)) {
4220 err = tg3_init_5401phy_dsp(tp);
4221 if (err)
4222 return err;
4223
4224 tg3_readphy(tp, MII_BMSR, &bmsr);
4225 for (i = 0; i < 1000; i++) {
4226 udelay(10);
4227 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4228 (bmsr & BMSR_LSTATUS)) {
4229 udelay(40);
4230 break;
4231 }
4232 }
4233
Matt Carlson79eb6902010-02-17 15:17:03 +00004234 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4235 TG3_PHY_REV_BCM5401_B0 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004236 !(bmsr & BMSR_LSTATUS) &&
4237 tp->link_config.active_speed == SPEED_1000) {
4238 err = tg3_phy_reset(tp);
4239 if (!err)
4240 err = tg3_init_5401phy_dsp(tp);
4241 if (err)
4242 return err;
4243 }
4244 }
4245 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4246 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
4247 /* 5701 {A0,B0} CRC bug workaround */
4248 tg3_writephy(tp, 0x15, 0x0a75);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00004249 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4250 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4251 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004252 }
4253
4254 /* Clear pending interrupts... */
Matt Carlsonf833c4c2010-09-15 09:00:01 +00004255 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4256 tg3_readphy(tp, MII_TG3_ISTAT, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004257
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004258 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004259 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004260 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004261 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4262
4263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
4264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
4265 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4266 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4267 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4268 else
4269 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4270 }
4271
4272 current_link_up = 0;
Matt Carlsone7405222012-02-13 15:20:16 +00004273 current_speed = SPEED_UNKNOWN;
4274 current_duplex = DUPLEX_UNKNOWN;
Matt Carlsone348c5e2011-11-21 15:01:20 +00004275 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
Matt Carlson859edb22011-12-08 14:40:16 +00004276 tp->link_config.rmt_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004277
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004278 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
Matt Carlson15ee95c2011-04-20 07:57:40 +00004279 err = tg3_phy_auxctl_read(tp,
4280 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4281 &val);
4282 if (!err && !(val & (1 << 10))) {
Matt Carlsonb4bd2922011-04-20 07:57:41 +00004283 tg3_phy_auxctl_write(tp,
4284 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4285 val | (1 << 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004286 goto relink;
4287 }
4288 }
4289
4290 bmsr = 0;
4291 for (i = 0; i < 100; i++) {
4292 tg3_readphy(tp, MII_BMSR, &bmsr);
4293 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4294 (bmsr & BMSR_LSTATUS))
4295 break;
4296 udelay(40);
4297 }
4298
4299 if (bmsr & BMSR_LSTATUS) {
4300 u32 aux_stat, bmcr;
4301
4302 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4303 for (i = 0; i < 2000; i++) {
4304 udelay(10);
4305 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4306 aux_stat)
4307 break;
4308 }
4309
4310 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4311 &current_speed,
4312 &current_duplex);
4313
4314 bmcr = 0;
4315 for (i = 0; i < 200; i++) {
4316 tg3_readphy(tp, MII_BMCR, &bmcr);
4317 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4318 continue;
4319 if (bmcr && bmcr != 0x7fff)
4320 break;
4321 udelay(10);
4322 }
4323
Matt Carlsonef167e22007-12-20 20:10:01 -08004324 lcl_adv = 0;
4325 rmt_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004326
Matt Carlsonef167e22007-12-20 20:10:01 -08004327 tp->link_config.active_speed = current_speed;
4328 tp->link_config.active_duplex = current_duplex;
4329
4330 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4331 if ((bmcr & BMCR_ANENABLE) &&
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004332 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
Matt Carlson859edb22011-12-08 14:40:16 +00004333 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
Matt Carlsone2bf73e2011-12-08 14:40:15 +00004334 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004335 } else {
4336 if (!(bmcr & BMCR_ANENABLE) &&
4337 tp->link_config.speed == current_speed &&
Matt Carlsonef167e22007-12-20 20:10:01 -08004338 tp->link_config.duplex == current_duplex &&
4339 tp->link_config.flowctrl ==
4340 tp->link_config.active_flowctrl) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004341 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004342 }
4343 }
4344
Matt Carlsonef167e22007-12-20 20:10:01 -08004345 if (current_link_up == 1 &&
Matt Carlsone348c5e2011-11-21 15:01:20 +00004346 tp->link_config.active_duplex == DUPLEX_FULL) {
4347 u32 reg, bit;
4348
4349 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4350 reg = MII_TG3_FET_GEN_STAT;
4351 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4352 } else {
4353 reg = MII_TG3_EXT_STAT;
4354 bit = MII_TG3_EXT_STAT_MDIX;
4355 }
4356
4357 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4358 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4359
Matt Carlsonef167e22007-12-20 20:10:01 -08004360 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
Matt Carlsone348c5e2011-11-21 15:01:20 +00004361 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004362 }
4363
Linus Torvalds1da177e2005-04-16 15:20:36 -07004364relink:
Matt Carlson80096062010-08-02 11:26:06 +00004365 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004366 tg3_phy_copper_begin(tp);
4367
Matt Carlsonf833c4c2010-09-15 09:00:01 +00004368 tg3_readphy(tp, MII_BMSR, &bmsr);
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00004369 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4370 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004371 current_link_up = 1;
4372 }
4373
4374 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4375 if (current_link_up == 1) {
4376 if (tp->link_config.active_speed == SPEED_100 ||
4377 tp->link_config.active_speed == SPEED_10)
4378 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4379 else
4380 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004381 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
Matt Carlson7f97a4b2009-08-25 10:10:03 +00004382 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4383 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004384 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4385
4386 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4387 if (tp->link_config.active_duplex == DUPLEX_HALF)
4388 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4389
Linus Torvalds1da177e2005-04-16 15:20:36 -07004390 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07004391 if (current_link_up == 1 &&
4392 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004393 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07004394 else
4395 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004396 }
4397
4398 /* ??? Without this setting Netgear GA302T PHY does not
4399 * ??? send/receive packets...
4400 */
Matt Carlson79eb6902010-02-17 15:17:03 +00004401 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004402 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4403 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4404 tw32_f(MAC_MI_MODE, tp->mi_mode);
4405 udelay(80);
4406 }
4407
4408 tw32_f(MAC_MODE, tp->mac_mode);
4409 udelay(40);
4410
Matt Carlson52b02d02010-10-14 10:37:41 +00004411 tg3_phy_eee_adjust(tp, current_link_up);
4412
Joe Perches63c3a662011-04-26 08:12:10 +00004413 if (tg3_flag(tp, USE_LINKCHG_REG)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004414 /* Polled via timer. */
4415 tw32_f(MAC_EVENT, 0);
4416 } else {
4417 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4418 }
4419 udelay(40);
4420
4421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4422 current_link_up == 1 &&
4423 tp->link_config.active_speed == SPEED_1000 &&
Joe Perches63c3a662011-04-26 08:12:10 +00004424 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004425 udelay(120);
4426 tw32_f(MAC_STATUS,
4427 (MAC_STATUS_SYNC_CHANGED |
4428 MAC_STATUS_CFG_CHANGED));
4429 udelay(40);
4430 tg3_write_mem(tp,
4431 NIC_SRAM_FIRMWARE_MBOX,
4432 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4433 }
4434
Matt Carlson5e7dfd02008-11-21 17:18:16 -08004435 /* Prevent send BD corruption. */
Joe Perches63c3a662011-04-26 08:12:10 +00004436 if (tg3_flag(tp, CLKREQ_BUG)) {
Matt Carlson5e7dfd02008-11-21 17:18:16 -08004437 u16 oldlnkctl, newlnkctl;
4438
4439 pci_read_config_word(tp->pdev,
Jon Mason708ebb3a2011-06-27 12:56:50 +00004440 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
Matt Carlson5e7dfd02008-11-21 17:18:16 -08004441 &oldlnkctl);
4442 if (tp->link_config.active_speed == SPEED_100 ||
4443 tp->link_config.active_speed == SPEED_10)
4444 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4445 else
4446 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4447 if (newlnkctl != oldlnkctl)
4448 pci_write_config_word(tp->pdev,
Matt Carlson93a700a2011-08-31 11:44:54 +00004449 pci_pcie_cap(tp->pdev) +
4450 PCI_EXP_LNKCTL, newlnkctl);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08004451 }
4452
Linus Torvalds1da177e2005-04-16 15:20:36 -07004453 if (current_link_up != netif_carrier_ok(tp->dev)) {
4454 if (current_link_up)
4455 netif_carrier_on(tp->dev);
4456 else
4457 netif_carrier_off(tp->dev);
4458 tg3_link_report(tp);
4459 }
4460
4461 return 0;
4462}
4463
4464struct tg3_fiber_aneginfo {
4465 int state;
4466#define ANEG_STATE_UNKNOWN 0
4467#define ANEG_STATE_AN_ENABLE 1
4468#define ANEG_STATE_RESTART_INIT 2
4469#define ANEG_STATE_RESTART 3
4470#define ANEG_STATE_DISABLE_LINK_OK 4
4471#define ANEG_STATE_ABILITY_DETECT_INIT 5
4472#define ANEG_STATE_ABILITY_DETECT 6
4473#define ANEG_STATE_ACK_DETECT_INIT 7
4474#define ANEG_STATE_ACK_DETECT 8
4475#define ANEG_STATE_COMPLETE_ACK_INIT 9
4476#define ANEG_STATE_COMPLETE_ACK 10
4477#define ANEG_STATE_IDLE_DETECT_INIT 11
4478#define ANEG_STATE_IDLE_DETECT 12
4479#define ANEG_STATE_LINK_OK 13
4480#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4481#define ANEG_STATE_NEXT_PAGE_WAIT 15
4482
4483 u32 flags;
4484#define MR_AN_ENABLE 0x00000001
4485#define MR_RESTART_AN 0x00000002
4486#define MR_AN_COMPLETE 0x00000004
4487#define MR_PAGE_RX 0x00000008
4488#define MR_NP_LOADED 0x00000010
4489#define MR_TOGGLE_TX 0x00000020
4490#define MR_LP_ADV_FULL_DUPLEX 0x00000040
4491#define MR_LP_ADV_HALF_DUPLEX 0x00000080
4492#define MR_LP_ADV_SYM_PAUSE 0x00000100
4493#define MR_LP_ADV_ASYM_PAUSE 0x00000200
4494#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4495#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4496#define MR_LP_ADV_NEXT_PAGE 0x00001000
4497#define MR_TOGGLE_RX 0x00002000
4498#define MR_NP_RX 0x00004000
4499
4500#define MR_LINK_OK 0x80000000
4501
4502 unsigned long link_time, cur_time;
4503
4504 u32 ability_match_cfg;
4505 int ability_match_count;
4506
4507 char ability_match, idle_match, ack_match;
4508
4509 u32 txconfig, rxconfig;
4510#define ANEG_CFG_NP 0x00000080
4511#define ANEG_CFG_ACK 0x00000040
4512#define ANEG_CFG_RF2 0x00000020
4513#define ANEG_CFG_RF1 0x00000010
4514#define ANEG_CFG_PS2 0x00000001
4515#define ANEG_CFG_PS1 0x00008000
4516#define ANEG_CFG_HD 0x00004000
4517#define ANEG_CFG_FD 0x00002000
4518#define ANEG_CFG_INVAL 0x00001f06
4519
4520};
4521#define ANEG_OK 0
4522#define ANEG_DONE 1
4523#define ANEG_TIMER_ENAB 2
4524#define ANEG_FAILED -1
4525
4526#define ANEG_STATE_SETTLE_TIME 10000
4527
4528static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4529 struct tg3_fiber_aneginfo *ap)
4530{
Matt Carlson5be73b42007-12-20 20:09:29 -08004531 u16 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004532 unsigned long delta;
4533 u32 rx_cfg_reg;
4534 int ret;
4535
4536 if (ap->state == ANEG_STATE_UNKNOWN) {
4537 ap->rxconfig = 0;
4538 ap->link_time = 0;
4539 ap->cur_time = 0;
4540 ap->ability_match_cfg = 0;
4541 ap->ability_match_count = 0;
4542 ap->ability_match = 0;
4543 ap->idle_match = 0;
4544 ap->ack_match = 0;
4545 }
4546 ap->cur_time++;
4547
4548 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4549 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4550
4551 if (rx_cfg_reg != ap->ability_match_cfg) {
4552 ap->ability_match_cfg = rx_cfg_reg;
4553 ap->ability_match = 0;
4554 ap->ability_match_count = 0;
4555 } else {
4556 if (++ap->ability_match_count > 1) {
4557 ap->ability_match = 1;
4558 ap->ability_match_cfg = rx_cfg_reg;
4559 }
4560 }
4561 if (rx_cfg_reg & ANEG_CFG_ACK)
4562 ap->ack_match = 1;
4563 else
4564 ap->ack_match = 0;
4565
4566 ap->idle_match = 0;
4567 } else {
4568 ap->idle_match = 1;
4569 ap->ability_match_cfg = 0;
4570 ap->ability_match_count = 0;
4571 ap->ability_match = 0;
4572 ap->ack_match = 0;
4573
4574 rx_cfg_reg = 0;
4575 }
4576
4577 ap->rxconfig = rx_cfg_reg;
4578 ret = ANEG_OK;
4579
Matt Carlson33f401a2010-04-05 10:19:27 +00004580 switch (ap->state) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004581 case ANEG_STATE_UNKNOWN:
4582 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4583 ap->state = ANEG_STATE_AN_ENABLE;
4584
4585 /* fallthru */
4586 case ANEG_STATE_AN_ENABLE:
4587 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4588 if (ap->flags & MR_AN_ENABLE) {
4589 ap->link_time = 0;
4590 ap->cur_time = 0;
4591 ap->ability_match_cfg = 0;
4592 ap->ability_match_count = 0;
4593 ap->ability_match = 0;
4594 ap->idle_match = 0;
4595 ap->ack_match = 0;
4596
4597 ap->state = ANEG_STATE_RESTART_INIT;
4598 } else {
4599 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4600 }
4601 break;
4602
4603 case ANEG_STATE_RESTART_INIT:
4604 ap->link_time = ap->cur_time;
4605 ap->flags &= ~(MR_NP_LOADED);
4606 ap->txconfig = 0;
4607 tw32(MAC_TX_AUTO_NEG, 0);
4608 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4609 tw32_f(MAC_MODE, tp->mac_mode);
4610 udelay(40);
4611
4612 ret = ANEG_TIMER_ENAB;
4613 ap->state = ANEG_STATE_RESTART;
4614
4615 /* fallthru */
4616 case ANEG_STATE_RESTART:
4617 delta = ap->cur_time - ap->link_time;
Matt Carlson859a588792010-04-05 10:19:28 +00004618 if (delta > ANEG_STATE_SETTLE_TIME)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004619 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
Matt Carlson859a588792010-04-05 10:19:28 +00004620 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004621 ret = ANEG_TIMER_ENAB;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004622 break;
4623
4624 case ANEG_STATE_DISABLE_LINK_OK:
4625 ret = ANEG_DONE;
4626 break;
4627
4628 case ANEG_STATE_ABILITY_DETECT_INIT:
4629 ap->flags &= ~(MR_TOGGLE_TX);
Matt Carlson5be73b42007-12-20 20:09:29 -08004630 ap->txconfig = ANEG_CFG_FD;
4631 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4632 if (flowctrl & ADVERTISE_1000XPAUSE)
4633 ap->txconfig |= ANEG_CFG_PS1;
4634 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4635 ap->txconfig |= ANEG_CFG_PS2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004636 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4637 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4638 tw32_f(MAC_MODE, tp->mac_mode);
4639 udelay(40);
4640
4641 ap->state = ANEG_STATE_ABILITY_DETECT;
4642 break;
4643
4644 case ANEG_STATE_ABILITY_DETECT:
Matt Carlson859a588792010-04-05 10:19:28 +00004645 if (ap->ability_match != 0 && ap->rxconfig != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004646 ap->state = ANEG_STATE_ACK_DETECT_INIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004647 break;
4648
4649 case ANEG_STATE_ACK_DETECT_INIT:
4650 ap->txconfig |= ANEG_CFG_ACK;
4651 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4652 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4653 tw32_f(MAC_MODE, tp->mac_mode);
4654 udelay(40);
4655
4656 ap->state = ANEG_STATE_ACK_DETECT;
4657
4658 /* fallthru */
4659 case ANEG_STATE_ACK_DETECT:
4660 if (ap->ack_match != 0) {
4661 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4662 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4663 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4664 } else {
4665 ap->state = ANEG_STATE_AN_ENABLE;
4666 }
4667 } else if (ap->ability_match != 0 &&
4668 ap->rxconfig == 0) {
4669 ap->state = ANEG_STATE_AN_ENABLE;
4670 }
4671 break;
4672
4673 case ANEG_STATE_COMPLETE_ACK_INIT:
4674 if (ap->rxconfig & ANEG_CFG_INVAL) {
4675 ret = ANEG_FAILED;
4676 break;
4677 }
4678 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4679 MR_LP_ADV_HALF_DUPLEX |
4680 MR_LP_ADV_SYM_PAUSE |
4681 MR_LP_ADV_ASYM_PAUSE |
4682 MR_LP_ADV_REMOTE_FAULT1 |
4683 MR_LP_ADV_REMOTE_FAULT2 |
4684 MR_LP_ADV_NEXT_PAGE |
4685 MR_TOGGLE_RX |
4686 MR_NP_RX);
4687 if (ap->rxconfig & ANEG_CFG_FD)
4688 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4689 if (ap->rxconfig & ANEG_CFG_HD)
4690 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4691 if (ap->rxconfig & ANEG_CFG_PS1)
4692 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4693 if (ap->rxconfig & ANEG_CFG_PS2)
4694 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4695 if (ap->rxconfig & ANEG_CFG_RF1)
4696 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4697 if (ap->rxconfig & ANEG_CFG_RF2)
4698 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4699 if (ap->rxconfig & ANEG_CFG_NP)
4700 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4701
4702 ap->link_time = ap->cur_time;
4703
4704 ap->flags ^= (MR_TOGGLE_TX);
4705 if (ap->rxconfig & 0x0008)
4706 ap->flags |= MR_TOGGLE_RX;
4707 if (ap->rxconfig & ANEG_CFG_NP)
4708 ap->flags |= MR_NP_RX;
4709 ap->flags |= MR_PAGE_RX;
4710
4711 ap->state = ANEG_STATE_COMPLETE_ACK;
4712 ret = ANEG_TIMER_ENAB;
4713 break;
4714
4715 case ANEG_STATE_COMPLETE_ACK:
4716 if (ap->ability_match != 0 &&
4717 ap->rxconfig == 0) {
4718 ap->state = ANEG_STATE_AN_ENABLE;
4719 break;
4720 }
4721 delta = ap->cur_time - ap->link_time;
4722 if (delta > ANEG_STATE_SETTLE_TIME) {
4723 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4724 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4725 } else {
4726 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4727 !(ap->flags & MR_NP_RX)) {
4728 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4729 } else {
4730 ret = ANEG_FAILED;
4731 }
4732 }
4733 }
4734 break;
4735
4736 case ANEG_STATE_IDLE_DETECT_INIT:
4737 ap->link_time = ap->cur_time;
4738 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4739 tw32_f(MAC_MODE, tp->mac_mode);
4740 udelay(40);
4741
4742 ap->state = ANEG_STATE_IDLE_DETECT;
4743 ret = ANEG_TIMER_ENAB;
4744 break;
4745
4746 case ANEG_STATE_IDLE_DETECT:
4747 if (ap->ability_match != 0 &&
4748 ap->rxconfig == 0) {
4749 ap->state = ANEG_STATE_AN_ENABLE;
4750 break;
4751 }
4752 delta = ap->cur_time - ap->link_time;
4753 if (delta > ANEG_STATE_SETTLE_TIME) {
4754 /* XXX another gem from the Broadcom driver :( */
4755 ap->state = ANEG_STATE_LINK_OK;
4756 }
4757 break;
4758
4759 case ANEG_STATE_LINK_OK:
4760 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4761 ret = ANEG_DONE;
4762 break;
4763
4764 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4765 /* ??? unimplemented */
4766 break;
4767
4768 case ANEG_STATE_NEXT_PAGE_WAIT:
4769 /* ??? unimplemented */
4770 break;
4771
4772 default:
4773 ret = ANEG_FAILED;
4774 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07004775 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004776
4777 return ret;
4778}
4779
Matt Carlson5be73b42007-12-20 20:09:29 -08004780static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004781{
4782 int res = 0;
4783 struct tg3_fiber_aneginfo aninfo;
4784 int status = ANEG_FAILED;
4785 unsigned int tick;
4786 u32 tmp;
4787
4788 tw32_f(MAC_TX_AUTO_NEG, 0);
4789
4790 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4791 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4792 udelay(40);
4793
4794 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4795 udelay(40);
4796
4797 memset(&aninfo, 0, sizeof(aninfo));
4798 aninfo.flags |= MR_AN_ENABLE;
4799 aninfo.state = ANEG_STATE_UNKNOWN;
4800 aninfo.cur_time = 0;
4801 tick = 0;
4802 while (++tick < 195000) {
4803 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4804 if (status == ANEG_DONE || status == ANEG_FAILED)
4805 break;
4806
4807 udelay(1);
4808 }
4809
4810 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4811 tw32_f(MAC_MODE, tp->mac_mode);
4812 udelay(40);
4813
Matt Carlson5be73b42007-12-20 20:09:29 -08004814 *txflags = aninfo.txconfig;
4815 *rxflags = aninfo.flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004816
4817 if (status == ANEG_DONE &&
4818 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4819 MR_LP_ADV_FULL_DUPLEX)))
4820 res = 1;
4821
4822 return res;
4823}
4824
4825static void tg3_init_bcm8002(struct tg3 *tp)
4826{
4827 u32 mac_status = tr32(MAC_STATUS);
4828 int i;
4829
4830 /* Reset when initting first time or we have a link. */
Joe Perches63c3a662011-04-26 08:12:10 +00004831 if (tg3_flag(tp, INIT_COMPLETE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004832 !(mac_status & MAC_STATUS_PCS_SYNCED))
4833 return;
4834
4835 /* Set PLL lock range. */
4836 tg3_writephy(tp, 0x16, 0x8007);
4837
4838 /* SW reset */
4839 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4840
4841 /* Wait for reset to complete. */
4842 /* XXX schedule_timeout() ... */
4843 for (i = 0; i < 500; i++)
4844 udelay(10);
4845
4846 /* Config mode; select PMA/Ch 1 regs. */
4847 tg3_writephy(tp, 0x10, 0x8411);
4848
4849 /* Enable auto-lock and comdet, select txclk for tx. */
4850 tg3_writephy(tp, 0x11, 0x0a10);
4851
4852 tg3_writephy(tp, 0x18, 0x00a0);
4853 tg3_writephy(tp, 0x16, 0x41ff);
4854
4855 /* Assert and deassert POR. */
4856 tg3_writephy(tp, 0x13, 0x0400);
4857 udelay(40);
4858 tg3_writephy(tp, 0x13, 0x0000);
4859
4860 tg3_writephy(tp, 0x11, 0x0a50);
4861 udelay(40);
4862 tg3_writephy(tp, 0x11, 0x0a10);
4863
4864 /* Wait for signal to stabilize */
4865 /* XXX schedule_timeout() ... */
4866 for (i = 0; i < 15000; i++)
4867 udelay(10);
4868
4869 /* Deselect the channel register so we can read the PHYID
4870 * later.
4871 */
4872 tg3_writephy(tp, 0x10, 0x8011);
4873}
4874
4875static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4876{
Matt Carlson82cd3d12007-12-20 20:09:00 -08004877 u16 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004878 u32 sg_dig_ctrl, sg_dig_status;
4879 u32 serdes_cfg, expected_sg_dig_ctrl;
4880 int workaround, port_a;
4881 int current_link_up;
4882
4883 serdes_cfg = 0;
4884 expected_sg_dig_ctrl = 0;
4885 workaround = 0;
4886 port_a = 1;
4887 current_link_up = 0;
4888
4889 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4890 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4891 workaround = 1;
4892 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4893 port_a = 0;
4894
4895 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4896 /* preserve bits 20-23 for voltage regulator */
4897 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4898 }
4899
4900 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4901
4902 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004903 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004904 if (workaround) {
4905 u32 val = serdes_cfg;
4906
4907 if (port_a)
4908 val |= 0xc010000;
4909 else
4910 val |= 0x4010000;
4911 tw32_f(MAC_SERDES_CFG, val);
4912 }
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004913
4914 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004915 }
4916 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4917 tg3_setup_flow_control(tp, 0, 0);
4918 current_link_up = 1;
4919 }
4920 goto out;
4921 }
4922
4923 /* Want auto-negotiation. */
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004924 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004925
Matt Carlson82cd3d12007-12-20 20:09:00 -08004926 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4927 if (flowctrl & ADVERTISE_1000XPAUSE)
4928 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4929 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4930 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004931
4932 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004933 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
Michael Chan3d3ebe72006-09-27 15:59:15 -07004934 tp->serdes_counter &&
4935 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4936 MAC_STATUS_RCVD_CFG)) ==
4937 MAC_STATUS_PCS_SYNCED)) {
4938 tp->serdes_counter--;
4939 current_link_up = 1;
4940 goto out;
4941 }
4942restart_autoneg:
Linus Torvalds1da177e2005-04-16 15:20:36 -07004943 if (workaround)
4944 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004945 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004946 udelay(5);
4947 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4948
Michael Chan3d3ebe72006-09-27 15:59:15 -07004949 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004950 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004951 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4952 MAC_STATUS_SIGNAL_DET)) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07004953 sg_dig_status = tr32(SG_DIG_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004954 mac_status = tr32(MAC_STATUS);
4955
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004956 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004957 (mac_status & MAC_STATUS_PCS_SYNCED)) {
Matt Carlson82cd3d12007-12-20 20:09:00 -08004958 u32 local_adv = 0, remote_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004959
Matt Carlson82cd3d12007-12-20 20:09:00 -08004960 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4961 local_adv |= ADVERTISE_1000XPAUSE;
4962 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4963 local_adv |= ADVERTISE_1000XPSE_ASYM;
4964
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004965 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
Matt Carlson82cd3d12007-12-20 20:09:00 -08004966 remote_adv |= LPA_1000XPAUSE;
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004967 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
Matt Carlson82cd3d12007-12-20 20:09:00 -08004968 remote_adv |= LPA_1000XPAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004969
Matt Carlson859edb22011-12-08 14:40:16 +00004970 tp->link_config.rmt_adv =
4971 mii_adv_to_ethtool_adv_x(remote_adv);
4972
Linus Torvalds1da177e2005-04-16 15:20:36 -07004973 tg3_setup_flow_control(tp, local_adv, remote_adv);
4974 current_link_up = 1;
Michael Chan3d3ebe72006-09-27 15:59:15 -07004975 tp->serdes_counter = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004976 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004977 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07004978 if (tp->serdes_counter)
4979 tp->serdes_counter--;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004980 else {
4981 if (workaround) {
4982 u32 val = serdes_cfg;
4983
4984 if (port_a)
4985 val |= 0xc010000;
4986 else
4987 val |= 0x4010000;
4988
4989 tw32_f(MAC_SERDES_CFG, val);
4990 }
4991
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004992 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004993 udelay(40);
4994
4995 /* Link parallel detection - link is up */
4996 /* only if we have PCS_SYNC and not */
4997 /* receiving config code words */
4998 mac_status = tr32(MAC_STATUS);
4999 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5000 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5001 tg3_setup_flow_control(tp, 0, 0);
5002 current_link_up = 1;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005003 tp->phy_flags |=
5004 TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan3d3ebe72006-09-27 15:59:15 -07005005 tp->serdes_counter =
5006 SERDES_PARALLEL_DET_TIMEOUT;
5007 } else
5008 goto restart_autoneg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005009 }
5010 }
Michael Chan3d3ebe72006-09-27 15:59:15 -07005011 } else {
5012 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005013 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005014 }
5015
5016out:
5017 return current_link_up;
5018}
5019
5020static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5021{
5022 int current_link_up = 0;
5023
Michael Chan5cf64b8a2007-05-05 12:11:21 -07005024 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
Linus Torvalds1da177e2005-04-16 15:20:36 -07005025 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005026
5027 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
Matt Carlson5be73b42007-12-20 20:09:29 -08005028 u32 txflags, rxflags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005029 int i;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005030
Matt Carlson5be73b42007-12-20 20:09:29 -08005031 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5032 u32 local_adv = 0, remote_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005033
Matt Carlson5be73b42007-12-20 20:09:29 -08005034 if (txflags & ANEG_CFG_PS1)
5035 local_adv |= ADVERTISE_1000XPAUSE;
5036 if (txflags & ANEG_CFG_PS2)
5037 local_adv |= ADVERTISE_1000XPSE_ASYM;
5038
5039 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5040 remote_adv |= LPA_1000XPAUSE;
5041 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5042 remote_adv |= LPA_1000XPAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005043
Matt Carlson859edb22011-12-08 14:40:16 +00005044 tp->link_config.rmt_adv =
5045 mii_adv_to_ethtool_adv_x(remote_adv);
5046
Linus Torvalds1da177e2005-04-16 15:20:36 -07005047 tg3_setup_flow_control(tp, local_adv, remote_adv);
5048
Linus Torvalds1da177e2005-04-16 15:20:36 -07005049 current_link_up = 1;
5050 }
5051 for (i = 0; i < 30; i++) {
5052 udelay(20);
5053 tw32_f(MAC_STATUS,
5054 (MAC_STATUS_SYNC_CHANGED |
5055 MAC_STATUS_CFG_CHANGED));
5056 udelay(40);
5057 if ((tr32(MAC_STATUS) &
5058 (MAC_STATUS_SYNC_CHANGED |
5059 MAC_STATUS_CFG_CHANGED)) == 0)
5060 break;
5061 }
5062
5063 mac_status = tr32(MAC_STATUS);
5064 if (current_link_up == 0 &&
5065 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5066 !(mac_status & MAC_STATUS_RCVD_CFG))
5067 current_link_up = 1;
5068 } else {
Matt Carlson5be73b42007-12-20 20:09:29 -08005069 tg3_setup_flow_control(tp, 0, 0);
5070
Linus Torvalds1da177e2005-04-16 15:20:36 -07005071 /* Forcing 1000FD link up. */
5072 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005073
5074 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5075 udelay(40);
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07005076
5077 tw32_f(MAC_MODE, tp->mac_mode);
5078 udelay(40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005079 }
5080
5081out:
5082 return current_link_up;
5083}
5084
5085static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
5086{
5087 u32 orig_pause_cfg;
5088 u16 orig_active_speed;
5089 u8 orig_active_duplex;
5090 u32 mac_status;
5091 int current_link_up;
5092 int i;
5093
Matt Carlson8d018622007-12-20 20:05:44 -08005094 orig_pause_cfg = tp->link_config.active_flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005095 orig_active_speed = tp->link_config.active_speed;
5096 orig_active_duplex = tp->link_config.active_duplex;
5097
Joe Perches63c3a662011-04-26 08:12:10 +00005098 if (!tg3_flag(tp, HW_AUTONEG) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07005099 netif_carrier_ok(tp->dev) &&
Joe Perches63c3a662011-04-26 08:12:10 +00005100 tg3_flag(tp, INIT_COMPLETE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005101 mac_status = tr32(MAC_STATUS);
5102 mac_status &= (MAC_STATUS_PCS_SYNCED |
5103 MAC_STATUS_SIGNAL_DET |
5104 MAC_STATUS_CFG_CHANGED |
5105 MAC_STATUS_RCVD_CFG);
5106 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5107 MAC_STATUS_SIGNAL_DET)) {
5108 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5109 MAC_STATUS_CFG_CHANGED));
5110 return 0;
5111 }
5112 }
5113
5114 tw32_f(MAC_TX_AUTO_NEG, 0);
5115
5116 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5117 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5118 tw32_f(MAC_MODE, tp->mac_mode);
5119 udelay(40);
5120
Matt Carlson79eb6902010-02-17 15:17:03 +00005121 if (tp->phy_id == TG3_PHY_ID_BCM8002)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005122 tg3_init_bcm8002(tp);
5123
5124 /* Enable link change event even when serdes polling. */
5125 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5126 udelay(40);
5127
5128 current_link_up = 0;
Matt Carlson859edb22011-12-08 14:40:16 +00005129 tp->link_config.rmt_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005130 mac_status = tr32(MAC_STATUS);
5131
Joe Perches63c3a662011-04-26 08:12:10 +00005132 if (tg3_flag(tp, HW_AUTONEG))
Linus Torvalds1da177e2005-04-16 15:20:36 -07005133 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5134 else
5135 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5136
Matt Carlson898a56f2009-08-28 14:02:40 +00005137 tp->napi[0].hw_status->status =
Linus Torvalds1da177e2005-04-16 15:20:36 -07005138 (SD_STATUS_UPDATED |
Matt Carlson898a56f2009-08-28 14:02:40 +00005139 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005140
5141 for (i = 0; i < 100; i++) {
5142 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5143 MAC_STATUS_CFG_CHANGED));
5144 udelay(5);
5145 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
Michael Chan3d3ebe72006-09-27 15:59:15 -07005146 MAC_STATUS_CFG_CHANGED |
5147 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005148 break;
5149 }
5150
5151 mac_status = tr32(MAC_STATUS);
5152 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5153 current_link_up = 0;
Michael Chan3d3ebe72006-09-27 15:59:15 -07005154 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5155 tp->serdes_counter == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005156 tw32_f(MAC_MODE, (tp->mac_mode |
5157 MAC_MODE_SEND_CONFIGS));
5158 udelay(1);
5159 tw32_f(MAC_MODE, tp->mac_mode);
5160 }
5161 }
5162
5163 if (current_link_up == 1) {
5164 tp->link_config.active_speed = SPEED_1000;
5165 tp->link_config.active_duplex = DUPLEX_FULL;
5166 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5167 LED_CTRL_LNKLED_OVERRIDE |
5168 LED_CTRL_1000MBPS_ON));
5169 } else {
Matt Carlsone7405222012-02-13 15:20:16 +00005170 tp->link_config.active_speed = SPEED_UNKNOWN;
5171 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005172 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5173 LED_CTRL_LNKLED_OVERRIDE |
5174 LED_CTRL_TRAFFIC_OVERRIDE));
5175 }
5176
5177 if (current_link_up != netif_carrier_ok(tp->dev)) {
5178 if (current_link_up)
5179 netif_carrier_on(tp->dev);
5180 else
5181 netif_carrier_off(tp->dev);
5182 tg3_link_report(tp);
5183 } else {
Matt Carlson8d018622007-12-20 20:05:44 -08005184 u32 now_pause_cfg = tp->link_config.active_flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005185 if (orig_pause_cfg != now_pause_cfg ||
5186 orig_active_speed != tp->link_config.active_speed ||
5187 orig_active_duplex != tp->link_config.active_duplex)
5188 tg3_link_report(tp);
5189 }
5190
5191 return 0;
5192}
5193
Michael Chan747e8f82005-07-25 12:33:22 -07005194static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5195{
5196 int current_link_up, err = 0;
5197 u32 bmsr, bmcr;
5198 u16 current_speed;
5199 u8 current_duplex;
Matt Carlsonef167e22007-12-20 20:10:01 -08005200 u32 local_adv, remote_adv;
Michael Chan747e8f82005-07-25 12:33:22 -07005201
5202 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5203 tw32_f(MAC_MODE, tp->mac_mode);
5204 udelay(40);
5205
5206 tw32(MAC_EVENT, 0);
5207
5208 tw32_f(MAC_STATUS,
5209 (MAC_STATUS_SYNC_CHANGED |
5210 MAC_STATUS_CFG_CHANGED |
5211 MAC_STATUS_MI_COMPLETION |
5212 MAC_STATUS_LNKSTATE_CHANGED));
5213 udelay(40);
5214
5215 if (force_reset)
5216 tg3_phy_reset(tp);
5217
5218 current_link_up = 0;
Matt Carlsone7405222012-02-13 15:20:16 +00005219 current_speed = SPEED_UNKNOWN;
5220 current_duplex = DUPLEX_UNKNOWN;
Matt Carlson859edb22011-12-08 14:40:16 +00005221 tp->link_config.rmt_adv = 0;
Michael Chan747e8f82005-07-25 12:33:22 -07005222
5223 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5224 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
Michael Chand4d2c552006-03-20 17:47:20 -08005225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
5226 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5227 bmsr |= BMSR_LSTATUS;
5228 else
5229 bmsr &= ~BMSR_LSTATUS;
5230 }
Michael Chan747e8f82005-07-25 12:33:22 -07005231
5232 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5233
5234 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005235 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
Michael Chan747e8f82005-07-25 12:33:22 -07005236 /* do nothing, just check for link up at the end */
5237 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
Matt Carlson28011cf2011-11-16 18:36:59 -05005238 u32 adv, newadv;
Michael Chan747e8f82005-07-25 12:33:22 -07005239
5240 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
Matt Carlson28011cf2011-11-16 18:36:59 -05005241 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5242 ADVERTISE_1000XPAUSE |
5243 ADVERTISE_1000XPSE_ASYM |
5244 ADVERTISE_SLCT);
Michael Chan747e8f82005-07-25 12:33:22 -07005245
Matt Carlson28011cf2011-11-16 18:36:59 -05005246 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
Matt Carlson37f07022011-11-17 14:30:55 +00005247 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
Michael Chan747e8f82005-07-25 12:33:22 -07005248
Matt Carlson28011cf2011-11-16 18:36:59 -05005249 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5250 tg3_writephy(tp, MII_ADVERTISE, newadv);
Michael Chan747e8f82005-07-25 12:33:22 -07005251 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5252 tg3_writephy(tp, MII_BMCR, bmcr);
5253
5254 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
Michael Chan3d3ebe72006-09-27 15:59:15 -07005255 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005256 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07005257
5258 return err;
5259 }
5260 } else {
5261 u32 new_bmcr;
5262
5263 bmcr &= ~BMCR_SPEED1000;
5264 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5265
5266 if (tp->link_config.duplex == DUPLEX_FULL)
5267 new_bmcr |= BMCR_FULLDPLX;
5268
5269 if (new_bmcr != bmcr) {
5270 /* BMCR_SPEED1000 is a reserved bit that needs
5271 * to be set on write.
5272 */
5273 new_bmcr |= BMCR_SPEED1000;
5274
5275 /* Force a linkdown */
5276 if (netif_carrier_ok(tp->dev)) {
5277 u32 adv;
5278
5279 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5280 adv &= ~(ADVERTISE_1000XFULL |
5281 ADVERTISE_1000XHALF |
5282 ADVERTISE_SLCT);
5283 tg3_writephy(tp, MII_ADVERTISE, adv);
5284 tg3_writephy(tp, MII_BMCR, bmcr |
5285 BMCR_ANRESTART |
5286 BMCR_ANENABLE);
5287 udelay(10);
5288 netif_carrier_off(tp->dev);
5289 }
5290 tg3_writephy(tp, MII_BMCR, new_bmcr);
5291 bmcr = new_bmcr;
5292 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5293 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
Michael Chand4d2c552006-03-20 17:47:20 -08005294 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5295 ASIC_REV_5714) {
5296 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5297 bmsr |= BMSR_LSTATUS;
5298 else
5299 bmsr &= ~BMSR_LSTATUS;
5300 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005301 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07005302 }
5303 }
5304
5305 if (bmsr & BMSR_LSTATUS) {
5306 current_speed = SPEED_1000;
5307 current_link_up = 1;
5308 if (bmcr & BMCR_FULLDPLX)
5309 current_duplex = DUPLEX_FULL;
5310 else
5311 current_duplex = DUPLEX_HALF;
5312
Matt Carlsonef167e22007-12-20 20:10:01 -08005313 local_adv = 0;
5314 remote_adv = 0;
5315
Michael Chan747e8f82005-07-25 12:33:22 -07005316 if (bmcr & BMCR_ANENABLE) {
Matt Carlsonef167e22007-12-20 20:10:01 -08005317 u32 common;
Michael Chan747e8f82005-07-25 12:33:22 -07005318
5319 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5320 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5321 common = local_adv & remote_adv;
5322 if (common & (ADVERTISE_1000XHALF |
5323 ADVERTISE_1000XFULL)) {
5324 if (common & ADVERTISE_1000XFULL)
5325 current_duplex = DUPLEX_FULL;
5326 else
5327 current_duplex = DUPLEX_HALF;
Matt Carlson859edb22011-12-08 14:40:16 +00005328
5329 tp->link_config.rmt_adv =
5330 mii_adv_to_ethtool_adv_x(remote_adv);
Joe Perches63c3a662011-04-26 08:12:10 +00005331 } else if (!tg3_flag(tp, 5780_CLASS)) {
Matt Carlson57d8b882010-06-05 17:24:35 +00005332 /* Link is up via parallel detect */
Matt Carlson859a588792010-04-05 10:19:28 +00005333 } else {
Michael Chan747e8f82005-07-25 12:33:22 -07005334 current_link_up = 0;
Matt Carlson859a588792010-04-05 10:19:28 +00005335 }
Michael Chan747e8f82005-07-25 12:33:22 -07005336 }
5337 }
5338
Matt Carlsonef167e22007-12-20 20:10:01 -08005339 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5340 tg3_setup_flow_control(tp, local_adv, remote_adv);
5341
Michael Chan747e8f82005-07-25 12:33:22 -07005342 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5343 if (tp->link_config.active_duplex == DUPLEX_HALF)
5344 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5345
5346 tw32_f(MAC_MODE, tp->mac_mode);
5347 udelay(40);
5348
5349 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5350
5351 tp->link_config.active_speed = current_speed;
5352 tp->link_config.active_duplex = current_duplex;
5353
5354 if (current_link_up != netif_carrier_ok(tp->dev)) {
5355 if (current_link_up)
5356 netif_carrier_on(tp->dev);
5357 else {
5358 netif_carrier_off(tp->dev);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005359 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07005360 }
5361 tg3_link_report(tp);
5362 }
5363 return err;
5364}
5365
5366static void tg3_serdes_parallel_detect(struct tg3 *tp)
5367{
Michael Chan3d3ebe72006-09-27 15:59:15 -07005368 if (tp->serdes_counter) {
Michael Chan747e8f82005-07-25 12:33:22 -07005369 /* Give autoneg time to complete. */
Michael Chan3d3ebe72006-09-27 15:59:15 -07005370 tp->serdes_counter--;
Michael Chan747e8f82005-07-25 12:33:22 -07005371 return;
5372 }
Matt Carlsonc6cdf432010-04-05 10:19:26 +00005373
Michael Chan747e8f82005-07-25 12:33:22 -07005374 if (!netif_carrier_ok(tp->dev) &&
5375 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5376 u32 bmcr;
5377
5378 tg3_readphy(tp, MII_BMCR, &bmcr);
5379 if (bmcr & BMCR_ANENABLE) {
5380 u32 phy1, phy2;
5381
5382 /* Select shadow register 0x1f */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00005383 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5384 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
Michael Chan747e8f82005-07-25 12:33:22 -07005385
5386 /* Select expansion interrupt status register */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00005387 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5388 MII_TG3_DSP_EXP1_INT_STAT);
5389 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5390 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
Michael Chan747e8f82005-07-25 12:33:22 -07005391
5392 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5393 /* We have signal detect and not receiving
5394 * config code words, link is up by parallel
5395 * detection.
5396 */
5397
5398 bmcr &= ~BMCR_ANENABLE;
5399 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5400 tg3_writephy(tp, MII_BMCR, bmcr);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005401 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07005402 }
5403 }
Matt Carlson859a588792010-04-05 10:19:28 +00005404 } else if (netif_carrier_ok(tp->dev) &&
5405 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005406 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
Michael Chan747e8f82005-07-25 12:33:22 -07005407 u32 phy2;
5408
5409 /* Select expansion interrupt status register */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00005410 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5411 MII_TG3_DSP_EXP1_INT_STAT);
5412 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
Michael Chan747e8f82005-07-25 12:33:22 -07005413 if (phy2 & 0x20) {
5414 u32 bmcr;
5415
5416 /* Config code words received, turn on autoneg. */
5417 tg3_readphy(tp, MII_BMCR, &bmcr);
5418 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5419
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005420 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07005421
5422 }
5423 }
5424}
5425
Linus Torvalds1da177e2005-04-16 15:20:36 -07005426static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5427{
Matt Carlsonf2096f92011-04-05 14:22:48 +00005428 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005429 int err;
5430
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005431 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005432 err = tg3_setup_fiber_phy(tp, force_reset);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005433 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chan747e8f82005-07-25 12:33:22 -07005434 err = tg3_setup_fiber_mii_phy(tp, force_reset);
Matt Carlson859a588792010-04-05 10:19:28 +00005435 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07005436 err = tg3_setup_copper_phy(tp, force_reset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005437
Matt Carlsonbcb37f62008-11-03 16:52:09 -08005438 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
Matt Carlsonf2096f92011-04-05 14:22:48 +00005439 u32 scale;
Matt Carlsonaa6c91f2007-11-12 21:18:04 -08005440
5441 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5442 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5443 scale = 65;
5444 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5445 scale = 6;
5446 else
5447 scale = 12;
5448
5449 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5450 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5451 tw32(GRC_MISC_CFG, val);
5452 }
5453
Matt Carlsonf2096f92011-04-05 14:22:48 +00005454 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5455 (6 << TX_LENGTHS_IPG_SHIFT);
5456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5457 val |= tr32(MAC_TX_LENGTHS) &
5458 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5459 TX_LENGTHS_CNT_DWN_VAL_MSK);
5460
Linus Torvalds1da177e2005-04-16 15:20:36 -07005461 if (tp->link_config.active_speed == SPEED_1000 &&
5462 tp->link_config.active_duplex == DUPLEX_HALF)
Matt Carlsonf2096f92011-04-05 14:22:48 +00005463 tw32(MAC_TX_LENGTHS, val |
5464 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005465 else
Matt Carlsonf2096f92011-04-05 14:22:48 +00005466 tw32(MAC_TX_LENGTHS, val |
5467 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005468
Joe Perches63c3a662011-04-26 08:12:10 +00005469 if (!tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005470 if (netif_carrier_ok(tp->dev)) {
5471 tw32(HOSTCC_STAT_COAL_TICKS,
David S. Miller15f98502005-05-18 22:49:26 -07005472 tp->coal.stats_block_coalesce_usecs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005473 } else {
5474 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5475 }
5476 }
5477
Joe Perches63c3a662011-04-26 08:12:10 +00005478 if (tg3_flag(tp, ASPM_WORKAROUND)) {
Matt Carlsonf2096f92011-04-05 14:22:48 +00005479 val = tr32(PCIE_PWR_MGMT_THRESH);
Matt Carlson8ed5d972007-05-07 00:25:49 -07005480 if (!netif_carrier_ok(tp->dev))
5481 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5482 tp->pwrmgmt_thresh;
5483 else
5484 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5485 tw32(PCIE_PWR_MGMT_THRESH, val);
5486 }
5487
Linus Torvalds1da177e2005-04-16 15:20:36 -07005488 return err;
5489}
5490
Matt Carlson66cfd1b2010-09-30 10:34:30 +00005491static inline int tg3_irq_sync(struct tg3 *tp)
5492{
5493 return tp->irq_sync;
5494}
5495
Matt Carlson97bd8e42011-04-13 11:05:04 +00005496static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5497{
5498 int i;
5499
5500 dst = (u32 *)((u8 *)dst + off);
5501 for (i = 0; i < len; i += sizeof(u32))
5502 *dst++ = tr32(off + i);
5503}
5504
5505static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5506{
5507 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5508 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5509 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5510 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5511 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5512 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5513 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5514 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5515 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5516 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5517 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5518 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5519 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5520 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5521 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5522 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5523 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5524 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5525 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5526
Joe Perches63c3a662011-04-26 08:12:10 +00005527 if (tg3_flag(tp, SUPPORT_MSIX))
Matt Carlson97bd8e42011-04-13 11:05:04 +00005528 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5529
5530 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5531 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5532 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5533 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5534 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5535 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5536 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5537 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5538
Joe Perches63c3a662011-04-26 08:12:10 +00005539 if (!tg3_flag(tp, 5705_PLUS)) {
Matt Carlson97bd8e42011-04-13 11:05:04 +00005540 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5541 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5542 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5543 }
5544
5545 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5546 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5547 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5548 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5549 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5550
Joe Perches63c3a662011-04-26 08:12:10 +00005551 if (tg3_flag(tp, NVRAM))
Matt Carlson97bd8e42011-04-13 11:05:04 +00005552 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5553}
5554
5555static void tg3_dump_state(struct tg3 *tp)
5556{
5557 int i;
5558 u32 *regs;
5559
5560 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5561 if (!regs) {
5562 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5563 return;
5564 }
5565
Joe Perches63c3a662011-04-26 08:12:10 +00005566 if (tg3_flag(tp, PCI_EXPRESS)) {
Matt Carlson97bd8e42011-04-13 11:05:04 +00005567 /* Read up to but not including private PCI registers */
5568 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5569 regs[i / sizeof(u32)] = tr32(i);
5570 } else
5571 tg3_dump_legacy_regs(tp, regs);
5572
5573 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5574 if (!regs[i + 0] && !regs[i + 1] &&
5575 !regs[i + 2] && !regs[i + 3])
5576 continue;
5577
5578 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5579 i * 4,
5580 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5581 }
5582
5583 kfree(regs);
5584
5585 for (i = 0; i < tp->irq_cnt; i++) {
5586 struct tg3_napi *tnapi = &tp->napi[i];
5587
5588 /* SW status block */
5589 netdev_err(tp->dev,
5590 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5591 i,
5592 tnapi->hw_status->status,
5593 tnapi->hw_status->status_tag,
5594 tnapi->hw_status->rx_jumbo_consumer,
5595 tnapi->hw_status->rx_consumer,
5596 tnapi->hw_status->rx_mini_consumer,
5597 tnapi->hw_status->idx[0].rx_producer,
5598 tnapi->hw_status->idx[0].tx_consumer);
5599
5600 netdev_err(tp->dev,
5601 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5602 i,
5603 tnapi->last_tag, tnapi->last_irq_tag,
5604 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5605 tnapi->rx_rcb_ptr,
5606 tnapi->prodring.rx_std_prod_idx,
5607 tnapi->prodring.rx_std_cons_idx,
5608 tnapi->prodring.rx_jmb_prod_idx,
5609 tnapi->prodring.rx_jmb_cons_idx);
5610 }
5611}
5612
Michael Chandf3e6542006-05-26 17:48:07 -07005613/* This is called whenever we suspect that the system chipset is re-
5614 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5615 * is bogus tx completions. We try to recover by setting the
5616 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5617 * in the workqueue.
5618 */
5619static void tg3_tx_recover(struct tg3 *tp)
5620{
Joe Perches63c3a662011-04-26 08:12:10 +00005621 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
Michael Chandf3e6542006-05-26 17:48:07 -07005622 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5623
Matt Carlson5129c3a2010-04-05 10:19:23 +00005624 netdev_warn(tp->dev,
5625 "The system may be re-ordering memory-mapped I/O "
5626 "cycles to the network device, attempting to recover. "
5627 "Please report the problem to the driver maintainer "
5628 "and include system chipset information.\n");
Michael Chandf3e6542006-05-26 17:48:07 -07005629
5630 spin_lock(&tp->lock);
Joe Perches63c3a662011-04-26 08:12:10 +00005631 tg3_flag_set(tp, TX_RECOVERY_PENDING);
Michael Chandf3e6542006-05-26 17:48:07 -07005632 spin_unlock(&tp->lock);
5633}
5634
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005635static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
Michael Chan1b2a7202006-08-07 21:46:02 -07005636{
Matt Carlsonf65aac12010-08-02 11:26:03 +00005637 /* Tell compiler to fetch tx indices from memory. */
5638 barrier();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005639 return tnapi->tx_pending -
5640 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
Michael Chan1b2a7202006-08-07 21:46:02 -07005641}
5642
Linus Torvalds1da177e2005-04-16 15:20:36 -07005643/* Tigon3 never reports partial packet sends. So we do not
5644 * need special logic to handle SKBs that have not had all
5645 * of their frags sent yet, like SunGEM does.
5646 */
Matt Carlson17375d22009-08-28 14:02:18 +00005647static void tg3_tx(struct tg3_napi *tnapi)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005648{
Matt Carlson17375d22009-08-28 14:02:18 +00005649 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00005650 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005651 u32 sw_idx = tnapi->tx_cons;
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005652 struct netdev_queue *txq;
5653 int index = tnapi - tp->napi;
Tom Herbert298376d2011-11-28 16:33:30 +00005654 unsigned int pkts_compl = 0, bytes_compl = 0;
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005655
Joe Perches63c3a662011-04-26 08:12:10 +00005656 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005657 index--;
5658
5659 txq = netdev_get_tx_queue(tp->dev, index);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005660
5661 while (sw_idx != hw_idx) {
Matt Carlsondf8944c2011-07-27 14:20:46 +00005662 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005663 struct sk_buff *skb = ri->skb;
Michael Chandf3e6542006-05-26 17:48:07 -07005664 int i, tx_bug = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005665
Michael Chandf3e6542006-05-26 17:48:07 -07005666 if (unlikely(skb == NULL)) {
5667 tg3_tx_recover(tp);
5668 return;
5669 }
5670
Alexander Duyckf4188d82009-12-02 16:48:38 +00005671 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005672 dma_unmap_addr(ri, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00005673 skb_headlen(skb),
5674 PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005675
5676 ri->skb = NULL;
5677
Matt Carlsone01ee142011-07-27 14:20:50 +00005678 while (ri->fragmented) {
5679 ri->fragmented = false;
5680 sw_idx = NEXT_TX(sw_idx);
5681 ri = &tnapi->tx_buffers[sw_idx];
5682 }
5683
Linus Torvalds1da177e2005-04-16 15:20:36 -07005684 sw_idx = NEXT_TX(sw_idx);
5685
5686 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005687 ri = &tnapi->tx_buffers[sw_idx];
Michael Chandf3e6542006-05-26 17:48:07 -07005688 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5689 tx_bug = 1;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005690
5691 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005692 dma_unmap_addr(ri, mapping),
Eric Dumazet9e903e02011-10-18 21:00:24 +00005693 skb_frag_size(&skb_shinfo(skb)->frags[i]),
Alexander Duyckf4188d82009-12-02 16:48:38 +00005694 PCI_DMA_TODEVICE);
Matt Carlsone01ee142011-07-27 14:20:50 +00005695
5696 while (ri->fragmented) {
5697 ri->fragmented = false;
5698 sw_idx = NEXT_TX(sw_idx);
5699 ri = &tnapi->tx_buffers[sw_idx];
5700 }
5701
Linus Torvalds1da177e2005-04-16 15:20:36 -07005702 sw_idx = NEXT_TX(sw_idx);
5703 }
5704
Tom Herbert298376d2011-11-28 16:33:30 +00005705 pkts_compl++;
5706 bytes_compl += skb->len;
5707
David S. Millerf47c11e2005-06-24 20:18:35 -07005708 dev_kfree_skb(skb);
Michael Chandf3e6542006-05-26 17:48:07 -07005709
5710 if (unlikely(tx_bug)) {
5711 tg3_tx_recover(tp);
5712 return;
5713 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005714 }
5715
Tom Herbert5cb917b2012-03-05 19:53:50 +00005716 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
Tom Herbert298376d2011-11-28 16:33:30 +00005717
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005718 tnapi->tx_cons = sw_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005719
Michael Chan1b2a7202006-08-07 21:46:02 -07005720 /* Need to make the tx_cons update visible to tg3_start_xmit()
5721 * before checking for netif_queue_stopped(). Without the
5722 * memory barrier, there is a small possibility that tg3_start_xmit()
5723 * will miss it and cause the queue to be stopped forever.
5724 */
5725 smp_mb();
5726
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005727 if (unlikely(netif_tx_queue_stopped(txq) &&
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005728 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005729 __netif_tx_lock(txq, smp_processor_id());
5730 if (netif_tx_queue_stopped(txq) &&
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005731 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005732 netif_tx_wake_queue(txq);
5733 __netif_tx_unlock(txq);
Michael Chan51b91462005-09-01 17:41:28 -07005734 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005735}
5736
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005737static void tg3_frag_free(bool is_frag, void *data)
5738{
5739 if (is_frag)
5740 put_page(virt_to_head_page(data));
5741 else
5742 kfree(data);
5743}
5744
Eric Dumazet9205fd92011-11-18 06:47:01 +00005745static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00005746{
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005747 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
5748 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5749
Eric Dumazet9205fd92011-11-18 06:47:01 +00005750 if (!ri->data)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00005751 return;
5752
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005753 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
Matt Carlson2b2cdb62009-11-13 13:03:48 +00005754 map_sz, PCI_DMA_FROMDEVICE);
Eric Dumazeta1e8b3072012-05-18 21:33:39 +00005755 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
Eric Dumazet9205fd92011-11-18 06:47:01 +00005756 ri->data = NULL;
Matt Carlson2b2cdb62009-11-13 13:03:48 +00005757}
5758
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005759
Linus Torvalds1da177e2005-04-16 15:20:36 -07005760/* Returns size of skb allocated or < 0 on error.
5761 *
5762 * We only need to fill in the address because the other members
5763 * of the RX descriptor are invariant, see tg3_init_rings.
5764 *
5765 * Note the purposeful assymetry of cpu vs. chip accesses. For
5766 * posting buffers we only dirty the first cache line of the RX
5767 * descriptor (containing the address). Whereas for the RX status
5768 * buffers the cpu only reads the last cacheline of the RX descriptor
5769 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5770 */
Eric Dumazet9205fd92011-11-18 06:47:01 +00005771static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005772 u32 opaque_key, u32 dest_idx_unmasked,
5773 unsigned int *frag_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005774{
5775 struct tg3_rx_buffer_desc *desc;
Matt Carlsonf94e2902010-10-14 10:37:42 +00005776 struct ring_info *map;
Eric Dumazet9205fd92011-11-18 06:47:01 +00005777 u8 *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005778 dma_addr_t mapping;
Eric Dumazet9205fd92011-11-18 06:47:01 +00005779 int skb_size, data_size, dest_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005780
Linus Torvalds1da177e2005-04-16 15:20:36 -07005781 switch (opaque_key) {
5782 case RXD_OPAQUE_RING_STD:
Matt Carlson2c49a442010-09-30 10:34:35 +00005783 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
Matt Carlson21f581a2009-08-28 14:00:25 +00005784 desc = &tpr->rx_std[dest_idx];
5785 map = &tpr->rx_std_buffers[dest_idx];
Eric Dumazet9205fd92011-11-18 06:47:01 +00005786 data_size = tp->rx_pkt_map_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005787 break;
5788
5789 case RXD_OPAQUE_RING_JUMBO:
Matt Carlson2c49a442010-09-30 10:34:35 +00005790 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
Matt Carlson79ed5ac2009-08-28 14:00:55 +00005791 desc = &tpr->rx_jmb[dest_idx].std;
Matt Carlson21f581a2009-08-28 14:00:25 +00005792 map = &tpr->rx_jmb_buffers[dest_idx];
Eric Dumazet9205fd92011-11-18 06:47:01 +00005793 data_size = TG3_RX_JMB_MAP_SZ;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005794 break;
5795
5796 default:
5797 return -EINVAL;
Stephen Hemminger855e1112008-04-16 16:37:28 -07005798 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005799
5800 /* Do not overwrite any of the map or rp information
5801 * until we are sure we can commit to a new buffer.
5802 *
5803 * Callers depend upon this behavior and assume that
5804 * we leave everything unchanged if we fail.
5805 */
Eric Dumazet9205fd92011-11-18 06:47:01 +00005806 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5807 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
Eric Dumazeta1e8b3072012-05-18 21:33:39 +00005808 if (skb_size <= PAGE_SIZE) {
5809 data = netdev_alloc_frag(skb_size);
5810 *frag_size = skb_size;
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005811 } else {
5812 data = kmalloc(skb_size, GFP_ATOMIC);
5813 *frag_size = 0;
5814 }
Eric Dumazet9205fd92011-11-18 06:47:01 +00005815 if (!data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005816 return -ENOMEM;
5817
Eric Dumazet9205fd92011-11-18 06:47:01 +00005818 mapping = pci_map_single(tp->pdev,
5819 data + TG3_RX_OFFSET(tp),
5820 data_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005821 PCI_DMA_FROMDEVICE);
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005822 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
Eric Dumazeta1e8b3072012-05-18 21:33:39 +00005823 tg3_frag_free(skb_size <= PAGE_SIZE, data);
Matt Carlsona21771d2009-11-02 14:25:31 +00005824 return -EIO;
5825 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005826
Eric Dumazet9205fd92011-11-18 06:47:01 +00005827 map->data = data;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005828 dma_unmap_addr_set(map, mapping, mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005829
Linus Torvalds1da177e2005-04-16 15:20:36 -07005830 desc->addr_hi = ((u64)mapping >> 32);
5831 desc->addr_lo = ((u64)mapping & 0xffffffff);
5832
Eric Dumazet9205fd92011-11-18 06:47:01 +00005833 return data_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005834}
5835
5836/* We only need to move over in the address because the other
5837 * members of the RX descriptor are invariant. See notes above
Eric Dumazet9205fd92011-11-18 06:47:01 +00005838 * tg3_alloc_rx_data for full details.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005839 */
Matt Carlsona3896162009-11-13 13:03:44 +00005840static void tg3_recycle_rx(struct tg3_napi *tnapi,
5841 struct tg3_rx_prodring_set *dpr,
5842 u32 opaque_key, int src_idx,
5843 u32 dest_idx_unmasked)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005844{
Matt Carlson17375d22009-08-28 14:02:18 +00005845 struct tg3 *tp = tnapi->tp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005846 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5847 struct ring_info *src_map, *dest_map;
Matt Carlson8fea32b2010-09-15 08:59:58 +00005848 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
Matt Carlsonc6cdf432010-04-05 10:19:26 +00005849 int dest_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005850
5851 switch (opaque_key) {
5852 case RXD_OPAQUE_RING_STD:
Matt Carlson2c49a442010-09-30 10:34:35 +00005853 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
Matt Carlsona3896162009-11-13 13:03:44 +00005854 dest_desc = &dpr->rx_std[dest_idx];
5855 dest_map = &dpr->rx_std_buffers[dest_idx];
5856 src_desc = &spr->rx_std[src_idx];
5857 src_map = &spr->rx_std_buffers[src_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005858 break;
5859
5860 case RXD_OPAQUE_RING_JUMBO:
Matt Carlson2c49a442010-09-30 10:34:35 +00005861 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
Matt Carlsona3896162009-11-13 13:03:44 +00005862 dest_desc = &dpr->rx_jmb[dest_idx].std;
5863 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5864 src_desc = &spr->rx_jmb[src_idx].std;
5865 src_map = &spr->rx_jmb_buffers[src_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005866 break;
5867
5868 default:
5869 return;
Stephen Hemminger855e1112008-04-16 16:37:28 -07005870 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005871
Eric Dumazet9205fd92011-11-18 06:47:01 +00005872 dest_map->data = src_map->data;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005873 dma_unmap_addr_set(dest_map, mapping,
5874 dma_unmap_addr(src_map, mapping));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005875 dest_desc->addr_hi = src_desc->addr_hi;
5876 dest_desc->addr_lo = src_desc->addr_lo;
Matt Carlsone92967b2010-02-12 14:47:06 +00005877
5878 /* Ensure that the update to the skb happens after the physical
5879 * addresses have been transferred to the new BD location.
5880 */
5881 smp_wmb();
5882
Eric Dumazet9205fd92011-11-18 06:47:01 +00005883 src_map->data = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005884}
5885
Linus Torvalds1da177e2005-04-16 15:20:36 -07005886/* The RX ring scheme is composed of multiple rings which post fresh
5887 * buffers to the chip, and one special ring the chip uses to report
5888 * status back to the host.
5889 *
5890 * The special ring reports the status of received packets to the
5891 * host. The chip does not write into the original descriptor the
5892 * RX buffer was obtained from. The chip simply takes the original
5893 * descriptor as provided by the host, updates the status and length
5894 * field, then writes this into the next status ring entry.
5895 *
5896 * Each ring the host uses to post buffers to the chip is described
5897 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5898 * it is first placed into the on-chip ram. When the packet's length
5899 * is known, it walks down the TG3_BDINFO entries to select the ring.
5900 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5901 * which is within the range of the new packet's length is chosen.
5902 *
5903 * The "separate ring for rx status" scheme may sound queer, but it makes
5904 * sense from a cache coherency perspective. If only the host writes
5905 * to the buffer post rings, and only the chip writes to the rx status
5906 * rings, then cache lines never move beyond shared-modified state.
5907 * If both the host and chip were to write into the same ring, cache line
5908 * eviction could occur since both entities want it in an exclusive state.
5909 */
Matt Carlson17375d22009-08-28 14:02:18 +00005910static int tg3_rx(struct tg3_napi *tnapi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005911{
Matt Carlson17375d22009-08-28 14:02:18 +00005912 struct tg3 *tp = tnapi->tp;
Michael Chanf92905d2006-06-29 20:14:29 -07005913 u32 work_mask, rx_std_posted = 0;
Matt Carlson43619352009-11-13 13:03:47 +00005914 u32 std_prod_idx, jmb_prod_idx;
Matt Carlson72334482009-08-28 14:03:01 +00005915 u32 sw_idx = tnapi->rx_rcb_ptr;
Michael Chan483ba502005-04-25 15:14:03 -07005916 u16 hw_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005917 int received;
Matt Carlson8fea32b2010-09-15 08:59:58 +00005918 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005919
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00005920 hw_idx = *(tnapi->rx_rcb_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005921 /*
5922 * We need to order the read of hw_idx and the read of
5923 * the opaque cookie.
5924 */
5925 rmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005926 work_mask = 0;
5927 received = 0;
Matt Carlson43619352009-11-13 13:03:47 +00005928 std_prod_idx = tpr->rx_std_prod_idx;
5929 jmb_prod_idx = tpr->rx_jmb_prod_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005930 while (sw_idx != hw_idx && budget > 0) {
Matt Carlsonafc081f2009-11-13 13:03:43 +00005931 struct ring_info *ri;
Matt Carlson72334482009-08-28 14:03:01 +00005932 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005933 unsigned int len;
5934 struct sk_buff *skb;
5935 dma_addr_t dma_addr;
5936 u32 opaque_key, desc_idx, *post_ptr;
Eric Dumazet9205fd92011-11-18 06:47:01 +00005937 u8 *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005938
5939 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5940 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5941 if (opaque_key == RXD_OPAQUE_RING_STD) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00005942 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005943 dma_addr = dma_unmap_addr(ri, mapping);
Eric Dumazet9205fd92011-11-18 06:47:01 +00005944 data = ri->data;
Matt Carlson43619352009-11-13 13:03:47 +00005945 post_ptr = &std_prod_idx;
Michael Chanf92905d2006-06-29 20:14:29 -07005946 rx_std_posted++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005947 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00005948 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005949 dma_addr = dma_unmap_addr(ri, mapping);
Eric Dumazet9205fd92011-11-18 06:47:01 +00005950 data = ri->data;
Matt Carlson43619352009-11-13 13:03:47 +00005951 post_ptr = &jmb_prod_idx;
Matt Carlson21f581a2009-08-28 14:00:25 +00005952 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07005953 goto next_pkt_nopost;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005954
5955 work_mask |= opaque_key;
5956
5957 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5958 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5959 drop_it:
Matt Carlsona3896162009-11-13 13:03:44 +00005960 tg3_recycle_rx(tnapi, tpr, opaque_key,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005961 desc_idx, *post_ptr);
5962 drop_it_no_recycle:
5963 /* Other statistics kept track of by card. */
Eric Dumazetb0057c52010-10-10 19:55:52 +00005964 tp->rx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005965 goto next_pkt;
5966 }
5967
Eric Dumazet9205fd92011-11-18 06:47:01 +00005968 prefetch(data + TG3_RX_OFFSET(tp));
Matt Carlsonad829262008-11-21 17:16:16 -08005969 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5970 ETH_FCS_LEN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005971
Matt Carlsond2757fc2010-04-12 06:58:27 +00005972 if (len > TG3_RX_COPY_THRESH(tp)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005973 int skb_size;
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005974 unsigned int frag_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005975
Eric Dumazet9205fd92011-11-18 06:47:01 +00005976 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005977 *post_ptr, &frag_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005978 if (skb_size < 0)
5979 goto drop_it;
5980
Matt Carlson287be122009-08-28 13:58:46 +00005981 pci_unmap_single(tp->pdev, dma_addr, skb_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005982 PCI_DMA_FROMDEVICE);
5983
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005984 skb = build_skb(data, frag_size);
Eric Dumazet9205fd92011-11-18 06:47:01 +00005985 if (!skb) {
Eric Dumazet8d4057a2012-04-27 00:34:49 +00005986 tg3_frag_free(frag_size != 0, data);
Eric Dumazet9205fd92011-11-18 06:47:01 +00005987 goto drop_it_no_recycle;
5988 }
5989 skb_reserve(skb, TG3_RX_OFFSET(tp));
5990 /* Ensure that the update to the data happens
Matt Carlson61e800c2010-02-17 15:16:54 +00005991 * after the usage of the old DMA mapping.
5992 */
5993 smp_wmb();
5994
Eric Dumazet9205fd92011-11-18 06:47:01 +00005995 ri->data = NULL;
Matt Carlson61e800c2010-02-17 15:16:54 +00005996
Linus Torvalds1da177e2005-04-16 15:20:36 -07005997 } else {
Matt Carlsona3896162009-11-13 13:03:44 +00005998 tg3_recycle_rx(tnapi, tpr, opaque_key,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005999 desc_idx, *post_ptr);
6000
Eric Dumazet9205fd92011-11-18 06:47:01 +00006001 skb = netdev_alloc_skb(tp->dev,
6002 len + TG3_RAW_IP_ALIGN);
6003 if (skb == NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006004 goto drop_it_no_recycle;
6005
Eric Dumazet9205fd92011-11-18 06:47:01 +00006006 skb_reserve(skb, TG3_RAW_IP_ALIGN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006007 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
Eric Dumazet9205fd92011-11-18 06:47:01 +00006008 memcpy(skb->data,
6009 data + TG3_RX_OFFSET(tp),
6010 len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006011 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006012 }
6013
Eric Dumazet9205fd92011-11-18 06:47:01 +00006014 skb_put(skb, len);
Michał Mirosławdc668912011-04-07 03:35:07 +00006015 if ((tp->dev->features & NETIF_F_RXCSUM) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07006016 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6017 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6018 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6019 skb->ip_summed = CHECKSUM_UNNECESSARY;
6020 else
Eric Dumazetbc8acf22010-09-02 13:07:41 -07006021 skb_checksum_none_assert(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006022
6023 skb->protocol = eth_type_trans(skb, tp->dev);
Matt Carlsonf7b493e2009-02-25 14:21:52 +00006024
6025 if (len > (tp->dev->mtu + ETH_HLEN) &&
6026 skb->protocol != htons(ETH_P_8021Q)) {
6027 dev_kfree_skb(skb);
Eric Dumazetb0057c52010-10-10 19:55:52 +00006028 goto drop_it_no_recycle;
Matt Carlsonf7b493e2009-02-25 14:21:52 +00006029 }
6030
Matt Carlson9dc7a112010-04-12 06:58:28 +00006031 if (desc->type_flags & RXD_FLAG_VLAN &&
Matt Carlsonbf933c82011-01-25 15:58:49 +00006032 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6033 __vlan_hwaccel_put_tag(skb,
6034 desc->err_vlan & RXD_VLAN_MASK);
Matt Carlson9dc7a112010-04-12 06:58:28 +00006035
Matt Carlsonbf933c82011-01-25 15:58:49 +00006036 napi_gro_receive(&tnapi->napi, skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006037
Linus Torvalds1da177e2005-04-16 15:20:36 -07006038 received++;
6039 budget--;
6040
6041next_pkt:
6042 (*post_ptr)++;
Michael Chanf92905d2006-06-29 20:14:29 -07006043
6044 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00006045 tpr->rx_std_prod_idx = std_prod_idx &
6046 tp->rx_std_ring_mask;
Matt Carlson86cfe4f2010-01-12 10:11:37 +00006047 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6048 tpr->rx_std_prod_idx);
Michael Chanf92905d2006-06-29 20:14:29 -07006049 work_mask &= ~RXD_OPAQUE_RING_STD;
6050 rx_std_posted = 0;
6051 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006052next_pkt_nopost:
Michael Chan483ba502005-04-25 15:14:03 -07006053 sw_idx++;
Matt Carlson7cb32cf2010-09-30 10:34:36 +00006054 sw_idx &= tp->rx_ret_ring_mask;
Michael Chan52f6d692005-04-25 15:14:32 -07006055
6056 /* Refresh hw_idx to see if there is new work */
6057 if (sw_idx == hw_idx) {
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00006058 hw_idx = *(tnapi->rx_rcb_prod_idx);
Michael Chan52f6d692005-04-25 15:14:32 -07006059 rmb();
6060 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006061 }
6062
6063 /* ACK the status ring. */
Matt Carlson72334482009-08-28 14:03:01 +00006064 tnapi->rx_rcb_ptr = sw_idx;
6065 tw32_rx_mbox(tnapi->consmbox, sw_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006066
6067 /* Refill RX ring(s). */
Joe Perches63c3a662011-04-26 08:12:10 +00006068 if (!tg3_flag(tp, ENABLE_RSS)) {
Michael Chan6541b802012-03-04 14:48:14 +00006069 /* Sync BD data before updating mailbox */
6070 wmb();
6071
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006072 if (work_mask & RXD_OPAQUE_RING_STD) {
Matt Carlson2c49a442010-09-30 10:34:35 +00006073 tpr->rx_std_prod_idx = std_prod_idx &
6074 tp->rx_std_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006075 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6076 tpr->rx_std_prod_idx);
6077 }
6078 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
Matt Carlson2c49a442010-09-30 10:34:35 +00006079 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6080 tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006081 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6082 tpr->rx_jmb_prod_idx);
6083 }
6084 mmiowb();
6085 } else if (work_mask) {
6086 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6087 * updated before the producer indices can be updated.
6088 */
6089 smp_wmb();
6090
Matt Carlson2c49a442010-09-30 10:34:35 +00006091 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6092 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006093
Michael Chan7ae52892012-03-21 15:38:33 +00006094 if (tnapi != &tp->napi[1]) {
6095 tp->rx_refill = true;
Matt Carlsone4af1af2010-02-12 14:47:05 +00006096 napi_schedule(&tp->napi[1].napi);
Michael Chan7ae52892012-03-21 15:38:33 +00006097 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006098 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006099
6100 return received;
6101}
6102
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006103static void tg3_poll_link(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006104{
Linus Torvalds1da177e2005-04-16 15:20:36 -07006105 /* handle link change and other phy events */
Joe Perches63c3a662011-04-26 08:12:10 +00006106 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006107 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6108
Linus Torvalds1da177e2005-04-16 15:20:36 -07006109 if (sblk->status & SD_STATUS_LINK_CHG) {
6110 sblk->status = SD_STATUS_UPDATED |
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006111 (sblk->status & ~SD_STATUS_LINK_CHG);
David S. Millerf47c11e2005-06-24 20:18:35 -07006112 spin_lock(&tp->lock);
Joe Perches63c3a662011-04-26 08:12:10 +00006113 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlsondd477002008-05-25 23:45:58 -07006114 tw32_f(MAC_STATUS,
6115 (MAC_STATUS_SYNC_CHANGED |
6116 MAC_STATUS_CFG_CHANGED |
6117 MAC_STATUS_MI_COMPLETION |
6118 MAC_STATUS_LNKSTATE_CHANGED));
6119 udelay(40);
6120 } else
6121 tg3_setup_phy(tp, 0);
David S. Millerf47c11e2005-06-24 20:18:35 -07006122 spin_unlock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006123 }
6124 }
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006125}
6126
Matt Carlsonf89f38b2010-02-12 14:47:07 +00006127static int tg3_rx_prodring_xfer(struct tg3 *tp,
6128 struct tg3_rx_prodring_set *dpr,
6129 struct tg3_rx_prodring_set *spr)
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006130{
6131 u32 si, di, cpycnt, src_prod_idx;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00006132 int i, err = 0;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006133
6134 while (1) {
6135 src_prod_idx = spr->rx_std_prod_idx;
6136
6137 /* Make sure updates to the rx_std_buffers[] entries and the
6138 * standard producer index are seen in the correct order.
6139 */
6140 smp_rmb();
6141
6142 if (spr->rx_std_cons_idx == src_prod_idx)
6143 break;
6144
6145 if (spr->rx_std_cons_idx < src_prod_idx)
6146 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6147 else
Matt Carlson2c49a442010-09-30 10:34:35 +00006148 cpycnt = tp->rx_std_ring_mask + 1 -
6149 spr->rx_std_cons_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006150
Matt Carlson2c49a442010-09-30 10:34:35 +00006151 cpycnt = min(cpycnt,
6152 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006153
6154 si = spr->rx_std_cons_idx;
6155 di = dpr->rx_std_prod_idx;
6156
Matt Carlsone92967b2010-02-12 14:47:06 +00006157 for (i = di; i < di + cpycnt; i++) {
Eric Dumazet9205fd92011-11-18 06:47:01 +00006158 if (dpr->rx_std_buffers[i].data) {
Matt Carlsone92967b2010-02-12 14:47:06 +00006159 cpycnt = i - di;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00006160 err = -ENOSPC;
Matt Carlsone92967b2010-02-12 14:47:06 +00006161 break;
6162 }
6163 }
6164
6165 if (!cpycnt)
6166 break;
6167
6168 /* Ensure that updates to the rx_std_buffers ring and the
6169 * shadowed hardware producer ring from tg3_recycle_skb() are
6170 * ordered correctly WRT the skb check above.
6171 */
6172 smp_rmb();
6173
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006174 memcpy(&dpr->rx_std_buffers[di],
6175 &spr->rx_std_buffers[si],
6176 cpycnt * sizeof(struct ring_info));
6177
6178 for (i = 0; i < cpycnt; i++, di++, si++) {
6179 struct tg3_rx_buffer_desc *sbd, *dbd;
6180 sbd = &spr->rx_std[si];
6181 dbd = &dpr->rx_std[di];
6182 dbd->addr_hi = sbd->addr_hi;
6183 dbd->addr_lo = sbd->addr_lo;
6184 }
6185
Matt Carlson2c49a442010-09-30 10:34:35 +00006186 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6187 tp->rx_std_ring_mask;
6188 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6189 tp->rx_std_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006190 }
6191
6192 while (1) {
6193 src_prod_idx = spr->rx_jmb_prod_idx;
6194
6195 /* Make sure updates to the rx_jmb_buffers[] entries and
6196 * the jumbo producer index are seen in the correct order.
6197 */
6198 smp_rmb();
6199
6200 if (spr->rx_jmb_cons_idx == src_prod_idx)
6201 break;
6202
6203 if (spr->rx_jmb_cons_idx < src_prod_idx)
6204 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
6205 else
Matt Carlson2c49a442010-09-30 10:34:35 +00006206 cpycnt = tp->rx_jmb_ring_mask + 1 -
6207 spr->rx_jmb_cons_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006208
6209 cpycnt = min(cpycnt,
Matt Carlson2c49a442010-09-30 10:34:35 +00006210 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006211
6212 si = spr->rx_jmb_cons_idx;
6213 di = dpr->rx_jmb_prod_idx;
6214
Matt Carlsone92967b2010-02-12 14:47:06 +00006215 for (i = di; i < di + cpycnt; i++) {
Eric Dumazet9205fd92011-11-18 06:47:01 +00006216 if (dpr->rx_jmb_buffers[i].data) {
Matt Carlsone92967b2010-02-12 14:47:06 +00006217 cpycnt = i - di;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00006218 err = -ENOSPC;
Matt Carlsone92967b2010-02-12 14:47:06 +00006219 break;
6220 }
6221 }
6222
6223 if (!cpycnt)
6224 break;
6225
6226 /* Ensure that updates to the rx_jmb_buffers ring and the
6227 * shadowed hardware producer ring from tg3_recycle_skb() are
6228 * ordered correctly WRT the skb check above.
6229 */
6230 smp_rmb();
6231
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006232 memcpy(&dpr->rx_jmb_buffers[di],
6233 &spr->rx_jmb_buffers[si],
6234 cpycnt * sizeof(struct ring_info));
6235
6236 for (i = 0; i < cpycnt; i++, di++, si++) {
6237 struct tg3_rx_buffer_desc *sbd, *dbd;
6238 sbd = &spr->rx_jmb[si].std;
6239 dbd = &dpr->rx_jmb[di].std;
6240 dbd->addr_hi = sbd->addr_hi;
6241 dbd->addr_lo = sbd->addr_lo;
6242 }
6243
Matt Carlson2c49a442010-09-30 10:34:35 +00006244 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
6245 tp->rx_jmb_ring_mask;
6246 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
6247 tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006248 }
Matt Carlsonf89f38b2010-02-12 14:47:07 +00006249
6250 return err;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006251}
6252
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006253static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
6254{
6255 struct tg3 *tp = tnapi->tp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006256
6257 /* run TX completion thread */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006258 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
Matt Carlson17375d22009-08-28 14:02:18 +00006259 tg3_tx(tnapi);
Joe Perches63c3a662011-04-26 08:12:10 +00006260 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
Michael Chan4fd7ab52007-10-12 01:39:50 -07006261 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006262 }
6263
Matt Carlsonf891ea12012-04-24 13:37:01 +00006264 if (!tnapi->rx_rcb_prod_idx)
6265 return work_done;
6266
Linus Torvalds1da177e2005-04-16 15:20:36 -07006267 /* run RX thread, within the bounds set by NAPI.
6268 * All RX "locking" is done by ensuring outside
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006269 * code synchronizes with tg3->napi.poll()
Linus Torvalds1da177e2005-04-16 15:20:36 -07006270 */
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00006271 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
Matt Carlson17375d22009-08-28 14:02:18 +00006272 work_done += tg3_rx(tnapi, budget - work_done);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006273
Joe Perches63c3a662011-04-26 08:12:10 +00006274 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00006275 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00006276 int i, err = 0;
Matt Carlsone4af1af2010-02-12 14:47:05 +00006277 u32 std_prod_idx = dpr->rx_std_prod_idx;
6278 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006279
Michael Chan7ae52892012-03-21 15:38:33 +00006280 tp->rx_refill = false;
Michael Chan91024262012-09-28 07:12:38 +00006281 for (i = 1; i <= tp->rxq_cnt; i++)
Matt Carlsonf89f38b2010-02-12 14:47:07 +00006282 err |= tg3_rx_prodring_xfer(tp, dpr,
Matt Carlson8fea32b2010-09-15 08:59:58 +00006283 &tp->napi[i].prodring);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006284
6285 wmb();
6286
Matt Carlsone4af1af2010-02-12 14:47:05 +00006287 if (std_prod_idx != dpr->rx_std_prod_idx)
6288 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6289 dpr->rx_std_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006290
Matt Carlsone4af1af2010-02-12 14:47:05 +00006291 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
6292 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6293 dpr->rx_jmb_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006294
6295 mmiowb();
Matt Carlsonf89f38b2010-02-12 14:47:07 +00006296
6297 if (err)
6298 tw32_f(HOSTCC_MODE, tp->coal_now);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006299 }
6300
David S. Miller6f535762007-10-11 18:08:29 -07006301 return work_done;
6302}
David S. Millerf7383c22005-05-18 22:50:53 -07006303
Matt Carlsondb219972011-11-04 09:15:03 +00006304static inline void tg3_reset_task_schedule(struct tg3 *tp)
6305{
6306 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
6307 schedule_work(&tp->reset_task);
6308}
6309
6310static inline void tg3_reset_task_cancel(struct tg3 *tp)
6311{
6312 cancel_work_sync(&tp->reset_task);
6313 tg3_flag_clear(tp, RESET_TASK_PENDING);
Matt Carlsonc7101352012-02-22 12:35:20 +00006314 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
Matt Carlsondb219972011-11-04 09:15:03 +00006315}
6316
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006317static int tg3_poll_msix(struct napi_struct *napi, int budget)
6318{
6319 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6320 struct tg3 *tp = tnapi->tp;
6321 int work_done = 0;
6322 struct tg3_hw_status *sblk = tnapi->hw_status;
6323
6324 while (1) {
6325 work_done = tg3_poll_work(tnapi, work_done, budget);
6326
Joe Perches63c3a662011-04-26 08:12:10 +00006327 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006328 goto tx_recovery;
6329
6330 if (unlikely(work_done >= budget))
6331 break;
6332
Matt Carlsonc6cdf432010-04-05 10:19:26 +00006333 /* tp->last_tag is used in tg3_int_reenable() below
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006334 * to tell the hw how much work has been processed,
6335 * so we must read it before checking for more work.
6336 */
6337 tnapi->last_tag = sblk->status_tag;
6338 tnapi->last_irq_tag = tnapi->last_tag;
6339 rmb();
6340
6341 /* check for RX/TX work to do */
Matt Carlson6d40db72010-04-05 10:19:20 +00006342 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
6343 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
Michael Chan7ae52892012-03-21 15:38:33 +00006344
6345 /* This test here is not race free, but will reduce
6346 * the number of interrupts by looping again.
6347 */
6348 if (tnapi == &tp->napi[1] && tp->rx_refill)
6349 continue;
6350
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006351 napi_complete(napi);
6352 /* Reenable interrupts. */
6353 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
Michael Chan7ae52892012-03-21 15:38:33 +00006354
6355 /* This test here is synchronized by napi_schedule()
6356 * and napi_complete() to close the race condition.
6357 */
6358 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
6359 tw32(HOSTCC_MODE, tp->coalesce_mode |
6360 HOSTCC_MODE_ENABLE |
6361 tnapi->coal_now);
6362 }
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006363 mmiowb();
6364 break;
6365 }
6366 }
6367
6368 return work_done;
6369
6370tx_recovery:
6371 /* work_done is guaranteed to be less than budget. */
6372 napi_complete(napi);
Matt Carlsondb219972011-11-04 09:15:03 +00006373 tg3_reset_task_schedule(tp);
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006374 return work_done;
6375}
6376
Matt Carlsone64de4e2011-04-13 11:05:05 +00006377static void tg3_process_error(struct tg3 *tp)
6378{
6379 u32 val;
6380 bool real_error = false;
6381
Joe Perches63c3a662011-04-26 08:12:10 +00006382 if (tg3_flag(tp, ERROR_PROCESSED))
Matt Carlsone64de4e2011-04-13 11:05:05 +00006383 return;
6384
6385 /* Check Flow Attention register */
6386 val = tr32(HOSTCC_FLOW_ATTN);
6387 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
6388 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6389 real_error = true;
6390 }
6391
6392 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6393 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6394 real_error = true;
6395 }
6396
6397 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6398 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6399 real_error = true;
6400 }
6401
6402 if (!real_error)
6403 return;
6404
6405 tg3_dump_state(tp);
6406
Joe Perches63c3a662011-04-26 08:12:10 +00006407 tg3_flag_set(tp, ERROR_PROCESSED);
Matt Carlsondb219972011-11-04 09:15:03 +00006408 tg3_reset_task_schedule(tp);
Matt Carlsone64de4e2011-04-13 11:05:05 +00006409}
6410
David S. Miller6f535762007-10-11 18:08:29 -07006411static int tg3_poll(struct napi_struct *napi, int budget)
6412{
Matt Carlson8ef04422009-08-28 14:01:37 +00006413 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6414 struct tg3 *tp = tnapi->tp;
David S. Miller6f535762007-10-11 18:08:29 -07006415 int work_done = 0;
Matt Carlson898a56f2009-08-28 14:02:40 +00006416 struct tg3_hw_status *sblk = tnapi->hw_status;
David S. Miller6f535762007-10-11 18:08:29 -07006417
6418 while (1) {
Matt Carlsone64de4e2011-04-13 11:05:05 +00006419 if (sblk->status & SD_STATUS_ERROR)
6420 tg3_process_error(tp);
6421
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006422 tg3_poll_link(tp);
6423
Matt Carlson17375d22009-08-28 14:02:18 +00006424 work_done = tg3_poll_work(tnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07006425
Joe Perches63c3a662011-04-26 08:12:10 +00006426 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
David S. Miller6f535762007-10-11 18:08:29 -07006427 goto tx_recovery;
6428
6429 if (unlikely(work_done >= budget))
6430 break;
6431
Joe Perches63c3a662011-04-26 08:12:10 +00006432 if (tg3_flag(tp, TAGGED_STATUS)) {
Matt Carlson17375d22009-08-28 14:02:18 +00006433 /* tp->last_tag is used in tg3_int_reenable() below
Michael Chan4fd7ab52007-10-12 01:39:50 -07006434 * to tell the hw how much work has been processed,
6435 * so we must read it before checking for more work.
6436 */
Matt Carlson898a56f2009-08-28 14:02:40 +00006437 tnapi->last_tag = sblk->status_tag;
6438 tnapi->last_irq_tag = tnapi->last_tag;
Michael Chan4fd7ab52007-10-12 01:39:50 -07006439 rmb();
6440 } else
6441 sblk->status &= ~SD_STATUS_UPDATED;
6442
Matt Carlson17375d22009-08-28 14:02:18 +00006443 if (likely(!tg3_has_work(tnapi))) {
Ben Hutchings288379f2009-01-19 16:43:59 -08006444 napi_complete(napi);
Matt Carlson17375d22009-08-28 14:02:18 +00006445 tg3_int_reenable(tnapi);
David S. Miller6f535762007-10-11 18:08:29 -07006446 break;
6447 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006448 }
6449
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006450 return work_done;
David S. Miller6f535762007-10-11 18:08:29 -07006451
6452tx_recovery:
Michael Chan4fd7ab52007-10-12 01:39:50 -07006453 /* work_done is guaranteed to be less than budget. */
Ben Hutchings288379f2009-01-19 16:43:59 -08006454 napi_complete(napi);
Matt Carlsondb219972011-11-04 09:15:03 +00006455 tg3_reset_task_schedule(tp);
Michael Chan4fd7ab52007-10-12 01:39:50 -07006456 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006457}
6458
Matt Carlson66cfd1b2010-09-30 10:34:30 +00006459static void tg3_napi_disable(struct tg3 *tp)
6460{
6461 int i;
6462
6463 for (i = tp->irq_cnt - 1; i >= 0; i--)
6464 napi_disable(&tp->napi[i].napi);
6465}
6466
6467static void tg3_napi_enable(struct tg3 *tp)
6468{
6469 int i;
6470
6471 for (i = 0; i < tp->irq_cnt; i++)
6472 napi_enable(&tp->napi[i].napi);
6473}
6474
6475static void tg3_napi_init(struct tg3 *tp)
6476{
6477 int i;
6478
6479 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6480 for (i = 1; i < tp->irq_cnt; i++)
6481 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6482}
6483
6484static void tg3_napi_fini(struct tg3 *tp)
6485{
6486 int i;
6487
6488 for (i = 0; i < tp->irq_cnt; i++)
6489 netif_napi_del(&tp->napi[i].napi);
6490}
6491
6492static inline void tg3_netif_stop(struct tg3 *tp)
6493{
6494 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6495 tg3_napi_disable(tp);
6496 netif_tx_disable(tp->dev);
6497}
6498
6499static inline void tg3_netif_start(struct tg3 *tp)
6500{
6501 /* NOTE: unconditional netif_tx_wake_all_queues is only
6502 * appropriate so long as all callers are assured to
6503 * have free tx slots (such as after tg3_init_hw)
6504 */
6505 netif_tx_wake_all_queues(tp->dev);
6506
6507 tg3_napi_enable(tp);
6508 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6509 tg3_enable_ints(tp);
6510}
6511
David S. Millerf47c11e2005-06-24 20:18:35 -07006512static void tg3_irq_quiesce(struct tg3 *tp)
6513{
Matt Carlson4f125f42009-09-01 12:55:02 +00006514 int i;
6515
David S. Millerf47c11e2005-06-24 20:18:35 -07006516 BUG_ON(tp->irq_sync);
6517
6518 tp->irq_sync = 1;
6519 smp_mb();
6520
Matt Carlson4f125f42009-09-01 12:55:02 +00006521 for (i = 0; i < tp->irq_cnt; i++)
6522 synchronize_irq(tp->napi[i].irq_vec);
David S. Millerf47c11e2005-06-24 20:18:35 -07006523}
6524
David S. Millerf47c11e2005-06-24 20:18:35 -07006525/* Fully shutdown all tg3 driver activity elsewhere in the system.
6526 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6527 * with as well. Most of the time, this is not necessary except when
6528 * shutting down the device.
6529 */
6530static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6531{
Michael Chan46966542007-07-11 19:47:19 -07006532 spin_lock_bh(&tp->lock);
David S. Millerf47c11e2005-06-24 20:18:35 -07006533 if (irq_sync)
6534 tg3_irq_quiesce(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07006535}
6536
6537static inline void tg3_full_unlock(struct tg3 *tp)
6538{
David S. Millerf47c11e2005-06-24 20:18:35 -07006539 spin_unlock_bh(&tp->lock);
6540}
6541
Michael Chanfcfa0a32006-03-20 22:28:41 -08006542/* One-shot MSI handler - Chip automatically disables interrupt
6543 * after sending MSI so driver doesn't have to do it.
6544 */
David Howells7d12e782006-10-05 14:55:46 +01006545static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
Michael Chanfcfa0a32006-03-20 22:28:41 -08006546{
Matt Carlson09943a12009-08-28 14:01:57 +00006547 struct tg3_napi *tnapi = dev_id;
6548 struct tg3 *tp = tnapi->tp;
Michael Chanfcfa0a32006-03-20 22:28:41 -08006549
Matt Carlson898a56f2009-08-28 14:02:40 +00006550 prefetch(tnapi->hw_status);
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006551 if (tnapi->rx_rcb)
6552 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Michael Chanfcfa0a32006-03-20 22:28:41 -08006553
6554 if (likely(!tg3_irq_sync(tp)))
Matt Carlson09943a12009-08-28 14:01:57 +00006555 napi_schedule(&tnapi->napi);
Michael Chanfcfa0a32006-03-20 22:28:41 -08006556
6557 return IRQ_HANDLED;
6558}
6559
Michael Chan88b06bc22005-04-21 17:13:25 -07006560/* MSI ISR - No need to check for interrupt sharing and no need to
6561 * flush status block and interrupt mailbox. PCI ordering rules
6562 * guarantee that MSI will arrive after the status block.
6563 */
David Howells7d12e782006-10-05 14:55:46 +01006564static irqreturn_t tg3_msi(int irq, void *dev_id)
Michael Chan88b06bc22005-04-21 17:13:25 -07006565{
Matt Carlson09943a12009-08-28 14:01:57 +00006566 struct tg3_napi *tnapi = dev_id;
6567 struct tg3 *tp = tnapi->tp;
Michael Chan88b06bc22005-04-21 17:13:25 -07006568
Matt Carlson898a56f2009-08-28 14:02:40 +00006569 prefetch(tnapi->hw_status);
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006570 if (tnapi->rx_rcb)
6571 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Michael Chan88b06bc22005-04-21 17:13:25 -07006572 /*
David S. Millerfac9b832005-05-18 22:46:34 -07006573 * Writing any value to intr-mbox-0 clears PCI INTA# and
Michael Chan88b06bc22005-04-21 17:13:25 -07006574 * chip-internal interrupt pending events.
David S. Millerfac9b832005-05-18 22:46:34 -07006575 * Writing non-zero to intr-mbox-0 additional tells the
Michael Chan88b06bc22005-04-21 17:13:25 -07006576 * NIC to stop sending us irqs, engaging "in-intr-handler"
6577 * event coalescing.
6578 */
Matt Carlson5b39de92011-08-31 11:44:50 +00006579 tw32_mailbox(tnapi->int_mbox, 0x00000001);
Michael Chan61487482005-09-05 17:53:19 -07006580 if (likely(!tg3_irq_sync(tp)))
Matt Carlson09943a12009-08-28 14:01:57 +00006581 napi_schedule(&tnapi->napi);
Michael Chan61487482005-09-05 17:53:19 -07006582
Michael Chan88b06bc22005-04-21 17:13:25 -07006583 return IRQ_RETVAL(1);
6584}
6585
David Howells7d12e782006-10-05 14:55:46 +01006586static irqreturn_t tg3_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006587{
Matt Carlson09943a12009-08-28 14:01:57 +00006588 struct tg3_napi *tnapi = dev_id;
6589 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00006590 struct tg3_hw_status *sblk = tnapi->hw_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006591 unsigned int handled = 1;
6592
Linus Torvalds1da177e2005-04-16 15:20:36 -07006593 /* In INTx mode, it is possible for the interrupt to arrive at
6594 * the CPU before the status block posted prior to the interrupt.
6595 * Reading the PCI State register will confirm whether the
6596 * interrupt is ours and will flush the status block.
6597 */
Michael Chand18edcb2007-03-24 20:57:11 -07006598 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
Joe Perches63c3a662011-04-26 08:12:10 +00006599 if (tg3_flag(tp, CHIP_RESETTING) ||
Michael Chand18edcb2007-03-24 20:57:11 -07006600 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6601 handled = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07006602 goto out;
David S. Millerfac9b832005-05-18 22:46:34 -07006603 }
Michael Chand18edcb2007-03-24 20:57:11 -07006604 }
6605
6606 /*
6607 * Writing any value to intr-mbox-0 clears PCI INTA# and
6608 * chip-internal interrupt pending events.
6609 * Writing non-zero to intr-mbox-0 additional tells the
6610 * NIC to stop sending us irqs, engaging "in-intr-handler"
6611 * event coalescing.
Michael Chanc04cb342007-05-07 00:26:15 -07006612 *
6613 * Flush the mailbox to de-assert the IRQ immediately to prevent
6614 * spurious interrupts. The flush impacts performance but
6615 * excessive spurious interrupts can be worse in some cases.
Michael Chand18edcb2007-03-24 20:57:11 -07006616 */
Michael Chanc04cb342007-05-07 00:26:15 -07006617 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Michael Chand18edcb2007-03-24 20:57:11 -07006618 if (tg3_irq_sync(tp))
6619 goto out;
6620 sblk->status &= ~SD_STATUS_UPDATED;
Matt Carlson17375d22009-08-28 14:02:18 +00006621 if (likely(tg3_has_work(tnapi))) {
Matt Carlson72334482009-08-28 14:03:01 +00006622 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Matt Carlson09943a12009-08-28 14:01:57 +00006623 napi_schedule(&tnapi->napi);
Michael Chand18edcb2007-03-24 20:57:11 -07006624 } else {
6625 /* No work, shared interrupt perhaps? re-enable
6626 * interrupts, and flush that PCI write
6627 */
6628 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6629 0x00000000);
David S. Millerfac9b832005-05-18 22:46:34 -07006630 }
David S. Millerf47c11e2005-06-24 20:18:35 -07006631out:
David S. Millerfac9b832005-05-18 22:46:34 -07006632 return IRQ_RETVAL(handled);
6633}
6634
David Howells7d12e782006-10-05 14:55:46 +01006635static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
David S. Millerfac9b832005-05-18 22:46:34 -07006636{
Matt Carlson09943a12009-08-28 14:01:57 +00006637 struct tg3_napi *tnapi = dev_id;
6638 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00006639 struct tg3_hw_status *sblk = tnapi->hw_status;
David S. Millerfac9b832005-05-18 22:46:34 -07006640 unsigned int handled = 1;
6641
David S. Millerfac9b832005-05-18 22:46:34 -07006642 /* In INTx mode, it is possible for the interrupt to arrive at
6643 * the CPU before the status block posted prior to the interrupt.
6644 * Reading the PCI State register will confirm whether the
6645 * interrupt is ours and will flush the status block.
6646 */
Matt Carlson898a56f2009-08-28 14:02:40 +00006647 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
Joe Perches63c3a662011-04-26 08:12:10 +00006648 if (tg3_flag(tp, CHIP_RESETTING) ||
Michael Chand18edcb2007-03-24 20:57:11 -07006649 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6650 handled = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07006651 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006652 }
Michael Chand18edcb2007-03-24 20:57:11 -07006653 }
6654
6655 /*
6656 * writing any value to intr-mbox-0 clears PCI INTA# and
6657 * chip-internal interrupt pending events.
6658 * writing non-zero to intr-mbox-0 additional tells the
6659 * NIC to stop sending us irqs, engaging "in-intr-handler"
6660 * event coalescing.
Michael Chanc04cb342007-05-07 00:26:15 -07006661 *
6662 * Flush the mailbox to de-assert the IRQ immediately to prevent
6663 * spurious interrupts. The flush impacts performance but
6664 * excessive spurious interrupts can be worse in some cases.
Michael Chand18edcb2007-03-24 20:57:11 -07006665 */
Michael Chanc04cb342007-05-07 00:26:15 -07006666 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Matt Carlson624f8e52009-04-20 06:55:01 +00006667
6668 /*
6669 * In a shared interrupt configuration, sometimes other devices'
6670 * interrupts will scream. We record the current status tag here
6671 * so that the above check can report that the screaming interrupts
6672 * are unhandled. Eventually they will be silenced.
6673 */
Matt Carlson898a56f2009-08-28 14:02:40 +00006674 tnapi->last_irq_tag = sblk->status_tag;
Matt Carlson624f8e52009-04-20 06:55:01 +00006675
Michael Chand18edcb2007-03-24 20:57:11 -07006676 if (tg3_irq_sync(tp))
6677 goto out;
Matt Carlson624f8e52009-04-20 06:55:01 +00006678
Matt Carlson72334482009-08-28 14:03:01 +00006679 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Matt Carlson624f8e52009-04-20 06:55:01 +00006680
Matt Carlson09943a12009-08-28 14:01:57 +00006681 napi_schedule(&tnapi->napi);
Matt Carlson624f8e52009-04-20 06:55:01 +00006682
David S. Millerf47c11e2005-06-24 20:18:35 -07006683out:
Linus Torvalds1da177e2005-04-16 15:20:36 -07006684 return IRQ_RETVAL(handled);
6685}
6686
Michael Chan79381092005-04-21 17:13:59 -07006687/* ISR for interrupt test */
David Howells7d12e782006-10-05 14:55:46 +01006688static irqreturn_t tg3_test_isr(int irq, void *dev_id)
Michael Chan79381092005-04-21 17:13:59 -07006689{
Matt Carlson09943a12009-08-28 14:01:57 +00006690 struct tg3_napi *tnapi = dev_id;
6691 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00006692 struct tg3_hw_status *sblk = tnapi->hw_status;
Michael Chan79381092005-04-21 17:13:59 -07006693
Michael Chanf9804dd2005-09-27 12:13:10 -07006694 if ((sblk->status & SD_STATUS_UPDATED) ||
6695 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
Michael Chanb16250e2006-09-27 16:10:14 -07006696 tg3_disable_ints(tp);
Michael Chan79381092005-04-21 17:13:59 -07006697 return IRQ_RETVAL(1);
6698 }
6699 return IRQ_RETVAL(0);
6700}
6701
Linus Torvalds1da177e2005-04-16 15:20:36 -07006702#ifdef CONFIG_NET_POLL_CONTROLLER
6703static void tg3_poll_controller(struct net_device *dev)
6704{
Matt Carlson4f125f42009-09-01 12:55:02 +00006705 int i;
Michael Chan88b06bc22005-04-21 17:13:25 -07006706 struct tg3 *tp = netdev_priv(dev);
6707
Matt Carlson4f125f42009-09-01 12:55:02 +00006708 for (i = 0; i < tp->irq_cnt; i++)
Louis Rillingfe234f02010-03-09 06:14:41 +00006709 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006710}
6711#endif
6712
Linus Torvalds1da177e2005-04-16 15:20:36 -07006713static void tg3_tx_timeout(struct net_device *dev)
6714{
6715 struct tg3 *tp = netdev_priv(dev);
6716
Michael Chanb0408752007-02-13 12:18:30 -08006717 if (netif_msg_tx_err(tp)) {
Joe Perches05dbe002010-02-17 19:44:19 +00006718 netdev_err(dev, "transmit timed out, resetting\n");
Matt Carlson97bd8e42011-04-13 11:05:04 +00006719 tg3_dump_state(tp);
Michael Chanb0408752007-02-13 12:18:30 -08006720 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006721
Matt Carlsondb219972011-11-04 09:15:03 +00006722 tg3_reset_task_schedule(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006723}
6724
Michael Chanc58ec932005-09-17 00:46:27 -07006725/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6726static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6727{
6728 u32 base = (u32) mapping & 0xffffffff;
6729
Eric Dumazet807540b2010-09-23 05:40:09 +00006730 return (base > 0xffffdcc0) && (base + len + 8 < base);
Michael Chanc58ec932005-09-17 00:46:27 -07006731}
6732
Michael Chan72f2afb2006-03-06 19:28:35 -08006733/* Test for DMA addresses > 40-bit */
6734static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6735 int len)
6736{
6737#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
Joe Perches63c3a662011-04-26 08:12:10 +00006738 if (tg3_flag(tp, 40BIT_DMA_BUG))
Eric Dumazet807540b2010-09-23 05:40:09 +00006739 return ((u64) mapping + len) > DMA_BIT_MASK(40);
Michael Chan72f2afb2006-03-06 19:28:35 -08006740 return 0;
6741#else
6742 return 0;
6743#endif
6744}
6745
Matt Carlsond1a3b732011-07-27 14:20:51 +00006746static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
Matt Carlson92cd3a12011-07-27 14:20:47 +00006747 dma_addr_t mapping, u32 len, u32 flags,
6748 u32 mss, u32 vlan)
Matt Carlson2ffcc982011-05-19 12:12:44 +00006749{
Matt Carlson92cd3a12011-07-27 14:20:47 +00006750 txbd->addr_hi = ((u64) mapping >> 32);
6751 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6752 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6753 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
Matt Carlson2ffcc982011-05-19 12:12:44 +00006754}
Linus Torvalds1da177e2005-04-16 15:20:36 -07006755
Matt Carlson84b67b22011-07-27 14:20:52 +00006756static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
Matt Carlsond1a3b732011-07-27 14:20:51 +00006757 dma_addr_t map, u32 len, u32 flags,
6758 u32 mss, u32 vlan)
6759{
6760 struct tg3 *tp = tnapi->tp;
6761 bool hwbug = false;
6762
6763 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
Rusty Russell3db1cd52011-12-19 13:56:45 +00006764 hwbug = true;
Matt Carlsond1a3b732011-07-27 14:20:51 +00006765
6766 if (tg3_4g_overflow_test(map, len))
Rusty Russell3db1cd52011-12-19 13:56:45 +00006767 hwbug = true;
Matt Carlsond1a3b732011-07-27 14:20:51 +00006768
6769 if (tg3_40bit_overflow_test(tp, map, len))
Rusty Russell3db1cd52011-12-19 13:56:45 +00006770 hwbug = true;
Matt Carlsond1a3b732011-07-27 14:20:51 +00006771
Matt Carlsona4cb4282011-12-14 11:09:58 +00006772 if (tp->dma_limit) {
Matt Carlsonb9e45482011-11-04 09:14:59 +00006773 u32 prvidx = *entry;
Matt Carlsone31aa982011-07-27 14:20:53 +00006774 u32 tmp_flag = flags & ~TXD_FLAG_END;
Matt Carlsona4cb4282011-12-14 11:09:58 +00006775 while (len > tp->dma_limit && *budget) {
6776 u32 frag_len = tp->dma_limit;
6777 len -= tp->dma_limit;
Matt Carlsone31aa982011-07-27 14:20:53 +00006778
Matt Carlsonb9e45482011-11-04 09:14:59 +00006779 /* Avoid the 8byte DMA problem */
6780 if (len <= 8) {
Matt Carlsona4cb4282011-12-14 11:09:58 +00006781 len += tp->dma_limit / 2;
6782 frag_len = tp->dma_limit / 2;
Matt Carlsone31aa982011-07-27 14:20:53 +00006783 }
6784
Matt Carlsonb9e45482011-11-04 09:14:59 +00006785 tnapi->tx_buffers[*entry].fragmented = true;
6786
6787 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6788 frag_len, tmp_flag, mss, vlan);
6789 *budget -= 1;
6790 prvidx = *entry;
6791 *entry = NEXT_TX(*entry);
6792
Matt Carlsone31aa982011-07-27 14:20:53 +00006793 map += frag_len;
6794 }
6795
6796 if (len) {
6797 if (*budget) {
6798 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6799 len, flags, mss, vlan);
Matt Carlsonb9e45482011-11-04 09:14:59 +00006800 *budget -= 1;
Matt Carlsone31aa982011-07-27 14:20:53 +00006801 *entry = NEXT_TX(*entry);
6802 } else {
Rusty Russell3db1cd52011-12-19 13:56:45 +00006803 hwbug = true;
Matt Carlsonb9e45482011-11-04 09:14:59 +00006804 tnapi->tx_buffers[prvidx].fragmented = false;
Matt Carlsone31aa982011-07-27 14:20:53 +00006805 }
6806 }
6807 } else {
Matt Carlson84b67b22011-07-27 14:20:52 +00006808 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6809 len, flags, mss, vlan);
Matt Carlsone31aa982011-07-27 14:20:53 +00006810 *entry = NEXT_TX(*entry);
6811 }
Matt Carlsond1a3b732011-07-27 14:20:51 +00006812
6813 return hwbug;
6814}
6815
Matt Carlson0d681b22011-07-27 14:20:49 +00006816static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
Matt Carlson432aa7e2011-05-19 12:12:45 +00006817{
6818 int i;
Matt Carlson0d681b22011-07-27 14:20:49 +00006819 struct sk_buff *skb;
Matt Carlsondf8944c2011-07-27 14:20:46 +00006820 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
Matt Carlson432aa7e2011-05-19 12:12:45 +00006821
Matt Carlson0d681b22011-07-27 14:20:49 +00006822 skb = txb->skb;
6823 txb->skb = NULL;
6824
Matt Carlson432aa7e2011-05-19 12:12:45 +00006825 pci_unmap_single(tnapi->tp->pdev,
6826 dma_unmap_addr(txb, mapping),
6827 skb_headlen(skb),
6828 PCI_DMA_TODEVICE);
Matt Carlsone01ee142011-07-27 14:20:50 +00006829
6830 while (txb->fragmented) {
6831 txb->fragmented = false;
6832 entry = NEXT_TX(entry);
6833 txb = &tnapi->tx_buffers[entry];
6834 }
6835
Matt Carlsonba1142e2011-11-04 09:15:00 +00006836 for (i = 0; i <= last; i++) {
Eric Dumazet9e903e02011-10-18 21:00:24 +00006837 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
Matt Carlson432aa7e2011-05-19 12:12:45 +00006838
6839 entry = NEXT_TX(entry);
6840 txb = &tnapi->tx_buffers[entry];
6841
6842 pci_unmap_page(tnapi->tp->pdev,
6843 dma_unmap_addr(txb, mapping),
Eric Dumazet9e903e02011-10-18 21:00:24 +00006844 skb_frag_size(frag), PCI_DMA_TODEVICE);
Matt Carlsone01ee142011-07-27 14:20:50 +00006845
6846 while (txb->fragmented) {
6847 txb->fragmented = false;
6848 entry = NEXT_TX(entry);
6849 txb = &tnapi->tx_buffers[entry];
6850 }
Matt Carlson432aa7e2011-05-19 12:12:45 +00006851 }
6852}
6853
Michael Chan72f2afb2006-03-06 19:28:35 -08006854/* Workaround 4GB and 40-bit hardware DMA bugs. */
Matt Carlson24f4efd2009-11-13 13:03:35 +00006855static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
David S. Miller1805b2f2011-10-24 18:18:09 -04006856 struct sk_buff **pskb,
Matt Carlson84b67b22011-07-27 14:20:52 +00006857 u32 *entry, u32 *budget,
Matt Carlson92cd3a12011-07-27 14:20:47 +00006858 u32 base_flags, u32 mss, u32 vlan)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006859{
Matt Carlson24f4efd2009-11-13 13:03:35 +00006860 struct tg3 *tp = tnapi->tp;
David S. Miller1805b2f2011-10-24 18:18:09 -04006861 struct sk_buff *new_skb, *skb = *pskb;
Michael Chanc58ec932005-09-17 00:46:27 -07006862 dma_addr_t new_addr = 0;
Matt Carlson432aa7e2011-05-19 12:12:45 +00006863 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006864
Matt Carlson41588ba2008-04-19 18:12:33 -07006865 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6866 new_skb = skb_copy(skb, GFP_ATOMIC);
6867 else {
6868 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6869
6870 new_skb = skb_copy_expand(skb,
6871 skb_headroom(skb) + more_headroom,
6872 skb_tailroom(skb), GFP_ATOMIC);
6873 }
6874
Linus Torvalds1da177e2005-04-16 15:20:36 -07006875 if (!new_skb) {
Michael Chanc58ec932005-09-17 00:46:27 -07006876 ret = -1;
6877 } else {
6878 /* New SKB is guaranteed to be linear. */
Alexander Duyckf4188d82009-12-02 16:48:38 +00006879 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6880 PCI_DMA_TODEVICE);
6881 /* Make sure the mapping succeeded */
6882 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
Alexander Duyckf4188d82009-12-02 16:48:38 +00006883 dev_kfree_skb(new_skb);
Michael Chanc58ec932005-09-17 00:46:27 -07006884 ret = -1;
Michael Chanc58ec932005-09-17 00:46:27 -07006885 } else {
Matt Carlsonb9e45482011-11-04 09:14:59 +00006886 u32 save_entry = *entry;
6887
Matt Carlson92cd3a12011-07-27 14:20:47 +00006888 base_flags |= TXD_FLAG_END;
6889
Matt Carlson84b67b22011-07-27 14:20:52 +00006890 tnapi->tx_buffers[*entry].skb = new_skb;
6891 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
Matt Carlson432aa7e2011-05-19 12:12:45 +00006892 mapping, new_addr);
6893
Matt Carlson84b67b22011-07-27 14:20:52 +00006894 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
Matt Carlsond1a3b732011-07-27 14:20:51 +00006895 new_skb->len, base_flags,
6896 mss, vlan)) {
Matt Carlsonba1142e2011-11-04 09:15:00 +00006897 tg3_tx_skb_unmap(tnapi, save_entry, -1);
Matt Carlsond1a3b732011-07-27 14:20:51 +00006898 dev_kfree_skb(new_skb);
6899 ret = -1;
6900 }
Michael Chanc58ec932005-09-17 00:46:27 -07006901 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006902 }
6903
Linus Torvalds1da177e2005-04-16 15:20:36 -07006904 dev_kfree_skb(skb);
David S. Miller1805b2f2011-10-24 18:18:09 -04006905 *pskb = new_skb;
Michael Chanc58ec932005-09-17 00:46:27 -07006906 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006907}
6908
Matt Carlson2ffcc982011-05-19 12:12:44 +00006909static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
Michael Chan52c0fd82006-06-29 20:15:54 -07006910
6911/* Use GSO to workaround a rare TSO bug that may be triggered when the
6912 * TSO header is greater than 80 bytes.
6913 */
6914static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6915{
6916 struct sk_buff *segs, *nskb;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006917 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
Michael Chan52c0fd82006-06-29 20:15:54 -07006918
6919 /* Estimate the number of fragments in the worst case */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006920 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
Michael Chan52c0fd82006-06-29 20:15:54 -07006921 netif_stop_queue(tp->dev);
Matt Carlsonf65aac12010-08-02 11:26:03 +00006922
6923 /* netif_tx_stop_queue() must be done before checking
6924 * checking tx index in tg3_tx_avail() below, because in
6925 * tg3_tx(), we update tx index before checking for
6926 * netif_tx_queue_stopped().
6927 */
6928 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006929 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
Michael Chan7f62ad52007-02-20 23:25:40 -08006930 return NETDEV_TX_BUSY;
6931
6932 netif_wake_queue(tp->dev);
Michael Chan52c0fd82006-06-29 20:15:54 -07006933 }
6934
6935 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
Hirofumi Nakagawa801678c2008-04-29 01:03:09 -07006936 if (IS_ERR(segs))
Michael Chan52c0fd82006-06-29 20:15:54 -07006937 goto tg3_tso_bug_end;
6938
6939 do {
6940 nskb = segs;
6941 segs = segs->next;
6942 nskb->next = NULL;
Matt Carlson2ffcc982011-05-19 12:12:44 +00006943 tg3_start_xmit(nskb, tp->dev);
Michael Chan52c0fd82006-06-29 20:15:54 -07006944 } while (segs);
6945
6946tg3_tso_bug_end:
6947 dev_kfree_skb(skb);
6948
6949 return NETDEV_TX_OK;
6950}
Michael Chan52c0fd82006-06-29 20:15:54 -07006951
Michael Chan5a6f3072006-03-20 22:28:05 -08006952/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
Joe Perches63c3a662011-04-26 08:12:10 +00006953 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
Michael Chan5a6f3072006-03-20 22:28:05 -08006954 */
Matt Carlson2ffcc982011-05-19 12:12:44 +00006955static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
Michael Chan5a6f3072006-03-20 22:28:05 -08006956{
6957 struct tg3 *tp = netdev_priv(dev);
Matt Carlson92cd3a12011-07-27 14:20:47 +00006958 u32 len, entry, base_flags, mss, vlan = 0;
Matt Carlson84b67b22011-07-27 14:20:52 +00006959 u32 budget;
Matt Carlson432aa7e2011-05-19 12:12:45 +00006960 int i = -1, would_hit_hwbug;
David S. Miller90079ce2008-09-11 04:52:51 -07006961 dma_addr_t mapping;
Matt Carlson24f4efd2009-11-13 13:03:35 +00006962 struct tg3_napi *tnapi;
6963 struct netdev_queue *txq;
Matt Carlson432aa7e2011-05-19 12:12:45 +00006964 unsigned int last;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006965
Matt Carlson24f4efd2009-11-13 13:03:35 +00006966 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6967 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
Joe Perches63c3a662011-04-26 08:12:10 +00006968 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlson24f4efd2009-11-13 13:03:35 +00006969 tnapi++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006970
Matt Carlson84b67b22011-07-27 14:20:52 +00006971 budget = tg3_tx_avail(tnapi);
6972
Michael Chan00b70502006-06-17 21:58:45 -07006973 /* We are running in BH disabled context with netif_tx_lock
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006974 * and TX reclaim runs via tp->napi.poll inside of a software
David S. Millerf47c11e2005-06-24 20:18:35 -07006975 * interrupt. Furthermore, IRQ processing runs lockless so we have
6976 * no IRQ context deadlocks to worry about either. Rejoice!
Linus Torvalds1da177e2005-04-16 15:20:36 -07006977 */
Matt Carlson84b67b22011-07-27 14:20:52 +00006978 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
Matt Carlson24f4efd2009-11-13 13:03:35 +00006979 if (!netif_tx_queue_stopped(txq)) {
6980 netif_tx_stop_queue(txq);
Stephen Hemminger1f064a82005-12-06 17:36:44 -08006981
6982 /* This is a hard error, log it. */
Matt Carlson5129c3a2010-04-05 10:19:23 +00006983 netdev_err(dev,
6984 "BUG! Tx Ring full when queue awake!\n");
Stephen Hemminger1f064a82005-12-06 17:36:44 -08006985 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006986 return NETDEV_TX_BUSY;
6987 }
6988
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006989 entry = tnapi->tx_prod;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006990 base_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07006991 if (skb->ip_summed == CHECKSUM_PARTIAL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006992 base_flags |= TXD_FLAG_TCPUDP_CSUM;
Matt Carlson24f4efd2009-11-13 13:03:35 +00006993
Matt Carlsonbe98da62010-07-11 09:31:46 +00006994 mss = skb_shinfo(skb)->gso_size;
6995 if (mss) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006996 struct iphdr *iph;
Matt Carlson34195c32010-07-11 09:31:42 +00006997 u32 tcp_opt_len, hdr_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006998
6999 if (skb_header_cloned(skb) &&
Eric Dumazet48855432011-10-24 07:53:03 +00007000 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7001 goto drop;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007002
Matt Carlson34195c32010-07-11 09:31:42 +00007003 iph = ip_hdr(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07007004 tcp_opt_len = tcp_optlen(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007005
Eric Dumazeta5a11952012-01-23 01:22:09 +00007006 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
Matt Carlson34195c32010-07-11 09:31:42 +00007007
Eric Dumazeta5a11952012-01-23 01:22:09 +00007008 if (!skb_is_gso_v6(skb)) {
Matt Carlson34195c32010-07-11 09:31:42 +00007009 iph->check = 0;
7010 iph->tot_len = htons(mss + hdr_len);
7011 }
7012
Michael Chan52c0fd82006-06-29 20:15:54 -07007013 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
Joe Perches63c3a662011-04-26 08:12:10 +00007014 tg3_flag(tp, TSO_BUG))
Matt Carlsonde6f31e2010-04-12 06:58:30 +00007015 return tg3_tso_bug(tp, skb);
Michael Chan52c0fd82006-06-29 20:15:54 -07007016
Linus Torvalds1da177e2005-04-16 15:20:36 -07007017 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7018 TXD_FLAG_CPU_POST_DMA);
7019
Joe Perches63c3a662011-04-26 08:12:10 +00007020 if (tg3_flag(tp, HW_TSO_1) ||
7021 tg3_flag(tp, HW_TSO_2) ||
7022 tg3_flag(tp, HW_TSO_3)) {
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07007023 tcp_hdr(skb)->check = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007024 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07007025 } else
7026 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7027 iph->daddr, 0,
7028 IPPROTO_TCP,
7029 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007030
Joe Perches63c3a662011-04-26 08:12:10 +00007031 if (tg3_flag(tp, HW_TSO_3)) {
Matt Carlson615774f2009-11-13 13:03:39 +00007032 mss |= (hdr_len & 0xc) << 12;
7033 if (hdr_len & 0x10)
7034 base_flags |= 0x00000010;
7035 base_flags |= (hdr_len & 0x3e0) << 5;
Joe Perches63c3a662011-04-26 08:12:10 +00007036 } else if (tg3_flag(tp, HW_TSO_2))
Matt Carlson92c6b8d2009-11-02 14:23:27 +00007037 mss |= hdr_len << 9;
Joe Perches63c3a662011-04-26 08:12:10 +00007038 else if (tg3_flag(tp, HW_TSO_1) ||
Matt Carlson92c6b8d2009-11-02 14:23:27 +00007039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07007040 if (tcp_opt_len || iph->ihl > 5) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007041 int tsflags;
7042
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07007043 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007044 mss |= (tsflags << 11);
7045 }
7046 } else {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07007047 if (tcp_opt_len || iph->ihl > 5) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007048 int tsflags;
7049
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07007050 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007051 base_flags |= tsflags << 12;
7052 }
7053 }
7054 }
Matt Carlsonbf933c82011-01-25 15:58:49 +00007055
Matt Carlson93a700a2011-08-31 11:44:54 +00007056 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7057 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7058 base_flags |= TXD_FLAG_JMB_PKT;
7059
Matt Carlson92cd3a12011-07-27 14:20:47 +00007060 if (vlan_tx_tag_present(skb)) {
7061 base_flags |= TXD_FLAG_VLAN;
7062 vlan = vlan_tx_tag_get(skb);
7063 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007064
Alexander Duyckf4188d82009-12-02 16:48:38 +00007065 len = skb_headlen(skb);
7066
7067 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
Eric Dumazet48855432011-10-24 07:53:03 +00007068 if (pci_dma_mapping_error(tp->pdev, mapping))
7069 goto drop;
7070
David S. Miller90079ce2008-09-11 04:52:51 -07007071
Matt Carlsonf3f3f272009-08-28 14:03:21 +00007072 tnapi->tx_buffers[entry].skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00007073 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007074
7075 would_hit_hwbug = 0;
7076
Joe Perches63c3a662011-04-26 08:12:10 +00007077 if (tg3_flag(tp, 5701_DMA_BUG))
Michael Chanc58ec932005-09-17 00:46:27 -07007078 would_hit_hwbug = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007079
Matt Carlson84b67b22011-07-27 14:20:52 +00007080 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
Matt Carlsond1a3b732011-07-27 14:20:51 +00007081 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
Matt Carlsonba1142e2011-11-04 09:15:00 +00007082 mss, vlan)) {
Matt Carlsond1a3b732011-07-27 14:20:51 +00007083 would_hit_hwbug = 1;
Matt Carlsonba1142e2011-11-04 09:15:00 +00007084 } else if (skb_shinfo(skb)->nr_frags > 0) {
Matt Carlson92cd3a12011-07-27 14:20:47 +00007085 u32 tmp_mss = mss;
7086
7087 if (!tg3_flag(tp, HW_TSO_1) &&
7088 !tg3_flag(tp, HW_TSO_2) &&
7089 !tg3_flag(tp, HW_TSO_3))
7090 tmp_mss = 0;
7091
Matt Carlsonc5665a52012-02-13 10:20:12 +00007092 /* Now loop through additional data
7093 * fragments, and queue them.
7094 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07007095 last = skb_shinfo(skb)->nr_frags - 1;
7096 for (i = 0; i <= last; i++) {
7097 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7098
Eric Dumazet9e903e02011-10-18 21:00:24 +00007099 len = skb_frag_size(frag);
Ian Campbelldc234d02011-08-24 22:28:11 +00007100 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
Ian Campbell5d6bcdf2011-10-06 11:10:48 +01007101 len, DMA_TO_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007102
Matt Carlsonf3f3f272009-08-28 14:03:21 +00007103 tnapi->tx_buffers[entry].skb = NULL;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00007104 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
Alexander Duyckf4188d82009-12-02 16:48:38 +00007105 mapping);
Ian Campbell5d6bcdf2011-10-06 11:10:48 +01007106 if (dma_mapping_error(&tp->pdev->dev, mapping))
Alexander Duyckf4188d82009-12-02 16:48:38 +00007107 goto dma_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007108
Matt Carlsonb9e45482011-11-04 09:14:59 +00007109 if (!budget ||
7110 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
Matt Carlson84b67b22011-07-27 14:20:52 +00007111 len, base_flags |
7112 ((i == last) ? TXD_FLAG_END : 0),
Matt Carlsonb9e45482011-11-04 09:14:59 +00007113 tmp_mss, vlan)) {
Matt Carlson92c6b8d2009-11-02 14:23:27 +00007114 would_hit_hwbug = 1;
Matt Carlsonb9e45482011-11-04 09:14:59 +00007115 break;
7116 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007117 }
7118 }
7119
7120 if (would_hit_hwbug) {
Matt Carlson0d681b22011-07-27 14:20:49 +00007121 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007122
7123 /* If the workaround fails due to memory/mapping
7124 * failure, silently drop this packet.
7125 */
Matt Carlson84b67b22011-07-27 14:20:52 +00007126 entry = tnapi->tx_prod;
7127 budget = tg3_tx_avail(tnapi);
David S. Miller1805b2f2011-10-24 18:18:09 -04007128 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
Matt Carlson84b67b22011-07-27 14:20:52 +00007129 base_flags, mss, vlan))
Eric Dumazet48855432011-10-24 07:53:03 +00007130 goto drop_nofree;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007131 }
7132
Richard Cochrand515b452011-06-19 03:31:41 +00007133 skb_tx_timestamp(skb);
Tom Herbert5cb917b2012-03-05 19:53:50 +00007134 netdev_tx_sent_queue(txq, skb->len);
Richard Cochrand515b452011-06-19 03:31:41 +00007135
Michael Chan6541b802012-03-04 14:48:14 +00007136 /* Sync BD data before updating mailbox */
7137 wmb();
7138
Linus Torvalds1da177e2005-04-16 15:20:36 -07007139 /* Packets are ready, update Tx producer idx local and on card. */
Matt Carlson24f4efd2009-11-13 13:03:35 +00007140 tw32_tx_mbox(tnapi->prodmbox, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007141
Matt Carlsonf3f3f272009-08-28 14:03:21 +00007142 tnapi->tx_prod = entry;
7143 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
Matt Carlson24f4efd2009-11-13 13:03:35 +00007144 netif_tx_stop_queue(txq);
Matt Carlsonf65aac12010-08-02 11:26:03 +00007145
7146 /* netif_tx_stop_queue() must be done before checking
7147 * checking tx index in tg3_tx_avail() below, because in
7148 * tg3_tx(), we update tx index before checking for
7149 * netif_tx_queue_stopped().
7150 */
7151 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00007152 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
Matt Carlson24f4efd2009-11-13 13:03:35 +00007153 netif_tx_wake_queue(txq);
Michael Chan51b91462005-09-01 17:41:28 -07007154 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007155
Eric Dumazetcdd0db02009-05-28 00:00:41 +00007156 mmiowb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07007157 return NETDEV_TX_OK;
Alexander Duyckf4188d82009-12-02 16:48:38 +00007158
7159dma_error:
Matt Carlsonba1142e2011-11-04 09:15:00 +00007160 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
Matt Carlson432aa7e2011-05-19 12:12:45 +00007161 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
Eric Dumazet48855432011-10-24 07:53:03 +00007162drop:
7163 dev_kfree_skb(skb);
7164drop_nofree:
7165 tp->tx_dropped++;
Alexander Duyckf4188d82009-12-02 16:48:38 +00007166 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007167}
7168
Matt Carlson6e01b202011-08-19 13:58:20 +00007169static void tg3_mac_loopback(struct tg3 *tp, bool enable)
7170{
7171 if (enable) {
7172 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
7173 MAC_MODE_PORT_MODE_MASK);
7174
7175 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
7176
7177 if (!tg3_flag(tp, 5705_PLUS))
7178 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7179
7180 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
7181 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
7182 else
7183 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7184 } else {
7185 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
7186
7187 if (tg3_flag(tp, 5705_PLUS) ||
7188 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
7189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7190 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
7191 }
7192
7193 tw32(MAC_MODE, tp->mac_mode);
7194 udelay(40);
7195}
7196
Matt Carlson941ec902011-08-19 13:58:23 +00007197static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
Matt Carlson5e5a7f32011-08-19 13:58:21 +00007198{
Matt Carlson941ec902011-08-19 13:58:23 +00007199 u32 val, bmcr, mac_mode, ptest = 0;
Matt Carlson5e5a7f32011-08-19 13:58:21 +00007200
7201 tg3_phy_toggle_apd(tp, false);
7202 tg3_phy_toggle_automdix(tp, 0);
7203
Matt Carlson941ec902011-08-19 13:58:23 +00007204 if (extlpbk && tg3_phy_set_extloopbk(tp))
7205 return -EIO;
7206
7207 bmcr = BMCR_FULLDPLX;
Matt Carlson5e5a7f32011-08-19 13:58:21 +00007208 switch (speed) {
7209 case SPEED_10:
7210 break;
7211 case SPEED_100:
7212 bmcr |= BMCR_SPEED100;
7213 break;
7214 case SPEED_1000:
7215 default:
7216 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7217 speed = SPEED_100;
7218 bmcr |= BMCR_SPEED100;
7219 } else {
7220 speed = SPEED_1000;
7221 bmcr |= BMCR_SPEED1000;
7222 }
7223 }
7224
Matt Carlson941ec902011-08-19 13:58:23 +00007225 if (extlpbk) {
7226 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
7227 tg3_readphy(tp, MII_CTRL1000, &val);
7228 val |= CTL1000_AS_MASTER |
7229 CTL1000_ENABLE_MASTER;
7230 tg3_writephy(tp, MII_CTRL1000, val);
7231 } else {
7232 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
7233 MII_TG3_FET_PTEST_TRIM_2;
7234 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
7235 }
7236 } else
7237 bmcr |= BMCR_LOOPBACK;
7238
Matt Carlson5e5a7f32011-08-19 13:58:21 +00007239 tg3_writephy(tp, MII_BMCR, bmcr);
7240
7241 /* The write needs to be flushed for the FETs */
7242 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7243 tg3_readphy(tp, MII_BMCR, &bmcr);
7244
7245 udelay(40);
7246
7247 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
Matt Carlson941ec902011-08-19 13:58:23 +00007249 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
Matt Carlson5e5a7f32011-08-19 13:58:21 +00007250 MII_TG3_FET_PTEST_FRC_TX_LINK |
7251 MII_TG3_FET_PTEST_FRC_TX_LOCK);
7252
7253 /* The write needs to be flushed for the AC131 */
7254 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
7255 }
7256
7257 /* Reset to prevent losing 1st rx packet intermittently */
7258 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
7259 tg3_flag(tp, 5780_CLASS)) {
7260 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7261 udelay(10);
7262 tw32_f(MAC_RX_MODE, tp->rx_mode);
7263 }
7264
7265 mac_mode = tp->mac_mode &
7266 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
7267 if (speed == SPEED_1000)
7268 mac_mode |= MAC_MODE_PORT_MODE_GMII;
7269 else
7270 mac_mode |= MAC_MODE_PORT_MODE_MII;
7271
7272 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
7273 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7274
7275 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7276 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7277 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7278 mac_mode |= MAC_MODE_LINK_POLARITY;
7279
7280 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7281 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7282 }
7283
7284 tw32(MAC_MODE, mac_mode);
7285 udelay(40);
Matt Carlson941ec902011-08-19 13:58:23 +00007286
7287 return 0;
Matt Carlson5e5a7f32011-08-19 13:58:21 +00007288}
7289
Michał Mirosławc8f44af2011-11-15 15:29:55 +00007290static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00007291{
7292 struct tg3 *tp = netdev_priv(dev);
7293
7294 if (features & NETIF_F_LOOPBACK) {
7295 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7296 return;
7297
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00007298 spin_lock_bh(&tp->lock);
Matt Carlson6e01b202011-08-19 13:58:20 +00007299 tg3_mac_loopback(tp, true);
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00007300 netif_carrier_on(tp->dev);
7301 spin_unlock_bh(&tp->lock);
7302 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
7303 } else {
7304 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
7305 return;
7306
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00007307 spin_lock_bh(&tp->lock);
Matt Carlson6e01b202011-08-19 13:58:20 +00007308 tg3_mac_loopback(tp, false);
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00007309 /* Force link status check */
7310 tg3_setup_phy(tp, 1);
7311 spin_unlock_bh(&tp->lock);
7312 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7313 }
7314}
7315
Michał Mirosławc8f44af2011-11-15 15:29:55 +00007316static netdev_features_t tg3_fix_features(struct net_device *dev,
7317 netdev_features_t features)
Michał Mirosławdc668912011-04-07 03:35:07 +00007318{
7319 struct tg3 *tp = netdev_priv(dev);
7320
Joe Perches63c3a662011-04-26 08:12:10 +00007321 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
Michał Mirosławdc668912011-04-07 03:35:07 +00007322 features &= ~NETIF_F_ALL_TSO;
7323
7324 return features;
7325}
7326
Michał Mirosławc8f44af2011-11-15 15:29:55 +00007327static int tg3_set_features(struct net_device *dev, netdev_features_t features)
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00007328{
Michał Mirosławc8f44af2011-11-15 15:29:55 +00007329 netdev_features_t changed = dev->features ^ features;
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00007330
7331 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7332 tg3_set_loopback(dev, features);
7333
7334 return 0;
7335}
7336
Matt Carlson21f581a2009-08-28 14:00:25 +00007337static void tg3_rx_prodring_free(struct tg3 *tp,
7338 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007339{
Linus Torvalds1da177e2005-04-16 15:20:36 -07007340 int i;
7341
Matt Carlson8fea32b2010-09-15 08:59:58 +00007342 if (tpr != &tp->napi[0].prodring) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007343 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
Matt Carlson2c49a442010-09-30 10:34:35 +00007344 i = (i + 1) & tp->rx_std_ring_mask)
Eric Dumazet9205fd92011-11-18 06:47:01 +00007345 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007346 tp->rx_pkt_map_sz);
7347
Joe Perches63c3a662011-04-26 08:12:10 +00007348 if (tg3_flag(tp, JUMBO_CAPABLE)) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007349 for (i = tpr->rx_jmb_cons_idx;
7350 i != tpr->rx_jmb_prod_idx;
Matt Carlson2c49a442010-09-30 10:34:35 +00007351 i = (i + 1) & tp->rx_jmb_ring_mask) {
Eric Dumazet9205fd92011-11-18 06:47:01 +00007352 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007353 TG3_RX_JMB_MAP_SZ);
7354 }
7355 }
7356
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007357 return;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007358 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007359
Matt Carlson2c49a442010-09-30 10:34:35 +00007360 for (i = 0; i <= tp->rx_std_ring_mask; i++)
Eric Dumazet9205fd92011-11-18 06:47:01 +00007361 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007362 tp->rx_pkt_map_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007363
Joe Perches63c3a662011-04-26 08:12:10 +00007364 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00007365 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
Eric Dumazet9205fd92011-11-18 06:47:01 +00007366 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007367 TG3_RX_JMB_MAP_SZ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007368 }
7369}
7370
Matt Carlsonc6cdf432010-04-05 10:19:26 +00007371/* Initialize rx rings for packet processing.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007372 *
7373 * The chip has been shut down and the driver detached from
7374 * the networking, so no interrupts or new tx packets will
7375 * end up in the driver. tp->{tx,}lock are held and thus
7376 * we may not sleep.
7377 */
Matt Carlson21f581a2009-08-28 14:00:25 +00007378static int tg3_rx_prodring_alloc(struct tg3 *tp,
7379 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007380{
Matt Carlson287be122009-08-28 13:58:46 +00007381 u32 i, rx_pkt_dma_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007382
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007383 tpr->rx_std_cons_idx = 0;
7384 tpr->rx_std_prod_idx = 0;
7385 tpr->rx_jmb_cons_idx = 0;
7386 tpr->rx_jmb_prod_idx = 0;
7387
Matt Carlson8fea32b2010-09-15 08:59:58 +00007388 if (tpr != &tp->napi[0].prodring) {
Matt Carlson2c49a442010-09-30 10:34:35 +00007389 memset(&tpr->rx_std_buffers[0], 0,
7390 TG3_RX_STD_BUFF_RING_SIZE(tp));
Matt Carlson48035722010-10-14 10:37:43 +00007391 if (tpr->rx_jmb_buffers)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007392 memset(&tpr->rx_jmb_buffers[0], 0,
Matt Carlson2c49a442010-09-30 10:34:35 +00007393 TG3_RX_JMB_BUFF_RING_SIZE(tp));
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007394 goto done;
7395 }
7396
Linus Torvalds1da177e2005-04-16 15:20:36 -07007397 /* Zero out all descriptors. */
Matt Carlson2c49a442010-09-30 10:34:35 +00007398 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007399
Matt Carlson287be122009-08-28 13:58:46 +00007400 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
Joe Perches63c3a662011-04-26 08:12:10 +00007401 if (tg3_flag(tp, 5780_CLASS) &&
Matt Carlson287be122009-08-28 13:58:46 +00007402 tp->dev->mtu > ETH_DATA_LEN)
7403 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7404 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
Michael Chan7e72aad2005-07-25 12:31:17 -07007405
Linus Torvalds1da177e2005-04-16 15:20:36 -07007406 /* Initialize invariants of the rings, we only set this
7407 * stuff once. This works because the card does not
7408 * write into the rx buffer posting rings.
7409 */
Matt Carlson2c49a442010-09-30 10:34:35 +00007410 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007411 struct tg3_rx_buffer_desc *rxd;
7412
Matt Carlson21f581a2009-08-28 14:00:25 +00007413 rxd = &tpr->rx_std[i];
Matt Carlson287be122009-08-28 13:58:46 +00007414 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007415 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7416 rxd->opaque = (RXD_OPAQUE_RING_STD |
7417 (i << RXD_OPAQUE_INDEX_SHIFT));
7418 }
7419
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007420 /* Now allocate fresh SKBs for each rx ring. */
7421 for (i = 0; i < tp->rx_pending; i++) {
Eric Dumazet8d4057a2012-04-27 00:34:49 +00007422 unsigned int frag_size;
7423
7424 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
7425 &frag_size) < 0) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007426 netdev_warn(tp->dev,
7427 "Using a smaller RX standard ring. Only "
7428 "%d out of %d buffers were allocated "
7429 "successfully\n", i, tp->rx_pending);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007430 if (i == 0)
7431 goto initfail;
7432 tp->rx_pending = i;
7433 break;
7434 }
7435 }
7436
Joe Perches63c3a662011-04-26 08:12:10 +00007437 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007438 goto done;
7439
Matt Carlson2c49a442010-09-30 10:34:35 +00007440 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007441
Joe Perches63c3a662011-04-26 08:12:10 +00007442 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
Matt Carlson0d86df82010-02-17 15:17:00 +00007443 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007444
Matt Carlson2c49a442010-09-30 10:34:35 +00007445 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
Matt Carlson0d86df82010-02-17 15:17:00 +00007446 struct tg3_rx_buffer_desc *rxd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007447
Matt Carlson0d86df82010-02-17 15:17:00 +00007448 rxd = &tpr->rx_jmb[i].std;
7449 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7450 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7451 RXD_FLAG_JUMBO;
7452 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7453 (i << RXD_OPAQUE_INDEX_SHIFT));
7454 }
7455
7456 for (i = 0; i < tp->rx_jumbo_pending; i++) {
Eric Dumazet8d4057a2012-04-27 00:34:49 +00007457 unsigned int frag_size;
7458
7459 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
7460 &frag_size) < 0) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007461 netdev_warn(tp->dev,
7462 "Using a smaller RX jumbo ring. Only %d "
7463 "out of %d buffers were allocated "
7464 "successfully\n", i, tp->rx_jumbo_pending);
Matt Carlson0d86df82010-02-17 15:17:00 +00007465 if (i == 0)
7466 goto initfail;
7467 tp->rx_jumbo_pending = i;
7468 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007469 }
7470 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007471
7472done:
Michael Chan32d8c572006-07-25 16:38:29 -07007473 return 0;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007474
7475initfail:
Matt Carlson21f581a2009-08-28 14:00:25 +00007476 tg3_rx_prodring_free(tp, tpr);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007477 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007478}
7479
Matt Carlson21f581a2009-08-28 14:00:25 +00007480static void tg3_rx_prodring_fini(struct tg3 *tp,
7481 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007482{
Matt Carlson21f581a2009-08-28 14:00:25 +00007483 kfree(tpr->rx_std_buffers);
7484 tpr->rx_std_buffers = NULL;
7485 kfree(tpr->rx_jmb_buffers);
7486 tpr->rx_jmb_buffers = NULL;
7487 if (tpr->rx_std) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007488 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7489 tpr->rx_std, tpr->rx_std_mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00007490 tpr->rx_std = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007491 }
Matt Carlson21f581a2009-08-28 14:00:25 +00007492 if (tpr->rx_jmb) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007493 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7494 tpr->rx_jmb, tpr->rx_jmb_mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00007495 tpr->rx_jmb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007496 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007497}
7498
Matt Carlson21f581a2009-08-28 14:00:25 +00007499static int tg3_rx_prodring_init(struct tg3 *tp,
7500 struct tg3_rx_prodring_set *tpr)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007501{
Matt Carlson2c49a442010-09-30 10:34:35 +00007502 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7503 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00007504 if (!tpr->rx_std_buffers)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007505 return -ENOMEM;
7506
Matt Carlson4bae65c2010-11-24 08:31:52 +00007507 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7508 TG3_RX_STD_RING_BYTES(tp),
7509 &tpr->rx_std_mapping,
7510 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00007511 if (!tpr->rx_std)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007512 goto err_out;
7513
Joe Perches63c3a662011-04-26 08:12:10 +00007514 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00007515 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
Matt Carlson21f581a2009-08-28 14:00:25 +00007516 GFP_KERNEL);
7517 if (!tpr->rx_jmb_buffers)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007518 goto err_out;
7519
Matt Carlson4bae65c2010-11-24 08:31:52 +00007520 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7521 TG3_RX_JMB_RING_BYTES(tp),
7522 &tpr->rx_jmb_mapping,
7523 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00007524 if (!tpr->rx_jmb)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007525 goto err_out;
7526 }
7527
7528 return 0;
7529
7530err_out:
Matt Carlson21f581a2009-08-28 14:00:25 +00007531 tg3_rx_prodring_fini(tp, tpr);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007532 return -ENOMEM;
7533}
7534
7535/* Free up pending packets in all rx/tx rings.
7536 *
7537 * The chip has been shut down and the driver detached from
7538 * the networking, so no interrupts or new tx packets will
7539 * end up in the driver. tp->{tx,}lock is not held and we are not
7540 * in an interrupt context and thus may sleep.
7541 */
7542static void tg3_free_rings(struct tg3 *tp)
7543{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007544 int i, j;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007545
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007546 for (j = 0; j < tp->irq_cnt; j++) {
7547 struct tg3_napi *tnapi = &tp->napi[j];
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007548
Matt Carlson8fea32b2010-09-15 08:59:58 +00007549 tg3_rx_prodring_free(tp, &tnapi->prodring);
Matt Carlsonb28f6422010-06-05 17:24:32 +00007550
Matt Carlson0c1d0e22009-09-01 13:16:33 +00007551 if (!tnapi->tx_buffers)
7552 continue;
7553
Matt Carlson0d681b22011-07-27 14:20:49 +00007554 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7555 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007556
Matt Carlson0d681b22011-07-27 14:20:49 +00007557 if (!skb)
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007558 continue;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007559
Matt Carlsonba1142e2011-11-04 09:15:00 +00007560 tg3_tx_skb_unmap(tnapi, i,
7561 skb_shinfo(skb)->nr_frags - 1);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007562
7563 dev_kfree_skb_any(skb);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007564 }
Tom Herbert5cb917b2012-03-05 19:53:50 +00007565 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007566 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007567}
7568
7569/* Initialize tx/rx rings for packet processing.
7570 *
7571 * The chip has been shut down and the driver detached from
7572 * the networking, so no interrupts or new tx packets will
7573 * end up in the driver. tp->{tx,}lock are held and thus
7574 * we may not sleep.
7575 */
7576static int tg3_init_rings(struct tg3 *tp)
7577{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007578 int i;
Matt Carlson72334482009-08-28 14:03:01 +00007579
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007580 /* Free up all the SKBs. */
7581 tg3_free_rings(tp);
7582
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007583 for (i = 0; i < tp->irq_cnt; i++) {
7584 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007585
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007586 tnapi->last_tag = 0;
7587 tnapi->last_irq_tag = 0;
7588 tnapi->hw_status->status = 0;
7589 tnapi->hw_status->status_tag = 0;
7590 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7591
7592 tnapi->tx_prod = 0;
7593 tnapi->tx_cons = 0;
Matt Carlson0c1d0e22009-09-01 13:16:33 +00007594 if (tnapi->tx_ring)
7595 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007596
7597 tnapi->rx_rcb_ptr = 0;
Matt Carlson0c1d0e22009-09-01 13:16:33 +00007598 if (tnapi->rx_rcb)
7599 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007600
Matt Carlson8fea32b2010-09-15 08:59:58 +00007601 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
Matt Carlsone4af1af2010-02-12 14:47:05 +00007602 tg3_free_rings(tp);
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007603 return -ENOMEM;
Matt Carlsone4af1af2010-02-12 14:47:05 +00007604 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007605 }
Matt Carlson72334482009-08-28 14:03:01 +00007606
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007607 return 0;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007608}
7609
Michael Chan49a359e2012-09-28 07:12:37 +00007610static void tg3_mem_tx_release(struct tg3 *tp)
7611{
7612 int i;
7613
7614 for (i = 0; i < tp->irq_max; i++) {
7615 struct tg3_napi *tnapi = &tp->napi[i];
7616
7617 if (tnapi->tx_ring) {
7618 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7619 tnapi->tx_ring, tnapi->tx_desc_mapping);
7620 tnapi->tx_ring = NULL;
7621 }
7622
7623 kfree(tnapi->tx_buffers);
7624 tnapi->tx_buffers = NULL;
7625 }
7626}
7627
7628static int tg3_mem_tx_acquire(struct tg3 *tp)
7629{
7630 int i;
7631 struct tg3_napi *tnapi = &tp->napi[0];
7632
7633 /* If multivector TSS is enabled, vector 0 does not handle
7634 * tx interrupts. Don't allocate any resources for it.
7635 */
7636 if (tg3_flag(tp, ENABLE_TSS))
7637 tnapi++;
7638
7639 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
7640 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
7641 TG3_TX_RING_SIZE, GFP_KERNEL);
7642 if (!tnapi->tx_buffers)
7643 goto err_out;
7644
7645 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7646 TG3_TX_RING_BYTES,
7647 &tnapi->tx_desc_mapping,
7648 GFP_KERNEL);
7649 if (!tnapi->tx_ring)
7650 goto err_out;
7651 }
7652
7653 return 0;
7654
7655err_out:
7656 tg3_mem_tx_release(tp);
7657 return -ENOMEM;
7658}
7659
7660static void tg3_mem_rx_release(struct tg3 *tp)
7661{
7662 int i;
7663
7664 for (i = 0; i < tp->irq_max; i++) {
7665 struct tg3_napi *tnapi = &tp->napi[i];
7666
7667 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7668
7669 if (!tnapi->rx_rcb)
7670 continue;
7671
7672 dma_free_coherent(&tp->pdev->dev,
7673 TG3_RX_RCB_RING_BYTES(tp),
7674 tnapi->rx_rcb,
7675 tnapi->rx_rcb_mapping);
7676 tnapi->rx_rcb = NULL;
7677 }
7678}
7679
7680static int tg3_mem_rx_acquire(struct tg3 *tp)
7681{
7682 unsigned int i, limit;
7683
7684 limit = tp->rxq_cnt;
7685
7686 /* If RSS is enabled, we need a (dummy) producer ring
7687 * set on vector zero. This is the true hw prodring.
7688 */
7689 if (tg3_flag(tp, ENABLE_RSS))
7690 limit++;
7691
7692 for (i = 0; i < limit; i++) {
7693 struct tg3_napi *tnapi = &tp->napi[i];
7694
7695 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7696 goto err_out;
7697
7698 /* If multivector RSS is enabled, vector 0
7699 * does not handle rx or tx interrupts.
7700 * Don't allocate any resources for it.
7701 */
7702 if (!i && tg3_flag(tp, ENABLE_RSS))
7703 continue;
7704
7705 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7706 TG3_RX_RCB_RING_BYTES(tp),
7707 &tnapi->rx_rcb_mapping,
7708 GFP_KERNEL);
7709 if (!tnapi->rx_rcb)
7710 goto err_out;
7711
7712 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7713 }
7714
7715 return 0;
7716
7717err_out:
7718 tg3_mem_rx_release(tp);
7719 return -ENOMEM;
7720}
7721
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007722/*
7723 * Must not be invoked with interrupt sources disabled and
7724 * the hardware shutdown down.
7725 */
7726static void tg3_free_consistent(struct tg3 *tp)
7727{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007728 int i;
Matt Carlson898a56f2009-08-28 14:02:40 +00007729
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007730 for (i = 0; i < tp->irq_cnt; i++) {
7731 struct tg3_napi *tnapi = &tp->napi[i];
7732
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007733 if (tnapi->hw_status) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007734 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7735 tnapi->hw_status,
7736 tnapi->status_mapping);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007737 tnapi->hw_status = NULL;
7738 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007739 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007740
Michael Chan49a359e2012-09-28 07:12:37 +00007741 tg3_mem_rx_release(tp);
7742 tg3_mem_tx_release(tp);
7743
Linus Torvalds1da177e2005-04-16 15:20:36 -07007744 if (tp->hw_stats) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007745 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7746 tp->hw_stats, tp->stats_mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007747 tp->hw_stats = NULL;
7748 }
7749}
7750
7751/*
7752 * Must not be invoked with interrupt sources disabled and
7753 * the hardware shutdown down. Can sleep.
7754 */
7755static int tg3_alloc_consistent(struct tg3 *tp)
7756{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007757 int i;
Matt Carlson898a56f2009-08-28 14:02:40 +00007758
Matt Carlson4bae65c2010-11-24 08:31:52 +00007759 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7760 sizeof(struct tg3_hw_stats),
7761 &tp->stats_mapping,
7762 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007763 if (!tp->hw_stats)
7764 goto err_out;
7765
Linus Torvalds1da177e2005-04-16 15:20:36 -07007766 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7767
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007768 for (i = 0; i < tp->irq_cnt; i++) {
7769 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00007770 struct tg3_hw_status *sblk;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007771
Matt Carlson4bae65c2010-11-24 08:31:52 +00007772 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7773 TG3_HW_STATUS_SIZE,
7774 &tnapi->status_mapping,
7775 GFP_KERNEL);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007776 if (!tnapi->hw_status)
7777 goto err_out;
7778
7779 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00007780 sblk = tnapi->hw_status;
7781
Michael Chan49a359e2012-09-28 07:12:37 +00007782 if (tg3_flag(tp, ENABLE_RSS)) {
7783 u16 *prodptr = 0;
Matt Carlson8fea32b2010-09-15 08:59:58 +00007784
Michael Chan49a359e2012-09-28 07:12:37 +00007785 /*
7786 * When RSS is enabled, the status block format changes
7787 * slightly. The "rx_jumbo_consumer", "reserved",
7788 * and "rx_mini_consumer" members get mapped to the
7789 * other three rx return ring producer indexes.
7790 */
7791 switch (i) {
7792 case 1:
7793 prodptr = &sblk->idx[0].rx_producer;
7794 break;
7795 case 2:
7796 prodptr = &sblk->rx_jumbo_consumer;
7797 break;
7798 case 3:
7799 prodptr = &sblk->reserved;
7800 break;
7801 case 4:
7802 prodptr = &sblk->rx_mini_consumer;
Matt Carlsonf891ea12012-04-24 13:37:01 +00007803 break;
7804 }
Michael Chan49a359e2012-09-28 07:12:37 +00007805 tnapi->rx_rcb_prod_idx = prodptr;
7806 } else {
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00007807 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00007808 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007809 }
7810
Michael Chan49a359e2012-09-28 07:12:37 +00007811 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
7812 goto err_out;
7813
Linus Torvalds1da177e2005-04-16 15:20:36 -07007814 return 0;
7815
7816err_out:
7817 tg3_free_consistent(tp);
7818 return -ENOMEM;
7819}
7820
7821#define MAX_WAIT_CNT 1000
7822
7823/* To stop a block, clear the enable bit and poll till it
7824 * clears. tp->lock is held.
7825 */
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007826static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007827{
7828 unsigned int i;
7829 u32 val;
7830
Joe Perches63c3a662011-04-26 08:12:10 +00007831 if (tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007832 switch (ofs) {
7833 case RCVLSC_MODE:
7834 case DMAC_MODE:
7835 case MBFREE_MODE:
7836 case BUFMGR_MODE:
7837 case MEMARB_MODE:
7838 /* We can't enable/disable these bits of the
7839 * 5705/5750, just say success.
7840 */
7841 return 0;
7842
7843 default:
7844 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07007845 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007846 }
7847
7848 val = tr32(ofs);
7849 val &= ~enable_bit;
7850 tw32_f(ofs, val);
7851
7852 for (i = 0; i < MAX_WAIT_CNT; i++) {
7853 udelay(100);
7854 val = tr32(ofs);
7855 if ((val & enable_bit) == 0)
7856 break;
7857 }
7858
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007859 if (i == MAX_WAIT_CNT && !silent) {
Matt Carlson2445e462010-04-05 10:19:21 +00007860 dev_err(&tp->pdev->dev,
7861 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7862 ofs, enable_bit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007863 return -ENODEV;
7864 }
7865
7866 return 0;
7867}
7868
7869/* tp->lock is held. */
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007870static int tg3_abort_hw(struct tg3 *tp, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007871{
7872 int i, err;
7873
7874 tg3_disable_ints(tp);
7875
7876 tp->rx_mode &= ~RX_MODE_ENABLE;
7877 tw32_f(MAC_RX_MODE, tp->rx_mode);
7878 udelay(10);
7879
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007880 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7881 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7882 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7883 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7884 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7885 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007886
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007887 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7888 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7889 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7890 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7891 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7892 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7893 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007894
7895 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7896 tw32_f(MAC_MODE, tp->mac_mode);
7897 udelay(40);
7898
7899 tp->tx_mode &= ~TX_MODE_ENABLE;
7900 tw32_f(MAC_TX_MODE, tp->tx_mode);
7901
7902 for (i = 0; i < MAX_WAIT_CNT; i++) {
7903 udelay(100);
7904 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7905 break;
7906 }
7907 if (i >= MAX_WAIT_CNT) {
Matt Carlsonab96b242010-04-05 10:19:22 +00007908 dev_err(&tp->pdev->dev,
7909 "%s timed out, TX_MODE_ENABLE will not clear "
7910 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
Michael Chane6de8ad2005-05-05 14:42:41 -07007911 err |= -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007912 }
7913
Michael Chane6de8ad2005-05-05 14:42:41 -07007914 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007915 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7916 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007917
7918 tw32(FTQ_RESET, 0xffffffff);
7919 tw32(FTQ_RESET, 0x00000000);
7920
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007921 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7922 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007923
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007924 for (i = 0; i < tp->irq_cnt; i++) {
7925 struct tg3_napi *tnapi = &tp->napi[i];
7926 if (tnapi->hw_status)
7927 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7928 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007929
Linus Torvalds1da177e2005-04-16 15:20:36 -07007930 return err;
7931}
7932
Michael Chanee6a99b2007-07-18 21:49:10 -07007933/* Save PCI command register before chip reset */
7934static void tg3_save_pci_state(struct tg3 *tp)
7935{
Matt Carlson8a6eac92007-10-21 16:17:55 -07007936 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
Michael Chanee6a99b2007-07-18 21:49:10 -07007937}
7938
7939/* Restore PCI state after chip reset */
7940static void tg3_restore_pci_state(struct tg3 *tp)
7941{
7942 u32 val;
7943
7944 /* Re-enable indirect register accesses. */
7945 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7946 tp->misc_host_ctrl);
7947
7948 /* Set MAX PCI retry to zero. */
7949 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7950 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
Joe Perches63c3a662011-04-26 08:12:10 +00007951 tg3_flag(tp, PCIX_MODE))
Michael Chanee6a99b2007-07-18 21:49:10 -07007952 val |= PCISTATE_RETRY_SAME_DMA;
Matt Carlson0d3031d2007-10-10 18:02:43 -07007953 /* Allow reads and writes to the APE register and memory space. */
Joe Perches63c3a662011-04-26 08:12:10 +00007954 if (tg3_flag(tp, ENABLE_APE))
Matt Carlson0d3031d2007-10-10 18:02:43 -07007955 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00007956 PCISTATE_ALLOW_APE_SHMEM_WR |
7957 PCISTATE_ALLOW_APE_PSPACE_WR;
Michael Chanee6a99b2007-07-18 21:49:10 -07007958 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7959
Matt Carlson8a6eac92007-10-21 16:17:55 -07007960 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
Michael Chanee6a99b2007-07-18 21:49:10 -07007961
Matt Carlson2c55a3d2011-11-28 09:41:04 +00007962 if (!tg3_flag(tp, PCI_EXPRESS)) {
7963 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7964 tp->pci_cacheline_sz);
7965 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7966 tp->pci_lat_timer);
Michael Chan114342f2007-10-15 02:12:26 -07007967 }
Matt Carlson5f5c51e2007-11-12 21:19:37 -08007968
Michael Chanee6a99b2007-07-18 21:49:10 -07007969 /* Make sure PCI-X relaxed ordering bit is clear. */
Joe Perches63c3a662011-04-26 08:12:10 +00007970 if (tg3_flag(tp, PCIX_MODE)) {
Matt Carlson9974a352007-10-07 23:27:28 -07007971 u16 pcix_cmd;
7972
7973 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7974 &pcix_cmd);
7975 pcix_cmd &= ~PCI_X_CMD_ERO;
7976 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7977 pcix_cmd);
7978 }
Michael Chanee6a99b2007-07-18 21:49:10 -07007979
Joe Perches63c3a662011-04-26 08:12:10 +00007980 if (tg3_flag(tp, 5780_CLASS)) {
Michael Chanee6a99b2007-07-18 21:49:10 -07007981
7982 /* Chip reset on 5780 will reset MSI enable bit,
7983 * so need to restore it.
7984 */
Joe Perches63c3a662011-04-26 08:12:10 +00007985 if (tg3_flag(tp, USING_MSI)) {
Michael Chanee6a99b2007-07-18 21:49:10 -07007986 u16 ctrl;
7987
7988 pci_read_config_word(tp->pdev,
7989 tp->msi_cap + PCI_MSI_FLAGS,
7990 &ctrl);
7991 pci_write_config_word(tp->pdev,
7992 tp->msi_cap + PCI_MSI_FLAGS,
7993 ctrl | PCI_MSI_FLAGS_ENABLE);
7994 val = tr32(MSGINT_MODE);
7995 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7996 }
7997 }
7998}
7999
Linus Torvalds1da177e2005-04-16 15:20:36 -07008000/* tp->lock is held. */
8001static int tg3_chip_reset(struct tg3 *tp)
8002{
8003 u32 val;
Michael Chan1ee582d2005-08-09 20:16:46 -07008004 void (*write_op)(struct tg3 *, u32, u32);
Matt Carlson4f125f42009-09-01 12:55:02 +00008005 int i, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008006
David S. Millerf49639e2006-06-09 11:58:36 -07008007 tg3_nvram_lock(tp);
8008
Matt Carlson77b483f2008-08-15 14:07:24 -07008009 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8010
David S. Millerf49639e2006-06-09 11:58:36 -07008011 /* No matching tg3_nvram_unlock() after this because
8012 * chip reset below will undo the nvram lock.
8013 */
8014 tp->nvram_lock_cnt = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008015
Michael Chanee6a99b2007-07-18 21:49:10 -07008016 /* GRC_MISC_CFG core clock reset will clear the memory
8017 * enable bit in PCI register 4 and the MSI enable bit
8018 * on some chips, so we save relevant registers here.
8019 */
8020 tg3_save_pci_state(tp);
8021
Michael Chand9ab5ad12006-03-20 22:27:35 -08008022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
Joe Perches63c3a662011-04-26 08:12:10 +00008023 tg3_flag(tp, 5755_PLUS))
Michael Chand9ab5ad12006-03-20 22:27:35 -08008024 tw32(GRC_FASTBOOT_PC, 0);
8025
Linus Torvalds1da177e2005-04-16 15:20:36 -07008026 /*
8027 * We must avoid the readl() that normally takes place.
8028 * It locks machines, causes machine checks, and other
8029 * fun things. So, temporarily disable the 5701
8030 * hardware workaround, while we do the reset.
8031 */
Michael Chan1ee582d2005-08-09 20:16:46 -07008032 write_op = tp->write32;
8033 if (write_op == tg3_write_flush_reg32)
8034 tp->write32 = tg3_write32;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008035
Michael Chand18edcb2007-03-24 20:57:11 -07008036 /* Prevent the irq handler from reading or writing PCI registers
8037 * during chip reset when the memory enable bit in the PCI command
8038 * register may be cleared. The chip does not generate interrupt
8039 * at this time, but the irq handler may still be called due to irq
8040 * sharing or irqpoll.
8041 */
Joe Perches63c3a662011-04-26 08:12:10 +00008042 tg3_flag_set(tp, CHIP_RESETTING);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008043 for (i = 0; i < tp->irq_cnt; i++) {
8044 struct tg3_napi *tnapi = &tp->napi[i];
8045 if (tnapi->hw_status) {
8046 tnapi->hw_status->status = 0;
8047 tnapi->hw_status->status_tag = 0;
8048 }
8049 tnapi->last_tag = 0;
8050 tnapi->last_irq_tag = 0;
Michael Chanb8fa2f32007-04-06 17:35:37 -07008051 }
Michael Chand18edcb2007-03-24 20:57:11 -07008052 smp_mb();
Matt Carlson4f125f42009-09-01 12:55:02 +00008053
8054 for (i = 0; i < tp->irq_cnt; i++)
8055 synchronize_irq(tp->napi[i].irq_vec);
Michael Chand18edcb2007-03-24 20:57:11 -07008056
Matt Carlson255ca312009-08-25 10:07:27 +00008057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8058 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8059 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8060 }
8061
Linus Torvalds1da177e2005-04-16 15:20:36 -07008062 /* do the reset */
8063 val = GRC_MISC_CFG_CORECLK_RESET;
8064
Joe Perches63c3a662011-04-26 08:12:10 +00008065 if (tg3_flag(tp, PCI_EXPRESS)) {
Matt Carlson88075d92010-08-02 11:25:58 +00008066 /* Force PCIe 1.0a mode */
8067 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Joe Perches63c3a662011-04-26 08:12:10 +00008068 !tg3_flag(tp, 57765_PLUS) &&
Matt Carlson88075d92010-08-02 11:25:58 +00008069 tr32(TG3_PCIE_PHY_TSTCTL) ==
8070 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8071 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8072
Linus Torvalds1da177e2005-04-16 15:20:36 -07008073 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
8074 tw32(GRC_MISC_CFG, (1 << 29));
8075 val |= (1 << 29);
8076 }
8077 }
8078
Michael Chanb5d37722006-09-27 16:06:21 -07008079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8080 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
8081 tw32(GRC_VCPU_EXT_CTRL,
8082 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
8083 }
8084
Matt Carlsonf37500d2010-08-02 11:25:59 +00008085 /* Manage gphy power for all CPMU absent PCIe devices. */
Joe Perches63c3a662011-04-26 08:12:10 +00008086 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008087 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
Matt Carlsonf37500d2010-08-02 11:25:59 +00008088
Linus Torvalds1da177e2005-04-16 15:20:36 -07008089 tw32(GRC_MISC_CFG, val);
8090
Michael Chan1ee582d2005-08-09 20:16:46 -07008091 /* restore 5701 hardware bug workaround write method */
8092 tp->write32 = write_op;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008093
8094 /* Unfortunately, we have to delay before the PCI read back.
8095 * Some 575X chips even will not respond to a PCI cfg access
8096 * when the reset command is given to the chip.
8097 *
8098 * How do these hardware designers expect things to work
8099 * properly if the PCI write is posted for a long period
8100 * of time? It is always necessary to have some method by
8101 * which a register read back can occur to push the write
8102 * out which does the reset.
8103 *
8104 * For most tg3 variants the trick below was working.
8105 * Ho hum...
8106 */
8107 udelay(120);
8108
8109 /* Flush PCI posted writes. The normal MMIO registers
8110 * are inaccessible at this time so this is the only
8111 * way to make this reliably (actually, this is no longer
8112 * the case, see above). I tried to use indirect
8113 * register read/write but this upset some 5701 variants.
8114 */
8115 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
8116
8117 udelay(120);
8118
Jon Mason708ebb3a2011-06-27 12:56:50 +00008119 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
Matt Carlsone7126992009-08-25 10:08:16 +00008120 u16 val16;
8121
Linus Torvalds1da177e2005-04-16 15:20:36 -07008122 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
8123 int i;
8124 u32 cfg_val;
8125
8126 /* Wait for link training to complete. */
8127 for (i = 0; i < 5000; i++)
8128 udelay(100);
8129
8130 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
8131 pci_write_config_dword(tp->pdev, 0xc4,
8132 cfg_val | (1 << 15));
8133 }
Matt Carlson5e7dfd02008-11-21 17:18:16 -08008134
Matt Carlsone7126992009-08-25 10:08:16 +00008135 /* Clear the "no snoop" and "relaxed ordering" bits. */
8136 pci_read_config_word(tp->pdev,
Jon Mason708ebb3a2011-06-27 12:56:50 +00008137 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
Matt Carlsone7126992009-08-25 10:08:16 +00008138 &val16);
8139 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
8140 PCI_EXP_DEVCTL_NOSNOOP_EN);
8141 /*
8142 * Older PCIe devices only support the 128 byte
8143 * MPS setting. Enforce the restriction.
Matt Carlson5e7dfd02008-11-21 17:18:16 -08008144 */
Joe Perches63c3a662011-04-26 08:12:10 +00008145 if (!tg3_flag(tp, CPMU_PRESENT))
Matt Carlsone7126992009-08-25 10:08:16 +00008146 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
Matt Carlson5e7dfd02008-11-21 17:18:16 -08008147 pci_write_config_word(tp->pdev,
Jon Mason708ebb3a2011-06-27 12:56:50 +00008148 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
Matt Carlsone7126992009-08-25 10:08:16 +00008149 val16);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08008150
Matt Carlson5e7dfd02008-11-21 17:18:16 -08008151 /* Clear error status */
8152 pci_write_config_word(tp->pdev,
Jon Mason708ebb3a2011-06-27 12:56:50 +00008153 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
Matt Carlson5e7dfd02008-11-21 17:18:16 -08008154 PCI_EXP_DEVSTA_CED |
8155 PCI_EXP_DEVSTA_NFED |
8156 PCI_EXP_DEVSTA_FED |
8157 PCI_EXP_DEVSTA_URD);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008158 }
8159
Michael Chanee6a99b2007-07-18 21:49:10 -07008160 tg3_restore_pci_state(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008161
Joe Perches63c3a662011-04-26 08:12:10 +00008162 tg3_flag_clear(tp, CHIP_RESETTING);
8163 tg3_flag_clear(tp, ERROR_PROCESSED);
Michael Chand18edcb2007-03-24 20:57:11 -07008164
Michael Chanee6a99b2007-07-18 21:49:10 -07008165 val = 0;
Joe Perches63c3a662011-04-26 08:12:10 +00008166 if (tg3_flag(tp, 5780_CLASS))
Michael Chan4cf78e42005-07-25 12:29:19 -07008167 val = tr32(MEMARB_MODE);
Michael Chanee6a99b2007-07-18 21:49:10 -07008168 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008169
8170 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
8171 tg3_stop_fw(tp);
8172 tw32(0x5000, 0x400);
8173 }
8174
8175 tw32(GRC_MODE, tp->grc_mode);
8176
8177 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
Andy Gospodarekab0049b2007-09-06 20:42:14 +01008178 val = tr32(0xc4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008179
8180 tw32(0xc4, val | (1 << 15));
8181 }
8182
8183 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
8184 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8185 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
8186 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
8187 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
8188 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8189 }
8190
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008191 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Matt Carlson9e975cc2011-07-20 10:20:50 +00008192 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
Matt Carlsond2394e6b2010-11-24 08:31:47 +00008193 val = tp->mac_mode;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008194 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
Matt Carlson9e975cc2011-07-20 10:20:50 +00008195 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
Matt Carlsond2394e6b2010-11-24 08:31:47 +00008196 val = tp->mac_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008197 } else
Matt Carlsond2394e6b2010-11-24 08:31:47 +00008198 val = 0;
8199
8200 tw32_f(MAC_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008201 udelay(40);
8202
Matt Carlson77b483f2008-08-15 14:07:24 -07008203 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
8204
Michael Chan7a6f4362006-09-27 16:03:31 -07008205 err = tg3_poll_fw(tp);
8206 if (err)
8207 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008208
Matt Carlson0a9140c2009-08-28 12:27:50 +00008209 tg3_mdio_start(tp);
8210
Joe Perches63c3a662011-04-26 08:12:10 +00008211 if (tg3_flag(tp, PCI_EXPRESS) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008212 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8213 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Joe Perches63c3a662011-04-26 08:12:10 +00008214 !tg3_flag(tp, 57765_PLUS)) {
Andy Gospodarekab0049b2007-09-06 20:42:14 +01008215 val = tr32(0x7c00);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008216
8217 tw32(0x7c00, val | (1 << 25));
8218 }
8219
Matt Carlsond78b59f2011-04-05 14:22:46 +00008220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8221 val = tr32(TG3_CPMU_CLCK_ORIDE);
8222 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8223 }
8224
Linus Torvalds1da177e2005-04-16 15:20:36 -07008225 /* Reprobe ASF enable state. */
Joe Perches63c3a662011-04-26 08:12:10 +00008226 tg3_flag_clear(tp, ENABLE_ASF);
8227 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008228 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8229 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8230 u32 nic_cfg;
8231
8232 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8233 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
Joe Perches63c3a662011-04-26 08:12:10 +00008234 tg3_flag_set(tp, ENABLE_ASF);
Matt Carlson4ba526c2008-08-15 14:10:04 -07008235 tp->last_event_jiffies = jiffies;
Joe Perches63c3a662011-04-26 08:12:10 +00008236 if (tg3_flag(tp, 5750_PLUS))
8237 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008238 }
8239 }
8240
8241 return 0;
8242}
8243
Matt Carlson65ec6982012-02-28 23:33:37 +00008244static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
8245static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
Matt Carlson92feeab2011-12-08 14:40:14 +00008246
Linus Torvalds1da177e2005-04-16 15:20:36 -07008247/* tp->lock is held. */
Michael Chan944d9802005-05-29 14:57:48 -07008248static int tg3_halt(struct tg3 *tp, int kind, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07008249{
8250 int err;
8251
8252 tg3_stop_fw(tp);
8253
Michael Chan944d9802005-05-29 14:57:48 -07008254 tg3_write_sig_pre_reset(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008255
David S. Millerb3b7d6b2005-05-05 14:40:20 -07008256 tg3_abort_hw(tp, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008257 err = tg3_chip_reset(tp);
8258
Matt Carlsondaba2a62009-04-20 06:58:52 +00008259 __tg3_set_mac_addr(tp, 0);
8260
Michael Chan944d9802005-05-29 14:57:48 -07008261 tg3_write_sig_legacy(tp, kind);
8262 tg3_write_sig_post_reset(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008263
Matt Carlson92feeab2011-12-08 14:40:14 +00008264 if (tp->hw_stats) {
8265 /* Save the stats across chip resets... */
David S. Millerb4017c52012-03-01 17:57:40 -05008266 tg3_get_nstats(tp, &tp->net_stats_prev);
Matt Carlson92feeab2011-12-08 14:40:14 +00008267 tg3_get_estats(tp, &tp->estats_prev);
8268
8269 /* And make sure the next sample is new data */
8270 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
8271 }
8272
Linus Torvalds1da177e2005-04-16 15:20:36 -07008273 if (err)
8274 return err;
8275
8276 return 0;
8277}
8278
Linus Torvalds1da177e2005-04-16 15:20:36 -07008279static int tg3_set_mac_addr(struct net_device *dev, void *p)
8280{
8281 struct tg3 *tp = netdev_priv(dev);
8282 struct sockaddr *addr = p;
Michael Chan986e0ae2007-05-05 12:10:20 -07008283 int err = 0, skip_mac_1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008284
Michael Chanf9804dd2005-09-27 12:13:10 -07008285 if (!is_valid_ether_addr(addr->sa_data))
Danny Kukawka504f9b52012-02-21 02:07:49 +00008286 return -EADDRNOTAVAIL;
Michael Chanf9804dd2005-09-27 12:13:10 -07008287
Linus Torvalds1da177e2005-04-16 15:20:36 -07008288 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8289
Michael Chane75f7c92006-03-20 21:33:26 -08008290 if (!netif_running(dev))
8291 return 0;
8292
Joe Perches63c3a662011-04-26 08:12:10 +00008293 if (tg3_flag(tp, ENABLE_ASF)) {
Michael Chan986e0ae2007-05-05 12:10:20 -07008294 u32 addr0_high, addr0_low, addr1_high, addr1_low;
Michael Chan58712ef2006-04-29 18:58:01 -07008295
Michael Chan986e0ae2007-05-05 12:10:20 -07008296 addr0_high = tr32(MAC_ADDR_0_HIGH);
8297 addr0_low = tr32(MAC_ADDR_0_LOW);
8298 addr1_high = tr32(MAC_ADDR_1_HIGH);
8299 addr1_low = tr32(MAC_ADDR_1_LOW);
8300
8301 /* Skip MAC addr 1 if ASF is using it. */
8302 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
8303 !(addr1_high == 0 && addr1_low == 0))
8304 skip_mac_1 = 1;
Michael Chan58712ef2006-04-29 18:58:01 -07008305 }
Michael Chan986e0ae2007-05-05 12:10:20 -07008306 spin_lock_bh(&tp->lock);
8307 __tg3_set_mac_addr(tp, skip_mac_1);
8308 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008309
Michael Chanb9ec6c12006-07-25 16:37:27 -07008310 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008311}
8312
8313/* tp->lock is held. */
8314static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8315 dma_addr_t mapping, u32 maxlen_flags,
8316 u32 nic_addr)
8317{
8318 tg3_write_mem(tp,
8319 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
8320 ((u64) mapping >> 32));
8321 tg3_write_mem(tp,
8322 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
8323 ((u64) mapping & 0xffffffff));
8324 tg3_write_mem(tp,
8325 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
8326 maxlen_flags);
8327
Joe Perches63c3a662011-04-26 08:12:10 +00008328 if (!tg3_flag(tp, 5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008329 tg3_write_mem(tp,
8330 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
8331 nic_addr);
8332}
8333
Michael Chana489b6d2012-09-28 07:12:39 +00008334
8335static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
David S. Miller15f98502005-05-18 22:49:26 -07008336{
Michael Chana489b6d2012-09-28 07:12:39 +00008337 int i = 0;
Matt Carlsonb6080e12009-09-01 13:12:00 +00008338
Joe Perches63c3a662011-04-26 08:12:10 +00008339 if (!tg3_flag(tp, ENABLE_TSS)) {
Matt Carlsonb6080e12009-09-01 13:12:00 +00008340 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8341 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8342 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
Matt Carlsonb6080e12009-09-01 13:12:00 +00008343 } else {
8344 tw32(HOSTCC_TXCOL_TICKS, 0);
8345 tw32(HOSTCC_TXMAX_FRAMES, 0);
8346 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
Michael Chana489b6d2012-09-28 07:12:39 +00008347
8348 for (; i < tp->txq_cnt; i++) {
8349 u32 reg;
8350
8351 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8352 tw32(reg, ec->tx_coalesce_usecs);
8353 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8354 tw32(reg, ec->tx_max_coalesced_frames);
8355 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8356 tw32(reg, ec->tx_max_coalesced_frames_irq);
8357 }
Matt Carlson19cfaec2009-12-03 08:36:20 +00008358 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00008359
Michael Chana489b6d2012-09-28 07:12:39 +00008360 for (; i < tp->irq_max - 1; i++) {
8361 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8362 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8363 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8364 }
8365}
8366
8367static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
8368{
8369 int i = 0;
8370 u32 limit = tp->rxq_cnt;
8371
Joe Perches63c3a662011-04-26 08:12:10 +00008372 if (!tg3_flag(tp, ENABLE_RSS)) {
Matt Carlson19cfaec2009-12-03 08:36:20 +00008373 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8374 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8375 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
Michael Chana489b6d2012-09-28 07:12:39 +00008376 limit--;
Matt Carlson19cfaec2009-12-03 08:36:20 +00008377 } else {
Matt Carlsonb6080e12009-09-01 13:12:00 +00008378 tw32(HOSTCC_RXCOL_TICKS, 0);
8379 tw32(HOSTCC_RXMAX_FRAMES, 0);
8380 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
David S. Miller15f98502005-05-18 22:49:26 -07008381 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00008382
Michael Chana489b6d2012-09-28 07:12:39 +00008383 for (; i < limit; i++) {
8384 u32 reg;
8385
8386 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8387 tw32(reg, ec->rx_coalesce_usecs);
8388 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8389 tw32(reg, ec->rx_max_coalesced_frames);
8390 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8391 tw32(reg, ec->rx_max_coalesced_frames_irq);
8392 }
8393
8394 for (; i < tp->irq_max - 1; i++) {
8395 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8396 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8397 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8398 }
8399}
8400
8401static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8402{
8403 tg3_coal_tx_init(tp, ec);
8404 tg3_coal_rx_init(tp, ec);
8405
Joe Perches63c3a662011-04-26 08:12:10 +00008406 if (!tg3_flag(tp, 5705_PLUS)) {
David S. Miller15f98502005-05-18 22:49:26 -07008407 u32 val = ec->stats_block_coalesce_usecs;
8408
Matt Carlsonb6080e12009-09-01 13:12:00 +00008409 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8410 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8411
David S. Miller15f98502005-05-18 22:49:26 -07008412 if (!netif_carrier_ok(tp->dev))
8413 val = 0;
8414
8415 tw32(HOSTCC_STAT_COAL_TICKS, val);
8416 }
8417}
Linus Torvalds1da177e2005-04-16 15:20:36 -07008418
8419/* tp->lock is held. */
Matt Carlson2d31eca2009-09-01 12:53:31 +00008420static void tg3_rings_reset(struct tg3 *tp)
8421{
8422 int i;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008423 u32 stblk, txrcb, rxrcb, limit;
Matt Carlson2d31eca2009-09-01 12:53:31 +00008424 struct tg3_napi *tnapi = &tp->napi[0];
8425
8426 /* Disable all transmit rings but the first. */
Joe Perches63c3a662011-04-26 08:12:10 +00008427 if (!tg3_flag(tp, 5705_PLUS))
Matt Carlson2d31eca2009-09-01 12:53:31 +00008428 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
Joe Perches63c3a662011-04-26 08:12:10 +00008429 else if (tg3_flag(tp, 5717_PLUS))
Matt Carlson3d377282010-10-14 10:37:39 +00008430 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
Matt Carlson55086ad2011-12-14 11:09:59 +00008431 else if (tg3_flag(tp, 57765_CLASS))
Matt Carlsonb703df62009-12-03 08:36:21 +00008432 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
Matt Carlson2d31eca2009-09-01 12:53:31 +00008433 else
8434 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8435
8436 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8437 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8438 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8439 BDINFO_FLAGS_DISABLED);
8440
8441
8442 /* Disable all receive return rings but the first. */
Joe Perches63c3a662011-04-26 08:12:10 +00008443 if (tg3_flag(tp, 5717_PLUS))
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008444 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
Joe Perches63c3a662011-04-26 08:12:10 +00008445 else if (!tg3_flag(tp, 5705_PLUS))
Matt Carlson2d31eca2009-09-01 12:53:31 +00008446 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
Matt Carlsonb703df62009-12-03 08:36:21 +00008447 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlson55086ad2011-12-14 11:09:59 +00008448 tg3_flag(tp, 57765_CLASS))
Matt Carlson2d31eca2009-09-01 12:53:31 +00008449 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8450 else
8451 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8452
8453 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8454 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8455 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8456 BDINFO_FLAGS_DISABLED);
8457
8458 /* Disable interrupts */
8459 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00008460 tp->napi[0].chk_msi_cnt = 0;
8461 tp->napi[0].last_rx_cons = 0;
8462 tp->napi[0].last_tx_cons = 0;
Matt Carlson2d31eca2009-09-01 12:53:31 +00008463
8464 /* Zero mailbox registers. */
Joe Perches63c3a662011-04-26 08:12:10 +00008465 if (tg3_flag(tp, SUPPORT_MSIX)) {
Matt Carlson6fd45cb2010-09-15 08:59:57 +00008466 for (i = 1; i < tp->irq_max; i++) {
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008467 tp->napi[i].tx_prod = 0;
8468 tp->napi[i].tx_cons = 0;
Joe Perches63c3a662011-04-26 08:12:10 +00008469 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlsonc2353a32010-01-20 16:58:08 +00008470 tw32_mailbox(tp->napi[i].prodmbox, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008471 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8472 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
Matt Carlson7f230732011-08-31 11:44:48 +00008473 tp->napi[i].chk_msi_cnt = 0;
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00008474 tp->napi[i].last_rx_cons = 0;
8475 tp->napi[i].last_tx_cons = 0;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008476 }
Joe Perches63c3a662011-04-26 08:12:10 +00008477 if (!tg3_flag(tp, ENABLE_TSS))
Matt Carlsonc2353a32010-01-20 16:58:08 +00008478 tw32_mailbox(tp->napi[0].prodmbox, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008479 } else {
8480 tp->napi[0].tx_prod = 0;
8481 tp->napi[0].tx_cons = 0;
8482 tw32_mailbox(tp->napi[0].prodmbox, 0);
8483 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8484 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00008485
8486 /* Make sure the NIC-based send BD rings are disabled. */
Joe Perches63c3a662011-04-26 08:12:10 +00008487 if (!tg3_flag(tp, 5705_PLUS)) {
Matt Carlson2d31eca2009-09-01 12:53:31 +00008488 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8489 for (i = 0; i < 16; i++)
8490 tw32_tx_mbox(mbox + i * 8, 0);
8491 }
8492
8493 txrcb = NIC_SRAM_SEND_RCB;
8494 rxrcb = NIC_SRAM_RCV_RET_RCB;
8495
8496 /* Clear status block in ram. */
8497 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8498
8499 /* Set status block DMA address */
8500 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8501 ((u64) tnapi->status_mapping >> 32));
8502 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8503 ((u64) tnapi->status_mapping & 0xffffffff));
8504
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008505 if (tnapi->tx_ring) {
8506 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8507 (TG3_TX_RING_SIZE <<
8508 BDINFO_FLAGS_MAXLEN_SHIFT),
8509 NIC_SRAM_TX_BUFFER_DESC);
8510 txrcb += TG3_BDINFO_SIZE;
8511 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00008512
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008513 if (tnapi->rx_rcb) {
8514 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008515 (tp->rx_ret_ring_mask + 1) <<
8516 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008517 rxrcb += TG3_BDINFO_SIZE;
8518 }
8519
8520 stblk = HOSTCC_STATBLCK_RING1;
8521
8522 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8523 u64 mapping = (u64)tnapi->status_mapping;
8524 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8525 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8526
8527 /* Clear status block in ram. */
8528 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8529
Matt Carlson19cfaec2009-12-03 08:36:20 +00008530 if (tnapi->tx_ring) {
8531 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8532 (TG3_TX_RING_SIZE <<
8533 BDINFO_FLAGS_MAXLEN_SHIFT),
8534 NIC_SRAM_TX_BUFFER_DESC);
8535 txrcb += TG3_BDINFO_SIZE;
8536 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008537
8538 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008539 ((tp->rx_ret_ring_mask + 1) <<
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008540 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8541
8542 stblk += 8;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008543 rxrcb += TG3_BDINFO_SIZE;
8544 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00008545}
8546
Matt Carlsoneb07a942011-04-20 07:57:36 +00008547static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8548{
8549 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8550
Joe Perches63c3a662011-04-26 08:12:10 +00008551 if (!tg3_flag(tp, 5750_PLUS) ||
8552 tg3_flag(tp, 5780_CLASS) ||
Matt Carlsoneb07a942011-04-20 07:57:36 +00008553 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
Matt Carlson513aa6e2011-11-21 15:01:18 +00008554 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8555 tg3_flag(tp, 57765_PLUS))
Matt Carlsoneb07a942011-04-20 07:57:36 +00008556 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8557 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8558 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8559 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8560 else
8561 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8562
8563 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8564 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8565
8566 val = min(nic_rep_thresh, host_rep_thresh);
8567 tw32(RCVBDI_STD_THRESH, val);
8568
Joe Perches63c3a662011-04-26 08:12:10 +00008569 if (tg3_flag(tp, 57765_PLUS))
Matt Carlsoneb07a942011-04-20 07:57:36 +00008570 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8571
Joe Perches63c3a662011-04-26 08:12:10 +00008572 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
Matt Carlsoneb07a942011-04-20 07:57:36 +00008573 return;
8574
Matt Carlson513aa6e2011-11-21 15:01:18 +00008575 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
Matt Carlsoneb07a942011-04-20 07:57:36 +00008576
8577 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8578
8579 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8580 tw32(RCVBDI_JUMBO_THRESH, val);
8581
Joe Perches63c3a662011-04-26 08:12:10 +00008582 if (tg3_flag(tp, 57765_PLUS))
Matt Carlsoneb07a942011-04-20 07:57:36 +00008583 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8584}
8585
Matt Carlsonccd5ba92012-02-13 10:20:08 +00008586static inline u32 calc_crc(unsigned char *buf, int len)
8587{
8588 u32 reg;
8589 u32 tmp;
8590 int j, k;
8591
8592 reg = 0xffffffff;
8593
8594 for (j = 0; j < len; j++) {
8595 reg ^= buf[j];
8596
8597 for (k = 0; k < 8; k++) {
8598 tmp = reg & 0x01;
8599
8600 reg >>= 1;
8601
8602 if (tmp)
8603 reg ^= 0xedb88320;
8604 }
8605 }
8606
8607 return ~reg;
8608}
8609
8610static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8611{
8612 /* accept or reject all multicast frames */
8613 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8614 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8615 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8616 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8617}
8618
8619static void __tg3_set_rx_mode(struct net_device *dev)
8620{
8621 struct tg3 *tp = netdev_priv(dev);
8622 u32 rx_mode;
8623
8624 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8625 RX_MODE_KEEP_VLAN_TAG);
8626
8627#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
8628 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8629 * flag clear.
8630 */
8631 if (!tg3_flag(tp, ENABLE_ASF))
8632 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8633#endif
8634
8635 if (dev->flags & IFF_PROMISC) {
8636 /* Promiscuous mode. */
8637 rx_mode |= RX_MODE_PROMISC;
8638 } else if (dev->flags & IFF_ALLMULTI) {
8639 /* Accept all multicast. */
8640 tg3_set_multi(tp, 1);
8641 } else if (netdev_mc_empty(dev)) {
8642 /* Reject all multicast. */
8643 tg3_set_multi(tp, 0);
8644 } else {
8645 /* Accept one or more multicast(s). */
8646 struct netdev_hw_addr *ha;
8647 u32 mc_filter[4] = { 0, };
8648 u32 regidx;
8649 u32 bit;
8650 u32 crc;
8651
8652 netdev_for_each_mc_addr(ha, dev) {
8653 crc = calc_crc(ha->addr, ETH_ALEN);
8654 bit = ~crc & 0x7f;
8655 regidx = (bit & 0x60) >> 5;
8656 bit &= 0x1f;
8657 mc_filter[regidx] |= (1 << bit);
8658 }
8659
8660 tw32(MAC_HASH_REG_0, mc_filter[0]);
8661 tw32(MAC_HASH_REG_1, mc_filter[1]);
8662 tw32(MAC_HASH_REG_2, mc_filter[2]);
8663 tw32(MAC_HASH_REG_3, mc_filter[3]);
8664 }
8665
8666 if (rx_mode != tp->rx_mode) {
8667 tp->rx_mode = rx_mode;
8668 tw32_f(MAC_RX_MODE, rx_mode);
8669 udelay(10);
8670 }
8671}
8672
Michael Chan91024262012-09-28 07:12:38 +00008673static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
Matt Carlson90415472011-12-16 13:33:23 +00008674{
8675 int i;
8676
8677 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
Michael Chan91024262012-09-28 07:12:38 +00008678 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
Matt Carlson90415472011-12-16 13:33:23 +00008679}
8680
8681static void tg3_rss_check_indir_tbl(struct tg3 *tp)
Matt Carlsonbcebcc42011-12-14 11:10:01 +00008682{
8683 int i;
8684
8685 if (!tg3_flag(tp, SUPPORT_MSIX))
8686 return;
8687
Matt Carlson90415472011-12-16 13:33:23 +00008688 if (tp->irq_cnt <= 2) {
Matt Carlsonbcebcc42011-12-14 11:10:01 +00008689 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
Matt Carlson90415472011-12-16 13:33:23 +00008690 return;
8691 }
8692
8693 /* Validate table against current IRQ count */
8694 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8695 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1)
8696 break;
8697 }
8698
8699 if (i != TG3_RSS_INDIR_TBL_SIZE)
Michael Chan91024262012-09-28 07:12:38 +00008700 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
Matt Carlsonbcebcc42011-12-14 11:10:01 +00008701}
8702
Matt Carlson90415472011-12-16 13:33:23 +00008703static void tg3_rss_write_indir_tbl(struct tg3 *tp)
Matt Carlsonbcebcc42011-12-14 11:10:01 +00008704{
8705 int i = 0;
8706 u32 reg = MAC_RSS_INDIR_TBL_0;
8707
8708 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8709 u32 val = tp->rss_ind_tbl[i];
8710 i++;
8711 for (; i % 8; i++) {
8712 val <<= 4;
8713 val |= tp->rss_ind_tbl[i];
8714 }
8715 tw32(reg, val);
8716 reg += 4;
8717 }
8718}
8719
Matt Carlson2d31eca2009-09-01 12:53:31 +00008720/* tp->lock is held. */
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07008721static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07008722{
8723 u32 val, rdmac_mode;
8724 int i, err, limit;
Matt Carlson8fea32b2010-09-15 08:59:58 +00008725 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008726
8727 tg3_disable_ints(tp);
8728
8729 tg3_stop_fw(tp);
8730
8731 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8732
Joe Perches63c3a662011-04-26 08:12:10 +00008733 if (tg3_flag(tp, INIT_COMPLETE))
Michael Chane6de8ad2005-05-05 14:42:41 -07008734 tg3_abort_hw(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008735
Matt Carlson699c0192010-12-06 08:28:51 +00008736 /* Enable MAC control of LPI */
8737 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8738 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8739 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8740 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8741
8742 tw32_f(TG3_CPMU_EEE_CTRL,
8743 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8744
Matt Carlsona386b902010-12-06 08:28:53 +00008745 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8746 TG3_CPMU_EEEMD_LPI_IN_TX |
8747 TG3_CPMU_EEEMD_LPI_IN_RX |
8748 TG3_CPMU_EEEMD_EEE_ENABLE;
8749
8750 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8751 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8752
Joe Perches63c3a662011-04-26 08:12:10 +00008753 if (tg3_flag(tp, ENABLE_APE))
Matt Carlsona386b902010-12-06 08:28:53 +00008754 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8755
8756 tw32_f(TG3_CPMU_EEE_MODE, val);
8757
8758 tw32_f(TG3_CPMU_EEE_DBTMR1,
8759 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8760 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8761
8762 tw32_f(TG3_CPMU_EEE_DBTMR2,
Matt Carlsond7f2ab22011-01-25 15:58:56 +00008763 TG3_CPMU_DBTMR2_APE_TX_2047US |
Matt Carlsona386b902010-12-06 08:28:53 +00008764 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
Matt Carlson699c0192010-12-06 08:28:51 +00008765 }
8766
Matt Carlson603f1172010-02-12 14:47:10 +00008767 if (reset_phy)
Michael Chand4d2c552006-03-20 17:47:20 -08008768 tg3_phy_reset(tp);
8769
Linus Torvalds1da177e2005-04-16 15:20:36 -07008770 err = tg3_chip_reset(tp);
8771 if (err)
8772 return err;
8773
8774 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8775
Matt Carlsonbcb37f62008-11-03 16:52:09 -08008776 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
Matt Carlsond30cdd22007-10-07 23:28:35 -07008777 val = tr32(TG3_CPMU_CTRL);
8778 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8779 tw32(TG3_CPMU_CTRL, val);
Matt Carlson9acb9612007-11-12 21:10:06 -08008780
8781 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8782 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8783 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8784 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8785
8786 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8787 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8788 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8789 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8790
8791 val = tr32(TG3_CPMU_HST_ACC);
8792 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8793 val |= CPMU_HST_ACC_MACCLK_6_25;
8794 tw32(TG3_CPMU_HST_ACC, val);
Matt Carlsond30cdd22007-10-07 23:28:35 -07008795 }
8796
Matt Carlson33466d92009-04-20 06:57:41 +00008797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8798 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8799 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8800 PCIE_PWR_MGMT_L1_THRESH_4MS;
8801 tw32(PCIE_PWR_MGMT_THRESH, val);
Matt Carlson521e6b92009-08-25 10:06:01 +00008802
8803 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8804 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8805
8806 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
Matt Carlson33466d92009-04-20 06:57:41 +00008807
Matt Carlsonf40386c2009-11-02 14:24:02 +00008808 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8809 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
Matt Carlson255ca312009-08-25 10:07:27 +00008810 }
8811
Joe Perches63c3a662011-04-26 08:12:10 +00008812 if (tg3_flag(tp, L1PLLPD_EN)) {
Matt Carlson614b0592010-01-20 16:58:02 +00008813 u32 grc_mode = tr32(GRC_MODE);
8814
8815 /* Access the lower 1K of PL PCIE block registers. */
8816 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8817 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8818
8819 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8820 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8821 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8822
8823 tw32(GRC_MODE, grc_mode);
8824 }
8825
Matt Carlson55086ad2011-12-14 11:09:59 +00008826 if (tg3_flag(tp, 57765_CLASS)) {
Matt Carlson5093eed2010-11-24 08:31:45 +00008827 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8828 u32 grc_mode = tr32(GRC_MODE);
Matt Carlsoncea46462010-04-12 06:58:24 +00008829
Matt Carlson5093eed2010-11-24 08:31:45 +00008830 /* Access the lower 1K of PL PCIE block registers. */
8831 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8832 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
Matt Carlsoncea46462010-04-12 06:58:24 +00008833
Matt Carlson5093eed2010-11-24 08:31:45 +00008834 val = tr32(TG3_PCIE_TLDLPL_PORT +
8835 TG3_PCIE_PL_LO_PHYCTL5);
8836 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8837 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
Matt Carlsoncea46462010-04-12 06:58:24 +00008838
Matt Carlson5093eed2010-11-24 08:31:45 +00008839 tw32(GRC_MODE, grc_mode);
8840 }
Matt Carlsona977dbe2010-04-12 06:58:26 +00008841
Matt Carlson1ff30a52011-05-19 12:12:46 +00008842 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8843 u32 grc_mode = tr32(GRC_MODE);
8844
8845 /* Access the lower 1K of DL PCIE block registers. */
8846 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8847 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8848
8849 val = tr32(TG3_PCIE_TLDLPL_PORT +
8850 TG3_PCIE_DL_LO_FTSMAX);
8851 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8852 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8853 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8854
8855 tw32(GRC_MODE, grc_mode);
8856 }
8857
Matt Carlsona977dbe2010-04-12 06:58:26 +00008858 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8859 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8860 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8861 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
Matt Carlsoncea46462010-04-12 06:58:24 +00008862 }
8863
Linus Torvalds1da177e2005-04-16 15:20:36 -07008864 /* This works around an issue with Athlon chipsets on
8865 * B3 tigon3 silicon. This bit has no effect on any
8866 * other revision. But do not set this on PCI Express
Matt Carlson795d01c2007-10-07 23:28:17 -07008867 * chips and don't even touch the clocks if the CPMU is present.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008868 */
Joe Perches63c3a662011-04-26 08:12:10 +00008869 if (!tg3_flag(tp, CPMU_PRESENT)) {
8870 if (!tg3_flag(tp, PCI_EXPRESS))
Matt Carlson795d01c2007-10-07 23:28:17 -07008871 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8872 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8873 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008874
8875 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
Joe Perches63c3a662011-04-26 08:12:10 +00008876 tg3_flag(tp, PCIX_MODE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008877 val = tr32(TG3PCI_PCISTATE);
8878 val |= PCISTATE_RETRY_SAME_DMA;
8879 tw32(TG3PCI_PCISTATE, val);
8880 }
8881
Joe Perches63c3a662011-04-26 08:12:10 +00008882 if (tg3_flag(tp, ENABLE_APE)) {
Matt Carlson0d3031d2007-10-10 18:02:43 -07008883 /* Allow reads and writes to the
8884 * APE register and memory space.
8885 */
8886 val = tr32(TG3PCI_PCISTATE);
8887 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00008888 PCISTATE_ALLOW_APE_SHMEM_WR |
8889 PCISTATE_ALLOW_APE_PSPACE_WR;
Matt Carlson0d3031d2007-10-10 18:02:43 -07008890 tw32(TG3PCI_PCISTATE, val);
8891 }
8892
Linus Torvalds1da177e2005-04-16 15:20:36 -07008893 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8894 /* Enable some hw fixes. */
8895 val = tr32(TG3PCI_MSI_DATA);
8896 val |= (1 << 26) | (1 << 28) | (1 << 29);
8897 tw32(TG3PCI_MSI_DATA, val);
8898 }
8899
8900 /* Descriptor ring init may make accesses to the
8901 * NIC SRAM area to setup the TX descriptors, so we
8902 * can only do this after the hardware has been
8903 * successfully reset.
8904 */
Michael Chan32d8c572006-07-25 16:38:29 -07008905 err = tg3_init_rings(tp);
8906 if (err)
8907 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008908
Joe Perches63c3a662011-04-26 08:12:10 +00008909 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlsoncbf9ca62009-11-13 13:03:40 +00008910 val = tr32(TG3PCI_DMA_RW_CTRL) &
8911 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
Matt Carlson1a319022010-04-12 06:58:25 +00008912 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8913 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
Matt Carlson55086ad2011-12-14 11:09:59 +00008914 if (!tg3_flag(tp, 57765_CLASS) &&
Matt Carlson0aebff42011-04-25 12:42:45 +00008915 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8916 val |= DMA_RWCTRL_TAGGED_STAT_WA;
Matt Carlsoncbf9ca62009-11-13 13:03:40 +00008917 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8918 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8919 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
Matt Carlsond30cdd22007-10-07 23:28:35 -07008920 /* This value is determined during the probe time DMA
8921 * engine test, tg3_test_dma.
8922 */
8923 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8924 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008925
8926 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8927 GRC_MODE_4X_NIC_SEND_RINGS |
8928 GRC_MODE_NO_TX_PHDR_CSUM |
8929 GRC_MODE_NO_RX_PHDR_CSUM);
8930 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
Michael Chand2d746f2006-04-06 21:45:39 -07008931
8932 /* Pseudo-header checksum is done by hardware logic and not
8933 * the offload processers, so make the chip do the pseudo-
8934 * header checksums on receive. For transmit it is more
8935 * convenient to do the pseudo-header checksum in software
8936 * as Linux does that on transmit for us in all cases.
8937 */
8938 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008939
8940 tw32(GRC_MODE,
8941 tp->grc_mode |
8942 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8943
8944 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8945 val = tr32(GRC_MISC_CFG);
8946 val &= ~0xff;
8947 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8948 tw32(GRC_MISC_CFG, val);
8949
8950 /* Initialize MBUF/DESC pool. */
Joe Perches63c3a662011-04-26 08:12:10 +00008951 if (tg3_flag(tp, 5750_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008952 /* Do nothing. */
8953 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8954 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8956 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8957 else
8958 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8959 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8960 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
Joe Perches63c3a662011-04-26 08:12:10 +00008961 } else if (tg3_flag(tp, TSO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008962 int fw_len;
8963
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08008964 fw_len = tp->fw_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008965 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8966 tw32(BUFMGR_MB_POOL_ADDR,
8967 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8968 tw32(BUFMGR_MB_POOL_SIZE,
8969 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8970 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008971
Michael Chan0f893dc2005-07-25 12:30:38 -07008972 if (tp->dev->mtu <= ETH_DATA_LEN) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008973 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8974 tp->bufmgr_config.mbuf_read_dma_low_water);
8975 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8976 tp->bufmgr_config.mbuf_mac_rx_low_water);
8977 tw32(BUFMGR_MB_HIGH_WATER,
8978 tp->bufmgr_config.mbuf_high_water);
8979 } else {
8980 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8981 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8982 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8983 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8984 tw32(BUFMGR_MB_HIGH_WATER,
8985 tp->bufmgr_config.mbuf_high_water_jumbo);
8986 }
8987 tw32(BUFMGR_DMA_LOW_WATER,
8988 tp->bufmgr_config.dma_low_water);
8989 tw32(BUFMGR_DMA_HIGH_WATER,
8990 tp->bufmgr_config.dma_high_water);
8991
Matt Carlsond309a462010-09-30 10:34:31 +00008992 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8994 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
Matt Carlson4d958472011-04-20 07:57:35 +00008995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8996 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8997 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8998 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
Matt Carlsond309a462010-09-30 10:34:31 +00008999 tw32(BUFMGR_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009000 for (i = 0; i < 2000; i++) {
9001 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9002 break;
9003 udelay(10);
9004 }
9005 if (i >= 2000) {
Joe Perches05dbe002010-02-17 19:44:19 +00009006 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009007 return -ENODEV;
9008 }
9009
Matt Carlsoneb07a942011-04-20 07:57:36 +00009010 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
9011 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
Michael Chanb5d37722006-09-27 16:06:21 -07009012
Matt Carlsoneb07a942011-04-20 07:57:36 +00009013 tg3_setup_rxbd_thresholds(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009014
9015 /* Initialize TG3_BDINFO's at:
9016 * RCVDBDI_STD_BD: standard eth size rx ring
9017 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9018 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9019 *
9020 * like so:
9021 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9022 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9023 * ring attribute flags
9024 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9025 *
9026 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9027 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9028 *
9029 * The size of each ring is fixed in the firmware, but the location is
9030 * configurable.
9031 */
9032 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
Matt Carlson21f581a2009-08-28 14:00:25 +00009033 ((u64) tpr->rx_std_mapping >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07009034 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
Matt Carlson21f581a2009-08-28 14:00:25 +00009035 ((u64) tpr->rx_std_mapping & 0xffffffff));
Joe Perches63c3a662011-04-26 08:12:10 +00009036 if (!tg3_flag(tp, 5717_PLUS))
Matt Carlson87668d32009-11-13 13:03:34 +00009037 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
9038 NIC_SRAM_RX_BUFFER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009039
Matt Carlsonfdb72b32009-08-28 13:57:12 +00009040 /* Disable the mini ring */
Joe Perches63c3a662011-04-26 08:12:10 +00009041 if (!tg3_flag(tp, 5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009042 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
9043 BDINFO_FLAGS_DISABLED);
9044
Matt Carlsonfdb72b32009-08-28 13:57:12 +00009045 /* Program the jumbo buffer descriptor ring control
9046 * blocks on those devices that have them.
9047 */
Matt Carlsona0512942011-07-27 14:20:54 +00009048 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
Joe Perches63c3a662011-04-26 08:12:10 +00009049 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009050
Joe Perches63c3a662011-04-26 08:12:10 +00009051 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009052 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
Matt Carlson21f581a2009-08-28 14:00:25 +00009053 ((u64) tpr->rx_jmb_mapping >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07009054 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
Matt Carlson21f581a2009-08-28 14:00:25 +00009055 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
Matt Carlsonde9f5232011-04-05 14:22:43 +00009056 val = TG3_RX_JMB_RING_SIZE(tp) <<
9057 BDINFO_FLAGS_MAXLEN_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009058 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
Matt Carlsonde9f5232011-04-05 14:22:43 +00009059 val | BDINFO_FLAGS_USE_EXT_RECV);
Joe Perches63c3a662011-04-26 08:12:10 +00009060 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
Matt Carlson55086ad2011-12-14 11:09:59 +00009061 tg3_flag(tp, 57765_CLASS))
Matt Carlson87668d32009-11-13 13:03:34 +00009062 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
9063 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009064 } else {
9065 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
9066 BDINFO_FLAGS_DISABLED);
9067 }
9068
Joe Perches63c3a662011-04-26 08:12:10 +00009069 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlsonfa6b2aa2011-11-21 15:01:19 +00009070 val = TG3_RX_STD_RING_SIZE(tp);
Matt Carlson7cb32cf2010-09-30 10:34:36 +00009071 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
9072 val |= (TG3_RX_STD_DMA_SZ << 2);
9073 } else
Matt Carlson04380d42010-04-12 06:58:29 +00009074 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
Matt Carlsonfdb72b32009-08-28 13:57:12 +00009075 } else
Matt Carlsonde9f5232011-04-05 14:22:43 +00009076 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
Matt Carlsonfdb72b32009-08-28 13:57:12 +00009077
9078 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009079
Matt Carlson411da642009-11-13 13:03:46 +00009080 tpr->rx_std_prod_idx = tp->rx_pending;
Matt Carlson66711e62009-11-13 13:03:49 +00009081 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009082
Joe Perches63c3a662011-04-26 08:12:10 +00009083 tpr->rx_jmb_prod_idx =
9084 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
Matt Carlson66711e62009-11-13 13:03:49 +00009085 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009086
Matt Carlson2d31eca2009-09-01 12:53:31 +00009087 tg3_rings_reset(tp);
9088
Linus Torvalds1da177e2005-04-16 15:20:36 -07009089 /* Initialize MAC address and backoff seed. */
Michael Chan986e0ae2007-05-05 12:10:20 -07009090 __tg3_set_mac_addr(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009091
9092 /* MTU + ethernet header + FCS + optional VLAN tag */
Matt Carlsonf7b493e2009-02-25 14:21:52 +00009093 tw32(MAC_RX_MTU_SIZE,
9094 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009095
9096 /* The slot time is changed by tg3_setup_phy if we
9097 * run at gigabit with half duplex.
9098 */
Matt Carlsonf2096f92011-04-05 14:22:48 +00009099 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
9100 (6 << TX_LENGTHS_IPG_SHIFT) |
9101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
9102
9103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
9104 val |= tr32(MAC_TX_LENGTHS) &
9105 (TX_LENGTHS_JMB_FRM_LEN_MSK |
9106 TX_LENGTHS_CNT_DWN_VAL_MSK);
9107
9108 tw32(MAC_TX_LENGTHS, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009109
9110 /* Receive rules. */
9111 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
9112 tw32(RCVLPC_CONFIG, 0x0181);
9113
9114 /* Calculate RDMAC_MODE setting early, we need it to determine
9115 * the RCVLPC_STATE_ENABLE mask.
9116 */
9117 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
9118 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
9119 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
9120 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
9121 RDMAC_MODE_LNGREAD_ENAB);
Michael Chan85e94ce2005-04-21 17:05:28 -07009122
Matt Carlsondeabaac2010-11-24 08:31:50 +00009123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
Matt Carlson0339e4e2010-02-12 14:47:09 +00009124 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
9125
Matt Carlson57e69832008-05-25 23:48:31 -07009126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson321d32a2008-11-21 17:22:19 -08009127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlsond30cdd22007-10-07 23:28:35 -07009129 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
9130 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
9131 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
9132
Matt Carlsonc5908932011-03-09 16:58:25 +00009133 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9134 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
Joe Perches63c3a662011-04-26 08:12:10 +00009135 if (tg3_flag(tp, TSO_CAPABLE) &&
Matt Carlsonc13e3712007-05-05 11:50:04 -07009136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009137 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
9138 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
Joe Perches63c3a662011-04-26 08:12:10 +00009139 !tg3_flag(tp, IS_5788)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009140 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9141 }
9142 }
9143
Joe Perches63c3a662011-04-26 08:12:10 +00009144 if (tg3_flag(tp, PCI_EXPRESS))
Michael Chan85e94ce2005-04-21 17:05:28 -07009145 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9146
Joe Perches63c3a662011-04-26 08:12:10 +00009147 if (tg3_flag(tp, HW_TSO_1) ||
9148 tg3_flag(tp, HW_TSO_2) ||
9149 tg3_flag(tp, HW_TSO_3))
Matt Carlson027455a2008-12-21 20:19:30 -08009150 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
9151
Matt Carlson108a6c12011-05-19 12:12:47 +00009152 if (tg3_flag(tp, 57765_PLUS) ||
Matt Carlsone849cdc2009-11-13 13:03:38 +00009153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlson027455a2008-12-21 20:19:30 -08009154 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9155 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009156
Matt Carlsonf2096f92011-04-05 14:22:48 +00009157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
9158 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
9159
Matt Carlson41a8a7e2010-09-15 08:59:53 +00009160 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9162 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9163 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Joe Perches63c3a662011-04-26 08:12:10 +00009164 tg3_flag(tp, 57765_PLUS)) {
Matt Carlson41a8a7e2010-09-15 08:59:53 +00009165 val = tr32(TG3_RDMA_RSRVCTRL_REG);
Michael Chan10ce95d2012-07-29 19:15:42 +00009166 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
Matt Carlsonb4495ed2011-01-25 15:58:47 +00009167 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
9168 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
9169 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
9170 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
9171 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
9172 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
Matt Carlsonb75cc0e2010-11-24 08:31:46 +00009173 }
Matt Carlson41a8a7e2010-09-15 08:59:53 +00009174 tw32(TG3_RDMA_RSRVCTRL_REG,
9175 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
9176 }
9177
Matt Carlsond78b59f2011-04-05 14:22:46 +00009178 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9179 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Matt Carlsond309a462010-09-30 10:34:31 +00009180 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9181 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
9182 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
9183 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
9184 }
9185
Linus Torvalds1da177e2005-04-16 15:20:36 -07009186 /* Receive/send statistics. */
Joe Perches63c3a662011-04-26 08:12:10 +00009187 if (tg3_flag(tp, 5750_PLUS)) {
Michael Chan16613942006-06-29 20:15:13 -07009188 val = tr32(RCVLPC_STATS_ENABLE);
9189 val &= ~RCVLPC_STATSENAB_DACK_FIX;
9190 tw32(RCVLPC_STATS_ENABLE, val);
9191 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
Joe Perches63c3a662011-04-26 08:12:10 +00009192 tg3_flag(tp, TSO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009193 val = tr32(RCVLPC_STATS_ENABLE);
9194 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
9195 tw32(RCVLPC_STATS_ENABLE, val);
9196 } else {
9197 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
9198 }
9199 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
9200 tw32(SNDDATAI_STATSENAB, 0xffffff);
9201 tw32(SNDDATAI_STATSCTRL,
9202 (SNDDATAI_SCTRL_ENABLE |
9203 SNDDATAI_SCTRL_FASTUPD));
9204
9205 /* Setup host coalescing engine. */
9206 tw32(HOSTCC_MODE, 0);
9207 for (i = 0; i < 2000; i++) {
9208 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
9209 break;
9210 udelay(10);
9211 }
9212
Michael Chand244c892005-07-05 14:42:33 -07009213 __tg3_set_coalesce(tp, &tp->coal);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009214
Joe Perches63c3a662011-04-26 08:12:10 +00009215 if (!tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009216 /* Status/statistics block address. See tg3_timer,
9217 * the tg3_periodic_fetch_stats call there, and
9218 * tg3_get_stats to see how this works for 5705/5750 chips.
9219 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07009220 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9221 ((u64) tp->stats_mapping >> 32));
9222 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9223 ((u64) tp->stats_mapping & 0xffffffff));
9224 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
Matt Carlson2d31eca2009-09-01 12:53:31 +00009225
Linus Torvalds1da177e2005-04-16 15:20:36 -07009226 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
Matt Carlson2d31eca2009-09-01 12:53:31 +00009227
9228 /* Clear statistics and status block memory areas */
9229 for (i = NIC_SRAM_STATS_BLK;
9230 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
9231 i += sizeof(u32)) {
9232 tg3_write_mem(tp, i, 0);
9233 udelay(40);
9234 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009235 }
9236
9237 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
9238
9239 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
9240 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
Joe Perches63c3a662011-04-26 08:12:10 +00009241 if (!tg3_flag(tp, 5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009242 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
9243
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009244 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9245 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chanc94e3942005-09-27 12:12:42 -07009246 /* reset to prevent losing 1st rx packet intermittently */
9247 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9248 udelay(10);
9249 }
9250
Matt Carlson3bda1252008-08-15 14:08:22 -07009251 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
Matt Carlson9e975cc2011-07-20 10:20:50 +00009252 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
9253 MAC_MODE_FHDE_ENABLE;
9254 if (tg3_flag(tp, ENABLE_APE))
9255 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
Joe Perches63c3a662011-04-26 08:12:10 +00009256 if (!tg3_flag(tp, 5705_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009257 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07009258 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
9259 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009260 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
9261 udelay(40);
9262
Michael Chan314fba32005-04-21 17:07:04 -07009263 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
Joe Perches63c3a662011-04-26 08:12:10 +00009264 * If TG3_FLAG_IS_NIC is zero, we should read the
Michael Chan314fba32005-04-21 17:07:04 -07009265 * register to preserve the GPIO settings for LOMs. The GPIOs,
9266 * whether used as inputs or outputs, are set by boot code after
9267 * reset.
9268 */
Joe Perches63c3a662011-04-26 08:12:10 +00009269 if (!tg3_flag(tp, IS_NIC)) {
Michael Chan314fba32005-04-21 17:07:04 -07009270 u32 gpio_mask;
9271
Michael Chan9d26e212006-12-07 00:21:14 -08009272 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
9273 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
9274 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
Michael Chan3e7d83b2005-04-21 17:10:36 -07009275
9276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9277 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
9278 GRC_LCLCTRL_GPIO_OUTPUT3;
9279
Michael Chanaf36e6b2006-03-23 01:28:06 -08009280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9281 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
9282
Gary Zambranoaaf84462007-05-05 11:51:45 -07009283 tp->grc_local_ctrl &= ~gpio_mask;
Michael Chan314fba32005-04-21 17:07:04 -07009284 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
9285
9286 /* GPIO1 must be driven high for eeprom write protect */
Joe Perches63c3a662011-04-26 08:12:10 +00009287 if (tg3_flag(tp, EEPROM_WRITE_PROT))
Michael Chan9d26e212006-12-07 00:21:14 -08009288 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9289 GRC_LCLCTRL_GPIO_OUTPUT1);
Michael Chan314fba32005-04-21 17:07:04 -07009290 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009291 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9292 udelay(100);
9293
Matt Carlsonc3b50032012-01-17 15:27:23 +00009294 if (tg3_flag(tp, USING_MSIX)) {
Matt Carlsonbaf8a942009-09-01 13:13:00 +00009295 val = tr32(MSGINT_MODE);
Matt Carlsonc3b50032012-01-17 15:27:23 +00009296 val |= MSGINT_MODE_ENABLE;
9297 if (tp->irq_cnt > 1)
9298 val |= MSGINT_MODE_MULTIVEC_EN;
Matt Carlson5b39de92011-08-31 11:44:50 +00009299 if (!tg3_flag(tp, 1SHOT_MSI))
9300 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
Matt Carlsonbaf8a942009-09-01 13:13:00 +00009301 tw32(MSGINT_MODE, val);
9302 }
9303
Joe Perches63c3a662011-04-26 08:12:10 +00009304 if (!tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009305 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
9306 udelay(40);
9307 }
9308
9309 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
9310 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
9311 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
9312 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
9313 WDMAC_MODE_LNGREAD_ENAB);
9314
Matt Carlsonc5908932011-03-09 16:58:25 +00009315 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9316 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
Joe Perches63c3a662011-04-26 08:12:10 +00009317 if (tg3_flag(tp, TSO_CAPABLE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07009318 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
9319 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
9320 /* nothing */
9321 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
Joe Perches63c3a662011-04-26 08:12:10 +00009322 !tg3_flag(tp, IS_5788)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009323 val |= WDMAC_MODE_RX_ACCEL;
9324 }
9325 }
9326
Michael Chand9ab5ad12006-03-20 22:27:35 -08009327 /* Enable host coalescing bug fix */
Joe Perches63c3a662011-04-26 08:12:10 +00009328 if (tg3_flag(tp, 5755_PLUS))
Matt Carlsonf51f3562008-05-25 23:45:08 -07009329 val |= WDMAC_MODE_STATUS_TAG_FIX;
Michael Chand9ab5ad12006-03-20 22:27:35 -08009330
Matt Carlson788a0352009-11-02 14:26:03 +00009331 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9332 val |= WDMAC_MODE_BURST_ALL_DATA;
9333
Linus Torvalds1da177e2005-04-16 15:20:36 -07009334 tw32_f(WDMAC_MODE, val);
9335 udelay(40);
9336
Joe Perches63c3a662011-04-26 08:12:10 +00009337 if (tg3_flag(tp, PCIX_MODE)) {
Matt Carlson9974a352007-10-07 23:27:28 -07009338 u16 pcix_cmd;
9339
9340 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9341 &pcix_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
Matt Carlson9974a352007-10-07 23:27:28 -07009343 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
9344 pcix_cmd |= PCI_X_CMD_READ_2K;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009345 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
Matt Carlson9974a352007-10-07 23:27:28 -07009346 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
9347 pcix_cmd |= PCI_X_CMD_READ_2K;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009348 }
Matt Carlson9974a352007-10-07 23:27:28 -07009349 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9350 pcix_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009351 }
9352
9353 tw32_f(RDMAC_MODE, rdmac_mode);
9354 udelay(40);
9355
Michael Chan091f0ea2012-07-29 19:15:43 +00009356 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9357 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
9358 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
9359 break;
9360 }
9361 if (i < TG3_NUM_RDMA_CHANNELS) {
9362 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9363 val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
9364 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9365 tg3_flag_set(tp, 5719_RDMA_BUG);
9366 }
9367 }
9368
Linus Torvalds1da177e2005-04-16 15:20:36 -07009369 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
Joe Perches63c3a662011-04-26 08:12:10 +00009370 if (!tg3_flag(tp, 5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009371 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
Matt Carlson9936bcf2007-10-10 18:03:07 -07009372
9373 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9374 tw32(SNDDATAC_MODE,
9375 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
9376 else
9377 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
9378
Linus Torvalds1da177e2005-04-16 15:20:36 -07009379 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
9380 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
Matt Carlson7cb32cf2010-09-30 10:34:36 +00009381 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
Joe Perches63c3a662011-04-26 08:12:10 +00009382 if (tg3_flag(tp, LRG_PROD_RING_CAP))
Matt Carlson7cb32cf2010-09-30 10:34:36 +00009383 val |= RCVDBDI_MODE_LRG_RING_SZ;
9384 tw32(RCVDBDI_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009385 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
Joe Perches63c3a662011-04-26 08:12:10 +00009386 if (tg3_flag(tp, HW_TSO_1) ||
9387 tg3_flag(tp, HW_TSO_2) ||
9388 tg3_flag(tp, HW_TSO_3))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009389 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
Matt Carlsonbaf8a942009-09-01 13:13:00 +00009390 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00009391 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlsonbaf8a942009-09-01 13:13:00 +00009392 val |= SNDBDI_MODE_MULTI_TXQ_EN;
9393 tw32(SNDBDI_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009394 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
9395
9396 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9397 err = tg3_load_5701_a0_firmware_fix(tp);
9398 if (err)
9399 return err;
9400 }
9401
Joe Perches63c3a662011-04-26 08:12:10 +00009402 if (tg3_flag(tp, TSO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009403 err = tg3_load_tso_firmware(tp);
9404 if (err)
9405 return err;
9406 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009407
9408 tp->tx_mode = TX_MODE_ENABLE;
Matt Carlsonf2096f92011-04-05 14:22:48 +00009409
Joe Perches63c3a662011-04-26 08:12:10 +00009410 if (tg3_flag(tp, 5755_PLUS) ||
Matt Carlsonb1d05212010-06-05 17:24:31 +00009411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9412 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
Matt Carlsonf2096f92011-04-05 14:22:48 +00009413
9414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9415 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
9416 tp->tx_mode &= ~val;
9417 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
9418 }
9419
Linus Torvalds1da177e2005-04-16 15:20:36 -07009420 tw32_f(MAC_TX_MODE, tp->tx_mode);
9421 udelay(100);
9422
Joe Perches63c3a662011-04-26 08:12:10 +00009423 if (tg3_flag(tp, ENABLE_RSS)) {
Matt Carlsonbcebcc42011-12-14 11:10:01 +00009424 tg3_rss_write_indir_tbl(tp);
Matt Carlsonbaf8a942009-09-01 13:13:00 +00009425
9426 /* Setup the "secret" hash key. */
9427 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
9428 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
9429 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
9430 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
9431 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
9432 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
9433 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
9434 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
9435 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
9436 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
9437 }
9438
Linus Torvalds1da177e2005-04-16 15:20:36 -07009439 tp->rx_mode = RX_MODE_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00009440 if (tg3_flag(tp, 5755_PLUS))
Michael Chanaf36e6b2006-03-23 01:28:06 -08009441 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
9442
Joe Perches63c3a662011-04-26 08:12:10 +00009443 if (tg3_flag(tp, ENABLE_RSS))
Matt Carlsonbaf8a942009-09-01 13:13:00 +00009444 tp->rx_mode |= RX_MODE_RSS_ENABLE |
9445 RX_MODE_RSS_ITBL_HASH_BITS_7 |
9446 RX_MODE_RSS_IPV6_HASH_EN |
9447 RX_MODE_RSS_TCP_IPV6_HASH_EN |
9448 RX_MODE_RSS_IPV4_HASH_EN |
9449 RX_MODE_RSS_TCP_IPV4_HASH_EN;
9450
Linus Torvalds1da177e2005-04-16 15:20:36 -07009451 tw32_f(MAC_RX_MODE, tp->rx_mode);
9452 udelay(10);
9453
Linus Torvalds1da177e2005-04-16 15:20:36 -07009454 tw32(MAC_LED_CTRL, tp->led_ctrl);
9455
9456 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009457 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009458 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9459 udelay(10);
9460 }
9461 tw32_f(MAC_RX_MODE, tp->rx_mode);
9462 udelay(10);
9463
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009464 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009465 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009466 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009467 /* Set drive transmission level to 1.2V */
9468 /* only if the signal pre-emphasis bit is not set */
9469 val = tr32(MAC_SERDES_CFG);
9470 val &= 0xfffff000;
9471 val |= 0x880;
9472 tw32(MAC_SERDES_CFG, val);
9473 }
9474 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9475 tw32(MAC_SERDES_CFG, 0x616000);
9476 }
9477
9478 /* Prevent chip from dropping frames when flow control
9479 * is enabled.
9480 */
Matt Carlson55086ad2011-12-14 11:09:59 +00009481 if (tg3_flag(tp, 57765_CLASS))
Matt Carlson666bc832010-01-20 16:58:03 +00009482 val = 1;
9483 else
9484 val = 2;
9485 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009486
9487 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009488 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009489 /* Use hardware link auto-negotiation */
Joe Perches63c3a662011-04-26 08:12:10 +00009490 tg3_flag_set(tp, HW_AUTONEG);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009491 }
9492
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009493 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
Matt Carlson6ff6f812011-05-19 12:12:54 +00009494 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
Michael Chand4d2c552006-03-20 17:47:20 -08009495 u32 tmp;
9496
9497 tmp = tr32(SERDES_RX_CTRL);
9498 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9499 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9500 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9501 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9502 }
9503
Joe Perches63c3a662011-04-26 08:12:10 +00009504 if (!tg3_flag(tp, USE_PHYLIB)) {
Matt Carlsonc6700ce2012-02-13 15:20:15 +00009505 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Matt Carlson80096062010-08-02 11:26:06 +00009506 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009507
Matt Carlsondd477002008-05-25 23:45:58 -07009508 err = tg3_setup_phy(tp, 0);
9509 if (err)
9510 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009511
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009512 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9513 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
Matt Carlsondd477002008-05-25 23:45:58 -07009514 u32 tmp;
9515
9516 /* Clear CRC stats. */
9517 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9518 tg3_writephy(tp, MII_TG3_TEST1,
9519 tmp | MII_TG3_TEST1_CRC_EN);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00009520 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
Matt Carlsondd477002008-05-25 23:45:58 -07009521 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009522 }
9523 }
9524
9525 __tg3_set_rx_mode(tp->dev);
9526
9527 /* Initialize receive rules. */
9528 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9529 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9530 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9531 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9532
Joe Perches63c3a662011-04-26 08:12:10 +00009533 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009534 limit = 8;
9535 else
9536 limit = 16;
Joe Perches63c3a662011-04-26 08:12:10 +00009537 if (tg3_flag(tp, ENABLE_ASF))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009538 limit -= 4;
9539 switch (limit) {
9540 case 16:
9541 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9542 case 15:
9543 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9544 case 14:
9545 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9546 case 13:
9547 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9548 case 12:
9549 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9550 case 11:
9551 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9552 case 10:
9553 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9554 case 9:
9555 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9556 case 8:
9557 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9558 case 7:
9559 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9560 case 6:
9561 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9562 case 5:
9563 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9564 case 4:
9565 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9566 case 3:
9567 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9568 case 2:
9569 case 1:
9570
9571 default:
9572 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07009573 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009574
Joe Perches63c3a662011-04-26 08:12:10 +00009575 if (tg3_flag(tp, ENABLE_APE))
Matt Carlson9ce768e2007-10-11 19:49:11 -07009576 /* Write our heartbeat update interval to APE. */
9577 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9578 APE_HOST_HEARTBEAT_INT_DISABLE);
Matt Carlson0d3031d2007-10-10 18:02:43 -07009579
Linus Torvalds1da177e2005-04-16 15:20:36 -07009580 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9581
Linus Torvalds1da177e2005-04-16 15:20:36 -07009582 return 0;
9583}
9584
9585/* Called at device open time to get the chip ready for
9586 * packet processing. Invoked with tp->lock held.
9587 */
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07009588static int tg3_init_hw(struct tg3 *tp, int reset_phy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009589{
Linus Torvalds1da177e2005-04-16 15:20:36 -07009590 tg3_switch_clocks(tp);
9591
9592 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9593
Matt Carlson2f751b62008-08-04 23:17:34 -07009594 return tg3_reset_hw(tp, reset_phy);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009595}
9596
Michael Chanaed93e02012-07-16 16:24:02 +00009597#if IS_ENABLED(CONFIG_HWMON)
9598static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
9599{
9600 int i;
9601
9602 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
9603 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
9604
9605 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
9606 off += len;
9607
9608 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
9609 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
9610 memset(ocir, 0, TG3_OCIR_LEN);
9611 }
9612}
9613
9614/* sysfs attributes for hwmon */
9615static ssize_t tg3_show_temp(struct device *dev,
9616 struct device_attribute *devattr, char *buf)
9617{
9618 struct pci_dev *pdev = to_pci_dev(dev);
9619 struct net_device *netdev = pci_get_drvdata(pdev);
9620 struct tg3 *tp = netdev_priv(netdev);
9621 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
9622 u32 temperature;
9623
9624 spin_lock_bh(&tp->lock);
9625 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
9626 sizeof(temperature));
9627 spin_unlock_bh(&tp->lock);
9628 return sprintf(buf, "%u\n", temperature);
9629}
9630
9631
9632static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
9633 TG3_TEMP_SENSOR_OFFSET);
9634static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
9635 TG3_TEMP_CAUTION_OFFSET);
9636static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
9637 TG3_TEMP_MAX_OFFSET);
9638
9639static struct attribute *tg3_attributes[] = {
9640 &sensor_dev_attr_temp1_input.dev_attr.attr,
9641 &sensor_dev_attr_temp1_crit.dev_attr.attr,
9642 &sensor_dev_attr_temp1_max.dev_attr.attr,
9643 NULL
9644};
9645
9646static const struct attribute_group tg3_group = {
9647 .attrs = tg3_attributes,
9648};
9649
9650#endif
9651
9652static void tg3_hwmon_close(struct tg3 *tp)
9653{
9654#if IS_ENABLED(CONFIG_HWMON)
9655 if (tp->hwmon_dev) {
9656 hwmon_device_unregister(tp->hwmon_dev);
9657 tp->hwmon_dev = NULL;
9658 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
9659 }
9660#endif
9661}
9662
9663static void tg3_hwmon_open(struct tg3 *tp)
9664{
9665#if IS_ENABLED(CONFIG_HWMON)
9666 int i, err;
9667 u32 size = 0;
9668 struct pci_dev *pdev = tp->pdev;
9669 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
9670
9671 tg3_sd_scan_scratchpad(tp, ocirs);
9672
9673 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
9674 if (!ocirs[i].src_data_length)
9675 continue;
9676
9677 size += ocirs[i].src_hdr_length;
9678 size += ocirs[i].src_data_length;
9679 }
9680
9681 if (!size)
9682 return;
9683
9684 /* Register hwmon sysfs hooks */
9685 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
9686 if (err) {
9687 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
9688 return;
9689 }
9690
9691 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
9692 if (IS_ERR(tp->hwmon_dev)) {
9693 tp->hwmon_dev = NULL;
9694 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
9695 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
9696 }
9697#endif
9698}
9699
9700
Linus Torvalds1da177e2005-04-16 15:20:36 -07009701#define TG3_STAT_ADD32(PSTAT, REG) \
9702do { u32 __val = tr32(REG); \
9703 (PSTAT)->low += __val; \
9704 if ((PSTAT)->low < __val) \
9705 (PSTAT)->high += 1; \
9706} while (0)
9707
9708static void tg3_periodic_fetch_stats(struct tg3 *tp)
9709{
9710 struct tg3_hw_stats *sp = tp->hw_stats;
9711
9712 if (!netif_carrier_ok(tp->dev))
9713 return;
9714
9715 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9716 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9717 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9718 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9719 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9720 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9721 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9722 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9723 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9724 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9725 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9726 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9727 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
Michael Chan091f0ea2012-07-29 19:15:43 +00009728 if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
9729 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
9730 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
9731 u32 val;
9732
9733 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9734 val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
9735 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9736 tg3_flag_clear(tp, 5719_RDMA_BUG);
9737 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009738
9739 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9740 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9741 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9742 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9743 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9744 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9745 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9746 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9747 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9748 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9749 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9750 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9751 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9752 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
Michael Chan463d3052006-05-22 16:36:27 -07009753
9754 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
Matt Carlson310050f2011-05-19 12:12:55 +00009755 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9756 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9757 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
Matt Carlson4d958472011-04-20 07:57:35 +00009758 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9759 } else {
9760 u32 val = tr32(HOSTCC_FLOW_ATTN);
9761 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9762 if (val) {
9763 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9764 sp->rx_discards.low += val;
9765 if (sp->rx_discards.low < val)
9766 sp->rx_discards.high += 1;
9767 }
9768 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9769 }
Michael Chan463d3052006-05-22 16:36:27 -07009770 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009771}
9772
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00009773static void tg3_chk_missed_msi(struct tg3 *tp)
9774{
9775 u32 i;
9776
9777 for (i = 0; i < tp->irq_cnt; i++) {
9778 struct tg3_napi *tnapi = &tp->napi[i];
9779
9780 if (tg3_has_work(tnapi)) {
9781 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9782 tnapi->last_tx_cons == tnapi->tx_cons) {
9783 if (tnapi->chk_msi_cnt < 1) {
9784 tnapi->chk_msi_cnt++;
9785 return;
9786 }
Matt Carlson7f230732011-08-31 11:44:48 +00009787 tg3_msi(0, tnapi);
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00009788 }
9789 }
9790 tnapi->chk_msi_cnt = 0;
9791 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9792 tnapi->last_tx_cons = tnapi->tx_cons;
9793 }
9794}
9795
Linus Torvalds1da177e2005-04-16 15:20:36 -07009796static void tg3_timer(unsigned long __opaque)
9797{
9798 struct tg3 *tp = (struct tg3 *) __opaque;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009799
Matt Carlson5b190622011-11-04 09:15:04 +00009800 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
Michael Chanf475f162006-03-27 23:20:14 -08009801 goto restart_timer;
9802
David S. Millerf47c11e2005-06-24 20:18:35 -07009803 spin_lock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009804
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00009805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
Matt Carlson55086ad2011-12-14 11:09:59 +00009806 tg3_flag(tp, 57765_CLASS))
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00009807 tg3_chk_missed_msi(tp);
9808
Joe Perches63c3a662011-04-26 08:12:10 +00009809 if (!tg3_flag(tp, TAGGED_STATUS)) {
David S. Millerfac9b832005-05-18 22:46:34 -07009810 /* All of this garbage is because when using non-tagged
9811 * IRQ status the mailbox/status_block protocol the chip
9812 * uses with the cpu is race prone.
9813 */
Matt Carlson898a56f2009-08-28 14:02:40 +00009814 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
David S. Millerfac9b832005-05-18 22:46:34 -07009815 tw32(GRC_LOCAL_CTRL,
9816 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9817 } else {
9818 tw32(HOSTCC_MODE, tp->coalesce_mode |
Matt Carlsonfd2ce372009-09-01 12:51:13 +00009819 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
David S. Millerfac9b832005-05-18 22:46:34 -07009820 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009821
David S. Millerfac9b832005-05-18 22:46:34 -07009822 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
David S. Millerf47c11e2005-06-24 20:18:35 -07009823 spin_unlock(&tp->lock);
Matt Carlsondb219972011-11-04 09:15:03 +00009824 tg3_reset_task_schedule(tp);
Matt Carlson5b190622011-11-04 09:15:04 +00009825 goto restart_timer;
David S. Millerfac9b832005-05-18 22:46:34 -07009826 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009827 }
9828
Linus Torvalds1da177e2005-04-16 15:20:36 -07009829 /* This part only runs once per second. */
9830 if (!--tp->timer_counter) {
Joe Perches63c3a662011-04-26 08:12:10 +00009831 if (tg3_flag(tp, 5705_PLUS))
David S. Millerfac9b832005-05-18 22:46:34 -07009832 tg3_periodic_fetch_stats(tp);
9833
Matt Carlsonb0c59432011-05-19 12:12:48 +00009834 if (tp->setlpicnt && !--tp->setlpicnt)
9835 tg3_phy_eee_enable(tp);
Matt Carlson52b02d02010-10-14 10:37:41 +00009836
Joe Perches63c3a662011-04-26 08:12:10 +00009837 if (tg3_flag(tp, USE_LINKCHG_REG)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009838 u32 mac_stat;
9839 int phy_event;
9840
9841 mac_stat = tr32(MAC_STATUS);
9842
9843 phy_event = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009844 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009845 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9846 phy_event = 1;
9847 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9848 phy_event = 1;
9849
9850 if (phy_event)
9851 tg3_setup_phy(tp, 0);
Joe Perches63c3a662011-04-26 08:12:10 +00009852 } else if (tg3_flag(tp, POLL_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009853 u32 mac_stat = tr32(MAC_STATUS);
9854 int need_setup = 0;
9855
9856 if (netif_carrier_ok(tp->dev) &&
9857 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9858 need_setup = 1;
9859 }
Matt Carlsonbe98da62010-07-11 09:31:46 +00009860 if (!netif_carrier_ok(tp->dev) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07009861 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9862 MAC_STATUS_SIGNAL_DET))) {
9863 need_setup = 1;
9864 }
9865 if (need_setup) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07009866 if (!tp->serdes_counter) {
9867 tw32_f(MAC_MODE,
9868 (tp->mac_mode &
9869 ~MAC_MODE_PORT_MODE_MASK));
9870 udelay(40);
9871 tw32_f(MAC_MODE, tp->mac_mode);
9872 udelay(40);
9873 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009874 tg3_setup_phy(tp, 0);
9875 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009876 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
Joe Perches63c3a662011-04-26 08:12:10 +00009877 tg3_flag(tp, 5780_CLASS)) {
Michael Chan747e8f82005-07-25 12:33:22 -07009878 tg3_serdes_parallel_detect(tp);
Matt Carlson57d8b882010-06-05 17:24:35 +00009879 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009880
9881 tp->timer_counter = tp->timer_multiplier;
9882 }
9883
Michael Chan130b8e42006-09-27 16:00:40 -07009884 /* Heartbeat is only sent once every 2 seconds.
9885 *
9886 * The heartbeat is to tell the ASF firmware that the host
9887 * driver is still alive. In the event that the OS crashes,
9888 * ASF needs to reset the hardware to free up the FIFO space
9889 * that may be filled with rx packets destined for the host.
9890 * If the FIFO is full, ASF will no longer function properly.
9891 *
9892 * Unintended resets have been reported on real time kernels
9893 * where the timer doesn't run on time. Netpoll will also have
9894 * same problem.
9895 *
9896 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9897 * to check the ring condition when the heartbeat is expiring
9898 * before doing the reset. This will prevent most unintended
9899 * resets.
9900 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07009901 if (!--tp->asf_counter) {
Joe Perches63c3a662011-04-26 08:12:10 +00009902 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
Matt Carlson7c5026a2008-05-02 16:49:29 -07009903 tg3_wait_for_event_ack(tp);
9904
Michael Chanbbadf502006-04-06 21:46:34 -07009905 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
Michael Chan130b8e42006-09-27 16:00:40 -07009906 FWCMD_NICDRV_ALIVE3);
Michael Chanbbadf502006-04-06 21:46:34 -07009907 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
Matt Carlsonc6cdf432010-04-05 10:19:26 +00009908 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9909 TG3_FW_UPDATE_TIMEOUT_SEC);
Matt Carlson4ba526c2008-08-15 14:10:04 -07009910
9911 tg3_generate_fw_event(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009912 }
9913 tp->asf_counter = tp->asf_multiplier;
9914 }
9915
David S. Millerf47c11e2005-06-24 20:18:35 -07009916 spin_unlock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009917
Michael Chanf475f162006-03-27 23:20:14 -08009918restart_timer:
Linus Torvalds1da177e2005-04-16 15:20:36 -07009919 tp->timer.expires = jiffies + tp->timer_offset;
9920 add_timer(&tp->timer);
9921}
9922
Matt Carlson21f76382012-02-22 12:35:21 +00009923static void __devinit tg3_timer_init(struct tg3 *tp)
9924{
9925 if (tg3_flag(tp, TAGGED_STATUS) &&
9926 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9927 !tg3_flag(tp, 57765_CLASS))
9928 tp->timer_offset = HZ;
9929 else
9930 tp->timer_offset = HZ / 10;
9931
9932 BUG_ON(tp->timer_offset > HZ);
9933
9934 tp->timer_multiplier = (HZ / tp->timer_offset);
9935 tp->asf_multiplier = (HZ / tp->timer_offset) *
9936 TG3_FW_UPDATE_FREQ_SEC;
9937
9938 init_timer(&tp->timer);
9939 tp->timer.data = (unsigned long) tp;
9940 tp->timer.function = tg3_timer;
9941}
9942
9943static void tg3_timer_start(struct tg3 *tp)
9944{
9945 tp->asf_counter = tp->asf_multiplier;
9946 tp->timer_counter = tp->timer_multiplier;
9947
9948 tp->timer.expires = jiffies + tp->timer_offset;
9949 add_timer(&tp->timer);
9950}
9951
9952static void tg3_timer_stop(struct tg3 *tp)
9953{
9954 del_timer_sync(&tp->timer);
9955}
9956
9957/* Restart hardware after configuration changes, self-test, etc.
9958 * Invoked with tp->lock held.
9959 */
9960static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
9961 __releases(tp->lock)
9962 __acquires(tp->lock)
9963{
9964 int err;
9965
9966 err = tg3_init_hw(tp, reset_phy);
9967 if (err) {
9968 netdev_err(tp->dev,
9969 "Failed to re-initialize device, aborting\n");
9970 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9971 tg3_full_unlock(tp);
9972 tg3_timer_stop(tp);
9973 tp->irq_sync = 0;
9974 tg3_napi_enable(tp);
9975 dev_close(tp->dev);
9976 tg3_full_lock(tp, 0);
9977 }
9978 return err;
9979}
9980
9981static void tg3_reset_task(struct work_struct *work)
9982{
9983 struct tg3 *tp = container_of(work, struct tg3, reset_task);
9984 int err;
9985
9986 tg3_full_lock(tp, 0);
9987
9988 if (!netif_running(tp->dev)) {
9989 tg3_flag_clear(tp, RESET_TASK_PENDING);
9990 tg3_full_unlock(tp);
9991 return;
9992 }
9993
9994 tg3_full_unlock(tp);
9995
9996 tg3_phy_stop(tp);
9997
9998 tg3_netif_stop(tp);
9999
10000 tg3_full_lock(tp, 1);
10001
10002 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
10003 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10004 tp->write32_rx_mbox = tg3_write_flush_reg32;
10005 tg3_flag_set(tp, MBOX_WRITE_REORDER);
10006 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
10007 }
10008
10009 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
10010 err = tg3_init_hw(tp, 1);
10011 if (err)
10012 goto out;
10013
10014 tg3_netif_start(tp);
10015
10016out:
10017 tg3_full_unlock(tp);
10018
10019 if (!err)
10020 tg3_phy_start(tp);
10021
10022 tg3_flag_clear(tp, RESET_TASK_PENDING);
10023}
10024
Matt Carlson4f125f42009-09-01 12:55:02 +000010025static int tg3_request_irq(struct tg3 *tp, int irq_num)
Michael Chanfcfa0a32006-03-20 22:28:41 -080010026{
David Howells7d12e782006-10-05 14:55:46 +010010027 irq_handler_t fn;
Michael Chanfcfa0a32006-03-20 22:28:41 -080010028 unsigned long flags;
Matt Carlson4f125f42009-09-01 12:55:02 +000010029 char *name;
10030 struct tg3_napi *tnapi = &tp->napi[irq_num];
10031
10032 if (tp->irq_cnt == 1)
10033 name = tp->dev->name;
10034 else {
10035 name = &tnapi->irq_lbl[0];
10036 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
10037 name[IFNAMSIZ-1] = 0;
10038 }
Michael Chanfcfa0a32006-03-20 22:28:41 -080010039
Joe Perches63c3a662011-04-26 08:12:10 +000010040 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
Michael Chanfcfa0a32006-03-20 22:28:41 -080010041 fn = tg3_msi;
Joe Perches63c3a662011-04-26 08:12:10 +000010042 if (tg3_flag(tp, 1SHOT_MSI))
Michael Chanfcfa0a32006-03-20 22:28:41 -080010043 fn = tg3_msi_1shot;
Javier Martinez Canillasab392d22011-03-28 16:27:31 +000010044 flags = 0;
Michael Chanfcfa0a32006-03-20 22:28:41 -080010045 } else {
10046 fn = tg3_interrupt;
Joe Perches63c3a662011-04-26 08:12:10 +000010047 if (tg3_flag(tp, TAGGED_STATUS))
Michael Chanfcfa0a32006-03-20 22:28:41 -080010048 fn = tg3_interrupt_tagged;
Javier Martinez Canillasab392d22011-03-28 16:27:31 +000010049 flags = IRQF_SHARED;
Michael Chanfcfa0a32006-03-20 22:28:41 -080010050 }
Matt Carlson4f125f42009-09-01 12:55:02 +000010051
10052 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
Michael Chanfcfa0a32006-03-20 22:28:41 -080010053}
10054
Michael Chan79381092005-04-21 17:13:59 -070010055static int tg3_test_interrupt(struct tg3 *tp)
10056{
Matt Carlson09943a12009-08-28 14:01:57 +000010057 struct tg3_napi *tnapi = &tp->napi[0];
Michael Chan79381092005-04-21 17:13:59 -070010058 struct net_device *dev = tp->dev;
Michael Chanb16250e2006-09-27 16:10:14 -070010059 int err, i, intr_ok = 0;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000010060 u32 val;
Michael Chan79381092005-04-21 17:13:59 -070010061
Michael Chand4bc3922005-05-29 14:59:20 -070010062 if (!netif_running(dev))
10063 return -ENODEV;
10064
Michael Chan79381092005-04-21 17:13:59 -070010065 tg3_disable_ints(tp);
10066
Matt Carlson4f125f42009-09-01 12:55:02 +000010067 free_irq(tnapi->irq_vec, tnapi);
Michael Chan79381092005-04-21 17:13:59 -070010068
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000010069 /*
10070 * Turn off MSI one shot mode. Otherwise this test has no
10071 * observable way to know whether the interrupt was delivered.
10072 */
Matt Carlson3aa1cdf2011-07-20 10:20:55 +000010073 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000010074 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
10075 tw32(MSGINT_MODE, val);
10076 }
10077
Matt Carlson4f125f42009-09-01 12:55:02 +000010078 err = request_irq(tnapi->irq_vec, tg3_test_isr,
Davidlohr Buesof274fd92012-02-22 03:06:54 +000010079 IRQF_SHARED, dev->name, tnapi);
Michael Chan79381092005-04-21 17:13:59 -070010080 if (err)
10081 return err;
10082
Matt Carlson898a56f2009-08-28 14:02:40 +000010083 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
Michael Chan79381092005-04-21 17:13:59 -070010084 tg3_enable_ints(tp);
10085
10086 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000010087 tnapi->coal_now);
Michael Chan79381092005-04-21 17:13:59 -070010088
10089 for (i = 0; i < 5; i++) {
Michael Chanb16250e2006-09-27 16:10:14 -070010090 u32 int_mbox, misc_host_ctrl;
10091
Matt Carlson898a56f2009-08-28 14:02:40 +000010092 int_mbox = tr32_mailbox(tnapi->int_mbox);
Michael Chanb16250e2006-09-27 16:10:14 -070010093 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
10094
10095 if ((int_mbox != 0) ||
10096 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
10097 intr_ok = 1;
Michael Chan79381092005-04-21 17:13:59 -070010098 break;
Michael Chanb16250e2006-09-27 16:10:14 -070010099 }
10100
Matt Carlson3aa1cdf2011-07-20 10:20:55 +000010101 if (tg3_flag(tp, 57765_PLUS) &&
10102 tnapi->hw_status->status_tag != tnapi->last_tag)
10103 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
10104
Michael Chan79381092005-04-21 17:13:59 -070010105 msleep(10);
10106 }
10107
10108 tg3_disable_ints(tp);
10109
Matt Carlson4f125f42009-09-01 12:55:02 +000010110 free_irq(tnapi->irq_vec, tnapi);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010111
Matt Carlson4f125f42009-09-01 12:55:02 +000010112 err = tg3_request_irq(tp, 0);
Michael Chan79381092005-04-21 17:13:59 -070010113
10114 if (err)
10115 return err;
10116
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000010117 if (intr_ok) {
10118 /* Reenable MSI one shot mode. */
Matt Carlson5b39de92011-08-31 11:44:50 +000010119 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000010120 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
10121 tw32(MSGINT_MODE, val);
10122 }
Michael Chan79381092005-04-21 17:13:59 -070010123 return 0;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000010124 }
Michael Chan79381092005-04-21 17:13:59 -070010125
10126 return -EIO;
10127}
10128
10129/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
10130 * successfully restored
10131 */
10132static int tg3_test_msi(struct tg3 *tp)
10133{
Michael Chan79381092005-04-21 17:13:59 -070010134 int err;
10135 u16 pci_cmd;
10136
Joe Perches63c3a662011-04-26 08:12:10 +000010137 if (!tg3_flag(tp, USING_MSI))
Michael Chan79381092005-04-21 17:13:59 -070010138 return 0;
10139
10140 /* Turn off SERR reporting in case MSI terminates with Master
10141 * Abort.
10142 */
10143 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10144 pci_write_config_word(tp->pdev, PCI_COMMAND,
10145 pci_cmd & ~PCI_COMMAND_SERR);
10146
10147 err = tg3_test_interrupt(tp);
10148
10149 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10150
10151 if (!err)
10152 return 0;
10153
10154 /* other failures */
10155 if (err != -EIO)
10156 return err;
10157
10158 /* MSI test failed, go back to INTx mode */
Matt Carlson5129c3a2010-04-05 10:19:23 +000010159 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
10160 "to INTx mode. Please report this failure to the PCI "
10161 "maintainer and include system chipset information\n");
Michael Chan79381092005-04-21 17:13:59 -070010162
Matt Carlson4f125f42009-09-01 12:55:02 +000010163 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
Matt Carlson09943a12009-08-28 14:01:57 +000010164
Michael Chan79381092005-04-21 17:13:59 -070010165 pci_disable_msi(tp->pdev);
10166
Joe Perches63c3a662011-04-26 08:12:10 +000010167 tg3_flag_clear(tp, USING_MSI);
Andre Detschdc8bf1b2010-04-26 07:27:07 +000010168 tp->napi[0].irq_vec = tp->pdev->irq;
Michael Chan79381092005-04-21 17:13:59 -070010169
Matt Carlson4f125f42009-09-01 12:55:02 +000010170 err = tg3_request_irq(tp, 0);
Michael Chan79381092005-04-21 17:13:59 -070010171 if (err)
10172 return err;
10173
10174 /* Need to reset the chip because the MSI cycle may have terminated
10175 * with Master Abort.
10176 */
David S. Millerf47c11e2005-06-24 20:18:35 -070010177 tg3_full_lock(tp, 1);
Michael Chan79381092005-04-21 17:13:59 -070010178
Michael Chan944d9802005-05-29 14:57:48 -070010179 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Gary Zambrano8e7a22e2006-04-29 18:59:13 -070010180 err = tg3_init_hw(tp, 1);
Michael Chan79381092005-04-21 17:13:59 -070010181
David S. Millerf47c11e2005-06-24 20:18:35 -070010182 tg3_full_unlock(tp);
Michael Chan79381092005-04-21 17:13:59 -070010183
10184 if (err)
Matt Carlson4f125f42009-09-01 12:55:02 +000010185 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
Michael Chan79381092005-04-21 17:13:59 -070010186
10187 return err;
10188}
10189
Matt Carlson9e9fd122009-01-19 16:57:45 -080010190static int tg3_request_firmware(struct tg3 *tp)
10191{
10192 const __be32 *fw_data;
10193
10194 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
Joe Perches05dbe002010-02-17 19:44:19 +000010195 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
10196 tp->fw_needed);
Matt Carlson9e9fd122009-01-19 16:57:45 -080010197 return -ENOENT;
10198 }
10199
10200 fw_data = (void *)tp->fw->data;
10201
10202 /* Firmware blob starts with version numbers, followed by
10203 * start address and _full_ length including BSS sections
10204 * (which must be longer than the actual data, of course
10205 */
10206
10207 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
10208 if (tp->fw_len < (tp->fw->size - 12)) {
Joe Perches05dbe002010-02-17 19:44:19 +000010209 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
10210 tp->fw_len, tp->fw_needed);
Matt Carlson9e9fd122009-01-19 16:57:45 -080010211 release_firmware(tp->fw);
10212 tp->fw = NULL;
10213 return -EINVAL;
10214 }
10215
10216 /* We no longer need firmware; we have it. */
10217 tp->fw_needed = NULL;
10218 return 0;
10219}
10220
Michael Chan91024262012-09-28 07:12:38 +000010221static u32 tg3_irq_count(struct tg3 *tp)
Matt Carlson679563f2009-09-01 12:55:46 +000010222{
Michael Chan91024262012-09-28 07:12:38 +000010223 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
Matt Carlson679563f2009-09-01 12:55:46 +000010224
Michael Chan91024262012-09-28 07:12:38 +000010225 if (irq_cnt > 1) {
Matt Carlsonc3b50032012-01-17 15:27:23 +000010226 /* We want as many rx rings enabled as there are cpus.
10227 * In multiqueue MSI-X mode, the first MSI-X vector
10228 * only deals with link interrupts, etc, so we add
10229 * one to the number of vectors we are requesting.
10230 */
Michael Chan91024262012-09-28 07:12:38 +000010231 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
Matt Carlsonc3b50032012-01-17 15:27:23 +000010232 }
Matt Carlson679563f2009-09-01 12:55:46 +000010233
Michael Chan91024262012-09-28 07:12:38 +000010234 return irq_cnt;
10235}
10236
10237static bool tg3_enable_msix(struct tg3 *tp)
10238{
10239 int i, rc;
10240 struct msix_entry msix_ent[tp->irq_max];
10241
Michael Chan09681692012-09-28 07:12:42 +000010242 tp->txq_cnt = tp->txq_req;
10243 tp->rxq_cnt = tp->rxq_req;
10244 if (!tp->rxq_cnt)
10245 tp->rxq_cnt = netif_get_num_default_rss_queues();
Michael Chan91024262012-09-28 07:12:38 +000010246 if (tp->rxq_cnt > tp->rxq_max)
10247 tp->rxq_cnt = tp->rxq_max;
Michael Chan09681692012-09-28 07:12:42 +000010248 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
10249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
10250 !tp->txq_req)
Michael Chan91024262012-09-28 07:12:38 +000010251 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
10252
10253 tp->irq_cnt = tg3_irq_count(tp);
10254
Matt Carlson679563f2009-09-01 12:55:46 +000010255 for (i = 0; i < tp->irq_max; i++) {
10256 msix_ent[i].entry = i;
10257 msix_ent[i].vector = 0;
10258 }
10259
10260 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
Matt Carlson2430b032010-06-05 17:24:34 +000010261 if (rc < 0) {
10262 return false;
10263 } else if (rc != 0) {
Matt Carlson679563f2009-09-01 12:55:46 +000010264 if (pci_enable_msix(tp->pdev, msix_ent, rc))
10265 return false;
Joe Perches05dbe002010-02-17 19:44:19 +000010266 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
10267 tp->irq_cnt, rc);
Matt Carlson679563f2009-09-01 12:55:46 +000010268 tp->irq_cnt = rc;
Michael Chan49a359e2012-09-28 07:12:37 +000010269 tp->rxq_cnt = max(rc - 1, 1);
Michael Chan91024262012-09-28 07:12:38 +000010270 if (tp->txq_cnt)
10271 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
Matt Carlson679563f2009-09-01 12:55:46 +000010272 }
10273
10274 for (i = 0; i < tp->irq_max; i++)
10275 tp->napi[i].irq_vec = msix_ent[i].vector;
10276
Michael Chan49a359e2012-09-28 07:12:37 +000010277 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
Ben Hutchings2ddaad32010-09-27 22:11:51 -070010278 pci_disable_msix(tp->pdev);
10279 return false;
10280 }
Matt Carlsonb92b9042010-11-24 08:31:51 +000010281
Michael Chan91024262012-09-28 07:12:38 +000010282 if (tp->irq_cnt == 1)
10283 return true;
Matt Carlsond78b59f2011-04-05 14:22:46 +000010284
Michael Chan91024262012-09-28 07:12:38 +000010285 tg3_flag_set(tp, ENABLE_RSS);
10286
10287 if (tp->txq_cnt > 1)
10288 tg3_flag_set(tp, ENABLE_TSS);
10289
10290 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
Matt Carlson2430b032010-06-05 17:24:34 +000010291
Matt Carlson679563f2009-09-01 12:55:46 +000010292 return true;
10293}
10294
Matt Carlson07b01732009-08-28 14:01:15 +000010295static void tg3_ints_init(struct tg3 *tp)
10296{
Joe Perches63c3a662011-04-26 08:12:10 +000010297 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
10298 !tg3_flag(tp, TAGGED_STATUS)) {
Matt Carlson07b01732009-08-28 14:01:15 +000010299 /* All MSI supporting chips should support tagged
10300 * status. Assert that this is the case.
10301 */
Matt Carlson5129c3a2010-04-05 10:19:23 +000010302 netdev_warn(tp->dev,
10303 "MSI without TAGGED_STATUS? Not using MSI\n");
Matt Carlson679563f2009-09-01 12:55:46 +000010304 goto defcfg;
Matt Carlson07b01732009-08-28 14:01:15 +000010305 }
Matt Carlson4f125f42009-09-01 12:55:02 +000010306
Joe Perches63c3a662011-04-26 08:12:10 +000010307 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
10308 tg3_flag_set(tp, USING_MSIX);
10309 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
10310 tg3_flag_set(tp, USING_MSI);
Matt Carlson679563f2009-09-01 12:55:46 +000010311
Joe Perches63c3a662011-04-26 08:12:10 +000010312 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
Matt Carlson679563f2009-09-01 12:55:46 +000010313 u32 msi_mode = tr32(MSGINT_MODE);
Joe Perches63c3a662011-04-26 08:12:10 +000010314 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
Matt Carlsonbaf8a942009-09-01 13:13:00 +000010315 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
Matt Carlson5b39de92011-08-31 11:44:50 +000010316 if (!tg3_flag(tp, 1SHOT_MSI))
10317 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
Matt Carlson679563f2009-09-01 12:55:46 +000010318 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
10319 }
10320defcfg:
Joe Perches63c3a662011-04-26 08:12:10 +000010321 if (!tg3_flag(tp, USING_MSIX)) {
Matt Carlson679563f2009-09-01 12:55:46 +000010322 tp->irq_cnt = 1;
10323 tp->napi[0].irq_vec = tp->pdev->irq;
Michael Chan49a359e2012-09-28 07:12:37 +000010324 }
10325
10326 if (tp->irq_cnt == 1) {
10327 tp->txq_cnt = 1;
10328 tp->rxq_cnt = 1;
Ben Hutchings2ddaad32010-09-27 22:11:51 -070010329 netif_set_real_num_tx_queues(tp->dev, 1);
Matt Carlson85407882010-10-06 13:40:58 -070010330 netif_set_real_num_rx_queues(tp->dev, 1);
Matt Carlson679563f2009-09-01 12:55:46 +000010331 }
Matt Carlson07b01732009-08-28 14:01:15 +000010332}
10333
10334static void tg3_ints_fini(struct tg3 *tp)
10335{
Joe Perches63c3a662011-04-26 08:12:10 +000010336 if (tg3_flag(tp, USING_MSIX))
Matt Carlson679563f2009-09-01 12:55:46 +000010337 pci_disable_msix(tp->pdev);
Joe Perches63c3a662011-04-26 08:12:10 +000010338 else if (tg3_flag(tp, USING_MSI))
Matt Carlson679563f2009-09-01 12:55:46 +000010339 pci_disable_msi(tp->pdev);
Joe Perches63c3a662011-04-26 08:12:10 +000010340 tg3_flag_clear(tp, USING_MSI);
10341 tg3_flag_clear(tp, USING_MSIX);
10342 tg3_flag_clear(tp, ENABLE_RSS);
10343 tg3_flag_clear(tp, ENABLE_TSS);
Matt Carlson07b01732009-08-28 14:01:15 +000010344}
10345
Michael Chand8f4cd32012-09-28 07:12:40 +000010346static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010347{
Michael Chand8f4cd32012-09-28 07:12:40 +000010348 struct net_device *dev = tp->dev;
Matt Carlson4f125f42009-09-01 12:55:02 +000010349 int i, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010350
Matt Carlson679563f2009-09-01 12:55:46 +000010351 /*
10352 * Setup interrupts first so we know how
10353 * many NAPI resources to allocate
10354 */
10355 tg3_ints_init(tp);
10356
Matt Carlson90415472011-12-16 13:33:23 +000010357 tg3_rss_check_indir_tbl(tp);
Matt Carlsonbcebcc42011-12-14 11:10:01 +000010358
Linus Torvalds1da177e2005-04-16 15:20:36 -070010359 /* The placement of this call is tied
10360 * to the setup and use of Host TX descriptors.
10361 */
10362 err = tg3_alloc_consistent(tp);
10363 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +000010364 goto err_out1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010365
Matt Carlson66cfd1b2010-09-30 10:34:30 +000010366 tg3_napi_init(tp);
10367
Matt Carlsonfed97812009-09-01 13:10:19 +000010368 tg3_napi_enable(tp);
Stephen Hemmingerbea33482007-10-03 16:41:36 -070010369
Matt Carlson4f125f42009-09-01 12:55:02 +000010370 for (i = 0; i < tp->irq_cnt; i++) {
10371 struct tg3_napi *tnapi = &tp->napi[i];
10372 err = tg3_request_irq(tp, i);
10373 if (err) {
Matt Carlson5bc09182011-11-04 09:15:01 +000010374 for (i--; i >= 0; i--) {
10375 tnapi = &tp->napi[i];
Matt Carlson4f125f42009-09-01 12:55:02 +000010376 free_irq(tnapi->irq_vec, tnapi);
Matt Carlson5bc09182011-11-04 09:15:01 +000010377 }
10378 goto err_out2;
Matt Carlson4f125f42009-09-01 12:55:02 +000010379 }
10380 }
Matt Carlson07b01732009-08-28 14:01:15 +000010381
David S. Millerf47c11e2005-06-24 20:18:35 -070010382 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010383
Michael Chand8f4cd32012-09-28 07:12:40 +000010384 err = tg3_init_hw(tp, reset_phy);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010385 if (err) {
Michael Chan944d9802005-05-29 14:57:48 -070010386 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010387 tg3_free_rings(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010388 }
10389
David S. Millerf47c11e2005-06-24 20:18:35 -070010390 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010391
Matt Carlson07b01732009-08-28 14:01:15 +000010392 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +000010393 goto err_out3;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010394
Michael Chand8f4cd32012-09-28 07:12:40 +000010395 if (test_irq && tg3_flag(tp, USING_MSI)) {
Michael Chan79381092005-04-21 17:13:59 -070010396 err = tg3_test_msi(tp);
David S. Millerfac9b832005-05-18 22:46:34 -070010397
Michael Chan79381092005-04-21 17:13:59 -070010398 if (err) {
David S. Millerf47c11e2005-06-24 20:18:35 -070010399 tg3_full_lock(tp, 0);
Michael Chan944d9802005-05-29 14:57:48 -070010400 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chan79381092005-04-21 17:13:59 -070010401 tg3_free_rings(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -070010402 tg3_full_unlock(tp);
Michael Chan79381092005-04-21 17:13:59 -070010403
Matt Carlson679563f2009-09-01 12:55:46 +000010404 goto err_out2;
Michael Chan79381092005-04-21 17:13:59 -070010405 }
Michael Chanfcfa0a32006-03-20 22:28:41 -080010406
Joe Perches63c3a662011-04-26 08:12:10 +000010407 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000010408 u32 val = tr32(PCIE_TRANSACTION_CFG);
Michael Chanfcfa0a32006-03-20 22:28:41 -080010409
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000010410 tw32(PCIE_TRANSACTION_CFG,
10411 val | PCIE_TRANS_CFG_1SHOT_MSI);
Michael Chanfcfa0a32006-03-20 22:28:41 -080010412 }
Michael Chan79381092005-04-21 17:13:59 -070010413 }
10414
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010415 tg3_phy_start(tp);
10416
Michael Chanaed93e02012-07-16 16:24:02 +000010417 tg3_hwmon_open(tp);
10418
David S. Millerf47c11e2005-06-24 20:18:35 -070010419 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010420
Matt Carlson21f76382012-02-22 12:35:21 +000010421 tg3_timer_start(tp);
Joe Perches63c3a662011-04-26 08:12:10 +000010422 tg3_flag_set(tp, INIT_COMPLETE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010423 tg3_enable_ints(tp);
10424
David S. Millerf47c11e2005-06-24 20:18:35 -070010425 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010426
Matt Carlsonfe5f5782009-09-01 13:09:39 +000010427 netif_tx_start_all_queues(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010428
Mahesh Bandewar06c03c02011-05-08 06:51:48 +000010429 /*
10430 * Reset loopback feature if it was turned on while the device was down
10431 * make sure that it's installed properly now.
10432 */
10433 if (dev->features & NETIF_F_LOOPBACK)
10434 tg3_set_loopback(dev, dev->features);
10435
Linus Torvalds1da177e2005-04-16 15:20:36 -070010436 return 0;
Matt Carlson07b01732009-08-28 14:01:15 +000010437
Matt Carlson679563f2009-09-01 12:55:46 +000010438err_out3:
Matt Carlson4f125f42009-09-01 12:55:02 +000010439 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10440 struct tg3_napi *tnapi = &tp->napi[i];
10441 free_irq(tnapi->irq_vec, tnapi);
10442 }
Matt Carlson07b01732009-08-28 14:01:15 +000010443
Matt Carlson679563f2009-09-01 12:55:46 +000010444err_out2:
Matt Carlsonfed97812009-09-01 13:10:19 +000010445 tg3_napi_disable(tp);
Matt Carlson66cfd1b2010-09-30 10:34:30 +000010446 tg3_napi_fini(tp);
Matt Carlson07b01732009-08-28 14:01:15 +000010447 tg3_free_consistent(tp);
Matt Carlson679563f2009-09-01 12:55:46 +000010448
10449err_out1:
10450 tg3_ints_fini(tp);
Michael Chand8f4cd32012-09-28 07:12:40 +000010451
10452 return err;
10453}
10454
Michael Chan65138592012-09-28 07:12:41 +000010455static void tg3_stop(struct tg3 *tp)
10456{
10457 int i;
10458
10459 tg3_napi_disable(tp);
10460 tg3_reset_task_cancel(tp);
10461
10462 netif_tx_disable(tp->dev);
10463
10464 tg3_timer_stop(tp);
10465
10466 tg3_hwmon_close(tp);
10467
10468 tg3_phy_stop(tp);
10469
10470 tg3_full_lock(tp, 1);
10471
10472 tg3_disable_ints(tp);
10473
10474 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10475 tg3_free_rings(tp);
10476 tg3_flag_clear(tp, INIT_COMPLETE);
10477
10478 tg3_full_unlock(tp);
10479
10480 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10481 struct tg3_napi *tnapi = &tp->napi[i];
10482 free_irq(tnapi->irq_vec, tnapi);
10483 }
10484
10485 tg3_ints_fini(tp);
10486
10487 tg3_napi_fini(tp);
10488
10489 tg3_free_consistent(tp);
10490}
10491
Michael Chand8f4cd32012-09-28 07:12:40 +000010492static int tg3_open(struct net_device *dev)
10493{
10494 struct tg3 *tp = netdev_priv(dev);
10495 int err;
10496
10497 if (tp->fw_needed) {
10498 err = tg3_request_firmware(tp);
10499 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
10500 if (err)
10501 return err;
10502 } else if (err) {
10503 netdev_warn(tp->dev, "TSO capability disabled\n");
10504 tg3_flag_clear(tp, TSO_CAPABLE);
10505 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
10506 netdev_notice(tp->dev, "TSO capability restored\n");
10507 tg3_flag_set(tp, TSO_CAPABLE);
10508 }
10509 }
10510
10511 netif_carrier_off(tp->dev);
10512
10513 err = tg3_power_up(tp);
10514 if (err)
10515 return err;
10516
10517 tg3_full_lock(tp, 0);
10518
10519 tg3_disable_ints(tp);
10520 tg3_flag_clear(tp, INIT_COMPLETE);
10521
10522 tg3_full_unlock(tp);
10523
10524 err = tg3_start(tp, true, true);
10525 if (err) {
10526 tg3_frob_aux_power(tp, false);
10527 pci_set_power_state(tp->pdev, PCI_D3hot);
10528 }
Matt Carlson07b01732009-08-28 14:01:15 +000010529 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010530}
10531
Linus Torvalds1da177e2005-04-16 15:20:36 -070010532static int tg3_close(struct net_device *dev)
10533{
10534 struct tg3 *tp = netdev_priv(dev);
10535
Michael Chan65138592012-09-28 07:12:41 +000010536 tg3_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010537
Matt Carlson92feeab2011-12-08 14:40:14 +000010538 /* Clear stats across close / open calls */
10539 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
10540 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
Linus Torvalds1da177e2005-04-16 15:20:36 -070010541
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000010542 tg3_power_down(tp);
Michael Chanbc1c7562006-03-20 17:48:03 -080010543
10544 netif_carrier_off(tp->dev);
10545
Linus Torvalds1da177e2005-04-16 15:20:36 -070010546 return 0;
10547}
10548
Eric Dumazet511d2222010-07-07 20:44:24 +000010549static inline u64 get_stat64(tg3_stat64_t *val)
Stefan Buehler816f8b82008-08-15 14:10:54 -070010550{
10551 return ((u64)val->high << 32) | ((u64)val->low);
10552}
10553
Matt Carlson65ec6982012-02-28 23:33:37 +000010554static u64 tg3_calc_crc_errors(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010555{
10556 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10557
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010558 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070010559 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10560 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010561 u32 val;
10562
Michael Chan569a5df2007-02-13 12:18:15 -080010563 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
10564 tg3_writephy(tp, MII_TG3_TEST1,
10565 val | MII_TG3_TEST1_CRC_EN);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +000010566 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010567 } else
10568 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010569
10570 tp->phy_crc_errors += val;
10571
10572 return tp->phy_crc_errors;
10573 }
10574
10575 return get_stat64(&hw_stats->rx_fcs_errors);
10576}
10577
10578#define ESTAT_ADD(member) \
10579 estats->member = old_estats->member + \
Eric Dumazet511d2222010-07-07 20:44:24 +000010580 get_stat64(&hw_stats->member)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010581
Matt Carlson65ec6982012-02-28 23:33:37 +000010582static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010583{
Linus Torvalds1da177e2005-04-16 15:20:36 -070010584 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
10585 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10586
Linus Torvalds1da177e2005-04-16 15:20:36 -070010587 ESTAT_ADD(rx_octets);
10588 ESTAT_ADD(rx_fragments);
10589 ESTAT_ADD(rx_ucast_packets);
10590 ESTAT_ADD(rx_mcast_packets);
10591 ESTAT_ADD(rx_bcast_packets);
10592 ESTAT_ADD(rx_fcs_errors);
10593 ESTAT_ADD(rx_align_errors);
10594 ESTAT_ADD(rx_xon_pause_rcvd);
10595 ESTAT_ADD(rx_xoff_pause_rcvd);
10596 ESTAT_ADD(rx_mac_ctrl_rcvd);
10597 ESTAT_ADD(rx_xoff_entered);
10598 ESTAT_ADD(rx_frame_too_long_errors);
10599 ESTAT_ADD(rx_jabbers);
10600 ESTAT_ADD(rx_undersize_packets);
10601 ESTAT_ADD(rx_in_length_errors);
10602 ESTAT_ADD(rx_out_length_errors);
10603 ESTAT_ADD(rx_64_or_less_octet_packets);
10604 ESTAT_ADD(rx_65_to_127_octet_packets);
10605 ESTAT_ADD(rx_128_to_255_octet_packets);
10606 ESTAT_ADD(rx_256_to_511_octet_packets);
10607 ESTAT_ADD(rx_512_to_1023_octet_packets);
10608 ESTAT_ADD(rx_1024_to_1522_octet_packets);
10609 ESTAT_ADD(rx_1523_to_2047_octet_packets);
10610 ESTAT_ADD(rx_2048_to_4095_octet_packets);
10611 ESTAT_ADD(rx_4096_to_8191_octet_packets);
10612 ESTAT_ADD(rx_8192_to_9022_octet_packets);
10613
10614 ESTAT_ADD(tx_octets);
10615 ESTAT_ADD(tx_collisions);
10616 ESTAT_ADD(tx_xon_sent);
10617 ESTAT_ADD(tx_xoff_sent);
10618 ESTAT_ADD(tx_flow_control);
10619 ESTAT_ADD(tx_mac_errors);
10620 ESTAT_ADD(tx_single_collisions);
10621 ESTAT_ADD(tx_mult_collisions);
10622 ESTAT_ADD(tx_deferred);
10623 ESTAT_ADD(tx_excessive_collisions);
10624 ESTAT_ADD(tx_late_collisions);
10625 ESTAT_ADD(tx_collide_2times);
10626 ESTAT_ADD(tx_collide_3times);
10627 ESTAT_ADD(tx_collide_4times);
10628 ESTAT_ADD(tx_collide_5times);
10629 ESTAT_ADD(tx_collide_6times);
10630 ESTAT_ADD(tx_collide_7times);
10631 ESTAT_ADD(tx_collide_8times);
10632 ESTAT_ADD(tx_collide_9times);
10633 ESTAT_ADD(tx_collide_10times);
10634 ESTAT_ADD(tx_collide_11times);
10635 ESTAT_ADD(tx_collide_12times);
10636 ESTAT_ADD(tx_collide_13times);
10637 ESTAT_ADD(tx_collide_14times);
10638 ESTAT_ADD(tx_collide_15times);
10639 ESTAT_ADD(tx_ucast_packets);
10640 ESTAT_ADD(tx_mcast_packets);
10641 ESTAT_ADD(tx_bcast_packets);
10642 ESTAT_ADD(tx_carrier_sense_errors);
10643 ESTAT_ADD(tx_discards);
10644 ESTAT_ADD(tx_errors);
10645
10646 ESTAT_ADD(dma_writeq_full);
10647 ESTAT_ADD(dma_write_prioq_full);
10648 ESTAT_ADD(rxbds_empty);
10649 ESTAT_ADD(rx_discards);
10650 ESTAT_ADD(rx_errors);
10651 ESTAT_ADD(rx_threshold_hit);
10652
10653 ESTAT_ADD(dma_readq_full);
10654 ESTAT_ADD(dma_read_prioq_full);
10655 ESTAT_ADD(tx_comp_queue_full);
10656
10657 ESTAT_ADD(ring_set_send_prod_index);
10658 ESTAT_ADD(ring_status_update);
10659 ESTAT_ADD(nic_irqs);
10660 ESTAT_ADD(nic_avoided_irqs);
10661 ESTAT_ADD(nic_tx_threshold_hit);
10662
Matt Carlson4452d092011-05-19 12:12:51 +000010663 ESTAT_ADD(mbuf_lwm_thresh_hit);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010664}
10665
Matt Carlson65ec6982012-02-28 23:33:37 +000010666static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010667{
Eric Dumazet511d2222010-07-07 20:44:24 +000010668 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010669 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10670
Linus Torvalds1da177e2005-04-16 15:20:36 -070010671 stats->rx_packets = old_stats->rx_packets +
10672 get_stat64(&hw_stats->rx_ucast_packets) +
10673 get_stat64(&hw_stats->rx_mcast_packets) +
10674 get_stat64(&hw_stats->rx_bcast_packets);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010675
Linus Torvalds1da177e2005-04-16 15:20:36 -070010676 stats->tx_packets = old_stats->tx_packets +
10677 get_stat64(&hw_stats->tx_ucast_packets) +
10678 get_stat64(&hw_stats->tx_mcast_packets) +
10679 get_stat64(&hw_stats->tx_bcast_packets);
10680
10681 stats->rx_bytes = old_stats->rx_bytes +
10682 get_stat64(&hw_stats->rx_octets);
10683 stats->tx_bytes = old_stats->tx_bytes +
10684 get_stat64(&hw_stats->tx_octets);
10685
10686 stats->rx_errors = old_stats->rx_errors +
John W. Linville4f63b872005-09-12 14:43:18 -070010687 get_stat64(&hw_stats->rx_errors);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010688 stats->tx_errors = old_stats->tx_errors +
10689 get_stat64(&hw_stats->tx_errors) +
10690 get_stat64(&hw_stats->tx_mac_errors) +
10691 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10692 get_stat64(&hw_stats->tx_discards);
10693
10694 stats->multicast = old_stats->multicast +
10695 get_stat64(&hw_stats->rx_mcast_packets);
10696 stats->collisions = old_stats->collisions +
10697 get_stat64(&hw_stats->tx_collisions);
10698
10699 stats->rx_length_errors = old_stats->rx_length_errors +
10700 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10701 get_stat64(&hw_stats->rx_undersize_packets);
10702
10703 stats->rx_over_errors = old_stats->rx_over_errors +
10704 get_stat64(&hw_stats->rxbds_empty);
10705 stats->rx_frame_errors = old_stats->rx_frame_errors +
10706 get_stat64(&hw_stats->rx_align_errors);
10707 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10708 get_stat64(&hw_stats->tx_discards);
10709 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10710 get_stat64(&hw_stats->tx_carrier_sense_errors);
10711
10712 stats->rx_crc_errors = old_stats->rx_crc_errors +
Matt Carlson65ec6982012-02-28 23:33:37 +000010713 tg3_calc_crc_errors(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010714
John W. Linville4f63b872005-09-12 14:43:18 -070010715 stats->rx_missed_errors = old_stats->rx_missed_errors +
10716 get_stat64(&hw_stats->rx_discards);
10717
Eric Dumazetb0057c52010-10-10 19:55:52 +000010718 stats->rx_dropped = tp->rx_dropped;
Eric Dumazet48855432011-10-24 07:53:03 +000010719 stats->tx_dropped = tp->tx_dropped;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010720}
10721
Linus Torvalds1da177e2005-04-16 15:20:36 -070010722static int tg3_get_regs_len(struct net_device *dev)
10723{
Matt Carlson97bd8e42011-04-13 11:05:04 +000010724 return TG3_REG_BLK_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010725}
10726
10727static void tg3_get_regs(struct net_device *dev,
10728 struct ethtool_regs *regs, void *_p)
10729{
Linus Torvalds1da177e2005-04-16 15:20:36 -070010730 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010731
10732 regs->version = 0;
10733
Matt Carlson97bd8e42011-04-13 11:05:04 +000010734 memset(_p, 0, TG3_REG_BLK_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010735
Matt Carlson80096062010-08-02 11:26:06 +000010736 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010737 return;
10738
David S. Millerf47c11e2005-06-24 20:18:35 -070010739 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010740
Matt Carlson97bd8e42011-04-13 11:05:04 +000010741 tg3_dump_legacy_regs(tp, (u32 *)_p);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010742
David S. Millerf47c11e2005-06-24 20:18:35 -070010743 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010744}
10745
10746static int tg3_get_eeprom_len(struct net_device *dev)
10747{
10748 struct tg3 *tp = netdev_priv(dev);
10749
10750 return tp->nvram_size;
10751}
10752
Linus Torvalds1da177e2005-04-16 15:20:36 -070010753static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10754{
10755 struct tg3 *tp = netdev_priv(dev);
10756 int ret;
10757 u8 *pd;
Al Virob9fc7dc2007-12-17 22:59:57 -080010758 u32 i, offset, len, b_offset, b_count;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010759 __be32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010760
Joe Perches63c3a662011-04-26 08:12:10 +000010761 if (tg3_flag(tp, NO_NVRAM))
Matt Carlsondf259d82009-04-20 06:57:14 +000010762 return -EINVAL;
10763
Matt Carlson80096062010-08-02 11:26:06 +000010764 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010765 return -EAGAIN;
10766
Linus Torvalds1da177e2005-04-16 15:20:36 -070010767 offset = eeprom->offset;
10768 len = eeprom->len;
10769 eeprom->len = 0;
10770
10771 eeprom->magic = TG3_EEPROM_MAGIC;
10772
10773 if (offset & 3) {
10774 /* adjustments to start on required 4 byte boundary */
10775 b_offset = offset & 3;
10776 b_count = 4 - b_offset;
10777 if (b_count > len) {
10778 /* i.e. offset=1 len=2 */
10779 b_count = len;
10780 }
Matt Carlsona9dc5292009-02-25 14:25:30 +000010781 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010782 if (ret)
10783 return ret;
Matt Carlsonbe98da62010-07-11 09:31:46 +000010784 memcpy(data, ((char *)&val) + b_offset, b_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010785 len -= b_count;
10786 offset += b_count;
Matt Carlsonc6cdf432010-04-05 10:19:26 +000010787 eeprom->len += b_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010788 }
10789
Lucas De Marchi25985ed2011-03-30 22:57:33 -030010790 /* read bytes up to the last 4 byte boundary */
Linus Torvalds1da177e2005-04-16 15:20:36 -070010791 pd = &data[eeprom->len];
10792 for (i = 0; i < (len - (len & 3)); i += 4) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000010793 ret = tg3_nvram_read_be32(tp, offset + i, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010794 if (ret) {
10795 eeprom->len += i;
10796 return ret;
10797 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070010798 memcpy(pd + i, &val, 4);
10799 }
10800 eeprom->len += i;
10801
10802 if (len & 3) {
10803 /* read last bytes not ending on 4 byte boundary */
10804 pd = &data[eeprom->len];
10805 b_count = len & 3;
10806 b_offset = offset + len - b_count;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010807 ret = tg3_nvram_read_be32(tp, b_offset, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010808 if (ret)
10809 return ret;
Al Virob9fc7dc2007-12-17 22:59:57 -080010810 memcpy(pd, &val, b_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010811 eeprom->len += b_count;
10812 }
10813 return 0;
10814}
10815
Linus Torvalds1da177e2005-04-16 15:20:36 -070010816static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10817{
10818 struct tg3 *tp = netdev_priv(dev);
10819 int ret;
Al Virob9fc7dc2007-12-17 22:59:57 -080010820 u32 offset, len, b_offset, odd_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010821 u8 *buf;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010822 __be32 start, end;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010823
Matt Carlson80096062010-08-02 11:26:06 +000010824 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010825 return -EAGAIN;
10826
Joe Perches63c3a662011-04-26 08:12:10 +000010827 if (tg3_flag(tp, NO_NVRAM) ||
Matt Carlsondf259d82009-04-20 06:57:14 +000010828 eeprom->magic != TG3_EEPROM_MAGIC)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010829 return -EINVAL;
10830
10831 offset = eeprom->offset;
10832 len = eeprom->len;
10833
10834 if ((b_offset = (offset & 3))) {
10835 /* adjustments to start on required 4 byte boundary */
Matt Carlsona9dc5292009-02-25 14:25:30 +000010836 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010837 if (ret)
10838 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010839 len += b_offset;
10840 offset &= ~3;
Michael Chan1c8594b2005-04-21 17:12:46 -070010841 if (len < 4)
10842 len = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010843 }
10844
10845 odd_len = 0;
Michael Chan1c8594b2005-04-21 17:12:46 -070010846 if (len & 3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010847 /* adjustments to end on required 4 byte boundary */
10848 odd_len = 1;
10849 len = (len + 3) & ~3;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010850 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010851 if (ret)
10852 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010853 }
10854
10855 buf = data;
10856 if (b_offset || odd_len) {
10857 buf = kmalloc(len, GFP_KERNEL);
Andy Gospodarekab0049b2007-09-06 20:42:14 +010010858 if (!buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010859 return -ENOMEM;
10860 if (b_offset)
10861 memcpy(buf, &start, 4);
10862 if (odd_len)
10863 memcpy(buf+len-4, &end, 4);
10864 memcpy(buf + b_offset, data, eeprom->len);
10865 }
10866
10867 ret = tg3_nvram_write_block(tp, offset, len, buf);
10868
10869 if (buf != data)
10870 kfree(buf);
10871
10872 return ret;
10873}
10874
10875static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10876{
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010877 struct tg3 *tp = netdev_priv(dev);
10878
Joe Perches63c3a662011-04-26 08:12:10 +000010879 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010880 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010881 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010882 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010883 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10884 return phy_ethtool_gset(phydev, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010885 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010886
Linus Torvalds1da177e2005-04-16 15:20:36 -070010887 cmd->supported = (SUPPORTED_Autoneg);
10888
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010889 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010890 cmd->supported |= (SUPPORTED_1000baseT_Half |
10891 SUPPORTED_1000baseT_Full);
10892
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010893 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010894 cmd->supported |= (SUPPORTED_100baseT_Half |
10895 SUPPORTED_100baseT_Full |
10896 SUPPORTED_10baseT_Half |
10897 SUPPORTED_10baseT_Full |
Matt Carlson3bebab52007-11-12 21:22:40 -080010898 SUPPORTED_TP);
Karsten Keilef348142006-05-12 12:49:08 -070010899 cmd->port = PORT_TP;
10900 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010901 cmd->supported |= SUPPORTED_FIBRE;
Karsten Keilef348142006-05-12 12:49:08 -070010902 cmd->port = PORT_FIBRE;
10903 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010904
Linus Torvalds1da177e2005-04-16 15:20:36 -070010905 cmd->advertising = tp->link_config.advertising;
Matt Carlson5bb09772011-06-13 13:39:00 +000010906 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10907 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10908 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10909 cmd->advertising |= ADVERTISED_Pause;
10910 } else {
10911 cmd->advertising |= ADVERTISED_Pause |
10912 ADVERTISED_Asym_Pause;
10913 }
10914 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10915 cmd->advertising |= ADVERTISED_Asym_Pause;
10916 }
10917 }
Matt Carlson859edb22011-12-08 14:40:16 +000010918 if (netif_running(dev) && netif_carrier_ok(dev)) {
David Decotigny70739492011-04-27 18:32:40 +000010919 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010920 cmd->duplex = tp->link_config.active_duplex;
Matt Carlson859edb22011-12-08 14:40:16 +000010921 cmd->lp_advertising = tp->link_config.rmt_adv;
Matt Carlsone348c5e2011-11-21 15:01:20 +000010922 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10923 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10924 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10925 else
10926 cmd->eth_tp_mdix = ETH_TP_MDI;
10927 }
Matt Carlson64c22182010-10-14 10:37:44 +000010928 } else {
Matt Carlsone7405222012-02-13 15:20:16 +000010929 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
10930 cmd->duplex = DUPLEX_UNKNOWN;
Matt Carlsone348c5e2011-11-21 15:01:20 +000010931 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010932 }
Matt Carlson882e9792009-09-01 13:21:36 +000010933 cmd->phy_address = tp->phy_addr;
Matt Carlson7e5856b2009-02-25 14:23:01 +000010934 cmd->transceiver = XCVR_INTERNAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010935 cmd->autoneg = tp->link_config.autoneg;
10936 cmd->maxtxpkt = 0;
10937 cmd->maxrxpkt = 0;
10938 return 0;
10939}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010940
Linus Torvalds1da177e2005-04-16 15:20:36 -070010941static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10942{
10943 struct tg3 *tp = netdev_priv(dev);
David Decotigny25db0332011-04-27 18:32:39 +000010944 u32 speed = ethtool_cmd_speed(cmd);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010945
Joe Perches63c3a662011-04-26 08:12:10 +000010946 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010947 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010948 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010949 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010950 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10951 return phy_ethtool_sset(phydev, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010952 }
10953
Matt Carlson7e5856b2009-02-25 14:23:01 +000010954 if (cmd->autoneg != AUTONEG_ENABLE &&
10955 cmd->autoneg != AUTONEG_DISABLE)
Michael Chan37ff2382005-10-26 15:49:51 -070010956 return -EINVAL;
Matt Carlson7e5856b2009-02-25 14:23:01 +000010957
10958 if (cmd->autoneg == AUTONEG_DISABLE &&
10959 cmd->duplex != DUPLEX_FULL &&
10960 cmd->duplex != DUPLEX_HALF)
Michael Chan37ff2382005-10-26 15:49:51 -070010961 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010962
Matt Carlson7e5856b2009-02-25 14:23:01 +000010963 if (cmd->autoneg == AUTONEG_ENABLE) {
10964 u32 mask = ADVERTISED_Autoneg |
10965 ADVERTISED_Pause |
10966 ADVERTISED_Asym_Pause;
10967
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010968 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Matt Carlson7e5856b2009-02-25 14:23:01 +000010969 mask |= ADVERTISED_1000baseT_Half |
10970 ADVERTISED_1000baseT_Full;
10971
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010972 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlson7e5856b2009-02-25 14:23:01 +000010973 mask |= ADVERTISED_100baseT_Half |
10974 ADVERTISED_100baseT_Full |
10975 ADVERTISED_10baseT_Half |
10976 ADVERTISED_10baseT_Full |
10977 ADVERTISED_TP;
10978 else
10979 mask |= ADVERTISED_FIBRE;
10980
10981 if (cmd->advertising & ~mask)
10982 return -EINVAL;
10983
10984 mask &= (ADVERTISED_1000baseT_Half |
10985 ADVERTISED_1000baseT_Full |
10986 ADVERTISED_100baseT_Half |
10987 ADVERTISED_100baseT_Full |
10988 ADVERTISED_10baseT_Half |
10989 ADVERTISED_10baseT_Full);
10990
10991 cmd->advertising &= mask;
10992 } else {
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010993 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
David Decotigny25db0332011-04-27 18:32:39 +000010994 if (speed != SPEED_1000)
Matt Carlson7e5856b2009-02-25 14:23:01 +000010995 return -EINVAL;
10996
10997 if (cmd->duplex != DUPLEX_FULL)
10998 return -EINVAL;
10999 } else {
David Decotigny25db0332011-04-27 18:32:39 +000011000 if (speed != SPEED_100 &&
11001 speed != SPEED_10)
Matt Carlson7e5856b2009-02-25 14:23:01 +000011002 return -EINVAL;
11003 }
11004 }
11005
David S. Millerf47c11e2005-06-24 20:18:35 -070011006 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011007
11008 tp->link_config.autoneg = cmd->autoneg;
11009 if (cmd->autoneg == AUTONEG_ENABLE) {
Andy Gospodarek405d8e52007-10-08 01:08:47 -070011010 tp->link_config.advertising = (cmd->advertising |
11011 ADVERTISED_Autoneg);
Matt Carlsone7405222012-02-13 15:20:16 +000011012 tp->link_config.speed = SPEED_UNKNOWN;
11013 tp->link_config.duplex = DUPLEX_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011014 } else {
11015 tp->link_config.advertising = 0;
David Decotigny25db0332011-04-27 18:32:39 +000011016 tp->link_config.speed = speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011017 tp->link_config.duplex = cmd->duplex;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011018 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011019
Linus Torvalds1da177e2005-04-16 15:20:36 -070011020 if (netif_running(dev))
11021 tg3_setup_phy(tp, 1);
11022
David S. Millerf47c11e2005-06-24 20:18:35 -070011023 tg3_full_unlock(tp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011024
Linus Torvalds1da177e2005-04-16 15:20:36 -070011025 return 0;
11026}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011027
Linus Torvalds1da177e2005-04-16 15:20:36 -070011028static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
11029{
11030 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011031
Rick Jones68aad782011-11-07 13:29:27 +000011032 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
11033 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
11034 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
11035 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
Linus Torvalds1da177e2005-04-16 15:20:36 -070011036}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011037
Linus Torvalds1da177e2005-04-16 15:20:36 -070011038static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11039{
11040 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011041
Joe Perches63c3a662011-04-26 08:12:10 +000011042 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
Gary Zambranoa85feb82007-05-05 11:52:19 -070011043 wol->supported = WAKE_MAGIC;
11044 else
11045 wol->supported = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011046 wol->wolopts = 0;
Joe Perches63c3a662011-04-26 08:12:10 +000011047 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011048 wol->wolopts = WAKE_MAGIC;
11049 memset(&wol->sopass, 0, sizeof(wol->sopass));
11050}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011051
Linus Torvalds1da177e2005-04-16 15:20:36 -070011052static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11053{
11054 struct tg3 *tp = netdev_priv(dev);
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070011055 struct device *dp = &tp->pdev->dev;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011056
Linus Torvalds1da177e2005-04-16 15:20:36 -070011057 if (wol->wolopts & ~WAKE_MAGIC)
11058 return -EINVAL;
11059 if ((wol->wolopts & WAKE_MAGIC) &&
Joe Perches63c3a662011-04-26 08:12:10 +000011060 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011061 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011062
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000011063 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
11064
David S. Millerf47c11e2005-06-24 20:18:35 -070011065 spin_lock_bh(&tp->lock);
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000011066 if (device_may_wakeup(dp))
Joe Perches63c3a662011-04-26 08:12:10 +000011067 tg3_flag_set(tp, WOL_ENABLE);
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000011068 else
Joe Perches63c3a662011-04-26 08:12:10 +000011069 tg3_flag_clear(tp, WOL_ENABLE);
David S. Millerf47c11e2005-06-24 20:18:35 -070011070 spin_unlock_bh(&tp->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011071
Linus Torvalds1da177e2005-04-16 15:20:36 -070011072 return 0;
11073}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011074
Linus Torvalds1da177e2005-04-16 15:20:36 -070011075static u32 tg3_get_msglevel(struct net_device *dev)
11076{
11077 struct tg3 *tp = netdev_priv(dev);
11078 return tp->msg_enable;
11079}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011080
Linus Torvalds1da177e2005-04-16 15:20:36 -070011081static void tg3_set_msglevel(struct net_device *dev, u32 value)
11082{
11083 struct tg3 *tp = netdev_priv(dev);
11084 tp->msg_enable = value;
11085}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011086
Linus Torvalds1da177e2005-04-16 15:20:36 -070011087static int tg3_nway_reset(struct net_device *dev)
11088{
11089 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011090 int r;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011091
Linus Torvalds1da177e2005-04-16 15:20:36 -070011092 if (!netif_running(dev))
11093 return -EAGAIN;
11094
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011095 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Michael Chanc94e3942005-09-27 12:12:42 -070011096 return -EINVAL;
11097
Joe Perches63c3a662011-04-26 08:12:10 +000011098 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011099 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011100 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000011101 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011102 } else {
11103 u32 bmcr;
11104
11105 spin_lock_bh(&tp->lock);
11106 r = -EINVAL;
11107 tg3_readphy(tp, MII_BMCR, &bmcr);
11108 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
11109 ((bmcr & BMCR_ANENABLE) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011110 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011111 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
11112 BMCR_ANENABLE);
11113 r = 0;
11114 }
11115 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011116 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011117
Linus Torvalds1da177e2005-04-16 15:20:36 -070011118 return r;
11119}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011120
Linus Torvalds1da177e2005-04-16 15:20:36 -070011121static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11122{
11123 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011124
Matt Carlson2c49a442010-09-30 10:34:35 +000011125 ering->rx_max_pending = tp->rx_std_ring_mask;
Joe Perches63c3a662011-04-26 08:12:10 +000011126 if (tg3_flag(tp, JUMBO_RING_ENABLE))
Matt Carlson2c49a442010-09-30 10:34:35 +000011127 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
Michael Chan4f81c322006-03-20 21:33:42 -080011128 else
11129 ering->rx_jumbo_max_pending = 0;
11130
11131 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011132
11133 ering->rx_pending = tp->rx_pending;
Joe Perches63c3a662011-04-26 08:12:10 +000011134 if (tg3_flag(tp, JUMBO_RING_ENABLE))
Michael Chan4f81c322006-03-20 21:33:42 -080011135 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
11136 else
11137 ering->rx_jumbo_pending = 0;
11138
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011139 ering->tx_pending = tp->napi[0].tx_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011140}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011141
Linus Torvalds1da177e2005-04-16 15:20:36 -070011142static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11143{
11144 struct tg3 *tp = netdev_priv(dev);
Matt Carlson646c9ed2009-09-01 12:58:41 +000011145 int i, irq_sync = 0, err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011146
Matt Carlson2c49a442010-09-30 10:34:35 +000011147 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
11148 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
Michael Chanbc3a9252006-10-18 20:55:18 -070011149 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
11150 (ering->tx_pending <= MAX_SKB_FRAGS) ||
Joe Perches63c3a662011-04-26 08:12:10 +000011151 (tg3_flag(tp, TSO_BUG) &&
Michael Chanbc3a9252006-10-18 20:55:18 -070011152 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011153 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011154
Michael Chanbbe832c2005-06-24 20:20:04 -070011155 if (netif_running(dev)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011156 tg3_phy_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011157 tg3_netif_stop(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070011158 irq_sync = 1;
11159 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070011160
Michael Chanbbe832c2005-06-24 20:20:04 -070011161 tg3_full_lock(tp, irq_sync);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011162
Linus Torvalds1da177e2005-04-16 15:20:36 -070011163 tp->rx_pending = ering->rx_pending;
11164
Joe Perches63c3a662011-04-26 08:12:10 +000011165 if (tg3_flag(tp, MAX_RXPEND_64) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070011166 tp->rx_pending > 63)
11167 tp->rx_pending = 63;
11168 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
Matt Carlson646c9ed2009-09-01 12:58:41 +000011169
Matt Carlson6fd45cb2010-09-15 08:59:57 +000011170 for (i = 0; i < tp->irq_max; i++)
Matt Carlson646c9ed2009-09-01 12:58:41 +000011171 tp->napi[i].tx_pending = ering->tx_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011172
11173 if (netif_running(dev)) {
Michael Chan944d9802005-05-29 14:57:48 -070011174 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chanb9ec6c12006-07-25 16:37:27 -070011175 err = tg3_restart_hw(tp, 1);
11176 if (!err)
11177 tg3_netif_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011178 }
11179
David S. Millerf47c11e2005-06-24 20:18:35 -070011180 tg3_full_unlock(tp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011181
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011182 if (irq_sync && !err)
11183 tg3_phy_start(tp);
11184
Michael Chanb9ec6c12006-07-25 16:37:27 -070011185 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011186}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011187
Linus Torvalds1da177e2005-04-16 15:20:36 -070011188static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11189{
11190 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011191
Joe Perches63c3a662011-04-26 08:12:10 +000011192 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
Matt Carlson8d018622007-12-20 20:05:44 -080011193
Matt Carlson4a2db502011-12-08 14:40:17 +000011194 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
Matt Carlson8d018622007-12-20 20:05:44 -080011195 epause->rx_pause = 1;
11196 else
11197 epause->rx_pause = 0;
11198
Matt Carlson4a2db502011-12-08 14:40:17 +000011199 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
Matt Carlson8d018622007-12-20 20:05:44 -080011200 epause->tx_pause = 1;
11201 else
11202 epause->tx_pause = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011203}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011204
Linus Torvalds1da177e2005-04-16 15:20:36 -070011205static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11206{
11207 struct tg3 *tp = netdev_priv(dev);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011208 int err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011209
Joe Perches63c3a662011-04-26 08:12:10 +000011210 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson27121682010-02-17 15:16:57 +000011211 u32 newadv;
11212 struct phy_device *phydev;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011213
Matt Carlson27121682010-02-17 15:16:57 +000011214 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011215
Matt Carlson27121682010-02-17 15:16:57 +000011216 if (!(phydev->supported & SUPPORTED_Pause) ||
11217 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
Nicolas Kaiser2259dca2010-10-07 23:29:27 +000011218 (epause->rx_pause != epause->tx_pause)))
Matt Carlson27121682010-02-17 15:16:57 +000011219 return -EINVAL;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011220
Matt Carlson27121682010-02-17 15:16:57 +000011221 tp->link_config.flowctrl = 0;
11222 if (epause->rx_pause) {
11223 tp->link_config.flowctrl |= FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011224
Matt Carlson27121682010-02-17 15:16:57 +000011225 if (epause->tx_pause) {
Steve Glendinninge18ce342008-12-16 02:00:00 -080011226 tp->link_config.flowctrl |= FLOW_CTRL_TX;
Matt Carlson27121682010-02-17 15:16:57 +000011227 newadv = ADVERTISED_Pause;
11228 } else
11229 newadv = ADVERTISED_Pause |
11230 ADVERTISED_Asym_Pause;
11231 } else if (epause->tx_pause) {
11232 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11233 newadv = ADVERTISED_Asym_Pause;
11234 } else
11235 newadv = 0;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011236
Matt Carlson27121682010-02-17 15:16:57 +000011237 if (epause->autoneg)
Joe Perches63c3a662011-04-26 08:12:10 +000011238 tg3_flag_set(tp, PAUSE_AUTONEG);
Matt Carlson27121682010-02-17 15:16:57 +000011239 else
Joe Perches63c3a662011-04-26 08:12:10 +000011240 tg3_flag_clear(tp, PAUSE_AUTONEG);
Matt Carlson27121682010-02-17 15:16:57 +000011241
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011242 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson27121682010-02-17 15:16:57 +000011243 u32 oldadv = phydev->advertising &
11244 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
11245 if (oldadv != newadv) {
11246 phydev->advertising &=
11247 ~(ADVERTISED_Pause |
11248 ADVERTISED_Asym_Pause);
11249 phydev->advertising |= newadv;
11250 if (phydev->autoneg) {
11251 /*
11252 * Always renegotiate the link to
11253 * inform our link partner of our
11254 * flow control settings, even if the
11255 * flow control is forced. Let
11256 * tg3_adjust_link() do the final
11257 * flow control setup.
11258 */
11259 return phy_start_aneg(phydev);
11260 }
11261 }
11262
11263 if (!epause->autoneg)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011264 tg3_setup_flow_control(tp, 0, 0);
Matt Carlson27121682010-02-17 15:16:57 +000011265 } else {
Matt Carlsonc6700ce2012-02-13 15:20:15 +000011266 tp->link_config.advertising &=
Matt Carlson27121682010-02-17 15:16:57 +000011267 ~(ADVERTISED_Pause |
11268 ADVERTISED_Asym_Pause);
Matt Carlsonc6700ce2012-02-13 15:20:15 +000011269 tp->link_config.advertising |= newadv;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011270 }
11271 } else {
11272 int irq_sync = 0;
11273
11274 if (netif_running(dev)) {
11275 tg3_netif_stop(tp);
11276 irq_sync = 1;
11277 }
11278
11279 tg3_full_lock(tp, irq_sync);
11280
11281 if (epause->autoneg)
Joe Perches63c3a662011-04-26 08:12:10 +000011282 tg3_flag_set(tp, PAUSE_AUTONEG);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011283 else
Joe Perches63c3a662011-04-26 08:12:10 +000011284 tg3_flag_clear(tp, PAUSE_AUTONEG);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011285 if (epause->rx_pause)
Steve Glendinninge18ce342008-12-16 02:00:00 -080011286 tp->link_config.flowctrl |= FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011287 else
Steve Glendinninge18ce342008-12-16 02:00:00 -080011288 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011289 if (epause->tx_pause)
Steve Glendinninge18ce342008-12-16 02:00:00 -080011290 tp->link_config.flowctrl |= FLOW_CTRL_TX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011291 else
Steve Glendinninge18ce342008-12-16 02:00:00 -080011292 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011293
11294 if (netif_running(dev)) {
11295 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11296 err = tg3_restart_hw(tp, 1);
11297 if (!err)
11298 tg3_netif_start(tp);
11299 }
11300
11301 tg3_full_unlock(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070011302 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070011303
Michael Chanb9ec6c12006-07-25 16:37:27 -070011304 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011305}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011306
Matt Carlsonde6f31e2010-04-12 06:58:30 +000011307static int tg3_get_sset_count(struct net_device *dev, int sset)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011308{
Jeff Garzikb9f2c042007-10-03 18:07:32 -070011309 switch (sset) {
11310 case ETH_SS_TEST:
11311 return TG3_NUM_TEST;
11312 case ETH_SS_STATS:
11313 return TG3_NUM_STATS;
11314 default:
11315 return -EOPNOTSUPP;
11316 }
Michael Chan4cafd3f2005-05-29 14:56:34 -070011317}
11318
Matt Carlson90415472011-12-16 13:33:23 +000011319static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
11320 u32 *rules __always_unused)
11321{
11322 struct tg3 *tp = netdev_priv(dev);
11323
11324 if (!tg3_flag(tp, SUPPORT_MSIX))
11325 return -EOPNOTSUPP;
11326
11327 switch (info->cmd) {
11328 case ETHTOOL_GRXRINGS:
11329 if (netif_running(tp->dev))
Michael Chan91024262012-09-28 07:12:38 +000011330 info->data = tp->rxq_cnt;
Matt Carlson90415472011-12-16 13:33:23 +000011331 else {
11332 info->data = num_online_cpus();
Michael Chan91024262012-09-28 07:12:38 +000011333 if (info->data > TG3_RSS_MAX_NUM_QS)
11334 info->data = TG3_RSS_MAX_NUM_QS;
Matt Carlson90415472011-12-16 13:33:23 +000011335 }
11336
11337 /* The first interrupt vector only
11338 * handles link interrupts.
11339 */
11340 info->data -= 1;
11341 return 0;
11342
11343 default:
11344 return -EOPNOTSUPP;
11345 }
11346}
11347
11348static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
11349{
11350 u32 size = 0;
11351 struct tg3 *tp = netdev_priv(dev);
11352
11353 if (tg3_flag(tp, SUPPORT_MSIX))
11354 size = TG3_RSS_INDIR_TBL_SIZE;
11355
11356 return size;
11357}
11358
11359static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
11360{
11361 struct tg3 *tp = netdev_priv(dev);
11362 int i;
11363
11364 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
11365 indir[i] = tp->rss_ind_tbl[i];
11366
11367 return 0;
11368}
11369
11370static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
11371{
11372 struct tg3 *tp = netdev_priv(dev);
11373 size_t i;
11374
11375 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
11376 tp->rss_ind_tbl[i] = indir[i];
11377
11378 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
11379 return 0;
11380
11381 /* It is legal to write the indirection
11382 * table while the device is running.
11383 */
11384 tg3_full_lock(tp, 0);
11385 tg3_rss_write_indir_tbl(tp);
11386 tg3_full_unlock(tp);
11387
11388 return 0;
11389}
11390
Michael Chan09681692012-09-28 07:12:42 +000011391static void tg3_get_channels(struct net_device *dev,
11392 struct ethtool_channels *channel)
11393{
11394 struct tg3 *tp = netdev_priv(dev);
11395 u32 deflt_qs = netif_get_num_default_rss_queues();
11396
11397 channel->max_rx = tp->rxq_max;
11398 channel->max_tx = tp->txq_max;
11399
11400 if (netif_running(dev)) {
11401 channel->rx_count = tp->rxq_cnt;
11402 channel->tx_count = tp->txq_cnt;
11403 } else {
11404 if (tp->rxq_req)
11405 channel->rx_count = tp->rxq_req;
11406 else
11407 channel->rx_count = min(deflt_qs, tp->rxq_max);
11408
11409 if (tp->txq_req)
11410 channel->tx_count = tp->txq_req;
11411 else
11412 channel->tx_count = min(deflt_qs, tp->txq_max);
11413 }
11414}
11415
11416static int tg3_set_channels(struct net_device *dev,
11417 struct ethtool_channels *channel)
11418{
11419 struct tg3 *tp = netdev_priv(dev);
11420
11421 if (!tg3_flag(tp, SUPPORT_MSIX))
11422 return -EOPNOTSUPP;
11423
11424 if (channel->rx_count > tp->rxq_max ||
11425 channel->tx_count > tp->txq_max)
11426 return -EINVAL;
11427
11428 tp->rxq_req = channel->rx_count;
11429 tp->txq_req = channel->tx_count;
11430
11431 if (!netif_running(dev))
11432 return 0;
11433
11434 tg3_stop(tp);
11435
11436 netif_carrier_off(dev);
11437
11438 tg3_start(tp, true, false);
11439
11440 return 0;
11441}
11442
Matt Carlsonde6f31e2010-04-12 06:58:30 +000011443static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011444{
11445 switch (stringset) {
11446 case ETH_SS_STATS:
11447 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
11448 break;
Michael Chan4cafd3f2005-05-29 14:56:34 -070011449 case ETH_SS_TEST:
11450 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
11451 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011452 default:
11453 WARN_ON(1); /* we need a WARN() */
11454 break;
11455 }
11456}
11457
stephen hemminger81b87092011-04-04 08:43:50 +000011458static int tg3_set_phys_id(struct net_device *dev,
11459 enum ethtool_phys_id_state state)
Michael Chan4009a932005-09-05 17:52:54 -070011460{
11461 struct tg3 *tp = netdev_priv(dev);
Michael Chan4009a932005-09-05 17:52:54 -070011462
11463 if (!netif_running(tp->dev))
11464 return -EAGAIN;
11465
stephen hemminger81b87092011-04-04 08:43:50 +000011466 switch (state) {
11467 case ETHTOOL_ID_ACTIVE:
Allan, Bruce Wfce55922011-04-13 13:09:10 +000011468 return 1; /* cycle on/off once per second */
Michael Chan4009a932005-09-05 17:52:54 -070011469
stephen hemminger81b87092011-04-04 08:43:50 +000011470 case ETHTOOL_ID_ON:
11471 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11472 LED_CTRL_1000MBPS_ON |
11473 LED_CTRL_100MBPS_ON |
11474 LED_CTRL_10MBPS_ON |
11475 LED_CTRL_TRAFFIC_OVERRIDE |
11476 LED_CTRL_TRAFFIC_BLINK |
11477 LED_CTRL_TRAFFIC_LED);
11478 break;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011479
stephen hemminger81b87092011-04-04 08:43:50 +000011480 case ETHTOOL_ID_OFF:
11481 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11482 LED_CTRL_TRAFFIC_OVERRIDE);
11483 break;
Michael Chan4009a932005-09-05 17:52:54 -070011484
stephen hemminger81b87092011-04-04 08:43:50 +000011485 case ETHTOOL_ID_INACTIVE:
11486 tw32(MAC_LED_CTRL, tp->led_ctrl);
11487 break;
Michael Chan4009a932005-09-05 17:52:54 -070011488 }
stephen hemminger81b87092011-04-04 08:43:50 +000011489
Michael Chan4009a932005-09-05 17:52:54 -070011490 return 0;
11491}
11492
Matt Carlsonde6f31e2010-04-12 06:58:30 +000011493static void tg3_get_ethtool_stats(struct net_device *dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011494 struct ethtool_stats *estats, u64 *tmp_stats)
11495{
11496 struct tg3 *tp = netdev_priv(dev);
Matt Carlson0e6c9da2011-12-08 14:40:13 +000011497
Matt Carlsonb546e462012-02-13 15:20:09 +000011498 if (tp->hw_stats)
11499 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
11500 else
11501 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
Linus Torvalds1da177e2005-04-16 15:20:36 -070011502}
11503
Matt Carlson535a4902011-07-20 10:20:56 +000011504static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
Matt Carlsonc3e94502011-04-13 11:05:08 +000011505{
11506 int i;
11507 __be32 *buf;
11508 u32 offset = 0, len = 0;
11509 u32 magic, val;
11510
Joe Perches63c3a662011-04-26 08:12:10 +000011511 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
Matt Carlsonc3e94502011-04-13 11:05:08 +000011512 return NULL;
11513
11514 if (magic == TG3_EEPROM_MAGIC) {
11515 for (offset = TG3_NVM_DIR_START;
11516 offset < TG3_NVM_DIR_END;
11517 offset += TG3_NVM_DIRENT_SIZE) {
11518 if (tg3_nvram_read(tp, offset, &val))
11519 return NULL;
11520
11521 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
11522 TG3_NVM_DIRTYPE_EXTVPD)
11523 break;
11524 }
11525
11526 if (offset != TG3_NVM_DIR_END) {
11527 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
11528 if (tg3_nvram_read(tp, offset + 4, &offset))
11529 return NULL;
11530
11531 offset = tg3_nvram_logical_addr(tp, offset);
11532 }
11533 }
11534
11535 if (!offset || !len) {
11536 offset = TG3_NVM_VPD_OFF;
11537 len = TG3_NVM_VPD_LEN;
11538 }
11539
11540 buf = kmalloc(len, GFP_KERNEL);
11541 if (buf == NULL)
11542 return NULL;
11543
11544 if (magic == TG3_EEPROM_MAGIC) {
11545 for (i = 0; i < len; i += 4) {
11546 /* The data is in little-endian format in NVRAM.
11547 * Use the big-endian read routines to preserve
11548 * the byte order as it exists in NVRAM.
11549 */
11550 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
11551 goto error;
11552 }
11553 } else {
11554 u8 *ptr;
11555 ssize_t cnt;
11556 unsigned int pos = 0;
11557
11558 ptr = (u8 *)&buf[0];
11559 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
11560 cnt = pci_read_vpd(tp->pdev, pos,
11561 len - pos, ptr);
11562 if (cnt == -ETIMEDOUT || cnt == -EINTR)
11563 cnt = 0;
11564 else if (cnt < 0)
11565 goto error;
11566 }
11567 if (pos != len)
11568 goto error;
11569 }
11570
Matt Carlson535a4902011-07-20 10:20:56 +000011571 *vpdlen = len;
11572
Matt Carlsonc3e94502011-04-13 11:05:08 +000011573 return buf;
11574
11575error:
11576 kfree(buf);
11577 return NULL;
11578}
11579
Michael Chan566f86a2005-05-29 14:56:58 -070011580#define NVRAM_TEST_SIZE 0x100
Matt Carlsona5767de2007-11-12 21:10:58 -080011581#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
11582#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
11583#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
Matt Carlson727a6d92011-06-13 13:38:58 +000011584#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
11585#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
Matt Carlsonbda18fa2011-07-20 10:20:57 +000011586#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
Michael Chanb16250e2006-09-27 16:10:14 -070011587#define NVRAM_SELFBOOT_HW_SIZE 0x20
11588#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
Michael Chan566f86a2005-05-29 14:56:58 -070011589
11590static int tg3_test_nvram(struct tg3 *tp)
11591{
Matt Carlson535a4902011-07-20 10:20:56 +000011592 u32 csum, magic, len;
Matt Carlsona9dc5292009-02-25 14:25:30 +000011593 __be32 *buf;
Andy Gospodarekab0049b2007-09-06 20:42:14 +010011594 int i, j, k, err = 0, size;
Michael Chan566f86a2005-05-29 14:56:58 -070011595
Joe Perches63c3a662011-04-26 08:12:10 +000011596 if (tg3_flag(tp, NO_NVRAM))
Matt Carlsondf259d82009-04-20 06:57:14 +000011597 return 0;
11598
Matt Carlsone4f34112009-02-25 14:25:00 +000011599 if (tg3_nvram_read(tp, 0, &magic) != 0)
Michael Chan1b277772006-03-20 22:27:48 -080011600 return -EIO;
11601
Michael Chan1b277772006-03-20 22:27:48 -080011602 if (magic == TG3_EEPROM_MAGIC)
11603 size = NVRAM_TEST_SIZE;
Michael Chanb16250e2006-09-27 16:10:14 -070011604 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
Matt Carlsona5767de2007-11-12 21:10:58 -080011605 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
11606 TG3_EEPROM_SB_FORMAT_1) {
11607 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
11608 case TG3_EEPROM_SB_REVISION_0:
11609 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
11610 break;
11611 case TG3_EEPROM_SB_REVISION_2:
11612 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
11613 break;
11614 case TG3_EEPROM_SB_REVISION_3:
11615 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
11616 break;
Matt Carlson727a6d92011-06-13 13:38:58 +000011617 case TG3_EEPROM_SB_REVISION_4:
11618 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
11619 break;
11620 case TG3_EEPROM_SB_REVISION_5:
11621 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
11622 break;
11623 case TG3_EEPROM_SB_REVISION_6:
11624 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
11625 break;
Matt Carlsona5767de2007-11-12 21:10:58 -080011626 default:
Matt Carlson727a6d92011-06-13 13:38:58 +000011627 return -EIO;
Matt Carlsona5767de2007-11-12 21:10:58 -080011628 }
11629 } else
Michael Chan1b277772006-03-20 22:27:48 -080011630 return 0;
Michael Chanb16250e2006-09-27 16:10:14 -070011631 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11632 size = NVRAM_SELFBOOT_HW_SIZE;
11633 else
Michael Chan1b277772006-03-20 22:27:48 -080011634 return -EIO;
11635
11636 buf = kmalloc(size, GFP_KERNEL);
Michael Chan566f86a2005-05-29 14:56:58 -070011637 if (buf == NULL)
11638 return -ENOMEM;
11639
Michael Chan1b277772006-03-20 22:27:48 -080011640 err = -EIO;
11641 for (i = 0, j = 0; i < size; i += 4, j++) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000011642 err = tg3_nvram_read_be32(tp, i, &buf[j]);
11643 if (err)
Michael Chan566f86a2005-05-29 14:56:58 -070011644 break;
Michael Chan566f86a2005-05-29 14:56:58 -070011645 }
Michael Chan1b277772006-03-20 22:27:48 -080011646 if (i < size)
Michael Chan566f86a2005-05-29 14:56:58 -070011647 goto out;
11648
Michael Chan1b277772006-03-20 22:27:48 -080011649 /* Selfboot format */
Matt Carlsona9dc5292009-02-25 14:25:30 +000011650 magic = be32_to_cpu(buf[0]);
Al Virob9fc7dc2007-12-17 22:59:57 -080011651 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
Michael Chanb16250e2006-09-27 16:10:14 -070011652 TG3_EEPROM_MAGIC_FW) {
Michael Chan1b277772006-03-20 22:27:48 -080011653 u8 *buf8 = (u8 *) buf, csum8 = 0;
11654
Al Virob9fc7dc2007-12-17 22:59:57 -080011655 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
Matt Carlsona5767de2007-11-12 21:10:58 -080011656 TG3_EEPROM_SB_REVISION_2) {
11657 /* For rev 2, the csum doesn't include the MBA. */
11658 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
11659 csum8 += buf8[i];
11660 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
11661 csum8 += buf8[i];
11662 } else {
11663 for (i = 0; i < size; i++)
11664 csum8 += buf8[i];
11665 }
Michael Chan1b277772006-03-20 22:27:48 -080011666
Adrian Bunkad96b482006-04-05 22:21:04 -070011667 if (csum8 == 0) {
11668 err = 0;
11669 goto out;
11670 }
11671
11672 err = -EIO;
11673 goto out;
Michael Chan1b277772006-03-20 22:27:48 -080011674 }
Michael Chan566f86a2005-05-29 14:56:58 -070011675
Al Virob9fc7dc2007-12-17 22:59:57 -080011676 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
Michael Chanb16250e2006-09-27 16:10:14 -070011677 TG3_EEPROM_MAGIC_HW) {
11678 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
Matt Carlsona9dc5292009-02-25 14:25:30 +000011679 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
Michael Chanb16250e2006-09-27 16:10:14 -070011680 u8 *buf8 = (u8 *) buf;
Michael Chanb16250e2006-09-27 16:10:14 -070011681
11682 /* Separate the parity bits and the data bytes. */
11683 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
11684 if ((i == 0) || (i == 8)) {
11685 int l;
11686 u8 msk;
11687
11688 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
11689 parity[k++] = buf8[i] & msk;
11690 i++;
Matt Carlson859a588792010-04-05 10:19:28 +000011691 } else if (i == 16) {
Michael Chanb16250e2006-09-27 16:10:14 -070011692 int l;
11693 u8 msk;
11694
11695 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
11696 parity[k++] = buf8[i] & msk;
11697 i++;
11698
11699 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
11700 parity[k++] = buf8[i] & msk;
11701 i++;
11702 }
11703 data[j++] = buf8[i];
11704 }
11705
11706 err = -EIO;
11707 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
11708 u8 hw8 = hweight8(data[i]);
11709
11710 if ((hw8 & 0x1) && parity[i])
11711 goto out;
11712 else if (!(hw8 & 0x1) && !parity[i])
11713 goto out;
11714 }
11715 err = 0;
11716 goto out;
11717 }
11718
Matt Carlson01c3a392011-03-09 16:58:20 +000011719 err = -EIO;
11720
Michael Chan566f86a2005-05-29 14:56:58 -070011721 /* Bootstrap checksum at offset 0x10 */
11722 csum = calc_crc((unsigned char *) buf, 0x10);
Matt Carlson01c3a392011-03-09 16:58:20 +000011723 if (csum != le32_to_cpu(buf[0x10/4]))
Michael Chan566f86a2005-05-29 14:56:58 -070011724 goto out;
11725
11726 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11727 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
Matt Carlson01c3a392011-03-09 16:58:20 +000011728 if (csum != le32_to_cpu(buf[0xfc/4]))
Matt Carlsona9dc5292009-02-25 14:25:30 +000011729 goto out;
Michael Chan566f86a2005-05-29 14:56:58 -070011730
Matt Carlsonc3e94502011-04-13 11:05:08 +000011731 kfree(buf);
11732
Matt Carlson535a4902011-07-20 10:20:56 +000011733 buf = tg3_vpd_readblock(tp, &len);
Matt Carlsonc3e94502011-04-13 11:05:08 +000011734 if (!buf)
11735 return -ENOMEM;
Matt Carlsond4894f32011-03-09 16:58:21 +000011736
Matt Carlson535a4902011-07-20 10:20:56 +000011737 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
Matt Carlsond4894f32011-03-09 16:58:21 +000011738 if (i > 0) {
11739 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11740 if (j < 0)
11741 goto out;
11742
Matt Carlson535a4902011-07-20 10:20:56 +000011743 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
Matt Carlsond4894f32011-03-09 16:58:21 +000011744 goto out;
11745
11746 i += PCI_VPD_LRDT_TAG_SIZE;
11747 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11748 PCI_VPD_RO_KEYWORD_CHKSUM);
11749 if (j > 0) {
11750 u8 csum8 = 0;
11751
11752 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11753
11754 for (i = 0; i <= j; i++)
11755 csum8 += ((u8 *)buf)[i];
11756
11757 if (csum8)
11758 goto out;
11759 }
11760 }
11761
Michael Chan566f86a2005-05-29 14:56:58 -070011762 err = 0;
11763
11764out:
11765 kfree(buf);
11766 return err;
11767}
11768
Michael Chanca430072005-05-29 14:57:23 -070011769#define TG3_SERDES_TIMEOUT_SEC 2
11770#define TG3_COPPER_TIMEOUT_SEC 6
11771
11772static int tg3_test_link(struct tg3 *tp)
11773{
11774 int i, max;
11775
11776 if (!netif_running(tp->dev))
11777 return -ENODEV;
11778
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011779 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Michael Chanca430072005-05-29 14:57:23 -070011780 max = TG3_SERDES_TIMEOUT_SEC;
11781 else
11782 max = TG3_COPPER_TIMEOUT_SEC;
11783
11784 for (i = 0; i < max; i++) {
11785 if (netif_carrier_ok(tp->dev))
11786 return 0;
11787
11788 if (msleep_interruptible(1000))
11789 break;
11790 }
11791
11792 return -EIO;
11793}
11794
Michael Chana71116d2005-05-29 14:58:11 -070011795/* Only test the commonly used registers */
David S. Miller30ca3e32006-03-20 23:02:36 -080011796static int tg3_test_registers(struct tg3 *tp)
Michael Chana71116d2005-05-29 14:58:11 -070011797{
Michael Chanb16250e2006-09-27 16:10:14 -070011798 int i, is_5705, is_5750;
Michael Chana71116d2005-05-29 14:58:11 -070011799 u32 offset, read_mask, write_mask, val, save_val, read_val;
11800 static struct {
11801 u16 offset;
11802 u16 flags;
11803#define TG3_FL_5705 0x1
11804#define TG3_FL_NOT_5705 0x2
11805#define TG3_FL_NOT_5788 0x4
Michael Chanb16250e2006-09-27 16:10:14 -070011806#define TG3_FL_NOT_5750 0x8
Michael Chana71116d2005-05-29 14:58:11 -070011807 u32 read_mask;
11808 u32 write_mask;
11809 } reg_tbl[] = {
11810 /* MAC Control Registers */
11811 { MAC_MODE, TG3_FL_NOT_5705,
11812 0x00000000, 0x00ef6f8c },
11813 { MAC_MODE, TG3_FL_5705,
11814 0x00000000, 0x01ef6b8c },
11815 { MAC_STATUS, TG3_FL_NOT_5705,
11816 0x03800107, 0x00000000 },
11817 { MAC_STATUS, TG3_FL_5705,
11818 0x03800100, 0x00000000 },
11819 { MAC_ADDR_0_HIGH, 0x0000,
11820 0x00000000, 0x0000ffff },
11821 { MAC_ADDR_0_LOW, 0x0000,
Matt Carlsonc6cdf432010-04-05 10:19:26 +000011822 0x00000000, 0xffffffff },
Michael Chana71116d2005-05-29 14:58:11 -070011823 { MAC_RX_MTU_SIZE, 0x0000,
11824 0x00000000, 0x0000ffff },
11825 { MAC_TX_MODE, 0x0000,
11826 0x00000000, 0x00000070 },
11827 { MAC_TX_LENGTHS, 0x0000,
11828 0x00000000, 0x00003fff },
11829 { MAC_RX_MODE, TG3_FL_NOT_5705,
11830 0x00000000, 0x000007fc },
11831 { MAC_RX_MODE, TG3_FL_5705,
11832 0x00000000, 0x000007dc },
11833 { MAC_HASH_REG_0, 0x0000,
11834 0x00000000, 0xffffffff },
11835 { MAC_HASH_REG_1, 0x0000,
11836 0x00000000, 0xffffffff },
11837 { MAC_HASH_REG_2, 0x0000,
11838 0x00000000, 0xffffffff },
11839 { MAC_HASH_REG_3, 0x0000,
11840 0x00000000, 0xffffffff },
11841
11842 /* Receive Data and Receive BD Initiator Control Registers. */
11843 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11844 0x00000000, 0xffffffff },
11845 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11846 0x00000000, 0xffffffff },
11847 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11848 0x00000000, 0x00000003 },
11849 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11850 0x00000000, 0xffffffff },
11851 { RCVDBDI_STD_BD+0, 0x0000,
11852 0x00000000, 0xffffffff },
11853 { RCVDBDI_STD_BD+4, 0x0000,
11854 0x00000000, 0xffffffff },
11855 { RCVDBDI_STD_BD+8, 0x0000,
11856 0x00000000, 0xffff0002 },
11857 { RCVDBDI_STD_BD+0xc, 0x0000,
11858 0x00000000, 0xffffffff },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011859
Michael Chana71116d2005-05-29 14:58:11 -070011860 /* Receive BD Initiator Control Registers. */
11861 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11862 0x00000000, 0xffffffff },
11863 { RCVBDI_STD_THRESH, TG3_FL_5705,
11864 0x00000000, 0x000003ff },
11865 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11866 0x00000000, 0xffffffff },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011867
Michael Chana71116d2005-05-29 14:58:11 -070011868 /* Host Coalescing Control Registers. */
11869 { HOSTCC_MODE, TG3_FL_NOT_5705,
11870 0x00000000, 0x00000004 },
11871 { HOSTCC_MODE, TG3_FL_5705,
11872 0x00000000, 0x000000f6 },
11873 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11874 0x00000000, 0xffffffff },
11875 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11876 0x00000000, 0x000003ff },
11877 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11878 0x00000000, 0xffffffff },
11879 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11880 0x00000000, 0x000003ff },
11881 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11882 0x00000000, 0xffffffff },
11883 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11884 0x00000000, 0x000000ff },
11885 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11886 0x00000000, 0xffffffff },
11887 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11888 0x00000000, 0x000000ff },
11889 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11890 0x00000000, 0xffffffff },
11891 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11892 0x00000000, 0xffffffff },
11893 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11894 0x00000000, 0xffffffff },
11895 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11896 0x00000000, 0x000000ff },
11897 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11898 0x00000000, 0xffffffff },
11899 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11900 0x00000000, 0x000000ff },
11901 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11902 0x00000000, 0xffffffff },
11903 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11904 0x00000000, 0xffffffff },
11905 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11906 0x00000000, 0xffffffff },
11907 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11908 0x00000000, 0xffffffff },
11909 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11910 0x00000000, 0xffffffff },
11911 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11912 0xffffffff, 0x00000000 },
11913 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11914 0xffffffff, 0x00000000 },
11915
11916 /* Buffer Manager Control Registers. */
Michael Chanb16250e2006-09-27 16:10:14 -070011917 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
Michael Chana71116d2005-05-29 14:58:11 -070011918 0x00000000, 0x007fff80 },
Michael Chanb16250e2006-09-27 16:10:14 -070011919 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
Michael Chana71116d2005-05-29 14:58:11 -070011920 0x00000000, 0x007fffff },
11921 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11922 0x00000000, 0x0000003f },
11923 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11924 0x00000000, 0x000001ff },
11925 { BUFMGR_MB_HIGH_WATER, 0x0000,
11926 0x00000000, 0x000001ff },
11927 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11928 0xffffffff, 0x00000000 },
11929 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11930 0xffffffff, 0x00000000 },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011931
Michael Chana71116d2005-05-29 14:58:11 -070011932 /* Mailbox Registers */
11933 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11934 0x00000000, 0x000001ff },
11935 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11936 0x00000000, 0x000001ff },
11937 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11938 0x00000000, 0x000007ff },
11939 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11940 0x00000000, 0x000001ff },
11941
11942 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11943 };
11944
Michael Chanb16250e2006-09-27 16:10:14 -070011945 is_5705 = is_5750 = 0;
Joe Perches63c3a662011-04-26 08:12:10 +000011946 if (tg3_flag(tp, 5705_PLUS)) {
Michael Chana71116d2005-05-29 14:58:11 -070011947 is_5705 = 1;
Joe Perches63c3a662011-04-26 08:12:10 +000011948 if (tg3_flag(tp, 5750_PLUS))
Michael Chanb16250e2006-09-27 16:10:14 -070011949 is_5750 = 1;
11950 }
Michael Chana71116d2005-05-29 14:58:11 -070011951
11952 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11953 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11954 continue;
11955
11956 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11957 continue;
11958
Joe Perches63c3a662011-04-26 08:12:10 +000011959 if (tg3_flag(tp, IS_5788) &&
Michael Chana71116d2005-05-29 14:58:11 -070011960 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11961 continue;
11962
Michael Chanb16250e2006-09-27 16:10:14 -070011963 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11964 continue;
11965
Michael Chana71116d2005-05-29 14:58:11 -070011966 offset = (u32) reg_tbl[i].offset;
11967 read_mask = reg_tbl[i].read_mask;
11968 write_mask = reg_tbl[i].write_mask;
11969
11970 /* Save the original register content */
11971 save_val = tr32(offset);
11972
11973 /* Determine the read-only value. */
11974 read_val = save_val & read_mask;
11975
11976 /* Write zero to the register, then make sure the read-only bits
11977 * are not changed and the read/write bits are all zeros.
11978 */
11979 tw32(offset, 0);
11980
11981 val = tr32(offset);
11982
11983 /* Test the read-only and read/write bits. */
11984 if (((val & read_mask) != read_val) || (val & write_mask))
11985 goto out;
11986
11987 /* Write ones to all the bits defined by RdMask and WrMask, then
11988 * make sure the read-only bits are not changed and the
11989 * read/write bits are all ones.
11990 */
11991 tw32(offset, read_mask | write_mask);
11992
11993 val = tr32(offset);
11994
11995 /* Test the read-only bits. */
11996 if ((val & read_mask) != read_val)
11997 goto out;
11998
11999 /* Test the read/write bits. */
12000 if ((val & write_mask) != write_mask)
12001 goto out;
12002
12003 tw32(offset, save_val);
12004 }
12005
12006 return 0;
12007
12008out:
Michael Chan9f88f292006-12-07 00:22:54 -080012009 if (netif_msg_hw(tp))
Matt Carlson2445e462010-04-05 10:19:21 +000012010 netdev_err(tp->dev,
12011 "Register test failed at offset %x\n", offset);
Michael Chana71116d2005-05-29 14:58:11 -070012012 tw32(offset, save_val);
12013 return -EIO;
12014}
12015
Michael Chan7942e1d2005-05-29 14:58:36 -070012016static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
12017{
Arjan van de Venf71e1302006-03-03 21:33:57 -050012018 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
Michael Chan7942e1d2005-05-29 14:58:36 -070012019 int i;
12020 u32 j;
12021
Alejandro Martinez Ruize9edda62007-10-15 03:37:43 +020012022 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
Michael Chan7942e1d2005-05-29 14:58:36 -070012023 for (j = 0; j < len; j += 4) {
12024 u32 val;
12025
12026 tg3_write_mem(tp, offset + j, test_pattern[i]);
12027 tg3_read_mem(tp, offset + j, &val);
12028 if (val != test_pattern[i])
12029 return -EIO;
12030 }
12031 }
12032 return 0;
12033}
12034
12035static int tg3_test_memory(struct tg3 *tp)
12036{
12037 static struct mem_entry {
12038 u32 offset;
12039 u32 len;
12040 } mem_tbl_570x[] = {
Michael Chan38690192005-12-19 16:27:28 -080012041 { 0x00000000, 0x00b50},
Michael Chan7942e1d2005-05-29 14:58:36 -070012042 { 0x00002000, 0x1c000},
12043 { 0xffffffff, 0x00000}
12044 }, mem_tbl_5705[] = {
12045 { 0x00000100, 0x0000c},
12046 { 0x00000200, 0x00008},
Michael Chan7942e1d2005-05-29 14:58:36 -070012047 { 0x00004000, 0x00800},
12048 { 0x00006000, 0x01000},
12049 { 0x00008000, 0x02000},
12050 { 0x00010000, 0x0e000},
12051 { 0xffffffff, 0x00000}
Michael Chan79f4d132006-03-20 22:28:57 -080012052 }, mem_tbl_5755[] = {
12053 { 0x00000200, 0x00008},
12054 { 0x00004000, 0x00800},
12055 { 0x00006000, 0x00800},
12056 { 0x00008000, 0x02000},
12057 { 0x00010000, 0x0c000},
12058 { 0xffffffff, 0x00000}
Michael Chanb16250e2006-09-27 16:10:14 -070012059 }, mem_tbl_5906[] = {
12060 { 0x00000200, 0x00008},
12061 { 0x00004000, 0x00400},
12062 { 0x00006000, 0x00400},
12063 { 0x00008000, 0x01000},
12064 { 0x00010000, 0x01000},
12065 { 0xffffffff, 0x00000}
Matt Carlson8b5a6c42010-01-20 16:58:06 +000012066 }, mem_tbl_5717[] = {
12067 { 0x00000200, 0x00008},
12068 { 0x00010000, 0x0a000},
12069 { 0x00020000, 0x13c00},
12070 { 0xffffffff, 0x00000}
12071 }, mem_tbl_57765[] = {
12072 { 0x00000200, 0x00008},
12073 { 0x00004000, 0x00800},
12074 { 0x00006000, 0x09800},
12075 { 0x00010000, 0x0a000},
12076 { 0xffffffff, 0x00000}
Michael Chan7942e1d2005-05-29 14:58:36 -070012077 };
12078 struct mem_entry *mem_tbl;
12079 int err = 0;
12080 int i;
12081
Joe Perches63c3a662011-04-26 08:12:10 +000012082 if (tg3_flag(tp, 5717_PLUS))
Matt Carlson8b5a6c42010-01-20 16:58:06 +000012083 mem_tbl = mem_tbl_5717;
Matt Carlson55086ad2011-12-14 11:09:59 +000012084 else if (tg3_flag(tp, 57765_CLASS))
Matt Carlson8b5a6c42010-01-20 16:58:06 +000012085 mem_tbl = mem_tbl_57765;
Joe Perches63c3a662011-04-26 08:12:10 +000012086 else if (tg3_flag(tp, 5755_PLUS))
Matt Carlson321d32a2008-11-21 17:22:19 -080012087 mem_tbl = mem_tbl_5755;
12088 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12089 mem_tbl = mem_tbl_5906;
Joe Perches63c3a662011-04-26 08:12:10 +000012090 else if (tg3_flag(tp, 5705_PLUS))
Matt Carlson321d32a2008-11-21 17:22:19 -080012091 mem_tbl = mem_tbl_5705;
12092 else
Michael Chan7942e1d2005-05-29 14:58:36 -070012093 mem_tbl = mem_tbl_570x;
12094
12095 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
Matt Carlsonbe98da62010-07-11 09:31:46 +000012096 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
12097 if (err)
Michael Chan7942e1d2005-05-29 14:58:36 -070012098 break;
12099 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040012100
Michael Chan7942e1d2005-05-29 14:58:36 -070012101 return err;
12102}
12103
Matt Carlsonbb158d62011-04-25 12:42:47 +000012104#define TG3_TSO_MSS 500
12105
12106#define TG3_TSO_IP_HDR_LEN 20
12107#define TG3_TSO_TCP_HDR_LEN 20
12108#define TG3_TSO_TCP_OPT_LEN 12
12109
12110static const u8 tg3_tso_header[] = {
121110x08, 0x00,
121120x45, 0x00, 0x00, 0x00,
121130x00, 0x00, 0x40, 0x00,
121140x40, 0x06, 0x00, 0x00,
121150x0a, 0x00, 0x00, 0x01,
121160x0a, 0x00, 0x00, 0x02,
121170x0d, 0x00, 0xe0, 0x00,
121180x00, 0x00, 0x01, 0x00,
121190x00, 0x00, 0x02, 0x00,
121200x80, 0x10, 0x10, 0x00,
121210x14, 0x09, 0x00, 0x00,
121220x01, 0x01, 0x08, 0x0a,
121230x11, 0x11, 0x11, 0x11,
121240x11, 0x11, 0x11, 0x11,
12125};
Michael Chan9f40dea2005-09-05 17:53:06 -070012126
Matt Carlson28a45952011-08-19 13:58:22 +000012127static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
Michael Chanc76949a2005-05-29 14:58:59 -070012128{
Matt Carlson5e5a7f32011-08-19 13:58:21 +000012129 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
Matt Carlsonbb158d62011-04-25 12:42:47 +000012130 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
Matt Carlson84b67b22011-07-27 14:20:52 +000012131 u32 budget;
Eric Dumazet9205fd92011-11-18 06:47:01 +000012132 struct sk_buff *skb;
12133 u8 *tx_data, *rx_data;
Michael Chanc76949a2005-05-29 14:58:59 -070012134 dma_addr_t map;
12135 int num_pkts, tx_len, rx_len, i, err;
12136 struct tg3_rx_buffer_desc *desc;
Matt Carlson898a56f2009-08-28 14:02:40 +000012137 struct tg3_napi *tnapi, *rnapi;
Matt Carlson8fea32b2010-09-15 08:59:58 +000012138 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
Michael Chanc76949a2005-05-29 14:58:59 -070012139
Matt Carlsonc8873402010-02-12 14:47:11 +000012140 tnapi = &tp->napi[0];
12141 rnapi = &tp->napi[0];
Matt Carlson0c1d0e22009-09-01 13:16:33 +000012142 if (tp->irq_cnt > 1) {
Joe Perches63c3a662011-04-26 08:12:10 +000012143 if (tg3_flag(tp, ENABLE_RSS))
Matt Carlson1da85aa2010-09-30 10:34:34 +000012144 rnapi = &tp->napi[1];
Joe Perches63c3a662011-04-26 08:12:10 +000012145 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlsonc8873402010-02-12 14:47:11 +000012146 tnapi = &tp->napi[1];
Matt Carlson0c1d0e22009-09-01 13:16:33 +000012147 }
Matt Carlsonfd2ce372009-09-01 12:51:13 +000012148 coal_now = tnapi->coal_now | rnapi->coal_now;
Matt Carlson898a56f2009-08-28 14:02:40 +000012149
Michael Chanc76949a2005-05-29 14:58:59 -070012150 err = -EIO;
12151
Matt Carlson4852a862011-04-13 11:05:07 +000012152 tx_len = pktsz;
David S. Millera20e9c62006-07-31 22:38:16 -070012153 skb = netdev_alloc_skb(tp->dev, tx_len);
Jesper Juhla50bb7b2006-05-09 23:14:35 -070012154 if (!skb)
12155 return -ENOMEM;
12156
Michael Chanc76949a2005-05-29 14:58:59 -070012157 tx_data = skb_put(skb, tx_len);
12158 memcpy(tx_data, tp->dev->dev_addr, 6);
12159 memset(tx_data + 6, 0x0, 8);
12160
Matt Carlson4852a862011-04-13 11:05:07 +000012161 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
Michael Chanc76949a2005-05-29 14:58:59 -070012162
Matt Carlson28a45952011-08-19 13:58:22 +000012163 if (tso_loopback) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000012164 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
12165
12166 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
12167 TG3_TSO_TCP_OPT_LEN;
12168
12169 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
12170 sizeof(tg3_tso_header));
12171 mss = TG3_TSO_MSS;
12172
12173 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
12174 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
12175
12176 /* Set the total length field in the IP header */
12177 iph->tot_len = htons((u16)(mss + hdr_len));
12178
12179 base_flags = (TXD_FLAG_CPU_PRE_DMA |
12180 TXD_FLAG_CPU_POST_DMA);
12181
Joe Perches63c3a662011-04-26 08:12:10 +000012182 if (tg3_flag(tp, HW_TSO_1) ||
12183 tg3_flag(tp, HW_TSO_2) ||
12184 tg3_flag(tp, HW_TSO_3)) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000012185 struct tcphdr *th;
12186 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
12187 th = (struct tcphdr *)&tx_data[val];
12188 th->check = 0;
12189 } else
12190 base_flags |= TXD_FLAG_TCPUDP_CSUM;
12191
Joe Perches63c3a662011-04-26 08:12:10 +000012192 if (tg3_flag(tp, HW_TSO_3)) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000012193 mss |= (hdr_len & 0xc) << 12;
12194 if (hdr_len & 0x10)
12195 base_flags |= 0x00000010;
12196 base_flags |= (hdr_len & 0x3e0) << 5;
Joe Perches63c3a662011-04-26 08:12:10 +000012197 } else if (tg3_flag(tp, HW_TSO_2))
Matt Carlsonbb158d62011-04-25 12:42:47 +000012198 mss |= hdr_len << 9;
Joe Perches63c3a662011-04-26 08:12:10 +000012199 else if (tg3_flag(tp, HW_TSO_1) ||
Matt Carlsonbb158d62011-04-25 12:42:47 +000012200 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
12201 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
12202 } else {
12203 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
12204 }
12205
12206 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
12207 } else {
12208 num_pkts = 1;
12209 data_off = ETH_HLEN;
Michael Chanc441b452012-03-04 14:48:13 +000012210
12211 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
12212 tx_len > VLAN_ETH_FRAME_LEN)
12213 base_flags |= TXD_FLAG_JMB_PKT;
Matt Carlsonbb158d62011-04-25 12:42:47 +000012214 }
12215
12216 for (i = data_off; i < tx_len; i++)
Michael Chanc76949a2005-05-29 14:58:59 -070012217 tx_data[i] = (u8) (i & 0xff);
12218
Alexander Duyckf4188d82009-12-02 16:48:38 +000012219 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
12220 if (pci_dma_mapping_error(tp->pdev, map)) {
Matt Carlsona21771d2009-11-02 14:25:31 +000012221 dev_kfree_skb(skb);
12222 return -EIO;
12223 }
Michael Chanc76949a2005-05-29 14:58:59 -070012224
Matt Carlson0d681b22011-07-27 14:20:49 +000012225 val = tnapi->tx_prod;
12226 tnapi->tx_buffers[val].skb = skb;
12227 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
12228
Michael Chanc76949a2005-05-29 14:58:59 -070012229 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000012230 rnapi->coal_now);
Michael Chanc76949a2005-05-29 14:58:59 -070012231
12232 udelay(10);
12233
Matt Carlson898a56f2009-08-28 14:02:40 +000012234 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
Michael Chanc76949a2005-05-29 14:58:59 -070012235
Matt Carlson84b67b22011-07-27 14:20:52 +000012236 budget = tg3_tx_avail(tnapi);
12237 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
Matt Carlsond1a3b732011-07-27 14:20:51 +000012238 base_flags | TXD_FLAG_END, mss, 0)) {
12239 tnapi->tx_buffers[val].skb = NULL;
12240 dev_kfree_skb(skb);
12241 return -EIO;
12242 }
Michael Chanc76949a2005-05-29 14:58:59 -070012243
Matt Carlsonf3f3f272009-08-28 14:03:21 +000012244 tnapi->tx_prod++;
Michael Chanc76949a2005-05-29 14:58:59 -070012245
Michael Chan6541b802012-03-04 14:48:14 +000012246 /* Sync BD data before updating mailbox */
12247 wmb();
12248
Matt Carlsonf3f3f272009-08-28 14:03:21 +000012249 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
12250 tr32_mailbox(tnapi->prodmbox);
Michael Chanc76949a2005-05-29 14:58:59 -070012251
12252 udelay(10);
12253
Matt Carlson303fc922009-11-02 14:27:34 +000012254 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
12255 for (i = 0; i < 35; i++) {
Michael Chanc76949a2005-05-29 14:58:59 -070012256 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000012257 coal_now);
Michael Chanc76949a2005-05-29 14:58:59 -070012258
12259 udelay(10);
12260
Matt Carlson898a56f2009-08-28 14:02:40 +000012261 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
12262 rx_idx = rnapi->hw_status->idx[0].rx_producer;
Matt Carlsonf3f3f272009-08-28 14:03:21 +000012263 if ((tx_idx == tnapi->tx_prod) &&
Michael Chanc76949a2005-05-29 14:58:59 -070012264 (rx_idx == (rx_start_idx + num_pkts)))
12265 break;
12266 }
12267
Matt Carlsonba1142e2011-11-04 09:15:00 +000012268 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
Michael Chanc76949a2005-05-29 14:58:59 -070012269 dev_kfree_skb(skb);
12270
Matt Carlsonf3f3f272009-08-28 14:03:21 +000012271 if (tx_idx != tnapi->tx_prod)
Michael Chanc76949a2005-05-29 14:58:59 -070012272 goto out;
12273
12274 if (rx_idx != rx_start_idx + num_pkts)
12275 goto out;
12276
Matt Carlsonbb158d62011-04-25 12:42:47 +000012277 val = data_off;
12278 while (rx_idx != rx_start_idx) {
12279 desc = &rnapi->rx_rcb[rx_start_idx++];
12280 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
12281 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
Michael Chanc76949a2005-05-29 14:58:59 -070012282
Matt Carlsonbb158d62011-04-25 12:42:47 +000012283 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
12284 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
Matt Carlson4852a862011-04-13 11:05:07 +000012285 goto out;
Michael Chanc76949a2005-05-29 14:58:59 -070012286
Matt Carlsonbb158d62011-04-25 12:42:47 +000012287 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
12288 - ETH_FCS_LEN;
12289
Matt Carlson28a45952011-08-19 13:58:22 +000012290 if (!tso_loopback) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000012291 if (rx_len != tx_len)
12292 goto out;
12293
12294 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
12295 if (opaque_key != RXD_OPAQUE_RING_STD)
12296 goto out;
12297 } else {
12298 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
12299 goto out;
12300 }
12301 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
12302 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
Matt Carlson54e0a672011-05-19 12:12:50 +000012303 >> RXD_TCPCSUM_SHIFT != 0xffff) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000012304 goto out;
12305 }
12306
12307 if (opaque_key == RXD_OPAQUE_RING_STD) {
Eric Dumazet9205fd92011-11-18 06:47:01 +000012308 rx_data = tpr->rx_std_buffers[desc_idx].data;
Matt Carlsonbb158d62011-04-25 12:42:47 +000012309 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
12310 mapping);
12311 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
Eric Dumazet9205fd92011-11-18 06:47:01 +000012312 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
Matt Carlsonbb158d62011-04-25 12:42:47 +000012313 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
12314 mapping);
12315 } else
Matt Carlson4852a862011-04-13 11:05:07 +000012316 goto out;
12317
Matt Carlsonbb158d62011-04-25 12:42:47 +000012318 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
12319 PCI_DMA_FROMDEVICE);
12320
Eric Dumazet9205fd92011-11-18 06:47:01 +000012321 rx_data += TG3_RX_OFFSET(tp);
Matt Carlsonbb158d62011-04-25 12:42:47 +000012322 for (i = data_off; i < rx_len; i++, val++) {
Eric Dumazet9205fd92011-11-18 06:47:01 +000012323 if (*(rx_data + i) != (u8) (val & 0xff))
Matt Carlsonbb158d62011-04-25 12:42:47 +000012324 goto out;
12325 }
Matt Carlson4852a862011-04-13 11:05:07 +000012326 }
12327
Michael Chanc76949a2005-05-29 14:58:59 -070012328 err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040012329
Eric Dumazet9205fd92011-11-18 06:47:01 +000012330 /* tg3_free_rings will unmap and free the rx_data */
Michael Chanc76949a2005-05-29 14:58:59 -070012331out:
12332 return err;
12333}
12334
Matt Carlson00c266b2011-04-25 12:42:46 +000012335#define TG3_STD_LOOPBACK_FAILED 1
12336#define TG3_JMB_LOOPBACK_FAILED 2
Matt Carlsonbb158d62011-04-25 12:42:47 +000012337#define TG3_TSO_LOOPBACK_FAILED 4
Matt Carlson28a45952011-08-19 13:58:22 +000012338#define TG3_LOOPBACK_FAILED \
12339 (TG3_STD_LOOPBACK_FAILED | \
12340 TG3_JMB_LOOPBACK_FAILED | \
12341 TG3_TSO_LOOPBACK_FAILED)
Matt Carlson00c266b2011-04-25 12:42:46 +000012342
Matt Carlson941ec902011-08-19 13:58:23 +000012343static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
Michael Chan9f40dea2005-09-05 17:53:06 -070012344{
Matt Carlson28a45952011-08-19 13:58:22 +000012345 int err = -EIO;
Matt Carlson2215e242011-08-19 13:58:19 +000012346 u32 eee_cap;
Michael Chanc441b452012-03-04 14:48:13 +000012347 u32 jmb_pkt_sz = 9000;
12348
12349 if (tp->dma_limit)
12350 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
Michael Chan9f40dea2005-09-05 17:53:06 -070012351
Matt Carlsonab789042011-01-25 15:58:54 +000012352 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
12353 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
12354
Matt Carlson28a45952011-08-19 13:58:22 +000012355 if (!netif_running(tp->dev)) {
12356 data[0] = TG3_LOOPBACK_FAILED;
12357 data[1] = TG3_LOOPBACK_FAILED;
Matt Carlson941ec902011-08-19 13:58:23 +000012358 if (do_extlpbk)
12359 data[2] = TG3_LOOPBACK_FAILED;
Matt Carlson28a45952011-08-19 13:58:22 +000012360 goto done;
12361 }
12362
Michael Chanb9ec6c12006-07-25 16:37:27 -070012363 err = tg3_reset_hw(tp, 1);
Matt Carlsonab789042011-01-25 15:58:54 +000012364 if (err) {
Matt Carlson28a45952011-08-19 13:58:22 +000012365 data[0] = TG3_LOOPBACK_FAILED;
12366 data[1] = TG3_LOOPBACK_FAILED;
Matt Carlson941ec902011-08-19 13:58:23 +000012367 if (do_extlpbk)
12368 data[2] = TG3_LOOPBACK_FAILED;
Matt Carlsonab789042011-01-25 15:58:54 +000012369 goto done;
12370 }
Michael Chan9f40dea2005-09-05 17:53:06 -070012371
Joe Perches63c3a662011-04-26 08:12:10 +000012372 if (tg3_flag(tp, ENABLE_RSS)) {
Matt Carlson4a85f092011-04-20 07:57:37 +000012373 int i;
12374
12375 /* Reroute all rx packets to the 1st queue */
12376 for (i = MAC_RSS_INDIR_TBL_0;
12377 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
12378 tw32(i, 0x0);
12379 }
12380
Matt Carlson6e01b202011-08-19 13:58:20 +000012381 /* HW errata - mac loopback fails in some cases on 5780.
12382 * Normal traffic and PHY loopback are not affected by
12383 * errata. Also, the MAC loopback test is deprecated for
12384 * all newer ASIC revisions.
12385 */
12386 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
12387 !tg3_flag(tp, CPMU_PRESENT)) {
12388 tg3_mac_loopback(tp, true);
Matt Carlson9936bcf2007-10-10 18:03:07 -070012389
Matt Carlson28a45952011-08-19 13:58:22 +000012390 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12391 data[0] |= TG3_STD_LOOPBACK_FAILED;
Matt Carlson6e01b202011-08-19 13:58:20 +000012392
12393 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
Michael Chanc441b452012-03-04 14:48:13 +000012394 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
Matt Carlson28a45952011-08-19 13:58:22 +000012395 data[0] |= TG3_JMB_LOOPBACK_FAILED;
Matt Carlson6e01b202011-08-19 13:58:20 +000012396
12397 tg3_mac_loopback(tp, false);
12398 }
Matt Carlson4852a862011-04-13 11:05:07 +000012399
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012400 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Joe Perches63c3a662011-04-26 08:12:10 +000012401 !tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson5e5a7f32011-08-19 13:58:21 +000012402 int i;
12403
Matt Carlson941ec902011-08-19 13:58:23 +000012404 tg3_phy_lpbk_set(tp, 0, false);
Matt Carlson5e5a7f32011-08-19 13:58:21 +000012405
12406 /* Wait for link */
12407 for (i = 0; i < 100; i++) {
12408 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
12409 break;
12410 mdelay(1);
12411 }
12412
Matt Carlson28a45952011-08-19 13:58:22 +000012413 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12414 data[1] |= TG3_STD_LOOPBACK_FAILED;
Joe Perches63c3a662011-04-26 08:12:10 +000012415 if (tg3_flag(tp, TSO_CAPABLE) &&
Matt Carlson28a45952011-08-19 13:58:22 +000012416 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
12417 data[1] |= TG3_TSO_LOOPBACK_FAILED;
Joe Perches63c3a662011-04-26 08:12:10 +000012418 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
Michael Chanc441b452012-03-04 14:48:13 +000012419 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
Matt Carlson28a45952011-08-19 13:58:22 +000012420 data[1] |= TG3_JMB_LOOPBACK_FAILED;
Michael Chan9f40dea2005-09-05 17:53:06 -070012421
Matt Carlson941ec902011-08-19 13:58:23 +000012422 if (do_extlpbk) {
12423 tg3_phy_lpbk_set(tp, 0, true);
12424
12425 /* All link indications report up, but the hardware
12426 * isn't really ready for about 20 msec. Double it
12427 * to be sure.
12428 */
12429 mdelay(40);
12430
12431 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12432 data[2] |= TG3_STD_LOOPBACK_FAILED;
12433 if (tg3_flag(tp, TSO_CAPABLE) &&
12434 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
12435 data[2] |= TG3_TSO_LOOPBACK_FAILED;
12436 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
Michael Chanc441b452012-03-04 14:48:13 +000012437 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
Matt Carlson941ec902011-08-19 13:58:23 +000012438 data[2] |= TG3_JMB_LOOPBACK_FAILED;
12439 }
12440
Matt Carlson5e5a7f32011-08-19 13:58:21 +000012441 /* Re-enable gphy autopowerdown. */
12442 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
12443 tg3_phy_toggle_apd(tp, true);
12444 }
Matt Carlson6833c042008-11-21 17:18:59 -080012445
Matt Carlson941ec902011-08-19 13:58:23 +000012446 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
Matt Carlson28a45952011-08-19 13:58:22 +000012447
Matt Carlsonab789042011-01-25 15:58:54 +000012448done:
12449 tp->phy_flags |= eee_cap;
12450
Michael Chan9f40dea2005-09-05 17:53:06 -070012451 return err;
12452}
12453
Michael Chan4cafd3f2005-05-29 14:56:34 -070012454static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
12455 u64 *data)
12456{
Michael Chan566f86a2005-05-29 14:56:58 -070012457 struct tg3 *tp = netdev_priv(dev);
Matt Carlson941ec902011-08-19 13:58:23 +000012458 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
Michael Chan566f86a2005-05-29 14:56:58 -070012459
Matt Carlsonbed98292011-07-13 09:27:29 +000012460 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
12461 tg3_power_up(tp)) {
12462 etest->flags |= ETH_TEST_FL_FAILED;
12463 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
12464 return;
12465 }
Michael Chanbc1c7562006-03-20 17:48:03 -080012466
Michael Chan566f86a2005-05-29 14:56:58 -070012467 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
12468
12469 if (tg3_test_nvram(tp) != 0) {
12470 etest->flags |= ETH_TEST_FL_FAILED;
12471 data[0] = 1;
12472 }
Matt Carlson941ec902011-08-19 13:58:23 +000012473 if (!doextlpbk && tg3_test_link(tp)) {
Michael Chanca430072005-05-29 14:57:23 -070012474 etest->flags |= ETH_TEST_FL_FAILED;
12475 data[1] = 1;
12476 }
Michael Chana71116d2005-05-29 14:58:11 -070012477 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070012478 int err, err2 = 0, irq_sync = 0;
Michael Chana71116d2005-05-29 14:58:11 -070012479
Michael Chanbbe832c2005-06-24 20:20:04 -070012480 if (netif_running(dev)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070012481 tg3_phy_stop(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070012482 tg3_netif_stop(tp);
12483 irq_sync = 1;
12484 }
12485
12486 tg3_full_lock(tp, irq_sync);
Michael Chana71116d2005-05-29 14:58:11 -070012487
12488 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
Michael Chanec41c7d2006-01-17 02:40:55 -080012489 err = tg3_nvram_lock(tp);
Michael Chana71116d2005-05-29 14:58:11 -070012490 tg3_halt_cpu(tp, RX_CPU_BASE);
Joe Perches63c3a662011-04-26 08:12:10 +000012491 if (!tg3_flag(tp, 5705_PLUS))
Michael Chana71116d2005-05-29 14:58:11 -070012492 tg3_halt_cpu(tp, TX_CPU_BASE);
Michael Chanec41c7d2006-01-17 02:40:55 -080012493 if (!err)
12494 tg3_nvram_unlock(tp);
Michael Chana71116d2005-05-29 14:58:11 -070012495
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012496 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chand9ab5ad12006-03-20 22:27:35 -080012497 tg3_phy_reset(tp);
12498
Michael Chana71116d2005-05-29 14:58:11 -070012499 if (tg3_test_registers(tp) != 0) {
12500 etest->flags |= ETH_TEST_FL_FAILED;
12501 data[2] = 1;
12502 }
Matt Carlson28a45952011-08-19 13:58:22 +000012503
Michael Chan7942e1d2005-05-29 14:58:36 -070012504 if (tg3_test_memory(tp) != 0) {
12505 etest->flags |= ETH_TEST_FL_FAILED;
12506 data[3] = 1;
12507 }
Matt Carlson28a45952011-08-19 13:58:22 +000012508
Matt Carlson941ec902011-08-19 13:58:23 +000012509 if (doextlpbk)
12510 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
12511
12512 if (tg3_test_loopback(tp, &data[4], doextlpbk))
Michael Chanc76949a2005-05-29 14:58:59 -070012513 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chana71116d2005-05-29 14:58:11 -070012514
David S. Millerf47c11e2005-06-24 20:18:35 -070012515 tg3_full_unlock(tp);
12516
Michael Chand4bc3922005-05-29 14:59:20 -070012517 if (tg3_test_interrupt(tp) != 0) {
12518 etest->flags |= ETH_TEST_FL_FAILED;
Matt Carlson941ec902011-08-19 13:58:23 +000012519 data[7] = 1;
Michael Chand4bc3922005-05-29 14:59:20 -070012520 }
David S. Millerf47c11e2005-06-24 20:18:35 -070012521
12522 tg3_full_lock(tp, 0);
Michael Chand4bc3922005-05-29 14:59:20 -070012523
Michael Chana71116d2005-05-29 14:58:11 -070012524 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12525 if (netif_running(dev)) {
Joe Perches63c3a662011-04-26 08:12:10 +000012526 tg3_flag_set(tp, INIT_COMPLETE);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070012527 err2 = tg3_restart_hw(tp, 1);
12528 if (!err2)
Michael Chanb9ec6c12006-07-25 16:37:27 -070012529 tg3_netif_start(tp);
Michael Chana71116d2005-05-29 14:58:11 -070012530 }
David S. Millerf47c11e2005-06-24 20:18:35 -070012531
12532 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070012533
12534 if (irq_sync && !err2)
12535 tg3_phy_start(tp);
Michael Chana71116d2005-05-29 14:58:11 -070012536 }
Matt Carlson80096062010-08-02 11:26:06 +000012537 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000012538 tg3_power_down(tp);
Michael Chanbc1c7562006-03-20 17:48:03 -080012539
Michael Chan4cafd3f2005-05-29 14:56:34 -070012540}
12541
Linus Torvalds1da177e2005-04-16 15:20:36 -070012542static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12543{
12544 struct mii_ioctl_data *data = if_mii(ifr);
12545 struct tg3 *tp = netdev_priv(dev);
12546 int err;
12547
Joe Perches63c3a662011-04-26 08:12:10 +000012548 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000012549 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012550 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070012551 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000012552 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Richard Cochran28b04112010-07-17 08:48:55 +000012553 return phy_mii_ioctl(phydev, ifr, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070012554 }
12555
Matt Carlson33f401a2010-04-05 10:19:27 +000012556 switch (cmd) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012557 case SIOCGMIIPHY:
Matt Carlson882e9792009-09-01 13:21:36 +000012558 data->phy_id = tp->phy_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012559
12560 /* fallthru */
12561 case SIOCGMIIREG: {
12562 u32 mii_regval;
12563
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012564 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012565 break; /* We have no PHY */
12566
Matt Carlson34eea5a2011-04-20 07:57:38 +000012567 if (!netif_running(dev))
Michael Chanbc1c7562006-03-20 17:48:03 -080012568 return -EAGAIN;
12569
David S. Millerf47c11e2005-06-24 20:18:35 -070012570 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012571 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
David S. Millerf47c11e2005-06-24 20:18:35 -070012572 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012573
12574 data->val_out = mii_regval;
12575
12576 return err;
12577 }
12578
12579 case SIOCSMIIREG:
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012580 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012581 break; /* We have no PHY */
12582
Matt Carlson34eea5a2011-04-20 07:57:38 +000012583 if (!netif_running(dev))
Michael Chanbc1c7562006-03-20 17:48:03 -080012584 return -EAGAIN;
12585
David S. Millerf47c11e2005-06-24 20:18:35 -070012586 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012587 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
David S. Millerf47c11e2005-06-24 20:18:35 -070012588 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012589
12590 return err;
12591
12592 default:
12593 /* do nothing */
12594 break;
12595 }
12596 return -EOPNOTSUPP;
12597}
12598
David S. Miller15f98502005-05-18 22:49:26 -070012599static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12600{
12601 struct tg3 *tp = netdev_priv(dev);
12602
12603 memcpy(ec, &tp->coal, sizeof(*ec));
12604 return 0;
12605}
12606
Michael Chand244c892005-07-05 14:42:33 -070012607static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12608{
12609 struct tg3 *tp = netdev_priv(dev);
12610 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
12611 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
12612
Joe Perches63c3a662011-04-26 08:12:10 +000012613 if (!tg3_flag(tp, 5705_PLUS)) {
Michael Chand244c892005-07-05 14:42:33 -070012614 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
12615 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
12616 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
12617 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
12618 }
12619
12620 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
12621 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
12622 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
12623 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
12624 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
12625 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
12626 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
12627 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
12628 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
12629 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
12630 return -EINVAL;
12631
12632 /* No rx interrupts will be generated if both are zero */
12633 if ((ec->rx_coalesce_usecs == 0) &&
12634 (ec->rx_max_coalesced_frames == 0))
12635 return -EINVAL;
12636
12637 /* No tx interrupts will be generated if both are zero */
12638 if ((ec->tx_coalesce_usecs == 0) &&
12639 (ec->tx_max_coalesced_frames == 0))
12640 return -EINVAL;
12641
12642 /* Only copy relevant parameters, ignore all others. */
12643 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
12644 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
12645 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
12646 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
12647 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
12648 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
12649 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
12650 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
12651 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
12652
12653 if (netif_running(dev)) {
12654 tg3_full_lock(tp, 0);
12655 __tg3_set_coalesce(tp, &tp->coal);
12656 tg3_full_unlock(tp);
12657 }
12658 return 0;
12659}
12660
Jeff Garzik7282d492006-09-13 14:30:00 -040012661static const struct ethtool_ops tg3_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012662 .get_settings = tg3_get_settings,
12663 .set_settings = tg3_set_settings,
12664 .get_drvinfo = tg3_get_drvinfo,
12665 .get_regs_len = tg3_get_regs_len,
12666 .get_regs = tg3_get_regs,
12667 .get_wol = tg3_get_wol,
12668 .set_wol = tg3_set_wol,
12669 .get_msglevel = tg3_get_msglevel,
12670 .set_msglevel = tg3_set_msglevel,
12671 .nway_reset = tg3_nway_reset,
12672 .get_link = ethtool_op_get_link,
12673 .get_eeprom_len = tg3_get_eeprom_len,
12674 .get_eeprom = tg3_get_eeprom,
12675 .set_eeprom = tg3_set_eeprom,
12676 .get_ringparam = tg3_get_ringparam,
12677 .set_ringparam = tg3_set_ringparam,
12678 .get_pauseparam = tg3_get_pauseparam,
12679 .set_pauseparam = tg3_set_pauseparam,
Michael Chan4cafd3f2005-05-29 14:56:34 -070012680 .self_test = tg3_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -070012681 .get_strings = tg3_get_strings,
stephen hemminger81b87092011-04-04 08:43:50 +000012682 .set_phys_id = tg3_set_phys_id,
Linus Torvalds1da177e2005-04-16 15:20:36 -070012683 .get_ethtool_stats = tg3_get_ethtool_stats,
David S. Miller15f98502005-05-18 22:49:26 -070012684 .get_coalesce = tg3_get_coalesce,
Michael Chand244c892005-07-05 14:42:33 -070012685 .set_coalesce = tg3_set_coalesce,
Jeff Garzikb9f2c042007-10-03 18:07:32 -070012686 .get_sset_count = tg3_get_sset_count,
Matt Carlson90415472011-12-16 13:33:23 +000012687 .get_rxnfc = tg3_get_rxnfc,
12688 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
12689 .get_rxfh_indir = tg3_get_rxfh_indir,
12690 .set_rxfh_indir = tg3_set_rxfh_indir,
Michael Chan09681692012-09-28 07:12:42 +000012691 .get_channels = tg3_get_channels,
12692 .set_channels = tg3_set_channels,
Richard Cochran3f847492012-04-03 22:59:39 +000012693 .get_ts_info = ethtool_op_get_ts_info,
Linus Torvalds1da177e2005-04-16 15:20:36 -070012694};
12695
David S. Millerb4017c52012-03-01 17:57:40 -050012696static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
12697 struct rtnl_link_stats64 *stats)
12698{
12699 struct tg3 *tp = netdev_priv(dev);
12700
David S. Millerb4017c52012-03-01 17:57:40 -050012701 spin_lock_bh(&tp->lock);
Michael Chan0f566b22012-07-29 19:15:44 +000012702 if (!tp->hw_stats) {
12703 spin_unlock_bh(&tp->lock);
12704 return &tp->net_stats_prev;
12705 }
12706
David S. Millerb4017c52012-03-01 17:57:40 -050012707 tg3_get_nstats(tp, stats);
12708 spin_unlock_bh(&tp->lock);
12709
12710 return stats;
12711}
12712
Matt Carlsonccd5ba92012-02-13 10:20:08 +000012713static void tg3_set_rx_mode(struct net_device *dev)
12714{
12715 struct tg3 *tp = netdev_priv(dev);
12716
12717 if (!netif_running(dev))
12718 return;
12719
12720 tg3_full_lock(tp, 0);
12721 __tg3_set_rx_mode(dev);
12722 tg3_full_unlock(tp);
12723}
12724
Matt Carlsonfaf16272012-02-13 10:20:07 +000012725static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
12726 int new_mtu)
12727{
12728 dev->mtu = new_mtu;
12729
12730 if (new_mtu > ETH_DATA_LEN) {
12731 if (tg3_flag(tp, 5780_CLASS)) {
12732 netdev_update_features(dev);
12733 tg3_flag_clear(tp, TSO_CAPABLE);
12734 } else {
12735 tg3_flag_set(tp, JUMBO_RING_ENABLE);
12736 }
12737 } else {
12738 if (tg3_flag(tp, 5780_CLASS)) {
12739 tg3_flag_set(tp, TSO_CAPABLE);
12740 netdev_update_features(dev);
12741 }
12742 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
12743 }
12744}
12745
12746static int tg3_change_mtu(struct net_device *dev, int new_mtu)
12747{
12748 struct tg3 *tp = netdev_priv(dev);
Michael Chan2fae5e32012-03-04 14:48:15 +000012749 int err, reset_phy = 0;
Matt Carlsonfaf16272012-02-13 10:20:07 +000012750
12751 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
12752 return -EINVAL;
12753
12754 if (!netif_running(dev)) {
12755 /* We'll just catch it later when the
12756 * device is up'd.
12757 */
12758 tg3_set_mtu(dev, tp, new_mtu);
12759 return 0;
12760 }
12761
12762 tg3_phy_stop(tp);
12763
12764 tg3_netif_stop(tp);
12765
12766 tg3_full_lock(tp, 1);
12767
12768 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12769
12770 tg3_set_mtu(dev, tp, new_mtu);
12771
Michael Chan2fae5e32012-03-04 14:48:15 +000012772 /* Reset PHY, otherwise the read DMA engine will be in a mode that
12773 * breaks all requests to 256 bytes.
12774 */
12775 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
12776 reset_phy = 1;
12777
12778 err = tg3_restart_hw(tp, reset_phy);
Matt Carlsonfaf16272012-02-13 10:20:07 +000012779
12780 if (!err)
12781 tg3_netif_start(tp);
12782
12783 tg3_full_unlock(tp);
12784
12785 if (!err)
12786 tg3_phy_start(tp);
12787
12788 return err;
12789}
12790
12791static const struct net_device_ops tg3_netdev_ops = {
12792 .ndo_open = tg3_open,
12793 .ndo_stop = tg3_close,
12794 .ndo_start_xmit = tg3_start_xmit,
12795 .ndo_get_stats64 = tg3_get_stats64,
12796 .ndo_validate_addr = eth_validate_addr,
12797 .ndo_set_rx_mode = tg3_set_rx_mode,
12798 .ndo_set_mac_address = tg3_set_mac_addr,
12799 .ndo_do_ioctl = tg3_ioctl,
12800 .ndo_tx_timeout = tg3_tx_timeout,
12801 .ndo_change_mtu = tg3_change_mtu,
12802 .ndo_fix_features = tg3_fix_features,
12803 .ndo_set_features = tg3_set_features,
12804#ifdef CONFIG_NET_POLL_CONTROLLER
12805 .ndo_poll_controller = tg3_poll_controller,
12806#endif
12807};
12808
Linus Torvalds1da177e2005-04-16 15:20:36 -070012809static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12810{
Michael Chan1b277772006-03-20 22:27:48 -080012811 u32 cursize, val, magic;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012812
12813 tp->nvram_size = EEPROM_CHIP_SIZE;
12814
Matt Carlsone4f34112009-02-25 14:25:00 +000012815 if (tg3_nvram_read(tp, 0, &magic) != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012816 return;
12817
Michael Chanb16250e2006-09-27 16:10:14 -070012818 if ((magic != TG3_EEPROM_MAGIC) &&
12819 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12820 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012821 return;
12822
12823 /*
12824 * Size the chip by reading offsets at increasing powers of two.
12825 * When we encounter our validation signature, we know the addressing
12826 * has wrapped around, and thus have our chip size.
12827 */
Michael Chan1b277772006-03-20 22:27:48 -080012828 cursize = 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012829
12830 while (cursize < tp->nvram_size) {
Matt Carlsone4f34112009-02-25 14:25:00 +000012831 if (tg3_nvram_read(tp, cursize, &val) != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012832 return;
12833
Michael Chan18201802006-03-20 22:29:15 -080012834 if (val == magic)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012835 break;
12836
12837 cursize <<= 1;
12838 }
12839
12840 tp->nvram_size = cursize;
12841}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040012842
Linus Torvalds1da177e2005-04-16 15:20:36 -070012843static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12844{
12845 u32 val;
12846
Joe Perches63c3a662011-04-26 08:12:10 +000012847 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
Michael Chan1b277772006-03-20 22:27:48 -080012848 return;
12849
12850 /* Selfboot format */
Michael Chan18201802006-03-20 22:29:15 -080012851 if (val != TG3_EEPROM_MAGIC) {
Michael Chan1b277772006-03-20 22:27:48 -080012852 tg3_get_eeprom_size(tp);
12853 return;
12854 }
12855
Matt Carlson6d348f22009-02-25 14:25:52 +000012856 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012857 if (val != 0) {
Matt Carlson6d348f22009-02-25 14:25:52 +000012858 /* This is confusing. We want to operate on the
12859 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12860 * call will read from NVRAM and byteswap the data
12861 * according to the byteswapping settings for all
12862 * other register accesses. This ensures the data we
12863 * want will always reside in the lower 16-bits.
12864 * However, the data in NVRAM is in LE format, which
12865 * means the data from the NVRAM read will always be
12866 * opposite the endianness of the CPU. The 16-bit
12867 * byteswap then brings the data to CPU endianness.
12868 */
12869 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012870 return;
12871 }
12872 }
Matt Carlsonfd1122a2008-05-02 16:48:36 -070012873 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012874}
12875
12876static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12877{
12878 u32 nvcfg1;
12879
12880 nvcfg1 = tr32(NVRAM_CFG1);
12881 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
Joe Perches63c3a662011-04-26 08:12:10 +000012882 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012883 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012884 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12885 tw32(NVRAM_CFG1, nvcfg1);
12886 }
12887
Matt Carlson6ff6f812011-05-19 12:12:54 +000012888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
Joe Perches63c3a662011-04-26 08:12:10 +000012889 tg3_flag(tp, 5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012890 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000012891 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12892 tp->nvram_jedecnum = JEDEC_ATMEL;
12893 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
Joe Perches63c3a662011-04-26 08:12:10 +000012894 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012895 break;
12896 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12897 tp->nvram_jedecnum = JEDEC_ATMEL;
12898 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12899 break;
12900 case FLASH_VENDOR_ATMEL_EEPROM:
12901 tp->nvram_jedecnum = JEDEC_ATMEL;
12902 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
Joe Perches63c3a662011-04-26 08:12:10 +000012903 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012904 break;
12905 case FLASH_VENDOR_ST:
12906 tp->nvram_jedecnum = JEDEC_ST;
12907 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
Joe Perches63c3a662011-04-26 08:12:10 +000012908 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012909 break;
12910 case FLASH_VENDOR_SAIFUN:
12911 tp->nvram_jedecnum = JEDEC_SAIFUN;
12912 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12913 break;
12914 case FLASH_VENDOR_SST_SMALL:
12915 case FLASH_VENDOR_SST_LARGE:
12916 tp->nvram_jedecnum = JEDEC_SST;
12917 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12918 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012919 }
Matt Carlson8590a602009-08-28 12:29:16 +000012920 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012921 tp->nvram_jedecnum = JEDEC_ATMEL;
12922 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
Joe Perches63c3a662011-04-26 08:12:10 +000012923 tg3_flag_set(tp, NVRAM_BUFFERED);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012924 }
12925}
12926
Matt Carlsona1b950d2009-09-01 13:20:17 +000012927static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12928{
12929 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12930 case FLASH_5752PAGE_SIZE_256:
12931 tp->nvram_pagesize = 256;
12932 break;
12933 case FLASH_5752PAGE_SIZE_512:
12934 tp->nvram_pagesize = 512;
12935 break;
12936 case FLASH_5752PAGE_SIZE_1K:
12937 tp->nvram_pagesize = 1024;
12938 break;
12939 case FLASH_5752PAGE_SIZE_2K:
12940 tp->nvram_pagesize = 2048;
12941 break;
12942 case FLASH_5752PAGE_SIZE_4K:
12943 tp->nvram_pagesize = 4096;
12944 break;
12945 case FLASH_5752PAGE_SIZE_264:
12946 tp->nvram_pagesize = 264;
12947 break;
12948 case FLASH_5752PAGE_SIZE_528:
12949 tp->nvram_pagesize = 528;
12950 break;
12951 }
12952}
12953
Michael Chan361b4ac2005-04-21 17:11:21 -070012954static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12955{
12956 u32 nvcfg1;
12957
12958 nvcfg1 = tr32(NVRAM_CFG1);
12959
Michael Chane6af3012005-04-21 17:12:05 -070012960 /* NVRAM protection for TPM */
12961 if (nvcfg1 & (1 << 27))
Joe Perches63c3a662011-04-26 08:12:10 +000012962 tg3_flag_set(tp, PROTECTED_NVRAM);
Michael Chane6af3012005-04-21 17:12:05 -070012963
Michael Chan361b4ac2005-04-21 17:11:21 -070012964 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000012965 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12966 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12967 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012968 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012969 break;
12970 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12971 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012972 tg3_flag_set(tp, NVRAM_BUFFERED);
12973 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012974 break;
12975 case FLASH_5752VENDOR_ST_M45PE10:
12976 case FLASH_5752VENDOR_ST_M45PE20:
12977 case FLASH_5752VENDOR_ST_M45PE40:
12978 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000012979 tg3_flag_set(tp, NVRAM_BUFFERED);
12980 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012981 break;
Michael Chan361b4ac2005-04-21 17:11:21 -070012982 }
12983
Joe Perches63c3a662011-04-26 08:12:10 +000012984 if (tg3_flag(tp, FLASH)) {
Matt Carlsona1b950d2009-09-01 13:20:17 +000012985 tg3_nvram_get_pagesize(tp, nvcfg1);
Matt Carlson8590a602009-08-28 12:29:16 +000012986 } else {
Michael Chan361b4ac2005-04-21 17:11:21 -070012987 /* For eeprom, set pagesize to maximum eeprom size */
12988 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12989
12990 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12991 tw32(NVRAM_CFG1, nvcfg1);
12992 }
12993}
12994
Michael Chand3c7b882006-03-23 01:28:25 -080012995static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12996{
Matt Carlson989a9d22007-05-05 11:51:05 -070012997 u32 nvcfg1, protect = 0;
Michael Chand3c7b882006-03-23 01:28:25 -080012998
12999 nvcfg1 = tr32(NVRAM_CFG1);
13000
13001 /* NVRAM protection for TPM */
Matt Carlson989a9d22007-05-05 11:51:05 -070013002 if (nvcfg1 & (1 << 27)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013003 tg3_flag_set(tp, PROTECTED_NVRAM);
Matt Carlson989a9d22007-05-05 11:51:05 -070013004 protect = 1;
13005 }
Michael Chand3c7b882006-03-23 01:28:25 -080013006
Matt Carlson989a9d22007-05-05 11:51:05 -070013007 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
13008 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000013009 case FLASH_5755VENDOR_ATMEL_FLASH_1:
13010 case FLASH_5755VENDOR_ATMEL_FLASH_2:
13011 case FLASH_5755VENDOR_ATMEL_FLASH_3:
13012 case FLASH_5755VENDOR_ATMEL_FLASH_5:
13013 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013014 tg3_flag_set(tp, NVRAM_BUFFERED);
13015 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000013016 tp->nvram_pagesize = 264;
13017 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
13018 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
13019 tp->nvram_size = (protect ? 0x3e200 :
13020 TG3_NVRAM_SIZE_512KB);
13021 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
13022 tp->nvram_size = (protect ? 0x1f200 :
13023 TG3_NVRAM_SIZE_256KB);
13024 else
13025 tp->nvram_size = (protect ? 0x1f200 :
13026 TG3_NVRAM_SIZE_128KB);
13027 break;
13028 case FLASH_5752VENDOR_ST_M45PE10:
13029 case FLASH_5752VENDOR_ST_M45PE20:
13030 case FLASH_5752VENDOR_ST_M45PE40:
13031 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000013032 tg3_flag_set(tp, NVRAM_BUFFERED);
13033 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000013034 tp->nvram_pagesize = 256;
13035 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
13036 tp->nvram_size = (protect ?
13037 TG3_NVRAM_SIZE_64KB :
13038 TG3_NVRAM_SIZE_128KB);
13039 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
13040 tp->nvram_size = (protect ?
13041 TG3_NVRAM_SIZE_64KB :
13042 TG3_NVRAM_SIZE_256KB);
13043 else
13044 tp->nvram_size = (protect ?
13045 TG3_NVRAM_SIZE_128KB :
13046 TG3_NVRAM_SIZE_512KB);
13047 break;
Michael Chand3c7b882006-03-23 01:28:25 -080013048 }
13049}
13050
Michael Chan1b277772006-03-20 22:27:48 -080013051static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
13052{
13053 u32 nvcfg1;
13054
13055 nvcfg1 = tr32(NVRAM_CFG1);
13056
13057 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000013058 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
13059 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
13060 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
13061 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
13062 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013063 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000013064 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
Michael Chan1b277772006-03-20 22:27:48 -080013065
Matt Carlson8590a602009-08-28 12:29:16 +000013066 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13067 tw32(NVRAM_CFG1, nvcfg1);
13068 break;
13069 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13070 case FLASH_5755VENDOR_ATMEL_FLASH_1:
13071 case FLASH_5755VENDOR_ATMEL_FLASH_2:
13072 case FLASH_5755VENDOR_ATMEL_FLASH_3:
13073 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013074 tg3_flag_set(tp, NVRAM_BUFFERED);
13075 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000013076 tp->nvram_pagesize = 264;
13077 break;
13078 case FLASH_5752VENDOR_ST_M45PE10:
13079 case FLASH_5752VENDOR_ST_M45PE20:
13080 case FLASH_5752VENDOR_ST_M45PE40:
13081 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000013082 tg3_flag_set(tp, NVRAM_BUFFERED);
13083 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000013084 tp->nvram_pagesize = 256;
13085 break;
Michael Chan1b277772006-03-20 22:27:48 -080013086 }
13087}
13088
Matt Carlson6b91fa02007-10-10 18:01:09 -070013089static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
13090{
13091 u32 nvcfg1, protect = 0;
13092
13093 nvcfg1 = tr32(NVRAM_CFG1);
13094
13095 /* NVRAM protection for TPM */
13096 if (nvcfg1 & (1 << 27)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013097 tg3_flag_set(tp, PROTECTED_NVRAM);
Matt Carlson6b91fa02007-10-10 18:01:09 -070013098 protect = 1;
13099 }
13100
13101 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
13102 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000013103 case FLASH_5761VENDOR_ATMEL_ADB021D:
13104 case FLASH_5761VENDOR_ATMEL_ADB041D:
13105 case FLASH_5761VENDOR_ATMEL_ADB081D:
13106 case FLASH_5761VENDOR_ATMEL_ADB161D:
13107 case FLASH_5761VENDOR_ATMEL_MDB021D:
13108 case FLASH_5761VENDOR_ATMEL_MDB041D:
13109 case FLASH_5761VENDOR_ATMEL_MDB081D:
13110 case FLASH_5761VENDOR_ATMEL_MDB161D:
13111 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013112 tg3_flag_set(tp, NVRAM_BUFFERED);
13113 tg3_flag_set(tp, FLASH);
13114 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
Matt Carlson8590a602009-08-28 12:29:16 +000013115 tp->nvram_pagesize = 256;
13116 break;
13117 case FLASH_5761VENDOR_ST_A_M45PE20:
13118 case FLASH_5761VENDOR_ST_A_M45PE40:
13119 case FLASH_5761VENDOR_ST_A_M45PE80:
13120 case FLASH_5761VENDOR_ST_A_M45PE16:
13121 case FLASH_5761VENDOR_ST_M_M45PE20:
13122 case FLASH_5761VENDOR_ST_M_M45PE40:
13123 case FLASH_5761VENDOR_ST_M_M45PE80:
13124 case FLASH_5761VENDOR_ST_M_M45PE16:
13125 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000013126 tg3_flag_set(tp, NVRAM_BUFFERED);
13127 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000013128 tp->nvram_pagesize = 256;
13129 break;
Matt Carlson6b91fa02007-10-10 18:01:09 -070013130 }
13131
13132 if (protect) {
13133 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
13134 } else {
13135 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000013136 case FLASH_5761VENDOR_ATMEL_ADB161D:
13137 case FLASH_5761VENDOR_ATMEL_MDB161D:
13138 case FLASH_5761VENDOR_ST_A_M45PE16:
13139 case FLASH_5761VENDOR_ST_M_M45PE16:
13140 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
13141 break;
13142 case FLASH_5761VENDOR_ATMEL_ADB081D:
13143 case FLASH_5761VENDOR_ATMEL_MDB081D:
13144 case FLASH_5761VENDOR_ST_A_M45PE80:
13145 case FLASH_5761VENDOR_ST_M_M45PE80:
13146 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13147 break;
13148 case FLASH_5761VENDOR_ATMEL_ADB041D:
13149 case FLASH_5761VENDOR_ATMEL_MDB041D:
13150 case FLASH_5761VENDOR_ST_A_M45PE40:
13151 case FLASH_5761VENDOR_ST_M_M45PE40:
13152 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13153 break;
13154 case FLASH_5761VENDOR_ATMEL_ADB021D:
13155 case FLASH_5761VENDOR_ATMEL_MDB021D:
13156 case FLASH_5761VENDOR_ST_A_M45PE20:
13157 case FLASH_5761VENDOR_ST_M_M45PE20:
13158 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13159 break;
Matt Carlson6b91fa02007-10-10 18:01:09 -070013160 }
13161 }
13162}
13163
Michael Chanb5d37722006-09-27 16:06:21 -070013164static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
13165{
13166 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013167 tg3_flag_set(tp, NVRAM_BUFFERED);
Michael Chanb5d37722006-09-27 16:06:21 -070013168 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13169}
13170
Matt Carlson321d32a2008-11-21 17:22:19 -080013171static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
13172{
13173 u32 nvcfg1;
13174
13175 nvcfg1 = tr32(NVRAM_CFG1);
13176
13177 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13178 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
13179 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
13180 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013181 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson321d32a2008-11-21 17:22:19 -080013182 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13183
13184 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13185 tw32(NVRAM_CFG1, nvcfg1);
13186 return;
13187 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13188 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
13189 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
13190 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
13191 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
13192 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
13193 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
13194 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013195 tg3_flag_set(tp, NVRAM_BUFFERED);
13196 tg3_flag_set(tp, FLASH);
Matt Carlson321d32a2008-11-21 17:22:19 -080013197
13198 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13199 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13200 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
13201 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
13202 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13203 break;
13204 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
13205 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
13206 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13207 break;
13208 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
13209 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
13210 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13211 break;
13212 }
13213 break;
13214 case FLASH_5752VENDOR_ST_M45PE10:
13215 case FLASH_5752VENDOR_ST_M45PE20:
13216 case FLASH_5752VENDOR_ST_M45PE40:
13217 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000013218 tg3_flag_set(tp, NVRAM_BUFFERED);
13219 tg3_flag_set(tp, FLASH);
Matt Carlson321d32a2008-11-21 17:22:19 -080013220
13221 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13222 case FLASH_5752VENDOR_ST_M45PE10:
13223 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13224 break;
13225 case FLASH_5752VENDOR_ST_M45PE20:
13226 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13227 break;
13228 case FLASH_5752VENDOR_ST_M45PE40:
13229 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13230 break;
13231 }
13232 break;
13233 default:
Joe Perches63c3a662011-04-26 08:12:10 +000013234 tg3_flag_set(tp, NO_NVRAM);
Matt Carlson321d32a2008-11-21 17:22:19 -080013235 return;
13236 }
13237
Matt Carlsona1b950d2009-09-01 13:20:17 +000013238 tg3_nvram_get_pagesize(tp, nvcfg1);
13239 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
Joe Perches63c3a662011-04-26 08:12:10 +000013240 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
Matt Carlsona1b950d2009-09-01 13:20:17 +000013241}
13242
13243
13244static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
13245{
13246 u32 nvcfg1;
13247
13248 nvcfg1 = tr32(NVRAM_CFG1);
13249
13250 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13251 case FLASH_5717VENDOR_ATMEL_EEPROM:
13252 case FLASH_5717VENDOR_MICRO_EEPROM:
13253 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013254 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlsona1b950d2009-09-01 13:20:17 +000013255 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13256
13257 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13258 tw32(NVRAM_CFG1, nvcfg1);
13259 return;
13260 case FLASH_5717VENDOR_ATMEL_MDB011D:
13261 case FLASH_5717VENDOR_ATMEL_ADB011B:
13262 case FLASH_5717VENDOR_ATMEL_ADB011D:
13263 case FLASH_5717VENDOR_ATMEL_MDB021D:
13264 case FLASH_5717VENDOR_ATMEL_ADB021B:
13265 case FLASH_5717VENDOR_ATMEL_ADB021D:
13266 case FLASH_5717VENDOR_ATMEL_45USPT:
13267 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013268 tg3_flag_set(tp, NVRAM_BUFFERED);
13269 tg3_flag_set(tp, FLASH);
Matt Carlsona1b950d2009-09-01 13:20:17 +000013270
13271 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13272 case FLASH_5717VENDOR_ATMEL_MDB021D:
Matt Carlson66ee33b2011-04-05 14:22:51 +000013273 /* Detect size with tg3_nvram_get_size() */
13274 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000013275 case FLASH_5717VENDOR_ATMEL_ADB021B:
13276 case FLASH_5717VENDOR_ATMEL_ADB021D:
13277 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13278 break;
13279 default:
13280 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13281 break;
13282 }
Matt Carlson321d32a2008-11-21 17:22:19 -080013283 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000013284 case FLASH_5717VENDOR_ST_M_M25PE10:
13285 case FLASH_5717VENDOR_ST_A_M25PE10:
13286 case FLASH_5717VENDOR_ST_M_M45PE10:
13287 case FLASH_5717VENDOR_ST_A_M45PE10:
13288 case FLASH_5717VENDOR_ST_M_M25PE20:
13289 case FLASH_5717VENDOR_ST_A_M25PE20:
13290 case FLASH_5717VENDOR_ST_M_M45PE20:
13291 case FLASH_5717VENDOR_ST_A_M45PE20:
13292 case FLASH_5717VENDOR_ST_25USPT:
13293 case FLASH_5717VENDOR_ST_45USPT:
13294 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000013295 tg3_flag_set(tp, NVRAM_BUFFERED);
13296 tg3_flag_set(tp, FLASH);
Matt Carlsona1b950d2009-09-01 13:20:17 +000013297
13298 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13299 case FLASH_5717VENDOR_ST_M_M25PE20:
Matt Carlsona1b950d2009-09-01 13:20:17 +000013300 case FLASH_5717VENDOR_ST_M_M45PE20:
Matt Carlson66ee33b2011-04-05 14:22:51 +000013301 /* Detect size with tg3_nvram_get_size() */
13302 break;
13303 case FLASH_5717VENDOR_ST_A_M25PE20:
Matt Carlsona1b950d2009-09-01 13:20:17 +000013304 case FLASH_5717VENDOR_ST_A_M45PE20:
13305 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13306 break;
13307 default:
13308 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13309 break;
13310 }
Matt Carlson321d32a2008-11-21 17:22:19 -080013311 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000013312 default:
Joe Perches63c3a662011-04-26 08:12:10 +000013313 tg3_flag_set(tp, NO_NVRAM);
Matt Carlsona1b950d2009-09-01 13:20:17 +000013314 return;
Matt Carlson321d32a2008-11-21 17:22:19 -080013315 }
Matt Carlsona1b950d2009-09-01 13:20:17 +000013316
13317 tg3_nvram_get_pagesize(tp, nvcfg1);
13318 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
Joe Perches63c3a662011-04-26 08:12:10 +000013319 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
Matt Carlson321d32a2008-11-21 17:22:19 -080013320}
13321
Matt Carlson9b91b5f2011-04-05 14:22:47 +000013322static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
13323{
13324 u32 nvcfg1, nvmpinstrp;
13325
13326 nvcfg1 = tr32(NVRAM_CFG1);
13327 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
13328
13329 switch (nvmpinstrp) {
13330 case FLASH_5720_EEPROM_HD:
13331 case FLASH_5720_EEPROM_LD:
13332 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013333 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000013334
13335 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13336 tw32(NVRAM_CFG1, nvcfg1);
13337 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
13338 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13339 else
13340 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
13341 return;
13342 case FLASH_5720VENDOR_M_ATMEL_DB011D:
13343 case FLASH_5720VENDOR_A_ATMEL_DB011B:
13344 case FLASH_5720VENDOR_A_ATMEL_DB011D:
13345 case FLASH_5720VENDOR_M_ATMEL_DB021D:
13346 case FLASH_5720VENDOR_A_ATMEL_DB021B:
13347 case FLASH_5720VENDOR_A_ATMEL_DB021D:
13348 case FLASH_5720VENDOR_M_ATMEL_DB041D:
13349 case FLASH_5720VENDOR_A_ATMEL_DB041B:
13350 case FLASH_5720VENDOR_A_ATMEL_DB041D:
13351 case FLASH_5720VENDOR_M_ATMEL_DB081D:
13352 case FLASH_5720VENDOR_A_ATMEL_DB081D:
13353 case FLASH_5720VENDOR_ATMEL_45USPT:
13354 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000013355 tg3_flag_set(tp, NVRAM_BUFFERED);
13356 tg3_flag_set(tp, FLASH);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000013357
13358 switch (nvmpinstrp) {
13359 case FLASH_5720VENDOR_M_ATMEL_DB021D:
13360 case FLASH_5720VENDOR_A_ATMEL_DB021B:
13361 case FLASH_5720VENDOR_A_ATMEL_DB021D:
13362 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13363 break;
13364 case FLASH_5720VENDOR_M_ATMEL_DB041D:
13365 case FLASH_5720VENDOR_A_ATMEL_DB041B:
13366 case FLASH_5720VENDOR_A_ATMEL_DB041D:
13367 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13368 break;
13369 case FLASH_5720VENDOR_M_ATMEL_DB081D:
13370 case FLASH_5720VENDOR_A_ATMEL_DB081D:
13371 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13372 break;
13373 default:
13374 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13375 break;
13376 }
13377 break;
13378 case FLASH_5720VENDOR_M_ST_M25PE10:
13379 case FLASH_5720VENDOR_M_ST_M45PE10:
13380 case FLASH_5720VENDOR_A_ST_M25PE10:
13381 case FLASH_5720VENDOR_A_ST_M45PE10:
13382 case FLASH_5720VENDOR_M_ST_M25PE20:
13383 case FLASH_5720VENDOR_M_ST_M45PE20:
13384 case FLASH_5720VENDOR_A_ST_M25PE20:
13385 case FLASH_5720VENDOR_A_ST_M45PE20:
13386 case FLASH_5720VENDOR_M_ST_M25PE40:
13387 case FLASH_5720VENDOR_M_ST_M45PE40:
13388 case FLASH_5720VENDOR_A_ST_M25PE40:
13389 case FLASH_5720VENDOR_A_ST_M45PE40:
13390 case FLASH_5720VENDOR_M_ST_M25PE80:
13391 case FLASH_5720VENDOR_M_ST_M45PE80:
13392 case FLASH_5720VENDOR_A_ST_M25PE80:
13393 case FLASH_5720VENDOR_A_ST_M45PE80:
13394 case FLASH_5720VENDOR_ST_25USPT:
13395 case FLASH_5720VENDOR_ST_45USPT:
13396 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000013397 tg3_flag_set(tp, NVRAM_BUFFERED);
13398 tg3_flag_set(tp, FLASH);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000013399
13400 switch (nvmpinstrp) {
13401 case FLASH_5720VENDOR_M_ST_M25PE20:
13402 case FLASH_5720VENDOR_M_ST_M45PE20:
13403 case FLASH_5720VENDOR_A_ST_M25PE20:
13404 case FLASH_5720VENDOR_A_ST_M45PE20:
13405 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13406 break;
13407 case FLASH_5720VENDOR_M_ST_M25PE40:
13408 case FLASH_5720VENDOR_M_ST_M45PE40:
13409 case FLASH_5720VENDOR_A_ST_M25PE40:
13410 case FLASH_5720VENDOR_A_ST_M45PE40:
13411 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13412 break;
13413 case FLASH_5720VENDOR_M_ST_M25PE80:
13414 case FLASH_5720VENDOR_M_ST_M45PE80:
13415 case FLASH_5720VENDOR_A_ST_M25PE80:
13416 case FLASH_5720VENDOR_A_ST_M45PE80:
13417 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13418 break;
13419 default:
13420 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13421 break;
13422 }
13423 break;
13424 default:
Joe Perches63c3a662011-04-26 08:12:10 +000013425 tg3_flag_set(tp, NO_NVRAM);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000013426 return;
13427 }
13428
13429 tg3_nvram_get_pagesize(tp, nvcfg1);
13430 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
Joe Perches63c3a662011-04-26 08:12:10 +000013431 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000013432}
13433
Linus Torvalds1da177e2005-04-16 15:20:36 -070013434/* Chips other than 5700/5701 use the NVRAM for fetching info. */
13435static void __devinit tg3_nvram_init(struct tg3 *tp)
13436{
Linus Torvalds1da177e2005-04-16 15:20:36 -070013437 tw32_f(GRC_EEPROM_ADDR,
13438 (EEPROM_ADDR_FSM_RESET |
13439 (EEPROM_DEFAULT_CLOCK_PERIOD <<
13440 EEPROM_ADDR_CLKPERD_SHIFT)));
13441
Michael Chan9d57f012006-12-07 00:23:25 -080013442 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013443
13444 /* Enable seeprom accesses. */
13445 tw32_f(GRC_LOCAL_CTRL,
13446 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
13447 udelay(100);
13448
13449 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13450 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
Joe Perches63c3a662011-04-26 08:12:10 +000013451 tg3_flag_set(tp, NVRAM);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013452
Michael Chanec41c7d2006-01-17 02:40:55 -080013453 if (tg3_nvram_lock(tp)) {
Matt Carlson5129c3a2010-04-05 10:19:23 +000013454 netdev_warn(tp->dev,
13455 "Cannot get nvram lock, %s failed\n",
Joe Perches05dbe002010-02-17 19:44:19 +000013456 __func__);
Michael Chanec41c7d2006-01-17 02:40:55 -080013457 return;
13458 }
Michael Chane6af3012005-04-21 17:12:05 -070013459 tg3_enable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013460
Matt Carlson989a9d22007-05-05 11:51:05 -070013461 tp->nvram_size = 0;
13462
Michael Chan361b4ac2005-04-21 17:11:21 -070013463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13464 tg3_get_5752_nvram_info(tp);
Michael Chand3c7b882006-03-23 01:28:25 -080013465 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13466 tg3_get_5755_nvram_info(tp);
Matt Carlsond30cdd22007-10-07 23:28:35 -070013467 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlson57e69832008-05-25 23:48:31 -070013468 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13469 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
Michael Chan1b277772006-03-20 22:27:48 -080013470 tg3_get_5787_nvram_info(tp);
Matt Carlson6b91fa02007-10-10 18:01:09 -070013471 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
13472 tg3_get_5761_nvram_info(tp);
Michael Chanb5d37722006-09-27 16:06:21 -070013473 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13474 tg3_get_5906_nvram_info(tp);
Matt Carlsonb703df62009-12-03 08:36:21 +000013475 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Matt Carlson55086ad2011-12-14 11:09:59 +000013476 tg3_flag(tp, 57765_CLASS))
Matt Carlson321d32a2008-11-21 17:22:19 -080013477 tg3_get_57780_nvram_info(tp);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000013478 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13479 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlsona1b950d2009-09-01 13:20:17 +000013480 tg3_get_5717_nvram_info(tp);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000013481 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13482 tg3_get_5720_nvram_info(tp);
Michael Chan361b4ac2005-04-21 17:11:21 -070013483 else
13484 tg3_get_nvram_info(tp);
13485
Matt Carlson989a9d22007-05-05 11:51:05 -070013486 if (tp->nvram_size == 0)
13487 tg3_get_nvram_size(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013488
Michael Chane6af3012005-04-21 17:12:05 -070013489 tg3_disable_nvram_access(tp);
Michael Chan381291b2005-12-13 21:08:21 -080013490 tg3_nvram_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013491
13492 } else {
Joe Perches63c3a662011-04-26 08:12:10 +000013493 tg3_flag_clear(tp, NVRAM);
13494 tg3_flag_clear(tp, NVRAM_BUFFERED);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013495
13496 tg3_get_eeprom_size(tp);
13497 }
13498}
13499
Linus Torvalds1da177e2005-04-16 15:20:36 -070013500struct subsys_tbl_ent {
13501 u16 subsys_vendor, subsys_devid;
13502 u32 phy_id;
13503};
13504
Matt Carlson24daf2b2010-02-17 15:17:02 +000013505static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013506 /* Broadcom boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000013507 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013508 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013509 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013510 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013511 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013512 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013513 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13514 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13515 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013516 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013517 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013518 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013519 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13520 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13521 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013522 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013523 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013524 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013525 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013526 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013527 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013528 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070013529
13530 /* 3com boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000013531 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013532 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013533 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013534 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013535 { TG3PCI_SUBVENDOR_ID_3COM,
13536 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13537 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013538 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013539 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000013540 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070013541
13542 /* DELL boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000013543 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000013544 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013545 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000013546 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013547 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000013548 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013549 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000013550 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070013551
13552 /* Compaq boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000013553 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000013554 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013555 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000013556 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013557 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13558 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
13559 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000013560 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000013561 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000013562 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070013563
13564 /* IBM boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000013565 { TG3PCI_SUBVENDOR_ID_IBM,
13566 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013567};
13568
Matt Carlson24daf2b2010-02-17 15:17:02 +000013569static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013570{
13571 int i;
13572
13573 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13574 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13575 tp->pdev->subsystem_vendor) &&
13576 (subsys_id_to_phy_id[i].subsys_devid ==
13577 tp->pdev->subsystem_device))
13578 return &subsys_id_to_phy_id[i];
13579 }
13580 return NULL;
13581}
13582
Michael Chan7d0c41e2005-04-21 17:06:20 -070013583static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013584{
Linus Torvalds1da177e2005-04-16 15:20:36 -070013585 u32 val;
David S. Millerf49639e2006-06-09 11:58:36 -070013586
Matt Carlson79eb6902010-02-17 15:17:03 +000013587 tp->phy_id = TG3_PHY_ID_INVALID;
Michael Chan7d0c41e2005-04-21 17:06:20 -070013588 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13589
Gary Zambranoa85feb82007-05-05 11:52:19 -070013590 /* Assume an onboard device and WOL capable by default. */
Joe Perches63c3a662011-04-26 08:12:10 +000013591 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13592 tg3_flag_set(tp, WOL_CAP);
David S. Miller72b845e2006-03-14 14:11:48 -080013593
Michael Chanb5d37722006-09-27 16:06:21 -070013594 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan9d26e212006-12-07 00:21:14 -080013595 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013596 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13597 tg3_flag_set(tp, IS_NIC);
Michael Chan9d26e212006-12-07 00:21:14 -080013598 }
Matt Carlson0527ba32007-10-10 18:03:30 -070013599 val = tr32(VCPU_CFGSHDW);
13600 if (val & VCPU_CFGSHDW_ASPM_DBNC)
Joe Perches63c3a662011-04-26 08:12:10 +000013601 tg3_flag_set(tp, ASPM_WORKAROUND);
Matt Carlson0527ba32007-10-10 18:03:30 -070013602 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
Rafael J. Wysocki6fdbab92011-04-28 11:02:15 +000013603 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013604 tg3_flag_set(tp, WOL_ENABLE);
Rafael J. Wysocki6fdbab92011-04-28 11:02:15 +000013605 device_set_wakeup_enable(&tp->pdev->dev, true);
13606 }
Matt Carlson05ac4cb2008-11-03 16:53:46 -080013607 goto done;
Michael Chanb5d37722006-09-27 16:06:21 -070013608 }
13609
Linus Torvalds1da177e2005-04-16 15:20:36 -070013610 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13611 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13612 u32 nic_cfg, led_cfg;
Matt Carlsona9daf362008-05-25 23:49:44 -070013613 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
Michael Chan7d0c41e2005-04-21 17:06:20 -070013614 int eeprom_phy_serdes = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013615
13616 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13617 tp->nic_sram_data_cfg = nic_cfg;
13618
13619 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13620 ver >>= NIC_SRAM_DATA_VER_SHIFT;
Matt Carlson6ff6f812011-05-19 12:12:54 +000013621 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13622 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13623 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070013624 (ver > 0) && (ver < 0x100))
13625 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13626
Matt Carlsona9daf362008-05-25 23:49:44 -070013627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13628 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13629
Linus Torvalds1da177e2005-04-16 15:20:36 -070013630 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13631 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13632 eeprom_phy_serdes = 1;
13633
13634 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13635 if (nic_phy_id != 0) {
13636 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13637 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13638
13639 eeprom_phy_id = (id1 >> 16) << 10;
13640 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13641 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13642 } else
13643 eeprom_phy_id = 0;
13644
Michael Chan7d0c41e2005-04-21 17:06:20 -070013645 tp->phy_id = eeprom_phy_id;
Michael Chan747e8f82005-07-25 12:33:22 -070013646 if (eeprom_phy_serdes) {
Joe Perches63c3a662011-04-26 08:12:10 +000013647 if (!tg3_flag(tp, 5705_PLUS))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013648 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Matt Carlsona50d0792010-06-05 17:24:37 +000013649 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013650 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
Michael Chan747e8f82005-07-25 12:33:22 -070013651 }
Michael Chan7d0c41e2005-04-21 17:06:20 -070013652
Joe Perches63c3a662011-04-26 08:12:10 +000013653 if (tg3_flag(tp, 5750_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -070013654 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13655 SHASTA_EXT_LED_MODE_MASK);
John W. Linvillecbf46852005-04-21 17:01:29 -070013656 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070013657 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13658
13659 switch (led_cfg) {
13660 default:
13661 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13662 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13663 break;
13664
13665 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13666 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13667 break;
13668
13669 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13670 tp->led_ctrl = LED_CTRL_MODE_MAC;
Michael Chan9ba27792005-06-06 15:16:20 -070013671
13672 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13673 * read on some older 5700/5701 bootcode.
13674 */
13675 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13676 ASIC_REV_5700 ||
13677 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13678 ASIC_REV_5701)
13679 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13680
Linus Torvalds1da177e2005-04-16 15:20:36 -070013681 break;
13682
13683 case SHASTA_EXT_LED_SHARED:
13684 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13685 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13686 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13687 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13688 LED_CTRL_MODE_PHY_2);
13689 break;
13690
13691 case SHASTA_EXT_LED_MAC:
13692 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13693 break;
13694
13695 case SHASTA_EXT_LED_COMBO:
13696 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13697 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13698 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13699 LED_CTRL_MODE_PHY_2);
13700 break;
13701
Stephen Hemminger855e1112008-04-16 16:37:28 -070013702 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013703
13704 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13705 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13706 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13707 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13708
Matt Carlsonb2a5c192008-04-03 21:44:44 -070013709 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13710 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
Matt Carlson5f608912007-11-12 21:17:07 -080013711
Michael Chan9d26e212006-12-07 00:21:14 -080013712 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
Joe Perches63c3a662011-04-26 08:12:10 +000013713 tg3_flag_set(tp, EEPROM_WRITE_PROT);
Michael Chan9d26e212006-12-07 00:21:14 -080013714 if ((tp->pdev->subsystem_vendor ==
13715 PCI_VENDOR_ID_ARIMA) &&
13716 (tp->pdev->subsystem_device == 0x205a ||
13717 tp->pdev->subsystem_device == 0x2063))
Joe Perches63c3a662011-04-26 08:12:10 +000013718 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
Michael Chan9d26e212006-12-07 00:21:14 -080013719 } else {
Joe Perches63c3a662011-04-26 08:12:10 +000013720 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13721 tg3_flag_set(tp, IS_NIC);
Michael Chan9d26e212006-12-07 00:21:14 -080013722 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013723
13724 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
Joe Perches63c3a662011-04-26 08:12:10 +000013725 tg3_flag_set(tp, ENABLE_ASF);
13726 if (tg3_flag(tp, 5750_PLUS))
13727 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013728 }
Matt Carlsonb2b98d42008-11-03 16:52:32 -080013729
13730 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
Joe Perches63c3a662011-04-26 08:12:10 +000013731 tg3_flag(tp, 5750_PLUS))
13732 tg3_flag_set(tp, ENABLE_APE);
Matt Carlsonb2b98d42008-11-03 16:52:32 -080013733
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013734 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
Gary Zambranoa85feb82007-05-05 11:52:19 -070013735 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
Joe Perches63c3a662011-04-26 08:12:10 +000013736 tg3_flag_clear(tp, WOL_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013737
Joe Perches63c3a662011-04-26 08:12:10 +000013738 if (tg3_flag(tp, WOL_CAP) &&
Rafael J. Wysocki6fdbab92011-04-28 11:02:15 +000013739 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013740 tg3_flag_set(tp, WOL_ENABLE);
Rafael J. Wysocki6fdbab92011-04-28 11:02:15 +000013741 device_set_wakeup_enable(&tp->pdev->dev, true);
13742 }
Matt Carlson0527ba32007-10-10 18:03:30 -070013743
Linus Torvalds1da177e2005-04-16 15:20:36 -070013744 if (cfg2 & (1 << 17))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013745 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013746
13747 /* serdes signal pre-emphasis in register 0x590 set by */
13748 /* bootcode if bit 18 is set */
13749 if (cfg2 & (1 << 18))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013750 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
Matt Carlson8ed5d972007-05-07 00:25:49 -070013751
Joe Perches63c3a662011-04-26 08:12:10 +000013752 if ((tg3_flag(tp, 57765_PLUS) ||
13753 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13754 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
Matt Carlson6833c042008-11-21 17:18:59 -080013755 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013756 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
Matt Carlson6833c042008-11-21 17:18:59 -080013757
Joe Perches63c3a662011-04-26 08:12:10 +000013758 if (tg3_flag(tp, PCI_EXPRESS) &&
Matt Carlson8c69b1e2010-08-02 11:26:00 +000013759 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Joe Perches63c3a662011-04-26 08:12:10 +000013760 !tg3_flag(tp, 57765_PLUS)) {
Matt Carlson8ed5d972007-05-07 00:25:49 -070013761 u32 cfg3;
13762
13763 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13764 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
Joe Perches63c3a662011-04-26 08:12:10 +000013765 tg3_flag_set(tp, ASPM_WORKAROUND);
Matt Carlson8ed5d972007-05-07 00:25:49 -070013766 }
Matt Carlsona9daf362008-05-25 23:49:44 -070013767
Matt Carlson14417062010-02-17 15:16:59 +000013768 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
Joe Perches63c3a662011-04-26 08:12:10 +000013769 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
Matt Carlsona9daf362008-05-25 23:49:44 -070013770 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
Joe Perches63c3a662011-04-26 08:12:10 +000013771 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
Matt Carlsona9daf362008-05-25 23:49:44 -070013772 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
Joe Perches63c3a662011-04-26 08:12:10 +000013773 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013774 }
Matt Carlson05ac4cb2008-11-03 16:53:46 -080013775done:
Joe Perches63c3a662011-04-26 08:12:10 +000013776 if (tg3_flag(tp, WOL_CAP))
Rafael J. Wysocki43067ed2011-02-10 06:53:09 +000013777 device_set_wakeup_enable(&tp->pdev->dev,
Joe Perches63c3a662011-04-26 08:12:10 +000013778 tg3_flag(tp, WOL_ENABLE));
Rafael J. Wysocki43067ed2011-02-10 06:53:09 +000013779 else
13780 device_set_wakeup_capable(&tp->pdev->dev, false);
Michael Chan7d0c41e2005-04-21 17:06:20 -070013781}
13782
Matt Carlsonb2a5c192008-04-03 21:44:44 -070013783static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13784{
13785 int i;
13786 u32 val;
13787
13788 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13789 tw32(OTP_CTRL, cmd);
13790
13791 /* Wait for up to 1 ms for command to execute. */
13792 for (i = 0; i < 100; i++) {
13793 val = tr32(OTP_STATUS);
13794 if (val & OTP_STATUS_CMD_DONE)
13795 break;
13796 udelay(10);
13797 }
13798
13799 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13800}
13801
13802/* Read the gphy configuration from the OTP region of the chip. The gphy
13803 * configuration is a 32-bit value that straddles the alignment boundary.
13804 * We do two 32-bit reads and then shift and merge the results.
13805 */
13806static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13807{
13808 u32 bhalf_otp, thalf_otp;
13809
13810 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13811
13812 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13813 return 0;
13814
13815 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13816
13817 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13818 return 0;
13819
13820 thalf_otp = tr32(OTP_READ_DATA);
13821
13822 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13823
13824 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13825 return 0;
13826
13827 bhalf_otp = tr32(OTP_READ_DATA);
13828
13829 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13830}
13831
Matt Carlsone256f8a2011-03-09 16:58:24 +000013832static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13833{
Hiroaki SHIMODA202ff1c2011-11-22 04:05:41 +000013834 u32 adv = ADVERTISED_Autoneg;
Matt Carlsone256f8a2011-03-09 16:58:24 +000013835
13836 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13837 adv |= ADVERTISED_1000baseT_Half |
13838 ADVERTISED_1000baseT_Full;
13839
13840 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13841 adv |= ADVERTISED_100baseT_Half |
13842 ADVERTISED_100baseT_Full |
13843 ADVERTISED_10baseT_Half |
13844 ADVERTISED_10baseT_Full |
13845 ADVERTISED_TP;
13846 else
13847 adv |= ADVERTISED_FIBRE;
13848
13849 tp->link_config.advertising = adv;
Matt Carlsone7405222012-02-13 15:20:16 +000013850 tp->link_config.speed = SPEED_UNKNOWN;
13851 tp->link_config.duplex = DUPLEX_UNKNOWN;
Matt Carlsone256f8a2011-03-09 16:58:24 +000013852 tp->link_config.autoneg = AUTONEG_ENABLE;
Matt Carlsone7405222012-02-13 15:20:16 +000013853 tp->link_config.active_speed = SPEED_UNKNOWN;
13854 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
Matt Carlson34655ad2012-02-22 12:35:18 +000013855
13856 tp->old_link = -1;
Matt Carlsone256f8a2011-03-09 16:58:24 +000013857}
13858
Michael Chan7d0c41e2005-04-21 17:06:20 -070013859static int __devinit tg3_phy_probe(struct tg3 *tp)
13860{
13861 u32 hw_phy_id_1, hw_phy_id_2;
13862 u32 hw_phy_id, hw_phy_id_masked;
13863 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013864
Matt Carlsone256f8a2011-03-09 16:58:24 +000013865 /* flow control autonegotiation is default behavior */
Joe Perches63c3a662011-04-26 08:12:10 +000013866 tg3_flag_set(tp, PAUSE_AUTONEG);
Matt Carlsone256f8a2011-03-09 16:58:24 +000013867 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13868
Michael Chan8151ad52012-07-29 19:15:41 +000013869 if (tg3_flag(tp, ENABLE_APE)) {
13870 switch (tp->pci_fn) {
13871 case 0:
13872 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
13873 break;
13874 case 1:
13875 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
13876 break;
13877 case 2:
13878 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
13879 break;
13880 case 3:
13881 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
13882 break;
13883 }
13884 }
13885
Joe Perches63c3a662011-04-26 08:12:10 +000013886 if (tg3_flag(tp, USE_PHYLIB))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070013887 return tg3_phy_init(tp);
13888
Linus Torvalds1da177e2005-04-16 15:20:36 -070013889 /* Reading the PHY ID register can conflict with ASF
Nick Andrew877d0312009-01-26 11:06:57 +010013890 * firmware access to the PHY hardware.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013891 */
13892 err = 0;
Joe Perches63c3a662011-04-26 08:12:10 +000013893 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
Matt Carlson79eb6902010-02-17 15:17:03 +000013894 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013895 } else {
13896 /* Now read the physical PHY_ID from the chip and verify
13897 * that it is sane. If it doesn't look good, we fall back
13898 * to either the hard-coded table based PHY_ID and failing
13899 * that the value found in the eeprom area.
13900 */
13901 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13902 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13903
13904 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13905 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13906 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13907
Matt Carlson79eb6902010-02-17 15:17:03 +000013908 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013909 }
13910
Matt Carlson79eb6902010-02-17 15:17:03 +000013911 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013912 tp->phy_id = hw_phy_id;
Matt Carlson79eb6902010-02-17 15:17:03 +000013913 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013914 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Michael Chanda6b2d02005-08-19 12:54:29 -070013915 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013916 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013917 } else {
Matt Carlson79eb6902010-02-17 15:17:03 +000013918 if (tp->phy_id != TG3_PHY_ID_INVALID) {
Michael Chan7d0c41e2005-04-21 17:06:20 -070013919 /* Do nothing, phy ID already set up in
13920 * tg3_get_eeprom_hw_cfg().
13921 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070013922 } else {
13923 struct subsys_tbl_ent *p;
13924
13925 /* No eeprom signature? Try the hardcoded
13926 * subsys device table.
13927 */
Matt Carlson24daf2b2010-02-17 15:17:02 +000013928 p = tg3_lookup_by_subsys(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013929 if (!p)
13930 return -ENODEV;
13931
13932 tp->phy_id = p->phy_id;
13933 if (!tp->phy_id ||
Matt Carlson79eb6902010-02-17 15:17:03 +000013934 tp->phy_id == TG3_PHY_ID_BCM8002)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013935 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013936 }
13937 }
13938
Matt Carlsona6b68da2010-12-06 08:28:52 +000013939 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
Matt Carlson5baa5e92011-07-20 10:20:53 +000013940 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13942 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
Matt Carlsona6b68da2010-12-06 08:28:52 +000013943 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13944 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13945 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
Matt Carlson52b02d02010-10-14 10:37:41 +000013946 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13947
Matt Carlsone256f8a2011-03-09 16:58:24 +000013948 tg3_phy_init_link_config(tp);
13949
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013950 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
Joe Perches63c3a662011-04-26 08:12:10 +000013951 !tg3_flag(tp, ENABLE_APE) &&
13952 !tg3_flag(tp, ENABLE_ASF)) {
Matt Carlsone2bf73e2011-12-08 14:40:15 +000013953 u32 bmsr, dummy;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013954
13955 tg3_readphy(tp, MII_BMSR, &bmsr);
13956 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13957 (bmsr & BMSR_LSTATUS))
13958 goto skip_phy_reset;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040013959
Linus Torvalds1da177e2005-04-16 15:20:36 -070013960 err = tg3_phy_reset(tp);
13961 if (err)
13962 return err;
13963
Matt Carlson42b64a42011-05-19 12:12:49 +000013964 tg3_phy_set_wirespeed(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013965
Matt Carlsone2bf73e2011-12-08 14:40:15 +000013966 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
Matt Carlson42b64a42011-05-19 12:12:49 +000013967 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13968 tp->link_config.flowctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013969
13970 tg3_writephy(tp, MII_BMCR,
13971 BMCR_ANENABLE | BMCR_ANRESTART);
13972 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013973 }
13974
13975skip_phy_reset:
Matt Carlson79eb6902010-02-17 15:17:03 +000013976 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013977 err = tg3_init_5401phy_dsp(tp);
13978 if (err)
13979 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013980
Linus Torvalds1da177e2005-04-16 15:20:36 -070013981 err = tg3_init_5401phy_dsp(tp);
13982 }
13983
Linus Torvalds1da177e2005-04-16 15:20:36 -070013984 return err;
13985}
13986
Matt Carlson184b8902010-04-05 10:19:25 +000013987static void __devinit tg3_read_vpd(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013988{
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013989 u8 *vpd_data;
Matt Carlson4181b2c2010-02-26 14:04:45 +000013990 unsigned int block_end, rosize, len;
Matt Carlson535a4902011-07-20 10:20:56 +000013991 u32 vpdlen;
Matt Carlson184b8902010-04-05 10:19:25 +000013992 int j, i = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013993
Matt Carlson535a4902011-07-20 10:20:56 +000013994 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013995 if (!vpd_data)
13996 goto out_no_vpd;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013997
Matt Carlson535a4902011-07-20 10:20:56 +000013998 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
Matt Carlson4181b2c2010-02-26 14:04:45 +000013999 if (i < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014000 goto out_not_found;
Matt Carlson4181b2c2010-02-26 14:04:45 +000014001
14002 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
14003 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
14004 i += PCI_VPD_LRDT_TAG_SIZE;
14005
Matt Carlson535a4902011-07-20 10:20:56 +000014006 if (block_end > vpdlen)
Matt Carlson4181b2c2010-02-26 14:04:45 +000014007 goto out_not_found;
14008
Matt Carlson184b8902010-04-05 10:19:25 +000014009 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
14010 PCI_VPD_RO_KEYWORD_MFR_ID);
14011 if (j > 0) {
14012 len = pci_vpd_info_field_size(&vpd_data[j]);
14013
14014 j += PCI_VPD_INFO_FLD_HDR_SIZE;
14015 if (j + len > block_end || len != 4 ||
14016 memcmp(&vpd_data[j], "1028", 4))
14017 goto partno;
14018
14019 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
14020 PCI_VPD_RO_KEYWORD_VENDOR0);
14021 if (j < 0)
14022 goto partno;
14023
14024 len = pci_vpd_info_field_size(&vpd_data[j]);
14025
14026 j += PCI_VPD_INFO_FLD_HDR_SIZE;
14027 if (j + len > block_end)
14028 goto partno;
14029
14030 memcpy(tp->fw_ver, &vpd_data[j], len);
Matt Carlson535a4902011-07-20 10:20:56 +000014031 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
Matt Carlson184b8902010-04-05 10:19:25 +000014032 }
14033
14034partno:
Matt Carlson4181b2c2010-02-26 14:04:45 +000014035 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
14036 PCI_VPD_RO_KEYWORD_PARTNO);
14037 if (i < 0)
14038 goto out_not_found;
14039
14040 len = pci_vpd_info_field_size(&vpd_data[i]);
14041
14042 i += PCI_VPD_INFO_FLD_HDR_SIZE;
14043 if (len > TG3_BPN_SIZE ||
Matt Carlson535a4902011-07-20 10:20:56 +000014044 (len + i) > vpdlen)
Matt Carlson4181b2c2010-02-26 14:04:45 +000014045 goto out_not_found;
14046
14047 memcpy(tp->board_part_number, &vpd_data[i], len);
14048
Linus Torvalds1da177e2005-04-16 15:20:36 -070014049out_not_found:
Matt Carlsona4a8bb12010-09-15 09:00:00 +000014050 kfree(vpd_data);
Matt Carlson37a949c2010-09-30 10:34:33 +000014051 if (tp->board_part_number[0])
Matt Carlsona4a8bb12010-09-15 09:00:00 +000014052 return;
14053
14054out_no_vpd:
Matt Carlson37a949c2010-09-30 10:34:33 +000014055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14056 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
14057 strcpy(tp->board_part_number, "BCM5717");
14058 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
14059 strcpy(tp->board_part_number, "BCM5718");
14060 else
14061 goto nomatch;
14062 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14063 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
14064 strcpy(tp->board_part_number, "BCM57780");
14065 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
14066 strcpy(tp->board_part_number, "BCM57760");
14067 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
14068 strcpy(tp->board_part_number, "BCM57790");
14069 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
14070 strcpy(tp->board_part_number, "BCM57788");
14071 else
14072 goto nomatch;
14073 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14074 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
14075 strcpy(tp->board_part_number, "BCM57761");
14076 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
14077 strcpy(tp->board_part_number, "BCM57765");
14078 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
14079 strcpy(tp->board_part_number, "BCM57781");
14080 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
14081 strcpy(tp->board_part_number, "BCM57785");
14082 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
14083 strcpy(tp->board_part_number, "BCM57791");
14084 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
14085 strcpy(tp->board_part_number, "BCM57795");
14086 else
14087 goto nomatch;
Matt Carlson55086ad2011-12-14 11:09:59 +000014088 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
14089 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
14090 strcpy(tp->board_part_number, "BCM57762");
14091 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
14092 strcpy(tp->board_part_number, "BCM57766");
14093 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
14094 strcpy(tp->board_part_number, "BCM57782");
14095 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
14096 strcpy(tp->board_part_number, "BCM57786");
14097 else
14098 goto nomatch;
Matt Carlson37a949c2010-09-30 10:34:33 +000014099 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chanb5d37722006-09-27 16:06:21 -070014100 strcpy(tp->board_part_number, "BCM95906");
Matt Carlson37a949c2010-09-30 10:34:33 +000014101 } else {
14102nomatch:
Michael Chanb5d37722006-09-27 16:06:21 -070014103 strcpy(tp->board_part_number, "none");
Matt Carlson37a949c2010-09-30 10:34:33 +000014104 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014105}
14106
Matt Carlson9c8a6202007-10-21 16:16:08 -070014107static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
14108{
14109 u32 val;
14110
Matt Carlsone4f34112009-02-25 14:25:00 +000014111 if (tg3_nvram_read(tp, offset, &val) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070014112 (val & 0xfc000000) != 0x0c000000 ||
Matt Carlsone4f34112009-02-25 14:25:00 +000014113 tg3_nvram_read(tp, offset + 4, &val) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070014114 val != 0)
14115 return 0;
14116
14117 return 1;
14118}
14119
Matt Carlsonacd9c112009-02-25 14:26:33 +000014120static void __devinit tg3_read_bc_ver(struct tg3 *tp)
14121{
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000014122 u32 val, offset, start, ver_offset;
Matt Carlson75f99362010-04-05 10:19:24 +000014123 int i, dst_off;
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000014124 bool newver = false;
Matt Carlsonacd9c112009-02-25 14:26:33 +000014125
14126 if (tg3_nvram_read(tp, 0xc, &offset) ||
14127 tg3_nvram_read(tp, 0x4, &start))
14128 return;
14129
14130 offset = tg3_nvram_logical_addr(tp, offset);
14131
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000014132 if (tg3_nvram_read(tp, offset, &val))
Matt Carlsonacd9c112009-02-25 14:26:33 +000014133 return;
14134
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000014135 if ((val & 0xfc000000) == 0x0c000000) {
14136 if (tg3_nvram_read(tp, offset + 4, &val))
Matt Carlsonacd9c112009-02-25 14:26:33 +000014137 return;
14138
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000014139 if (val == 0)
14140 newver = true;
14141 }
14142
Matt Carlson75f99362010-04-05 10:19:24 +000014143 dst_off = strlen(tp->fw_ver);
14144
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000014145 if (newver) {
Matt Carlson75f99362010-04-05 10:19:24 +000014146 if (TG3_VER_SIZE - dst_off < 16 ||
14147 tg3_nvram_read(tp, offset + 8, &ver_offset))
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000014148 return;
14149
14150 offset = offset + ver_offset - start;
14151 for (i = 0; i < 16; i += 4) {
14152 __be32 v;
14153 if (tg3_nvram_read_be32(tp, offset + i, &v))
14154 return;
14155
Matt Carlson75f99362010-04-05 10:19:24 +000014156 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000014157 }
14158 } else {
14159 u32 major, minor;
14160
14161 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
14162 return;
14163
14164 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
14165 TG3_NVM_BCVER_MAJSFT;
14166 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
Matt Carlson75f99362010-04-05 10:19:24 +000014167 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
14168 "v%d.%02d", major, minor);
Matt Carlsonacd9c112009-02-25 14:26:33 +000014169 }
14170}
14171
Matt Carlsona6f6cb12009-02-25 14:27:43 +000014172static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
14173{
14174 u32 val, major, minor;
14175
14176 /* Use native endian representation */
14177 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
14178 return;
14179
14180 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
14181 TG3_NVM_HWSB_CFG1_MAJSFT;
14182 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
14183 TG3_NVM_HWSB_CFG1_MINSFT;
14184
14185 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
14186}
14187
Matt Carlsondfe00d72008-11-21 17:19:41 -080014188static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
14189{
14190 u32 offset, major, minor, build;
14191
Matt Carlson75f99362010-04-05 10:19:24 +000014192 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
Matt Carlsondfe00d72008-11-21 17:19:41 -080014193
14194 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
14195 return;
14196
14197 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
14198 case TG3_EEPROM_SB_REVISION_0:
14199 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
14200 break;
14201 case TG3_EEPROM_SB_REVISION_2:
14202 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
14203 break;
14204 case TG3_EEPROM_SB_REVISION_3:
14205 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
14206 break;
Matt Carlsona4153d42010-02-17 15:16:56 +000014207 case TG3_EEPROM_SB_REVISION_4:
14208 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
14209 break;
14210 case TG3_EEPROM_SB_REVISION_5:
14211 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
14212 break;
Matt Carlsonbba226a2010-10-14 10:37:38 +000014213 case TG3_EEPROM_SB_REVISION_6:
14214 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
14215 break;
Matt Carlsondfe00d72008-11-21 17:19:41 -080014216 default:
14217 return;
14218 }
14219
Matt Carlsone4f34112009-02-25 14:25:00 +000014220 if (tg3_nvram_read(tp, offset, &val))
Matt Carlsondfe00d72008-11-21 17:19:41 -080014221 return;
14222
14223 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
14224 TG3_EEPROM_SB_EDH_BLD_SHFT;
14225 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
14226 TG3_EEPROM_SB_EDH_MAJ_SHFT;
14227 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
14228
14229 if (minor > 99 || build > 26)
14230 return;
14231
Matt Carlson75f99362010-04-05 10:19:24 +000014232 offset = strlen(tp->fw_ver);
14233 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
14234 " v%d.%02d", major, minor);
Matt Carlsondfe00d72008-11-21 17:19:41 -080014235
14236 if (build > 0) {
Matt Carlson75f99362010-04-05 10:19:24 +000014237 offset = strlen(tp->fw_ver);
14238 if (offset < TG3_VER_SIZE - 1)
14239 tp->fw_ver[offset] = 'a' + build - 1;
Matt Carlsondfe00d72008-11-21 17:19:41 -080014240 }
14241}
14242
Matt Carlsonacd9c112009-02-25 14:26:33 +000014243static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
Michael Chanc4e65752006-03-20 22:29:32 -080014244{
14245 u32 val, offset, start;
Matt Carlsonacd9c112009-02-25 14:26:33 +000014246 int i, vlen;
Matt Carlson9c8a6202007-10-21 16:16:08 -070014247
14248 for (offset = TG3_NVM_DIR_START;
14249 offset < TG3_NVM_DIR_END;
14250 offset += TG3_NVM_DIRENT_SIZE) {
Matt Carlsone4f34112009-02-25 14:25:00 +000014251 if (tg3_nvram_read(tp, offset, &val))
Matt Carlson9c8a6202007-10-21 16:16:08 -070014252 return;
14253
14254 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
14255 break;
14256 }
14257
14258 if (offset == TG3_NVM_DIR_END)
14259 return;
14260
Joe Perches63c3a662011-04-26 08:12:10 +000014261 if (!tg3_flag(tp, 5705_PLUS))
Matt Carlson9c8a6202007-10-21 16:16:08 -070014262 start = 0x08000000;
Matt Carlsone4f34112009-02-25 14:25:00 +000014263 else if (tg3_nvram_read(tp, offset - 4, &start))
Matt Carlson9c8a6202007-10-21 16:16:08 -070014264 return;
14265
Matt Carlsone4f34112009-02-25 14:25:00 +000014266 if (tg3_nvram_read(tp, offset + 4, &offset) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070014267 !tg3_fw_img_is_valid(tp, offset) ||
Matt Carlsone4f34112009-02-25 14:25:00 +000014268 tg3_nvram_read(tp, offset + 8, &val))
Matt Carlson9c8a6202007-10-21 16:16:08 -070014269 return;
14270
14271 offset += val - start;
14272
Matt Carlsonacd9c112009-02-25 14:26:33 +000014273 vlen = strlen(tp->fw_ver);
Matt Carlson9c8a6202007-10-21 16:16:08 -070014274
Matt Carlsonacd9c112009-02-25 14:26:33 +000014275 tp->fw_ver[vlen++] = ',';
14276 tp->fw_ver[vlen++] = ' ';
Matt Carlson9c8a6202007-10-21 16:16:08 -070014277
14278 for (i = 0; i < 4; i++) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000014279 __be32 v;
14280 if (tg3_nvram_read_be32(tp, offset, &v))
Matt Carlson9c8a6202007-10-21 16:16:08 -070014281 return;
14282
Al Virob9fc7dc2007-12-17 22:59:57 -080014283 offset += sizeof(v);
Matt Carlson9c8a6202007-10-21 16:16:08 -070014284
Matt Carlsonacd9c112009-02-25 14:26:33 +000014285 if (vlen > TG3_VER_SIZE - sizeof(v)) {
14286 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
Matt Carlson9c8a6202007-10-21 16:16:08 -070014287 break;
14288 }
14289
Matt Carlsonacd9c112009-02-25 14:26:33 +000014290 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
14291 vlen += sizeof(v);
Matt Carlson9c8a6202007-10-21 16:16:08 -070014292 }
Matt Carlsonacd9c112009-02-25 14:26:33 +000014293}
14294
Michael Chan165f4d12012-07-16 16:23:59 +000014295static void __devinit tg3_probe_ncsi(struct tg3 *tp)
Matt Carlson7fd76442009-02-25 14:27:20 +000014296{
Matt Carlson7fd76442009-02-25 14:27:20 +000014297 u32 apedata;
Matt Carlson7fd76442009-02-25 14:27:20 +000014298
14299 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
14300 if (apedata != APE_SEG_SIG_MAGIC)
14301 return;
14302
14303 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
14304 if (!(apedata & APE_FW_STATUS_READY))
14305 return;
14306
Michael Chan165f4d12012-07-16 16:23:59 +000014307 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
14308 tg3_flag_set(tp, APE_HAS_NCSI);
14309}
14310
14311static void __devinit tg3_read_dash_ver(struct tg3 *tp)
14312{
14313 int vlen;
14314 u32 apedata;
14315 char *fwtype;
14316
Matt Carlson7fd76442009-02-25 14:27:20 +000014317 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
14318
Michael Chan165f4d12012-07-16 16:23:59 +000014319 if (tg3_flag(tp, APE_HAS_NCSI))
Matt Carlsonecc79642010-08-02 11:26:01 +000014320 fwtype = "NCSI";
Michael Chan165f4d12012-07-16 16:23:59 +000014321 else
Matt Carlsonecc79642010-08-02 11:26:01 +000014322 fwtype = "DASH";
14323
Matt Carlson7fd76442009-02-25 14:27:20 +000014324 vlen = strlen(tp->fw_ver);
14325
Matt Carlsonecc79642010-08-02 11:26:01 +000014326 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
14327 fwtype,
Matt Carlson7fd76442009-02-25 14:27:20 +000014328 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
14329 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
14330 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
14331 (apedata & APE_FW_VERSION_BLDMSK));
14332}
14333
Matt Carlsonacd9c112009-02-25 14:26:33 +000014334static void __devinit tg3_read_fw_ver(struct tg3 *tp)
14335{
14336 u32 val;
Matt Carlson75f99362010-04-05 10:19:24 +000014337 bool vpd_vers = false;
14338
14339 if (tp->fw_ver[0] != 0)
14340 vpd_vers = true;
Matt Carlsonacd9c112009-02-25 14:26:33 +000014341
Joe Perches63c3a662011-04-26 08:12:10 +000014342 if (tg3_flag(tp, NO_NVRAM)) {
Matt Carlson75f99362010-04-05 10:19:24 +000014343 strcat(tp->fw_ver, "sb");
Matt Carlsondf259d82009-04-20 06:57:14 +000014344 return;
14345 }
14346
Matt Carlsonacd9c112009-02-25 14:26:33 +000014347 if (tg3_nvram_read(tp, 0, &val))
14348 return;
14349
14350 if (val == TG3_EEPROM_MAGIC)
14351 tg3_read_bc_ver(tp);
14352 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
14353 tg3_read_sb_ver(tp, val);
Matt Carlsona6f6cb12009-02-25 14:27:43 +000014354 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
14355 tg3_read_hwsb_ver(tp);
Matt Carlsonacd9c112009-02-25 14:26:33 +000014356
Michael Chan165f4d12012-07-16 16:23:59 +000014357 if (tg3_flag(tp, ENABLE_ASF)) {
14358 if (tg3_flag(tp, ENABLE_APE)) {
14359 tg3_probe_ncsi(tp);
14360 if (!vpd_vers)
14361 tg3_read_dash_ver(tp);
14362 } else if (!vpd_vers) {
14363 tg3_read_mgmtfw_ver(tp);
14364 }
Matt Carlsonc9cab242011-07-13 09:27:27 +000014365 }
Matt Carlson9c8a6202007-10-21 16:16:08 -070014366
14367 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
Michael Chanc4e65752006-03-20 22:29:32 -080014368}
14369
Matt Carlson7cb32cf2010-09-30 10:34:36 +000014370static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
14371{
Joe Perches63c3a662011-04-26 08:12:10 +000014372 if (tg3_flag(tp, LRG_PROD_RING_CAP))
Matt Carlsonde9f5232011-04-05 14:22:43 +000014373 return TG3_RX_RET_MAX_SIZE_5717;
Joe Perches63c3a662011-04-26 08:12:10 +000014374 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
Matt Carlsonde9f5232011-04-05 14:22:43 +000014375 return TG3_RX_RET_MAX_SIZE_5700;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000014376 else
Matt Carlsonde9f5232011-04-05 14:22:43 +000014377 return TG3_RX_RET_MAX_SIZE_5705;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000014378}
14379
Matt Carlson41434702011-03-09 16:58:22 +000014380static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
Joe Perches895950c2010-12-21 02:16:08 -080014381 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
14382 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
14383 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
14384 { },
14385};
14386
Matt Carlson16c7fa72012-02-13 10:20:10 +000014387static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14388{
14389 struct pci_dev *peer;
14390 unsigned int func, devnr = tp->pdev->devfn & ~7;
14391
14392 for (func = 0; func < 8; func++) {
14393 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14394 if (peer && peer != tp->pdev)
14395 break;
14396 pci_dev_put(peer);
14397 }
14398 /* 5704 can be configured in single-port mode, set peer to
14399 * tp->pdev in that case.
14400 */
14401 if (!peer) {
14402 peer = tp->pdev;
14403 return peer;
14404 }
14405
14406 /*
14407 * We don't need to keep the refcount elevated; there's no way
14408 * to remove one half of this device without removing the other
14409 */
14410 pci_dev_put(peer);
14411
14412 return peer;
14413}
14414
Matt Carlson42b123b2012-02-13 15:20:13 +000014415static void __devinit tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
14416{
14417 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
14418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
14419 u32 reg;
14420
14421 /* All devices that use the alternate
14422 * ASIC REV location have a CPMU.
14423 */
14424 tg3_flag_set(tp, CPMU_PRESENT);
14425
14426 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
14427 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
14428 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
14429 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
14430 reg = TG3PCI_GEN2_PRODID_ASICREV;
14431 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
14432 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
14433 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
14434 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
14435 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14436 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14437 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
14438 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
14439 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
14440 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
14441 reg = TG3PCI_GEN15_PRODID_ASICREV;
14442 else
14443 reg = TG3PCI_PRODID_ASICREV;
14444
14445 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
14446 }
14447
14448 /* Wrong chip ID in 5752 A0. This code can be removed later
14449 * as A0 is not in production.
14450 */
14451 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
14452 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
14453
14454 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14457 tg3_flag_set(tp, 5717_PLUS);
14458
14459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
14460 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14461 tg3_flag_set(tp, 57765_CLASS);
14462
14463 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
14464 tg3_flag_set(tp, 57765_PLUS);
14465
14466 /* Intentionally exclude ASIC_REV_5906 */
14467 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14468 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14469 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14470 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14471 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14473 tg3_flag(tp, 57765_PLUS))
14474 tg3_flag_set(tp, 5755_PLUS);
14475
14476 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
14477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14478 tg3_flag_set(tp, 5780_CLASS);
14479
14480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14481 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14482 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14483 tg3_flag(tp, 5755_PLUS) ||
14484 tg3_flag(tp, 5780_CLASS))
14485 tg3_flag_set(tp, 5750_PLUS);
14486
14487 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14488 tg3_flag(tp, 5750_PLUS))
14489 tg3_flag_set(tp, 5705_PLUS);
14490}
14491
Linus Torvalds1da177e2005-04-16 15:20:36 -070014492static int __devinit tg3_get_invariants(struct tg3 *tp)
14493{
Linus Torvalds1da177e2005-04-16 15:20:36 -070014494 u32 misc_ctrl_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014495 u32 pci_state_reg, grc_misc_cfg;
14496 u32 val;
14497 u16 pci_cmd;
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014498 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014499
Linus Torvalds1da177e2005-04-16 15:20:36 -070014500 /* Force memory write invalidate off. If we leave it on,
14501 * then on 5700_BX chips we have to enable a workaround.
14502 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
14503 * to match the cacheline size. The Broadcom driver have this
14504 * workaround but turns MWI off all the times so never uses
14505 * it. This seems to suggest that the workaround is insufficient.
14506 */
14507 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14508 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
14509 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14510
Matt Carlson16821282011-07-13 09:27:28 +000014511 /* Important! -- Make sure register accesses are byteswapped
14512 * correctly. Also, for those chips that require it, make
14513 * sure that indirect register accesses are enabled before
14514 * the first operation.
Linus Torvalds1da177e2005-04-16 15:20:36 -070014515 */
14516 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14517 &misc_ctrl_reg);
Matt Carlson16821282011-07-13 09:27:28 +000014518 tp->misc_host_ctrl |= (misc_ctrl_reg &
14519 MISC_HOST_CTRL_CHIPREV);
14520 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14521 tp->misc_host_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014522
Matt Carlson42b123b2012-02-13 15:20:13 +000014523 tg3_detect_asic_rev(tp, misc_ctrl_reg);
Michael Chanff645be2005-04-21 17:09:53 -070014524
Michael Chan68929142005-08-09 20:17:14 -070014525 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
14526 * we need to disable memory and use config. cycles
14527 * only to access all registers. The 5702/03 chips
14528 * can mistakenly decode the special cycles from the
14529 * ICH chipsets as memory write cycles, causing corruption
14530 * of register and memory space. Only certain ICH bridges
14531 * will drive special cycles with non-zero data during the
14532 * address phase which can fall within the 5703's address
14533 * range. This is not an ICH bug as the PCI spec allows
14534 * non-zero address during special cycles. However, only
14535 * these ICH bridges are known to drive non-zero addresses
14536 * during special cycles.
14537 *
14538 * Since special cycles do not cross PCI bridges, we only
14539 * enable this workaround if the 5703 is on the secondary
14540 * bus of these ICH bridges.
14541 */
14542 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
14543 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
14544 static struct tg3_dev_id {
14545 u32 vendor;
14546 u32 device;
14547 u32 rev;
14548 } ich_chipsets[] = {
14549 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
14550 PCI_ANY_ID },
14551 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
14552 PCI_ANY_ID },
14553 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
14554 0xa },
14555 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
14556 PCI_ANY_ID },
14557 { },
14558 };
14559 struct tg3_dev_id *pci_id = &ich_chipsets[0];
14560 struct pci_dev *bridge = NULL;
14561
14562 while (pci_id->vendor != 0) {
14563 bridge = pci_get_device(pci_id->vendor, pci_id->device,
14564 bridge);
14565 if (!bridge) {
14566 pci_id++;
14567 continue;
14568 }
14569 if (pci_id->rev != PCI_ANY_ID) {
Auke Kok44c10132007-06-08 15:46:36 -070014570 if (bridge->revision > pci_id->rev)
Michael Chan68929142005-08-09 20:17:14 -070014571 continue;
14572 }
14573 if (bridge->subordinate &&
14574 (bridge->subordinate->number ==
14575 tp->pdev->bus->number)) {
Joe Perches63c3a662011-04-26 08:12:10 +000014576 tg3_flag_set(tp, ICH_WORKAROUND);
Michael Chan68929142005-08-09 20:17:14 -070014577 pci_dev_put(bridge);
14578 break;
14579 }
14580 }
14581 }
14582
Matt Carlson6ff6f812011-05-19 12:12:54 +000014583 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
Matt Carlson41588ba2008-04-19 18:12:33 -070014584 static struct tg3_dev_id {
14585 u32 vendor;
14586 u32 device;
14587 } bridge_chipsets[] = {
14588 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
14589 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
14590 { },
14591 };
14592 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
14593 struct pci_dev *bridge = NULL;
14594
14595 while (pci_id->vendor != 0) {
14596 bridge = pci_get_device(pci_id->vendor,
14597 pci_id->device,
14598 bridge);
14599 if (!bridge) {
14600 pci_id++;
14601 continue;
14602 }
14603 if (bridge->subordinate &&
14604 (bridge->subordinate->number <=
14605 tp->pdev->bus->number) &&
Yinghai Lub918c622012-05-17 18:51:11 -070014606 (bridge->subordinate->busn_res.end >=
Matt Carlson41588ba2008-04-19 18:12:33 -070014607 tp->pdev->bus->number)) {
Joe Perches63c3a662011-04-26 08:12:10 +000014608 tg3_flag_set(tp, 5701_DMA_BUG);
Matt Carlson41588ba2008-04-19 18:12:33 -070014609 pci_dev_put(bridge);
14610 break;
14611 }
14612 }
14613 }
14614
Michael Chan4a29cc22006-03-19 13:21:12 -080014615 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
14616 * DMA addresses > 40-bit. This bridge may have other additional
14617 * 57xx devices behind it in some 4-port NIC designs for example.
14618 * Any tg3 device found behind the bridge will also need the 40-bit
14619 * DMA workaround.
14620 */
Matt Carlson42b123b2012-02-13 15:20:13 +000014621 if (tg3_flag(tp, 5780_CLASS)) {
Joe Perches63c3a662011-04-26 08:12:10 +000014622 tg3_flag_set(tp, 40BIT_DMA_BUG);
Michael Chan4cf78e42005-07-25 12:29:19 -070014623 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
Matt Carlson859a588792010-04-05 10:19:28 +000014624 } else {
Michael Chan4a29cc22006-03-19 13:21:12 -080014625 struct pci_dev *bridge = NULL;
14626
14627 do {
14628 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
14629 PCI_DEVICE_ID_SERVERWORKS_EPB,
14630 bridge);
14631 if (bridge && bridge->subordinate &&
14632 (bridge->subordinate->number <=
14633 tp->pdev->bus->number) &&
Yinghai Lub918c622012-05-17 18:51:11 -070014634 (bridge->subordinate->busn_res.end >=
Michael Chan4a29cc22006-03-19 13:21:12 -080014635 tp->pdev->bus->number)) {
Joe Perches63c3a662011-04-26 08:12:10 +000014636 tg3_flag_set(tp, 40BIT_DMA_BUG);
Michael Chan4a29cc22006-03-19 13:21:12 -080014637 pci_dev_put(bridge);
14638 break;
14639 }
14640 } while (bridge);
14641 }
Michael Chan4cf78e42005-07-25 12:29:19 -070014642
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000014643 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
Matt Carlson3a1e19d2011-07-13 09:27:32 +000014644 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
Michael Chan7544b092007-05-05 13:08:32 -070014645 tp->pdev_peer = tg3_find_peer(tp);
14646
Matt Carlson507399f2009-11-13 13:03:37 +000014647 /* Determine TSO capabilities */
Matt Carlsona0512942011-07-27 14:20:54 +000014648 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
Matt Carlson4d163b72011-01-25 15:58:48 +000014649 ; /* Do nothing. HW bug. */
Joe Perches63c3a662011-04-26 08:12:10 +000014650 else if (tg3_flag(tp, 57765_PLUS))
14651 tg3_flag_set(tp, HW_TSO_3);
14652 else if (tg3_flag(tp, 5755_PLUS) ||
Matt Carlsone849cdc2009-11-13 13:03:38 +000014653 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Joe Perches63c3a662011-04-26 08:12:10 +000014654 tg3_flag_set(tp, HW_TSO_2);
14655 else if (tg3_flag(tp, 5750_PLUS)) {
14656 tg3_flag_set(tp, HW_TSO_1);
14657 tg3_flag_set(tp, TSO_BUG);
Matt Carlson507399f2009-11-13 13:03:37 +000014658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14659 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
Joe Perches63c3a662011-04-26 08:12:10 +000014660 tg3_flag_clear(tp, TSO_BUG);
Matt Carlson507399f2009-11-13 13:03:37 +000014661 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14662 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14663 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
Joe Perches63c3a662011-04-26 08:12:10 +000014664 tg3_flag_set(tp, TSO_BUG);
Matt Carlson507399f2009-11-13 13:03:37 +000014665 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14666 tp->fw_needed = FIRMWARE_TG3TSO5;
14667 else
14668 tp->fw_needed = FIRMWARE_TG3TSO;
14669 }
14670
Matt Carlsondabc5c62011-05-19 12:12:52 +000014671 /* Selectively allow TSO based on operating conditions */
Matt Carlson6ff6f812011-05-19 12:12:54 +000014672 if (tg3_flag(tp, HW_TSO_1) ||
14673 tg3_flag(tp, HW_TSO_2) ||
14674 tg3_flag(tp, HW_TSO_3) ||
Matt Carlsoncf9ecf42011-11-28 09:41:03 +000014675 tp->fw_needed) {
14676 /* For firmware TSO, assume ASF is disabled.
14677 * We'll disable TSO later if we discover ASF
14678 * is enabled in tg3_get_eeprom_hw_cfg().
14679 */
Matt Carlsondabc5c62011-05-19 12:12:52 +000014680 tg3_flag_set(tp, TSO_CAPABLE);
Matt Carlsoncf9ecf42011-11-28 09:41:03 +000014681 } else {
Matt Carlsondabc5c62011-05-19 12:12:52 +000014682 tg3_flag_clear(tp, TSO_CAPABLE);
14683 tg3_flag_clear(tp, TSO_BUG);
14684 tp->fw_needed = NULL;
14685 }
14686
14687 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14688 tp->fw_needed = FIRMWARE_TG3;
14689
Matt Carlson507399f2009-11-13 13:03:37 +000014690 tp->irq_max = 1;
14691
Joe Perches63c3a662011-04-26 08:12:10 +000014692 if (tg3_flag(tp, 5750_PLUS)) {
14693 tg3_flag_set(tp, SUPPORT_MSI);
Michael Chan7544b092007-05-05 13:08:32 -070014694 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14695 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14696 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14697 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14698 tp->pdev_peer == tp->pdev))
Joe Perches63c3a662011-04-26 08:12:10 +000014699 tg3_flag_clear(tp, SUPPORT_MSI);
Michael Chan7544b092007-05-05 13:08:32 -070014700
Joe Perches63c3a662011-04-26 08:12:10 +000014701 if (tg3_flag(tp, 5755_PLUS) ||
Michael Chanb5d37722006-09-27 16:06:21 -070014702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Joe Perches63c3a662011-04-26 08:12:10 +000014703 tg3_flag_set(tp, 1SHOT_MSI);
Michael Chan52c0fd82006-06-29 20:15:54 -070014704 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014705
Joe Perches63c3a662011-04-26 08:12:10 +000014706 if (tg3_flag(tp, 57765_PLUS)) {
14707 tg3_flag_set(tp, SUPPORT_MSIX);
Matt Carlson507399f2009-11-13 13:03:37 +000014708 tp->irq_max = TG3_IRQ_MAX_VECS;
14709 }
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000014710 }
Matt Carlson0e1406d2009-11-02 12:33:33 +000014711
Michael Chan91024262012-09-28 07:12:38 +000014712 tp->txq_max = 1;
14713 tp->rxq_max = 1;
14714 if (tp->irq_max > 1) {
14715 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
14716 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
14717
14718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14719 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14720 tp->txq_max = tp->irq_max - 1;
14721 }
14722
Matt Carlsonb7abee62012-06-07 12:56:54 +000014723 if (tg3_flag(tp, 5755_PLUS) ||
14724 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Joe Perches63c3a662011-04-26 08:12:10 +000014725 tg3_flag_set(tp, SHORT_DMA_BUG);
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000014726
Matt Carlsone31aa982011-07-27 14:20:53 +000014727 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlsona4cb4282011-12-14 11:09:58 +000014728 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
Matt Carlsone31aa982011-07-27 14:20:53 +000014729
Matt Carlsonfa6b2aa2011-11-21 15:01:19 +000014730 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14731 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14732 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
Joe Perches63c3a662011-04-26 08:12:10 +000014733 tg3_flag_set(tp, LRG_PROD_RING_CAP);
Matt Carlsonde9f5232011-04-05 14:22:43 +000014734
Joe Perches63c3a662011-04-26 08:12:10 +000014735 if (tg3_flag(tp, 57765_PLUS) &&
Matt Carlsona0512942011-07-27 14:20:54 +000014736 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
Joe Perches63c3a662011-04-26 08:12:10 +000014737 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
Matt Carlsonb703df62009-12-03 08:36:21 +000014738
Joe Perches63c3a662011-04-26 08:12:10 +000014739 if (!tg3_flag(tp, 5705_PLUS) ||
14740 tg3_flag(tp, 5780_CLASS) ||
14741 tg3_flag(tp, USE_JUMBO_BDFLAG))
14742 tg3_flag_set(tp, JUMBO_CAPABLE);
Michael Chan0f893dc2005-07-25 12:30:38 -070014743
Matt Carlson52f44902008-11-21 17:17:04 -080014744 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14745 &pci_state_reg);
14746
Jon Mason708ebb3a2011-06-27 12:56:50 +000014747 if (pci_is_pcie(tp->pdev)) {
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014748 u16 lnkctl;
14749
Joe Perches63c3a662011-04-26 08:12:10 +000014750 tg3_flag_set(tp, PCI_EXPRESS);
Matt Carlson5f5c51e2007-11-12 21:19:37 -080014751
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014752 pci_read_config_word(tp->pdev,
Jon Mason708ebb3a2011-06-27 12:56:50 +000014753 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014754 &lnkctl);
14755 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
Matt Carlson7196cd62011-05-19 16:02:44 +000014756 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14757 ASIC_REV_5906) {
Joe Perches63c3a662011-04-26 08:12:10 +000014758 tg3_flag_clear(tp, HW_TSO_2);
Matt Carlsondabc5c62011-05-19 12:12:52 +000014759 tg3_flag_clear(tp, TSO_CAPABLE);
Matt Carlson7196cd62011-05-19 16:02:44 +000014760 }
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080014762 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson9cf74eb2009-04-20 06:58:27 +000014763 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14764 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
Joe Perches63c3a662011-04-26 08:12:10 +000014765 tg3_flag_set(tp, CLKREQ_BUG);
Matt Carlson614b0592010-01-20 16:58:02 +000014766 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
Joe Perches63c3a662011-04-26 08:12:10 +000014767 tg3_flag_set(tp, L1PLLPD_EN);
Michael Chanc7835a72006-11-15 21:14:42 -080014768 }
Matt Carlson52f44902008-11-21 17:17:04 -080014769 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
Jon Mason708ebb3a2011-06-27 12:56:50 +000014770 /* BCM5785 devices are effectively PCIe devices, and should
14771 * follow PCIe codepaths, but do not have a PCIe capabilities
14772 * section.
Matt Carlson93a700a2011-08-31 11:44:54 +000014773 */
Joe Perches63c3a662011-04-26 08:12:10 +000014774 tg3_flag_set(tp, PCI_EXPRESS);
14775 } else if (!tg3_flag(tp, 5705_PLUS) ||
14776 tg3_flag(tp, 5780_CLASS)) {
Matt Carlson52f44902008-11-21 17:17:04 -080014777 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14778 if (!tp->pcix_cap) {
Matt Carlson2445e462010-04-05 10:19:21 +000014779 dev_err(&tp->pdev->dev,
14780 "Cannot find PCI-X capability, aborting\n");
Matt Carlson52f44902008-11-21 17:17:04 -080014781 return -EIO;
14782 }
14783
14784 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
Joe Perches63c3a662011-04-26 08:12:10 +000014785 tg3_flag_set(tp, PCIX_MODE);
Matt Carlson52f44902008-11-21 17:17:04 -080014786 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014787
Michael Chan399de502005-10-03 14:02:39 -070014788 /* If we have an AMD 762 or VIA K8T800 chipset, write
14789 * reordering to the mailbox registers done by the host
14790 * controller can cause major troubles. We read back from
14791 * every mailbox register write to force the writes to be
14792 * posted to the chip in order.
14793 */
Matt Carlson41434702011-03-09 16:58:22 +000014794 if (pci_dev_present(tg3_write_reorder_chipsets) &&
Joe Perches63c3a662011-04-26 08:12:10 +000014795 !tg3_flag(tp, PCI_EXPRESS))
14796 tg3_flag_set(tp, MBOX_WRITE_REORDER);
Michael Chan399de502005-10-03 14:02:39 -070014797
Matt Carlson69fc4052008-12-21 20:19:57 -080014798 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14799 &tp->pci_cacheline_sz);
14800 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14801 &tp->pci_lat_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014802 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14803 tp->pci_lat_timer < 64) {
14804 tp->pci_lat_timer = 64;
Matt Carlson69fc4052008-12-21 20:19:57 -080014805 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14806 tp->pci_lat_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014807 }
14808
Matt Carlson16821282011-07-13 09:27:28 +000014809 /* Important! -- It is critical that the PCI-X hw workaround
14810 * situation is decided before the first MMIO register access.
14811 */
Matt Carlson52f44902008-11-21 17:17:04 -080014812 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14813 /* 5700 BX chips need to have their TX producer index
14814 * mailboxes written twice to workaround a bug.
14815 */
Joe Perches63c3a662011-04-26 08:12:10 +000014816 tg3_flag_set(tp, TXD_MBOX_HWBUG);
Matt Carlson9974a352007-10-07 23:27:28 -070014817
Matt Carlson52f44902008-11-21 17:17:04 -080014818 /* If we are in PCI-X mode, enable register write workaround.
Linus Torvalds1da177e2005-04-16 15:20:36 -070014819 *
14820 * The workaround is to use indirect register accesses
14821 * for all chip writes not to mailbox registers.
14822 */
Joe Perches63c3a662011-04-26 08:12:10 +000014823 if (tg3_flag(tp, PCIX_MODE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070014824 u32 pm_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014825
Joe Perches63c3a662011-04-26 08:12:10 +000014826 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014827
14828 /* The chip can have it's power management PCI config
14829 * space registers clobbered due to this bug.
14830 * So explicitly force the chip into D0 here.
14831 */
Matt Carlson9974a352007-10-07 23:27:28 -070014832 pci_read_config_dword(tp->pdev,
14833 tp->pm_cap + PCI_PM_CTRL,
Linus Torvalds1da177e2005-04-16 15:20:36 -070014834 &pm_reg);
14835 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14836 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
Matt Carlson9974a352007-10-07 23:27:28 -070014837 pci_write_config_dword(tp->pdev,
14838 tp->pm_cap + PCI_PM_CTRL,
Linus Torvalds1da177e2005-04-16 15:20:36 -070014839 pm_reg);
14840
14841 /* Also, force SERR#/PERR# in PCI command. */
14842 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14843 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14844 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14845 }
14846 }
14847
Linus Torvalds1da177e2005-04-16 15:20:36 -070014848 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
Joe Perches63c3a662011-04-26 08:12:10 +000014849 tg3_flag_set(tp, PCI_HIGH_SPEED);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014850 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
Joe Perches63c3a662011-04-26 08:12:10 +000014851 tg3_flag_set(tp, PCI_32BIT);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014852
14853 /* Chip-specific fixup from Broadcom driver */
14854 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14855 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14856 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14857 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14858 }
14859
Michael Chan1ee582d2005-08-09 20:16:46 -070014860 /* Default fast path register access methods */
Michael Chan20094932005-08-09 20:16:32 -070014861 tp->read32 = tg3_read32;
Michael Chan1ee582d2005-08-09 20:16:46 -070014862 tp->write32 = tg3_write32;
Michael Chan09ee9292005-08-09 20:17:00 -070014863 tp->read32_mbox = tg3_read32;
Michael Chan20094932005-08-09 20:16:32 -070014864 tp->write32_mbox = tg3_write32;
Michael Chan1ee582d2005-08-09 20:16:46 -070014865 tp->write32_tx_mbox = tg3_write32;
14866 tp->write32_rx_mbox = tg3_write32;
14867
14868 /* Various workaround register access methods */
Joe Perches63c3a662011-04-26 08:12:10 +000014869 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
Michael Chan1ee582d2005-08-09 20:16:46 -070014870 tp->write32 = tg3_write_indirect_reg32;
Matt Carlson98efd8a2007-05-05 12:47:25 -070014871 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
Joe Perches63c3a662011-04-26 08:12:10 +000014872 (tg3_flag(tp, PCI_EXPRESS) &&
Matt Carlson98efd8a2007-05-05 12:47:25 -070014873 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14874 /*
14875 * Back to back register writes can cause problems on these
14876 * chips, the workaround is to read back all reg writes
14877 * except those to mailbox regs.
14878 *
14879 * See tg3_write_indirect_reg32().
14880 */
Michael Chan1ee582d2005-08-09 20:16:46 -070014881 tp->write32 = tg3_write_flush_reg32;
Matt Carlson98efd8a2007-05-05 12:47:25 -070014882 }
14883
Joe Perches63c3a662011-04-26 08:12:10 +000014884 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
Michael Chan1ee582d2005-08-09 20:16:46 -070014885 tp->write32_tx_mbox = tg3_write32_tx_mbox;
Joe Perches63c3a662011-04-26 08:12:10 +000014886 if (tg3_flag(tp, MBOX_WRITE_REORDER))
Michael Chan1ee582d2005-08-09 20:16:46 -070014887 tp->write32_rx_mbox = tg3_write_flush_reg32;
14888 }
Michael Chan20094932005-08-09 20:16:32 -070014889
Joe Perches63c3a662011-04-26 08:12:10 +000014890 if (tg3_flag(tp, ICH_WORKAROUND)) {
Michael Chan68929142005-08-09 20:17:14 -070014891 tp->read32 = tg3_read_indirect_reg32;
14892 tp->write32 = tg3_write_indirect_reg32;
14893 tp->read32_mbox = tg3_read_indirect_mbox;
14894 tp->write32_mbox = tg3_write_indirect_mbox;
14895 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14896 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14897
14898 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070014899 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070014900
14901 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14902 pci_cmd &= ~PCI_COMMAND_MEMORY;
14903 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14904 }
Michael Chanb5d37722006-09-27 16:06:21 -070014905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14906 tp->read32_mbox = tg3_read32_mbox_5906;
14907 tp->write32_mbox = tg3_write32_mbox_5906;
14908 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14909 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14910 }
Michael Chan68929142005-08-09 20:17:14 -070014911
Michael Chanbbadf502006-04-06 21:46:34 -070014912 if (tp->write32 == tg3_write_indirect_reg32 ||
Joe Perches63c3a662011-04-26 08:12:10 +000014913 (tg3_flag(tp, PCIX_MODE) &&
Michael Chanbbadf502006-04-06 21:46:34 -070014914 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
David S. Millerf49639e2006-06-09 11:58:36 -070014915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
Joe Perches63c3a662011-04-26 08:12:10 +000014916 tg3_flag_set(tp, SRAM_USE_CONFIG);
Michael Chanbbadf502006-04-06 21:46:34 -070014917
Matt Carlson16821282011-07-13 09:27:28 +000014918 /* The memory arbiter has to be enabled in order for SRAM accesses
14919 * to succeed. Normally on powerup the tg3 chip firmware will make
14920 * sure it is enabled, but other entities such as system netboot
14921 * code might disable it.
14922 */
14923 val = tr32(MEMARB_MODE);
14924 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14925
Matt Carlson9dc5e342011-11-04 09:15:02 +000014926 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14928 tg3_flag(tp, 5780_CLASS)) {
14929 if (tg3_flag(tp, PCIX_MODE)) {
14930 pci_read_config_dword(tp->pdev,
14931 tp->pcix_cap + PCI_X_STATUS,
14932 &val);
14933 tp->pci_fn = val & 0x7;
14934 }
14935 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14936 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14937 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14938 NIC_SRAM_CPMUSTAT_SIG) {
14939 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14940 tp->pci_fn = tp->pci_fn ? 1 : 0;
14941 }
14942 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14944 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14945 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14946 NIC_SRAM_CPMUSTAT_SIG) {
14947 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14948 TG3_CPMU_STATUS_FSHFT_5719;
14949 }
Matt Carlson69f11c92011-07-13 09:27:30 +000014950 }
14951
Michael Chan7d0c41e2005-04-21 17:06:20 -070014952 /* Get eeprom hw config before calling tg3_set_power_state().
Joe Perches63c3a662011-04-26 08:12:10 +000014953 * In particular, the TG3_FLAG_IS_NIC flag must be
Michael Chan7d0c41e2005-04-21 17:06:20 -070014954 * determined before calling tg3_set_power_state() so that
14955 * we know whether or not to switch out of Vaux power.
14956 * When the flag is set, it means that GPIO1 is used for eeprom
14957 * write protect and also implies that it is a LOM where GPIOs
14958 * are not used to switch power.
Jeff Garzik6aa20a22006-09-13 13:24:59 -040014959 */
Michael Chan7d0c41e2005-04-21 17:06:20 -070014960 tg3_get_eeprom_hw_cfg(tp);
14961
Matt Carlsoncf9ecf42011-11-28 09:41:03 +000014962 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14963 tg3_flag_clear(tp, TSO_CAPABLE);
14964 tg3_flag_clear(tp, TSO_BUG);
14965 tp->fw_needed = NULL;
14966 }
14967
Joe Perches63c3a662011-04-26 08:12:10 +000014968 if (tg3_flag(tp, ENABLE_APE)) {
Matt Carlson0d3031d2007-10-10 18:02:43 -070014969 /* Allow reads and writes to the
14970 * APE register and memory space.
14971 */
14972 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +000014973 PCISTATE_ALLOW_APE_SHMEM_WR |
14974 PCISTATE_ALLOW_APE_PSPACE_WR;
Matt Carlson0d3031d2007-10-10 18:02:43 -070014975 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14976 pci_state_reg);
Matt Carlsonc9cab242011-07-13 09:27:27 +000014977
14978 tg3_ape_lock_init(tp);
Matt Carlson0d3031d2007-10-10 18:02:43 -070014979 }
14980
Matt Carlson16821282011-07-13 09:27:28 +000014981 /* Set up tp->grc_local_ctrl before calling
14982 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14983 * will bring 5700's external PHY out of reset.
Michael Chan314fba32005-04-21 17:07:04 -070014984 * It is also used as eeprom write protect on LOMs.
14985 */
14986 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
Matt Carlson6ff6f812011-05-19 12:12:54 +000014987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
Joe Perches63c3a662011-04-26 08:12:10 +000014988 tg3_flag(tp, EEPROM_WRITE_PROT))
Michael Chan314fba32005-04-21 17:07:04 -070014989 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14990 GRC_LCLCTRL_GPIO_OUTPUT1);
Michael Chan3e7d83b2005-04-21 17:10:36 -070014991 /* Unused GPIO3 must be driven as output on 5752 because there
14992 * are no pull-up resistors on unused GPIO pins.
14993 */
14994 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14995 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
Michael Chan314fba32005-04-21 17:07:04 -070014996
Matt Carlson321d32a2008-11-21 17:22:19 -080014997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlsoncb4ed1f2010-01-20 16:58:09 +000014998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Matt Carlson55086ad2011-12-14 11:09:59 +000014999 tg3_flag(tp, 57765_CLASS))
Michael Chanaf36e6b2006-03-23 01:28:06 -080015000 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
15001
Matt Carlson8d519ab2009-04-20 06:58:01 +000015002 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15003 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
Matt Carlson5f0c4a32008-06-09 15:41:12 -070015004 /* Turn off the debug UART. */
15005 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
Joe Perches63c3a662011-04-26 08:12:10 +000015006 if (tg3_flag(tp, IS_NIC))
Matt Carlson5f0c4a32008-06-09 15:41:12 -070015007 /* Keep VMain power. */
15008 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
15009 GRC_LCLCTRL_GPIO_OUTPUT0;
15010 }
15011
Matt Carlson16821282011-07-13 09:27:28 +000015012 /* Switch out of Vaux if it is a NIC */
15013 tg3_pwrsrc_switch_to_vmain(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015014
Linus Torvalds1da177e2005-04-16 15:20:36 -070015015 /* Derive initial jumbo mode from MTU assigned in
15016 * ether_setup() via the alloc_etherdev() call
15017 */
Joe Perches63c3a662011-04-26 08:12:10 +000015018 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
15019 tg3_flag_set(tp, JUMBO_RING_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015020
15021 /* Determine WakeOnLan speed to use. */
15022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15023 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
15024 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
15025 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
Joe Perches63c3a662011-04-26 08:12:10 +000015026 tg3_flag_clear(tp, WOL_SPEED_100MB);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015027 } else {
Joe Perches63c3a662011-04-26 08:12:10 +000015028 tg3_flag_set(tp, WOL_SPEED_100MB);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015029 }
15030
Matt Carlson7f97a4b2009-08-25 10:10:03 +000015031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015032 tp->phy_flags |= TG3_PHYFLG_IS_FET;
Matt Carlson7f97a4b2009-08-25 10:10:03 +000015033
Linus Torvalds1da177e2005-04-16 15:20:36 -070015034 /* A few boards don't want Ethernet@WireSpeed phy feature */
Matt Carlson6ff6f812011-05-19 12:12:54 +000015035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15036 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070015037 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
Michael Chan747e8f82005-07-25 12:33:22 -070015038 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015039 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
15040 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15041 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015042
15043 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
15044 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015045 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015046 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015047 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015048
Joe Perches63c3a662011-04-26 08:12:10 +000015049 if (tg3_flag(tp, 5705_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015050 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
Matt Carlson321d32a2008-11-21 17:22:19 -080015051 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000015052 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
Joe Perches63c3a662011-04-26 08:12:10 +000015053 !tg3_flag(tp, 57765_PLUS)) {
Michael Chanc424cb22006-04-29 18:56:34 -070015054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlsond30cdd22007-10-07 23:28:35 -070015055 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlson9936bcf2007-10-10 18:03:07 -070015056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
15057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
Michael Chand4011ad2007-02-13 12:17:25 -080015058 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
15059 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015060 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
Michael Chanc1d2a192007-01-08 19:57:20 -080015061 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015062 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
Matt Carlson321d32a2008-11-21 17:22:19 -080015063 } else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015064 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
Michael Chanc424cb22006-04-29 18:56:34 -070015065 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015066
Matt Carlsonb2a5c192008-04-03 21:44:44 -070015067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15068 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
15069 tp->phy_otp = tg3_read_otp_phycfg(tp);
15070 if (tp->phy_otp == 0)
15071 tp->phy_otp = TG3_OTP_DEFAULT;
15072 }
15073
Joe Perches63c3a662011-04-26 08:12:10 +000015074 if (tg3_flag(tp, CPMU_PRESENT))
Matt Carlson8ef21422008-05-02 16:47:53 -070015075 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
15076 else
15077 tp->mi_mode = MAC_MI_MODE_BASE;
15078
Linus Torvalds1da177e2005-04-16 15:20:36 -070015079 tp->coalesce_mode = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015080 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
15081 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
15082 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
15083
Matt Carlson4d958472011-04-20 07:57:35 +000015084 /* Set these bits to enable statistics workaround. */
15085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
15086 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
15087 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
15088 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
15089 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
15090 }
15091
Matt Carlson321d32a2008-11-21 17:22:19 -080015092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Joe Perches63c3a662011-04-26 08:12:10 +000015094 tg3_flag_set(tp, USE_PHYLIB);
Matt Carlson57e69832008-05-25 23:48:31 -070015095
Matt Carlson158d7ab2008-05-29 01:37:54 -070015096 err = tg3_mdio_init(tp);
15097 if (err)
15098 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015099
15100 /* Initialize data/descriptor byte/word swapping. */
15101 val = tr32(GRC_MODE);
Matt Carlsonf2096f92011-04-05 14:22:48 +000015102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
15103 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
15104 GRC_MODE_WORD_SWAP_B2HRX_DATA |
15105 GRC_MODE_B2HRX_ENABLE |
15106 GRC_MODE_HTX2B_ENABLE |
15107 GRC_MODE_HOST_STACKUP);
15108 else
15109 val &= GRC_MODE_HOST_STACKUP;
15110
Linus Torvalds1da177e2005-04-16 15:20:36 -070015111 tw32(GRC_MODE, val | tp->grc_mode);
15112
15113 tg3_switch_clocks(tp);
15114
15115 /* Clear this out for sanity. */
15116 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
15117
15118 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
15119 &pci_state_reg);
15120 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
Joe Perches63c3a662011-04-26 08:12:10 +000015121 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070015122 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
15123
15124 if (chiprevid == CHIPREV_ID_5701_A0 ||
15125 chiprevid == CHIPREV_ID_5701_B0 ||
15126 chiprevid == CHIPREV_ID_5701_B2 ||
15127 chiprevid == CHIPREV_ID_5701_B5) {
15128 void __iomem *sram_base;
15129
15130 /* Write some dummy words into the SRAM status block
15131 * area, see if it reads back correctly. If the return
15132 * value is bad, force enable the PCIX workaround.
15133 */
15134 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
15135
15136 writel(0x00000000, sram_base);
15137 writel(0x00000000, sram_base + 4);
15138 writel(0xffffffff, sram_base + 4);
15139 if (readl(sram_base) != 0x00000000)
Joe Perches63c3a662011-04-26 08:12:10 +000015140 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015141 }
15142 }
15143
15144 udelay(50);
15145 tg3_nvram_init(tp);
15146
15147 grc_misc_cfg = tr32(GRC_MISC_CFG);
15148 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
15149
Linus Torvalds1da177e2005-04-16 15:20:36 -070015150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
15151 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
15152 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
Joe Perches63c3a662011-04-26 08:12:10 +000015153 tg3_flag_set(tp, IS_5788);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015154
Joe Perches63c3a662011-04-26 08:12:10 +000015155 if (!tg3_flag(tp, IS_5788) &&
Matt Carlson6ff6f812011-05-19 12:12:54 +000015156 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
Joe Perches63c3a662011-04-26 08:12:10 +000015157 tg3_flag_set(tp, TAGGED_STATUS);
15158 if (tg3_flag(tp, TAGGED_STATUS)) {
David S. Millerfac9b832005-05-18 22:46:34 -070015159 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
15160 HOSTCC_MODE_CLRTICK_TXBD);
15161
15162 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
15163 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15164 tp->misc_host_ctrl);
15165 }
15166
Matt Carlson3bda1252008-08-15 14:08:22 -070015167 /* Preserve the APE MAC_MODE bits */
Joe Perches63c3a662011-04-26 08:12:10 +000015168 if (tg3_flag(tp, ENABLE_APE))
Matt Carlsond2394e6b2010-11-24 08:31:47 +000015169 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
Matt Carlson3bda1252008-08-15 14:08:22 -070015170 else
Matt Carlson6e01b202011-08-19 13:58:20 +000015171 tp->mac_mode = 0;
Matt Carlson3bda1252008-08-15 14:08:22 -070015172
Linus Torvalds1da177e2005-04-16 15:20:36 -070015173 /* these are limited to 10/100 only */
15174 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
15175 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
15176 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
15177 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
15178 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
15179 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
15180 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
15181 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
15182 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
Michael Chan676917d2006-12-07 00:20:22 -080015183 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
15184 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
Matt Carlson321d32a2008-11-21 17:22:19 -080015185 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
Matt Carlsond1101142010-02-17 15:16:55 +000015186 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15187 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015188 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15189 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015190
15191 err = tg3_phy_probe(tp);
15192 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000015193 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015194 /* ... but do not return immediately ... */
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015195 tg3_mdio_fini(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015196 }
15197
Matt Carlson184b8902010-04-05 10:19:25 +000015198 tg3_read_vpd(tp);
Michael Chanc4e65752006-03-20 22:29:32 -080015199 tg3_read_fw_ver(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015200
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015201 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
15202 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015203 } else {
15204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015205 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015206 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015207 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015208 }
15209
15210 /* 5700 {AX,BX} chips have a broken status block link
15211 * change bit implementation, so we must use the
15212 * status register in those cases.
15213 */
15214 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
Joe Perches63c3a662011-04-26 08:12:10 +000015215 tg3_flag_set(tp, USE_LINKCHG_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015216 else
Joe Perches63c3a662011-04-26 08:12:10 +000015217 tg3_flag_clear(tp, USE_LINKCHG_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015218
15219 /* The led_ctrl is set during tg3_phy_probe, here we might
15220 * have to force the link status polling mechanism based
15221 * upon subsystem IDs.
15222 */
15223 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
Michael Chan007a880d2007-05-31 14:49:51 -070015224 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015225 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
15226 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
Joe Perches63c3a662011-04-26 08:12:10 +000015227 tg3_flag_set(tp, USE_LINKCHG_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015228 }
15229
15230 /* For all SERDES we poll the MAC status register. */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015231 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Joe Perches63c3a662011-04-26 08:12:10 +000015232 tg3_flag_set(tp, POLL_SERDES);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015233 else
Joe Perches63c3a662011-04-26 08:12:10 +000015234 tg3_flag_clear(tp, POLL_SERDES);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015235
Eric Dumazet9205fd92011-11-18 06:47:01 +000015236 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
Matt Carlsond2757fc2010-04-12 06:58:27 +000015237 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015238 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
Joe Perches63c3a662011-04-26 08:12:10 +000015239 tg3_flag(tp, PCIX_MODE)) {
Eric Dumazet9205fd92011-11-18 06:47:01 +000015240 tp->rx_offset = NET_SKB_PAD;
Matt Carlsond2757fc2010-04-12 06:58:27 +000015241#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Matt Carlson9dc7a112010-04-12 06:58:28 +000015242 tp->rx_copy_thresh = ~(u16)0;
Matt Carlsond2757fc2010-04-12 06:58:27 +000015243#endif
15244 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015245
Matt Carlson2c49a442010-09-30 10:34:35 +000015246 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
15247 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000015248 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
15249
Matt Carlson2c49a442010-09-30 10:34:35 +000015250 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
Michael Chanf92905d2006-06-29 20:14:29 -070015251
15252 /* Increment the rx prod index on the rx std ring by at most
15253 * 8 for these chips to workaround hw errata.
15254 */
15255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
15256 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
15257 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
15258 tp->rx_std_max_post = 8;
15259
Joe Perches63c3a662011-04-26 08:12:10 +000015260 if (tg3_flag(tp, ASPM_WORKAROUND))
Matt Carlson8ed5d972007-05-07 00:25:49 -070015261 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
15262 PCIE_PWR_MGMT_L1_THRESH_MSK;
15263
Linus Torvalds1da177e2005-04-16 15:20:36 -070015264 return err;
15265}
15266
David S. Miller49b6e95f2007-03-29 01:38:42 -070015267#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070015268static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
15269{
15270 struct net_device *dev = tp->dev;
15271 struct pci_dev *pdev = tp->pdev;
David S. Miller49b6e95f2007-03-29 01:38:42 -070015272 struct device_node *dp = pci_device_to_OF_node(pdev);
David S. Miller374d4ca2007-03-29 01:57:57 -070015273 const unsigned char *addr;
David S. Miller49b6e95f2007-03-29 01:38:42 -070015274 int len;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015275
David S. Miller49b6e95f2007-03-29 01:38:42 -070015276 addr = of_get_property(dp, "local-mac-address", &len);
15277 if (addr && len == 6) {
15278 memcpy(dev->dev_addr, addr, 6);
15279 memcpy(dev->perm_addr, dev->dev_addr, 6);
15280 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015281 }
15282 return -ENODEV;
15283}
15284
15285static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
15286{
15287 struct net_device *dev = tp->dev;
15288
15289 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
John W. Linville2ff43692005-09-12 14:44:20 -070015290 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015291 return 0;
15292}
15293#endif
15294
15295static int __devinit tg3_get_device_address(struct tg3 *tp)
15296{
15297 struct net_device *dev = tp->dev;
15298 u32 hi, lo, mac_offset;
Michael Chan008652b2006-03-27 23:14:53 -080015299 int addr_ok = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015300
David S. Miller49b6e95f2007-03-29 01:38:42 -070015301#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070015302 if (!tg3_get_macaddr_sparc(tp))
15303 return 0;
15304#endif
15305
15306 mac_offset = 0x7c;
Matt Carlson6ff6f812011-05-19 12:12:54 +000015307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
Joe Perches63c3a662011-04-26 08:12:10 +000015308 tg3_flag(tp, 5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070015309 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
15310 mac_offset = 0xcc;
15311 if (tg3_nvram_lock(tp))
15312 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
15313 else
15314 tg3_nvram_unlock(tp);
Joe Perches63c3a662011-04-26 08:12:10 +000015315 } else if (tg3_flag(tp, 5717_PLUS)) {
Matt Carlson69f11c92011-07-13 09:27:30 +000015316 if (tp->pci_fn & 1)
Matt Carlsona1b950d2009-09-01 13:20:17 +000015317 mac_offset = 0xcc;
Matt Carlson69f11c92011-07-13 09:27:30 +000015318 if (tp->pci_fn > 1)
Matt Carlsona50d0792010-06-05 17:24:37 +000015319 mac_offset += 0x18c;
Matt Carlsona1b950d2009-09-01 13:20:17 +000015320 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Michael Chanb5d37722006-09-27 16:06:21 -070015321 mac_offset = 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015322
15323 /* First try to get it from MAC address mailbox. */
15324 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
15325 if ((hi >> 16) == 0x484b) {
15326 dev->dev_addr[0] = (hi >> 8) & 0xff;
15327 dev->dev_addr[1] = (hi >> 0) & 0xff;
15328
15329 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
15330 dev->dev_addr[2] = (lo >> 24) & 0xff;
15331 dev->dev_addr[3] = (lo >> 16) & 0xff;
15332 dev->dev_addr[4] = (lo >> 8) & 0xff;
15333 dev->dev_addr[5] = (lo >> 0) & 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015334
Michael Chan008652b2006-03-27 23:14:53 -080015335 /* Some old bootcode may report a 0 MAC address in SRAM */
15336 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
15337 }
15338 if (!addr_ok) {
15339 /* Next, try NVRAM. */
Joe Perches63c3a662011-04-26 08:12:10 +000015340 if (!tg3_flag(tp, NO_NVRAM) &&
Matt Carlsondf259d82009-04-20 06:57:14 +000015341 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
Matt Carlson6d348f22009-02-25 14:25:52 +000015342 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
Matt Carlson62cedd12009-04-20 14:52:29 -070015343 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
15344 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
Michael Chan008652b2006-03-27 23:14:53 -080015345 }
15346 /* Finally just fetch it out of the MAC control regs. */
15347 else {
15348 hi = tr32(MAC_ADDR_0_HIGH);
15349 lo = tr32(MAC_ADDR_0_LOW);
15350
15351 dev->dev_addr[5] = lo & 0xff;
15352 dev->dev_addr[4] = (lo >> 8) & 0xff;
15353 dev->dev_addr[3] = (lo >> 16) & 0xff;
15354 dev->dev_addr[2] = (lo >> 24) & 0xff;
15355 dev->dev_addr[1] = hi & 0xff;
15356 dev->dev_addr[0] = (hi >> 8) & 0xff;
15357 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015358 }
15359
15360 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
David S. Miller7582a332008-03-20 15:53:15 -070015361#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070015362 if (!tg3_get_default_macaddr_sparc(tp))
15363 return 0;
15364#endif
15365 return -EINVAL;
15366 }
John W. Linville2ff43692005-09-12 14:44:20 -070015367 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015368 return 0;
15369}
15370
David S. Miller59e6b432005-05-18 22:50:10 -070015371#define BOUNDARY_SINGLE_CACHELINE 1
15372#define BOUNDARY_MULTI_CACHELINE 2
15373
15374static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
15375{
15376 int cacheline_size;
15377 u8 byte;
15378 int goal;
15379
15380 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
15381 if (byte == 0)
15382 cacheline_size = 1024;
15383 else
15384 cacheline_size = (int) byte * 4;
15385
15386 /* On 5703 and later chips, the boundary bits have no
15387 * effect.
15388 */
15389 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15390 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
Joe Perches63c3a662011-04-26 08:12:10 +000015391 !tg3_flag(tp, PCI_EXPRESS))
David S. Miller59e6b432005-05-18 22:50:10 -070015392 goto out;
15393
15394#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
15395 goal = BOUNDARY_MULTI_CACHELINE;
15396#else
15397#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
15398 goal = BOUNDARY_SINGLE_CACHELINE;
15399#else
15400 goal = 0;
15401#endif
15402#endif
15403
Joe Perches63c3a662011-04-26 08:12:10 +000015404 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000015405 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
15406 goto out;
15407 }
15408
David S. Miller59e6b432005-05-18 22:50:10 -070015409 if (!goal)
15410 goto out;
15411
15412 /* PCI controllers on most RISC systems tend to disconnect
15413 * when a device tries to burst across a cache-line boundary.
15414 * Therefore, letting tg3 do so just wastes PCI bandwidth.
15415 *
15416 * Unfortunately, for PCI-E there are only limited
15417 * write-side controls for this, and thus for reads
15418 * we will still get the disconnects. We'll also waste
15419 * these PCI cycles for both read and write for chips
15420 * other than 5700 and 5701 which do not implement the
15421 * boundary bits.
15422 */
Joe Perches63c3a662011-04-26 08:12:10 +000015423 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
David S. Miller59e6b432005-05-18 22:50:10 -070015424 switch (cacheline_size) {
15425 case 16:
15426 case 32:
15427 case 64:
15428 case 128:
15429 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15430 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
15431 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
15432 } else {
15433 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
15434 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
15435 }
15436 break;
15437
15438 case 256:
15439 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
15440 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
15441 break;
15442
15443 default:
15444 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
15445 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
15446 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070015447 }
Joe Perches63c3a662011-04-26 08:12:10 +000015448 } else if (tg3_flag(tp, PCI_EXPRESS)) {
David S. Miller59e6b432005-05-18 22:50:10 -070015449 switch (cacheline_size) {
15450 case 16:
15451 case 32:
15452 case 64:
15453 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15454 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
15455 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
15456 break;
15457 }
15458 /* fallthrough */
15459 case 128:
15460 default:
15461 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
15462 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
15463 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070015464 }
David S. Miller59e6b432005-05-18 22:50:10 -070015465 } else {
15466 switch (cacheline_size) {
15467 case 16:
15468 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15469 val |= (DMA_RWCTRL_READ_BNDRY_16 |
15470 DMA_RWCTRL_WRITE_BNDRY_16);
15471 break;
15472 }
15473 /* fallthrough */
15474 case 32:
15475 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15476 val |= (DMA_RWCTRL_READ_BNDRY_32 |
15477 DMA_RWCTRL_WRITE_BNDRY_32);
15478 break;
15479 }
15480 /* fallthrough */
15481 case 64:
15482 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15483 val |= (DMA_RWCTRL_READ_BNDRY_64 |
15484 DMA_RWCTRL_WRITE_BNDRY_64);
15485 break;
15486 }
15487 /* fallthrough */
15488 case 128:
15489 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15490 val |= (DMA_RWCTRL_READ_BNDRY_128 |
15491 DMA_RWCTRL_WRITE_BNDRY_128);
15492 break;
15493 }
15494 /* fallthrough */
15495 case 256:
15496 val |= (DMA_RWCTRL_READ_BNDRY_256 |
15497 DMA_RWCTRL_WRITE_BNDRY_256);
15498 break;
15499 case 512:
15500 val |= (DMA_RWCTRL_READ_BNDRY_512 |
15501 DMA_RWCTRL_WRITE_BNDRY_512);
15502 break;
15503 case 1024:
15504 default:
15505 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
15506 DMA_RWCTRL_WRITE_BNDRY_1024);
15507 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070015508 }
David S. Miller59e6b432005-05-18 22:50:10 -070015509 }
15510
15511out:
15512 return val;
15513}
15514
Linus Torvalds1da177e2005-04-16 15:20:36 -070015515static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
15516{
15517 struct tg3_internal_buffer_desc test_desc;
15518 u32 sram_dma_descs;
15519 int i, ret;
15520
15521 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
15522
15523 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
15524 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
15525 tw32(RDMAC_STATUS, 0);
15526 tw32(WDMAC_STATUS, 0);
15527
15528 tw32(BUFMGR_MODE, 0);
15529 tw32(FTQ_RESET, 0);
15530
15531 test_desc.addr_hi = ((u64) buf_dma) >> 32;
15532 test_desc.addr_lo = buf_dma & 0xffffffff;
15533 test_desc.nic_mbuf = 0x00002100;
15534 test_desc.len = size;
15535
15536 /*
15537 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
15538 * the *second* time the tg3 driver was getting loaded after an
15539 * initial scan.
15540 *
15541 * Broadcom tells me:
15542 * ...the DMA engine is connected to the GRC block and a DMA
15543 * reset may affect the GRC block in some unpredictable way...
15544 * The behavior of resets to individual blocks has not been tested.
15545 *
15546 * Broadcom noted the GRC reset will also reset all sub-components.
15547 */
15548 if (to_device) {
15549 test_desc.cqid_sqid = (13 << 8) | 2;
15550
15551 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
15552 udelay(40);
15553 } else {
15554 test_desc.cqid_sqid = (16 << 8) | 7;
15555
15556 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
15557 udelay(40);
15558 }
15559 test_desc.flags = 0x00000005;
15560
15561 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
15562 u32 val;
15563
15564 val = *(((u32 *)&test_desc) + i);
15565 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
15566 sram_dma_descs + (i * sizeof(u32)));
15567 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
15568 }
15569 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
15570
Matt Carlson859a588792010-04-05 10:19:28 +000015571 if (to_device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015572 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
Matt Carlson859a588792010-04-05 10:19:28 +000015573 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070015574 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015575
15576 ret = -ENODEV;
15577 for (i = 0; i < 40; i++) {
15578 u32 val;
15579
15580 if (to_device)
15581 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
15582 else
15583 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
15584 if ((val & 0xffff) == sram_dma_descs) {
15585 ret = 0;
15586 break;
15587 }
15588
15589 udelay(100);
15590 }
15591
15592 return ret;
15593}
15594
David S. Millerded73402005-05-23 13:59:47 -070015595#define TEST_BUFFER_SIZE 0x2000
Linus Torvalds1da177e2005-04-16 15:20:36 -070015596
Matt Carlson41434702011-03-09 16:58:22 +000015597static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
Joe Perches895950c2010-12-21 02:16:08 -080015598 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
15599 { },
15600};
15601
Linus Torvalds1da177e2005-04-16 15:20:36 -070015602static int __devinit tg3_test_dma(struct tg3 *tp)
15603{
15604 dma_addr_t buf_dma;
David S. Miller59e6b432005-05-18 22:50:10 -070015605 u32 *buf, saved_dma_rwctrl;
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000015606 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015607
Matt Carlson4bae65c2010-11-24 08:31:52 +000015608 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
15609 &buf_dma, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015610 if (!buf) {
15611 ret = -ENOMEM;
15612 goto out_nofree;
15613 }
15614
15615 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
15616 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
15617
David S. Miller59e6b432005-05-18 22:50:10 -070015618 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015619
Joe Perches63c3a662011-04-26 08:12:10 +000015620 if (tg3_flag(tp, 57765_PLUS))
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000015621 goto out;
15622
Joe Perches63c3a662011-04-26 08:12:10 +000015623 if (tg3_flag(tp, PCI_EXPRESS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070015624 /* DMA read watermark not used on PCIE */
15625 tp->dma_rwctrl |= 0x00180000;
Joe Perches63c3a662011-04-26 08:12:10 +000015626 } else if (!tg3_flag(tp, PCIX_MODE)) {
Michael Chan85e94ce2005-04-21 17:05:28 -070015627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015629 tp->dma_rwctrl |= 0x003f0000;
15630 else
15631 tp->dma_rwctrl |= 0x003f000f;
15632 } else {
15633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15634 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15635 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
Michael Chan49afdeb2007-02-13 12:17:03 -080015636 u32 read_water = 0x7;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015637
Michael Chan4a29cc22006-03-19 13:21:12 -080015638 /* If the 5704 is behind the EPB bridge, we can
15639 * do the less restrictive ONE_DMA workaround for
15640 * better performance.
15641 */
Joe Perches63c3a662011-04-26 08:12:10 +000015642 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
Michael Chan4a29cc22006-03-19 13:21:12 -080015643 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15644 tp->dma_rwctrl |= 0x8000;
15645 else if (ccval == 0x6 || ccval == 0x7)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015646 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15647
Michael Chan49afdeb2007-02-13 12:17:03 -080015648 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15649 read_water = 4;
David S. Miller59e6b432005-05-18 22:50:10 -070015650 /* Set bit 23 to enable PCIX hw bug fix */
Michael Chan49afdeb2007-02-13 12:17:03 -080015651 tp->dma_rwctrl |=
15652 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15653 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15654 (1 << 23);
Michael Chan4cf78e42005-07-25 12:29:19 -070015655 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15656 /* 5780 always in PCIX mode */
15657 tp->dma_rwctrl |= 0x00144000;
Michael Chana4e2b342005-10-26 15:46:52 -070015658 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15659 /* 5714 always in PCIX mode */
15660 tp->dma_rwctrl |= 0x00148000;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015661 } else {
15662 tp->dma_rwctrl |= 0x001b000f;
15663 }
15664 }
15665
15666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15667 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15668 tp->dma_rwctrl &= 0xfffffff0;
15669
15670 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15672 /* Remove this if it causes problems for some boards. */
15673 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15674
15675 /* On 5700/5701 chips, we need to set this bit.
15676 * Otherwise the chip will issue cacheline transactions
15677 * to streamable DMA memory with not all the byte
15678 * enables turned on. This is an error on several
15679 * RISC PCI controllers, in particular sparc64.
15680 *
15681 * On 5703/5704 chips, this bit has been reassigned
15682 * a different meaning. In particular, it is used
15683 * on those chips to enable a PCI-X workaround.
15684 */
15685 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15686 }
15687
15688 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15689
15690#if 0
15691 /* Unneeded, already done by tg3_get_invariants. */
15692 tg3_switch_clocks(tp);
15693#endif
15694
Linus Torvalds1da177e2005-04-16 15:20:36 -070015695 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15696 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15697 goto out;
15698
David S. Miller59e6b432005-05-18 22:50:10 -070015699 /* It is best to perform DMA test with maximum write burst size
15700 * to expose the 5700/5701 write DMA bug.
15701 */
15702 saved_dma_rwctrl = tp->dma_rwctrl;
15703 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15704 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15705
Linus Torvalds1da177e2005-04-16 15:20:36 -070015706 while (1) {
15707 u32 *p = buf, i;
15708
15709 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15710 p[i] = i;
15711
15712 /* Send the buffer to the chip. */
15713 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15714 if (ret) {
Matt Carlson2445e462010-04-05 10:19:21 +000015715 dev_err(&tp->pdev->dev,
15716 "%s: Buffer write failed. err = %d\n",
15717 __func__, ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015718 break;
15719 }
15720
15721#if 0
15722 /* validate data reached card RAM correctly. */
15723 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15724 u32 val;
15725 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15726 if (le32_to_cpu(val) != p[i]) {
Matt Carlson2445e462010-04-05 10:19:21 +000015727 dev_err(&tp->pdev->dev,
15728 "%s: Buffer corrupted on device! "
15729 "(%d != %d)\n", __func__, val, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015730 /* ret = -ENODEV here? */
15731 }
15732 p[i] = 0;
15733 }
15734#endif
15735 /* Now read it back. */
15736 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15737 if (ret) {
Matt Carlson5129c3a2010-04-05 10:19:23 +000015738 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15739 "err = %d\n", __func__, ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015740 break;
15741 }
15742
15743 /* Verify it. */
15744 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15745 if (p[i] == i)
15746 continue;
15747
David S. Miller59e6b432005-05-18 22:50:10 -070015748 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15749 DMA_RWCTRL_WRITE_BNDRY_16) {
15750 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015751 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15752 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15753 break;
15754 } else {
Matt Carlson2445e462010-04-05 10:19:21 +000015755 dev_err(&tp->pdev->dev,
15756 "%s: Buffer corrupted on read back! "
15757 "(%d != %d)\n", __func__, p[i], i);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015758 ret = -ENODEV;
15759 goto out;
15760 }
15761 }
15762
15763 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15764 /* Success. */
15765 ret = 0;
15766 break;
15767 }
15768 }
David S. Miller59e6b432005-05-18 22:50:10 -070015769 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15770 DMA_RWCTRL_WRITE_BNDRY_16) {
15771 /* DMA test passed without adjusting DMA boundary,
Michael Chan6d1cfba2005-06-08 14:13:14 -070015772 * now look for chipsets that are known to expose the
15773 * DMA bug without failing the test.
David S. Miller59e6b432005-05-18 22:50:10 -070015774 */
Matt Carlson41434702011-03-09 16:58:22 +000015775 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
Michael Chan6d1cfba2005-06-08 14:13:14 -070015776 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15777 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
Matt Carlson859a588792010-04-05 10:19:28 +000015778 } else {
Michael Chan6d1cfba2005-06-08 14:13:14 -070015779 /* Safe to use the calculated DMA boundary. */
15780 tp->dma_rwctrl = saved_dma_rwctrl;
Matt Carlson859a588792010-04-05 10:19:28 +000015781 }
Michael Chan6d1cfba2005-06-08 14:13:14 -070015782
David S. Miller59e6b432005-05-18 22:50:10 -070015783 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15784 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015785
15786out:
Matt Carlson4bae65c2010-11-24 08:31:52 +000015787 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015788out_nofree:
15789 return ret;
15790}
15791
Linus Torvalds1da177e2005-04-16 15:20:36 -070015792static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15793{
Joe Perches63c3a662011-04-26 08:12:10 +000015794 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlson666bc832010-01-20 16:58:03 +000015795 tp->bufmgr_config.mbuf_read_dma_low_water =
15796 DEFAULT_MB_RDMA_LOW_WATER_5705;
15797 tp->bufmgr_config.mbuf_mac_rx_low_water =
15798 DEFAULT_MB_MACRX_LOW_WATER_57765;
15799 tp->bufmgr_config.mbuf_high_water =
15800 DEFAULT_MB_HIGH_WATER_57765;
15801
15802 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15803 DEFAULT_MB_RDMA_LOW_WATER_5705;
15804 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15805 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15806 tp->bufmgr_config.mbuf_high_water_jumbo =
15807 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
Joe Perches63c3a662011-04-26 08:12:10 +000015808 } else if (tg3_flag(tp, 5705_PLUS)) {
Michael Chanfdfec1722005-07-25 12:31:48 -070015809 tp->bufmgr_config.mbuf_read_dma_low_water =
15810 DEFAULT_MB_RDMA_LOW_WATER_5705;
15811 tp->bufmgr_config.mbuf_mac_rx_low_water =
15812 DEFAULT_MB_MACRX_LOW_WATER_5705;
15813 tp->bufmgr_config.mbuf_high_water =
15814 DEFAULT_MB_HIGH_WATER_5705;
Michael Chanb5d37722006-09-27 16:06:21 -070015815 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15816 tp->bufmgr_config.mbuf_mac_rx_low_water =
15817 DEFAULT_MB_MACRX_LOW_WATER_5906;
15818 tp->bufmgr_config.mbuf_high_water =
15819 DEFAULT_MB_HIGH_WATER_5906;
15820 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015821
Michael Chanfdfec1722005-07-25 12:31:48 -070015822 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15823 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15824 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15825 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15826 tp->bufmgr_config.mbuf_high_water_jumbo =
15827 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15828 } else {
15829 tp->bufmgr_config.mbuf_read_dma_low_water =
15830 DEFAULT_MB_RDMA_LOW_WATER;
15831 tp->bufmgr_config.mbuf_mac_rx_low_water =
15832 DEFAULT_MB_MACRX_LOW_WATER;
15833 tp->bufmgr_config.mbuf_high_water =
15834 DEFAULT_MB_HIGH_WATER;
15835
15836 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15837 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15838 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15839 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15840 tp->bufmgr_config.mbuf_high_water_jumbo =
15841 DEFAULT_MB_HIGH_WATER_JUMBO;
15842 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015843
15844 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15845 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15846}
15847
15848static char * __devinit tg3_phy_string(struct tg3 *tp)
15849{
Matt Carlson79eb6902010-02-17 15:17:03 +000015850 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15851 case TG3_PHY_ID_BCM5400: return "5400";
15852 case TG3_PHY_ID_BCM5401: return "5401";
15853 case TG3_PHY_ID_BCM5411: return "5411";
15854 case TG3_PHY_ID_BCM5701: return "5701";
15855 case TG3_PHY_ID_BCM5703: return "5703";
15856 case TG3_PHY_ID_BCM5704: return "5704";
15857 case TG3_PHY_ID_BCM5705: return "5705";
15858 case TG3_PHY_ID_BCM5750: return "5750";
15859 case TG3_PHY_ID_BCM5752: return "5752";
15860 case TG3_PHY_ID_BCM5714: return "5714";
15861 case TG3_PHY_ID_BCM5780: return "5780";
15862 case TG3_PHY_ID_BCM5755: return "5755";
15863 case TG3_PHY_ID_BCM5787: return "5787";
15864 case TG3_PHY_ID_BCM5784: return "5784";
15865 case TG3_PHY_ID_BCM5756: return "5722/5756";
15866 case TG3_PHY_ID_BCM5906: return "5906";
15867 case TG3_PHY_ID_BCM5761: return "5761";
15868 case TG3_PHY_ID_BCM5718C: return "5718C";
15869 case TG3_PHY_ID_BCM5718S: return "5718S";
15870 case TG3_PHY_ID_BCM57765: return "57765";
Matt Carlson302b5002010-06-05 17:24:38 +000015871 case TG3_PHY_ID_BCM5719C: return "5719C";
Matt Carlson6418f2c2011-04-05 14:22:49 +000015872 case TG3_PHY_ID_BCM5720C: return "5720C";
Matt Carlson79eb6902010-02-17 15:17:03 +000015873 case TG3_PHY_ID_BCM8002: return "8002/serdes";
Linus Torvalds1da177e2005-04-16 15:20:36 -070015874 case 0: return "serdes";
15875 default: return "unknown";
Stephen Hemminger855e1112008-04-16 16:37:28 -070015876 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015877}
15878
Michael Chanf9804dd2005-09-27 12:13:10 -070015879static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15880{
Joe Perches63c3a662011-04-26 08:12:10 +000015881 if (tg3_flag(tp, PCI_EXPRESS)) {
Michael Chanf9804dd2005-09-27 12:13:10 -070015882 strcpy(str, "PCI Express");
15883 return str;
Joe Perches63c3a662011-04-26 08:12:10 +000015884 } else if (tg3_flag(tp, PCIX_MODE)) {
Michael Chanf9804dd2005-09-27 12:13:10 -070015885 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15886
15887 strcpy(str, "PCIX:");
15888
15889 if ((clock_ctrl == 7) ||
15890 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15891 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15892 strcat(str, "133MHz");
15893 else if (clock_ctrl == 0)
15894 strcat(str, "33MHz");
15895 else if (clock_ctrl == 2)
15896 strcat(str, "50MHz");
15897 else if (clock_ctrl == 4)
15898 strcat(str, "66MHz");
15899 else if (clock_ctrl == 6)
15900 strcat(str, "100MHz");
Michael Chanf9804dd2005-09-27 12:13:10 -070015901 } else {
15902 strcpy(str, "PCI:");
Joe Perches63c3a662011-04-26 08:12:10 +000015903 if (tg3_flag(tp, PCI_HIGH_SPEED))
Michael Chanf9804dd2005-09-27 12:13:10 -070015904 strcat(str, "66MHz");
15905 else
15906 strcat(str, "33MHz");
15907 }
Joe Perches63c3a662011-04-26 08:12:10 +000015908 if (tg3_flag(tp, PCI_32BIT))
Michael Chanf9804dd2005-09-27 12:13:10 -070015909 strcat(str, ":32-bit");
15910 else
15911 strcat(str, ":64-bit");
15912 return str;
15913}
15914
David S. Miller15f98502005-05-18 22:49:26 -070015915static void __devinit tg3_init_coal(struct tg3 *tp)
15916{
15917 struct ethtool_coalesce *ec = &tp->coal;
15918
15919 memset(ec, 0, sizeof(*ec));
15920 ec->cmd = ETHTOOL_GCOALESCE;
15921 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15922 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15923 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15924 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15925 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15926 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15927 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15928 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15929 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15930
15931 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15932 HOSTCC_MODE_CLRTICK_TXBD)) {
15933 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15934 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15935 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15936 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15937 }
Michael Chand244c892005-07-05 14:42:33 -070015938
Joe Perches63c3a662011-04-26 08:12:10 +000015939 if (tg3_flag(tp, 5705_PLUS)) {
Michael Chand244c892005-07-05 14:42:33 -070015940 ec->rx_coalesce_usecs_irq = 0;
15941 ec->tx_coalesce_usecs_irq = 0;
15942 ec->stats_block_coalesce_usecs = 0;
15943 }
David S. Miller15f98502005-05-18 22:49:26 -070015944}
15945
Linus Torvalds1da177e2005-04-16 15:20:36 -070015946static int __devinit tg3_init_one(struct pci_dev *pdev,
15947 const struct pci_device_id *ent)
15948{
Linus Torvalds1da177e2005-04-16 15:20:36 -070015949 struct net_device *dev;
15950 struct tg3 *tp;
Matt Carlson646c9ed2009-09-01 12:58:41 +000015951 int i, err, pm_cap;
15952 u32 sndmbx, rcvmbx, intmbx;
Michael Chanf9804dd2005-09-27 12:13:10 -070015953 char str[40];
Michael Chan72f2afb2006-03-06 19:28:35 -080015954 u64 dma_mask, persist_dma_mask;
Michał Mirosławc8f44af2011-11-15 15:29:55 +000015955 netdev_features_t features = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015956
Joe Perches05dbe002010-02-17 19:44:19 +000015957 printk_once(KERN_INFO "%s\n", version);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015958
15959 err = pci_enable_device(pdev);
15960 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000015961 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015962 return err;
15963 }
15964
Linus Torvalds1da177e2005-04-16 15:20:36 -070015965 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15966 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000015967 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015968 goto err_out_disable_pdev;
15969 }
15970
15971 pci_set_master(pdev);
15972
15973 /* Find power-management capability. */
15974 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15975 if (pm_cap == 0) {
Matt Carlson2445e462010-04-05 10:19:21 +000015976 dev_err(&pdev->dev,
15977 "Cannot find Power Management capability, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015978 err = -EIO;
15979 goto err_out_free_res;
15980 }
15981
Matt Carlson16821282011-07-13 09:27:28 +000015982 err = pci_set_power_state(pdev, PCI_D0);
15983 if (err) {
15984 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15985 goto err_out_free_res;
15986 }
15987
Matt Carlsonfe5f5782009-09-01 13:09:39 +000015988 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015989 if (!dev) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070015990 err = -ENOMEM;
Matt Carlson16821282011-07-13 09:27:28 +000015991 goto err_out_power_down;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015992 }
15993
Linus Torvalds1da177e2005-04-16 15:20:36 -070015994 SET_NETDEV_DEV(dev, &pdev->dev);
15995
Linus Torvalds1da177e2005-04-16 15:20:36 -070015996 tp = netdev_priv(dev);
15997 tp->pdev = pdev;
15998 tp->dev = dev;
15999 tp->pm_cap = pm_cap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016000 tp->rx_mode = TG3_DEF_RX_MODE;
16001 tp->tx_mode = TG3_DEF_TX_MODE;
Matt Carlson8ef21422008-05-02 16:47:53 -070016002
Linus Torvalds1da177e2005-04-16 15:20:36 -070016003 if (tg3_debug > 0)
16004 tp->msg_enable = tg3_debug;
16005 else
16006 tp->msg_enable = TG3_DEF_MSG_ENABLE;
16007
16008 /* The word/byte swap controls here control register access byte
16009 * swapping. DMA data byte swapping is controlled in the GRC_MODE
16010 * setting below.
16011 */
16012 tp->misc_host_ctrl =
16013 MISC_HOST_CTRL_MASK_PCI_INT |
16014 MISC_HOST_CTRL_WORD_SWAP |
16015 MISC_HOST_CTRL_INDIR_ACCESS |
16016 MISC_HOST_CTRL_PCISTATE_RW;
16017
16018 /* The NONFRM (non-frame) byte/word swap controls take effect
16019 * on descriptor entries, anything which isn't packet data.
16020 *
16021 * The StrongARM chips on the board (one for tx, one for rx)
16022 * are running in big-endian mode.
16023 */
16024 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
16025 GRC_MODE_WSWAP_NONFRM_DATA);
16026#ifdef __BIG_ENDIAN
16027 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
16028#endif
16029 spin_lock_init(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016030 spin_lock_init(&tp->indirect_lock);
David Howellsc4028952006-11-22 14:57:56 +000016031 INIT_WORK(&tp->reset_task, tg3_reset_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016032
Matt Carlsond5fe4882008-11-21 17:20:32 -080016033 tp->regs = pci_ioremap_bar(pdev, BAR_0);
Andy Gospodarekab0049b2007-09-06 20:42:14 +010016034 if (!tp->regs) {
Matt Carlsonab96b242010-04-05 10:19:22 +000016035 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070016036 err = -ENOMEM;
16037 goto err_out_free_dev;
16038 }
16039
Matt Carlsonc9cab242011-07-13 09:27:27 +000016040 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16041 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
16042 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
16043 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
16044 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16045 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16046 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16047 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
16048 tg3_flag_set(tp, ENABLE_APE);
16049 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
16050 if (!tp->aperegs) {
16051 dev_err(&pdev->dev,
16052 "Cannot map APE registers, aborting\n");
16053 err = -ENOMEM;
16054 goto err_out_iounmap;
16055 }
16056 }
16057
Linus Torvalds1da177e2005-04-16 15:20:36 -070016058 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
16059 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016060
Linus Torvalds1da177e2005-04-16 15:20:36 -070016061 dev->ethtool_ops = &tg3_ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016062 dev->watchdog_timeo = TG3_TX_TIMEOUT;
Matt Carlson2ffcc982011-05-19 12:12:44 +000016063 dev->netdev_ops = &tg3_netdev_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016064 dev->irq = pdev->irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016065
16066 err = tg3_get_invariants(tp);
16067 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000016068 dev_err(&pdev->dev,
16069 "Problem fetching invariants of chip, aborting\n");
Matt Carlsonc9cab242011-07-13 09:27:27 +000016070 goto err_out_apeunmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016071 }
16072
Michael Chan4a29cc22006-03-19 13:21:12 -080016073 /* The EPB bridge inside 5714, 5715, and 5780 and any
16074 * device behind the EPB cannot support DMA addresses > 40-bit.
Michael Chan72f2afb2006-03-06 19:28:35 -080016075 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
16076 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
16077 * do DMA address check in tg3_start_xmit().
16078 */
Joe Perches63c3a662011-04-26 08:12:10 +000016079 if (tg3_flag(tp, IS_5788))
Yang Hongyang284901a2009-04-06 19:01:15 -070016080 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
Joe Perches63c3a662011-04-26 08:12:10 +000016081 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
Yang Hongyang50cf1562009-04-06 19:01:14 -070016082 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
Michael Chan72f2afb2006-03-06 19:28:35 -080016083#ifdef CONFIG_HIGHMEM
Yang Hongyang6a355282009-04-06 19:01:13 -070016084 dma_mask = DMA_BIT_MASK(64);
Michael Chan72f2afb2006-03-06 19:28:35 -080016085#endif
Michael Chan4a29cc22006-03-19 13:21:12 -080016086 } else
Yang Hongyang6a355282009-04-06 19:01:13 -070016087 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
Michael Chan72f2afb2006-03-06 19:28:35 -080016088
16089 /* Configure DMA attributes. */
Yang Hongyang284901a2009-04-06 19:01:15 -070016090 if (dma_mask > DMA_BIT_MASK(32)) {
Michael Chan72f2afb2006-03-06 19:28:35 -080016091 err = pci_set_dma_mask(pdev, dma_mask);
16092 if (!err) {
Matt Carlson0da06062011-05-19 12:12:53 +000016093 features |= NETIF_F_HIGHDMA;
Michael Chan72f2afb2006-03-06 19:28:35 -080016094 err = pci_set_consistent_dma_mask(pdev,
16095 persist_dma_mask);
16096 if (err < 0) {
Matt Carlsonab96b242010-04-05 10:19:22 +000016097 dev_err(&pdev->dev, "Unable to obtain 64 bit "
16098 "DMA for consistent allocations\n");
Matt Carlsonc9cab242011-07-13 09:27:27 +000016099 goto err_out_apeunmap;
Michael Chan72f2afb2006-03-06 19:28:35 -080016100 }
16101 }
16102 }
Yang Hongyang284901a2009-04-06 19:01:15 -070016103 if (err || dma_mask == DMA_BIT_MASK(32)) {
16104 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Michael Chan72f2afb2006-03-06 19:28:35 -080016105 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000016106 dev_err(&pdev->dev,
16107 "No usable DMA configuration, aborting\n");
Matt Carlsonc9cab242011-07-13 09:27:27 +000016108 goto err_out_apeunmap;
Michael Chan72f2afb2006-03-06 19:28:35 -080016109 }
16110 }
16111
Michael Chanfdfec1722005-07-25 12:31:48 -070016112 tg3_init_bufmgr_config(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016113
Matt Carlson0da06062011-05-19 12:12:53 +000016114 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
16115
16116 /* 5700 B0 chips do not support checksumming correctly due
16117 * to hardware bugs.
16118 */
16119 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
16120 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
16121
16122 if (tg3_flag(tp, 5755_PLUS))
16123 features |= NETIF_F_IPV6_CSUM;
16124 }
16125
Michael Chan4e3a7aa2006-03-20 17:47:44 -080016126 /* TSO is on by default on chips that support hardware TSO.
16127 * Firmware TSO on older chips gives lower performance, so it
16128 * is off by default, but can be enabled using ethtool.
16129 */
Joe Perches63c3a662011-04-26 08:12:10 +000016130 if ((tg3_flag(tp, HW_TSO_1) ||
16131 tg3_flag(tp, HW_TSO_2) ||
16132 tg3_flag(tp, HW_TSO_3)) &&
Matt Carlson0da06062011-05-19 12:12:53 +000016133 (features & NETIF_F_IP_CSUM))
16134 features |= NETIF_F_TSO;
Joe Perches63c3a662011-04-26 08:12:10 +000016135 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
Matt Carlson0da06062011-05-19 12:12:53 +000016136 if (features & NETIF_F_IPV6_CSUM)
16137 features |= NETIF_F_TSO6;
Joe Perches63c3a662011-04-26 08:12:10 +000016138 if (tg3_flag(tp, HW_TSO_3) ||
Matt Carlsone849cdc2009-11-13 13:03:38 +000016139 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson57e69832008-05-25 23:48:31 -070016140 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
16141 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
Joe Perches63c3a662011-04-26 08:12:10 +000016142 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Michał Mirosławdc668912011-04-07 03:35:07 +000016143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlson0da06062011-05-19 12:12:53 +000016144 features |= NETIF_F_TSO_ECN;
Michael Chanb0026622006-07-03 19:42:14 -070016145 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070016146
Matt Carlsond542fe22011-05-19 16:02:43 +000016147 dev->features |= features;
16148 dev->vlan_features |= features;
16149
Mahesh Bandewar06c03c02011-05-08 06:51:48 +000016150 /*
16151 * Add loopback capability only for a subset of devices that support
16152 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
16153 * loopback for the remaining devices.
16154 */
16155 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
16156 !tg3_flag(tp, CPMU_PRESENT))
16157 /* Add the loopback capability */
Matt Carlson0da06062011-05-19 12:12:53 +000016158 features |= NETIF_F_LOOPBACK;
16159
Matt Carlson0da06062011-05-19 12:12:53 +000016160 dev->hw_features |= features;
Mahesh Bandewar06c03c02011-05-08 06:51:48 +000016161
Linus Torvalds1da177e2005-04-16 15:20:36 -070016162 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
Joe Perches63c3a662011-04-26 08:12:10 +000016163 !tg3_flag(tp, TSO_CAPABLE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070016164 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
Joe Perches63c3a662011-04-26 08:12:10 +000016165 tg3_flag_set(tp, MAX_RXPEND_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016166 tp->rx_pending = 63;
16167 }
16168
Linus Torvalds1da177e2005-04-16 15:20:36 -070016169 err = tg3_get_device_address(tp);
16170 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000016171 dev_err(&pdev->dev,
16172 "Could not obtain valid ethernet address, aborting\n");
Matt Carlsonc9cab242011-07-13 09:27:27 +000016173 goto err_out_apeunmap;
Matt Carlson0d3031d2007-10-10 18:02:43 -070016174 }
16175
Matt Carlsonc88864d2007-11-12 21:07:01 -080016176 /*
16177 * Reset chip in case UNDI or EFI driver did not shutdown
16178 * DMA self test will enable WDMAC and we'll see (spurious)
16179 * pending DMA on the PCI bus at that point.
16180 */
16181 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
16182 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
16183 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
16184 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
16185 }
16186
16187 err = tg3_test_dma(tp);
16188 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000016189 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
Matt Carlsonc88864d2007-11-12 21:07:01 -080016190 goto err_out_apeunmap;
16191 }
16192
Matt Carlson78f90dc2009-11-13 13:03:42 +000016193 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
16194 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
16195 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
Matt Carlson6fd45cb2010-09-15 08:59:57 +000016196 for (i = 0; i < tp->irq_max; i++) {
Matt Carlson78f90dc2009-11-13 13:03:42 +000016197 struct tg3_napi *tnapi = &tp->napi[i];
16198
16199 tnapi->tp = tp;
16200 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
16201
16202 tnapi->int_mbox = intmbx;
Matt Carlson93a700a2011-08-31 11:44:54 +000016203 if (i <= 4)
Matt Carlson78f90dc2009-11-13 13:03:42 +000016204 intmbx += 0x8;
16205 else
16206 intmbx += 0x4;
16207
16208 tnapi->consmbox = rcvmbx;
16209 tnapi->prodmbox = sndmbx;
16210
Matt Carlson66cfd1b2010-09-30 10:34:30 +000016211 if (i)
Matt Carlson78f90dc2009-11-13 13:03:42 +000016212 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
Matt Carlson66cfd1b2010-09-30 10:34:30 +000016213 else
Matt Carlson78f90dc2009-11-13 13:03:42 +000016214 tnapi->coal_now = HOSTCC_MODE_NOW;
Matt Carlson78f90dc2009-11-13 13:03:42 +000016215
Joe Perches63c3a662011-04-26 08:12:10 +000016216 if (!tg3_flag(tp, SUPPORT_MSIX))
Matt Carlson78f90dc2009-11-13 13:03:42 +000016217 break;
16218
16219 /*
16220 * If we support MSIX, we'll be using RSS. If we're using
16221 * RSS, the first vector only handles link interrupts and the
16222 * remaining vectors handle rx and tx interrupts. Reuse the
16223 * mailbox values for the next iteration. The values we setup
16224 * above are still useful for the single vectored mode.
16225 */
16226 if (!i)
16227 continue;
16228
16229 rcvmbx += 0x8;
16230
16231 if (sndmbx & 0x4)
16232 sndmbx -= 0x4;
16233 else
16234 sndmbx += 0xc;
16235 }
16236
Matt Carlsonc88864d2007-11-12 21:07:01 -080016237 tg3_init_coal(tp);
16238
Michael Chanc49a1562006-12-17 17:07:29 -080016239 pci_set_drvdata(pdev, dev);
16240
Matt Carlsoncd0d7222011-07-13 09:27:33 +000016241 if (tg3_flag(tp, 5717_PLUS)) {
16242 /* Resume a low-power mode */
16243 tg3_frob_aux_power(tp, false);
16244 }
16245
Matt Carlson21f76382012-02-22 12:35:21 +000016246 tg3_timer_init(tp);
16247
Linus Torvalds1da177e2005-04-16 15:20:36 -070016248 err = register_netdev(dev);
16249 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000016250 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
Matt Carlson0d3031d2007-10-10 18:02:43 -070016251 goto err_out_apeunmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016252 }
16253
Joe Perches05dbe002010-02-17 19:44:19 +000016254 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
16255 tp->board_part_number,
16256 tp->pci_chip_rev_id,
16257 tg3_bus_string(tp, str),
16258 dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016259
Matt Carlsonf07e9af2010-08-02 11:26:07 +000016260 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000016261 struct phy_device *phydev;
16262 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlson5129c3a2010-04-05 10:19:23 +000016263 netdev_info(dev,
16264 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
Joe Perches05dbe002010-02-17 19:44:19 +000016265 phydev->drv->name, dev_name(&phydev->dev));
Matt Carlsonf07e9af2010-08-02 11:26:07 +000016266 } else {
16267 char *ethtype;
16268
16269 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
16270 ethtype = "10/100Base-TX";
16271 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
16272 ethtype = "1000Base-SX";
16273 else
16274 ethtype = "10/100/1000Base-T";
16275
Matt Carlson5129c3a2010-04-05 10:19:23 +000016276 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
Matt Carlson47007832011-04-20 07:57:43 +000016277 "(WireSpeed[%d], EEE[%d])\n",
16278 tg3_phy_string(tp), ethtype,
16279 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
16280 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
Matt Carlsonf07e9af2010-08-02 11:26:07 +000016281 }
Matt Carlsondf59c942008-11-03 16:52:56 -080016282
Joe Perches05dbe002010-02-17 19:44:19 +000016283 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
Michał Mirosławdc668912011-04-07 03:35:07 +000016284 (dev->features & NETIF_F_RXCSUM) != 0,
Joe Perches63c3a662011-04-26 08:12:10 +000016285 tg3_flag(tp, USE_LINKCHG_REG) != 0,
Matt Carlsonf07e9af2010-08-02 11:26:07 +000016286 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
Joe Perches63c3a662011-04-26 08:12:10 +000016287 tg3_flag(tp, ENABLE_ASF) != 0,
16288 tg3_flag(tp, TSO_CAPABLE) != 0);
Joe Perches05dbe002010-02-17 19:44:19 +000016289 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
16290 tp->dma_rwctrl,
16291 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
16292 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016293
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016294 pci_save_state(pdev);
16295
Linus Torvalds1da177e2005-04-16 15:20:36 -070016296 return 0;
16297
Matt Carlson0d3031d2007-10-10 18:02:43 -070016298err_out_apeunmap:
16299 if (tp->aperegs) {
16300 iounmap(tp->aperegs);
16301 tp->aperegs = NULL;
16302 }
16303
Linus Torvalds1da177e2005-04-16 15:20:36 -070016304err_out_iounmap:
Michael Chan68929142005-08-09 20:17:14 -070016305 if (tp->regs) {
16306 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070016307 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070016308 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070016309
16310err_out_free_dev:
16311 free_netdev(dev);
16312
Matt Carlson16821282011-07-13 09:27:28 +000016313err_out_power_down:
16314 pci_set_power_state(pdev, PCI_D3hot);
16315
Linus Torvalds1da177e2005-04-16 15:20:36 -070016316err_out_free_res:
16317 pci_release_regions(pdev);
16318
16319err_out_disable_pdev:
16320 pci_disable_device(pdev);
16321 pci_set_drvdata(pdev, NULL);
16322 return err;
16323}
16324
16325static void __devexit tg3_remove_one(struct pci_dev *pdev)
16326{
16327 struct net_device *dev = pci_get_drvdata(pdev);
16328
16329 if (dev) {
16330 struct tg3 *tp = netdev_priv(dev);
16331
Jesper Juhle3c55302012-04-09 22:50:15 +020016332 release_firmware(tp->fw);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080016333
Matt Carlsondb219972011-11-04 09:15:03 +000016334 tg3_reset_task_cancel(tp);
Matt Carlson158d7ab2008-05-29 01:37:54 -070016335
David S. Miller1805b2f2011-10-24 18:18:09 -040016336 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070016337 tg3_phy_fini(tp);
Matt Carlson158d7ab2008-05-29 01:37:54 -070016338 tg3_mdio_fini(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070016339 }
Matt Carlson158d7ab2008-05-29 01:37:54 -070016340
Linus Torvalds1da177e2005-04-16 15:20:36 -070016341 unregister_netdev(dev);
Matt Carlson0d3031d2007-10-10 18:02:43 -070016342 if (tp->aperegs) {
16343 iounmap(tp->aperegs);
16344 tp->aperegs = NULL;
16345 }
Michael Chan68929142005-08-09 20:17:14 -070016346 if (tp->regs) {
16347 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070016348 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070016349 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070016350 free_netdev(dev);
16351 pci_release_regions(pdev);
16352 pci_disable_device(pdev);
16353 pci_set_drvdata(pdev, NULL);
16354 }
16355}
16356
Eric Dumazetaa6027c2011-01-01 05:22:46 +000016357#ifdef CONFIG_PM_SLEEP
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000016358static int tg3_suspend(struct device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070016359{
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000016360 struct pci_dev *pdev = to_pci_dev(device);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016361 struct net_device *dev = pci_get_drvdata(pdev);
16362 struct tg3 *tp = netdev_priv(dev);
16363 int err;
16364
16365 if (!netif_running(dev))
16366 return 0;
16367
Matt Carlsondb219972011-11-04 09:15:03 +000016368 tg3_reset_task_cancel(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070016369 tg3_phy_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016370 tg3_netif_stop(tp);
16371
Matt Carlson21f76382012-02-22 12:35:21 +000016372 tg3_timer_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016373
David S. Millerf47c11e2005-06-24 20:18:35 -070016374 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016375 tg3_disable_ints(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -070016376 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016377
16378 netif_device_detach(dev);
16379
David S. Millerf47c11e2005-06-24 20:18:35 -070016380 tg3_full_lock(tp, 0);
Michael Chan944d9802005-05-29 14:57:48 -070016381 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Joe Perches63c3a662011-04-26 08:12:10 +000016382 tg3_flag_clear(tp, INIT_COMPLETE);
David S. Millerf47c11e2005-06-24 20:18:35 -070016383 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016384
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000016385 err = tg3_power_down_prepare(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016386 if (err) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070016387 int err2;
16388
David S. Millerf47c11e2005-06-24 20:18:35 -070016389 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016390
Joe Perches63c3a662011-04-26 08:12:10 +000016391 tg3_flag_set(tp, INIT_COMPLETE);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070016392 err2 = tg3_restart_hw(tp, 1);
16393 if (err2)
Michael Chanb9ec6c12006-07-25 16:37:27 -070016394 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016395
Matt Carlson21f76382012-02-22 12:35:21 +000016396 tg3_timer_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016397
16398 netif_device_attach(dev);
16399 tg3_netif_start(tp);
16400
Michael Chanb9ec6c12006-07-25 16:37:27 -070016401out:
David S. Millerf47c11e2005-06-24 20:18:35 -070016402 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070016403
16404 if (!err2)
16405 tg3_phy_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016406 }
16407
16408 return err;
16409}
16410
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000016411static int tg3_resume(struct device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070016412{
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000016413 struct pci_dev *pdev = to_pci_dev(device);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016414 struct net_device *dev = pci_get_drvdata(pdev);
16415 struct tg3 *tp = netdev_priv(dev);
16416 int err;
16417
16418 if (!netif_running(dev))
16419 return 0;
16420
Linus Torvalds1da177e2005-04-16 15:20:36 -070016421 netif_device_attach(dev);
16422
David S. Millerf47c11e2005-06-24 20:18:35 -070016423 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016424
Joe Perches63c3a662011-04-26 08:12:10 +000016425 tg3_flag_set(tp, INIT_COMPLETE);
Michael Chanb9ec6c12006-07-25 16:37:27 -070016426 err = tg3_restart_hw(tp, 1);
16427 if (err)
16428 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016429
Matt Carlson21f76382012-02-22 12:35:21 +000016430 tg3_timer_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016431
Linus Torvalds1da177e2005-04-16 15:20:36 -070016432 tg3_netif_start(tp);
16433
Michael Chanb9ec6c12006-07-25 16:37:27 -070016434out:
David S. Millerf47c11e2005-06-24 20:18:35 -070016435 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016436
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070016437 if (!err)
16438 tg3_phy_start(tp);
16439
Michael Chanb9ec6c12006-07-25 16:37:27 -070016440 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070016441}
16442
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000016443static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
Eric Dumazetaa6027c2011-01-01 05:22:46 +000016444#define TG3_PM_OPS (&tg3_pm_ops)
16445
16446#else
16447
16448#define TG3_PM_OPS NULL
16449
16450#endif /* CONFIG_PM_SLEEP */
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000016451
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016452/**
16453 * tg3_io_error_detected - called when PCI error is detected
16454 * @pdev: Pointer to PCI device
16455 * @state: The current pci connection state
16456 *
16457 * This function is called after a PCI bus error affecting
16458 * this device has been detected.
16459 */
16460static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
16461 pci_channel_state_t state)
16462{
16463 struct net_device *netdev = pci_get_drvdata(pdev);
16464 struct tg3 *tp = netdev_priv(netdev);
16465 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
16466
16467 netdev_info(netdev, "PCI I/O error detected\n");
16468
16469 rtnl_lock();
16470
16471 if (!netif_running(netdev))
16472 goto done;
16473
16474 tg3_phy_stop(tp);
16475
16476 tg3_netif_stop(tp);
16477
Matt Carlson21f76382012-02-22 12:35:21 +000016478 tg3_timer_stop(tp);
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016479
16480 /* Want to make sure that the reset task doesn't run */
Matt Carlsondb219972011-11-04 09:15:03 +000016481 tg3_reset_task_cancel(tp);
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016482
16483 netif_device_detach(netdev);
16484
16485 /* Clean up software state, even if MMIO is blocked */
16486 tg3_full_lock(tp, 0);
16487 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
16488 tg3_full_unlock(tp);
16489
16490done:
16491 if (state == pci_channel_io_perm_failure)
16492 err = PCI_ERS_RESULT_DISCONNECT;
16493 else
16494 pci_disable_device(pdev);
16495
16496 rtnl_unlock();
16497
16498 return err;
16499}
16500
16501/**
16502 * tg3_io_slot_reset - called after the pci bus has been reset.
16503 * @pdev: Pointer to PCI device
16504 *
16505 * Restart the card from scratch, as if from a cold-boot.
16506 * At this point, the card has exprienced a hard reset,
16507 * followed by fixups by BIOS, and has its config space
16508 * set up identically to what it was at cold boot.
16509 */
16510static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
16511{
16512 struct net_device *netdev = pci_get_drvdata(pdev);
16513 struct tg3 *tp = netdev_priv(netdev);
16514 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
16515 int err;
16516
16517 rtnl_lock();
16518
16519 if (pci_enable_device(pdev)) {
16520 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
16521 goto done;
16522 }
16523
16524 pci_set_master(pdev);
16525 pci_restore_state(pdev);
16526 pci_save_state(pdev);
16527
16528 if (!netif_running(netdev)) {
16529 rc = PCI_ERS_RESULT_RECOVERED;
16530 goto done;
16531 }
16532
16533 err = tg3_power_up(tp);
Matt Carlsonbed98292011-07-13 09:27:29 +000016534 if (err)
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016535 goto done;
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016536
16537 rc = PCI_ERS_RESULT_RECOVERED;
16538
16539done:
16540 rtnl_unlock();
16541
16542 return rc;
16543}
16544
16545/**
16546 * tg3_io_resume - called when traffic can start flowing again.
16547 * @pdev: Pointer to PCI device
16548 *
16549 * This callback is called when the error recovery driver tells
16550 * us that its OK to resume normal operation.
16551 */
16552static void tg3_io_resume(struct pci_dev *pdev)
16553{
16554 struct net_device *netdev = pci_get_drvdata(pdev);
16555 struct tg3 *tp = netdev_priv(netdev);
16556 int err;
16557
16558 rtnl_lock();
16559
16560 if (!netif_running(netdev))
16561 goto done;
16562
16563 tg3_full_lock(tp, 0);
Joe Perches63c3a662011-04-26 08:12:10 +000016564 tg3_flag_set(tp, INIT_COMPLETE);
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016565 err = tg3_restart_hw(tp, 1);
16566 tg3_full_unlock(tp);
16567 if (err) {
16568 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16569 goto done;
16570 }
16571
16572 netif_device_attach(netdev);
16573
Matt Carlson21f76382012-02-22 12:35:21 +000016574 tg3_timer_start(tp);
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016575
16576 tg3_netif_start(tp);
16577
16578 tg3_phy_start(tp);
16579
16580done:
16581 rtnl_unlock();
16582}
16583
16584static struct pci_error_handlers tg3_err_handler = {
16585 .error_detected = tg3_io_error_detected,
16586 .slot_reset = tg3_io_slot_reset,
16587 .resume = tg3_io_resume
16588};
16589
Linus Torvalds1da177e2005-04-16 15:20:36 -070016590static struct pci_driver tg3_driver = {
16591 .name = DRV_MODULE_NAME,
16592 .id_table = tg3_pci_tbl,
16593 .probe = tg3_init_one,
16594 .remove = __devexit_p(tg3_remove_one),
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000016595 .err_handler = &tg3_err_handler,
Eric Dumazetaa6027c2011-01-01 05:22:46 +000016596 .driver.pm = TG3_PM_OPS,
Linus Torvalds1da177e2005-04-16 15:20:36 -070016597};
16598
16599static int __init tg3_init(void)
16600{
Jeff Garzik29917622006-08-19 17:48:59 -040016601 return pci_register_driver(&tg3_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -070016602}
16603
16604static void __exit tg3_cleanup(void)
16605{
16606 pci_unregister_driver(&tg3_driver);
16607}
16608
16609module_init(tg3_init);
16610module_exit(tg3_cleanup);