blob: 8ef8d0bcb08b96899a18b6fb909430c379b14ba3 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010051#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020052#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020053#include <linux/dcbnl.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020054#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
Ido Schimmelbe945352016-06-09 09:51:39 +0200251static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
252 u8 swid)
253{
254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
256 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200260static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
261{
262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200263
Ido Schimmelbe945352016-06-09 09:51:39 +0200264 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
265 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200266}
267
268static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
269 bool enable)
270{
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
272 char svpe_pl[MLXSW_REG_SVPE_LEN];
273
274 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
276}
277
278int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
279 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
280 u16 vid)
281{
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
283 char svfa_pl[MLXSW_REG_SVFA_LEN];
284
285 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
286 fid, vid);
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
288}
289
290static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
291 u16 vid, bool learn_enable)
292{
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
294 char *spvmlr_pl;
295 int err;
296
297 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
298 if (!spvmlr_pl)
299 return -ENOMEM;
300 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
301 learn_enable);
302 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
303 kfree(spvmlr_pl);
304 return err;
305}
306
307static int
308mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
309{
310 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
311 char sspr_pl[MLXSW_REG_SSPR_LEN];
312
313 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
315}
316
Ido Schimmeld664b412016-06-09 09:51:40 +0200317static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
318 u8 local_port, u8 *p_module,
319 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200320{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200321 char pmlp_pl[MLXSW_REG_PMLP_LEN];
322 int err;
323
Ido Schimmel558c2d52016-02-26 17:32:29 +0100324 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200325 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
326 if (err)
327 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100328 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
329 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200330 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200331 return 0;
332}
333
Ido Schimmel18f1e702016-02-26 17:32:31 +0100334static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
335 u8 module, u8 width, u8 lane)
336{
337 char pmlp_pl[MLXSW_REG_PMLP_LEN];
338 int i;
339
340 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
341 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
342 for (i = 0; i < width; i++) {
343 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
344 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
345 }
346
347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
348}
349
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100350static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
351{
352 char pmlp_pl[MLXSW_REG_PMLP_LEN];
353
354 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
355 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
357}
358
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200359static int mlxsw_sp_port_open(struct net_device *dev)
360{
361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
362 int err;
363
364 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
365 if (err)
366 return err;
367 netif_start_queue(dev);
368 return 0;
369}
370
371static int mlxsw_sp_port_stop(struct net_device *dev)
372{
373 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
374
375 netif_stop_queue(dev);
376 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
377}
378
379static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
380 struct net_device *dev)
381{
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
385 const struct mlxsw_tx_info tx_info = {
386 .local_port = mlxsw_sp_port->local_port,
387 .is_emad = false,
388 };
389 u64 len;
390 int err;
391
Jiri Pirko307c2432016-04-08 19:11:22 +0200392 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200393 return NETDEV_TX_BUSY;
394
395 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
396 struct sk_buff *skb_orig = skb;
397
398 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
399 if (!skb) {
400 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
401 dev_kfree_skb_any(skb_orig);
402 return NETDEV_TX_OK;
403 }
404 }
405
406 if (eth_skb_pad(skb)) {
407 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
408 return NETDEV_TX_OK;
409 }
410
411 mlxsw_sp_txhdr_construct(skb, &tx_info);
412 len = skb->len;
413 /* Due to a race we might fail here because of a full queue. In that
414 * unlikely case we simply drop the packet.
415 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200416 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200417
418 if (!err) {
419 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
420 u64_stats_update_begin(&pcpu_stats->syncp);
421 pcpu_stats->tx_packets++;
422 pcpu_stats->tx_bytes += len;
423 u64_stats_update_end(&pcpu_stats->syncp);
424 } else {
425 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
426 dev_kfree_skb_any(skb);
427 }
428 return NETDEV_TX_OK;
429}
430
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100431static void mlxsw_sp_set_rx_mode(struct net_device *dev)
432{
433}
434
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200435static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
436{
437 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
438 struct sockaddr *addr = p;
439 int err;
440
441 if (!is_valid_ether_addr(addr->sa_data))
442 return -EADDRNOTAVAIL;
443
444 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
445 if (err)
446 return err;
447 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
448 return 0;
449}
450
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200451static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200452 bool pause_en, bool pfc_en, u16 delay)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200453{
454 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
455
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200456 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
457 MLXSW_SP_PAUSE_DELAY;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200458
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200459 if (pause_en || pfc_en)
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200460 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200461 pg_size + delay, pg_size);
462 else
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200463 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200464}
465
466int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200467 u8 *prio_tc, bool pause_en,
468 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200469{
470 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200471 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
472 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200473 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200474 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200475
476 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
477 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
478 if (err)
479 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200480
481 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
482 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200483 bool pfc = false;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200484
485 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
486 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200487 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200488 configure = true;
489 break;
490 }
491 }
492
493 if (!configure)
494 continue;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200495 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200496 }
497
Ido Schimmelff6551e2016-04-06 17:10:03 +0200498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
499}
500
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200501static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200502 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200503{
504 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
505 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200506 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200507 u8 *prio_tc;
508
509 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200510 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200511
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200512 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200513 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200514}
515
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200516static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
517{
518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200519 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200520 int err;
521
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200522 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200523 if (err)
524 return err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200525 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
526 if (err)
527 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200528 dev->mtu = mtu;
529 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200530
531err_port_mtu_set:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200532 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200533 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534}
535
536static struct rtnl_link_stats64 *
537mlxsw_sp_port_get_stats64(struct net_device *dev,
538 struct rtnl_link_stats64 *stats)
539{
540 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
541 struct mlxsw_sp_port_pcpu_stats *p;
542 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
543 u32 tx_dropped = 0;
544 unsigned int start;
545 int i;
546
547 for_each_possible_cpu(i) {
548 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
549 do {
550 start = u64_stats_fetch_begin_irq(&p->syncp);
551 rx_packets = p->rx_packets;
552 rx_bytes = p->rx_bytes;
553 tx_packets = p->tx_packets;
554 tx_bytes = p->tx_bytes;
555 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
556
557 stats->rx_packets += rx_packets;
558 stats->rx_bytes += rx_bytes;
559 stats->tx_packets += tx_packets;
560 stats->tx_bytes += tx_bytes;
561 /* tx_dropped is u32, updated without syncp protection. */
562 tx_dropped += p->tx_dropped;
563 }
564 stats->tx_dropped = tx_dropped;
565 return stats;
566}
567
568int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
569 u16 vid_end, bool is_member, bool untagged)
570{
571 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
572 char *spvm_pl;
573 int err;
574
575 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
576 if (!spvm_pl)
577 return -ENOMEM;
578
579 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
580 vid_end, is_member, untagged);
581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
582 kfree(spvm_pl);
583 return err;
584}
585
586static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
587{
588 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
589 u16 vid, last_visited_vid;
590 int err;
591
592 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
593 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
594 vid);
595 if (err) {
596 last_visited_vid = vid;
597 goto err_port_vid_to_fid_set;
598 }
599 }
600
601 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
602 if (err) {
603 last_visited_vid = VLAN_N_VID;
604 goto err_port_vid_to_fid_set;
605 }
606
607 return 0;
608
609err_port_vid_to_fid_set:
610 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
611 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
612 vid);
613 return err;
614}
615
616static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
617{
618 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
619 u16 vid;
620 int err;
621
622 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
623 if (err)
624 return err;
625
626 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
627 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
628 vid, vid);
629 if (err)
630 return err;
631 }
632
633 return 0;
634}
635
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200636static struct mlxsw_sp_fid *
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100637mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
638{
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200639 struct mlxsw_sp_fid *f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100640
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200641 list_for_each_entry(f, &mlxsw_sp->port_vfids.list, list) {
642 if (f->vid == vid)
643 return f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100644 }
645
646 return NULL;
647}
648
649static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
650{
651 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
652 MLXSW_SP_VFID_PORT_MAX);
653}
654
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200655static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100656{
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100657 char sfmr_pl[MLXSW_REG_SFMR_LEN];
658
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200659 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100660 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
661}
662
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200663static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
664 u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100665{
666 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200667 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200668 u16 vfid, fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100669 int err;
670
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200671 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
672 if (vfid == MLXSW_SP_VFID_PORT_MAX) {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100673 dev_err(dev, "No available vFIDs\n");
674 return ERR_PTR(-ERANGE);
675 }
676
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200677 fid = mlxsw_sp_vfid_to_fid(vfid);
678 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100679 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200680 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100681 return ERR_PTR(err);
682 }
683
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200684 f = kzalloc(sizeof(*f), GFP_KERNEL);
685 if (!f)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100686 goto err_allocate_vfid;
687
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200688 f->fid = fid;
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200689 f->vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100690
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200691 list_add(&f->list, &mlxsw_sp->port_vfids.list);
692 set_bit(vfid, mlxsw_sp->port_vfids.mapped);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100693
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200694 return f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100695
696err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200697 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100698 return ERR_PTR(-ENOMEM);
699}
700
701static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200702 struct mlxsw_sp_fid *f)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100703{
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200704 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200705
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200706 clear_bit(vfid, mlxsw_sp->port_vfids.mapped);
707 list_del(&f->list);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100708
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200709 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100710
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200711 kfree(f);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100712}
713
714static struct mlxsw_sp_port *
715mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200716 struct mlxsw_sp_fid *f)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100717{
718 struct mlxsw_sp_port *mlxsw_sp_vport;
719
720 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
721 if (!mlxsw_sp_vport)
722 return NULL;
723
724 /* dev will be set correctly after the VLAN device is linked
725 * with the real device. In case of bridge SELF invocation, dev
726 * will remain as is.
727 */
728 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
729 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
730 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
731 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +0100732 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
733 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200734 mlxsw_sp_vport->vport.f = f;
735 mlxsw_sp_vport->vport.vid = f->vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100736
737 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
738
739 return mlxsw_sp_vport;
740}
741
742static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
743{
744 list_del(&mlxsw_sp_vport->vport.list);
745 kfree(mlxsw_sp_vport);
746}
747
Ido Schimmel9c4d4422016-06-20 23:04:10 +0200748static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
749 bool valid)
750{
751 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
752 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
753
754 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
755 vid);
756}
757
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200758int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
759 u16 vid)
760{
761 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
762 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100763 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200764 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200765 int err;
766
767 /* VLAN 0 is added to HW filter when device goes up, but it is
768 * reserved in our case, so simply return.
769 */
770 if (!vid)
771 return 0;
772
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100773 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200774 netdev_warn(dev, "VID=%d already configured\n", vid);
775 return 0;
776 }
777
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200778 f = mlxsw_sp_vfid_find(mlxsw_sp, vid);
779 if (!f) {
780 f = mlxsw_sp_vfid_create(mlxsw_sp, vid);
781 if (IS_ERR(f)) {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100782 netdev_err(dev, "Failed to create vFID for VID=%d\n",
783 vid);
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200784 return PTR_ERR(f);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200785 }
786 }
787
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200788 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, f);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100789 if (!mlxsw_sp_vport) {
790 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
791 err = -ENOMEM;
792 goto err_port_vport_create;
793 }
794
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200795 if (!f->ref_count) {
796 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100797 if (err) {
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200798 netdev_err(dev, "Failed to setup flooding for FID=%d\n",
799 f->fid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100800 goto err_vport_flood_set;
801 }
802 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200803
804 /* When adding the first VLAN interface on a bridged port we need to
805 * transition all the active 802.1Q bridge VLANs to use explicit
806 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
807 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100808 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200809 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
810 if (err) {
811 netdev_err(dev, "Failed to set to Virtual mode\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100812 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200813 }
814 }
815
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200816 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200817 if (err) {
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200818 netdev_err(dev, "Failed to map {Port, VID=%d} to FID=%d\n",
819 vid, f->fid);
Ido Schimmel9c4d4422016-06-20 23:04:10 +0200820 goto err_vport_fid_map;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200821 }
822
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100823 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200824 if (err) {
825 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
826 goto err_port_vid_learning_set;
827 }
828
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100829 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200830 if (err) {
831 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
832 vid);
833 goto err_port_add_vid;
834 }
835
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100836 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200837 MLXSW_REG_SPMS_STATE_FORWARDING);
838 if (err) {
839 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
840 goto err_port_stp_state_set;
841 }
842
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200843 f->ref_count++;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200844
845 return 0;
846
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200847err_port_stp_state_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100848 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200849err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100850 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200851err_port_vid_learning_set:
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200852 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
Ido Schimmel9c4d4422016-06-20 23:04:10 +0200853err_vport_fid_map:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100854 if (list_is_singular(&mlxsw_sp_port->vports_list))
855 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
856err_port_vp_mode_trans:
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200857 if (!f->ref_count)
858 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100859err_vport_flood_set:
860 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
861err_port_vport_create:
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200862 if (!f->ref_count)
863 mlxsw_sp_vfid_destroy(mlxsw_sp, f);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200864 return err;
865}
866
867int mlxsw_sp_port_kill_vid(struct net_device *dev,
868 __be16 __always_unused proto, u16 vid)
869{
870 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100871 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200872 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200873 int err;
874
875 /* VLAN 0 is removed from HW filter when device goes down, but
876 * it is reserved in our case, so simply return.
877 */
878 if (!vid)
879 return 0;
880
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100881 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
882 if (!mlxsw_sp_vport) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200883 netdev_warn(dev, "VID=%d does not exist\n", vid);
884 return 0;
885 }
886
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200887 f = mlxsw_sp_vport->vport.f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100888
889 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 MLXSW_REG_SPMS_STATE_DISCARDING);
891 if (err) {
892 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
893 return err;
894 }
895
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100896 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897 if (err) {
898 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
899 vid);
900 return err;
901 }
902
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100903 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200904 if (err) {
905 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
906 return err;
907 }
908
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200909 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200910 if (err) {
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200911 netdev_err(dev, "Failed to invalidate {Port, VID=%d} to FID=%d mapping\n",
912 vid, f->fid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200913 return err;
914 }
915
916 /* When removing the last VLAN interface on a bridged port we need to
917 * transition all active 802.1Q bridge VLANs to use VID to FID
918 * mappings and set port's mode to VLAN mode.
919 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100920 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200921 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
922 if (err) {
923 netdev_err(dev, "Failed to set to VLAN mode\n");
924 return err;
925 }
926 }
927
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200928 f->ref_count--;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100929 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
930
931 /* Destroy the vFID if no vPorts are assigned to it anymore. */
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200932 if (!f->ref_count)
933 mlxsw_sp_vfid_destroy(mlxsw_sp_port->mlxsw_sp, f);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200934
935 return 0;
936}
937
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200938static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
939 size_t len)
940{
941 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +0200942 u8 module = mlxsw_sp_port->mapping.module;
943 u8 width = mlxsw_sp_port->mapping.width;
944 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200945 int err;
946
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200947 if (!mlxsw_sp_port->split)
948 err = snprintf(name, len, "p%d", module + 1);
949 else
950 err = snprintf(name, len, "p%ds%d", module + 1,
951 lane / width);
952
953 if (err >= len)
954 return -EINVAL;
955
956 return 0;
957}
958
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200959static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
960 .ndo_open = mlxsw_sp_port_open,
961 .ndo_stop = mlxsw_sp_port_stop,
962 .ndo_start_xmit = mlxsw_sp_port_xmit,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100963 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200964 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
965 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
966 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
967 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
968 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
969 .ndo_fdb_add = switchdev_port_fdb_add,
970 .ndo_fdb_del = switchdev_port_fdb_del,
971 .ndo_fdb_dump = switchdev_port_fdb_dump,
972 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
973 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
974 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200975 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200976};
977
978static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
979 struct ethtool_drvinfo *drvinfo)
980{
981 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
982 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
983
984 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
985 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
986 sizeof(drvinfo->version));
987 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
988 "%d.%d.%d",
989 mlxsw_sp->bus_info->fw_rev.major,
990 mlxsw_sp->bus_info->fw_rev.minor,
991 mlxsw_sp->bus_info->fw_rev.subminor);
992 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
993 sizeof(drvinfo->bus_info));
994}
995
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200996static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
997 struct ethtool_pauseparam *pause)
998{
999 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1000
1001 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1002 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1003}
1004
1005static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1006 struct ethtool_pauseparam *pause)
1007{
1008 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1009
1010 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1011 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1012 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1013
1014 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1015 pfcc_pl);
1016}
1017
1018static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1019 struct ethtool_pauseparam *pause)
1020{
1021 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1022 bool pause_en = pause->tx_pause || pause->rx_pause;
1023 int err;
1024
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001025 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1026 netdev_err(dev, "PFC already enabled on port\n");
1027 return -EINVAL;
1028 }
1029
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001030 if (pause->autoneg) {
1031 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1032 return -EINVAL;
1033 }
1034
1035 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1036 if (err) {
1037 netdev_err(dev, "Failed to configure port's headroom\n");
1038 return err;
1039 }
1040
1041 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1042 if (err) {
1043 netdev_err(dev, "Failed to set PAUSE parameters\n");
1044 goto err_port_pause_configure;
1045 }
1046
1047 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1048 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1049
1050 return 0;
1051
1052err_port_pause_configure:
1053 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1054 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1055 return err;
1056}
1057
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001058struct mlxsw_sp_port_hw_stats {
1059 char str[ETH_GSTRING_LEN];
1060 u64 (*getter)(char *payload);
1061};
1062
1063static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1064 {
1065 .str = "a_frames_transmitted_ok",
1066 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1067 },
1068 {
1069 .str = "a_frames_received_ok",
1070 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1071 },
1072 {
1073 .str = "a_frame_check_sequence_errors",
1074 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1075 },
1076 {
1077 .str = "a_alignment_errors",
1078 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1079 },
1080 {
1081 .str = "a_octets_transmitted_ok",
1082 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1083 },
1084 {
1085 .str = "a_octets_received_ok",
1086 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1087 },
1088 {
1089 .str = "a_multicast_frames_xmitted_ok",
1090 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1091 },
1092 {
1093 .str = "a_broadcast_frames_xmitted_ok",
1094 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1095 },
1096 {
1097 .str = "a_multicast_frames_received_ok",
1098 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1099 },
1100 {
1101 .str = "a_broadcast_frames_received_ok",
1102 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1103 },
1104 {
1105 .str = "a_in_range_length_errors",
1106 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1107 },
1108 {
1109 .str = "a_out_of_range_length_field",
1110 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1111 },
1112 {
1113 .str = "a_frame_too_long_errors",
1114 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1115 },
1116 {
1117 .str = "a_symbol_error_during_carrier",
1118 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1119 },
1120 {
1121 .str = "a_mac_control_frames_transmitted",
1122 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1123 },
1124 {
1125 .str = "a_mac_control_frames_received",
1126 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1127 },
1128 {
1129 .str = "a_unsupported_opcodes_received",
1130 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1131 },
1132 {
1133 .str = "a_pause_mac_ctrl_frames_received",
1134 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1135 },
1136 {
1137 .str = "a_pause_mac_ctrl_frames_xmitted",
1138 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1139 },
1140};
1141
1142#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1143
1144static void mlxsw_sp_port_get_strings(struct net_device *dev,
1145 u32 stringset, u8 *data)
1146{
1147 u8 *p = data;
1148 int i;
1149
1150 switch (stringset) {
1151 case ETH_SS_STATS:
1152 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1153 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1154 ETH_GSTRING_LEN);
1155 p += ETH_GSTRING_LEN;
1156 }
1157 break;
1158 }
1159}
1160
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001161static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1162 enum ethtool_phys_id_state state)
1163{
1164 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1165 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1166 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1167 bool active;
1168
1169 switch (state) {
1170 case ETHTOOL_ID_ACTIVE:
1171 active = true;
1172 break;
1173 case ETHTOOL_ID_INACTIVE:
1174 active = false;
1175 break;
1176 default:
1177 return -EOPNOTSUPP;
1178 }
1179
1180 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1181 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1182}
1183
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001184static void mlxsw_sp_port_get_stats(struct net_device *dev,
1185 struct ethtool_stats *stats, u64 *data)
1186{
1187 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1188 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1189 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1190 int i;
1191 int err;
1192
Ido Schimmel34dba0a2016-04-06 17:10:15 +02001193 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1194 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001195 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1196 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1197 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1198}
1199
1200static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1201{
1202 switch (sset) {
1203 case ETH_SS_STATS:
1204 return MLXSW_SP_PORT_HW_STATS_LEN;
1205 default:
1206 return -EOPNOTSUPP;
1207 }
1208}
1209
1210struct mlxsw_sp_port_link_mode {
1211 u32 mask;
1212 u32 supported;
1213 u32 advertised;
1214 u32 speed;
1215};
1216
1217static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1218 {
1219 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1220 .supported = SUPPORTED_100baseT_Full,
1221 .advertised = ADVERTISED_100baseT_Full,
1222 .speed = 100,
1223 },
1224 {
1225 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1226 .speed = 100,
1227 },
1228 {
1229 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1230 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1231 .supported = SUPPORTED_1000baseKX_Full,
1232 .advertised = ADVERTISED_1000baseKX_Full,
1233 .speed = 1000,
1234 },
1235 {
1236 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1237 .supported = SUPPORTED_10000baseT_Full,
1238 .advertised = ADVERTISED_10000baseT_Full,
1239 .speed = 10000,
1240 },
1241 {
1242 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1243 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1244 .supported = SUPPORTED_10000baseKX4_Full,
1245 .advertised = ADVERTISED_10000baseKX4_Full,
1246 .speed = 10000,
1247 },
1248 {
1249 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1250 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1251 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1252 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1253 .supported = SUPPORTED_10000baseKR_Full,
1254 .advertised = ADVERTISED_10000baseKR_Full,
1255 .speed = 10000,
1256 },
1257 {
1258 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1259 .supported = SUPPORTED_20000baseKR2_Full,
1260 .advertised = ADVERTISED_20000baseKR2_Full,
1261 .speed = 20000,
1262 },
1263 {
1264 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1265 .supported = SUPPORTED_40000baseCR4_Full,
1266 .advertised = ADVERTISED_40000baseCR4_Full,
1267 .speed = 40000,
1268 },
1269 {
1270 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1271 .supported = SUPPORTED_40000baseKR4_Full,
1272 .advertised = ADVERTISED_40000baseKR4_Full,
1273 .speed = 40000,
1274 },
1275 {
1276 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1277 .supported = SUPPORTED_40000baseSR4_Full,
1278 .advertised = ADVERTISED_40000baseSR4_Full,
1279 .speed = 40000,
1280 },
1281 {
1282 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1283 .supported = SUPPORTED_40000baseLR4_Full,
1284 .advertised = ADVERTISED_40000baseLR4_Full,
1285 .speed = 40000,
1286 },
1287 {
1288 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1289 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1290 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1291 .speed = 25000,
1292 },
1293 {
1294 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1295 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1296 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1297 .speed = 50000,
1298 },
1299 {
1300 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1301 .supported = SUPPORTED_56000baseKR4_Full,
1302 .advertised = ADVERTISED_56000baseKR4_Full,
1303 .speed = 56000,
1304 },
1305 {
1306 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1307 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1308 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1309 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1310 .speed = 100000,
1311 },
1312};
1313
1314#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1315
1316static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1317{
1318 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1319 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1320 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1321 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1322 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1323 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1324 return SUPPORTED_FIBRE;
1325
1326 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1327 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1328 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1329 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1330 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1331 return SUPPORTED_Backplane;
1332 return 0;
1333}
1334
1335static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1336{
1337 u32 modes = 0;
1338 int i;
1339
1340 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1341 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1342 modes |= mlxsw_sp_port_link_mode[i].supported;
1343 }
1344 return modes;
1345}
1346
1347static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1348{
1349 u32 modes = 0;
1350 int i;
1351
1352 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1353 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1354 modes |= mlxsw_sp_port_link_mode[i].advertised;
1355 }
1356 return modes;
1357}
1358
1359static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1360 struct ethtool_cmd *cmd)
1361{
1362 u32 speed = SPEED_UNKNOWN;
1363 u8 duplex = DUPLEX_UNKNOWN;
1364 int i;
1365
1366 if (!carrier_ok)
1367 goto out;
1368
1369 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1370 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1371 speed = mlxsw_sp_port_link_mode[i].speed;
1372 duplex = DUPLEX_FULL;
1373 break;
1374 }
1375 }
1376out:
1377 ethtool_cmd_speed_set(cmd, speed);
1378 cmd->duplex = duplex;
1379}
1380
1381static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1382{
1383 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1384 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1385 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1386 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1387 return PORT_FIBRE;
1388
1389 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1390 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1391 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1392 return PORT_DA;
1393
1394 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1395 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1396 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1397 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1398 return PORT_NONE;
1399
1400 return PORT_OTHER;
1401}
1402
1403static int mlxsw_sp_port_get_settings(struct net_device *dev,
1404 struct ethtool_cmd *cmd)
1405{
1406 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1407 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1408 char ptys_pl[MLXSW_REG_PTYS_LEN];
1409 u32 eth_proto_cap;
1410 u32 eth_proto_admin;
1411 u32 eth_proto_oper;
1412 int err;
1413
1414 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1415 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1416 if (err) {
1417 netdev_err(dev, "Failed to get proto");
1418 return err;
1419 }
1420 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1421 &eth_proto_admin, &eth_proto_oper);
1422
1423 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1424 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1425 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1426 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1427 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1428 eth_proto_oper, cmd);
1429
1430 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1431 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1432 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1433
1434 cmd->transceiver = XCVR_INTERNAL;
1435 return 0;
1436}
1437
1438static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1439{
1440 u32 ptys_proto = 0;
1441 int i;
1442
1443 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1444 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1445 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1446 }
1447 return ptys_proto;
1448}
1449
1450static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1451{
1452 u32 ptys_proto = 0;
1453 int i;
1454
1455 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1456 if (speed == mlxsw_sp_port_link_mode[i].speed)
1457 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1458 }
1459 return ptys_proto;
1460}
1461
Ido Schimmel18f1e702016-02-26 17:32:31 +01001462static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1463{
1464 u32 ptys_proto = 0;
1465 int i;
1466
1467 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1468 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1469 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1470 }
1471 return ptys_proto;
1472}
1473
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001474static int mlxsw_sp_port_set_settings(struct net_device *dev,
1475 struct ethtool_cmd *cmd)
1476{
1477 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1478 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1479 char ptys_pl[MLXSW_REG_PTYS_LEN];
1480 u32 speed;
1481 u32 eth_proto_new;
1482 u32 eth_proto_cap;
1483 u32 eth_proto_admin;
1484 bool is_up;
1485 int err;
1486
1487 speed = ethtool_cmd_speed(cmd);
1488
1489 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1490 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1491 mlxsw_sp_to_ptys_speed(speed);
1492
1493 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1494 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1495 if (err) {
1496 netdev_err(dev, "Failed to get proto");
1497 return err;
1498 }
1499 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1500
1501 eth_proto_new = eth_proto_new & eth_proto_cap;
1502 if (!eth_proto_new) {
1503 netdev_err(dev, "Not supported proto admin requested");
1504 return -EINVAL;
1505 }
1506 if (eth_proto_new == eth_proto_admin)
1507 return 0;
1508
1509 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1510 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1511 if (err) {
1512 netdev_err(dev, "Failed to set proto admin");
1513 return err;
1514 }
1515
1516 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1517 if (err) {
1518 netdev_err(dev, "Failed to get oper status");
1519 return err;
1520 }
1521 if (!is_up)
1522 return 0;
1523
1524 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1525 if (err) {
1526 netdev_err(dev, "Failed to set admin status");
1527 return err;
1528 }
1529
1530 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1531 if (err) {
1532 netdev_err(dev, "Failed to set admin status");
1533 return err;
1534 }
1535
1536 return 0;
1537}
1538
1539static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1540 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1541 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001542 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1543 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001544 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001545 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001546 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1547 .get_sset_count = mlxsw_sp_port_get_sset_count,
1548 .get_settings = mlxsw_sp_port_get_settings,
1549 .set_settings = mlxsw_sp_port_set_settings,
1550};
1551
Ido Schimmel18f1e702016-02-26 17:32:31 +01001552static int
1553mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1554{
1555 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1556 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1557 char ptys_pl[MLXSW_REG_PTYS_LEN];
1558 u32 eth_proto_admin;
1559
1560 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1561 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1562 eth_proto_admin);
1563 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1564}
1565
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001566int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1567 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1568 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02001569{
1570 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1571 char qeec_pl[MLXSW_REG_QEEC_LEN];
1572
1573 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1574 next_index);
1575 mlxsw_reg_qeec_de_set(qeec_pl, true);
1576 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1577 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1578 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1579}
1580
Ido Schimmelcc7cf512016-04-06 17:10:11 +02001581int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1582 enum mlxsw_reg_qeec_hr hr, u8 index,
1583 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02001584{
1585 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1586 char qeec_pl[MLXSW_REG_QEEC_LEN];
1587
1588 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1589 next_index);
1590 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1591 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1592 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1593}
1594
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001595int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1596 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02001597{
1598 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1599 char qtct_pl[MLXSW_REG_QTCT_LEN];
1600
1601 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1602 tclass);
1603 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1604}
1605
1606static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1607{
1608 int err, i;
1609
1610 /* Setup the elements hierarcy, so that each TC is linked to
1611 * one subgroup, which are all member in the same group.
1612 */
1613 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1614 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1615 0);
1616 if (err)
1617 return err;
1618 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1619 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1620 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1621 0, false, 0);
1622 if (err)
1623 return err;
1624 }
1625 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1626 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1627 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1628 false, 0);
1629 if (err)
1630 return err;
1631 }
1632
1633 /* Make sure the max shaper is disabled in all hierarcies that
1634 * support it.
1635 */
1636 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1637 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1638 MLXSW_REG_QEEC_MAS_DIS);
1639 if (err)
1640 return err;
1641 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1642 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1643 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1644 i, 0,
1645 MLXSW_REG_QEEC_MAS_DIS);
1646 if (err)
1647 return err;
1648 }
1649 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1650 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1651 MLXSW_REG_QEEC_HIERARCY_TC,
1652 i, i,
1653 MLXSW_REG_QEEC_MAS_DIS);
1654 if (err)
1655 return err;
1656 }
1657
1658 /* Map all priorities to traffic class 0. */
1659 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1660 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1661 if (err)
1662 return err;
1663 }
1664
1665 return 0;
1666}
1667
Ido Schimmelbe945352016-06-09 09:51:39 +02001668static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
Ido Schimmeld664b412016-06-09 09:51:40 +02001669 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001670{
1671 struct mlxsw_sp_port *mlxsw_sp_port;
1672 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001673 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001674 int err;
1675
1676 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1677 if (!dev)
1678 return -ENOMEM;
1679 mlxsw_sp_port = netdev_priv(dev);
1680 mlxsw_sp_port->dev = dev;
1681 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1682 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001683 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02001684 mlxsw_sp_port->mapping.module = module;
1685 mlxsw_sp_port->mapping.width = width;
1686 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001687 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1688 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1689 if (!mlxsw_sp_port->active_vlans) {
1690 err = -ENOMEM;
1691 goto err_port_active_vlans_alloc;
1692 }
Elad Razfc1273a2016-01-06 13:01:11 +01001693 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1694 if (!mlxsw_sp_port->untagged_vlans) {
1695 err = -ENOMEM;
1696 goto err_port_untagged_vlans_alloc;
1697 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001698 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001699
1700 mlxsw_sp_port->pcpu_stats =
1701 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1702 if (!mlxsw_sp_port->pcpu_stats) {
1703 err = -ENOMEM;
1704 goto err_alloc_stats;
1705 }
1706
1707 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1708 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1709
1710 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1711 if (err) {
1712 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1713 mlxsw_sp_port->local_port);
1714 goto err_dev_addr_init;
1715 }
1716
1717 netif_carrier_off(dev);
1718
1719 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1720 NETIF_F_HW_VLAN_CTAG_FILTER;
1721
1722 /* Each packet needs to have a Tx header (metadata) on top all other
1723 * headers.
1724 */
1725 dev->hard_header_len += MLXSW_TXHDR_LEN;
1726
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001727 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1728 if (err) {
1729 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1730 mlxsw_sp_port->local_port);
1731 goto err_port_system_port_mapping_set;
1732 }
1733
1734 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1735 if (err) {
1736 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1737 mlxsw_sp_port->local_port);
1738 goto err_port_swid_set;
1739 }
1740
Ido Schimmel18f1e702016-02-26 17:32:31 +01001741 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1742 if (err) {
1743 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1744 mlxsw_sp_port->local_port);
1745 goto err_port_speed_by_width_set;
1746 }
1747
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001748 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1749 if (err) {
1750 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1751 mlxsw_sp_port->local_port);
1752 goto err_port_mtu_set;
1753 }
1754
1755 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1756 if (err)
1757 goto err_port_admin_status_set;
1758
1759 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1760 if (err) {
1761 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1762 mlxsw_sp_port->local_port);
1763 goto err_port_buffers_init;
1764 }
1765
Ido Schimmel90183b92016-04-06 17:10:08 +02001766 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1767 if (err) {
1768 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1769 mlxsw_sp_port->local_port);
1770 goto err_port_ets_init;
1771 }
1772
Ido Schimmelf00817d2016-04-06 17:10:09 +02001773 /* ETS and buffers must be initialized before DCB. */
1774 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1775 if (err) {
1776 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1777 mlxsw_sp_port->local_port);
1778 goto err_port_dcb_init;
1779 }
1780
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001781 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1782 err = register_netdev(dev);
1783 if (err) {
1784 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1785 mlxsw_sp_port->local_port);
1786 goto err_register_netdev;
1787 }
1788
Jiri Pirko932762b2016-04-08 19:11:21 +02001789 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1790 mlxsw_sp_port->local_port, dev,
1791 mlxsw_sp_port->split, module);
1792 if (err) {
1793 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1794 mlxsw_sp_port->local_port);
1795 goto err_core_port_init;
1796 }
Jiri Pirkoc4745502016-02-26 17:32:26 +01001797
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001798 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1799 if (err)
1800 goto err_port_vlan_init;
1801
1802 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1803 return 0;
1804
1805err_port_vlan_init:
Jiri Pirko932762b2016-04-08 19:11:21 +02001806 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1807err_core_port_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001808 unregister_netdev(dev);
1809err_register_netdev:
Ido Schimmelf00817d2016-04-06 17:10:09 +02001810err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02001811err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001812err_port_buffers_init:
1813err_port_admin_status_set:
1814err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01001815err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001816err_port_swid_set:
1817err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001818err_dev_addr_init:
1819 free_percpu(mlxsw_sp_port->pcpu_stats);
1820err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01001821 kfree(mlxsw_sp_port->untagged_vlans);
1822err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001823 kfree(mlxsw_sp_port->active_vlans);
1824err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001825 free_netdev(dev);
1826 return err;
1827}
1828
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001829static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001830{
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001831 struct net_device *dev = mlxsw_sp_port->dev;
1832 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001833
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001834 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1835 &mlxsw_sp_port->vports_list, vport.list) {
1836 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1837
1838 /* vPorts created for VLAN devices should already be gone
1839 * by now, since we unregistered the port netdev.
1840 */
1841 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1842 mlxsw_sp_port_kill_vid(dev, 0, vid);
1843 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001844}
1845
1846static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1847{
1848 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1849
1850 if (!mlxsw_sp_port)
1851 return;
Ido Schimmela1333182016-02-26 17:32:30 +01001852 mlxsw_sp->ports[local_port] = NULL;
Jiri Pirko932762b2016-04-08 19:11:21 +02001853 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001854 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmelf00817d2016-04-06 17:10:09 +02001855 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001856 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001857 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001858 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1859 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001860 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01001861 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001862 kfree(mlxsw_sp_port->active_vlans);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001863 free_netdev(mlxsw_sp_port->dev);
1864}
1865
1866static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1867{
1868 int i;
1869
1870 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1871 mlxsw_sp_port_remove(mlxsw_sp, i);
1872 kfree(mlxsw_sp->ports);
1873}
1874
1875static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1876{
Ido Schimmeld664b412016-06-09 09:51:40 +02001877 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001878 size_t alloc_size;
1879 int i;
1880 int err;
1881
1882 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1883 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1884 if (!mlxsw_sp->ports)
1885 return -ENOMEM;
1886
1887 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01001888 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02001889 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01001890 if (err)
1891 goto err_port_module_info_get;
1892 if (!width)
1893 continue;
1894 mlxsw_sp->port_to_module[i] = module;
Ido Schimmeld664b412016-06-09 09:51:40 +02001895 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1896 lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001897 if (err)
1898 goto err_port_create;
1899 }
1900 return 0;
1901
1902err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01001903err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001904 for (i--; i >= 1; i--)
1905 mlxsw_sp_port_remove(mlxsw_sp, i);
1906 kfree(mlxsw_sp->ports);
1907 return err;
1908}
1909
Ido Schimmel18f1e702016-02-26 17:32:31 +01001910static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1911{
1912 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1913
1914 return local_port - offset;
1915}
1916
Ido Schimmelbe945352016-06-09 09:51:39 +02001917static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1918 u8 module, unsigned int count)
1919{
1920 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1921 int err, i;
1922
1923 for (i = 0; i < count; i++) {
1924 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1925 width, i * width);
1926 if (err)
1927 goto err_port_module_map;
1928 }
1929
1930 for (i = 0; i < count; i++) {
1931 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1932 if (err)
1933 goto err_port_swid_set;
1934 }
1935
1936 for (i = 0; i < count; i++) {
1937 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02001938 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02001939 if (err)
1940 goto err_port_create;
1941 }
1942
1943 return 0;
1944
1945err_port_create:
1946 for (i--; i >= 0; i--)
1947 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1948 i = count;
1949err_port_swid_set:
1950 for (i--; i >= 0; i--)
1951 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1952 MLXSW_PORT_SWID_DISABLED_PORT);
1953 i = count;
1954err_port_module_map:
1955 for (i--; i >= 0; i--)
1956 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1957 return err;
1958}
1959
1960static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1961 u8 base_port, unsigned int count)
1962{
1963 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1964 int i;
1965
1966 /* Split by four means we need to re-create two ports, otherwise
1967 * only one.
1968 */
1969 count = count / 2;
1970
1971 for (i = 0; i < count; i++) {
1972 local_port = base_port + i * 2;
1973 module = mlxsw_sp->port_to_module[local_port];
1974
1975 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1976 0);
1977 }
1978
1979 for (i = 0; i < count; i++)
1980 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
1981
1982 for (i = 0; i < count; i++) {
1983 local_port = base_port + i * 2;
1984 module = mlxsw_sp->port_to_module[local_port];
1985
1986 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02001987 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02001988 }
1989}
1990
Jiri Pirkob2f10572016-04-08 19:11:23 +02001991static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
1992 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01001993{
Jiri Pirkob2f10572016-04-08 19:11:23 +02001994 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01001995 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001996 u8 module, cur_width, base_port;
1997 int i;
1998 int err;
1999
2000 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2001 if (!mlxsw_sp_port) {
2002 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2003 local_port);
2004 return -EINVAL;
2005 }
2006
Ido Schimmeld664b412016-06-09 09:51:40 +02002007 module = mlxsw_sp_port->mapping.module;
2008 cur_width = mlxsw_sp_port->mapping.width;
2009
Ido Schimmel18f1e702016-02-26 17:32:31 +01002010 if (count != 2 && count != 4) {
2011 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2012 return -EINVAL;
2013 }
2014
Ido Schimmel18f1e702016-02-26 17:32:31 +01002015 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2016 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2017 return -EINVAL;
2018 }
2019
2020 /* Make sure we have enough slave (even) ports for the split. */
2021 if (count == 2) {
2022 base_port = local_port;
2023 if (mlxsw_sp->ports[base_port + 1]) {
2024 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2025 return -EINVAL;
2026 }
2027 } else {
2028 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2029 if (mlxsw_sp->ports[base_port + 1] ||
2030 mlxsw_sp->ports[base_port + 3]) {
2031 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2032 return -EINVAL;
2033 }
2034 }
2035
2036 for (i = 0; i < count; i++)
2037 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2038
Ido Schimmelbe945352016-06-09 09:51:39 +02002039 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2040 if (err) {
2041 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2042 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002043 }
2044
2045 return 0;
2046
Ido Schimmelbe945352016-06-09 09:51:39 +02002047err_port_split_create:
2048 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002049 return err;
2050}
2051
Jiri Pirkob2f10572016-04-08 19:11:23 +02002052static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002053{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002054 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002055 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02002056 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002057 unsigned int count;
2058 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002059
2060 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2061 if (!mlxsw_sp_port) {
2062 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2063 local_port);
2064 return -EINVAL;
2065 }
2066
2067 if (!mlxsw_sp_port->split) {
2068 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2069 return -EINVAL;
2070 }
2071
Ido Schimmeld664b412016-06-09 09:51:40 +02002072 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002073 count = cur_width == 1 ? 4 : 2;
2074
2075 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2076
2077 /* Determine which ports to remove. */
2078 if (count == 2 && local_port >= base_port + 2)
2079 base_port = base_port + 2;
2080
2081 for (i = 0; i < count; i++)
2082 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2083
Ido Schimmelbe945352016-06-09 09:51:39 +02002084 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002085
2086 return 0;
2087}
2088
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002089static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2090 char *pude_pl, void *priv)
2091{
2092 struct mlxsw_sp *mlxsw_sp = priv;
2093 struct mlxsw_sp_port *mlxsw_sp_port;
2094 enum mlxsw_reg_pude_oper_status status;
2095 u8 local_port;
2096
2097 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2098 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2099 if (!mlxsw_sp_port) {
2100 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2101 local_port);
2102 return;
2103 }
2104
2105 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2106 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2107 netdev_info(mlxsw_sp_port->dev, "link up\n");
2108 netif_carrier_on(mlxsw_sp_port->dev);
2109 } else {
2110 netdev_info(mlxsw_sp_port->dev, "link down\n");
2111 netif_carrier_off(mlxsw_sp_port->dev);
2112 }
2113}
2114
2115static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2116 .func = mlxsw_sp_pude_event_func,
2117 .trap_id = MLXSW_TRAP_ID_PUDE,
2118};
2119
2120static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2121 enum mlxsw_event_trap_id trap_id)
2122{
2123 struct mlxsw_event_listener *el;
2124 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2125 int err;
2126
2127 switch (trap_id) {
2128 case MLXSW_TRAP_ID_PUDE:
2129 el = &mlxsw_sp_pude_event;
2130 break;
2131 }
2132 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2133 if (err)
2134 return err;
2135
2136 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2137 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2138 if (err)
2139 goto err_event_trap_set;
2140
2141 return 0;
2142
2143err_event_trap_set:
2144 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2145 return err;
2146}
2147
2148static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2149 enum mlxsw_event_trap_id trap_id)
2150{
2151 struct mlxsw_event_listener *el;
2152
2153 switch (trap_id) {
2154 case MLXSW_TRAP_ID_PUDE:
2155 el = &mlxsw_sp_pude_event;
2156 break;
2157 }
2158 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2159}
2160
2161static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2162 void *priv)
2163{
2164 struct mlxsw_sp *mlxsw_sp = priv;
2165 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2166 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2167
2168 if (unlikely(!mlxsw_sp_port)) {
2169 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2170 local_port);
2171 return;
2172 }
2173
2174 skb->dev = mlxsw_sp_port->dev;
2175
2176 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2177 u64_stats_update_begin(&pcpu_stats->syncp);
2178 pcpu_stats->rx_packets++;
2179 pcpu_stats->rx_bytes += skb->len;
2180 u64_stats_update_end(&pcpu_stats->syncp);
2181
2182 skb->protocol = eth_type_trans(skb, skb->dev);
2183 netif_receive_skb(skb);
2184}
2185
2186static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2187 {
2188 .func = mlxsw_sp_rx_listener_func,
2189 .local_port = MLXSW_PORT_DONT_CARE,
2190 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2191 },
2192 /* Traps for specific L2 packet types, not trapped as FDB MC */
2193 {
2194 .func = mlxsw_sp_rx_listener_func,
2195 .local_port = MLXSW_PORT_DONT_CARE,
2196 .trap_id = MLXSW_TRAP_ID_STP,
2197 },
2198 {
2199 .func = mlxsw_sp_rx_listener_func,
2200 .local_port = MLXSW_PORT_DONT_CARE,
2201 .trap_id = MLXSW_TRAP_ID_LACP,
2202 },
2203 {
2204 .func = mlxsw_sp_rx_listener_func,
2205 .local_port = MLXSW_PORT_DONT_CARE,
2206 .trap_id = MLXSW_TRAP_ID_EAPOL,
2207 },
2208 {
2209 .func = mlxsw_sp_rx_listener_func,
2210 .local_port = MLXSW_PORT_DONT_CARE,
2211 .trap_id = MLXSW_TRAP_ID_LLDP,
2212 },
2213 {
2214 .func = mlxsw_sp_rx_listener_func,
2215 .local_port = MLXSW_PORT_DONT_CARE,
2216 .trap_id = MLXSW_TRAP_ID_MMRP,
2217 },
2218 {
2219 .func = mlxsw_sp_rx_listener_func,
2220 .local_port = MLXSW_PORT_DONT_CARE,
2221 .trap_id = MLXSW_TRAP_ID_MVRP,
2222 },
2223 {
2224 .func = mlxsw_sp_rx_listener_func,
2225 .local_port = MLXSW_PORT_DONT_CARE,
2226 .trap_id = MLXSW_TRAP_ID_RPVST,
2227 },
2228 {
2229 .func = mlxsw_sp_rx_listener_func,
2230 .local_port = MLXSW_PORT_DONT_CARE,
2231 .trap_id = MLXSW_TRAP_ID_DHCP,
2232 },
2233 {
2234 .func = mlxsw_sp_rx_listener_func,
2235 .local_port = MLXSW_PORT_DONT_CARE,
2236 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2237 },
2238 {
2239 .func = mlxsw_sp_rx_listener_func,
2240 .local_port = MLXSW_PORT_DONT_CARE,
2241 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2242 },
2243 {
2244 .func = mlxsw_sp_rx_listener_func,
2245 .local_port = MLXSW_PORT_DONT_CARE,
2246 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2247 },
2248 {
2249 .func = mlxsw_sp_rx_listener_func,
2250 .local_port = MLXSW_PORT_DONT_CARE,
2251 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2252 },
2253 {
2254 .func = mlxsw_sp_rx_listener_func,
2255 .local_port = MLXSW_PORT_DONT_CARE,
2256 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2257 },
2258};
2259
2260static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2261{
2262 char htgt_pl[MLXSW_REG_HTGT_LEN];
2263 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2264 int i;
2265 int err;
2266
2267 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2268 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2269 if (err)
2270 return err;
2271
2272 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2273 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2274 if (err)
2275 return err;
2276
2277 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2278 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2279 &mlxsw_sp_rx_listener[i],
2280 mlxsw_sp);
2281 if (err)
2282 goto err_rx_listener_register;
2283
2284 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2285 mlxsw_sp_rx_listener[i].trap_id);
2286 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2287 if (err)
2288 goto err_rx_trap_set;
2289 }
2290 return 0;
2291
2292err_rx_trap_set:
2293 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2294 &mlxsw_sp_rx_listener[i],
2295 mlxsw_sp);
2296err_rx_listener_register:
2297 for (i--; i >= 0; i--) {
2298 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2299 mlxsw_sp_rx_listener[i].trap_id);
2300 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2301
2302 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2303 &mlxsw_sp_rx_listener[i],
2304 mlxsw_sp);
2305 }
2306 return err;
2307}
2308
2309static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2310{
2311 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2312 int i;
2313
2314 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2315 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2316 mlxsw_sp_rx_listener[i].trap_id);
2317 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2318
2319 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2320 &mlxsw_sp_rx_listener[i],
2321 mlxsw_sp);
2322 }
2323}
2324
2325static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2326 enum mlxsw_reg_sfgc_type type,
2327 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2328{
2329 enum mlxsw_flood_table_type table_type;
2330 enum mlxsw_sp_flood_table flood_table;
2331 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2332
Ido Schimmel19ae6122015-12-15 16:03:39 +01002333 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002334 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002335 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002336 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002337
2338 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2339 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2340 else
2341 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002342
2343 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2344 flood_table);
2345 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2346}
2347
2348static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2349{
2350 int type, err;
2351
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002352 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2353 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2354 continue;
2355
2356 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2357 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2358 if (err)
2359 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002360
2361 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2362 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2363 if (err)
2364 return err;
2365 }
2366
2367 return 0;
2368}
2369
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002370static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2371{
2372 char slcr_pl[MLXSW_REG_SLCR_LEN];
2373
2374 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2375 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2376 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2377 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2378 MLXSW_REG_SLCR_LAG_HASH_SIP |
2379 MLXSW_REG_SLCR_LAG_HASH_DIP |
2380 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2381 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2382 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2383 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2384}
2385
Jiri Pirkob2f10572016-04-08 19:11:23 +02002386static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002387 const struct mlxsw_bus_info *mlxsw_bus_info)
2388{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002389 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002390 int err;
2391
2392 mlxsw_sp->core = mlxsw_core;
2393 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002394 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002395 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
Elad Raz3a49b4f2016-01-10 21:06:28 +01002396 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002397
2398 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2399 if (err) {
2400 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2401 return err;
2402 }
2403
2404 err = mlxsw_sp_ports_create(mlxsw_sp);
2405 if (err) {
2406 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002407 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002408 }
2409
2410 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2411 if (err) {
2412 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2413 goto err_event_register;
2414 }
2415
2416 err = mlxsw_sp_traps_init(mlxsw_sp);
2417 if (err) {
2418 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2419 goto err_rx_listener_register;
2420 }
2421
2422 err = mlxsw_sp_flood_init(mlxsw_sp);
2423 if (err) {
2424 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2425 goto err_flood_init;
2426 }
2427
2428 err = mlxsw_sp_buffers_init(mlxsw_sp);
2429 if (err) {
2430 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2431 goto err_buffers_init;
2432 }
2433
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002434 err = mlxsw_sp_lag_init(mlxsw_sp);
2435 if (err) {
2436 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2437 goto err_lag_init;
2438 }
2439
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002440 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2441 if (err) {
2442 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2443 goto err_switchdev_init;
2444 }
2445
2446 return 0;
2447
2448err_switchdev_init:
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002449err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02002450 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002451err_buffers_init:
2452err_flood_init:
2453 mlxsw_sp_traps_fini(mlxsw_sp);
2454err_rx_listener_register:
2455 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2456err_event_register:
2457 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002458 return err;
2459}
2460
Jiri Pirkob2f10572016-04-08 19:11:23 +02002461static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002462{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002463 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002464
2465 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02002466 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002467 mlxsw_sp_traps_fini(mlxsw_sp);
2468 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2469 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002470}
2471
2472static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2473 .used_max_vepa_channels = 1,
2474 .max_vepa_channels = 0,
2475 .used_max_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002476 .max_lag = MLXSW_SP_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002477 .used_max_port_per_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002478 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002479 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01002480 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002481 .used_max_pgt = 1,
2482 .max_pgt = 0,
2483 .used_max_system_port = 1,
2484 .max_system_port = 64,
2485 .used_max_vlan_groups = 1,
2486 .max_vlan_groups = 127,
2487 .used_max_regions = 1,
2488 .max_regions = 400,
2489 .used_flood_tables = 1,
2490 .used_flood_mode = 1,
2491 .flood_mode = 3,
2492 .max_fid_offset_flood_tables = 2,
2493 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Ido Schimmel19ae6122015-12-15 16:03:39 +01002494 .max_fid_flood_tables = 2,
2495 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002496 .used_max_ib_mc = 1,
2497 .max_ib_mc = 0,
2498 .used_max_pkey = 1,
2499 .max_pkey = 0,
2500 .swid_config = {
2501 {
2502 .used_type = 1,
2503 .type = MLXSW_PORT_SWID_TYPE_ETH,
2504 }
2505 },
2506};
2507
2508static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko2d0ed392016-04-14 18:19:30 +02002509 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2510 .owner = THIS_MODULE,
2511 .priv_size = sizeof(struct mlxsw_sp),
2512 .init = mlxsw_sp_init,
2513 .fini = mlxsw_sp_fini,
2514 .port_split = mlxsw_sp_port_split,
2515 .port_unsplit = mlxsw_sp_port_unsplit,
2516 .sb_pool_get = mlxsw_sp_sb_pool_get,
2517 .sb_pool_set = mlxsw_sp_sb_pool_set,
2518 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2519 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2520 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2521 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2522 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2523 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2524 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2525 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2526 .txhdr_construct = mlxsw_sp_txhdr_construct,
2527 .txhdr_len = MLXSW_TXHDR_LEN,
2528 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002529};
2530
Ido Schimmel039c49a2016-01-27 15:20:18 +01002531static int
2532mlxsw_sp_port_fdb_flush_by_port(const struct mlxsw_sp_port *mlxsw_sp_port)
2533{
2534 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2535 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2536
2537 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT);
2538 mlxsw_reg_sfdf_system_port_set(sfdf_pl, mlxsw_sp_port->local_port);
2539
2540 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2541}
2542
2543static int
2544mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2545 u16 fid)
2546{
2547 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2548 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2549
2550 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2551 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2552 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2553 mlxsw_sp_port->local_port);
2554
2555 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2556}
2557
2558static int
2559mlxsw_sp_port_fdb_flush_by_lag_id(const struct mlxsw_sp_port *mlxsw_sp_port)
2560{
2561 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2562 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2563
2564 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG);
2565 mlxsw_reg_sfdf_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2566
2567 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2568}
2569
2570static int
2571mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2572 u16 fid)
2573{
2574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2575 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2576
2577 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2578 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2579 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2580
2581 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2582}
2583
2584static int
2585__mlxsw_sp_port_fdb_flush(const struct mlxsw_sp_port *mlxsw_sp_port)
2586{
2587 int err, last_err = 0;
2588 u16 vid;
2589
2590 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2591 err = mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, vid);
2592 if (err)
2593 last_err = err;
2594 }
2595
2596 return last_err;
2597}
2598
2599static int
2600__mlxsw_sp_port_fdb_flush_lagged(const struct mlxsw_sp_port *mlxsw_sp_port)
2601{
2602 int err, last_err = 0;
2603 u16 vid;
2604
2605 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2606 err = mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port, vid);
2607 if (err)
2608 last_err = err;
2609 }
2610
2611 return last_err;
2612}
2613
2614static int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port)
2615{
2616 if (!list_empty(&mlxsw_sp_port->vports_list))
2617 if (mlxsw_sp_port->lagged)
2618 return __mlxsw_sp_port_fdb_flush_lagged(mlxsw_sp_port);
2619 else
2620 return __mlxsw_sp_port_fdb_flush(mlxsw_sp_port);
2621 else
2622 if (mlxsw_sp_port->lagged)
2623 return mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port);
2624 else
2625 return mlxsw_sp_port_fdb_flush_by_port(mlxsw_sp_port);
2626}
2627
2628static int mlxsw_sp_vport_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_vport)
2629{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02002630 u16 fid = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002631
2632 if (mlxsw_sp_vport->lagged)
2633 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_vport,
2634 fid);
2635 else
2636 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_vport, fid);
2637}
2638
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002639static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2640{
2641 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2642}
2643
Ido Schimmel7117a572016-06-20 23:04:06 +02002644static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2645 struct net_device *br_dev)
2646{
2647 return !mlxsw_sp->master_bridge.dev ||
2648 mlxsw_sp->master_bridge.dev == br_dev;
2649}
2650
2651static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2652 struct net_device *br_dev)
2653{
2654 mlxsw_sp->master_bridge.dev = br_dev;
2655 mlxsw_sp->master_bridge.ref_count++;
2656}
2657
2658static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
2659{
2660 if (--mlxsw_sp->master_bridge.ref_count == 0)
2661 mlxsw_sp->master_bridge.dev = NULL;
2662}
2663
2664static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
2665 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002666{
2667 struct net_device *dev = mlxsw_sp_port->dev;
2668 int err;
2669
2670 /* When port is not bridged untagged packets are tagged with
2671 * PVID=VID=1, thereby creating an implicit VLAN interface in
2672 * the device. Remove it and let bridge code take care of its
2673 * own VLANs.
2674 */
2675 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002676 if (err)
2677 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002678
Ido Schimmel7117a572016-06-20 23:04:06 +02002679 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
2680
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002681 mlxsw_sp_port->learning = 1;
2682 mlxsw_sp_port->learning_sync = 1;
2683 mlxsw_sp_port->uc_flood = 1;
2684 mlxsw_sp_port->bridged = 1;
2685
2686 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002687}
2688
Ido Schimmel82e6db02016-06-20 23:04:04 +02002689static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2690 bool flush_fdb)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002691{
2692 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002693
Ido Schimmel039c49a2016-01-27 15:20:18 +01002694 if (flush_fdb && mlxsw_sp_port_fdb_flush(mlxsw_sp_port))
2695 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
2696
Ido Schimmel28a01d22016-02-18 11:30:02 +01002697 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2698
Ido Schimmel7117a572016-06-20 23:04:06 +02002699 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
2700
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002701 mlxsw_sp_port->learning = 0;
2702 mlxsw_sp_port->learning_sync = 0;
2703 mlxsw_sp_port->uc_flood = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002704 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002705
2706 /* Add implicit VLAN interface in the device, so that untagged
2707 * packets will be classified to the default vFID.
2708 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02002709 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002710}
2711
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002712static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002713{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002714 char sldr_pl[MLXSW_REG_SLDR_LEN];
2715
2716 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2717 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2718}
2719
2720static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2721{
2722 char sldr_pl[MLXSW_REG_SLDR_LEN];
2723
2724 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2725 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2726}
2727
2728static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2729 u16 lag_id, u8 port_index)
2730{
2731 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2732 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2733
2734 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2735 lag_id, port_index);
2736 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2737}
2738
2739static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2740 u16 lag_id)
2741{
2742 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2743 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2744
2745 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2746 lag_id);
2747 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2748}
2749
2750static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2751 u16 lag_id)
2752{
2753 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2754 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2755
2756 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2757 lag_id);
2758 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2759}
2760
2761static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2762 u16 lag_id)
2763{
2764 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2765 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2766
2767 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2768 lag_id);
2769 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2770}
2771
2772static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2773 struct net_device *lag_dev,
2774 u16 *p_lag_id)
2775{
2776 struct mlxsw_sp_upper *lag;
2777 int free_lag_id = -1;
2778 int i;
2779
2780 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2781 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2782 if (lag->ref_count) {
2783 if (lag->dev == lag_dev) {
2784 *p_lag_id = i;
2785 return 0;
2786 }
2787 } else if (free_lag_id < 0) {
2788 free_lag_id = i;
2789 }
2790 }
2791 if (free_lag_id < 0)
2792 return -EBUSY;
2793 *p_lag_id = free_lag_id;
2794 return 0;
2795}
2796
2797static bool
2798mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2799 struct net_device *lag_dev,
2800 struct netdev_lag_upper_info *lag_upper_info)
2801{
2802 u16 lag_id;
2803
2804 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2805 return false;
2806 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2807 return false;
2808 return true;
2809}
2810
2811static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2812 u16 lag_id, u8 *p_port_index)
2813{
2814 int i;
2815
2816 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2817 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2818 *p_port_index = i;
2819 return 0;
2820 }
2821 }
2822 return -EBUSY;
2823}
2824
2825static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2826 struct net_device *lag_dev)
2827{
2828 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2829 struct mlxsw_sp_upper *lag;
2830 u16 lag_id;
2831 u8 port_index;
2832 int err;
2833
2834 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2835 if (err)
2836 return err;
2837 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2838 if (!lag->ref_count) {
2839 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2840 if (err)
2841 return err;
2842 lag->dev = lag_dev;
2843 }
2844
2845 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2846 if (err)
2847 return err;
2848 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2849 if (err)
2850 goto err_col_port_add;
2851 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2852 if (err)
2853 goto err_col_port_enable;
2854
2855 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2856 mlxsw_sp_port->local_port);
2857 mlxsw_sp_port->lag_id = lag_id;
2858 mlxsw_sp_port->lagged = 1;
2859 lag->ref_count++;
2860 return 0;
2861
Ido Schimmel51554db2016-05-06 22:18:39 +02002862err_col_port_enable:
2863 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002864err_col_port_add:
2865 if (!lag->ref_count)
2866 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002867 return err;
2868}
2869
Ido Schimmel82e6db02016-06-20 23:04:04 +02002870static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
2871 struct net_device *br_dev,
2872 bool flush_fdb);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002873
Ido Schimmel82e6db02016-06-20 23:04:04 +02002874static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2875 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002876{
2877 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002878 struct mlxsw_sp_port *mlxsw_sp_vport;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002879 struct mlxsw_sp_upper *lag;
2880 u16 lag_id = mlxsw_sp_port->lag_id;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002881
2882 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02002883 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002884 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2885 WARN_ON(lag->ref_count == 0);
2886
Ido Schimmel82e6db02016-06-20 23:04:04 +02002887 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2888 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002889
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002890 /* In case we leave a LAG device that has bridges built on top,
2891 * then their teardown sequence is never issued and we need to
2892 * invoke the necessary cleanup routines ourselves.
2893 */
2894 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
2895 vport.list) {
2896 struct net_device *br_dev;
2897
2898 if (!mlxsw_sp_vport->bridged)
2899 continue;
2900
2901 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002902 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, false);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002903 }
2904
2905 if (mlxsw_sp_port->bridged) {
2906 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002907 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, false);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002908 }
2909
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002910 if (lag->ref_count == 1) {
Ido Schimmel039c49a2016-01-27 15:20:18 +01002911 if (mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port))
2912 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
Ido Schimmel82e6db02016-06-20 23:04:04 +02002913 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002914 }
2915
2916 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2917 mlxsw_sp_port->local_port);
2918 mlxsw_sp_port->lagged = 0;
2919 lag->ref_count--;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002920}
2921
Jiri Pirko74581202015-12-03 12:12:30 +01002922static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2923 u16 lag_id)
2924{
2925 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2926 char sldr_pl[MLXSW_REG_SLDR_LEN];
2927
2928 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2929 mlxsw_sp_port->local_port);
2930 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2931}
2932
2933static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2934 u16 lag_id)
2935{
2936 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2937 char sldr_pl[MLXSW_REG_SLDR_LEN];
2938
2939 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2940 mlxsw_sp_port->local_port);
2941 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2942}
2943
2944static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2945 bool lag_tx_enabled)
2946{
2947 if (lag_tx_enabled)
2948 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2949 mlxsw_sp_port->lag_id);
2950 else
2951 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2952 mlxsw_sp_port->lag_id);
2953}
2954
2955static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2956 struct netdev_lag_lower_state_info *info)
2957{
2958 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2959}
2960
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002961static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2962 struct net_device *vlan_dev)
2963{
2964 struct mlxsw_sp_port *mlxsw_sp_vport;
2965 u16 vid = vlan_dev_vlan_id(vlan_dev);
2966
2967 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02002968 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002969 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002970
2971 mlxsw_sp_vport->dev = vlan_dev;
2972
2973 return 0;
2974}
2975
Ido Schimmel82e6db02016-06-20 23:04:04 +02002976static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2977 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002978{
2979 struct mlxsw_sp_port *mlxsw_sp_vport;
2980 u16 vid = vlan_dev_vlan_id(vlan_dev);
2981
2982 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02002983 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02002984 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002985
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002986 /* When removing a VLAN device while still bridged we should first
2987 * remove it from the bridge, as we receive the bridge's notification
2988 * when the vPort is already gone.
2989 */
2990 if (mlxsw_sp_vport->bridged) {
2991 struct net_device *br_dev;
2992
2993 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002994 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002995 }
2996
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002997 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002998}
2999
Jiri Pirko74581202015-12-03 12:12:30 +01003000static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
3001 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003002{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003003 struct netdev_notifier_changeupper_info *info;
3004 struct mlxsw_sp_port *mlxsw_sp_port;
3005 struct net_device *upper_dev;
3006 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003007 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003008
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003009 mlxsw_sp_port = netdev_priv(dev);
3010 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3011 info = ptr;
3012
3013 switch (event) {
3014 case NETDEV_PRECHANGEUPPER:
3015 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02003016 if (!is_vlan_dev(upper_dev) &&
3017 !netif_is_lag_master(upper_dev) &&
3018 !netif_is_bridge_master(upper_dev))
3019 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02003020 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003021 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003022 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003023 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003024 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003025 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003026 if (netif_is_lag_master(upper_dev) &&
3027 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3028 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003029 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02003030 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
3031 return -EINVAL;
3032 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
3033 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
3034 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003035 break;
3036 case NETDEV_CHANGEUPPER:
3037 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003038 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02003039 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003040 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3041 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003042 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003043 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3044 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003045 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02003046 if (info->linking)
3047 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
3048 upper_dev);
3049 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003050 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, true);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003051 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02003052 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003053 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3054 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003055 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003056 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3057 upper_dev);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02003058 } else {
3059 err = -EINVAL;
3060 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003061 }
3062 break;
3063 }
3064
Ido Schimmel80bedf12016-06-20 23:03:59 +02003065 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003066}
3067
Jiri Pirko74581202015-12-03 12:12:30 +01003068static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3069 unsigned long event, void *ptr)
3070{
3071 struct netdev_notifier_changelowerstate_info *info;
3072 struct mlxsw_sp_port *mlxsw_sp_port;
3073 int err;
3074
3075 mlxsw_sp_port = netdev_priv(dev);
3076 info = ptr;
3077
3078 switch (event) {
3079 case NETDEV_CHANGELOWERSTATE:
3080 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3081 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3082 info->lower_state_info);
3083 if (err)
3084 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3085 }
3086 break;
3087 }
3088
Ido Schimmel80bedf12016-06-20 23:03:59 +02003089 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01003090}
3091
3092static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3093 unsigned long event, void *ptr)
3094{
3095 switch (event) {
3096 case NETDEV_PRECHANGEUPPER:
3097 case NETDEV_CHANGEUPPER:
3098 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3099 case NETDEV_CHANGELOWERSTATE:
3100 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3101 }
3102
Ido Schimmel80bedf12016-06-20 23:03:59 +02003103 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01003104}
3105
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003106static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3107 unsigned long event, void *ptr)
3108{
3109 struct net_device *dev;
3110 struct list_head *iter;
3111 int ret;
3112
3113 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3114 if (mlxsw_sp_port_dev_check(dev)) {
3115 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003116 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003117 return ret;
3118 }
3119 }
3120
Ido Schimmel80bedf12016-06-20 23:03:59 +02003121 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003122}
3123
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003124static struct mlxsw_sp_fid *
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003125mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3126 const struct net_device *br_dev)
3127{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003128 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003129
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003130 list_for_each_entry(f, &mlxsw_sp->br_vfids.list, list) {
3131 if (f->dev == br_dev)
3132 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003133 }
3134
3135 return NULL;
3136}
3137
3138static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3139{
3140 return vfid - MLXSW_SP_VFID_PORT_MAX;
3141}
3142
3143static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3144{
3145 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3146}
3147
3148static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3149{
3150 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3151 MLXSW_SP_VFID_BR_MAX);
3152}
3153
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003154static struct mlxsw_sp_fid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3155 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003156{
3157 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003158 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003159 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003160 int err;
3161
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003162 vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3163 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003164 dev_err(dev, "No available vFIDs\n");
3165 return ERR_PTR(-ERANGE);
3166 }
3167
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003168 fid = mlxsw_sp_vfid_to_fid(vfid);
3169 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003170 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003171 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003172 return ERR_PTR(err);
3173 }
3174
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003175 f = kzalloc(sizeof(*f), GFP_KERNEL);
3176 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003177 goto err_allocate_vfid;
3178
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003179 f->fid = fid;
3180 f->dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003181
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003182 list_add(&f->list, &mlxsw_sp->br_vfids.list);
3183 set_bit(mlxsw_sp_vfid_to_br_vfid(vfid), mlxsw_sp->br_vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003184
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003185 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003186
3187err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003188 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003189 return ERR_PTR(-ENOMEM);
3190}
3191
3192static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003193 struct mlxsw_sp_fid *f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003194{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003195 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
3196 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003197
3198 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003199 list_del(&f->list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003200
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003201 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003202
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003203 kfree(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003204}
3205
Ido Schimmel82e6db02016-06-20 23:04:04 +02003206static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
3207 struct net_device *br_dev,
3208 bool flush_fdb)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003209{
3210 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3211 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3212 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003213 struct mlxsw_sp_fid *f, *new_f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003214 int err;
3215
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003216 f = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3217 if (WARN_ON(!f))
Ido Schimmel82e6db02016-06-20 23:04:04 +02003218 return;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003219
3220 /* We need a vFID to go back to after leaving the bridge's vFID. */
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003221 new_f = mlxsw_sp_vfid_find(mlxsw_sp, vid);
3222 if (!new_f) {
3223 new_f = mlxsw_sp_vfid_create(mlxsw_sp, vid);
3224 if (IS_ERR(new_f)) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003225 netdev_err(dev, "Failed to create vFID for VID=%d\n",
3226 vid);
Ido Schimmel82e6db02016-06-20 23:04:04 +02003227 return;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003228 }
3229 }
3230
3231 /* Invalidate existing {Port, VID} to vFID mapping and create a new
3232 * one for the new vFID.
3233 */
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003234 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003235 if (err) {
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003236 netdev_err(dev, "Failed to invalidate {Port, VID} to FID=%d mapping\n",
3237 f->fid);
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003238 goto err_vport_fid_unmap;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003239 }
3240
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003241 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, new_f->fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003242 if (err) {
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003243 netdev_err(dev, "Failed to map {Port, VID} to FID=%d\n",
3244 new_f->fid);
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003245 goto err_vport_fid_map;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003246 }
3247
3248 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3249 if (err) {
3250 netdev_err(dev, "Failed to disable learning\n");
3251 goto err_port_vid_learning_set;
3252 }
3253
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003254 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003255 if (err) {
3256 netdev_err(dev, "Failed clear to clear flooding\n");
3257 goto err_vport_flood_set;
3258 }
3259
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003260 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3261 MLXSW_REG_SPMS_STATE_FORWARDING);
3262 if (err) {
3263 netdev_err(dev, "Failed to set STP state\n");
3264 goto err_port_stp_state_set;
3265 }
3266
Ido Schimmel039c49a2016-01-27 15:20:18 +01003267 if (flush_fdb && mlxsw_sp_vport_fdb_flush(mlxsw_sp_vport))
3268 netdev_err(dev, "Failed to flush FDB\n");
3269
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003270 /* Switch between the vFIDs and destroy the old one if needed. */
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003271 new_f->ref_count++;
3272 mlxsw_sp_vport->vport.f = new_f;
3273 f->ref_count--;
3274 if (!f->ref_count)
3275 mlxsw_sp_br_vfid_destroy(mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003276
3277 mlxsw_sp_vport->learning = 0;
3278 mlxsw_sp_vport->learning_sync = 0;
3279 mlxsw_sp_vport->uc_flood = 0;
3280 mlxsw_sp_vport->bridged = 0;
3281
Ido Schimmel82e6db02016-06-20 23:04:04 +02003282 return;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003283
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003284err_port_stp_state_set:
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003285err_vport_flood_set:
3286err_port_vid_learning_set:
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003287err_vport_fid_map:
3288err_vport_fid_unmap:
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003289 /* Rollback vFID only if new. */
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003290 if (!new_f->ref_count)
3291 mlxsw_sp_vfid_destroy(mlxsw_sp, new_f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003292}
3293
3294static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3295 struct net_device *br_dev)
3296{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003297 struct mlxsw_sp_fid *old_f = mlxsw_sp_vport->vport.f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003298 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3299 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3300 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003301 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003302 int err;
3303
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003304 f = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3305 if (!f) {
3306 f = mlxsw_sp_br_vfid_create(mlxsw_sp, br_dev);
3307 if (IS_ERR(f)) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003308 netdev_err(dev, "Failed to create bridge vFID\n");
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003309 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003310 }
3311 }
3312
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003313 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003314 if (err) {
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003315 netdev_err(dev, "Failed to setup flooding for FID=%d\n",
3316 f->fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003317 goto err_port_flood_set;
3318 }
3319
3320 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3321 if (err) {
3322 netdev_err(dev, "Failed to enable learning\n");
3323 goto err_port_vid_learning_set;
3324 }
3325
3326 /* We need to invalidate existing {Port, VID} to vFID mapping and
3327 * create a new one for the bridge's vFID.
3328 */
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003329 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, old_f->fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003330 if (err) {
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003331 netdev_err(dev, "Failed to invalidate {Port, VID} to FID=%d mapping\n",
3332 old_f->fid);
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003333 goto err_vport_fid_unmap;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003334 }
3335
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003336 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003337 if (err) {
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003338 netdev_err(dev, "Failed to map {Port, VID} to FID=%d\n",
3339 f->fid);
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003340 goto err_vport_fid_map;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003341 }
3342
3343 /* Switch between the vFIDs and destroy the old one if needed. */
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003344 f->ref_count++;
3345 mlxsw_sp_vport->vport.f = f;
3346 old_f->ref_count--;
3347 if (!old_f->ref_count)
3348 mlxsw_sp_vfid_destroy(mlxsw_sp, old_f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003349
3350 mlxsw_sp_vport->learning = 1;
3351 mlxsw_sp_vport->learning_sync = 1;
3352 mlxsw_sp_vport->uc_flood = 1;
3353 mlxsw_sp_vport->bridged = 1;
3354
3355 return 0;
3356
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003357err_vport_fid_map:
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003358 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, old_f->fid, true);
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003359err_vport_fid_unmap:
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003360 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3361err_port_vid_learning_set:
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003362 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003363err_port_flood_set:
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003364 if (!f->ref_count)
3365 mlxsw_sp_br_vfid_destroy(mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003366 return err;
3367}
3368
3369static bool
3370mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3371 const struct net_device *br_dev)
3372{
3373 struct mlxsw_sp_port *mlxsw_sp_vport;
3374
3375 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3376 vport.list) {
3377 if (mlxsw_sp_vport_br_get(mlxsw_sp_vport) == br_dev)
3378 return false;
3379 }
3380
3381 return true;
3382}
3383
3384static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3385 unsigned long event, void *ptr,
3386 u16 vid)
3387{
3388 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3389 struct netdev_notifier_changeupper_info *info = ptr;
3390 struct mlxsw_sp_port *mlxsw_sp_vport;
3391 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003392 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003393
3394 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3395
3396 switch (event) {
3397 case NETDEV_PRECHANGEUPPER:
3398 upper_dev = info->upper_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003399 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003400 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02003401 if (!info->linking)
3402 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003403 /* We can't have multiple VLAN interfaces configured on
3404 * the same port and being members in the same bridge.
3405 */
3406 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3407 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003408 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003409 break;
3410 case NETDEV_CHANGEUPPER:
3411 upper_dev = info->upper_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003412 if (info->linking) {
Ido Schimmel423b9372016-06-20 23:04:03 +02003413 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003414 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003415 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3416 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003417 } else {
3418 /* We ignore bridge's unlinking notifications if vPort
3419 * is gone, since we already left the bridge when the
3420 * VLAN device was unlinked from the real device.
3421 */
3422 if (!mlxsw_sp_vport)
Ido Schimmel80bedf12016-06-20 23:03:59 +02003423 return 0;
Ido Schimmel82e6db02016-06-20 23:04:04 +02003424 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, upper_dev,
3425 true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003426 }
3427 }
3428
Ido Schimmel80bedf12016-06-20 23:03:59 +02003429 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003430}
3431
Ido Schimmel272c4472015-12-15 16:03:47 +01003432static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3433 unsigned long event, void *ptr,
3434 u16 vid)
3435{
3436 struct net_device *dev;
3437 struct list_head *iter;
3438 int ret;
3439
3440 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3441 if (mlxsw_sp_port_dev_check(dev)) {
3442 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3443 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003444 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01003445 return ret;
3446 }
3447 }
3448
Ido Schimmel80bedf12016-06-20 23:03:59 +02003449 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01003450}
3451
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003452static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3453 unsigned long event, void *ptr)
3454{
3455 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3456 u16 vid = vlan_dev_vlan_id(vlan_dev);
3457
Ido Schimmel272c4472015-12-15 16:03:47 +01003458 if (mlxsw_sp_port_dev_check(real_dev))
3459 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3460 vid);
3461 else if (netif_is_lag_master(real_dev))
3462 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3463 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003464
Ido Schimmel80bedf12016-06-20 23:03:59 +02003465 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003466}
3467
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003468static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3469 unsigned long event, void *ptr)
3470{
3471 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003472 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003473
3474 if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003475 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3476 else if (netif_is_lag_master(dev))
3477 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3478 else if (is_vlan_dev(dev))
3479 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003480
Ido Schimmel80bedf12016-06-20 23:03:59 +02003481 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003482}
3483
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003484static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3485 .notifier_call = mlxsw_sp_netdevice_event,
3486};
3487
3488static int __init mlxsw_sp_module_init(void)
3489{
3490 int err;
3491
3492 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3493 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3494 if (err)
3495 goto err_core_driver_register;
3496 return 0;
3497
3498err_core_driver_register:
3499 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3500 return err;
3501}
3502
3503static void __exit mlxsw_sp_module_exit(void)
3504{
3505 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3506 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3507}
3508
3509module_init(mlxsw_sp_module_init);
3510module_exit(mlxsw_sp_module_exit);
3511
3512MODULE_LICENSE("Dual BSD/GPL");
3513MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3514MODULE_DESCRIPTION("Mellanox Spectrum driver");
3515MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);