blob: e6e76237f46b114288e406569ce869b41669eab0 [file] [log] [blame]
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
Shreyas NC6277e832016-08-12 12:29:51 +053024#include <uapi/sound/snd_sst_tokens.h>
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010025#include "skl-sst-dsp.h"
26#include "skl-sst-ipc.h"
27#include "skl-topology.h"
28#include "skl.h"
29#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053030#include "../common/sst-dsp.h"
31#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010032
Jeeja KPf7590d42015-10-07 11:31:53 +010033#define SKL_CH_FIXUP_MASK (1 << 0)
34#define SKL_RATE_FIXUP_MASK (1 << 1)
35#define SKL_FMT_FIXUP_MASK (1 << 2)
Shreyas NC6277e832016-08-12 12:29:51 +053036#define SKL_IN_DIR_BIT_MASK BIT(0)
37#define SKL_PIN_COUNT_MASK GENMASK(7, 4)
Jeeja KPf7590d42015-10-07 11:31:53 +010038
Vinod Koula83e3b42016-11-03 17:07:20 +053039void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps)
40{
41 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
42
43 switch (caps) {
44 case SKL_D0I3_NONE:
45 d0i3->non_d0i3++;
46 break;
47
48 case SKL_D0I3_STREAMING:
49 d0i3->streaming++;
50 break;
51
52 case SKL_D0I3_NON_STREAMING:
53 d0i3->non_streaming++;
54 break;
55 }
56}
57
58void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps)
59{
60 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
61
62 switch (caps) {
63 case SKL_D0I3_NONE:
64 d0i3->non_d0i3--;
65 break;
66
67 case SKL_D0I3_STREAMING:
68 d0i3->streaming--;
69 break;
70
71 case SKL_D0I3_NON_STREAMING:
72 d0i3->non_streaming--;
73 break;
74 }
75}
76
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010077/*
78 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
79 * ignore. This helpers checks if the SKL driver handles this widget type
80 */
81static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
82{
83 switch (w->id) {
84 case snd_soc_dapm_dai_link:
85 case snd_soc_dapm_dai_in:
86 case snd_soc_dapm_aif_in:
87 case snd_soc_dapm_aif_out:
88 case snd_soc_dapm_dai_out:
89 case snd_soc_dapm_switch:
90 return false;
91 default:
92 return true;
93 }
94}
95
96/*
97 * Each pipelines needs memory to be allocated. Check if we have free memory
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053098 * from available pool.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010099 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530100static bool skl_is_pipe_mem_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100101 struct skl_module_cfg *mconfig)
102{
103 struct skl_sst *ctx = skl->skl_sst;
104
105 if (skl->resource.mem + mconfig->pipe->memory_pages >
106 skl->resource.max_mem) {
107 dev_err(ctx->dev,
108 "%s: module_id %d instance %d\n", __func__,
109 mconfig->id.module_id,
110 mconfig->id.instance_id);
111 dev_err(ctx->dev,
112 "exceeds ppl memory available %d mem %d\n",
113 skl->resource.max_mem, skl->resource.mem);
114 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530115 } else {
116 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100117 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530118}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100119
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530120/*
121 * Add the mem to the mem pool. This is freed when pipe is deleted.
122 * Note: DSP does actual memory management we only keep track for complete
123 * pool
124 */
125static void skl_tplg_alloc_pipe_mem(struct skl *skl,
126 struct skl_module_cfg *mconfig)
127{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100128 skl->resource.mem += mconfig->pipe->memory_pages;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100129}
130
131/*
132 * Pipeline needs needs DSP CPU resources for computation, this is
133 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
134 *
135 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530136 * pipe.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100137 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530138
139static bool skl_is_pipe_mcps_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100140 struct skl_module_cfg *mconfig)
141{
142 struct skl_sst *ctx = skl->skl_sst;
143
144 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
145 dev_err(ctx->dev,
146 "%s: module_id %d instance %d\n", __func__,
147 mconfig->id.module_id, mconfig->id.instance_id);
148 dev_err(ctx->dev,
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530149 "exceeds ppl mcps available %d > mem %d\n",
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100150 skl->resource.max_mcps, skl->resource.mcps);
151 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530152 } else {
153 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100154 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530155}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100156
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530157static void skl_tplg_alloc_pipe_mcps(struct skl *skl,
158 struct skl_module_cfg *mconfig)
159{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100160 skl->resource.mcps += mconfig->mcps;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100161}
162
163/*
164 * Free the mcps when tearing down
165 */
166static void
167skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
168{
169 skl->resource.mcps -= mconfig->mcps;
170}
171
172/*
173 * Free the memory when tearing down
174 */
175static void
176skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
177{
178 skl->resource.mem -= mconfig->pipe->memory_pages;
179}
180
Jeeja KPf7590d42015-10-07 11:31:53 +0100181
182static void skl_dump_mconfig(struct skl_sst *ctx,
183 struct skl_module_cfg *mcfg)
184{
185 dev_dbg(ctx->dev, "Dumping config\n");
186 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900187 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
188 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
189 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
190 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100191 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900192 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
193 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
194 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
195 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100196}
197
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530198static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs)
199{
200 int slot_map = 0xFFFFFFFF;
201 int start_slot = 0;
202 int i;
203
204 for (i = 0; i < chs; i++) {
205 /*
206 * For 2 channels with starting slot as 0, slot map will
207 * look like 0xFFFFFF10.
208 */
209 slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i)));
210 start_slot++;
211 }
212 fmt->ch_map = slot_map;
213}
214
Jeeja KPf7590d42015-10-07 11:31:53 +0100215static void skl_tplg_update_params(struct skl_module_fmt *fmt,
216 struct skl_pipe_params *params, int fixup)
217{
218 if (fixup & SKL_RATE_FIXUP_MASK)
219 fmt->s_freq = params->s_freq;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530220 if (fixup & SKL_CH_FIXUP_MASK) {
Jeeja KPf7590d42015-10-07 11:31:53 +0100221 fmt->channels = params->ch;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530222 skl_tplg_update_chmap(fmt, fmt->channels);
223 }
Jeeja KP98256f82015-11-23 22:26:25 +0530224 if (fixup & SKL_FMT_FIXUP_MASK) {
225 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
226
227 /*
228 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
229 * container so update bit depth accordingly
230 */
231 switch (fmt->valid_bit_depth) {
232 case SKL_DEPTH_16BIT:
233 fmt->bit_depth = fmt->valid_bit_depth;
234 break;
235
236 default:
237 fmt->bit_depth = SKL_DEPTH_32BIT;
238 break;
239 }
240 }
241
Jeeja KPf7590d42015-10-07 11:31:53 +0100242}
243
244/*
245 * A pipeline may have modules which impact the pcm parameters, like SRC,
246 * channel converter, format converter.
247 * We need to calculate the output params by applying the 'fixup'
248 * Topology will tell driver which type of fixup is to be applied by
249 * supplying the fixup mask, so based on that we calculate the output
250 *
251 * Now In FE the pcm hw_params is source/target format. Same is applicable
252 * for BE with its hw_params invoked.
253 * here based on FE, BE pipeline and direction we calculate the input and
254 * outfix and then apply that for a module
255 */
256static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
257 struct skl_pipe_params *params, bool is_fe)
258{
259 int in_fixup, out_fixup;
260 struct skl_module_fmt *in_fmt, *out_fmt;
261
Hardik T Shah4cd98992015-10-27 09:22:55 +0900262 /* Fixups will be applied to pin 0 only */
263 in_fmt = &m_cfg->in_fmt[0];
264 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100265
266 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
267 if (is_fe) {
268 in_fixup = m_cfg->params_fixup;
269 out_fixup = (~m_cfg->converter) &
270 m_cfg->params_fixup;
271 } else {
272 out_fixup = m_cfg->params_fixup;
273 in_fixup = (~m_cfg->converter) &
274 m_cfg->params_fixup;
275 }
276 } else {
277 if (is_fe) {
278 out_fixup = m_cfg->params_fixup;
279 in_fixup = (~m_cfg->converter) &
280 m_cfg->params_fixup;
281 } else {
282 in_fixup = m_cfg->params_fixup;
283 out_fixup = (~m_cfg->converter) &
284 m_cfg->params_fixup;
285 }
286 }
287
288 skl_tplg_update_params(in_fmt, params, in_fixup);
289 skl_tplg_update_params(out_fmt, params, out_fixup);
290}
291
292/*
293 * A module needs input and output buffers, which are dependent upon pcm
294 * params, so once we have calculate params, we need buffer calculation as
295 * well.
296 */
297static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
298 struct skl_module_cfg *mcfg)
299{
300 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900301 struct skl_module_fmt *in_fmt, *out_fmt;
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530302 int in_rate, out_rate;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900303
304
305 /* Since fixups is applied to pin 0 only, ibs, obs needs
306 * change for pin 0 only
307 */
308 in_fmt = &mcfg->in_fmt[0];
309 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100310
311 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
312 multiplier = 5;
Jeeja KPf7590d42015-10-07 11:31:53 +0100313
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530314 if (in_fmt->s_freq % 1000)
315 in_rate = (in_fmt->s_freq / 1000) + 1;
316 else
317 in_rate = (in_fmt->s_freq / 1000);
318
319 mcfg->ibs = in_rate * (mcfg->in_fmt->channels) *
320 (mcfg->in_fmt->bit_depth >> 3) *
321 multiplier;
322
323 if (mcfg->out_fmt->s_freq % 1000)
324 out_rate = (mcfg->out_fmt->s_freq / 1000) + 1;
325 else
326 out_rate = (mcfg->out_fmt->s_freq / 1000);
327
328 mcfg->obs = out_rate * (mcfg->out_fmt->channels) *
329 (mcfg->out_fmt->bit_depth >> 3) *
330 multiplier;
Jeeja KPf7590d42015-10-07 11:31:53 +0100331}
332
Jeeja KP2d1419a2016-02-05 12:19:10 +0530333static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
334 struct skl_sst *ctx)
335{
336 struct skl_module_cfg *m_cfg = w->priv;
337 int link_type, dir;
338 u32 ch, s_freq, s_fmt;
339 struct nhlt_specific_cfg *cfg;
340 struct skl *skl = get_skl_ctx(ctx->dev);
341
342 /* check if we already have blob */
343 if (m_cfg->formats_config.caps_size > 0)
344 return 0;
345
Jeeja KPc7c6c732016-03-01 07:59:10 +0530346 dev_dbg(ctx->dev, "Applying default cfg blob\n");
Jeeja KP2d1419a2016-02-05 12:19:10 +0530347 switch (m_cfg->dev_type) {
348 case SKL_DEVICE_DMIC:
349 link_type = NHLT_LINK_DMIC;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530350 dir = SNDRV_PCM_STREAM_CAPTURE;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530351 s_freq = m_cfg->in_fmt[0].s_freq;
352 s_fmt = m_cfg->in_fmt[0].bit_depth;
353 ch = m_cfg->in_fmt[0].channels;
354 break;
355
356 case SKL_DEVICE_I2S:
357 link_type = NHLT_LINK_SSP;
358 if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) {
Jeeja KPc7c6c732016-03-01 07:59:10 +0530359 dir = SNDRV_PCM_STREAM_PLAYBACK;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530360 s_freq = m_cfg->out_fmt[0].s_freq;
361 s_fmt = m_cfg->out_fmt[0].bit_depth;
362 ch = m_cfg->out_fmt[0].channels;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530363 } else {
364 dir = SNDRV_PCM_STREAM_CAPTURE;
365 s_freq = m_cfg->in_fmt[0].s_freq;
366 s_fmt = m_cfg->in_fmt[0].bit_depth;
367 ch = m_cfg->in_fmt[0].channels;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530368 }
369 break;
370
371 default:
372 return -EINVAL;
373 }
374
375 /* update the blob based on virtual bus_id and default params */
376 cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
377 s_fmt, ch, s_freq, dir);
378 if (cfg) {
379 m_cfg->formats_config.caps_size = cfg->size;
380 m_cfg->formats_config.caps = (u32 *) &cfg->caps;
381 } else {
382 dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n",
383 m_cfg->vbus_id, link_type, dir);
384 dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n",
385 ch, s_freq, s_fmt);
386 return -EIO;
387 }
388
389 return 0;
390}
391
Jeeja KPf7590d42015-10-07 11:31:53 +0100392static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
393 struct skl_sst *ctx)
394{
395 struct skl_module_cfg *m_cfg = w->priv;
396 struct skl_pipe_params *params = m_cfg->pipe->p_params;
397 int p_conn_type = m_cfg->pipe->conn_type;
398 bool is_fe;
399
400 if (!m_cfg->params_fixup)
401 return;
402
403 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
404 w->name);
405
406 skl_dump_mconfig(ctx, m_cfg);
407
408 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
409 is_fe = true;
410 else
411 is_fe = false;
412
413 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
414 skl_tplg_update_buffer_size(ctx, m_cfg);
415
416 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
417 w->name);
418
419 skl_dump_mconfig(ctx, m_cfg);
420}
421
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100422/*
Jeeja KPabb74002015-11-28 15:01:49 +0530423 * some modules can have multiple params set from user control and
424 * need to be set after module is initialized. If set_param flag is
425 * set module params will be done after module is initialised.
426 */
427static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
428 struct skl_sst *ctx)
429{
430 int i, ret;
431 struct skl_module_cfg *mconfig = w->priv;
432 const struct snd_kcontrol_new *k;
433 struct soc_bytes_ext *sb;
434 struct skl_algo_data *bc;
435 struct skl_specific_cfg *sp_cfg;
436
437 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530438 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530439 sp_cfg = &mconfig->formats_config;
440 ret = skl_set_module_params(ctx, sp_cfg->caps,
441 sp_cfg->caps_size,
442 sp_cfg->param_id, mconfig);
443 if (ret < 0)
444 return ret;
445 }
446
447 for (i = 0; i < w->num_kcontrols; i++) {
448 k = &w->kcontrol_news[i];
449 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
450 sb = (void *) k->private_value;
451 bc = (struct skl_algo_data *)sb->dobj.private;
452
Jeeja KP4ced1822015-12-03 23:29:53 +0530453 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530454 ret = skl_set_module_params(ctx,
Dharageswari R0d682102016-07-08 18:15:03 +0530455 (u32 *)bc->params, bc->size,
Jeeja KPabb74002015-11-28 15:01:49 +0530456 bc->param_id, mconfig);
457 if (ret < 0)
458 return ret;
459 }
460 }
461 }
462
463 return 0;
464}
465
466/*
467 * some module param can set from user control and this is required as
468 * when module is initailzed. if module param is required in init it is
469 * identifed by set_param flag. if set_param flag is not set, then this
470 * parameter needs to set as part of module init.
471 */
472static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
473{
474 const struct snd_kcontrol_new *k;
475 struct soc_bytes_ext *sb;
476 struct skl_algo_data *bc;
477 struct skl_module_cfg *mconfig = w->priv;
478 int i;
479
480 for (i = 0; i < w->num_kcontrols; i++) {
481 k = &w->kcontrol_news[i];
482 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
483 sb = (struct soc_bytes_ext *)k->private_value;
484 bc = (struct skl_algo_data *)sb->dobj.private;
485
Jeeja KP4ced1822015-12-03 23:29:53 +0530486 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530487 continue;
488
489 mconfig->formats_config.caps = (u32 *)&bc->params;
Dharageswari R0d682102016-07-08 18:15:03 +0530490 mconfig->formats_config.caps_size = bc->size;
Jeeja KPabb74002015-11-28 15:01:49 +0530491
492 break;
493 }
494 }
495
496 return 0;
497}
498
Jeeja KPbb704a732016-12-08 13:41:14 +0530499static int skl_tplg_module_prepare(struct skl_sst *ctx, struct skl_pipe *pipe,
500 struct snd_soc_dapm_widget *w, struct skl_module_cfg *mcfg)
501{
502 switch (mcfg->dev_type) {
503 case SKL_DEVICE_HDAHOST:
504 return skl_pcm_host_dma_prepare(ctx->dev, pipe->p_params);
505
506 case SKL_DEVICE_HDALINK:
507 return skl_pcm_link_dma_prepare(ctx->dev, pipe->p_params);
508 }
509
510 return 0;
511}
512
Jeeja KPabb74002015-11-28 15:01:49 +0530513/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100514 * Inside a pipe instance, we can have various modules. These modules need
515 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
516 * skl_init_module() routine, so invoke that for all modules in a pipeline
517 */
518static int
519skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
520{
521 struct skl_pipe_module *w_module;
522 struct snd_soc_dapm_widget *w;
523 struct skl_module_cfg *mconfig;
524 struct skl_sst *ctx = skl->skl_sst;
525 int ret = 0;
526
527 list_for_each_entry(w_module, &pipe->w_list, node) {
528 w = w_module->w;
529 mconfig = w->priv;
530
Vinod Koulb7c50552016-07-26 18:06:40 +0530531 /* check if module ids are populated */
532 if (mconfig->id.module_id < 0) {
Vinod Koula657ae72016-08-10 09:40:50 +0530533 dev_err(skl->skl_sst->dev,
534 "module %pUL id not populated\n",
535 (uuid_le *)mconfig->guid);
536 return -EIO;
Vinod Koulb7c50552016-07-26 18:06:40 +0530537 }
538
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100539 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530540 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100541 return -ENOMEM;
542
Dharageswari R6c5768b2015-12-03 23:29:50 +0530543 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
544 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
545 mconfig->id.module_id, mconfig->guid);
546 if (ret < 0)
547 return ret;
Jeeja KPd6436782016-03-28 22:11:30 +0530548
549 mconfig->m_state = SKL_MODULE_LOADED;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530550 }
551
Jeeja KPbb704a732016-12-08 13:41:14 +0530552 /* prepare the DMA if the module is gateway cpr */
553 ret = skl_tplg_module_prepare(ctx, pipe, w, mconfig);
554 if (ret < 0)
555 return ret;
556
Jeeja KP2d1419a2016-02-05 12:19:10 +0530557 /* update blob if blob is null for be with default value */
558 skl_tplg_update_be_blob(w, ctx);
559
Jeeja KPf7590d42015-10-07 11:31:53 +0100560 /*
561 * apply fix/conversion to module params based on
562 * FE/BE params
563 */
564 skl_tplg_update_module_params(w, ctx);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530565 mconfig->id.pvt_id = skl_get_pvt_id(ctx, mconfig);
566 if (mconfig->id.pvt_id < 0)
567 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530568 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530569 ret = skl_init_module(ctx, mconfig);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530570 if (ret < 0) {
571 skl_put_pvt_id(ctx, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100572 return ret;
Dharageswari Ref2a3522016-09-22 14:00:38 +0530573 }
Dharageswari R260eb732016-06-03 18:29:38 +0530574 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Jeeja KPabb74002015-11-28 15:01:49 +0530575 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100576 if (ret < 0)
577 return ret;
578 }
579
580 return 0;
581}
Vinod Kould93f8e52015-10-07 11:31:54 +0100582
Dharageswari R6c5768b2015-12-03 23:29:50 +0530583static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
584 struct skl_pipe *pipe)
585{
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530586 int ret;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530587 struct skl_pipe_module *w_module = NULL;
588 struct skl_module_cfg *mconfig = NULL;
589
590 list_for_each_entry(w_module, &pipe->w_list, node) {
591 mconfig = w_module->w->priv;
592
Jeeja KPd6436782016-03-28 22:11:30 +0530593 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod &&
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530594 mconfig->m_state > SKL_MODULE_UNINIT) {
595 ret = ctx->dsp->fw_ops.unload_mod(ctx->dsp,
Dharageswari R6c5768b2015-12-03 23:29:50 +0530596 mconfig->id.module_id);
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530597 if (ret < 0)
598 return -EIO;
599 }
Dharageswari Ref2a3522016-09-22 14:00:38 +0530600 skl_put_pvt_id(ctx, mconfig);
Dharageswari R6c5768b2015-12-03 23:29:50 +0530601 }
602
603 /* no modules to unload in this path, so return */
604 return 0;
605}
606
Vinod Kould93f8e52015-10-07 11:31:54 +0100607/*
608 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
609 * need create the pipeline. So we do following:
610 * - check the resources
611 * - Create the pipeline
612 * - Initialize the modules in pipeline
613 * - finally bind all modules together
614 */
615static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
616 struct skl *skl)
617{
618 int ret;
619 struct skl_module_cfg *mconfig = w->priv;
620 struct skl_pipe_module *w_module;
621 struct skl_pipe *s_pipe = mconfig->pipe;
622 struct skl_module_cfg *src_module = NULL, *dst_module;
623 struct skl_sst *ctx = skl->skl_sst;
624
625 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530626 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100627 return -EBUSY;
628
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530629 if (!skl_is_pipe_mem_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100630 return -ENOMEM;
631
632 /*
633 * Create a list of modules for pipe.
634 * This list contains modules from source to sink
635 */
636 ret = skl_create_pipeline(ctx, mconfig->pipe);
637 if (ret < 0)
638 return ret;
639
Dharageswari R260eb732016-06-03 18:29:38 +0530640 skl_tplg_alloc_pipe_mem(skl, mconfig);
641 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100642
643 /* Init all pipe modules from source to sink */
644 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
645 if (ret < 0)
646 return ret;
647
648 /* Bind modules from source to sink */
649 list_for_each_entry(w_module, &s_pipe->w_list, node) {
650 dst_module = w_module->w->priv;
651
652 if (src_module == NULL) {
653 src_module = dst_module;
654 continue;
655 }
656
657 ret = skl_bind_modules(ctx, src_module, dst_module);
658 if (ret < 0)
659 return ret;
660
661 src_module = dst_module;
662 }
663
664 return 0;
665}
666
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530667static int skl_fill_sink_instance_id(struct skl_sst *ctx,
668 struct skl_algo_data *alg_data)
669{
670 struct skl_kpb_params *params = (struct skl_kpb_params *)alg_data->params;
671 struct skl_mod_inst_map *inst;
672 int i, pvt_id;
673
674 inst = params->map;
675
676 for (i = 0; i < params->num_modules; i++) {
677 pvt_id = skl_get_pvt_instance_id_map(ctx,
678 inst->mod_id, inst->inst_id);
679 if (pvt_id < 0)
680 return -EINVAL;
681 inst->inst_id = pvt_id;
682 inst++;
683 }
684 return 0;
685}
686
Jeeja KPcc6a4042016-02-05 12:19:08 +0530687/*
688 * Some modules require params to be set after the module is bound to
689 * all pins connected.
690 *
691 * The module provider initializes set_param flag for such modules and we
692 * send params after binding
693 */
694static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w,
695 struct skl_module_cfg *mcfg, struct skl_sst *ctx)
696{
697 int i, ret;
698 struct skl_module_cfg *mconfig = w->priv;
699 const struct snd_kcontrol_new *k;
700 struct soc_bytes_ext *sb;
701 struct skl_algo_data *bc;
702 struct skl_specific_cfg *sp_cfg;
703
704 /*
705 * check all out/in pins are in bind state.
706 * if so set the module param
707 */
708 for (i = 0; i < mcfg->max_out_queue; i++) {
709 if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE)
710 return 0;
711 }
712
713 for (i = 0; i < mcfg->max_in_queue; i++) {
714 if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE)
715 return 0;
716 }
717
718 if (mconfig->formats_config.caps_size > 0 &&
719 mconfig->formats_config.set_params == SKL_PARAM_BIND) {
720 sp_cfg = &mconfig->formats_config;
721 ret = skl_set_module_params(ctx, sp_cfg->caps,
722 sp_cfg->caps_size,
723 sp_cfg->param_id, mconfig);
724 if (ret < 0)
725 return ret;
726 }
727
728 for (i = 0; i < w->num_kcontrols; i++) {
729 k = &w->kcontrol_news[i];
730 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
731 sb = (void *) k->private_value;
732 bc = (struct skl_algo_data *)sb->dobj.private;
733
734 if (bc->set_params == SKL_PARAM_BIND) {
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530735 if (mconfig->m_type == SKL_MODULE_TYPE_KPB)
736 skl_fill_sink_instance_id(ctx, bc);
Jeeja KPcc6a4042016-02-05 12:19:08 +0530737 ret = skl_set_module_params(ctx,
738 (u32 *)bc->params, bc->max,
739 bc->param_id, mconfig);
740 if (ret < 0)
741 return ret;
742 }
743 }
744 }
745
746 return 0;
747}
748
Jeeja KP8724ff12015-10-27 09:22:52 +0900749static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
750 struct skl *skl,
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530751 struct snd_soc_dapm_widget *src_w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900752 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100753{
754 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530755 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900756 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100757 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900758 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100759
Jeeja KP8724ff12015-10-27 09:22:52 +0900760 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100761 if (!p->connect)
762 continue;
763
764 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
765 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
766
Jeeja KP0ed95d72015-11-13 19:22:11 +0530767 next_sink = p->sink;
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530768
769 if (!is_skl_dsp_widget_type(p->sink))
770 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
771
Vinod Kould93f8e52015-10-07 11:31:54 +0100772 /*
773 * here we will check widgets in sink pipelines, so that
774 * can be any widgets type and we are only interested if
775 * they are ones used for SKL so check that first
776 */
777 if ((p->sink->priv != NULL) &&
778 is_skl_dsp_widget_type(p->sink)) {
779
780 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100781 sink_mconfig = sink->priv;
782
Jeeja KPcc6a4042016-02-05 12:19:08 +0530783 if (src_mconfig->m_state == SKL_MODULE_UNINIT ||
784 sink_mconfig->m_state == SKL_MODULE_UNINIT)
785 continue;
786
Vinod Kould93f8e52015-10-07 11:31:54 +0100787 /* Bind source to sink, mixin is always source */
788 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
789 if (ret)
790 return ret;
791
Jeeja KPcc6a4042016-02-05 12:19:08 +0530792 /* set module params after bind */
793 skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx);
794 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
795
Vinod Kould93f8e52015-10-07 11:31:54 +0100796 /* Start sinks pipe first */
797 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900798 if (sink_mconfig->pipe->conn_type !=
799 SKL_PIPE_CONN_TYPE_FE)
800 ret = skl_run_pipe(ctx,
801 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100802 if (ret)
803 return ret;
804 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100805 }
806 }
807
Jeeja KP8724ff12015-10-27 09:22:52 +0900808 if (!sink)
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530809 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900810
811 return 0;
812}
813
Vinod Kould93f8e52015-10-07 11:31:54 +0100814/*
815 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
816 * we need to do following:
817 * - Bind to sink pipeline
818 * Since the sink pipes can be running and we don't get mixer event on
819 * connect for already running mixer, we need to find the sink pipes
820 * here and bind to them. This way dynamic connect works.
821 * - Start sink pipeline, if not running
822 * - Then run current pipe
823 */
824static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900825 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100826{
Jeeja KP8724ff12015-10-27 09:22:52 +0900827 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100828 struct skl_sst *ctx = skl->skl_sst;
829 int ret = 0;
830
Jeeja KP8724ff12015-10-27 09:22:52 +0900831 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100832
833 /*
834 * find which sink it is connected to, bind with the sink,
835 * if sink is not started, start sink pipe first, then start
836 * this pipe
837 */
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530838 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100839 if (ret)
840 return ret;
841
Vinod Kould93f8e52015-10-07 11:31:54 +0100842 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900843 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
844 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100845
846 return 0;
847}
848
Jeeja KP8724ff12015-10-27 09:22:52 +0900849static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
850 struct snd_soc_dapm_widget *w, struct skl *skl)
851{
852 struct snd_soc_dapm_path *p;
853 struct snd_soc_dapm_widget *src_w = NULL;
854 struct skl_sst *ctx = skl->skl_sst;
855
856 snd_soc_dapm_widget_for_each_source_path(w, p) {
857 src_w = p->source;
858 if (!p->connect)
859 continue;
860
861 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
862 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
863
864 /*
865 * here we will check widgets in sink pipelines, so that can
866 * be any widgets type and we are only interested if they are
867 * ones used for SKL so check that first
868 */
869 if ((p->source->priv != NULL) &&
870 is_skl_dsp_widget_type(p->source)) {
871 return p->source;
872 }
873 }
874
875 if (src_w != NULL)
876 return skl_get_src_dsp_widget(src_w, skl);
877
878 return NULL;
879}
880
Vinod Kould93f8e52015-10-07 11:31:54 +0100881/*
882 * in the Post-PMU event of mixer we need to do following:
883 * - Check if this pipe is running
884 * - if not, then
885 * - bind this pipeline to its source pipeline
886 * if source pipe is already running, this means it is a dynamic
887 * connection and we need to bind only to that pipe
888 * - start this pipeline
889 */
890static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
891 struct skl *skl)
892{
893 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100894 struct snd_soc_dapm_widget *source, *sink;
895 struct skl_module_cfg *src_mconfig, *sink_mconfig;
896 struct skl_sst *ctx = skl->skl_sst;
897 int src_pipe_started = 0;
898
899 sink = w;
900 sink_mconfig = sink->priv;
901
902 /*
903 * If source pipe is already started, that means source is driving
904 * one more sink before this sink got connected, Since source is
905 * started, bind this sink to source and start this pipe.
906 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900907 source = skl_get_src_dsp_widget(w, skl);
908 if (source != NULL) {
909 src_mconfig = source->priv;
910 sink_mconfig = sink->priv;
911 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100912
913 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900914 * check pipe state, then no need to bind or start the
915 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100916 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900917 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
918 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100919 }
920
921 if (src_pipe_started) {
922 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
923 if (ret)
924 return ret;
925
Jeeja KPcc6a4042016-02-05 12:19:08 +0530926 /* set module params after bind */
927 skl_tplg_set_module_bind_params(source, src_mconfig, ctx);
928 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
929
Jeeja KPd1730c32015-10-27 09:22:53 +0900930 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
931 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100932 }
933
934 return ret;
935}
936
937/*
938 * in the Pre-PMD event of mixer we need to do following:
939 * - Stop the pipe
940 * - find the source connections and remove that from dapm_path_list
941 * - unbind with source pipelines if still connected
942 */
943static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
944 struct skl *skl)
945{
Vinod Kould93f8e52015-10-07 11:31:54 +0100946 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900947 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100948 struct skl_sst *ctx = skl->skl_sst;
949
Jeeja KPce1b5552015-10-27 09:22:51 +0900950 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100951
952 /* Stop the pipe */
953 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
954 if (ret)
955 return ret;
956
Jeeja KPce1b5552015-10-27 09:22:51 +0900957 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
958 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
959 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
960 if (!src_mconfig)
961 continue;
962 /*
963 * If path_found == 1, that means pmd for source
964 * pipe has not occurred, source is connected to
965 * some other sink. so its responsibility of sink
966 * to unbind itself from source.
967 */
968 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
969 if (ret < 0)
970 return ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100971
Jeeja KPce1b5552015-10-27 09:22:51 +0900972 ret = skl_unbind_modules(ctx,
973 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100974 }
975 }
976
Vinod Kould93f8e52015-10-07 11:31:54 +0100977 return ret;
978}
979
980/*
981 * in the Post-PMD event of mixer we need to do following:
982 * - Free the mcps used
983 * - Free the mem used
984 * - Unbind the modules within the pipeline
985 * - Delete the pipeline (modules are not required to be explicitly
986 * deleted, pipeline delete is enough here
987 */
988static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
989 struct skl *skl)
990{
991 struct skl_module_cfg *mconfig = w->priv;
992 struct skl_pipe_module *w_module;
993 struct skl_module_cfg *src_module = NULL, *dst_module;
994 struct skl_sst *ctx = skl->skl_sst;
995 struct skl_pipe *s_pipe = mconfig->pipe;
Vinod Kould93f8e52015-10-07 11:31:54 +0100996
Dharageswari R260eb732016-06-03 18:29:38 +0530997 if (s_pipe->state == SKL_PIPE_INVALID)
998 return -EINVAL;
999
Vinod Kould93f8e52015-10-07 11:31:54 +01001000 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +05301001 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001002
1003 list_for_each_entry(w_module, &s_pipe->w_list, node) {
1004 dst_module = w_module->w->priv;
1005
Dharageswari R260eb732016-06-03 18:29:38 +05301006 if (mconfig->m_state >= SKL_MODULE_INIT_DONE)
1007 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001008 if (src_module == NULL) {
1009 src_module = dst_module;
1010 continue;
1011 }
1012
Guneshwor Singh7ca42f52016-02-03 17:59:46 +05301013 skl_unbind_modules(ctx, src_module, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001014 src_module = dst_module;
1015 }
1016
Vinod Koul547cafa2016-12-08 23:01:24 +05301017 skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001018
Dharageswari R6c5768b2015-12-03 23:29:50 +05301019 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001020}
1021
1022/*
1023 * in the Post-PMD event of PGA we need to do following:
1024 * - Free the mcps used
1025 * - Stop the pipeline
1026 * - In source pipe is connected, unbind with source pipelines
1027 */
1028static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
1029 struct skl *skl)
1030{
Vinod Kould93f8e52015-10-07 11:31:54 +01001031 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +09001032 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +01001033 struct skl_sst *ctx = skl->skl_sst;
1034
Jeeja KPce1b5552015-10-27 09:22:51 +09001035 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +01001036
Vinod Kould93f8e52015-10-07 11:31:54 +01001037 /* Stop the pipe since this is a mixin module */
1038 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
1039 if (ret)
1040 return ret;
1041
Jeeja KPce1b5552015-10-27 09:22:51 +09001042 for (i = 0; i < src_mconfig->max_out_queue; i++) {
1043 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
1044 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
1045 if (!sink_mconfig)
1046 continue;
1047 /*
1048 * This is a connecter and if path is found that means
1049 * unbind between source and sink has not happened yet
1050 */
Jeeja KPce1b5552015-10-27 09:22:51 +09001051 ret = skl_unbind_modules(ctx, src_mconfig,
1052 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001053 }
1054 }
1055
Vinod Kould93f8e52015-10-07 11:31:54 +01001056 return ret;
1057}
1058
1059/*
1060 * In modelling, we assume there will be ONLY one mixer in a pipeline. If
1061 * mixer is not required then it is treated as static mixer aka vmixer with
1062 * a hard path to source module
1063 * So we don't need to check if source is started or not as hard path puts
1064 * dependency on each other
1065 */
1066static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w,
1067 struct snd_kcontrol *k, int event)
1068{
1069 struct snd_soc_dapm_context *dapm = w->dapm;
1070 struct skl *skl = get_skl_ctx(dapm->dev);
1071
1072 switch (event) {
1073 case SND_SOC_DAPM_PRE_PMU:
1074 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1075
Jeeja KPde1fedf2016-02-03 17:59:52 +05301076 case SND_SOC_DAPM_POST_PMU:
1077 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1078
1079 case SND_SOC_DAPM_PRE_PMD:
1080 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1081
Vinod Kould93f8e52015-10-07 11:31:54 +01001082 case SND_SOC_DAPM_POST_PMD:
1083 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1084 }
1085
1086 return 0;
1087}
1088
1089/*
1090 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
1091 * second one is required that is created as another pipe entity.
1092 * The mixer is responsible for pipe management and represent a pipeline
1093 * instance
1094 */
1095static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
1096 struct snd_kcontrol *k, int event)
1097{
1098 struct snd_soc_dapm_context *dapm = w->dapm;
1099 struct skl *skl = get_skl_ctx(dapm->dev);
1100
1101 switch (event) {
1102 case SND_SOC_DAPM_PRE_PMU:
1103 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1104
1105 case SND_SOC_DAPM_POST_PMU:
1106 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1107
1108 case SND_SOC_DAPM_PRE_PMD:
1109 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1110
1111 case SND_SOC_DAPM_POST_PMD:
1112 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1113 }
1114
1115 return 0;
1116}
1117
1118/*
1119 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
1120 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
1121 * the sink when it is running (two FE to one BE or one FE to two BE)
1122 * scenarios
1123 */
1124static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
1125 struct snd_kcontrol *k, int event)
1126
1127{
1128 struct snd_soc_dapm_context *dapm = w->dapm;
1129 struct skl *skl = get_skl_ctx(dapm->dev);
1130
1131 switch (event) {
1132 case SND_SOC_DAPM_PRE_PMU:
1133 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
1134
1135 case SND_SOC_DAPM_POST_PMD:
1136 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
1137 }
1138
1139 return 0;
1140}
Vinod Koulcfb0a872015-10-07 11:31:55 +01001141
Jeeja KP140adfb2015-11-28 15:01:50 +05301142static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
1143 unsigned int __user *data, unsigned int size)
1144{
1145 struct soc_bytes_ext *sb =
1146 (struct soc_bytes_ext *)kcontrol->private_value;
1147 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +05301148 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1149 struct skl_module_cfg *mconfig = w->priv;
1150 struct skl *skl = get_skl_ctx(w->dapm->dev);
1151
1152 if (w->power)
1153 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
Dharageswari R0d682102016-07-08 18:15:03 +05301154 bc->size, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +05301155
Vinod Koul41556f62016-02-03 17:59:44 +05301156 /* decrement size for TLV header */
1157 size -= 2 * sizeof(u32);
1158
1159 /* check size as we don't want to send kernel data */
1160 if (size > bc->max)
1161 size = bc->max;
1162
Jeeja KP140adfb2015-11-28 15:01:50 +05301163 if (bc->params) {
1164 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
1165 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001166 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +05301167 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001168 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301169 return -EFAULT;
1170 }
1171
1172 return 0;
1173}
1174
1175#define SKL_PARAM_VENDOR_ID 0xff
1176
1177static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
1178 const unsigned int __user *data, unsigned int size)
1179{
1180 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1181 struct skl_module_cfg *mconfig = w->priv;
1182 struct soc_bytes_ext *sb =
1183 (struct soc_bytes_ext *)kcontrol->private_value;
1184 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
1185 struct skl *skl = get_skl_ctx(w->dapm->dev);
1186
1187 if (ac->params) {
Dharageswari R0d682102016-07-08 18:15:03 +05301188 if (size > ac->max)
1189 return -EINVAL;
1190
1191 ac->size = size;
Jeeja KP140adfb2015-11-28 15:01:50 +05301192 /*
1193 * if the param_is is of type Vendor, firmware expects actual
1194 * parameter id and size from the control.
1195 */
1196 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
1197 if (copy_from_user(ac->params, data, size))
1198 return -EFAULT;
1199 } else {
1200 if (copy_from_user(ac->params,
Alan65b4bcb2016-02-19 11:42:32 +05301201 data + 2, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301202 return -EFAULT;
1203 }
1204
1205 if (w->power)
1206 return skl_set_module_params(skl->skl_sst,
Dharageswari R0d682102016-07-08 18:15:03 +05301207 (u32 *)ac->params, ac->size,
Jeeja KP140adfb2015-11-28 15:01:50 +05301208 ac->param_id, mconfig);
1209 }
1210
1211 return 0;
1212}
1213
Vinod Koulcfb0a872015-10-07 11:31:55 +01001214/*
Jeeja KP8871dcb2016-06-03 18:29:42 +05301215 * Fill the dma id for host and link. In case of passthrough
1216 * pipeline, this will both host and link in the same
1217 * pipeline, so need to copy the link and host based on dev_type
1218 */
1219static void skl_tplg_fill_dma_id(struct skl_module_cfg *mcfg,
1220 struct skl_pipe_params *params)
1221{
1222 struct skl_pipe *pipe = mcfg->pipe;
1223
1224 if (pipe->passthru) {
1225 switch (mcfg->dev_type) {
1226 case SKL_DEVICE_HDALINK:
1227 pipe->p_params->link_dma_id = params->link_dma_id;
Jeeja KP12c3be02016-12-08 13:41:12 +05301228 pipe->p_params->link_index = params->link_index;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301229 break;
1230
1231 case SKL_DEVICE_HDAHOST:
1232 pipe->p_params->host_dma_id = params->host_dma_id;
1233 break;
1234
1235 default:
1236 break;
1237 }
1238 pipe->p_params->s_fmt = params->s_fmt;
1239 pipe->p_params->ch = params->ch;
1240 pipe->p_params->s_freq = params->s_freq;
1241 pipe->p_params->stream = params->stream;
Jeeja KP12c3be02016-12-08 13:41:12 +05301242 pipe->p_params->format = params->format;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301243
1244 } else {
1245 memcpy(pipe->p_params, params, sizeof(*params));
1246 }
1247}
1248
1249/*
Vinod Koulcfb0a872015-10-07 11:31:55 +01001250 * The FE params are passed by hw_params of the DAI.
1251 * On hw_params, the params are stored in Gateway module of the FE and we
1252 * need to calculate the format in DSP module configuration, that
1253 * conversion is done here
1254 */
1255int skl_tplg_update_pipe_params(struct device *dev,
1256 struct skl_module_cfg *mconfig,
1257 struct skl_pipe_params *params)
1258{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001259 struct skl_module_fmt *format = NULL;
1260
Jeeja KP8871dcb2016-06-03 18:29:42 +05301261 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001262
1263 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001264 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001265 else
Hardik T Shah4cd98992015-10-27 09:22:55 +09001266 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001267
1268 /* set the hw_params */
1269 format->s_freq = params->s_freq;
1270 format->channels = params->ch;
1271 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
1272
1273 /*
1274 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1275 * container so update bit depth accordingly
1276 */
1277 switch (format->valid_bit_depth) {
1278 case SKL_DEPTH_16BIT:
1279 format->bit_depth = format->valid_bit_depth;
1280 break;
1281
1282 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001283 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001284 format->bit_depth = SKL_DEPTH_32BIT;
1285 break;
1286
1287 default:
1288 dev_err(dev, "Invalid bit depth %x for pipe\n",
1289 format->valid_bit_depth);
1290 return -EINVAL;
1291 }
1292
1293 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1294 mconfig->ibs = (format->s_freq / 1000) *
1295 (format->channels) *
1296 (format->bit_depth >> 3);
1297 } else {
1298 mconfig->obs = (format->s_freq / 1000) *
1299 (format->channels) *
1300 (format->bit_depth >> 3);
1301 }
1302
1303 return 0;
1304}
1305
1306/*
1307 * Query the module config for the FE DAI
1308 * This is used to find the hw_params set for that DAI and apply to FE
1309 * pipeline
1310 */
1311struct skl_module_cfg *
1312skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1313{
1314 struct snd_soc_dapm_widget *w;
1315 struct snd_soc_dapm_path *p = NULL;
1316
1317 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1318 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301319 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001320 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001321 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001322 continue;
1323
1324 if (p->sink->priv) {
1325 dev_dbg(dai->dev, "set params for %s\n",
1326 p->sink->name);
1327 return p->sink->priv;
1328 }
1329 }
1330 } else {
1331 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301332 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001333 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001334 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001335 continue;
1336
1337 if (p->source->priv) {
1338 dev_dbg(dai->dev, "set params for %s\n",
1339 p->source->name);
1340 return p->source->priv;
1341 }
1342 }
1343 }
1344
1345 return NULL;
1346}
1347
Dharageswari.R718a42b2016-02-05 12:19:06 +05301348static struct skl_module_cfg *skl_get_mconfig_pb_cpr(
1349 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1350{
1351 struct snd_soc_dapm_path *p;
1352 struct skl_module_cfg *mconfig = NULL;
1353
1354 snd_soc_dapm_widget_for_each_source_path(w, p) {
1355 if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) {
1356 if (p->connect &&
1357 (p->sink->id == snd_soc_dapm_aif_out) &&
1358 p->source->priv) {
1359 mconfig = p->source->priv;
1360 return mconfig;
1361 }
1362 mconfig = skl_get_mconfig_pb_cpr(dai, p->source);
1363 if (mconfig)
1364 return mconfig;
1365 }
1366 }
1367 return mconfig;
1368}
1369
1370static struct skl_module_cfg *skl_get_mconfig_cap_cpr(
1371 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1372{
1373 struct snd_soc_dapm_path *p;
1374 struct skl_module_cfg *mconfig = NULL;
1375
1376 snd_soc_dapm_widget_for_each_sink_path(w, p) {
1377 if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) {
1378 if (p->connect &&
1379 (p->source->id == snd_soc_dapm_aif_in) &&
1380 p->sink->priv) {
1381 mconfig = p->sink->priv;
1382 return mconfig;
1383 }
1384 mconfig = skl_get_mconfig_cap_cpr(dai, p->sink);
1385 if (mconfig)
1386 return mconfig;
1387 }
1388 }
1389 return mconfig;
1390}
1391
1392struct skl_module_cfg *
1393skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream)
1394{
1395 struct snd_soc_dapm_widget *w;
1396 struct skl_module_cfg *mconfig;
1397
1398 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1399 w = dai->playback_widget;
1400 mconfig = skl_get_mconfig_pb_cpr(dai, w);
1401 } else {
1402 w = dai->capture_widget;
1403 mconfig = skl_get_mconfig_cap_cpr(dai, w);
1404 }
1405 return mconfig;
1406}
1407
Vinod Koulcfb0a872015-10-07 11:31:55 +01001408static u8 skl_tplg_be_link_type(int dev_type)
1409{
1410 int ret;
1411
1412 switch (dev_type) {
1413 case SKL_DEVICE_BT:
1414 ret = NHLT_LINK_SSP;
1415 break;
1416
1417 case SKL_DEVICE_DMIC:
1418 ret = NHLT_LINK_DMIC;
1419 break;
1420
1421 case SKL_DEVICE_I2S:
1422 ret = NHLT_LINK_SSP;
1423 break;
1424
1425 case SKL_DEVICE_HDALINK:
1426 ret = NHLT_LINK_HDA;
1427 break;
1428
1429 default:
1430 ret = NHLT_LINK_INVALID;
1431 break;
1432 }
1433
1434 return ret;
1435}
1436
1437/*
1438 * Fill the BE gateway parameters
1439 * The BE gateway expects a blob of parameters which are kept in the ACPI
1440 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1441 * The port can have multiple settings so pick based on the PCM
1442 * parameters
1443 */
1444static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1445 struct skl_module_cfg *mconfig,
1446 struct skl_pipe_params *params)
1447{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001448 struct nhlt_specific_cfg *cfg;
1449 struct skl *skl = get_skl_ctx(dai->dev);
1450 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
1451
Jeeja KP8871dcb2016-06-03 18:29:42 +05301452 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001453
Jeeja KPb30c2752015-10-27 09:22:48 +09001454 if (link_type == NHLT_LINK_HDA)
1455 return 0;
1456
Vinod Koulcfb0a872015-10-07 11:31:55 +01001457 /* update the blob based on virtual bus_id*/
1458 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1459 params->s_fmt, params->ch,
1460 params->s_freq, params->stream);
1461 if (cfg) {
1462 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301463 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001464 } else {
1465 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1466 mconfig->vbus_id, link_type,
1467 params->stream);
1468 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1469 params->ch, params->s_freq, params->s_fmt);
1470 return -EINVAL;
1471 }
1472
1473 return 0;
1474}
1475
1476static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1477 struct snd_soc_dapm_widget *w,
1478 struct skl_pipe_params *params)
1479{
1480 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301481 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001482
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301483 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001484 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1485 p->source->priv) {
1486
Jeeja KP9a03cb42015-10-27 09:22:54 +09001487 ret = skl_tplg_be_fill_pipe_params(dai,
1488 p->source->priv, params);
1489 if (ret < 0)
1490 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001491 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001492 ret = skl_tplg_be_set_src_pipe_params(dai,
1493 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301494 if (ret < 0)
1495 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001496 }
1497 }
1498
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301499 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001500}
1501
1502static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1503 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1504{
1505 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301506 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001507
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301508 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001509 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1510 p->sink->priv) {
1511
Jeeja KP9a03cb42015-10-27 09:22:54 +09001512 ret = skl_tplg_be_fill_pipe_params(dai,
1513 p->sink->priv, params);
1514 if (ret < 0)
1515 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001516 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301517 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001518 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301519 if (ret < 0)
1520 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001521 }
1522 }
1523
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301524 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001525}
1526
1527/*
1528 * BE hw_params can be a source parameters (capture) or sink parameters
1529 * (playback). Based on sink and source we need to either find the source
1530 * list or the sink list and set the pipeline parameters
1531 */
1532int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1533 struct skl_pipe_params *params)
1534{
1535 struct snd_soc_dapm_widget *w;
1536
1537 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1538 w = dai->playback_widget;
1539
1540 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1541
1542 } else {
1543 w = dai->capture_widget;
1544
1545 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1546 }
1547
1548 return 0;
1549}
Vinod Koul3af36702015-10-07 11:31:56 +01001550
1551static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1552 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
1553 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event},
1554 {SKL_PGA_EVENT, skl_tplg_pga_event},
1555};
1556
Jeeja KP140adfb2015-11-28 15:01:50 +05301557static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1558 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1559 skl_tplg_tlv_control_set},
1560};
1561
Shreyas NC6277e832016-08-12 12:29:51 +05301562static int skl_tplg_fill_pipe_tkn(struct device *dev,
1563 struct skl_pipe *pipe, u32 tkn,
1564 u32 tkn_val)
Vinod Koul3af36702015-10-07 11:31:56 +01001565{
Vinod Koul3af36702015-10-07 11:31:56 +01001566
Shreyas NC6277e832016-08-12 12:29:51 +05301567 switch (tkn) {
1568 case SKL_TKN_U32_PIPE_CONN_TYPE:
1569 pipe->conn_type = tkn_val;
1570 break;
1571
1572 case SKL_TKN_U32_PIPE_PRIORITY:
1573 pipe->pipe_priority = tkn_val;
1574 break;
1575
1576 case SKL_TKN_U32_PIPE_MEM_PGS:
1577 pipe->memory_pages = tkn_val;
1578 break;
1579
Vinod Koul8a0cb232016-11-03 17:07:18 +05301580 case SKL_TKN_U32_PMODE:
1581 pipe->lp_mode = tkn_val;
1582 break;
1583
Shreyas NC6277e832016-08-12 12:29:51 +05301584 default:
1585 dev_err(dev, "Token not handled %d\n", tkn);
1586 return -EINVAL;
Vinod Koul3af36702015-10-07 11:31:56 +01001587 }
Shreyas NC6277e832016-08-12 12:29:51 +05301588
1589 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001590}
1591
1592/*
Shreyas NC6277e832016-08-12 12:29:51 +05301593 * Add pipeline by parsing the relevant tokens
1594 * Return an existing pipe if the pipe already exists.
Vinod Koul3af36702015-10-07 11:31:56 +01001595 */
Shreyas NC6277e832016-08-12 12:29:51 +05301596static int skl_tplg_add_pipe(struct device *dev,
1597 struct skl_module_cfg *mconfig, struct skl *skl,
1598 struct snd_soc_tplg_vendor_value_elem *tkn_elem)
Vinod Koul3af36702015-10-07 11:31:56 +01001599{
1600 struct skl_pipeline *ppl;
1601 struct skl_pipe *pipe;
1602 struct skl_pipe_params *params;
1603
1604 list_for_each_entry(ppl, &skl->ppl_list, node) {
Shreyas NC6277e832016-08-12 12:29:51 +05301605 if (ppl->pipe->ppl_id == tkn_elem->value) {
1606 mconfig->pipe = ppl->pipe;
1607 return EEXIST;
1608 }
Vinod Koul3af36702015-10-07 11:31:56 +01001609 }
1610
1611 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1612 if (!ppl)
Shreyas NC6277e832016-08-12 12:29:51 +05301613 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001614
1615 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1616 if (!pipe)
Shreyas NC6277e832016-08-12 12:29:51 +05301617 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001618
1619 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1620 if (!params)
Shreyas NC6277e832016-08-12 12:29:51 +05301621 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001622
Vinod Koul3af36702015-10-07 11:31:56 +01001623 pipe->p_params = params;
Shreyas NC6277e832016-08-12 12:29:51 +05301624 pipe->ppl_id = tkn_elem->value;
Vinod Koul3af36702015-10-07 11:31:56 +01001625 INIT_LIST_HEAD(&pipe->w_list);
1626
1627 ppl->pipe = pipe;
1628 list_add(&ppl->node, &skl->ppl_list);
1629
Shreyas NC6277e832016-08-12 12:29:51 +05301630 mconfig->pipe = pipe;
1631 mconfig->pipe->state = SKL_PIPE_INVALID;
1632
1633 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001634}
1635
Shreyas NC6277e832016-08-12 12:29:51 +05301636static int skl_tplg_fill_pin(struct device *dev, u32 tkn,
1637 struct skl_module_pin *m_pin,
1638 int pin_index, u32 value)
1639{
1640 switch (tkn) {
1641 case SKL_TKN_U32_PIN_MOD_ID:
1642 m_pin[pin_index].id.module_id = value;
1643 break;
1644
1645 case SKL_TKN_U32_PIN_INST_ID:
1646 m_pin[pin_index].id.instance_id = value;
1647 break;
1648
1649 default:
1650 dev_err(dev, "%d Not a pin token\n", value);
1651 return -EINVAL;
1652 }
1653
1654 return 0;
1655}
1656
1657/*
1658 * Parse for pin config specific tokens to fill up the
1659 * module private data
1660 */
1661static int skl_tplg_fill_pins_info(struct device *dev,
1662 struct skl_module_cfg *mconfig,
1663 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1664 int dir, int pin_count)
1665{
1666 int ret;
1667 struct skl_module_pin *m_pin;
1668
1669 switch (dir) {
1670 case SKL_DIR_IN:
1671 m_pin = mconfig->m_in_pin;
1672 break;
1673
1674 case SKL_DIR_OUT:
1675 m_pin = mconfig->m_out_pin;
1676 break;
1677
1678 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001679 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301680 return -EINVAL;
1681 }
1682
1683 ret = skl_tplg_fill_pin(dev, tkn_elem->token,
1684 m_pin, pin_count, tkn_elem->value);
1685
1686 if (ret < 0)
1687 return ret;
1688
1689 m_pin[pin_count].in_use = false;
1690 m_pin[pin_count].pin_state = SKL_PIN_UNBIND;
1691
1692 return 0;
1693}
1694
1695/*
1696 * Fill up input/output module config format based
1697 * on the direction
1698 */
1699static int skl_tplg_fill_fmt(struct device *dev,
1700 struct skl_module_cfg *mconfig, u32 tkn,
1701 u32 value, u32 dir, u32 pin_count)
1702{
1703 struct skl_module_fmt *dst_fmt;
1704
1705 switch (dir) {
1706 case SKL_DIR_IN:
1707 dst_fmt = mconfig->in_fmt;
1708 dst_fmt += pin_count;
1709 break;
1710
1711 case SKL_DIR_OUT:
1712 dst_fmt = mconfig->out_fmt;
1713 dst_fmt += pin_count;
1714 break;
1715
1716 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001717 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301718 return -EINVAL;
1719 }
1720
1721 switch (tkn) {
1722 case SKL_TKN_U32_FMT_CH:
1723 dst_fmt->channels = value;
1724 break;
1725
1726 case SKL_TKN_U32_FMT_FREQ:
1727 dst_fmt->s_freq = value;
1728 break;
1729
1730 case SKL_TKN_U32_FMT_BIT_DEPTH:
1731 dst_fmt->bit_depth = value;
1732 break;
1733
1734 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1735 dst_fmt->valid_bit_depth = value;
1736 break;
1737
1738 case SKL_TKN_U32_FMT_CH_CONFIG:
1739 dst_fmt->ch_cfg = value;
1740 break;
1741
1742 case SKL_TKN_U32_FMT_INTERLEAVE:
1743 dst_fmt->interleaving_style = value;
1744 break;
1745
1746 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1747 dst_fmt->sample_type = value;
1748 break;
1749
1750 case SKL_TKN_U32_FMT_CH_MAP:
1751 dst_fmt->ch_map = value;
1752 break;
1753
1754 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001755 dev_err(dev, "Invalid token %d\n", tkn);
Shreyas NC6277e832016-08-12 12:29:51 +05301756 return -EINVAL;
1757 }
1758
1759 return 0;
1760}
1761
1762static int skl_tplg_get_uuid(struct device *dev, struct skl_module_cfg *mconfig,
1763 struct snd_soc_tplg_vendor_uuid_elem *uuid_tkn)
1764{
1765 if (uuid_tkn->token == SKL_TKN_UUID)
1766 memcpy(&mconfig->guid, &uuid_tkn->uuid, 16);
1767 else {
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001768 dev_err(dev, "Not an UUID token tkn %d\n", uuid_tkn->token);
Shreyas NC6277e832016-08-12 12:29:51 +05301769 return -EINVAL;
1770 }
1771
1772 return 0;
1773}
1774
1775static void skl_tplg_fill_pin_dynamic_val(
1776 struct skl_module_pin *mpin, u32 pin_count, u32 value)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001777{
1778 int i;
1779
Shreyas NC6277e832016-08-12 12:29:51 +05301780 for (i = 0; i < pin_count; i++)
1781 mpin[i].is_dynamic = value;
1782}
1783
1784/*
1785 * Parse tokens to fill up the module private data
1786 */
1787static int skl_tplg_get_token(struct device *dev,
1788 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1789 struct skl *skl, struct skl_module_cfg *mconfig)
1790{
1791 int tkn_count = 0;
1792 int ret;
1793 static int is_pipe_exists;
1794 static int pin_index, dir;
1795
1796 if (tkn_elem->token > SKL_TKN_MAX)
1797 return -EINVAL;
1798
1799 switch (tkn_elem->token) {
1800 case SKL_TKN_U8_IN_QUEUE_COUNT:
1801 mconfig->max_in_queue = tkn_elem->value;
1802 mconfig->m_in_pin = devm_kzalloc(dev, mconfig->max_in_queue *
1803 sizeof(*mconfig->m_in_pin),
1804 GFP_KERNEL);
1805 if (!mconfig->m_in_pin)
1806 return -ENOMEM;
1807
1808 break;
1809
1810 case SKL_TKN_U8_OUT_QUEUE_COUNT:
1811 mconfig->max_out_queue = tkn_elem->value;
1812 mconfig->m_out_pin = devm_kzalloc(dev, mconfig->max_out_queue *
1813 sizeof(*mconfig->m_out_pin),
1814 GFP_KERNEL);
1815
1816 if (!mconfig->m_out_pin)
1817 return -ENOMEM;
1818
1819 break;
1820
1821 case SKL_TKN_U8_DYN_IN_PIN:
1822 if (!mconfig->m_in_pin)
1823 return -ENOMEM;
1824
1825 skl_tplg_fill_pin_dynamic_val(mconfig->m_in_pin,
1826 mconfig->max_in_queue, tkn_elem->value);
1827
1828 break;
1829
1830 case SKL_TKN_U8_DYN_OUT_PIN:
1831 if (!mconfig->m_out_pin)
1832 return -ENOMEM;
1833
1834 skl_tplg_fill_pin_dynamic_val(mconfig->m_out_pin,
1835 mconfig->max_out_queue, tkn_elem->value);
1836
1837 break;
1838
1839 case SKL_TKN_U8_TIME_SLOT:
1840 mconfig->time_slot = tkn_elem->value;
1841 break;
1842
1843 case SKL_TKN_U8_CORE_ID:
1844 mconfig->core_id = tkn_elem->value;
1845
1846 case SKL_TKN_U8_MOD_TYPE:
1847 mconfig->m_type = tkn_elem->value;
1848 break;
1849
1850 case SKL_TKN_U8_DEV_TYPE:
1851 mconfig->dev_type = tkn_elem->value;
1852 break;
1853
1854 case SKL_TKN_U8_HW_CONN_TYPE:
1855 mconfig->hw_conn_type = tkn_elem->value;
1856 break;
1857
1858 case SKL_TKN_U16_MOD_INST_ID:
1859 mconfig->id.instance_id =
1860 tkn_elem->value;
1861 break;
1862
1863 case SKL_TKN_U32_MEM_PAGES:
1864 mconfig->mem_pages = tkn_elem->value;
1865 break;
1866
1867 case SKL_TKN_U32_MAX_MCPS:
1868 mconfig->mcps = tkn_elem->value;
1869 break;
1870
1871 case SKL_TKN_U32_OBS:
1872 mconfig->obs = tkn_elem->value;
1873 break;
1874
1875 case SKL_TKN_U32_IBS:
1876 mconfig->ibs = tkn_elem->value;
1877 break;
1878
1879 case SKL_TKN_U32_VBUS_ID:
1880 mconfig->vbus_id = tkn_elem->value;
1881 break;
1882
1883 case SKL_TKN_U32_PARAMS_FIXUP:
1884 mconfig->params_fixup = tkn_elem->value;
1885 break;
1886
1887 case SKL_TKN_U32_CONVERTER:
1888 mconfig->converter = tkn_elem->value;
1889 break;
1890
Vinod Koul6bd9dcf2016-11-03 17:07:19 +05301891 case SKL_TKL_U32_D0I3_CAPS:
1892 mconfig->d0i3_caps = tkn_elem->value;
1893 break;
1894
Shreyas NC6277e832016-08-12 12:29:51 +05301895 case SKL_TKN_U32_PIPE_ID:
1896 ret = skl_tplg_add_pipe(dev,
1897 mconfig, skl, tkn_elem);
1898
1899 if (ret < 0)
1900 return is_pipe_exists;
1901
1902 if (ret == EEXIST)
1903 is_pipe_exists = 1;
1904
1905 break;
1906
1907 case SKL_TKN_U32_PIPE_CONN_TYPE:
1908 case SKL_TKN_U32_PIPE_PRIORITY:
1909 case SKL_TKN_U32_PIPE_MEM_PGS:
Vinod Koul8a0cb232016-11-03 17:07:18 +05301910 case SKL_TKN_U32_PMODE:
Shreyas NC6277e832016-08-12 12:29:51 +05301911 if (is_pipe_exists) {
1912 ret = skl_tplg_fill_pipe_tkn(dev, mconfig->pipe,
1913 tkn_elem->token, tkn_elem->value);
1914 if (ret < 0)
1915 return ret;
1916 }
1917
1918 break;
1919
1920 /*
1921 * SKL_TKN_U32_DIR_PIN_COUNT token has the value for both
1922 * direction and the pin count. The first four bits represent
1923 * direction and next four the pin count.
1924 */
1925 case SKL_TKN_U32_DIR_PIN_COUNT:
1926 dir = tkn_elem->value & SKL_IN_DIR_BIT_MASK;
1927 pin_index = (tkn_elem->value &
1928 SKL_PIN_COUNT_MASK) >> 4;
1929
1930 break;
1931
1932 case SKL_TKN_U32_FMT_CH:
1933 case SKL_TKN_U32_FMT_FREQ:
1934 case SKL_TKN_U32_FMT_BIT_DEPTH:
1935 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1936 case SKL_TKN_U32_FMT_CH_CONFIG:
1937 case SKL_TKN_U32_FMT_INTERLEAVE:
1938 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1939 case SKL_TKN_U32_FMT_CH_MAP:
1940 ret = skl_tplg_fill_fmt(dev, mconfig, tkn_elem->token,
1941 tkn_elem->value, dir, pin_index);
1942
1943 if (ret < 0)
1944 return ret;
1945
1946 break;
1947
1948 case SKL_TKN_U32_PIN_MOD_ID:
1949 case SKL_TKN_U32_PIN_INST_ID:
1950 ret = skl_tplg_fill_pins_info(dev,
1951 mconfig, tkn_elem, dir,
1952 pin_index);
1953 if (ret < 0)
1954 return ret;
1955
1956 break;
1957
1958 case SKL_TKN_U32_CAPS_SIZE:
1959 mconfig->formats_config.caps_size =
1960 tkn_elem->value;
1961
1962 break;
1963
1964 case SKL_TKN_U32_PROC_DOMAIN:
1965 mconfig->domain =
1966 tkn_elem->value;
1967
1968 break;
1969
1970 case SKL_TKN_U8_IN_PIN_TYPE:
1971 case SKL_TKN_U8_OUT_PIN_TYPE:
1972 case SKL_TKN_U8_CONN_TYPE:
1973 break;
1974
1975 default:
1976 dev_err(dev, "Token %d not handled\n",
1977 tkn_elem->token);
1978 return -EINVAL;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001979 }
Shreyas NC6277e832016-08-12 12:29:51 +05301980
1981 tkn_count++;
1982
1983 return tkn_count;
1984}
1985
1986/*
1987 * Parse the vendor array for specific tokens to construct
1988 * module private data
1989 */
1990static int skl_tplg_get_tokens(struct device *dev,
1991 char *pvt_data, struct skl *skl,
1992 struct skl_module_cfg *mconfig, int block_size)
1993{
1994 struct snd_soc_tplg_vendor_array *array;
1995 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
1996 int tkn_count = 0, ret;
1997 int off = 0, tuple_size = 0;
1998
1999 if (block_size <= 0)
2000 return -EINVAL;
2001
2002 while (tuple_size < block_size) {
2003 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2004
2005 off += array->size;
2006
2007 switch (array->type) {
2008 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002009 dev_warn(dev, "no string tokens expected for skl tplg\n");
Shreyas NC6277e832016-08-12 12:29:51 +05302010 continue;
2011
2012 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
2013 ret = skl_tplg_get_uuid(dev, mconfig, array->uuid);
2014 if (ret < 0)
2015 return ret;
2016
2017 tuple_size += sizeof(*array->uuid);
2018
2019 continue;
2020
2021 default:
2022 tkn_elem = array->value;
2023 tkn_count = 0;
2024 break;
2025 }
2026
2027 while (tkn_count <= (array->num_elems - 1)) {
2028 ret = skl_tplg_get_token(dev, tkn_elem,
2029 skl, mconfig);
2030
2031 if (ret < 0)
2032 return ret;
2033
2034 tkn_count = tkn_count + ret;
2035 tkn_elem++;
2036 }
2037
2038 tuple_size += tkn_count * sizeof(*tkn_elem);
2039 }
2040
2041 return 0;
2042}
2043
2044/*
2045 * Every data block is preceded by a descriptor to read the number
2046 * of data blocks, they type of the block and it's size
2047 */
2048static int skl_tplg_get_desc_blocks(struct device *dev,
2049 struct snd_soc_tplg_vendor_array *array)
2050{
2051 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2052
2053 tkn_elem = array->value;
2054
2055 switch (tkn_elem->token) {
2056 case SKL_TKN_U8_NUM_BLOCKS:
2057 case SKL_TKN_U8_BLOCK_TYPE:
2058 case SKL_TKN_U16_BLOCK_SIZE:
2059 return tkn_elem->value;
2060
2061 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002062 dev_err(dev, "Invalid descriptor token %d\n", tkn_elem->token);
Shreyas NC6277e832016-08-12 12:29:51 +05302063 break;
2064 }
2065
2066 return -EINVAL;
2067}
2068
2069/*
2070 * Parse the private data for the token and corresponding value.
2071 * The private data can have multiple data blocks. So, a data block
2072 * is preceded by a descriptor for number of blocks and a descriptor
2073 * for the type and size of the suceeding data block.
2074 */
2075static int skl_tplg_get_pvt_data(struct snd_soc_tplg_dapm_widget *tplg_w,
2076 struct skl *skl, struct device *dev,
2077 struct skl_module_cfg *mconfig)
2078{
2079 struct snd_soc_tplg_vendor_array *array;
2080 int num_blocks, block_size = 0, block_type, off = 0;
2081 char *data;
2082 int ret;
2083
2084 /* Read the NUM_DATA_BLOCKS descriptor */
2085 array = (struct snd_soc_tplg_vendor_array *)tplg_w->priv.data;
2086 ret = skl_tplg_get_desc_blocks(dev, array);
2087 if (ret < 0)
2088 return ret;
2089 num_blocks = ret;
2090
2091 off += array->size;
2092 array = (struct snd_soc_tplg_vendor_array *)(tplg_w->priv.data + off);
2093
2094 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2095 while (num_blocks > 0) {
2096 ret = skl_tplg_get_desc_blocks(dev, array);
2097
2098 if (ret < 0)
2099 return ret;
2100 block_type = ret;
2101 off += array->size;
2102
2103 array = (struct snd_soc_tplg_vendor_array *)
2104 (tplg_w->priv.data + off);
2105
2106 ret = skl_tplg_get_desc_blocks(dev, array);
2107
2108 if (ret < 0)
2109 return ret;
2110 block_size = ret;
2111 off += array->size;
2112
2113 array = (struct snd_soc_tplg_vendor_array *)
2114 (tplg_w->priv.data + off);
2115
2116 data = (tplg_w->priv.data + off);
2117
2118 if (block_type == SKL_TYPE_TUPLE) {
2119 ret = skl_tplg_get_tokens(dev, data,
2120 skl, mconfig, block_size);
2121
2122 if (ret < 0)
2123 return ret;
2124
2125 --num_blocks;
2126 } else {
2127 if (mconfig->formats_config.caps_size > 0)
2128 memcpy(mconfig->formats_config.caps, data,
2129 mconfig->formats_config.caps_size);
2130 --num_blocks;
2131 }
2132 }
2133
2134 return 0;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002135}
2136
Dharageswari Rfe3f4442016-06-03 18:29:39 +05302137static void skl_clear_pin_config(struct snd_soc_platform *platform,
2138 struct snd_soc_dapm_widget *w)
2139{
2140 int i;
2141 struct skl_module_cfg *mconfig;
2142 struct skl_pipe *pipe;
2143
2144 if (!strncmp(w->dapm->component->name, platform->component.name,
2145 strlen(platform->component.name))) {
2146 mconfig = w->priv;
2147 pipe = mconfig->pipe;
2148 for (i = 0; i < mconfig->max_in_queue; i++) {
2149 mconfig->m_in_pin[i].in_use = false;
2150 mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND;
2151 }
2152 for (i = 0; i < mconfig->max_out_queue; i++) {
2153 mconfig->m_out_pin[i].in_use = false;
2154 mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND;
2155 }
2156 pipe->state = SKL_PIPE_INVALID;
2157 mconfig->m_state = SKL_MODULE_UNINIT;
2158 }
2159}
2160
2161void skl_cleanup_resources(struct skl *skl)
2162{
2163 struct skl_sst *ctx = skl->skl_sst;
2164 struct snd_soc_platform *soc_platform = skl->platform;
2165 struct snd_soc_dapm_widget *w;
2166 struct snd_soc_card *card;
2167
2168 if (soc_platform == NULL)
2169 return;
2170
2171 card = soc_platform->component.card;
2172 if (!card || !card->instantiated)
2173 return;
2174
2175 skl->resource.mem = 0;
2176 skl->resource.mcps = 0;
2177
2178 list_for_each_entry(w, &card->widgets, list) {
2179 if (is_skl_dsp_widget_type(w) && (w->priv != NULL))
2180 skl_clear_pin_config(soc_platform, w);
2181 }
2182
2183 skl_clear_module_cnt(ctx->dsp);
2184}
2185
Vinod Koul3af36702015-10-07 11:31:56 +01002186/*
2187 * Topology core widget load callback
2188 *
2189 * This is used to save the private data for each widget which gives
2190 * information to the driver about module and pipeline parameters which DSP
2191 * FW expects like ids, resource values, formats etc
2192 */
2193static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002194 struct snd_soc_dapm_widget *w,
2195 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01002196{
2197 int ret;
2198 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2199 struct skl *skl = ebus_to_skl(ebus);
2200 struct hdac_bus *bus = ebus_to_hbus(ebus);
2201 struct skl_module_cfg *mconfig;
Vinod Koul3af36702015-10-07 11:31:56 +01002202
2203 if (!tplg_w->priv.size)
2204 goto bind_event;
2205
2206 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
2207
2208 if (!mconfig)
2209 return -ENOMEM;
2210
2211 w->priv = mconfig;
Shreyas NC09305da2016-04-21 11:45:22 +05302212
Vinod Koulb7c50552016-07-26 18:06:40 +05302213 /*
2214 * module binary can be loaded later, so set it to query when
2215 * module is load for a use case
2216 */
2217 mconfig->id.module_id = -1;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002218
Shreyas NC6277e832016-08-12 12:29:51 +05302219 /* Parse private data for tuples */
2220 ret = skl_tplg_get_pvt_data(tplg_w, skl, bus->dev, mconfig);
2221 if (ret < 0)
2222 return ret;
Vinod Koul3af36702015-10-07 11:31:56 +01002223bind_event:
2224 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01002225 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01002226 return 0;
2227 }
2228
2229 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002230 ARRAY_SIZE(skl_tplg_widget_ops),
2231 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01002232
2233 if (ret) {
2234 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
2235 __func__, tplg_w->event_type);
2236 return -EINVAL;
2237 }
2238
2239 return 0;
2240}
2241
Jeeja KP140adfb2015-11-28 15:01:50 +05302242static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
2243 struct snd_soc_tplg_bytes_control *bc)
2244{
2245 struct skl_algo_data *ac;
2246 struct skl_dfw_algo_data *dfw_ac =
2247 (struct skl_dfw_algo_data *)bc->priv.data;
2248
2249 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
2250 if (!ac)
2251 return -ENOMEM;
2252
2253 /* Fill private data */
2254 ac->max = dfw_ac->max;
2255 ac->param_id = dfw_ac->param_id;
2256 ac->set_params = dfw_ac->set_params;
Dharageswari R0d682102016-07-08 18:15:03 +05302257 ac->size = dfw_ac->max;
Jeeja KP140adfb2015-11-28 15:01:50 +05302258
2259 if (ac->max) {
2260 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
2261 if (!ac->params)
2262 return -ENOMEM;
2263
Alan Coxedd7ea22016-02-22 09:37:27 +05302264 memcpy(ac->params, dfw_ac->params, ac->max);
Jeeja KP140adfb2015-11-28 15:01:50 +05302265 }
2266
2267 be->dobj.private = ac;
2268 return 0;
2269}
2270
2271static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
2272 struct snd_kcontrol_new *kctl,
2273 struct snd_soc_tplg_ctl_hdr *hdr)
2274{
2275 struct soc_bytes_ext *sb;
2276 struct snd_soc_tplg_bytes_control *tplg_bc;
2277 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2278 struct hdac_bus *bus = ebus_to_hbus(ebus);
2279
2280 switch (hdr->ops.info) {
2281 case SND_SOC_TPLG_CTL_BYTES:
2282 tplg_bc = container_of(hdr,
2283 struct snd_soc_tplg_bytes_control, hdr);
2284 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
2285 sb = (struct soc_bytes_ext *)kctl->private_value;
2286 if (tplg_bc->priv.size)
2287 return skl_init_algo_data(
2288 bus->dev, sb, tplg_bc);
2289 }
2290 break;
2291
2292 default:
2293 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
2294 hdr->ops.get, hdr->ops.put, hdr->ops.info);
2295 break;
2296 }
2297
2298 return 0;
2299}
2300
Shreyas NC541070c2016-08-23 09:31:03 +05302301static int skl_tplg_fill_str_mfest_tkn(struct device *dev,
2302 struct snd_soc_tplg_vendor_string_elem *str_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302303 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302304{
2305 int tkn_count = 0;
2306 static int ref_count;
2307
2308 switch (str_elem->token) {
2309 case SKL_TKN_STR_LIB_NAME:
Jeeja KPeee0e162017-01-02 09:50:04 +05302310 if (ref_count > skl->skl_sst->lib_count - 1) {
Shreyas NC541070c2016-08-23 09:31:03 +05302311 ref_count = 0;
2312 return -EINVAL;
2313 }
2314
Jeeja KPeee0e162017-01-02 09:50:04 +05302315 strncpy(skl->skl_sst->lib_info[ref_count].name,
2316 str_elem->string,
2317 ARRAY_SIZE(skl->skl_sst->lib_info[ref_count].name));
Shreyas NC541070c2016-08-23 09:31:03 +05302318 ref_count++;
2319 tkn_count++;
2320 break;
2321
2322 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002323 dev_err(dev, "Not a string token %d\n", str_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302324 break;
2325 }
2326
2327 return tkn_count;
2328}
2329
2330static int skl_tplg_get_str_tkn(struct device *dev,
2331 struct snd_soc_tplg_vendor_array *array,
Jeeja KPeee0e162017-01-02 09:50:04 +05302332 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302333{
2334 int tkn_count = 0, ret;
2335 struct snd_soc_tplg_vendor_string_elem *str_elem;
2336
2337 str_elem = (struct snd_soc_tplg_vendor_string_elem *)array->value;
2338 while (tkn_count < array->num_elems) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302339 ret = skl_tplg_fill_str_mfest_tkn(dev, str_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302340 str_elem++;
2341
2342 if (ret < 0)
2343 return ret;
2344
2345 tkn_count = tkn_count + ret;
2346 }
2347
2348 return tkn_count;
2349}
2350
2351static int skl_tplg_get_int_tkn(struct device *dev,
2352 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302353 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302354{
2355 int tkn_count = 0;
2356
2357 switch (tkn_elem->token) {
2358 case SKL_TKN_U32_LIB_COUNT:
Jeeja KPeee0e162017-01-02 09:50:04 +05302359 skl->skl_sst->lib_count = tkn_elem->value;
Shreyas NC541070c2016-08-23 09:31:03 +05302360 tkn_count++;
2361 break;
2362
2363 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002364 dev_err(dev, "Not a manifest token %d\n", tkn_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302365 return -EINVAL;
2366 }
2367
2368 return tkn_count;
2369}
2370
2371/*
2372 * Fill the manifest structure by parsing the tokens based on the
2373 * type.
2374 */
2375static int skl_tplg_get_manifest_tkn(struct device *dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302376 char *pvt_data, struct skl *skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302377 int block_size)
2378{
2379 int tkn_count = 0, ret;
2380 int off = 0, tuple_size = 0;
2381 struct snd_soc_tplg_vendor_array *array;
2382 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2383
2384 if (block_size <= 0)
2385 return -EINVAL;
2386
2387 while (tuple_size < block_size) {
2388 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2389 off += array->size;
2390 switch (array->type) {
2391 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Jeeja KPeee0e162017-01-02 09:50:04 +05302392 ret = skl_tplg_get_str_tkn(dev, array, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302393
2394 if (ret < 0)
2395 return ret;
2396 tkn_count += ret;
2397
2398 tuple_size += tkn_count *
2399 sizeof(struct snd_soc_tplg_vendor_string_elem);
2400 continue;
2401
2402 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002403 dev_warn(dev, "no uuid tokens for skl tplf manifest\n");
Shreyas NC541070c2016-08-23 09:31:03 +05302404 continue;
2405
2406 default:
2407 tkn_elem = array->value;
2408 tkn_count = 0;
2409 break;
2410 }
2411
2412 while (tkn_count <= array->num_elems - 1) {
2413 ret = skl_tplg_get_int_tkn(dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302414 tkn_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302415 if (ret < 0)
2416 return ret;
2417
2418 tkn_count = tkn_count + ret;
2419 tkn_elem++;
2420 tuple_size += tkn_count *
2421 sizeof(struct snd_soc_tplg_vendor_value_elem);
2422 break;
2423 }
2424 tkn_count = 0;
2425 }
2426
2427 return 0;
2428}
2429
2430/*
2431 * Parse manifest private data for tokens. The private data block is
2432 * preceded by descriptors for type and size of data block.
2433 */
2434static int skl_tplg_get_manifest_data(struct snd_soc_tplg_manifest *manifest,
Jeeja KPeee0e162017-01-02 09:50:04 +05302435 struct device *dev, struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302436{
2437 struct snd_soc_tplg_vendor_array *array;
2438 int num_blocks, block_size = 0, block_type, off = 0;
2439 char *data;
2440 int ret;
2441
2442 /* Read the NUM_DATA_BLOCKS descriptor */
2443 array = (struct snd_soc_tplg_vendor_array *)manifest->priv.data;
2444 ret = skl_tplg_get_desc_blocks(dev, array);
2445 if (ret < 0)
2446 return ret;
2447 num_blocks = ret;
2448
2449 off += array->size;
2450 array = (struct snd_soc_tplg_vendor_array *)
2451 (manifest->priv.data + off);
2452
2453 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2454 while (num_blocks > 0) {
2455 ret = skl_tplg_get_desc_blocks(dev, array);
2456
2457 if (ret < 0)
2458 return ret;
2459 block_type = ret;
2460 off += array->size;
2461
2462 array = (struct snd_soc_tplg_vendor_array *)
2463 (manifest->priv.data + off);
2464
2465 ret = skl_tplg_get_desc_blocks(dev, array);
2466
2467 if (ret < 0)
2468 return ret;
2469 block_size = ret;
2470 off += array->size;
2471
2472 array = (struct snd_soc_tplg_vendor_array *)
2473 (manifest->priv.data + off);
2474
2475 data = (manifest->priv.data + off);
2476
2477 if (block_type == SKL_TYPE_TUPLE) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302478 ret = skl_tplg_get_manifest_tkn(dev, data, skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302479 block_size);
2480
2481 if (ret < 0)
2482 return ret;
2483
2484 --num_blocks;
2485 } else {
2486 return -EINVAL;
2487 }
2488 }
2489
2490 return 0;
2491}
2492
Kranthi G15ecaba92016-07-26 18:06:43 +05302493static int skl_manifest_load(struct snd_soc_component *cmpnt,
2494 struct snd_soc_tplg_manifest *manifest)
2495{
Kranthi G15ecaba92016-07-26 18:06:43 +05302496 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2497 struct hdac_bus *bus = ebus_to_hbus(ebus);
2498 struct skl *skl = ebus_to_skl(ebus);
Kranthi G15ecaba92016-07-26 18:06:43 +05302499
Vinod Koulc15ad602016-08-24 18:03:13 +05302500 /* proceed only if we have private data defined */
2501 if (manifest->priv.size == 0)
2502 return 0;
2503
Jeeja KPeee0e162017-01-02 09:50:04 +05302504 skl_tplg_get_manifest_data(manifest, bus->dev, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302505
Jeeja KPeee0e162017-01-02 09:50:04 +05302506 if (skl->skl_sst->lib_count > SKL_MAX_LIB) {
Kranthi G15ecaba92016-07-26 18:06:43 +05302507 dev_err(bus->dev, "Exceeding max Library count. Got:%d\n",
Jeeja KPeee0e162017-01-02 09:50:04 +05302508 skl->skl_sst->lib_count);
2509 return -EINVAL;
Kranthi G15ecaba92016-07-26 18:06:43 +05302510 }
2511
Jeeja KPeee0e162017-01-02 09:50:04 +05302512 return 0;
Kranthi G15ecaba92016-07-26 18:06:43 +05302513}
2514
Vinod Koul3af36702015-10-07 11:31:56 +01002515static struct snd_soc_tplg_ops skl_tplg_ops = {
2516 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05302517 .control_load = skl_tplg_control_load,
2518 .bytes_ext_ops = skl_tlv_ops,
2519 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Kranthi G15ecaba92016-07-26 18:06:43 +05302520 .manifest = skl_manifest_load,
Vinod Koul3af36702015-10-07 11:31:56 +01002521};
2522
Jeeja KP287af4f2016-06-03 18:29:40 +05302523/*
2524 * A pipe can have multiple modules, each of them will be a DAPM widget as
2525 * well. While managing a pipeline we need to get the list of all the
2526 * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list()
2527 * helps to get the SKL type widgets in that pipeline
2528 */
2529static int skl_tplg_create_pipe_widget_list(struct snd_soc_platform *platform)
2530{
2531 struct snd_soc_dapm_widget *w;
2532 struct skl_module_cfg *mcfg = NULL;
2533 struct skl_pipe_module *p_module = NULL;
2534 struct skl_pipe *pipe;
2535
2536 list_for_each_entry(w, &platform->component.card->widgets, list) {
2537 if (is_skl_dsp_widget_type(w) && w->priv != NULL) {
2538 mcfg = w->priv;
2539 pipe = mcfg->pipe;
2540
2541 p_module = devm_kzalloc(platform->dev,
2542 sizeof(*p_module), GFP_KERNEL);
2543 if (!p_module)
2544 return -ENOMEM;
2545
2546 p_module->w = w;
2547 list_add_tail(&p_module->node, &pipe->w_list);
2548 }
2549 }
2550
2551 return 0;
2552}
2553
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302554static void skl_tplg_set_pipe_type(struct skl *skl, struct skl_pipe *pipe)
2555{
2556 struct skl_pipe_module *w_module;
2557 struct snd_soc_dapm_widget *w;
2558 struct skl_module_cfg *mconfig;
2559 bool host_found = false, link_found = false;
2560
2561 list_for_each_entry(w_module, &pipe->w_list, node) {
2562 w = w_module->w;
2563 mconfig = w->priv;
2564
2565 if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
2566 host_found = true;
2567 else if (mconfig->dev_type != SKL_DEVICE_NONE)
2568 link_found = true;
2569 }
2570
2571 if (host_found && link_found)
2572 pipe->passthru = true;
2573 else
2574 pipe->passthru = false;
2575}
2576
Vinod Koul3af36702015-10-07 11:31:56 +01002577/* This will be read from topology manifest, currently defined here */
2578#define SKL_MAX_MCPS 30000000
2579#define SKL_FW_MAX_MEM 1000000
2580
2581/*
2582 * SKL topology init routine
2583 */
2584int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
2585{
2586 int ret;
2587 const struct firmware *fw;
2588 struct hdac_bus *bus = ebus_to_hbus(ebus);
2589 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302590 struct skl_pipeline *ppl;
Vinod Koul3af36702015-10-07 11:31:56 +01002591
Vinod Koul4b235c42016-02-19 11:42:34 +05302592 ret = request_firmware(&fw, skl->tplg_name, bus->dev);
Vinod Koul3af36702015-10-07 11:31:56 +01002593 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01002594 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul4b235c42016-02-19 11:42:34 +05302595 skl->tplg_name, ret);
2596 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
2597 if (ret < 0) {
2598 dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n",
2599 "dfw_sst.bin", ret);
2600 return ret;
2601 }
Vinod Koul3af36702015-10-07 11:31:56 +01002602 }
2603
2604 /*
2605 * The complete tplg for SKL is loaded as index 0, we don't use
2606 * any other index
2607 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01002608 ret = snd_soc_tplg_component_load(&platform->component,
2609 &skl_tplg_ops, fw, 0);
Vinod Koul3af36702015-10-07 11:31:56 +01002610 if (ret < 0) {
2611 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05302612 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01002613 return -EINVAL;
2614 }
2615
2616 skl->resource.max_mcps = SKL_MAX_MCPS;
2617 skl->resource.max_mem = SKL_FW_MAX_MEM;
2618
Vinod Kould8018362016-01-05 17:16:04 +05302619 skl->tplg = fw;
Jeeja KP287af4f2016-06-03 18:29:40 +05302620 ret = skl_tplg_create_pipe_widget_list(platform);
2621 if (ret < 0)
2622 return ret;
Vinod Kould8018362016-01-05 17:16:04 +05302623
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302624 list_for_each_entry(ppl, &skl->ppl_list, node)
2625 skl_tplg_set_pipe_type(skl, ppl->pipe);
Vinod Koul3af36702015-10-07 11:31:56 +01002626
2627 return 0;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01002628}