R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
Sricharan R | fa63d03 | 2013-06-07 18:52:47 +0530 | [diff] [blame] | 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 10 | #include "omap5.dtsi" |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 13 | |
| 14 | / { |
Sricharan R | fa63d03 | 2013-06-07 18:52:47 +0530 | [diff] [blame] | 15 | model = "TI OMAP5 uEVM board"; |
| 16 | compatible = "ti,omap5-uevm", "ti,omap5"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 17 | |
| 18 | memory { |
| 19 | device_type = "memory"; |
Santosh Shilimkar | 03178c6 | 2013-01-18 11:43:16 +0530 | [diff] [blame] | 20 | reg = <0x80000000 0x7F000000>; /* 2032 MB */ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 21 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 22 | |
| 23 | vmmcsd_fixed: fixedregulator-mmcsd { |
| 24 | compatible = "regulator-fixed"; |
| 25 | regulator-name = "vmmcsd_fixed"; |
| 26 | regulator-min-microvolt = <3000000>; |
| 27 | regulator-max-microvolt = <3000000>; |
| 28 | }; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 29 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 30 | /* HS USB Port 2 RESET */ |
| 31 | hsusb2_reset: hsusb2_reset_reg { |
| 32 | compatible = "regulator-fixed"; |
| 33 | regulator-name = "hsusb2_reset"; |
| 34 | regulator-min-microvolt = <3300000>; |
| 35 | regulator-max-microvolt = <3300000>; |
| 36 | gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ |
| 37 | startup-delay-us = <70000>; |
| 38 | enable-active-high; |
| 39 | }; |
| 40 | |
| 41 | /* HS USB Host PHY on PORT 2 */ |
| 42 | hsusb2_phy: hsusb2_phy { |
| 43 | compatible = "usb-nop-xceiv"; |
| 44 | reset-supply = <&hsusb2_reset>; |
Roger Quadros | 153030c | 2013-06-18 19:04:46 +0300 | [diff] [blame] | 45 | /** |
| 46 | * FIXME |
| 47 | * Put the right clock phandle here when available |
| 48 | * clocks = <&auxclk1>; |
| 49 | * clock-names = "main_clk"; |
| 50 | */ |
| 51 | clock-frequency = <19200000>; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 52 | }; |
| 53 | |
| 54 | /* HS USB Port 3 RESET */ |
| 55 | hsusb3_reset: hsusb3_reset_reg { |
| 56 | compatible = "regulator-fixed"; |
| 57 | regulator-name = "hsusb3_reset"; |
| 58 | regulator-min-microvolt = <3300000>; |
| 59 | regulator-max-microvolt = <3300000>; |
| 60 | gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ |
| 61 | startup-delay-us = <70000>; |
| 62 | enable-active-high; |
| 63 | }; |
| 64 | |
| 65 | /* HS USB Host PHY on PORT 3 */ |
| 66 | hsusb3_phy: hsusb3_phy { |
| 67 | compatible = "usb-nop-xceiv"; |
| 68 | reset-supply = <&hsusb3_reset>; |
| 69 | }; |
| 70 | |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 71 | leds { |
| 72 | compatible = "gpio-leds"; |
| 73 | led@1 { |
| 74 | label = "omap5:blue:usr1"; |
| 75 | gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ |
| 76 | linux,default-trigger = "heartbeat"; |
| 77 | default-state = "off"; |
| 78 | }; |
| 79 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 80 | }; |
| 81 | |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 82 | &omap5_pmx_core { |
| 83 | pinctrl-names = "default"; |
| 84 | pinctrl-0 = < |
| 85 | &twl6040_pins |
| 86 | &mcpdm_pins |
| 87 | &dmic_pins |
| 88 | &mcbsp1_pins |
| 89 | &mcbsp2_pins |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 90 | &usbhost_pins |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 91 | &led_gpio_pins |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 92 | >; |
| 93 | |
| 94 | twl6040_pins: pinmux_twl6040_pins { |
| 95 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 96 | 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 97 | >; |
| 98 | }; |
| 99 | |
| 100 | mcpdm_pins: pinmux_mcpdm_pins { |
| 101 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 102 | 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ |
| 103 | 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ |
| 104 | 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ |
| 105 | 0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ |
| 106 | 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 107 | >; |
| 108 | }; |
| 109 | |
| 110 | dmic_pins: pinmux_dmic_pins { |
| 111 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 112 | 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */ |
| 113 | 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */ |
| 114 | 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */ |
| 115 | 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 116 | >; |
| 117 | }; |
| 118 | |
| 119 | mcbsp1_pins: pinmux_mcbsp1_pins { |
| 120 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 121 | 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ |
| 122 | 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ |
| 123 | 0x150 (PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ |
| 124 | 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 125 | >; |
| 126 | }; |
| 127 | |
| 128 | mcbsp2_pins: pinmux_mcbsp2_pins { |
| 129 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 130 | 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ |
| 131 | 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ |
| 132 | 0x158 (PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ |
| 133 | 0x15a (PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 134 | >; |
| 135 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 136 | |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 137 | i2c1_pins: pinmux_i2c1_pins { |
| 138 | pinctrl-single,pins = < |
| 139 | 0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ |
| 140 | 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ |
| 141 | >; |
| 142 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 143 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 144 | i2c5_pins: pinmux_i2c5_pins { |
| 145 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 146 | 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */ |
| 147 | 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */ |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 148 | >; |
| 149 | }; |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 150 | |
| 151 | mcspi2_pins: pinmux_mcspi2_pins { |
| 152 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 153 | 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ |
| 154 | 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ |
| 155 | 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ |
| 156 | 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 157 | >; |
| 158 | }; |
| 159 | |
| 160 | mcspi3_pins: pinmux_mcspi3_pins { |
| 161 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 162 | 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ |
| 163 | 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ |
| 164 | 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ |
| 165 | 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 166 | >; |
| 167 | }; |
| 168 | |
| 169 | mcspi4_pins: pinmux_mcspi4_pins { |
| 170 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 171 | 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ |
| 172 | 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ |
| 173 | 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ |
| 174 | 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 175 | >; |
| 176 | }; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 177 | |
| 178 | usbhost_pins: pinmux_usbhost_pins { |
| 179 | pinctrl-single,pins = < |
| 180 | 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ |
| 181 | 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ |
| 182 | |
| 183 | 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ |
| 184 | 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ |
| 185 | |
| 186 | 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ |
| 187 | 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ |
| 188 | >; |
| 189 | }; |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 190 | |
| 191 | led_gpio_pins: pinmux_led_gpio_pins { |
| 192 | pinctrl-single,pins = < |
| 193 | 0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ |
| 194 | >; |
| 195 | }; |
Sourav Poddar | ed22fee | 2013-06-07 18:52:50 +0530 | [diff] [blame] | 196 | |
| 197 | uart1_pins: pinmux_uart1_pins { |
| 198 | pinctrl-single,pins = < |
| 199 | 0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ |
| 200 | 0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ |
| 201 | 0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ |
| 202 | 0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ |
| 203 | >; |
| 204 | }; |
| 205 | |
| 206 | uart3_pins: pinmux_uart3_pins { |
| 207 | pinctrl-single,pins = < |
| 208 | 0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ |
| 209 | 0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ |
| 210 | >; |
| 211 | }; |
| 212 | |
| 213 | uart5_pins: pinmux_uart5_pins { |
| 214 | pinctrl-single,pins = < |
| 215 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ |
| 216 | 0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ |
| 217 | 0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ |
| 218 | 0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ |
| 219 | >; |
| 220 | }; |
| 221 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 222 | }; |
| 223 | |
| 224 | &omap5_pmx_wkup { |
| 225 | pinctrl-names = "default"; |
| 226 | pinctrl-0 = < |
| 227 | &usbhost_wkup_pins |
| 228 | >; |
| 229 | |
| 230 | usbhost_wkup_pins: pinmux_usbhost_wkup_pins { |
| 231 | pinctrl-single,pins = < |
| 232 | 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ |
| 233 | >; |
| 234 | }; |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 235 | }; |
| 236 | |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 237 | &mmc1 { |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 238 | vmmc-supply = <&ldo9_reg>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 239 | bus-width = <4>; |
| 240 | }; |
| 241 | |
| 242 | &mmc2 { |
| 243 | vmmc-supply = <&vmmcsd_fixed>; |
| 244 | bus-width = <8>; |
| 245 | ti,non-removable; |
| 246 | }; |
| 247 | |
| 248 | &mmc3 { |
| 249 | bus-width = <4>; |
| 250 | ti,non-removable; |
| 251 | }; |
| 252 | |
| 253 | &mmc4 { |
| 254 | status = "disabled"; |
| 255 | }; |
| 256 | |
| 257 | &mmc5 { |
| 258 | status = "disabled"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 259 | }; |
Sourav Poddar | 08f3e21 | 2012-07-25 11:02:43 +0530 | [diff] [blame] | 260 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 261 | &i2c1 { |
| 262 | pinctrl-names = "default"; |
| 263 | pinctrl-0 = <&i2c1_pins>; |
| 264 | |
| 265 | clock-frequency = <400000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 266 | |
| 267 | palmas: palmas@48 { |
| 268 | compatible = "ti,palmas"; |
| 269 | interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
| 270 | interrupt-parent = <&gic>; |
| 271 | reg = <0x48>; |
| 272 | interrupt-controller; |
| 273 | #interrupt-cells = <2>; |
| 274 | |
| 275 | palmas_pmic { |
| 276 | compatible = "ti,palmas-pmic"; |
| 277 | interrupt-parent = <&palmas>; |
| 278 | interrupts = <14 IRQ_TYPE_NONE>; |
| 279 | interrupt-name = "short-irq"; |
| 280 | |
| 281 | ti,ldo6-vibrator; |
| 282 | |
| 283 | regulators { |
| 284 | smps123_reg: smps123 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 285 | /* VDD_OPP_MPU */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 286 | regulator-name = "smps123"; |
| 287 | regulator-min-microvolt = < 600000>; |
| 288 | regulator-max-microvolt = <1500000>; |
| 289 | regulator-always-on; |
| 290 | regulator-boot-on; |
| 291 | }; |
| 292 | |
| 293 | smps45_reg: smps45 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 294 | /* VDD_OPP_MM */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 295 | regulator-name = "smps45"; |
| 296 | regulator-min-microvolt = < 600000>; |
| 297 | regulator-max-microvolt = <1310000>; |
| 298 | regulator-always-on; |
| 299 | regulator-boot-on; |
| 300 | }; |
| 301 | |
| 302 | smps6_reg: smps6 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 303 | /* VDD_DDR3 - over VDD_SMPS6 */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 304 | regulator-name = "smps6"; |
| 305 | regulator-min-microvolt = <1200000>; |
| 306 | regulator-max-microvolt = <1200000>; |
| 307 | regulator-always-on; |
| 308 | regulator-boot-on; |
| 309 | }; |
| 310 | |
| 311 | smps7_reg: smps7 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 312 | /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 313 | regulator-name = "smps7"; |
| 314 | regulator-min-microvolt = <1800000>; |
| 315 | regulator-max-microvolt = <1800000>; |
| 316 | regulator-always-on; |
| 317 | regulator-boot-on; |
| 318 | }; |
| 319 | |
| 320 | smps8_reg: smps8 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 321 | /* VDD_OPP_CORE */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 322 | regulator-name = "smps8"; |
| 323 | regulator-min-microvolt = < 600000>; |
| 324 | regulator-max-microvolt = <1310000>; |
| 325 | regulator-always-on; |
| 326 | regulator-boot-on; |
| 327 | }; |
| 328 | |
| 329 | smps9_reg: smps9 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 330 | /* VDDA_2v1_AUD over VDD_2v1 */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 331 | regulator-name = "smps9"; |
| 332 | regulator-min-microvolt = <2100000>; |
| 333 | regulator-max-microvolt = <2100000>; |
| 334 | regulator-always-on; |
| 335 | regulator-boot-on; |
| 336 | ti,smps-range = <0x80>; |
| 337 | }; |
| 338 | |
| 339 | smps10_reg: smps10 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 340 | /* VBUS_5V_OTG */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 341 | regulator-name = "smps10"; |
| 342 | regulator-min-microvolt = <5000000>; |
| 343 | regulator-max-microvolt = <5000000>; |
| 344 | regulator-always-on; |
| 345 | regulator-boot-on; |
| 346 | }; |
| 347 | |
| 348 | ldo1_reg: ldo1 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 349 | /* VDDAPHY_CAM: vdda_csiport */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 350 | regulator-name = "ldo1"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 351 | regulator-min-microvolt = <1500000>; |
| 352 | regulator-max-microvolt = <1800000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | ldo2_reg: ldo2 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 356 | /* VCC_2V8_DISP: Does not go anywhere */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 357 | regulator-name = "ldo2"; |
| 358 | regulator-min-microvolt = <2900000>; |
| 359 | regulator-max-microvolt = <2900000>; |
| 360 | regulator-always-on; |
| 361 | regulator-boot-on; |
| 362 | }; |
| 363 | |
| 364 | ldo3_reg: ldo3 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 365 | /* VDDAPHY_MDM: vdda_lli */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 366 | regulator-name = "ldo3"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 367 | regulator-min-microvolt = <1500000>; |
| 368 | regulator-max-microvolt = <1500000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 369 | regulator-boot-on; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 370 | /* Only if Modem is used */ |
| 371 | status = "disabled"; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 372 | }; |
| 373 | |
| 374 | ldo4_reg: ldo4 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 375 | /* VDDAPHY_DISP: vdda_dsiport/hdmi */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 376 | regulator-name = "ldo4"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 377 | regulator-min-microvolt = <1500000>; |
| 378 | regulator-max-microvolt = <1800000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 379 | }; |
| 380 | |
| 381 | ldo5_reg: ldo5 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 382 | /* VDDA_1V8_PHY: usb/sata/hdmi.. */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 383 | regulator-name = "ldo5"; |
| 384 | regulator-min-microvolt = <1800000>; |
| 385 | regulator-max-microvolt = <1800000>; |
| 386 | regulator-always-on; |
| 387 | regulator-boot-on; |
| 388 | }; |
| 389 | |
| 390 | ldo6_reg: ldo6 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 391 | /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 392 | regulator-name = "ldo6"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 393 | regulator-min-microvolt = <1200000>; |
| 394 | regulator-max-microvolt = <1200000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 395 | regulator-always-on; |
| 396 | regulator-boot-on; |
| 397 | }; |
| 398 | |
| 399 | ldo7_reg: ldo7 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 400 | /* VDD_VPP: vpp1 */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 401 | regulator-name = "ldo7"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 402 | regulator-min-microvolt = <2000000>; |
| 403 | regulator-max-microvolt = <2000000>; |
| 404 | /* Only for efuse reprograming! */ |
| 405 | status = "disabled"; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 406 | }; |
| 407 | |
| 408 | ldo8_reg: ldo8 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 409 | /* VDD_3v0: Does not go anywhere */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 410 | regulator-name = "ldo8"; |
| 411 | regulator-min-microvolt = <1500000>; |
| 412 | regulator-max-microvolt = <1500000>; |
| 413 | regulator-always-on; |
| 414 | regulator-boot-on; |
| 415 | }; |
| 416 | |
| 417 | ldo9_reg: ldo9 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 418 | /* VCC_DV_SDIO: vdds_sdcard */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 419 | regulator-name = "ldo9"; |
| 420 | regulator-min-microvolt = <1800000>; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 421 | regulator-max-microvolt = <3000000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 422 | regulator-boot-on; |
| 423 | }; |
| 424 | |
| 425 | ldoln_reg: ldoln { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 426 | /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 427 | regulator-name = "ldoln"; |
| 428 | regulator-min-microvolt = <1800000>; |
| 429 | regulator-max-microvolt = <1800000>; |
| 430 | regulator-always-on; |
| 431 | regulator-boot-on; |
| 432 | }; |
| 433 | |
| 434 | ldousb_reg: ldousb { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 435 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 436 | regulator-name = "ldousb"; |
| 437 | regulator-min-microvolt = <3250000>; |
| 438 | regulator-max-microvolt = <3250000>; |
| 439 | regulator-always-on; |
| 440 | regulator-boot-on; |
| 441 | }; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame^] | 442 | |
| 443 | regen3_reg: regen3 { |
| 444 | /* REGEN3 controls LDO9 supply to card */ |
| 445 | regulator-name = "regen3"; |
| 446 | regulator-always-on; |
| 447 | regulator-boot-on; |
| 448 | }; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 449 | }; |
| 450 | }; |
| 451 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 452 | }; |
| 453 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 454 | &i2c5 { |
| 455 | pinctrl-names = "default"; |
| 456 | pinctrl-0 = <&i2c5_pins>; |
| 457 | |
| 458 | clock-frequency = <400000>; |
| 459 | }; |
| 460 | |
Peter Ujfalusi | 42601d5 | 2012-10-04 14:57:24 +0300 | [diff] [blame] | 461 | &mcbsp3 { |
| 462 | status = "disabled"; |
| 463 | }; |
Lokesh Vutla | 4d2750f | 2012-11-05 18:22:52 +0530 | [diff] [blame] | 464 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 465 | &usbhshost { |
| 466 | port2-mode = "ehci-hsic"; |
| 467 | port3-mode = "ehci-hsic"; |
| 468 | }; |
| 469 | |
| 470 | &usbhsehci { |
| 471 | phys = <0 &hsusb2_phy &hsusb3_phy>; |
| 472 | }; |
| 473 | |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 474 | &mcspi1 { |
| 475 | |
| 476 | }; |
| 477 | |
| 478 | &mcspi2 { |
| 479 | pinctrl-names = "default"; |
| 480 | pinctrl-0 = <&mcspi2_pins>; |
| 481 | }; |
| 482 | |
| 483 | &mcspi3 { |
| 484 | pinctrl-names = "default"; |
| 485 | pinctrl-0 = <&mcspi3_pins>; |
| 486 | }; |
| 487 | |
| 488 | &mcspi4 { |
| 489 | pinctrl-names = "default"; |
| 490 | pinctrl-0 = <&mcspi4_pins>; |
| 491 | }; |
Sourav Poddar | ed22fee | 2013-06-07 18:52:50 +0530 | [diff] [blame] | 492 | |
| 493 | &uart1 { |
| 494 | pinctrl-names = "default"; |
| 495 | pinctrl-0 = <&uart1_pins>; |
| 496 | }; |
| 497 | |
| 498 | &uart3 { |
| 499 | pinctrl-names = "default"; |
| 500 | pinctrl-0 = <&uart3_pins>; |
| 501 | }; |
| 502 | |
| 503 | &uart5 { |
| 504 | pinctrl-names = "default"; |
| 505 | pinctrl-0 = <&uart5_pins>; |
| 506 | }; |