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Yuval Mintz32a47e72016-05-11 16:36:12 +03001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintz32a47e72016-05-11 16:36:12 +03003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintz32a47e72016-05-11 16:36:12 +030031 */
32
Yuval Mintzdacd88d2016-05-11 16:36:16 +030033#include <linux/etherdevice.h>
Yuval Mintz36558c32016-05-11 16:36:17 +030034#include <linux/crc32.h>
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +020035#include <linux/vmalloc.h>
Yuval Mintz0b55e272016-05-11 16:36:15 +030036#include <linux/qed/qed_iov_if.h>
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030037#include "qed_cxt.h"
38#include "qed_hsi.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030039#include "qed_hw.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030040#include "qed_init_ops.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030041#include "qed_int.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030042#include "qed_mcp.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030043#include "qed_reg_addr.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030044#include "qed_sp.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030045#include "qed_sriov.h"
46#include "qed_vf.h"
47
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030048/* IOV ramrods */
Yuval Mintz1fe614d2016-06-05 13:11:11 +030049static int qed_sp_vf_start(struct qed_hwfn *p_hwfn, struct qed_vf_info *p_vf)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030050{
51 struct vf_start_ramrod_data *p_ramrod = NULL;
52 struct qed_spq_entry *p_ent = NULL;
53 struct qed_sp_init_data init_data;
54 int rc = -EINVAL;
Yuval Mintz1fe614d2016-06-05 13:11:11 +030055 u8 fp_minor;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030056
57 /* Get SPQ entry */
58 memset(&init_data, 0, sizeof(init_data));
59 init_data.cid = qed_spq_get_cid(p_hwfn);
Yuval Mintz1fe614d2016-06-05 13:11:11 +030060 init_data.opaque_fid = p_vf->opaque_fid;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030061 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
62
63 rc = qed_sp_init_request(p_hwfn, &p_ent,
64 COMMON_RAMROD_VF_START,
65 PROTOCOLID_COMMON, &init_data);
66 if (rc)
67 return rc;
68
69 p_ramrod = &p_ent->ramrod.vf_start;
70
Yuval Mintz1fe614d2016-06-05 13:11:11 +030071 p_ramrod->vf_id = GET_FIELD(p_vf->concrete_fid, PXP_CONCRETE_FID_VFID);
72 p_ramrod->opaque_fid = cpu_to_le16(p_vf->opaque_fid);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030073
Yuval Mintz1fe614d2016-06-05 13:11:11 +030074 switch (p_hwfn->hw_info.personality) {
75 case QED_PCI_ETH:
76 p_ramrod->personality = PERSONALITY_ETH;
77 break;
78 case QED_PCI_ETH_ROCE:
79 p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
80 break;
81 default:
82 DP_NOTICE(p_hwfn, "Unknown VF personality %d\n",
83 p_hwfn->hw_info.personality);
84 return -EINVAL;
85 }
86
87 fp_minor = p_vf->acquire.vfdev_info.eth_fp_hsi_minor;
Yuval Mintza044df82016-08-22 13:25:09 +030088 if (fp_minor > ETH_HSI_VER_MINOR &&
89 fp_minor != ETH_HSI_VER_NO_PKT_LEN_TUNN) {
Yuval Mintz1fe614d2016-06-05 13:11:11 +030090 DP_VERBOSE(p_hwfn,
91 QED_MSG_IOV,
92 "VF [%d] - Requested fp hsi %02x.%02x which is slightly newer than PF's %02x.%02x; Configuring PFs version\n",
93 p_vf->abs_vf_id,
94 ETH_HSI_VER_MAJOR,
95 fp_minor, ETH_HSI_VER_MAJOR, ETH_HSI_VER_MINOR);
96 fp_minor = ETH_HSI_VER_MINOR;
97 }
98
Yuval Mintz351a4ded2016-06-02 10:23:29 +030099 p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
Yuval Mintz1fe614d2016-06-05 13:11:11 +0300100 p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = fp_minor;
101
102 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
103 "VF[%d] - Starting using HSI %02x.%02x\n",
104 p_vf->abs_vf_id, ETH_HSI_VER_MAJOR, fp_minor);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300105
106 return qed_spq_post(p_hwfn, p_ent, NULL);
107}
108
Yuval Mintz0b55e272016-05-11 16:36:15 +0300109static int qed_sp_vf_stop(struct qed_hwfn *p_hwfn,
110 u32 concrete_vfid, u16 opaque_vfid)
111{
112 struct vf_stop_ramrod_data *p_ramrod = NULL;
113 struct qed_spq_entry *p_ent = NULL;
114 struct qed_sp_init_data init_data;
115 int rc = -EINVAL;
116
117 /* Get SPQ entry */
118 memset(&init_data, 0, sizeof(init_data));
119 init_data.cid = qed_spq_get_cid(p_hwfn);
120 init_data.opaque_fid = opaque_vfid;
121 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
122
123 rc = qed_sp_init_request(p_hwfn, &p_ent,
124 COMMON_RAMROD_VF_STOP,
125 PROTOCOLID_COMMON, &init_data);
126 if (rc)
127 return rc;
128
129 p_ramrod = &p_ent->ramrod.vf_stop;
130
131 p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
132
133 return qed_spq_post(p_hwfn, p_ent, NULL);
134}
135
Baoyou Xieba569472016-09-09 09:21:15 +0800136static bool qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400137 int rel_vf_id,
138 bool b_enabled_only, bool b_non_malicious)
Yuval Mintz32a47e72016-05-11 16:36:12 +0300139{
140 if (!p_hwfn->pf_iov_info) {
141 DP_NOTICE(p_hwfn->cdev, "No iov info\n");
142 return false;
143 }
144
145 if ((rel_vf_id >= p_hwfn->cdev->p_iov_info->total_vfs) ||
146 (rel_vf_id < 0))
147 return false;
148
149 if ((!p_hwfn->pf_iov_info->vfs_array[rel_vf_id].b_init) &&
150 b_enabled_only)
151 return false;
152
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400153 if ((p_hwfn->pf_iov_info->vfs_array[rel_vf_id].b_malicious) &&
154 b_non_malicious)
155 return false;
156
Yuval Mintz32a47e72016-05-11 16:36:12 +0300157 return true;
158}
159
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300160static struct qed_vf_info *qed_iov_get_vf_info(struct qed_hwfn *p_hwfn,
161 u16 relative_vf_id,
162 bool b_enabled_only)
163{
164 struct qed_vf_info *vf = NULL;
165
166 if (!p_hwfn->pf_iov_info) {
167 DP_NOTICE(p_hwfn->cdev, "No iov info\n");
168 return NULL;
169 }
170
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400171 if (qed_iov_is_valid_vfid(p_hwfn, relative_vf_id,
172 b_enabled_only, false))
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300173 vf = &p_hwfn->pf_iov_info->vfs_array[relative_vf_id];
174 else
175 DP_ERR(p_hwfn, "qed_iov_get_vf_info: VF[%d] is not enabled\n",
176 relative_vf_id);
177
178 return vf;
179}
180
Mintz, Yuvalf109c242017-03-19 13:08:16 +0200181enum qed_iov_validate_q_mode {
182 QED_IOV_VALIDATE_Q_NA,
183 QED_IOV_VALIDATE_Q_ENABLE,
184 QED_IOV_VALIDATE_Q_DISABLE,
185};
186
187static bool qed_iov_validate_queue_mode(struct qed_hwfn *p_hwfn,
188 struct qed_vf_info *p_vf,
189 u16 qid,
190 enum qed_iov_validate_q_mode mode,
191 bool b_is_tx)
Yuval Mintz41086462016-06-05 13:11:13 +0300192{
Mintz, Yuvalf109c242017-03-19 13:08:16 +0200193 if (mode == QED_IOV_VALIDATE_Q_NA)
194 return true;
195
196 if ((b_is_tx && p_vf->vf_queues[qid].p_tx_cid) ||
197 (!b_is_tx && p_vf->vf_queues[qid].p_rx_cid))
198 return mode == QED_IOV_VALIDATE_Q_ENABLE;
199
200 /* In case we haven't found any valid cid, then its disabled */
201 return mode == QED_IOV_VALIDATE_Q_DISABLE;
202}
203
204static bool qed_iov_validate_rxq(struct qed_hwfn *p_hwfn,
205 struct qed_vf_info *p_vf,
206 u16 rx_qid,
207 enum qed_iov_validate_q_mode mode)
208{
209 if (rx_qid >= p_vf->num_rxqs) {
Yuval Mintz41086462016-06-05 13:11:13 +0300210 DP_VERBOSE(p_hwfn,
211 QED_MSG_IOV,
212 "VF[0x%02x] - can't touch Rx queue[%04x]; Only 0x%04x are allocated\n",
213 p_vf->abs_vf_id, rx_qid, p_vf->num_rxqs);
Mintz, Yuvalf109c242017-03-19 13:08:16 +0200214 return false;
215 }
216
217 return qed_iov_validate_queue_mode(p_hwfn, p_vf, rx_qid, mode, false);
Yuval Mintz41086462016-06-05 13:11:13 +0300218}
219
220static bool qed_iov_validate_txq(struct qed_hwfn *p_hwfn,
Mintz, Yuvalf109c242017-03-19 13:08:16 +0200221 struct qed_vf_info *p_vf,
222 u16 tx_qid,
223 enum qed_iov_validate_q_mode mode)
Yuval Mintz41086462016-06-05 13:11:13 +0300224{
Mintz, Yuvalf109c242017-03-19 13:08:16 +0200225 if (tx_qid >= p_vf->num_txqs) {
Yuval Mintz41086462016-06-05 13:11:13 +0300226 DP_VERBOSE(p_hwfn,
227 QED_MSG_IOV,
228 "VF[0x%02x] - can't touch Tx queue[%04x]; Only 0x%04x are allocated\n",
229 p_vf->abs_vf_id, tx_qid, p_vf->num_txqs);
Mintz, Yuvalf109c242017-03-19 13:08:16 +0200230 return false;
231 }
232
233 return qed_iov_validate_queue_mode(p_hwfn, p_vf, tx_qid, mode, true);
Yuval Mintz41086462016-06-05 13:11:13 +0300234}
235
236static bool qed_iov_validate_sb(struct qed_hwfn *p_hwfn,
237 struct qed_vf_info *p_vf, u16 sb_idx)
238{
239 int i;
240
241 for (i = 0; i < p_vf->num_sbs; i++)
242 if (p_vf->igu_sbs[i] == sb_idx)
243 return true;
244
245 DP_VERBOSE(p_hwfn,
246 QED_MSG_IOV,
247 "VF[0%02x] - tried using sb_idx %04x which doesn't exist as one of its 0x%02x SBs\n",
248 p_vf->abs_vf_id, sb_idx, p_vf->num_sbs);
249
250 return false;
251}
252
Mintz, Yuvalf109c242017-03-19 13:08:16 +0200253static bool qed_iov_validate_active_rxq(struct qed_hwfn *p_hwfn,
254 struct qed_vf_info *p_vf)
255{
256 u8 i;
257
258 for (i = 0; i < p_vf->num_rxqs; i++)
259 if (qed_iov_validate_queue_mode(p_hwfn, p_vf, i,
260 QED_IOV_VALIDATE_Q_ENABLE,
261 false))
262 return true;
263
264 return false;
265}
266
267static bool qed_iov_validate_active_txq(struct qed_hwfn *p_hwfn,
268 struct qed_vf_info *p_vf)
269{
270 u8 i;
271
272 for (i = 0; i < p_vf->num_txqs; i++)
273 if (qed_iov_validate_queue_mode(p_hwfn, p_vf, i,
274 QED_IOV_VALIDATE_Q_ENABLE,
275 true))
276 return true;
277
278 return false;
279}
280
Baoyou Xieba569472016-09-09 09:21:15 +0800281static int qed_iov_post_vf_bulletin(struct qed_hwfn *p_hwfn,
282 int vfid, struct qed_ptt *p_ptt)
Yuval Mintz36558c32016-05-11 16:36:17 +0300283{
284 struct qed_bulletin_content *p_bulletin;
285 int crc_size = sizeof(p_bulletin->crc);
286 struct qed_dmae_params params;
287 struct qed_vf_info *p_vf;
288
289 p_vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
290 if (!p_vf)
291 return -EINVAL;
292
293 if (!p_vf->vf_bulletin)
294 return -EINVAL;
295
296 p_bulletin = p_vf->bulletin.p_virt;
297
298 /* Increment bulletin board version and compute crc */
299 p_bulletin->version++;
300 p_bulletin->crc = crc32(0, (u8 *)p_bulletin + crc_size,
301 p_vf->bulletin.size - crc_size);
302
303 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
304 "Posting Bulletin 0x%08x to VF[%d] (CRC 0x%08x)\n",
305 p_bulletin->version, p_vf->relative_vf_id, p_bulletin->crc);
306
307 /* propagate bulletin board via dmae to vm memory */
308 memset(&params, 0, sizeof(params));
309 params.flags = QED_DMAE_FLAG_VF_DST;
310 params.dst_vfid = p_vf->abs_vf_id;
311 return qed_dmae_host2host(p_hwfn, p_ptt, p_vf->bulletin.phys,
312 p_vf->vf_bulletin, p_vf->bulletin.size / 4,
313 &params);
314}
315
Yuval Mintz32a47e72016-05-11 16:36:12 +0300316static int qed_iov_pci_cfg_info(struct qed_dev *cdev)
317{
318 struct qed_hw_sriov_info *iov = cdev->p_iov_info;
319 int pos = iov->pos;
320
321 DP_VERBOSE(cdev, QED_MSG_IOV, "sriov ext pos %d\n", pos);
322 pci_read_config_word(cdev->pdev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
323
324 pci_read_config_word(cdev->pdev,
325 pos + PCI_SRIOV_TOTAL_VF, &iov->total_vfs);
326 pci_read_config_word(cdev->pdev,
327 pos + PCI_SRIOV_INITIAL_VF, &iov->initial_vfs);
328
329 pci_read_config_word(cdev->pdev, pos + PCI_SRIOV_NUM_VF, &iov->num_vfs);
330 if (iov->num_vfs) {
331 DP_VERBOSE(cdev,
332 QED_MSG_IOV,
333 "Number of VFs are already set to non-zero value. Ignoring PCI configuration value\n");
334 iov->num_vfs = 0;
335 }
336
337 pci_read_config_word(cdev->pdev,
338 pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
339
340 pci_read_config_word(cdev->pdev,
341 pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
342
343 pci_read_config_word(cdev->pdev,
344 pos + PCI_SRIOV_VF_DID, &iov->vf_device_id);
345
346 pci_read_config_dword(cdev->pdev,
347 pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
348
349 pci_read_config_dword(cdev->pdev, pos + PCI_SRIOV_CAP, &iov->cap);
350
351 pci_read_config_byte(cdev->pdev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
352
353 DP_VERBOSE(cdev,
354 QED_MSG_IOV,
355 "IOV info: nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
356 iov->nres,
357 iov->cap,
358 iov->ctrl,
359 iov->total_vfs,
360 iov->initial_vfs,
361 iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
362
363 /* Some sanity checks */
364 if (iov->num_vfs > NUM_OF_VFS(cdev) ||
365 iov->total_vfs > NUM_OF_VFS(cdev)) {
366 /* This can happen only due to a bug. In this case we set
367 * num_vfs to zero to avoid memory corruption in the code that
368 * assumes max number of vfs
369 */
370 DP_NOTICE(cdev,
371 "IOV: Unexpected number of vfs set: %d setting num_vf to zero\n",
372 iov->num_vfs);
373
374 iov->num_vfs = 0;
375 iov->total_vfs = 0;
376 }
377
378 return 0;
379}
380
381static void qed_iov_clear_vf_igu_blocks(struct qed_hwfn *p_hwfn,
382 struct qed_ptt *p_ptt)
383{
384 struct qed_igu_block *p_sb;
385 u16 sb_id;
386 u32 val;
387
388 if (!p_hwfn->hw_info.p_igu_info) {
389 DP_ERR(p_hwfn,
390 "qed_iov_clear_vf_igu_blocks IGU Info not initialized\n");
391 return;
392 }
393
394 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
395 sb_id++) {
396 p_sb = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
397 if ((p_sb->status & QED_IGU_STATUS_FREE) &&
398 !(p_sb->status & QED_IGU_STATUS_PF)) {
399 val = qed_rd(p_hwfn, p_ptt,
400 IGU_REG_MAPPING_MEMORY + sb_id * 4);
401 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0);
402 qed_wr(p_hwfn, p_ptt,
403 IGU_REG_MAPPING_MEMORY + 4 * sb_id, val);
404 }
405 }
406}
407
408static void qed_iov_setup_vfdb(struct qed_hwfn *p_hwfn)
409{
410 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
411 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
412 struct qed_bulletin_content *p_bulletin_virt;
413 dma_addr_t req_p, rply_p, bulletin_p;
414 union pfvf_tlvs *p_reply_virt_addr;
415 union vfpf_tlvs *p_req_virt_addr;
416 u8 idx = 0;
417
418 memset(p_iov_info->vfs_array, 0, sizeof(p_iov_info->vfs_array));
419
420 p_req_virt_addr = p_iov_info->mbx_msg_virt_addr;
421 req_p = p_iov_info->mbx_msg_phys_addr;
422 p_reply_virt_addr = p_iov_info->mbx_reply_virt_addr;
423 rply_p = p_iov_info->mbx_reply_phys_addr;
424 p_bulletin_virt = p_iov_info->p_bulletins;
425 bulletin_p = p_iov_info->bulletins_phys;
426 if (!p_req_virt_addr || !p_reply_virt_addr || !p_bulletin_virt) {
427 DP_ERR(p_hwfn,
428 "qed_iov_setup_vfdb called without allocating mem first\n");
429 return;
430 }
431
432 for (idx = 0; idx < p_iov->total_vfs; idx++) {
433 struct qed_vf_info *vf = &p_iov_info->vfs_array[idx];
434 u32 concrete;
435
436 vf->vf_mbx.req_virt = p_req_virt_addr + idx;
437 vf->vf_mbx.req_phys = req_p + idx * sizeof(union vfpf_tlvs);
438 vf->vf_mbx.reply_virt = p_reply_virt_addr + idx;
439 vf->vf_mbx.reply_phys = rply_p + idx * sizeof(union pfvf_tlvs);
440
441 vf->state = VF_STOPPED;
442 vf->b_init = false;
443
444 vf->bulletin.phys = idx *
445 sizeof(struct qed_bulletin_content) +
446 bulletin_p;
447 vf->bulletin.p_virt = p_bulletin_virt + idx;
448 vf->bulletin.size = sizeof(struct qed_bulletin_content);
449
450 vf->relative_vf_id = idx;
451 vf->abs_vf_id = idx + p_iov->first_vf_in_pf;
452 concrete = qed_vfid_to_concrete(p_hwfn, vf->abs_vf_id);
453 vf->concrete_fid = concrete;
454 vf->opaque_fid = (p_hwfn->hw_info.opaque_fid & 0xff) |
455 (vf->abs_vf_id << 8);
456 vf->vport_id = idx + 1;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300457
458 vf->num_mac_filters = QED_ETH_VF_NUM_MAC_FILTERS;
459 vf->num_vlan_filters = QED_ETH_VF_NUM_VLAN_FILTERS;
Yuval Mintz32a47e72016-05-11 16:36:12 +0300460 }
461}
462
463static int qed_iov_allocate_vfdb(struct qed_hwfn *p_hwfn)
464{
465 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
466 void **p_v_addr;
467 u16 num_vfs = 0;
468
469 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
470
471 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
472 "qed_iov_allocate_vfdb for %d VFs\n", num_vfs);
473
474 /* Allocate PF Mailbox buffer (per-VF) */
475 p_iov_info->mbx_msg_size = sizeof(union vfpf_tlvs) * num_vfs;
476 p_v_addr = &p_iov_info->mbx_msg_virt_addr;
477 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
478 p_iov_info->mbx_msg_size,
479 &p_iov_info->mbx_msg_phys_addr,
480 GFP_KERNEL);
481 if (!*p_v_addr)
482 return -ENOMEM;
483
484 /* Allocate PF Mailbox Reply buffer (per-VF) */
485 p_iov_info->mbx_reply_size = sizeof(union pfvf_tlvs) * num_vfs;
486 p_v_addr = &p_iov_info->mbx_reply_virt_addr;
487 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
488 p_iov_info->mbx_reply_size,
489 &p_iov_info->mbx_reply_phys_addr,
490 GFP_KERNEL);
491 if (!*p_v_addr)
492 return -ENOMEM;
493
494 p_iov_info->bulletins_size = sizeof(struct qed_bulletin_content) *
495 num_vfs;
496 p_v_addr = &p_iov_info->p_bulletins;
497 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
498 p_iov_info->bulletins_size,
499 &p_iov_info->bulletins_phys,
500 GFP_KERNEL);
501 if (!*p_v_addr)
502 return -ENOMEM;
503
504 DP_VERBOSE(p_hwfn,
505 QED_MSG_IOV,
506 "PF's Requests mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys] Bulletins [%p virt 0x%llx phys]\n",
507 p_iov_info->mbx_msg_virt_addr,
508 (u64) p_iov_info->mbx_msg_phys_addr,
509 p_iov_info->mbx_reply_virt_addr,
510 (u64) p_iov_info->mbx_reply_phys_addr,
511 p_iov_info->p_bulletins, (u64) p_iov_info->bulletins_phys);
512
513 return 0;
514}
515
516static void qed_iov_free_vfdb(struct qed_hwfn *p_hwfn)
517{
518 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
519
520 if (p_hwfn->pf_iov_info->mbx_msg_virt_addr)
521 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
522 p_iov_info->mbx_msg_size,
523 p_iov_info->mbx_msg_virt_addr,
524 p_iov_info->mbx_msg_phys_addr);
525
526 if (p_hwfn->pf_iov_info->mbx_reply_virt_addr)
527 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
528 p_iov_info->mbx_reply_size,
529 p_iov_info->mbx_reply_virt_addr,
530 p_iov_info->mbx_reply_phys_addr);
531
532 if (p_iov_info->p_bulletins)
533 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
534 p_iov_info->bulletins_size,
535 p_iov_info->p_bulletins,
536 p_iov_info->bulletins_phys);
537}
538
539int qed_iov_alloc(struct qed_hwfn *p_hwfn)
540{
541 struct qed_pf_iov *p_sriov;
542
543 if (!IS_PF_SRIOV(p_hwfn)) {
544 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
545 "No SR-IOV - no need for IOV db\n");
546 return 0;
547 }
548
549 p_sriov = kzalloc(sizeof(*p_sriov), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700550 if (!p_sriov)
Yuval Mintz32a47e72016-05-11 16:36:12 +0300551 return -ENOMEM;
Yuval Mintz32a47e72016-05-11 16:36:12 +0300552
553 p_hwfn->pf_iov_info = p_sriov;
554
555 return qed_iov_allocate_vfdb(p_hwfn);
556}
557
558void qed_iov_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
559{
560 if (!IS_PF_SRIOV(p_hwfn) || !IS_PF_SRIOV_ALLOC(p_hwfn))
561 return;
562
563 qed_iov_setup_vfdb(p_hwfn);
564 qed_iov_clear_vf_igu_blocks(p_hwfn, p_ptt);
565}
566
567void qed_iov_free(struct qed_hwfn *p_hwfn)
568{
569 if (IS_PF_SRIOV_ALLOC(p_hwfn)) {
570 qed_iov_free_vfdb(p_hwfn);
571 kfree(p_hwfn->pf_iov_info);
572 }
573}
574
575void qed_iov_free_hw_info(struct qed_dev *cdev)
576{
577 kfree(cdev->p_iov_info);
578 cdev->p_iov_info = NULL;
579}
580
581int qed_iov_hw_info(struct qed_hwfn *p_hwfn)
582{
583 struct qed_dev *cdev = p_hwfn->cdev;
584 int pos;
585 int rc;
586
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300587 if (IS_VF(p_hwfn->cdev))
588 return 0;
589
Yuval Mintz32a47e72016-05-11 16:36:12 +0300590 /* Learn the PCI configuration */
591 pos = pci_find_ext_capability(p_hwfn->cdev->pdev,
592 PCI_EXT_CAP_ID_SRIOV);
593 if (!pos) {
594 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "No PCIe IOV support\n");
595 return 0;
596 }
597
598 /* Allocate a new struct for IOV information */
599 cdev->p_iov_info = kzalloc(sizeof(*cdev->p_iov_info), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700600 if (!cdev->p_iov_info)
Yuval Mintz32a47e72016-05-11 16:36:12 +0300601 return -ENOMEM;
Joe Perches2591c282016-09-04 14:24:03 -0700602
Yuval Mintz32a47e72016-05-11 16:36:12 +0300603 cdev->p_iov_info->pos = pos;
604
605 rc = qed_iov_pci_cfg_info(cdev);
606 if (rc)
607 return rc;
608
609 /* We want PF IOV to be synonemous with the existance of p_iov_info;
610 * In case the capability is published but there are no VFs, simply
611 * de-allocate the struct.
612 */
613 if (!cdev->p_iov_info->total_vfs) {
614 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
615 "IOV capabilities, but no VFs are published\n");
616 kfree(cdev->p_iov_info);
617 cdev->p_iov_info = NULL;
618 return 0;
619 }
620
Mintz, Yuval9c79dda2017-03-14 16:23:54 +0200621 /* First VF index based on offset is tricky:
622 * - If ARI is supported [likely], offset - (16 - pf_id) would
623 * provide the number for eng0. 2nd engine Vfs would begin
624 * after the first engine's VFs.
625 * - If !ARI, VFs would start on next device.
626 * so offset - (256 - pf_id) would provide the number.
627 * Utilize the fact that (256 - pf_id) is achieved only by later
628 * to diffrentiate between the two.
Yuval Mintz32a47e72016-05-11 16:36:12 +0300629 */
Mintz, Yuval9c79dda2017-03-14 16:23:54 +0200630
631 if (p_hwfn->cdev->p_iov_info->offset < (256 - p_hwfn->abs_pf_id)) {
632 u32 first = p_hwfn->cdev->p_iov_info->offset +
633 p_hwfn->abs_pf_id - 16;
634
635 cdev->p_iov_info->first_vf_in_pf = first;
636
637 if (QED_PATH_ID(p_hwfn))
638 cdev->p_iov_info->first_vf_in_pf -= MAX_NUM_VFS_BB;
639 } else {
640 u32 first = p_hwfn->cdev->p_iov_info->offset +
641 p_hwfn->abs_pf_id - 256;
642
643 cdev->p_iov_info->first_vf_in_pf = first;
644 }
Yuval Mintz32a47e72016-05-11 16:36:12 +0300645
646 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
647 "First VF in hwfn 0x%08x\n",
648 cdev->p_iov_info->first_vf_in_pf);
649
650 return 0;
651}
652
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400653bool _qed_iov_pf_sanity_check(struct qed_hwfn *p_hwfn,
654 int vfid, bool b_fail_malicious)
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300655{
656 /* Check PF supports sriov */
Yuval Mintzb0409fa2016-05-15 14:48:05 +0300657 if (IS_VF(p_hwfn->cdev) || !IS_QED_SRIOV(p_hwfn->cdev) ||
658 !IS_PF_SRIOV_ALLOC(p_hwfn))
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300659 return false;
660
661 /* Check VF validity */
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400662 if (!qed_iov_is_valid_vfid(p_hwfn, vfid, true, b_fail_malicious))
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300663 return false;
664
665 return true;
666}
667
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400668bool qed_iov_pf_sanity_check(struct qed_hwfn *p_hwfn, int vfid)
669{
670 return _qed_iov_pf_sanity_check(p_hwfn, vfid, true);
671}
672
Yuval Mintz0b55e272016-05-11 16:36:15 +0300673static void qed_iov_set_vf_to_disable(struct qed_dev *cdev,
674 u16 rel_vf_id, u8 to_disable)
675{
676 struct qed_vf_info *vf;
677 int i;
678
679 for_each_hwfn(cdev, i) {
680 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
681
682 vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, false);
683 if (!vf)
684 continue;
685
686 vf->to_disable = to_disable;
687 }
688}
689
Baoyou Xieba569472016-09-09 09:21:15 +0800690static void qed_iov_set_vfs_to_disable(struct qed_dev *cdev, u8 to_disable)
Yuval Mintz0b55e272016-05-11 16:36:15 +0300691{
692 u16 i;
693
694 if (!IS_QED_SRIOV(cdev))
695 return;
696
697 for (i = 0; i < cdev->p_iov_info->total_vfs; i++)
698 qed_iov_set_vf_to_disable(cdev, i, to_disable);
699}
700
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300701static void qed_iov_vf_pglue_clear_err(struct qed_hwfn *p_hwfn,
702 struct qed_ptt *p_ptt, u8 abs_vfid)
703{
704 qed_wr(p_hwfn, p_ptt,
705 PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR + (abs_vfid >> 5) * 4,
706 1 << (abs_vfid & 0x1f));
707}
708
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300709static void qed_iov_vf_igu_reset(struct qed_hwfn *p_hwfn,
710 struct qed_ptt *p_ptt, struct qed_vf_info *vf)
711{
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300712 int i;
713
714 /* Set VF masks and configuration - pretend */
715 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
716
717 qed_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_VF_MSG_SENT, 0);
718
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300719 /* unpretend */
720 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
721
722 /* iterate over all queues, clear sb consumer */
Yuval Mintzb2b897e2016-05-15 14:48:06 +0300723 for (i = 0; i < vf->num_sbs; i++)
724 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
725 vf->igu_sbs[i],
726 vf->opaque_fid, true);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300727}
728
Yuval Mintz0b55e272016-05-11 16:36:15 +0300729static void qed_iov_vf_igu_set_int(struct qed_hwfn *p_hwfn,
730 struct qed_ptt *p_ptt,
731 struct qed_vf_info *vf, bool enable)
732{
733 u32 igu_vf_conf;
734
735 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
736
737 igu_vf_conf = qed_rd(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION);
738
739 if (enable)
740 igu_vf_conf |= IGU_VF_CONF_MSI_MSIX_EN;
741 else
742 igu_vf_conf &= ~IGU_VF_CONF_MSI_MSIX_EN;
743
744 qed_wr(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION, igu_vf_conf);
745
746 /* unpretend */
747 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
748}
749
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300750static int qed_iov_enable_vf_access(struct qed_hwfn *p_hwfn,
751 struct qed_ptt *p_ptt,
752 struct qed_vf_info *vf)
753{
754 u32 igu_vf_conf = IGU_VF_CONF_FUNC_EN;
755 int rc;
756
Mintz, Yuval4e9b2a62017-03-19 13:08:13 +0200757 /* It's possible VF was previously considered malicious -
758 * clear the indication even if we're only going to disable VF.
759 */
760 vf->b_malicious = false;
761
Yuval Mintz0b55e272016-05-11 16:36:15 +0300762 if (vf->to_disable)
763 return 0;
764
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300765 DP_VERBOSE(p_hwfn,
766 QED_MSG_IOV,
767 "Enable internal access for vf %x [abs %x]\n",
768 vf->abs_vf_id, QED_VF_ABS_ID(p_hwfn, vf));
769
770 qed_iov_vf_pglue_clear_err(p_hwfn, p_ptt, QED_VF_ABS_ID(p_hwfn, vf));
771
Yuval Mintzb2b897e2016-05-15 14:48:06 +0300772 qed_iov_vf_igu_reset(p_hwfn, p_ptt, vf);
773
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300774 rc = qed_mcp_config_vf_msix(p_hwfn, p_ptt, vf->abs_vf_id, vf->num_sbs);
775 if (rc)
776 return rc;
777
778 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
779
780 SET_FIELD(igu_vf_conf, IGU_VF_CONF_PARENT, p_hwfn->rel_pf_id);
781 STORE_RT_REG(p_hwfn, IGU_REG_VF_CONFIGURATION_RT_OFFSET, igu_vf_conf);
782
783 qed_init_run(p_hwfn, p_ptt, PHASE_VF, vf->abs_vf_id,
784 p_hwfn->hw_info.hw_mode);
785
786 /* unpretend */
787 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
788
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300789 vf->state = VF_FREE;
790
791 return rc;
792}
793
Yuval Mintz0b55e272016-05-11 16:36:15 +0300794/**
795 * @brief qed_iov_config_perm_table - configure the permission
796 * zone table.
797 * In E4, queue zone permission table size is 320x9. There
798 * are 320 VF queues for single engine device (256 for dual
799 * engine device), and each entry has the following format:
800 * {Valid, VF[7:0]}
801 * @param p_hwfn
802 * @param p_ptt
803 * @param vf
804 * @param enable
805 */
806static void qed_iov_config_perm_table(struct qed_hwfn *p_hwfn,
807 struct qed_ptt *p_ptt,
808 struct qed_vf_info *vf, u8 enable)
809{
810 u32 reg_addr, val;
811 u16 qzone_id = 0;
812 int qid;
813
814 for (qid = 0; qid < vf->num_rxqs; qid++) {
815 qed_fw_l2_queue(p_hwfn, vf->vf_queues[qid].fw_rx_qid,
816 &qzone_id);
817
818 reg_addr = PSWHST_REG_ZONE_PERMISSION_TABLE + qzone_id * 4;
Yuval Mintz1a635e42016-08-15 10:42:43 +0300819 val = enable ? (vf->abs_vf_id | BIT(8)) : 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +0300820 qed_wr(p_hwfn, p_ptt, reg_addr, val);
821 }
822}
823
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300824static void qed_iov_enable_vf_traffic(struct qed_hwfn *p_hwfn,
825 struct qed_ptt *p_ptt,
826 struct qed_vf_info *vf)
827{
828 /* Reset vf in IGU - interrupts are still disabled */
829 qed_iov_vf_igu_reset(p_hwfn, p_ptt, vf);
830
831 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 1);
832
833 /* Permission Table */
834 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, true);
835}
836
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300837static u8 qed_iov_alloc_vf_igu_sbs(struct qed_hwfn *p_hwfn,
838 struct qed_ptt *p_ptt,
839 struct qed_vf_info *vf, u16 num_rx_queues)
840{
841 struct qed_igu_block *igu_blocks;
842 int qid = 0, igu_id = 0;
843 u32 val = 0;
844
845 igu_blocks = p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks;
846
847 if (num_rx_queues > p_hwfn->hw_info.p_igu_info->free_blks)
848 num_rx_queues = p_hwfn->hw_info.p_igu_info->free_blks;
849 p_hwfn->hw_info.p_igu_info->free_blks -= num_rx_queues;
850
851 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, vf->abs_vf_id);
852 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 1);
853 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, 0);
854
855 while ((qid < num_rx_queues) &&
856 (igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev))) {
857 if (igu_blocks[igu_id].status & QED_IGU_STATUS_FREE) {
858 struct cau_sb_entry sb_entry;
859
860 vf->igu_sbs[qid] = (u16)igu_id;
861 igu_blocks[igu_id].status &= ~QED_IGU_STATUS_FREE;
862
863 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, qid);
864
865 qed_wr(p_hwfn, p_ptt,
866 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_id,
867 val);
868
869 /* Configure igu sb in CAU which were marked valid */
870 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
871 p_hwfn->rel_pf_id,
872 vf->abs_vf_id, 1);
873 qed_dmae_host2grc(p_hwfn, p_ptt,
874 (u64)(uintptr_t)&sb_entry,
875 CAU_REG_SB_VAR_MEMORY +
876 igu_id * sizeof(u64), 2, 0);
877 qid++;
878 }
879 igu_id++;
880 }
881
882 vf->num_sbs = (u8) num_rx_queues;
883
884 return vf->num_sbs;
885}
886
Yuval Mintz0b55e272016-05-11 16:36:15 +0300887static void qed_iov_free_vf_igu_sbs(struct qed_hwfn *p_hwfn,
888 struct qed_ptt *p_ptt,
889 struct qed_vf_info *vf)
890{
891 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
892 int idx, igu_id;
893 u32 addr, val;
894
895 /* Invalidate igu CAM lines and mark them as free */
896 for (idx = 0; idx < vf->num_sbs; idx++) {
897 igu_id = vf->igu_sbs[idx];
898 addr = IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_id;
899
900 val = qed_rd(p_hwfn, p_ptt, addr);
901 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0);
902 qed_wr(p_hwfn, p_ptt, addr, val);
903
904 p_info->igu_map.igu_blocks[igu_id].status |=
905 QED_IGU_STATUS_FREE;
906
907 p_hwfn->hw_info.p_igu_info->free_blks++;
908 }
909
910 vf->num_sbs = 0;
911}
912
Mintz, Yuval33b2fbd2017-02-20 22:43:36 +0200913static void qed_iov_set_link(struct qed_hwfn *p_hwfn,
914 u16 vfid,
915 struct qed_mcp_link_params *params,
916 struct qed_mcp_link_state *link,
917 struct qed_mcp_link_capabilities *p_caps)
918{
919 struct qed_vf_info *p_vf = qed_iov_get_vf_info(p_hwfn,
920 vfid,
921 false);
922 struct qed_bulletin_content *p_bulletin;
923
924 if (!p_vf)
925 return;
926
927 p_bulletin = p_vf->bulletin.p_virt;
928 p_bulletin->req_autoneg = params->speed.autoneg;
929 p_bulletin->req_adv_speed = params->speed.advertised_speeds;
930 p_bulletin->req_forced_speed = params->speed.forced_speed;
931 p_bulletin->req_autoneg_pause = params->pause.autoneg;
932 p_bulletin->req_forced_rx = params->pause.forced_rx;
933 p_bulletin->req_forced_tx = params->pause.forced_tx;
934 p_bulletin->req_loopback = params->loopback_mode;
935
936 p_bulletin->link_up = link->link_up;
937 p_bulletin->speed = link->speed;
938 p_bulletin->full_duplex = link->full_duplex;
939 p_bulletin->autoneg = link->an;
940 p_bulletin->autoneg_complete = link->an_complete;
941 p_bulletin->parallel_detection = link->parallel_detection;
942 p_bulletin->pfc_enabled = link->pfc_enabled;
943 p_bulletin->partner_adv_speed = link->partner_adv_speed;
944 p_bulletin->partner_tx_flow_ctrl_en = link->partner_tx_flow_ctrl_en;
945 p_bulletin->partner_rx_flow_ctrl_en = link->partner_rx_flow_ctrl_en;
946 p_bulletin->partner_adv_pause = link->partner_adv_pause;
947 p_bulletin->sfp_tx_fault = link->sfp_tx_fault;
948
949 p_bulletin->capability_speed = p_caps->speed_capabilities;
950}
951
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300952static int qed_iov_init_hw_for_vf(struct qed_hwfn *p_hwfn,
953 struct qed_ptt *p_ptt,
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200954 struct qed_iov_vf_init_params *p_params)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300955{
Mintz, Yuval33b2fbd2017-02-20 22:43:36 +0200956 struct qed_mcp_link_capabilities link_caps;
957 struct qed_mcp_link_params link_params;
958 struct qed_mcp_link_state link_state;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300959 u8 num_of_vf_avaiable_chains = 0;
960 struct qed_vf_info *vf = NULL;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200961 u16 qid, num_irqs;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300962 int rc = 0;
963 u32 cids;
964 u8 i;
965
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200966 vf = qed_iov_get_vf_info(p_hwfn, p_params->rel_vf_id, false);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300967 if (!vf) {
968 DP_ERR(p_hwfn, "qed_iov_init_hw_for_vf : vf is NULL\n");
969 return -EINVAL;
970 }
971
972 if (vf->b_init) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200973 DP_NOTICE(p_hwfn, "VF[%d] is already active.\n",
974 p_params->rel_vf_id);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300975 return -EINVAL;
976 }
977
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200978 /* Perform sanity checking on the requested queue_id */
979 for (i = 0; i < p_params->num_queues; i++) {
980 u16 min_vf_qzone = FEAT_NUM(p_hwfn, QED_PF_L2_QUE);
981 u16 max_vf_qzone = min_vf_qzone +
982 FEAT_NUM(p_hwfn, QED_VF_L2_QUE) - 1;
983
984 qid = p_params->req_rx_queue[i];
985 if (qid < min_vf_qzone || qid > max_vf_qzone) {
986 DP_NOTICE(p_hwfn,
987 "Can't enable Rx qid [%04x] for VF[%d]: qids [0x%04x,...,0x%04x] available\n",
988 qid,
989 p_params->rel_vf_id,
990 min_vf_qzone, max_vf_qzone);
991 return -EINVAL;
992 }
993
994 qid = p_params->req_tx_queue[i];
995 if (qid > max_vf_qzone) {
996 DP_NOTICE(p_hwfn,
997 "Can't enable Tx qid [%04x] for VF[%d]: max qid 0x%04x\n",
998 qid, p_params->rel_vf_id, max_vf_qzone);
999 return -EINVAL;
1000 }
1001
1002 /* If client *really* wants, Tx qid can be shared with PF */
1003 if (qid < min_vf_qzone)
1004 DP_VERBOSE(p_hwfn,
1005 QED_MSG_IOV,
1006 "VF[%d] is using PF qid [0x%04x] for Txq[0x%02x]\n",
1007 p_params->rel_vf_id, qid, i);
1008 }
1009
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001010 /* Limit number of queues according to number of CIDs */
1011 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, &cids);
1012 DP_VERBOSE(p_hwfn,
1013 QED_MSG_IOV,
1014 "VF[%d] - requesting to initialize for 0x%04x queues [0x%04x CIDs available]\n",
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001015 vf->relative_vf_id, p_params->num_queues, (u16)cids);
1016 num_irqs = min_t(u16, p_params->num_queues, ((u16)cids));
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001017
1018 num_of_vf_avaiable_chains = qed_iov_alloc_vf_igu_sbs(p_hwfn,
1019 p_ptt,
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001020 vf, num_irqs);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001021 if (!num_of_vf_avaiable_chains) {
1022 DP_ERR(p_hwfn, "no available igu sbs\n");
1023 return -ENOMEM;
1024 }
1025
1026 /* Choose queue number and index ranges */
1027 vf->num_rxqs = num_of_vf_avaiable_chains;
1028 vf->num_txqs = num_of_vf_avaiable_chains;
1029
1030 for (i = 0; i < vf->num_rxqs; i++) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001031 struct qed_vf_q_info *p_queue = &vf->vf_queues[i];
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001032
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001033 p_queue->fw_rx_qid = p_params->req_rx_queue[i];
1034 p_queue->fw_tx_qid = p_params->req_tx_queue[i];
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001035
1036 /* CIDs are per-VF, so no problem having them 0-based. */
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001037 p_queue->fw_cid = i;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001038
1039 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001040 "VF[%d] - Q[%d] SB %04x, qid [Rx %04x Tx %04x] CID %04x\n",
1041 vf->relative_vf_id,
1042 i, vf->igu_sbs[i],
1043 p_queue->fw_rx_qid,
1044 p_queue->fw_tx_qid, p_queue->fw_cid);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001045 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001046
Mintz, Yuval33b2fbd2017-02-20 22:43:36 +02001047 /* Update the link configuration in bulletin */
1048 memcpy(&link_params, qed_mcp_get_link_params(p_hwfn),
1049 sizeof(link_params));
1050 memcpy(&link_state, qed_mcp_get_link_state(p_hwfn), sizeof(link_state));
1051 memcpy(&link_caps, qed_mcp_get_link_capabilities(p_hwfn),
1052 sizeof(link_caps));
1053 qed_iov_set_link(p_hwfn, p_params->rel_vf_id,
1054 &link_params, &link_state, &link_caps);
1055
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001056 rc = qed_iov_enable_vf_access(p_hwfn, p_ptt, vf);
1057 if (!rc) {
1058 vf->b_init = true;
1059
1060 if (IS_LEAD_HWFN(p_hwfn))
1061 p_hwfn->cdev->p_iov_info->num_vfs++;
1062 }
1063
1064 return rc;
1065}
1066
Yuval Mintz0b55e272016-05-11 16:36:15 +03001067static int qed_iov_release_hw_for_vf(struct qed_hwfn *p_hwfn,
1068 struct qed_ptt *p_ptt, u16 rel_vf_id)
1069{
Manish Chopra079d20a2016-05-15 14:48:07 +03001070 struct qed_mcp_link_capabilities caps;
1071 struct qed_mcp_link_params params;
1072 struct qed_mcp_link_state link;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001073 struct qed_vf_info *vf = NULL;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001074
1075 vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
1076 if (!vf) {
1077 DP_ERR(p_hwfn, "qed_iov_release_hw_for_vf : vf is NULL\n");
1078 return -EINVAL;
1079 }
1080
Yuval Mintz36558c32016-05-11 16:36:17 +03001081 if (vf->bulletin.p_virt)
1082 memset(vf->bulletin.p_virt, 0, sizeof(*vf->bulletin.p_virt));
1083
1084 memset(&vf->p_vf_info, 0, sizeof(vf->p_vf_info));
1085
Manish Chopra079d20a2016-05-15 14:48:07 +03001086 /* Get the link configuration back in bulletin so
1087 * that when VFs are re-enabled they get the actual
1088 * link configuration.
1089 */
1090 memcpy(&params, qed_mcp_get_link_params(p_hwfn), sizeof(params));
1091 memcpy(&link, qed_mcp_get_link_state(p_hwfn), sizeof(link));
1092 memcpy(&caps, qed_mcp_get_link_capabilities(p_hwfn), sizeof(caps));
1093 qed_iov_set_link(p_hwfn, rel_vf_id, &params, &link, &caps);
1094
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001095 /* Forget the VF's acquisition message */
1096 memset(&vf->acquire, 0, sizeof(vf->acquire));
Yuval Mintz0b55e272016-05-11 16:36:15 +03001097
1098 /* disablng interrupts and resetting permission table was done during
1099 * vf-close, however, we could get here without going through vf_close
1100 */
1101 /* Disable Interrupts for VF */
1102 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 0);
1103
1104 /* Reset Permission table */
1105 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, 0);
1106
1107 vf->num_rxqs = 0;
1108 vf->num_txqs = 0;
1109 qed_iov_free_vf_igu_sbs(p_hwfn, p_ptt, vf);
1110
1111 if (vf->b_init) {
1112 vf->b_init = false;
1113
1114 if (IS_LEAD_HWFN(p_hwfn))
1115 p_hwfn->cdev->p_iov_info->num_vfs--;
1116 }
1117
1118 return 0;
1119}
1120
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001121static bool qed_iov_tlv_supported(u16 tlvtype)
1122{
1123 return CHANNEL_TLV_NONE < tlvtype && tlvtype < CHANNEL_TLV_MAX;
1124}
1125
1126/* place a given tlv on the tlv buffer, continuing current tlv list */
1127void *qed_add_tlv(struct qed_hwfn *p_hwfn, u8 **offset, u16 type, u16 length)
1128{
1129 struct channel_tlv *tl = (struct channel_tlv *)*offset;
1130
1131 tl->type = type;
1132 tl->length = length;
1133
1134 /* Offset should keep pointing to next TLV (the end of the last) */
1135 *offset += length;
1136
1137 /* Return a pointer to the start of the added tlv */
1138 return *offset - length;
1139}
1140
1141/* list the types and lengths of the tlvs on the buffer */
1142void qed_dp_tlv_list(struct qed_hwfn *p_hwfn, void *tlvs_list)
1143{
1144 u16 i = 1, total_length = 0;
1145 struct channel_tlv *tlv;
1146
1147 do {
1148 tlv = (struct channel_tlv *)((u8 *)tlvs_list + total_length);
1149
1150 /* output tlv */
1151 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1152 "TLV number %d: type %d, length %d\n",
1153 i, tlv->type, tlv->length);
1154
1155 if (tlv->type == CHANNEL_TLV_LIST_END)
1156 return;
1157
1158 /* Validate entry - protect against malicious VFs */
1159 if (!tlv->length) {
1160 DP_NOTICE(p_hwfn, "TLV of length 0 found\n");
1161 return;
1162 }
1163
1164 total_length += tlv->length;
1165
1166 if (total_length >= sizeof(struct tlv_buffer_size)) {
1167 DP_NOTICE(p_hwfn, "TLV ==> Buffer overflow\n");
1168 return;
1169 }
1170
1171 i++;
1172 } while (1);
1173}
1174
1175static void qed_iov_send_response(struct qed_hwfn *p_hwfn,
1176 struct qed_ptt *p_ptt,
1177 struct qed_vf_info *p_vf,
1178 u16 length, u8 status)
1179{
1180 struct qed_iov_vf_mbx *mbx = &p_vf->vf_mbx;
1181 struct qed_dmae_params params;
1182 u8 eng_vf_id;
1183
1184 mbx->reply_virt->default_resp.hdr.status = status;
1185
1186 qed_dp_tlv_list(p_hwfn, mbx->reply_virt);
1187
1188 eng_vf_id = p_vf->abs_vf_id;
1189
1190 memset(&params, 0, sizeof(struct qed_dmae_params));
1191 params.flags = QED_DMAE_FLAG_VF_DST;
1192 params.dst_vfid = eng_vf_id;
1193
1194 qed_dmae_host2host(p_hwfn, p_ptt, mbx->reply_phys + sizeof(u64),
1195 mbx->req_virt->first_tlv.reply_address +
1196 sizeof(u64),
1197 (sizeof(union pfvf_tlvs) - sizeof(u64)) / 4,
1198 &params);
1199
Mintz, Yuvald9194082017-03-19 13:08:14 +02001200 /* Once PF copies the rc to the VF, the latter can continue
1201 * and send an additional message. So we have to make sure the
1202 * channel would be re-set to ready prior to that.
1203 */
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001204 REG_WR(p_hwfn,
1205 GTT_BAR0_MAP_REG_USDM_RAM +
1206 USTORM_VF_PF_CHANNEL_READY_OFFSET(eng_vf_id), 1);
Mintz, Yuvald9194082017-03-19 13:08:14 +02001207
1208 qed_dmae_host2host(p_hwfn, p_ptt, mbx->reply_phys,
1209 mbx->req_virt->first_tlv.reply_address,
1210 sizeof(u64) / 4, &params);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001211}
1212
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001213static u16 qed_iov_vport_to_tlv(struct qed_hwfn *p_hwfn,
1214 enum qed_iov_vport_update_flag flag)
1215{
1216 switch (flag) {
1217 case QED_IOV_VP_UPDATE_ACTIVATE:
1218 return CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
Yuval Mintz17b235c2016-05-11 16:36:18 +03001219 case QED_IOV_VP_UPDATE_VLAN_STRIP:
1220 return CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP;
1221 case QED_IOV_VP_UPDATE_TX_SWITCH:
1222 return CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001223 case QED_IOV_VP_UPDATE_MCAST:
1224 return CHANNEL_TLV_VPORT_UPDATE_MCAST;
1225 case QED_IOV_VP_UPDATE_ACCEPT_PARAM:
1226 return CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
1227 case QED_IOV_VP_UPDATE_RSS:
1228 return CHANNEL_TLV_VPORT_UPDATE_RSS;
Yuval Mintz17b235c2016-05-11 16:36:18 +03001229 case QED_IOV_VP_UPDATE_ACCEPT_ANY_VLAN:
1230 return CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
1231 case QED_IOV_VP_UPDATE_SGE_TPA:
1232 return CHANNEL_TLV_VPORT_UPDATE_SGE_TPA;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001233 default:
1234 return 0;
1235 }
1236}
1237
1238static u16 qed_iov_prep_vp_update_resp_tlvs(struct qed_hwfn *p_hwfn,
1239 struct qed_vf_info *p_vf,
1240 struct qed_iov_vf_mbx *p_mbx,
1241 u8 status,
1242 u16 tlvs_mask, u16 tlvs_accepted)
1243{
1244 struct pfvf_def_resp_tlv *resp;
1245 u16 size, total_len, i;
1246
1247 memset(p_mbx->reply_virt, 0, sizeof(union pfvf_tlvs));
1248 p_mbx->offset = (u8 *)p_mbx->reply_virt;
1249 size = sizeof(struct pfvf_def_resp_tlv);
1250 total_len = size;
1251
1252 qed_add_tlv(p_hwfn, &p_mbx->offset, CHANNEL_TLV_VPORT_UPDATE, size);
1253
1254 /* Prepare response for all extended tlvs if they are found by PF */
1255 for (i = 0; i < QED_IOV_VP_UPDATE_MAX; i++) {
Yuval Mintz1a635e42016-08-15 10:42:43 +03001256 if (!(tlvs_mask & BIT(i)))
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001257 continue;
1258
1259 resp = qed_add_tlv(p_hwfn, &p_mbx->offset,
1260 qed_iov_vport_to_tlv(p_hwfn, i), size);
1261
Yuval Mintz1a635e42016-08-15 10:42:43 +03001262 if (tlvs_accepted & BIT(i))
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001263 resp->hdr.status = status;
1264 else
1265 resp->hdr.status = PFVF_STATUS_NOT_SUPPORTED;
1266
1267 DP_VERBOSE(p_hwfn,
1268 QED_MSG_IOV,
1269 "VF[%d] - vport_update response: TLV %d, status %02x\n",
1270 p_vf->relative_vf_id,
1271 qed_iov_vport_to_tlv(p_hwfn, i), resp->hdr.status);
1272
1273 total_len += size;
1274 }
1275
1276 qed_add_tlv(p_hwfn, &p_mbx->offset, CHANNEL_TLV_LIST_END,
1277 sizeof(struct channel_list_end_tlv));
1278
1279 return total_len;
1280}
1281
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001282static void qed_iov_prepare_resp(struct qed_hwfn *p_hwfn,
1283 struct qed_ptt *p_ptt,
1284 struct qed_vf_info *vf_info,
1285 u16 type, u16 length, u8 status)
1286{
1287 struct qed_iov_vf_mbx *mbx = &vf_info->vf_mbx;
1288
1289 mbx->offset = (u8 *)mbx->reply_virt;
1290
1291 qed_add_tlv(p_hwfn, &mbx->offset, type, length);
1292 qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_LIST_END,
1293 sizeof(struct channel_list_end_tlv));
1294
1295 qed_iov_send_response(p_hwfn, p_ptt, vf_info, length, status);
1296}
1297
Baoyou Xieba569472016-09-09 09:21:15 +08001298static struct
1299qed_public_vf_info *qed_iov_get_public_vf_info(struct qed_hwfn *p_hwfn,
1300 u16 relative_vf_id,
1301 bool b_enabled_only)
Yuval Mintz0b55e272016-05-11 16:36:15 +03001302{
1303 struct qed_vf_info *vf = NULL;
1304
1305 vf = qed_iov_get_vf_info(p_hwfn, relative_vf_id, b_enabled_only);
1306 if (!vf)
1307 return NULL;
1308
1309 return &vf->p_vf_info;
1310}
1311
Baoyou Xieba569472016-09-09 09:21:15 +08001312static void qed_iov_clean_vf(struct qed_hwfn *p_hwfn, u8 vfid)
Yuval Mintz0b55e272016-05-11 16:36:15 +03001313{
1314 struct qed_public_vf_info *vf_info;
1315
1316 vf_info = qed_iov_get_public_vf_info(p_hwfn, vfid, false);
1317
1318 if (!vf_info)
1319 return;
1320
1321 /* Clear the VF mac */
Shyam Saini0ee28e32017-01-17 07:35:04 +05301322 eth_zero_addr(vf_info->mac);
Mintz, Yuvalf990c822017-01-01 13:57:08 +02001323
1324 vf_info->rx_accept_mode = 0;
1325 vf_info->tx_accept_mode = 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001326}
1327
1328static void qed_iov_vf_cleanup(struct qed_hwfn *p_hwfn,
1329 struct qed_vf_info *p_vf)
1330{
1331 u32 i;
1332
1333 p_vf->vf_bulletin = 0;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001334 p_vf->vport_instance = 0;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001335 p_vf->configured_features = 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001336
1337 /* If VF previously requested less resources, go back to default */
1338 p_vf->num_rxqs = p_vf->num_sbs;
1339 p_vf->num_txqs = p_vf->num_sbs;
1340
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001341 p_vf->num_active_rxqs = 0;
1342
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001343 for (i = 0; i < QED_MAX_VF_CHAINS_PER_PF; i++) {
1344 struct qed_vf_q_info *p_queue = &p_vf->vf_queues[i];
1345
1346 if (p_queue->p_rx_cid) {
1347 qed_eth_queue_cid_release(p_hwfn, p_queue->p_rx_cid);
1348 p_queue->p_rx_cid = NULL;
1349 }
1350
1351 if (p_queue->p_tx_cid) {
1352 qed_eth_queue_cid_release(p_hwfn, p_queue->p_tx_cid);
1353 p_queue->p_tx_cid = NULL;
1354 }
1355 }
Yuval Mintz0b55e272016-05-11 16:36:15 +03001356
Yuval Mintz08feecd2016-05-11 16:36:20 +03001357 memset(&p_vf->shadow_config, 0, sizeof(p_vf->shadow_config));
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001358 memset(&p_vf->acquire, 0, sizeof(p_vf->acquire));
Yuval Mintz0b55e272016-05-11 16:36:15 +03001359 qed_iov_clean_vf(p_hwfn, p_vf->relative_vf_id);
1360}
1361
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001362static u8 qed_iov_vf_mbx_acquire_resc(struct qed_hwfn *p_hwfn,
1363 struct qed_ptt *p_ptt,
1364 struct qed_vf_info *p_vf,
1365 struct vf_pf_resc_request *p_req,
1366 struct pf_vf_resc *p_resp)
1367{
1368 int i;
1369
1370 /* Queue related information */
1371 p_resp->num_rxqs = p_vf->num_rxqs;
1372 p_resp->num_txqs = p_vf->num_txqs;
1373 p_resp->num_sbs = p_vf->num_sbs;
1374
1375 for (i = 0; i < p_resp->num_sbs; i++) {
1376 p_resp->hw_sbs[i].hw_sb_id = p_vf->igu_sbs[i];
1377 p_resp->hw_sbs[i].sb_qid = 0;
1378 }
1379
1380 /* These fields are filled for backward compatibility.
1381 * Unused by modern vfs.
1382 */
1383 for (i = 0; i < p_resp->num_rxqs; i++) {
1384 qed_fw_l2_queue(p_hwfn, p_vf->vf_queues[i].fw_rx_qid,
1385 (u16 *)&p_resp->hw_qid[i]);
1386 p_resp->cid[i] = p_vf->vf_queues[i].fw_cid;
1387 }
1388
1389 /* Filter related information */
1390 p_resp->num_mac_filters = min_t(u8, p_vf->num_mac_filters,
1391 p_req->num_mac_filters);
1392 p_resp->num_vlan_filters = min_t(u8, p_vf->num_vlan_filters,
1393 p_req->num_vlan_filters);
1394
1395 /* This isn't really needed/enforced, but some legacy VFs might depend
1396 * on the correct filling of this field.
1397 */
1398 p_resp->num_mc_filters = QED_MAX_MC_ADDRS;
1399
1400 /* Validate sufficient resources for VF */
1401 if (p_resp->num_rxqs < p_req->num_rxqs ||
1402 p_resp->num_txqs < p_req->num_txqs ||
1403 p_resp->num_sbs < p_req->num_sbs ||
1404 p_resp->num_mac_filters < p_req->num_mac_filters ||
1405 p_resp->num_vlan_filters < p_req->num_vlan_filters ||
1406 p_resp->num_mc_filters < p_req->num_mc_filters) {
1407 DP_VERBOSE(p_hwfn,
1408 QED_MSG_IOV,
1409 "VF[%d] - Insufficient resources: rxq [%02x/%02x] txq [%02x/%02x] sbs [%02x/%02x] mac [%02x/%02x] vlan [%02x/%02x] mc [%02x/%02x]\n",
1410 p_vf->abs_vf_id,
1411 p_req->num_rxqs,
1412 p_resp->num_rxqs,
1413 p_req->num_rxqs,
1414 p_resp->num_txqs,
1415 p_req->num_sbs,
1416 p_resp->num_sbs,
1417 p_req->num_mac_filters,
1418 p_resp->num_mac_filters,
1419 p_req->num_vlan_filters,
1420 p_resp->num_vlan_filters,
1421 p_req->num_mc_filters, p_resp->num_mc_filters);
Yuval Mintza044df82016-08-22 13:25:09 +03001422
1423 /* Some legacy OSes are incapable of correctly handling this
1424 * failure.
1425 */
1426 if ((p_vf->acquire.vfdev_info.eth_fp_hsi_minor ==
1427 ETH_HSI_VER_NO_PKT_LEN_TUNN) &&
1428 (p_vf->acquire.vfdev_info.os_type ==
1429 VFPF_ACQUIRE_OS_WINDOWS))
1430 return PFVF_STATUS_SUCCESS;
1431
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001432 return PFVF_STATUS_NO_RESOURCE;
1433 }
1434
1435 return PFVF_STATUS_SUCCESS;
1436}
1437
1438static void qed_iov_vf_mbx_acquire_stats(struct qed_hwfn *p_hwfn,
1439 struct pfvf_stats_info *p_stats)
1440{
1441 p_stats->mstats.address = PXP_VF_BAR0_START_MSDM_ZONE_B +
1442 offsetof(struct mstorm_vf_zone,
1443 non_trigger.eth_queue_stat);
1444 p_stats->mstats.len = sizeof(struct eth_mstorm_per_queue_stat);
1445 p_stats->ustats.address = PXP_VF_BAR0_START_USDM_ZONE_B +
1446 offsetof(struct ustorm_vf_zone,
1447 non_trigger.eth_queue_stat);
1448 p_stats->ustats.len = sizeof(struct eth_ustorm_per_queue_stat);
1449 p_stats->pstats.address = PXP_VF_BAR0_START_PSDM_ZONE_B +
1450 offsetof(struct pstorm_vf_zone,
1451 non_trigger.eth_queue_stat);
1452 p_stats->pstats.len = sizeof(struct eth_pstorm_per_queue_stat);
1453 p_stats->tstats.address = 0;
1454 p_stats->tstats.len = 0;
1455}
1456
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001457static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
1458 struct qed_ptt *p_ptt,
1459 struct qed_vf_info *vf)
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001460{
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001461 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1462 struct pfvf_acquire_resp_tlv *resp = &mbx->reply_virt->acquire_resp;
1463 struct pf_vf_pfdev_info *pfdev_info = &resp->pfdev_info;
1464 struct vfpf_acquire_tlv *req = &mbx->req_virt->acquire;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001465 u8 vfpf_status = PFVF_STATUS_NOT_SUPPORTED;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001466 struct pf_vf_resc *resc = &resp->resc;
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001467 int rc;
1468
1469 memset(resp, 0, sizeof(*resp));
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001470
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001471 /* Write the PF version so that VF would know which version
1472 * is supported - might be later overriden. This guarantees that
1473 * VF could recognize legacy PF based on lack of versions in reply.
1474 */
1475 pfdev_info->major_fp_hsi = ETH_HSI_VER_MAJOR;
1476 pfdev_info->minor_fp_hsi = ETH_HSI_VER_MINOR;
1477
Yuval Mintza044df82016-08-22 13:25:09 +03001478 if (vf->state != VF_FREE && vf->state != VF_STOPPED) {
1479 DP_VERBOSE(p_hwfn,
1480 QED_MSG_IOV,
1481 "VF[%d] sent ACQUIRE but is already in state %d - fail request\n",
1482 vf->abs_vf_id, vf->state);
1483 goto out;
1484 }
1485
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001486 /* Validate FW compatibility */
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001487 if (req->vfdev_info.eth_fp_hsi_major != ETH_HSI_VER_MAJOR) {
Yuval Mintza044df82016-08-22 13:25:09 +03001488 if (req->vfdev_info.capabilities &
1489 VFPF_ACQUIRE_CAP_PRE_FP_HSI) {
1490 struct vf_pf_vfdev_info *p_vfdev = &req->vfdev_info;
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001491
Yuval Mintza044df82016-08-22 13:25:09 +03001492 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1493 "VF[%d] is pre-fastpath HSI\n",
1494 vf->abs_vf_id);
1495 p_vfdev->eth_fp_hsi_major = ETH_HSI_VER_MAJOR;
1496 p_vfdev->eth_fp_hsi_minor = ETH_HSI_VER_NO_PKT_LEN_TUNN;
1497 } else {
1498 DP_INFO(p_hwfn,
1499 "VF[%d] needs fastpath HSI %02x.%02x, which is incompatible with loaded FW's faspath HSI %02x.%02x\n",
1500 vf->abs_vf_id,
1501 req->vfdev_info.eth_fp_hsi_major,
1502 req->vfdev_info.eth_fp_hsi_minor,
1503 ETH_HSI_VER_MAJOR, ETH_HSI_VER_MINOR);
1504
1505 goto out;
1506 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001507 }
1508
1509 /* On 100g PFs, prevent old VFs from loading */
1510 if ((p_hwfn->cdev->num_hwfns > 1) &&
1511 !(req->vfdev_info.capabilities & VFPF_ACQUIRE_CAP_100G)) {
1512 DP_INFO(p_hwfn,
1513 "VF[%d] is running an old driver that doesn't support 100g\n",
1514 vf->abs_vf_id);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001515 goto out;
1516 }
1517
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001518 /* Store the acquire message */
1519 memcpy(&vf->acquire, req, sizeof(vf->acquire));
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001520
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001521 vf->opaque_fid = req->vfdev_info.opaque_fid;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001522
1523 vf->vf_bulletin = req->bulletin_addr;
1524 vf->bulletin.size = (vf->bulletin.size < req->bulletin_size) ?
1525 vf->bulletin.size : req->bulletin_size;
1526
1527 /* fill in pfdev info */
1528 pfdev_info->chip_num = p_hwfn->cdev->chip_num;
1529 pfdev_info->db_size = 0;
1530 pfdev_info->indices_per_sb = PIS_PER_SB;
1531
1532 pfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |
1533 PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;
1534 if (p_hwfn->cdev->num_hwfns > 1)
1535 pfdev_info->capabilities |= PFVF_ACQUIRE_CAP_100G;
1536
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001537 qed_iov_vf_mbx_acquire_stats(p_hwfn, &pfdev_info->stats_info);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001538
1539 memcpy(pfdev_info->port_mac, p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
1540
1541 pfdev_info->fw_major = FW_MAJOR_VERSION;
1542 pfdev_info->fw_minor = FW_MINOR_VERSION;
1543 pfdev_info->fw_rev = FW_REVISION_VERSION;
1544 pfdev_info->fw_eng = FW_ENGINEERING_VERSION;
Yuval Mintza044df82016-08-22 13:25:09 +03001545
1546 /* Incorrect when legacy, but doesn't matter as legacy isn't reading
1547 * this field.
1548 */
Yuval Mintz1a635e42016-08-15 10:42:43 +03001549 pfdev_info->minor_fp_hsi = min_t(u8, ETH_HSI_VER_MINOR,
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001550 req->vfdev_info.eth_fp_hsi_minor);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001551 pfdev_info->os_type = VFPF_ACQUIRE_OS_LINUX;
1552 qed_mcp_get_mfw_ver(p_hwfn, p_ptt, &pfdev_info->mfw_ver, NULL);
1553
1554 pfdev_info->dev_type = p_hwfn->cdev->type;
1555 pfdev_info->chip_rev = p_hwfn->cdev->chip_rev;
1556
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001557 /* Fill resources available to VF; Make sure there are enough to
1558 * satisfy the VF's request.
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001559 */
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001560 vfpf_status = qed_iov_vf_mbx_acquire_resc(p_hwfn, p_ptt, vf,
1561 &req->resc_request, resc);
1562 if (vfpf_status != PFVF_STATUS_SUCCESS)
1563 goto out;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001564
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001565 /* Start the VF in FW */
1566 rc = qed_sp_vf_start(p_hwfn, vf);
1567 if (rc) {
1568 DP_NOTICE(p_hwfn, "Failed to start VF[%02x]\n", vf->abs_vf_id);
1569 vfpf_status = PFVF_STATUS_FAILURE;
1570 goto out;
1571 }
1572
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001573 /* Fill agreed size of bulletin board in response */
1574 resp->bulletin_size = vf->bulletin.size;
Yuval Mintz36558c32016-05-11 16:36:17 +03001575 qed_iov_post_vf_bulletin(p_hwfn, vf->relative_vf_id, p_ptt);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001576
1577 DP_VERBOSE(p_hwfn,
1578 QED_MSG_IOV,
1579 "VF[%d] ACQUIRE_RESPONSE: pfdev_info- chip_num=0x%x, db_size=%d, idx_per_sb=%d, pf_cap=0x%llx\n"
1580 "resources- n_rxq-%d, n_txq-%d, n_sbs-%d, n_macs-%d, n_vlans-%d\n",
1581 vf->abs_vf_id,
1582 resp->pfdev_info.chip_num,
1583 resp->pfdev_info.db_size,
1584 resp->pfdev_info.indices_per_sb,
1585 resp->pfdev_info.capabilities,
1586 resc->num_rxqs,
1587 resc->num_txqs,
1588 resc->num_sbs,
1589 resc->num_mac_filters,
1590 resc->num_vlan_filters);
1591 vf->state = VF_ACQUIRED;
1592
1593 /* Prepare Response */
1594out:
1595 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_ACQUIRE,
1596 sizeof(struct pfvf_acquire_resp_tlv), vfpf_status);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001597}
1598
Yuval Mintz6ddc7602016-05-11 16:36:23 +03001599static int __qed_iov_spoofchk_set(struct qed_hwfn *p_hwfn,
1600 struct qed_vf_info *p_vf, bool val)
1601{
1602 struct qed_sp_vport_update_params params;
1603 int rc;
1604
1605 if (val == p_vf->spoof_chk) {
1606 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1607 "Spoofchk value[%d] is already configured\n", val);
1608 return 0;
1609 }
1610
1611 memset(&params, 0, sizeof(struct qed_sp_vport_update_params));
1612 params.opaque_fid = p_vf->opaque_fid;
1613 params.vport_id = p_vf->vport_id;
1614 params.update_anti_spoofing_en_flg = 1;
1615 params.anti_spoofing_en = val;
1616
1617 rc = qed_sp_vport_update(p_hwfn, &params, QED_SPQ_MODE_EBLOCK, NULL);
Yuval Mintzcb1fa082016-07-27 14:45:20 +03001618 if (!rc) {
Yuval Mintz6ddc7602016-05-11 16:36:23 +03001619 p_vf->spoof_chk = val;
1620 p_vf->req_spoofchk_val = p_vf->spoof_chk;
1621 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1622 "Spoofchk val[%d] configured\n", val);
1623 } else {
1624 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1625 "Spoofchk configuration[val:%d] failed for VF[%d]\n",
1626 val, p_vf->relative_vf_id);
1627 }
1628
1629 return rc;
1630}
1631
Yuval Mintz08feecd2016-05-11 16:36:20 +03001632static int qed_iov_reconfigure_unicast_vlan(struct qed_hwfn *p_hwfn,
1633 struct qed_vf_info *p_vf)
1634{
1635 struct qed_filter_ucast filter;
1636 int rc = 0;
1637 int i;
1638
1639 memset(&filter, 0, sizeof(filter));
1640 filter.is_rx_filter = 1;
1641 filter.is_tx_filter = 1;
1642 filter.vport_to_add_to = p_vf->vport_id;
1643 filter.opcode = QED_FILTER_ADD;
1644
1645 /* Reconfigure vlans */
1646 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++) {
1647 if (!p_vf->shadow_config.vlans[i].used)
1648 continue;
1649
1650 filter.type = QED_FILTER_VLAN;
1651 filter.vlan = p_vf->shadow_config.vlans[i].vid;
Yuval Mintz1a635e42016-08-15 10:42:43 +03001652 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
Yuval Mintz08feecd2016-05-11 16:36:20 +03001653 "Reconfiguring VLAN [0x%04x] for VF [%04x]\n",
1654 filter.vlan, p_vf->relative_vf_id);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001655 rc = qed_sp_eth_filter_ucast(p_hwfn, p_vf->opaque_fid,
1656 &filter, QED_SPQ_MODE_CB, NULL);
Yuval Mintz08feecd2016-05-11 16:36:20 +03001657 if (rc) {
1658 DP_NOTICE(p_hwfn,
1659 "Failed to configure VLAN [%04x] to VF [%04x]\n",
1660 filter.vlan, p_vf->relative_vf_id);
1661 break;
1662 }
1663 }
1664
1665 return rc;
1666}
1667
1668static int
1669qed_iov_reconfigure_unicast_shadow(struct qed_hwfn *p_hwfn,
1670 struct qed_vf_info *p_vf, u64 events)
1671{
1672 int rc = 0;
1673
Yuval Mintz1a635e42016-08-15 10:42:43 +03001674 if ((events & BIT(VLAN_ADDR_FORCED)) &&
Yuval Mintz08feecd2016-05-11 16:36:20 +03001675 !(p_vf->configured_features & (1 << VLAN_ADDR_FORCED)))
1676 rc = qed_iov_reconfigure_unicast_vlan(p_hwfn, p_vf);
1677
1678 return rc;
1679}
1680
1681static int qed_iov_configure_vport_forced(struct qed_hwfn *p_hwfn,
1682 struct qed_vf_info *p_vf, u64 events)
1683{
1684 int rc = 0;
1685 struct qed_filter_ucast filter;
1686
1687 if (!p_vf->vport_instance)
1688 return -EINVAL;
1689
Yuval Mintz1a635e42016-08-15 10:42:43 +03001690 if (events & BIT(MAC_ADDR_FORCED)) {
Yuval Mintzeff16962016-05-11 16:36:21 +03001691 /* Since there's no way [currently] of removing the MAC,
1692 * we can always assume this means we need to force it.
1693 */
1694 memset(&filter, 0, sizeof(filter));
1695 filter.type = QED_FILTER_MAC;
1696 filter.opcode = QED_FILTER_REPLACE;
1697 filter.is_rx_filter = 1;
1698 filter.is_tx_filter = 1;
1699 filter.vport_to_add_to = p_vf->vport_id;
1700 ether_addr_copy(filter.mac, p_vf->bulletin.p_virt->mac);
1701
1702 rc = qed_sp_eth_filter_ucast(p_hwfn, p_vf->opaque_fid,
1703 &filter, QED_SPQ_MODE_CB, NULL);
1704 if (rc) {
1705 DP_NOTICE(p_hwfn,
1706 "PF failed to configure MAC for VF\n");
1707 return rc;
1708 }
1709
1710 p_vf->configured_features |= 1 << MAC_ADDR_FORCED;
1711 }
1712
Yuval Mintz1a635e42016-08-15 10:42:43 +03001713 if (events & BIT(VLAN_ADDR_FORCED)) {
Yuval Mintz08feecd2016-05-11 16:36:20 +03001714 struct qed_sp_vport_update_params vport_update;
1715 u8 removal;
1716 int i;
1717
1718 memset(&filter, 0, sizeof(filter));
1719 filter.type = QED_FILTER_VLAN;
1720 filter.is_rx_filter = 1;
1721 filter.is_tx_filter = 1;
1722 filter.vport_to_add_to = p_vf->vport_id;
1723 filter.vlan = p_vf->bulletin.p_virt->pvid;
1724 filter.opcode = filter.vlan ? QED_FILTER_REPLACE :
1725 QED_FILTER_FLUSH;
1726
1727 /* Send the ramrod */
1728 rc = qed_sp_eth_filter_ucast(p_hwfn, p_vf->opaque_fid,
1729 &filter, QED_SPQ_MODE_CB, NULL);
1730 if (rc) {
1731 DP_NOTICE(p_hwfn,
1732 "PF failed to configure VLAN for VF\n");
1733 return rc;
1734 }
1735
1736 /* Update the default-vlan & silent vlan stripping */
1737 memset(&vport_update, 0, sizeof(vport_update));
1738 vport_update.opaque_fid = p_vf->opaque_fid;
1739 vport_update.vport_id = p_vf->vport_id;
1740 vport_update.update_default_vlan_enable_flg = 1;
1741 vport_update.default_vlan_enable_flg = filter.vlan ? 1 : 0;
1742 vport_update.update_default_vlan_flg = 1;
1743 vport_update.default_vlan = filter.vlan;
1744
1745 vport_update.update_inner_vlan_removal_flg = 1;
1746 removal = filter.vlan ? 1
1747 : p_vf->shadow_config.inner_vlan_removal;
1748 vport_update.inner_vlan_removal_flg = removal;
1749 vport_update.silent_vlan_removal_flg = filter.vlan ? 1 : 0;
1750 rc = qed_sp_vport_update(p_hwfn,
1751 &vport_update,
1752 QED_SPQ_MODE_EBLOCK, NULL);
1753 if (rc) {
1754 DP_NOTICE(p_hwfn,
1755 "PF failed to configure VF vport for vlan\n");
1756 return rc;
1757 }
1758
1759 /* Update all the Rx queues */
1760 for (i = 0; i < QED_MAX_VF_CHAINS_PER_PF; i++) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001761 struct qed_queue_cid *p_cid;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001762
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001763 p_cid = p_vf->vf_queues[i].p_rx_cid;
1764 if (!p_cid)
Yuval Mintz08feecd2016-05-11 16:36:20 +03001765 continue;
1766
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001767 rc = qed_sp_eth_rx_queues_update(p_hwfn,
1768 (void **)&p_cid,
Yuval Mintz08feecd2016-05-11 16:36:20 +03001769 1, 0, 1,
1770 QED_SPQ_MODE_EBLOCK,
1771 NULL);
1772 if (rc) {
1773 DP_NOTICE(p_hwfn,
1774 "Failed to send Rx update fo queue[0x%04x]\n",
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001775 p_cid->rel.queue_id);
Yuval Mintz08feecd2016-05-11 16:36:20 +03001776 return rc;
1777 }
1778 }
1779
1780 if (filter.vlan)
1781 p_vf->configured_features |= 1 << VLAN_ADDR_FORCED;
1782 else
Yuval Mintz1a635e42016-08-15 10:42:43 +03001783 p_vf->configured_features &= ~BIT(VLAN_ADDR_FORCED);
Yuval Mintz08feecd2016-05-11 16:36:20 +03001784 }
1785
1786 /* If forced features are terminated, we need to configure the shadow
1787 * configuration back again.
1788 */
1789 if (events)
1790 qed_iov_reconfigure_unicast_shadow(p_hwfn, p_vf, events);
1791
1792 return rc;
1793}
1794
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001795static void qed_iov_vf_mbx_start_vport(struct qed_hwfn *p_hwfn,
1796 struct qed_ptt *p_ptt,
1797 struct qed_vf_info *vf)
1798{
1799 struct qed_sp_vport_start_params params = { 0 };
1800 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1801 struct vfpf_vport_start_tlv *start;
1802 u8 status = PFVF_STATUS_SUCCESS;
1803 struct qed_vf_info *vf_info;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001804 u64 *p_bitmap;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001805 int sb_id;
1806 int rc;
1807
1808 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vf->relative_vf_id, true);
1809 if (!vf_info) {
1810 DP_NOTICE(p_hwfn->cdev,
1811 "Failed to get VF info, invalid vfid [%d]\n",
1812 vf->relative_vf_id);
1813 return;
1814 }
1815
1816 vf->state = VF_ENABLED;
1817 start = &mbx->req_virt->start_vport;
1818
Mintz, Yuvalb801b152017-03-19 13:08:15 +02001819 qed_iov_enable_vf_traffic(p_hwfn, p_ptt, vf);
1820
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001821 /* Initialize Status block in CAU */
1822 for (sb_id = 0; sb_id < vf->num_sbs; sb_id++) {
1823 if (!start->sb_addr[sb_id]) {
1824 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1825 "VF[%d] did not fill the address of SB %d\n",
1826 vf->relative_vf_id, sb_id);
1827 break;
1828 }
1829
1830 qed_int_cau_conf_sb(p_hwfn, p_ptt,
1831 start->sb_addr[sb_id],
Yuval Mintz1a635e42016-08-15 10:42:43 +03001832 vf->igu_sbs[sb_id], vf->abs_vf_id, 1);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001833 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001834
1835 vf->mtu = start->mtu;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001836 vf->shadow_config.inner_vlan_removal = start->inner_vlan_removal;
1837
1838 /* Take into consideration configuration forced by hypervisor;
1839 * If none is configured, use the supplied VF values [for old
1840 * vfs that would still be fine, since they passed '0' as padding].
1841 */
1842 p_bitmap = &vf_info->bulletin.p_virt->valid_bitmap;
Yuval Mintz1a635e42016-08-15 10:42:43 +03001843 if (!(*p_bitmap & BIT(VFPF_BULLETIN_UNTAGGED_DEFAULT_FORCED))) {
Yuval Mintz08feecd2016-05-11 16:36:20 +03001844 u8 vf_req = start->only_untagged;
1845
1846 vf_info->bulletin.p_virt->default_only_untagged = vf_req;
1847 *p_bitmap |= 1 << VFPF_BULLETIN_UNTAGGED_DEFAULT;
1848 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001849
1850 params.tpa_mode = start->tpa_mode;
1851 params.remove_inner_vlan = start->inner_vlan_removal;
Yuval Mintz831bfb0e2016-05-11 16:36:25 +03001852 params.tx_switching = true;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001853
Yuval Mintz08feecd2016-05-11 16:36:20 +03001854 params.only_untagged = vf_info->bulletin.p_virt->default_only_untagged;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001855 params.drop_ttl0 = false;
1856 params.concrete_fid = vf->concrete_fid;
1857 params.opaque_fid = vf->opaque_fid;
1858 params.vport_id = vf->vport_id;
1859 params.max_buffers_per_cqe = start->max_buffers_per_cqe;
1860 params.mtu = vf->mtu;
Yuval Mintz11a85d72016-08-22 13:25:10 +03001861 params.check_mac = true;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001862
1863 rc = qed_sp_eth_vport_start(p_hwfn, &params);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001864 if (rc) {
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001865 DP_ERR(p_hwfn,
1866 "qed_iov_vf_mbx_start_vport returned error %d\n", rc);
1867 status = PFVF_STATUS_FAILURE;
1868 } else {
1869 vf->vport_instance++;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001870
1871 /* Force configuration if needed on the newly opened vport */
1872 qed_iov_configure_vport_forced(p_hwfn, vf, *p_bitmap);
Yuval Mintz6ddc7602016-05-11 16:36:23 +03001873
1874 __qed_iov_spoofchk_set(p_hwfn, vf, vf->req_spoofchk_val);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001875 }
1876 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_VPORT_START,
1877 sizeof(struct pfvf_def_resp_tlv), status);
1878}
1879
1880static void qed_iov_vf_mbx_stop_vport(struct qed_hwfn *p_hwfn,
1881 struct qed_ptt *p_ptt,
1882 struct qed_vf_info *vf)
1883{
1884 u8 status = PFVF_STATUS_SUCCESS;
1885 int rc;
1886
1887 vf->vport_instance--;
Yuval Mintz6ddc7602016-05-11 16:36:23 +03001888 vf->spoof_chk = false;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001889
Mintz, Yuvalf109c242017-03-19 13:08:16 +02001890 if ((qed_iov_validate_active_rxq(p_hwfn, vf)) ||
1891 (qed_iov_validate_active_txq(p_hwfn, vf))) {
1892 vf->b_malicious = true;
1893 DP_NOTICE(p_hwfn,
1894 "VF [%02x] - considered malicious; Unable to stop RX/TX queuess\n",
1895 vf->abs_vf_id);
1896 status = PFVF_STATUS_MALICIOUS;
1897 goto out;
1898 }
1899
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001900 rc = qed_sp_vport_stop(p_hwfn, vf->opaque_fid, vf->vport_id);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001901 if (rc) {
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001902 DP_ERR(p_hwfn, "qed_iov_vf_mbx_stop_vport returned error %d\n",
1903 rc);
1904 status = PFVF_STATUS_FAILURE;
1905 }
1906
Yuval Mintz08feecd2016-05-11 16:36:20 +03001907 /* Forget the configuration on the vport */
1908 vf->configured_features = 0;
1909 memset(&vf->shadow_config, 0, sizeof(vf->shadow_config));
1910
Mintz, Yuvalf109c242017-03-19 13:08:16 +02001911out:
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001912 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_VPORT_TEARDOWN,
1913 sizeof(struct pfvf_def_resp_tlv), status);
1914}
1915
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001916static void qed_iov_vf_mbx_start_rxq_resp(struct qed_hwfn *p_hwfn,
1917 struct qed_ptt *p_ptt,
Yuval Mintza044df82016-08-22 13:25:09 +03001918 struct qed_vf_info *vf,
1919 u8 status, bool b_legacy)
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001920{
1921 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1922 struct pfvf_start_queue_resp_tlv *p_tlv;
1923 struct vfpf_start_rxq_tlv *req;
Yuval Mintza044df82016-08-22 13:25:09 +03001924 u16 length;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001925
1926 mbx->offset = (u8 *)mbx->reply_virt;
1927
Yuval Mintza044df82016-08-22 13:25:09 +03001928 /* Taking a bigger struct instead of adding a TLV to list was a
1929 * mistake, but one which we're now stuck with, as some older
1930 * clients assume the size of the previous response.
1931 */
1932 if (!b_legacy)
1933 length = sizeof(*p_tlv);
1934 else
1935 length = sizeof(struct pfvf_def_resp_tlv);
1936
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001937 p_tlv = qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_START_RXQ,
Yuval Mintza044df82016-08-22 13:25:09 +03001938 length);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001939 qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_LIST_END,
1940 sizeof(struct channel_list_end_tlv));
1941
1942 /* Update the TLV with the response */
Yuval Mintza044df82016-08-22 13:25:09 +03001943 if ((status == PFVF_STATUS_SUCCESS) && !b_legacy) {
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001944 req = &mbx->req_virt->start_rxq;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001945 p_tlv->offset = PXP_VF_BAR0_START_MSDM_ZONE_B +
1946 offsetof(struct mstorm_vf_zone,
1947 non_trigger.eth_rx_queue_producers) +
1948 sizeof(struct eth_rx_prod_data) * req->rx_qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001949 }
1950
Yuval Mintza044df82016-08-22 13:25:09 +03001951 qed_iov_send_response(p_hwfn, p_ptt, vf, length, status);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001952}
1953
1954static void qed_iov_vf_mbx_start_rxq(struct qed_hwfn *p_hwfn,
1955 struct qed_ptt *p_ptt,
1956 struct qed_vf_info *vf)
1957{
1958 struct qed_queue_start_common_params params;
1959 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
Yuval Mintz41086462016-06-05 13:11:13 +03001960 u8 status = PFVF_STATUS_NO_RESOURCE;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001961 struct qed_vf_q_info *p_queue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001962 struct vfpf_start_rxq_tlv *req;
Yuval Mintza044df82016-08-22 13:25:09 +03001963 bool b_legacy_vf = false;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001964 int rc;
1965
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001966 req = &mbx->req_virt->start_rxq;
Yuval Mintz41086462016-06-05 13:11:13 +03001967
Mintz, Yuvalf109c242017-03-19 13:08:16 +02001968 if (!qed_iov_validate_rxq(p_hwfn, vf, req->rx_qid,
1969 QED_IOV_VALIDATE_Q_DISABLE) ||
Yuval Mintz41086462016-06-05 13:11:13 +03001970 !qed_iov_validate_sb(p_hwfn, vf, req->hw_sb))
1971 goto out;
1972
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001973 /* Acquire a new queue-cid */
1974 p_queue = &vf->vf_queues[req->rx_qid];
1975
1976 memset(&params, 0, sizeof(params));
1977 params.queue_id = p_queue->fw_rx_qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001978 params.vport_id = vf->vport_id;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001979 params.stats_id = vf->abs_vf_id + 0x10;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001980 params.sb = req->hw_sb;
1981 params.sb_idx = req->sb_index;
1982
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001983 p_queue->p_rx_cid = _qed_eth_queue_to_cid(p_hwfn,
1984 vf->opaque_fid,
1985 p_queue->fw_cid,
1986 req->rx_qid, &params);
1987 if (!p_queue->p_rx_cid)
1988 goto out;
1989
Yuval Mintza044df82016-08-22 13:25:09 +03001990 /* Legacy VFs have their Producers in a different location, which they
1991 * calculate on their own and clean the producer prior to this.
1992 */
1993 if (vf->acquire.vfdev_info.eth_fp_hsi_minor ==
1994 ETH_HSI_VER_NO_PKT_LEN_TUNN) {
1995 b_legacy_vf = true;
1996 } else {
1997 REG_WR(p_hwfn,
1998 GTT_BAR0_MAP_REG_MSDM_RAM +
1999 MSTORM_ETH_VF_PRODS_OFFSET(vf->abs_vf_id, req->rx_qid),
2000 0);
2001 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002002 p_queue->p_rx_cid->b_legacy_vf = b_legacy_vf;
Yuval Mintza044df82016-08-22 13:25:09 +03002003
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002004 rc = qed_eth_rxq_start_ramrod(p_hwfn,
2005 p_queue->p_rx_cid,
2006 req->bd_max_bytes,
2007 req->rxq_addr,
2008 req->cqe_pbl_addr, req->cqe_pbl_size);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002009 if (rc) {
2010 status = PFVF_STATUS_FAILURE;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002011 qed_eth_queue_cid_release(p_hwfn, p_queue->p_rx_cid);
2012 p_queue->p_rx_cid = NULL;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002013 } else {
Yuval Mintz41086462016-06-05 13:11:13 +03002014 status = PFVF_STATUS_SUCCESS;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002015 vf->num_active_rxqs++;
2016 }
2017
Yuval Mintz41086462016-06-05 13:11:13 +03002018out:
Yuval Mintza044df82016-08-22 13:25:09 +03002019 qed_iov_vf_mbx_start_rxq_resp(p_hwfn, p_ptt, vf, status, b_legacy_vf);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002020}
2021
Yuval Mintz5040acf2016-06-05 13:11:14 +03002022static void qed_iov_vf_mbx_start_txq_resp(struct qed_hwfn *p_hwfn,
2023 struct qed_ptt *p_ptt,
2024 struct qed_vf_info *p_vf, u8 status)
2025{
2026 struct qed_iov_vf_mbx *mbx = &p_vf->vf_mbx;
2027 struct pfvf_start_queue_resp_tlv *p_tlv;
Yuval Mintza044df82016-08-22 13:25:09 +03002028 bool b_legacy = false;
2029 u16 length;
Yuval Mintz5040acf2016-06-05 13:11:14 +03002030
2031 mbx->offset = (u8 *)mbx->reply_virt;
2032
Yuval Mintza044df82016-08-22 13:25:09 +03002033 /* Taking a bigger struct instead of adding a TLV to list was a
2034 * mistake, but one which we're now stuck with, as some older
2035 * clients assume the size of the previous response.
2036 */
2037 if (p_vf->acquire.vfdev_info.eth_fp_hsi_minor ==
2038 ETH_HSI_VER_NO_PKT_LEN_TUNN)
2039 b_legacy = true;
2040
2041 if (!b_legacy)
2042 length = sizeof(*p_tlv);
2043 else
2044 length = sizeof(struct pfvf_def_resp_tlv);
2045
Yuval Mintz5040acf2016-06-05 13:11:14 +03002046 p_tlv = qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_START_TXQ,
Yuval Mintza044df82016-08-22 13:25:09 +03002047 length);
Yuval Mintz5040acf2016-06-05 13:11:14 +03002048 qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_LIST_END,
2049 sizeof(struct channel_list_end_tlv));
2050
2051 /* Update the TLV with the response */
Yuval Mintza044df82016-08-22 13:25:09 +03002052 if ((status == PFVF_STATUS_SUCCESS) && !b_legacy) {
Yuval Mintz5040acf2016-06-05 13:11:14 +03002053 u16 qid = mbx->req_virt->start_txq.tx_qid;
2054
Ram Amrani51ff1722016-10-01 21:59:57 +03002055 p_tlv->offset = qed_db_addr_vf(p_vf->vf_queues[qid].fw_cid,
2056 DQ_DEMS_LEGACY);
Yuval Mintz5040acf2016-06-05 13:11:14 +03002057 }
2058
Yuval Mintza044df82016-08-22 13:25:09 +03002059 qed_iov_send_response(p_hwfn, p_ptt, p_vf, length, status);
Yuval Mintz5040acf2016-06-05 13:11:14 +03002060}
2061
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002062static void qed_iov_vf_mbx_start_txq(struct qed_hwfn *p_hwfn,
2063 struct qed_ptt *p_ptt,
2064 struct qed_vf_info *vf)
2065{
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002066 struct qed_queue_start_common_params params;
2067 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
Yuval Mintz41086462016-06-05 13:11:13 +03002068 u8 status = PFVF_STATUS_NO_RESOURCE;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002069 union qed_qm_pq_params pq_params;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002070 struct vfpf_start_txq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002071 struct qed_vf_q_info *p_queue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002072 int rc;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002073 u16 pq;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002074
2075 /* Prepare the parameters which would choose the right PQ */
2076 memset(&pq_params, 0, sizeof(pq_params));
2077 pq_params.eth.is_vf = 1;
2078 pq_params.eth.vf_id = vf->relative_vf_id;
2079
2080 memset(&params, 0, sizeof(params));
2081 req = &mbx->req_virt->start_txq;
Yuval Mintz41086462016-06-05 13:11:13 +03002082
Mintz, Yuvalf109c242017-03-19 13:08:16 +02002083 if (!qed_iov_validate_txq(p_hwfn, vf, req->tx_qid,
2084 QED_IOV_VALIDATE_Q_DISABLE) ||
Yuval Mintz41086462016-06-05 13:11:13 +03002085 !qed_iov_validate_sb(p_hwfn, vf, req->hw_sb))
2086 goto out;
2087
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002088 /* Acquire a new queue-cid */
2089 p_queue = &vf->vf_queues[req->tx_qid];
2090
2091 params.queue_id = p_queue->fw_tx_qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002092 params.vport_id = vf->vport_id;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002093 params.stats_id = vf->abs_vf_id + 0x10;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002094 params.sb = req->hw_sb;
2095 params.sb_idx = req->sb_index;
2096
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002097 p_queue->p_tx_cid = _qed_eth_queue_to_cid(p_hwfn,
2098 vf->opaque_fid,
2099 p_queue->fw_cid,
2100 req->tx_qid, &params);
2101 if (!p_queue->p_tx_cid)
2102 goto out;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002103
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002104 pq = qed_get_qm_pq(p_hwfn, PROTOCOLID_ETH, &pq_params);
2105 rc = qed_eth_txq_start_ramrod(p_hwfn, p_queue->p_tx_cid,
2106 req->pbl_addr, req->pbl_size, pq);
Yuval Mintz41086462016-06-05 13:11:13 +03002107 if (rc) {
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002108 status = PFVF_STATUS_FAILURE;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002109 qed_eth_queue_cid_release(p_hwfn, p_queue->p_tx_cid);
2110 p_queue->p_tx_cid = NULL;
Yuval Mintz41086462016-06-05 13:11:13 +03002111 } else {
2112 status = PFVF_STATUS_SUCCESS;
Yuval Mintz41086462016-06-05 13:11:13 +03002113 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002114
Yuval Mintz41086462016-06-05 13:11:13 +03002115out:
Yuval Mintz5040acf2016-06-05 13:11:14 +03002116 qed_iov_vf_mbx_start_txq_resp(p_hwfn, p_ptt, vf, status);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002117}
2118
2119static int qed_iov_vf_stop_rxqs(struct qed_hwfn *p_hwfn,
2120 struct qed_vf_info *vf,
2121 u16 rxq_id, u8 num_rxqs, bool cqe_completion)
2122{
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002123 struct qed_vf_q_info *p_queue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002124 int rc = 0;
2125 int qid;
2126
2127 if (rxq_id + num_rxqs > ARRAY_SIZE(vf->vf_queues))
2128 return -EINVAL;
2129
2130 for (qid = rxq_id; qid < rxq_id + num_rxqs; qid++) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002131 p_queue = &vf->vf_queues[qid];
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002132
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002133 if (!p_queue->p_rx_cid)
2134 continue;
2135
2136 rc = qed_eth_rx_queue_stop(p_hwfn,
2137 p_queue->p_rx_cid,
2138 false, cqe_completion);
2139 if (rc)
2140 return rc;
2141
2142 vf->vf_queues[qid].p_rx_cid = NULL;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002143 vf->num_active_rxqs--;
2144 }
2145
2146 return rc;
2147}
2148
2149static int qed_iov_vf_stop_txqs(struct qed_hwfn *p_hwfn,
2150 struct qed_vf_info *vf, u16 txq_id, u8 num_txqs)
2151{
2152 int rc = 0;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002153 struct qed_vf_q_info *p_queue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002154 int qid;
2155
2156 if (txq_id + num_txqs > ARRAY_SIZE(vf->vf_queues))
2157 return -EINVAL;
2158
2159 for (qid = txq_id; qid < txq_id + num_txqs; qid++) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002160 p_queue = &vf->vf_queues[qid];
2161 if (!p_queue->p_tx_cid)
2162 continue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002163
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002164 rc = qed_eth_tx_queue_stop(p_hwfn, p_queue->p_tx_cid);
2165 if (rc)
2166 return rc;
2167
2168 p_queue->p_tx_cid = NULL;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002169 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002170
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002171 return rc;
2172}
2173
2174static void qed_iov_vf_mbx_stop_rxqs(struct qed_hwfn *p_hwfn,
2175 struct qed_ptt *p_ptt,
2176 struct qed_vf_info *vf)
2177{
2178 u16 length = sizeof(struct pfvf_def_resp_tlv);
2179 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2180 u8 status = PFVF_STATUS_SUCCESS;
2181 struct vfpf_stop_rxqs_tlv *req;
2182 int rc;
2183
2184 /* We give the option of starting from qid != 0, in this case we
2185 * need to make sure that qid + num_qs doesn't exceed the actual
2186 * amount of queues that exist.
2187 */
2188 req = &mbx->req_virt->stop_rxqs;
2189 rc = qed_iov_vf_stop_rxqs(p_hwfn, vf, req->rx_qid,
2190 req->num_rxqs, req->cqe_completion);
2191 if (rc)
2192 status = PFVF_STATUS_FAILURE;
2193
2194 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_STOP_RXQS,
2195 length, status);
2196}
2197
2198static void qed_iov_vf_mbx_stop_txqs(struct qed_hwfn *p_hwfn,
2199 struct qed_ptt *p_ptt,
2200 struct qed_vf_info *vf)
2201{
2202 u16 length = sizeof(struct pfvf_def_resp_tlv);
2203 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2204 u8 status = PFVF_STATUS_SUCCESS;
2205 struct vfpf_stop_txqs_tlv *req;
2206 int rc;
2207
2208 /* We give the option of starting from qid != 0, in this case we
2209 * need to make sure that qid + num_qs doesn't exceed the actual
2210 * amount of queues that exist.
2211 */
2212 req = &mbx->req_virt->stop_txqs;
2213 rc = qed_iov_vf_stop_txqs(p_hwfn, vf, req->tx_qid, req->num_txqs);
2214 if (rc)
2215 status = PFVF_STATUS_FAILURE;
2216
2217 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_STOP_TXQS,
2218 length, status);
2219}
2220
Yuval Mintz17b235c2016-05-11 16:36:18 +03002221static void qed_iov_vf_mbx_update_rxqs(struct qed_hwfn *p_hwfn,
2222 struct qed_ptt *p_ptt,
2223 struct qed_vf_info *vf)
2224{
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002225 struct qed_queue_cid *handlers[QED_MAX_VF_CHAINS_PER_PF];
Yuval Mintz17b235c2016-05-11 16:36:18 +03002226 u16 length = sizeof(struct pfvf_def_resp_tlv);
2227 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2228 struct vfpf_update_rxq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002229 u8 status = PFVF_STATUS_FAILURE;
Yuval Mintz17b235c2016-05-11 16:36:18 +03002230 u8 complete_event_flg;
2231 u8 complete_cqe_flg;
2232 u16 qid;
2233 int rc;
2234 u8 i;
2235
2236 req = &mbx->req_virt->update_rxq;
2237 complete_cqe_flg = !!(req->flags & VFPF_RXQ_UPD_COMPLETE_CQE_FLAG);
2238 complete_event_flg = !!(req->flags & VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG);
2239
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002240 /* Validate inputs */
Mintz, Yuvalf109c242017-03-19 13:08:16 +02002241 for (i = req->rx_qid; i < req->rx_qid + req->num_rxqs; i++)
2242 if (!qed_iov_validate_rxq(p_hwfn, vf, i,
2243 QED_IOV_VALIDATE_Q_ENABLE)) {
2244 DP_INFO(p_hwfn, "VF[%d]: Incorrect Rxqs [%04x, %02x]\n",
2245 vf->relative_vf_id, req->rx_qid, req->num_rxqs);
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002246 goto out;
2247 }
2248
Mintz, Yuvalf109c242017-03-19 13:08:16 +02002249 /* Prepare the handlers */
2250 for (i = 0; i < req->num_rxqs; i++) {
2251 qid = req->rx_qid + i;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002252 handlers[i] = vf->vf_queues[qid].p_rx_cid;
2253 }
2254
2255 rc = qed_sp_eth_rx_queues_update(p_hwfn, (void **)&handlers,
2256 req->num_rxqs,
2257 complete_cqe_flg,
2258 complete_event_flg,
2259 QED_SPQ_MODE_EBLOCK, NULL);
2260 if (rc)
2261 goto out;
2262
2263 status = PFVF_STATUS_SUCCESS;
2264out:
Yuval Mintz17b235c2016-05-11 16:36:18 +03002265 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_UPDATE_RXQ,
2266 length, status);
2267}
2268
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002269void *qed_iov_search_list_tlvs(struct qed_hwfn *p_hwfn,
2270 void *p_tlvs_list, u16 req_type)
2271{
2272 struct channel_tlv *p_tlv = (struct channel_tlv *)p_tlvs_list;
2273 int len = 0;
2274
2275 do {
2276 if (!p_tlv->length) {
2277 DP_NOTICE(p_hwfn, "Zero length TLV found\n");
2278 return NULL;
2279 }
2280
2281 if (p_tlv->type == req_type) {
2282 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2283 "Extended tlv type %d, length %d found\n",
2284 p_tlv->type, p_tlv->length);
2285 return p_tlv;
2286 }
2287
2288 len += p_tlv->length;
2289 p_tlv = (struct channel_tlv *)((u8 *)p_tlv + p_tlv->length);
2290
2291 if ((len + p_tlv->length) > TLV_BUFFER_SIZE) {
2292 DP_NOTICE(p_hwfn, "TLVs has overrun the buffer size\n");
2293 return NULL;
2294 }
2295 } while (p_tlv->type != CHANNEL_TLV_LIST_END);
2296
2297 return NULL;
2298}
2299
2300static void
2301qed_iov_vp_update_act_param(struct qed_hwfn *p_hwfn,
2302 struct qed_sp_vport_update_params *p_data,
2303 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2304{
2305 struct vfpf_vport_update_activate_tlv *p_act_tlv;
2306 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
2307
2308 p_act_tlv = (struct vfpf_vport_update_activate_tlv *)
2309 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2310 if (!p_act_tlv)
2311 return;
2312
2313 p_data->update_vport_active_rx_flg = p_act_tlv->update_rx;
2314 p_data->vport_active_rx_flg = p_act_tlv->active_rx;
2315 p_data->update_vport_active_tx_flg = p_act_tlv->update_tx;
2316 p_data->vport_active_tx_flg = p_act_tlv->active_tx;
2317 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACTIVATE;
2318}
2319
2320static void
Yuval Mintz17b235c2016-05-11 16:36:18 +03002321qed_iov_vp_update_vlan_param(struct qed_hwfn *p_hwfn,
2322 struct qed_sp_vport_update_params *p_data,
2323 struct qed_vf_info *p_vf,
2324 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2325{
2326 struct vfpf_vport_update_vlan_strip_tlv *p_vlan_tlv;
2327 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP;
2328
2329 p_vlan_tlv = (struct vfpf_vport_update_vlan_strip_tlv *)
2330 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2331 if (!p_vlan_tlv)
2332 return;
2333
Yuval Mintz08feecd2016-05-11 16:36:20 +03002334 p_vf->shadow_config.inner_vlan_removal = p_vlan_tlv->remove_vlan;
2335
2336 /* Ignore the VF request if we're forcing a vlan */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002337 if (!(p_vf->configured_features & BIT(VLAN_ADDR_FORCED))) {
Yuval Mintz08feecd2016-05-11 16:36:20 +03002338 p_data->update_inner_vlan_removal_flg = 1;
2339 p_data->inner_vlan_removal_flg = p_vlan_tlv->remove_vlan;
2340 }
Yuval Mintz17b235c2016-05-11 16:36:18 +03002341
2342 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_VLAN_STRIP;
2343}
2344
2345static void
2346qed_iov_vp_update_tx_switch(struct qed_hwfn *p_hwfn,
2347 struct qed_sp_vport_update_params *p_data,
2348 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2349{
2350 struct vfpf_vport_update_tx_switch_tlv *p_tx_switch_tlv;
2351 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
2352
2353 p_tx_switch_tlv = (struct vfpf_vport_update_tx_switch_tlv *)
2354 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt,
2355 tlv);
2356 if (!p_tx_switch_tlv)
2357 return;
2358
2359 p_data->update_tx_switching_flg = 1;
2360 p_data->tx_switching_flg = p_tx_switch_tlv->tx_switching;
2361 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_TX_SWITCH;
2362}
2363
2364static void
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002365qed_iov_vp_update_mcast_bin_param(struct qed_hwfn *p_hwfn,
2366 struct qed_sp_vport_update_params *p_data,
2367 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2368{
2369 struct vfpf_vport_update_mcast_bin_tlv *p_mcast_tlv;
2370 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_MCAST;
2371
2372 p_mcast_tlv = (struct vfpf_vport_update_mcast_bin_tlv *)
2373 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2374 if (!p_mcast_tlv)
2375 return;
2376
2377 p_data->update_approx_mcast_flg = 1;
2378 memcpy(p_data->bins, p_mcast_tlv->bins,
2379 sizeof(unsigned long) * ETH_MULTICAST_MAC_BINS_IN_REGS);
2380 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_MCAST;
2381}
2382
2383static void
2384qed_iov_vp_update_accept_flag(struct qed_hwfn *p_hwfn,
2385 struct qed_sp_vport_update_params *p_data,
2386 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2387{
2388 struct qed_filter_accept_flags *p_flags = &p_data->accept_flags;
2389 struct vfpf_vport_update_accept_param_tlv *p_accept_tlv;
2390 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
2391
2392 p_accept_tlv = (struct vfpf_vport_update_accept_param_tlv *)
2393 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2394 if (!p_accept_tlv)
2395 return;
2396
2397 p_flags->update_rx_mode_config = p_accept_tlv->update_rx_mode;
2398 p_flags->rx_accept_filter = p_accept_tlv->rx_accept_filter;
2399 p_flags->update_tx_mode_config = p_accept_tlv->update_tx_mode;
2400 p_flags->tx_accept_filter = p_accept_tlv->tx_accept_filter;
2401 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACCEPT_PARAM;
2402}
2403
2404static void
Yuval Mintz17b235c2016-05-11 16:36:18 +03002405qed_iov_vp_update_accept_any_vlan(struct qed_hwfn *p_hwfn,
2406 struct qed_sp_vport_update_params *p_data,
2407 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2408{
2409 struct vfpf_vport_update_accept_any_vlan_tlv *p_accept_any_vlan;
2410 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
2411
2412 p_accept_any_vlan = (struct vfpf_vport_update_accept_any_vlan_tlv *)
2413 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt,
2414 tlv);
2415 if (!p_accept_any_vlan)
2416 return;
2417
2418 p_data->accept_any_vlan = p_accept_any_vlan->accept_any_vlan;
2419 p_data->update_accept_any_vlan_flg =
2420 p_accept_any_vlan->update_accept_any_vlan_flg;
2421 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACCEPT_ANY_VLAN;
2422}
2423
2424static void
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002425qed_iov_vp_update_rss_param(struct qed_hwfn *p_hwfn,
2426 struct qed_vf_info *vf,
2427 struct qed_sp_vport_update_params *p_data,
2428 struct qed_rss_params *p_rss,
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002429 struct qed_iov_vf_mbx *p_mbx,
2430 u16 *tlvs_mask, u16 *tlvs_accepted)
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002431{
2432 struct vfpf_vport_update_rss_tlv *p_rss_tlv;
2433 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_RSS;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002434 bool b_reject = false;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002435 u16 table_size;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002436 u16 i, q_idx;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002437
2438 p_rss_tlv = (struct vfpf_vport_update_rss_tlv *)
2439 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2440 if (!p_rss_tlv) {
2441 p_data->rss_params = NULL;
2442 return;
2443 }
2444
2445 memset(p_rss, 0, sizeof(struct qed_rss_params));
2446
2447 p_rss->update_rss_config = !!(p_rss_tlv->update_rss_flags &
2448 VFPF_UPDATE_RSS_CONFIG_FLAG);
2449 p_rss->update_rss_capabilities = !!(p_rss_tlv->update_rss_flags &
2450 VFPF_UPDATE_RSS_CAPS_FLAG);
2451 p_rss->update_rss_ind_table = !!(p_rss_tlv->update_rss_flags &
2452 VFPF_UPDATE_RSS_IND_TABLE_FLAG);
2453 p_rss->update_rss_key = !!(p_rss_tlv->update_rss_flags &
2454 VFPF_UPDATE_RSS_KEY_FLAG);
2455
2456 p_rss->rss_enable = p_rss_tlv->rss_enable;
2457 p_rss->rss_eng_id = vf->relative_vf_id + 1;
2458 p_rss->rss_caps = p_rss_tlv->rss_caps;
2459 p_rss->rss_table_size_log = p_rss_tlv->rss_table_size_log;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002460 memcpy(p_rss->rss_key, p_rss_tlv->rss_key, sizeof(p_rss->rss_key));
2461
2462 table_size = min_t(u16, ARRAY_SIZE(p_rss->rss_ind_table),
2463 (1 << p_rss_tlv->rss_table_size_log));
2464
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002465 for (i = 0; i < table_size; i++) {
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002466 q_idx = p_rss_tlv->rss_ind_table[i];
Mintz, Yuvalf109c242017-03-19 13:08:16 +02002467 if (!qed_iov_validate_rxq(p_hwfn, vf, q_idx,
2468 QED_IOV_VALIDATE_Q_ENABLE)) {
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002469 DP_VERBOSE(p_hwfn,
2470 QED_MSG_IOV,
2471 "VF[%d]: Omitting RSS due to wrong queue %04x\n",
2472 vf->relative_vf_id, q_idx);
2473 b_reject = true;
2474 goto out;
2475 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002476
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002477 p_rss->rss_ind_table[i] = vf->vf_queues[q_idx].p_rx_cid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002478 }
2479
2480 p_data->rss_params = p_rss;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002481out:
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002482 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_RSS;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002483 if (!b_reject)
2484 *tlvs_accepted |= 1 << QED_IOV_VP_UPDATE_RSS;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002485}
2486
Yuval Mintz17b235c2016-05-11 16:36:18 +03002487static void
2488qed_iov_vp_update_sge_tpa_param(struct qed_hwfn *p_hwfn,
2489 struct qed_vf_info *vf,
2490 struct qed_sp_vport_update_params *p_data,
2491 struct qed_sge_tpa_params *p_sge_tpa,
2492 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2493{
2494 struct vfpf_vport_update_sge_tpa_tlv *p_sge_tpa_tlv;
2495 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_SGE_TPA;
2496
2497 p_sge_tpa_tlv = (struct vfpf_vport_update_sge_tpa_tlv *)
2498 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2499
2500 if (!p_sge_tpa_tlv) {
2501 p_data->sge_tpa_params = NULL;
2502 return;
2503 }
2504
2505 memset(p_sge_tpa, 0, sizeof(struct qed_sge_tpa_params));
2506
2507 p_sge_tpa->update_tpa_en_flg =
2508 !!(p_sge_tpa_tlv->update_sge_tpa_flags & VFPF_UPDATE_TPA_EN_FLAG);
2509 p_sge_tpa->update_tpa_param_flg =
2510 !!(p_sge_tpa_tlv->update_sge_tpa_flags &
2511 VFPF_UPDATE_TPA_PARAM_FLAG);
2512
2513 p_sge_tpa->tpa_ipv4_en_flg =
2514 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_IPV4_EN_FLAG);
2515 p_sge_tpa->tpa_ipv6_en_flg =
2516 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_IPV6_EN_FLAG);
2517 p_sge_tpa->tpa_pkt_split_flg =
2518 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_PKT_SPLIT_FLAG);
2519 p_sge_tpa->tpa_hdr_data_split_flg =
2520 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_HDR_DATA_SPLIT_FLAG);
2521 p_sge_tpa->tpa_gro_consistent_flg =
2522 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_GRO_CONSIST_FLAG);
2523
2524 p_sge_tpa->tpa_max_aggs_num = p_sge_tpa_tlv->tpa_max_aggs_num;
2525 p_sge_tpa->tpa_max_size = p_sge_tpa_tlv->tpa_max_size;
2526 p_sge_tpa->tpa_min_size_to_start = p_sge_tpa_tlv->tpa_min_size_to_start;
2527 p_sge_tpa->tpa_min_size_to_cont = p_sge_tpa_tlv->tpa_min_size_to_cont;
2528 p_sge_tpa->max_buffers_per_cqe = p_sge_tpa_tlv->max_buffers_per_cqe;
2529
2530 p_data->sge_tpa_params = p_sge_tpa;
2531
2532 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_SGE_TPA;
2533}
2534
Mintz, Yuvalf990c822017-01-01 13:57:08 +02002535static int qed_iov_pre_update_vport(struct qed_hwfn *hwfn,
2536 u8 vfid,
2537 struct qed_sp_vport_update_params *params,
2538 u16 *tlvs)
2539{
2540 u8 mask = QED_ACCEPT_UCAST_UNMATCHED | QED_ACCEPT_MCAST_UNMATCHED;
2541 struct qed_filter_accept_flags *flags = &params->accept_flags;
2542 struct qed_public_vf_info *vf_info;
2543
2544 /* Untrusted VFs can't even be trusted to know that fact.
2545 * Simply indicate everything is configured fine, and trace
2546 * configuration 'behind their back'.
2547 */
2548 if (!(*tlvs & BIT(QED_IOV_VP_UPDATE_ACCEPT_PARAM)))
2549 return 0;
2550
2551 vf_info = qed_iov_get_public_vf_info(hwfn, vfid, true);
2552
2553 if (flags->update_rx_mode_config) {
2554 vf_info->rx_accept_mode = flags->rx_accept_filter;
2555 if (!vf_info->is_trusted_configured)
2556 flags->rx_accept_filter &= ~mask;
2557 }
2558
2559 if (flags->update_tx_mode_config) {
2560 vf_info->tx_accept_mode = flags->tx_accept_filter;
2561 if (!vf_info->is_trusted_configured)
2562 flags->tx_accept_filter &= ~mask;
2563 }
2564
2565 return 0;
2566}
2567
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002568static void qed_iov_vf_mbx_vport_update(struct qed_hwfn *p_hwfn,
2569 struct qed_ptt *p_ptt,
2570 struct qed_vf_info *vf)
2571{
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002572 struct qed_rss_params *p_rss_params = NULL;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002573 struct qed_sp_vport_update_params params;
2574 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
Yuval Mintz17b235c2016-05-11 16:36:18 +03002575 struct qed_sge_tpa_params sge_tpa_params;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002576 u16 tlvs_mask = 0, tlvs_accepted = 0;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002577 u8 status = PFVF_STATUS_SUCCESS;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002578 u16 length;
2579 int rc;
2580
Yuval Mintz41086462016-06-05 13:11:13 +03002581 /* Valiate PF can send such a request */
2582 if (!vf->vport_instance) {
2583 DP_VERBOSE(p_hwfn,
2584 QED_MSG_IOV,
2585 "No VPORT instance available for VF[%d], failing vport update\n",
2586 vf->abs_vf_id);
2587 status = PFVF_STATUS_FAILURE;
2588 goto out;
2589 }
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002590 p_rss_params = vzalloc(sizeof(*p_rss_params));
2591 if (p_rss_params == NULL) {
2592 status = PFVF_STATUS_FAILURE;
2593 goto out;
2594 }
Yuval Mintz41086462016-06-05 13:11:13 +03002595
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002596 memset(&params, 0, sizeof(params));
2597 params.opaque_fid = vf->opaque_fid;
2598 params.vport_id = vf->vport_id;
2599 params.rss_params = NULL;
2600
2601 /* Search for extended tlvs list and update values
2602 * from VF in struct qed_sp_vport_update_params.
2603 */
2604 qed_iov_vp_update_act_param(p_hwfn, &params, mbx, &tlvs_mask);
Yuval Mintz17b235c2016-05-11 16:36:18 +03002605 qed_iov_vp_update_vlan_param(p_hwfn, &params, vf, mbx, &tlvs_mask);
2606 qed_iov_vp_update_tx_switch(p_hwfn, &params, mbx, &tlvs_mask);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002607 qed_iov_vp_update_mcast_bin_param(p_hwfn, &params, mbx, &tlvs_mask);
2608 qed_iov_vp_update_accept_flag(p_hwfn, &params, mbx, &tlvs_mask);
Yuval Mintz17b235c2016-05-11 16:36:18 +03002609 qed_iov_vp_update_accept_any_vlan(p_hwfn, &params, mbx, &tlvs_mask);
2610 qed_iov_vp_update_sge_tpa_param(p_hwfn, vf, &params,
2611 &sge_tpa_params, mbx, &tlvs_mask);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002612
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002613 tlvs_accepted = tlvs_mask;
2614
2615 /* Some of the extended TLVs need to be validated first; In that case,
2616 * they can update the mask without updating the accepted [so that
2617 * PF could communicate to VF it has rejected request].
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002618 */
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002619 qed_iov_vp_update_rss_param(p_hwfn, vf, &params, p_rss_params,
2620 mbx, &tlvs_mask, &tlvs_accepted);
2621
Mintz, Yuvalf990c822017-01-01 13:57:08 +02002622 if (qed_iov_pre_update_vport(p_hwfn, vf->relative_vf_id,
2623 &params, &tlvs_accepted)) {
2624 tlvs_accepted = 0;
2625 status = PFVF_STATUS_NOT_SUPPORTED;
2626 goto out;
2627 }
2628
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002629 if (!tlvs_accepted) {
2630 if (tlvs_mask)
2631 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2632 "Upper-layer prevents VF vport configuration\n");
2633 else
2634 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2635 "No feature tlvs found for vport update\n");
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002636 status = PFVF_STATUS_NOT_SUPPORTED;
2637 goto out;
2638 }
2639
2640 rc = qed_sp_vport_update(p_hwfn, &params, QED_SPQ_MODE_EBLOCK, NULL);
2641
2642 if (rc)
2643 status = PFVF_STATUS_FAILURE;
2644
2645out:
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002646 vfree(p_rss_params);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002647 length = qed_iov_prep_vp_update_resp_tlvs(p_hwfn, vf, mbx, status,
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002648 tlvs_mask, tlvs_accepted);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002649 qed_iov_send_response(p_hwfn, p_ptt, vf, length, status);
2650}
2651
Yuval Mintz8246d0b2016-06-05 13:11:15 +03002652static int qed_iov_vf_update_vlan_shadow(struct qed_hwfn *p_hwfn,
2653 struct qed_vf_info *p_vf,
2654 struct qed_filter_ucast *p_params)
Yuval Mintz08feecd2016-05-11 16:36:20 +03002655{
2656 int i;
2657
Yuval Mintz08feecd2016-05-11 16:36:20 +03002658 /* First remove entries and then add new ones */
2659 if (p_params->opcode == QED_FILTER_REMOVE) {
2660 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++)
2661 if (p_vf->shadow_config.vlans[i].used &&
2662 p_vf->shadow_config.vlans[i].vid ==
2663 p_params->vlan) {
2664 p_vf->shadow_config.vlans[i].used = false;
2665 break;
2666 }
2667 if (i == QED_ETH_VF_NUM_VLAN_FILTERS + 1) {
2668 DP_VERBOSE(p_hwfn,
2669 QED_MSG_IOV,
2670 "VF [%d] - Tries to remove a non-existing vlan\n",
2671 p_vf->relative_vf_id);
2672 return -EINVAL;
2673 }
2674 } else if (p_params->opcode == QED_FILTER_REPLACE ||
2675 p_params->opcode == QED_FILTER_FLUSH) {
2676 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++)
2677 p_vf->shadow_config.vlans[i].used = false;
2678 }
2679
2680 /* In forced mode, we're willing to remove entries - but we don't add
2681 * new ones.
2682 */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002683 if (p_vf->bulletin.p_virt->valid_bitmap & BIT(VLAN_ADDR_FORCED))
Yuval Mintz08feecd2016-05-11 16:36:20 +03002684 return 0;
2685
2686 if (p_params->opcode == QED_FILTER_ADD ||
2687 p_params->opcode == QED_FILTER_REPLACE) {
2688 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++) {
2689 if (p_vf->shadow_config.vlans[i].used)
2690 continue;
2691
2692 p_vf->shadow_config.vlans[i].used = true;
2693 p_vf->shadow_config.vlans[i].vid = p_params->vlan;
2694 break;
2695 }
2696
2697 if (i == QED_ETH_VF_NUM_VLAN_FILTERS + 1) {
2698 DP_VERBOSE(p_hwfn,
2699 QED_MSG_IOV,
2700 "VF [%d] - Tries to configure more than %d vlan filters\n",
2701 p_vf->relative_vf_id,
2702 QED_ETH_VF_NUM_VLAN_FILTERS + 1);
2703 return -EINVAL;
2704 }
2705 }
2706
2707 return 0;
2708}
2709
Yuval Mintz8246d0b2016-06-05 13:11:15 +03002710static int qed_iov_vf_update_mac_shadow(struct qed_hwfn *p_hwfn,
2711 struct qed_vf_info *p_vf,
2712 struct qed_filter_ucast *p_params)
2713{
2714 int i;
2715
2716 /* If we're in forced-mode, we don't allow any change */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002717 if (p_vf->bulletin.p_virt->valid_bitmap & BIT(MAC_ADDR_FORCED))
Yuval Mintz8246d0b2016-06-05 13:11:15 +03002718 return 0;
2719
2720 /* First remove entries and then add new ones */
2721 if (p_params->opcode == QED_FILTER_REMOVE) {
2722 for (i = 0; i < QED_ETH_VF_NUM_MAC_FILTERS; i++) {
2723 if (ether_addr_equal(p_vf->shadow_config.macs[i],
2724 p_params->mac)) {
Shyam Saini0ee28e32017-01-17 07:35:04 +05302725 eth_zero_addr(p_vf->shadow_config.macs[i]);
Yuval Mintz8246d0b2016-06-05 13:11:15 +03002726 break;
2727 }
2728 }
2729
2730 if (i == QED_ETH_VF_NUM_MAC_FILTERS) {
2731 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2732 "MAC isn't configured\n");
2733 return -EINVAL;
2734 }
2735 } else if (p_params->opcode == QED_FILTER_REPLACE ||
2736 p_params->opcode == QED_FILTER_FLUSH) {
2737 for (i = 0; i < QED_ETH_VF_NUM_MAC_FILTERS; i++)
Shyam Saini0ee28e32017-01-17 07:35:04 +05302738 eth_zero_addr(p_vf->shadow_config.macs[i]);
Yuval Mintz8246d0b2016-06-05 13:11:15 +03002739 }
2740
2741 /* List the new MAC address */
2742 if (p_params->opcode != QED_FILTER_ADD &&
2743 p_params->opcode != QED_FILTER_REPLACE)
2744 return 0;
2745
2746 for (i = 0; i < QED_ETH_VF_NUM_MAC_FILTERS; i++) {
2747 if (is_zero_ether_addr(p_vf->shadow_config.macs[i])) {
2748 ether_addr_copy(p_vf->shadow_config.macs[i],
2749 p_params->mac);
2750 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2751 "Added MAC at %d entry in shadow\n", i);
2752 break;
2753 }
2754 }
2755
2756 if (i == QED_ETH_VF_NUM_MAC_FILTERS) {
2757 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "No available place for MAC\n");
2758 return -EINVAL;
2759 }
2760
2761 return 0;
2762}
2763
2764static int
2765qed_iov_vf_update_unicast_shadow(struct qed_hwfn *p_hwfn,
2766 struct qed_vf_info *p_vf,
2767 struct qed_filter_ucast *p_params)
2768{
2769 int rc = 0;
2770
2771 if (p_params->type == QED_FILTER_MAC) {
2772 rc = qed_iov_vf_update_mac_shadow(p_hwfn, p_vf, p_params);
2773 if (rc)
2774 return rc;
2775 }
2776
2777 if (p_params->type == QED_FILTER_VLAN)
2778 rc = qed_iov_vf_update_vlan_shadow(p_hwfn, p_vf, p_params);
2779
2780 return rc;
2781}
2782
Baoyou Xieba569472016-09-09 09:21:15 +08002783static int qed_iov_chk_ucast(struct qed_hwfn *hwfn,
2784 int vfid, struct qed_filter_ucast *params)
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002785{
2786 struct qed_public_vf_info *vf;
2787
2788 vf = qed_iov_get_public_vf_info(hwfn, vfid, true);
2789 if (!vf)
2790 return -EINVAL;
2791
2792 /* No real decision to make; Store the configured MAC */
2793 if (params->type == QED_FILTER_MAC ||
2794 params->type == QED_FILTER_MAC_VLAN)
2795 ether_addr_copy(vf->mac, params->mac);
2796
2797 return 0;
2798}
2799
2800static void qed_iov_vf_mbx_ucast_filter(struct qed_hwfn *p_hwfn,
2801 struct qed_ptt *p_ptt,
2802 struct qed_vf_info *vf)
2803{
Yuval Mintz08feecd2016-05-11 16:36:20 +03002804 struct qed_bulletin_content *p_bulletin = vf->bulletin.p_virt;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002805 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2806 struct vfpf_ucast_filter_tlv *req;
2807 u8 status = PFVF_STATUS_SUCCESS;
2808 struct qed_filter_ucast params;
2809 int rc;
2810
2811 /* Prepare the unicast filter params */
2812 memset(&params, 0, sizeof(struct qed_filter_ucast));
2813 req = &mbx->req_virt->ucast_filter;
2814 params.opcode = (enum qed_filter_opcode)req->opcode;
2815 params.type = (enum qed_filter_ucast_type)req->type;
2816
2817 params.is_rx_filter = 1;
2818 params.is_tx_filter = 1;
2819 params.vport_to_remove_from = vf->vport_id;
2820 params.vport_to_add_to = vf->vport_id;
2821 memcpy(params.mac, req->mac, ETH_ALEN);
2822 params.vlan = req->vlan;
2823
2824 DP_VERBOSE(p_hwfn,
2825 QED_MSG_IOV,
2826 "VF[%d]: opcode 0x%02x type 0x%02x [%s %s] [vport 0x%02x] MAC %02x:%02x:%02x:%02x:%02x:%02x, vlan 0x%04x\n",
2827 vf->abs_vf_id, params.opcode, params.type,
2828 params.is_rx_filter ? "RX" : "",
2829 params.is_tx_filter ? "TX" : "",
2830 params.vport_to_add_to,
2831 params.mac[0], params.mac[1],
2832 params.mac[2], params.mac[3],
2833 params.mac[4], params.mac[5], params.vlan);
2834
2835 if (!vf->vport_instance) {
2836 DP_VERBOSE(p_hwfn,
2837 QED_MSG_IOV,
2838 "No VPORT instance available for VF[%d], failing ucast MAC configuration\n",
2839 vf->abs_vf_id);
2840 status = PFVF_STATUS_FAILURE;
2841 goto out;
2842 }
2843
Yuval Mintz08feecd2016-05-11 16:36:20 +03002844 /* Update shadow copy of the VF configuration */
2845 if (qed_iov_vf_update_unicast_shadow(p_hwfn, vf, &params)) {
2846 status = PFVF_STATUS_FAILURE;
2847 goto out;
2848 }
2849
2850 /* Determine if the unicast filtering is acceptible by PF */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002851 if ((p_bulletin->valid_bitmap & BIT(VLAN_ADDR_FORCED)) &&
Yuval Mintz08feecd2016-05-11 16:36:20 +03002852 (params.type == QED_FILTER_VLAN ||
2853 params.type == QED_FILTER_MAC_VLAN)) {
2854 /* Once VLAN is forced or PVID is set, do not allow
2855 * to add/replace any further VLANs.
2856 */
2857 if (params.opcode == QED_FILTER_ADD ||
2858 params.opcode == QED_FILTER_REPLACE)
2859 status = PFVF_STATUS_FORCED;
2860 goto out;
2861 }
2862
Yuval Mintz1a635e42016-08-15 10:42:43 +03002863 if ((p_bulletin->valid_bitmap & BIT(MAC_ADDR_FORCED)) &&
Yuval Mintzeff16962016-05-11 16:36:21 +03002864 (params.type == QED_FILTER_MAC ||
2865 params.type == QED_FILTER_MAC_VLAN)) {
2866 if (!ether_addr_equal(p_bulletin->mac, params.mac) ||
2867 (params.opcode != QED_FILTER_ADD &&
2868 params.opcode != QED_FILTER_REPLACE))
2869 status = PFVF_STATUS_FORCED;
2870 goto out;
2871 }
2872
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002873 rc = qed_iov_chk_ucast(p_hwfn, vf->relative_vf_id, &params);
2874 if (rc) {
2875 status = PFVF_STATUS_FAILURE;
2876 goto out;
2877 }
2878
2879 rc = qed_sp_eth_filter_ucast(p_hwfn, vf->opaque_fid, &params,
2880 QED_SPQ_MODE_CB, NULL);
2881 if (rc)
2882 status = PFVF_STATUS_FAILURE;
2883
2884out:
2885 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_UCAST_FILTER,
2886 sizeof(struct pfvf_def_resp_tlv), status);
2887}
2888
Yuval Mintz0b55e272016-05-11 16:36:15 +03002889static void qed_iov_vf_mbx_int_cleanup(struct qed_hwfn *p_hwfn,
2890 struct qed_ptt *p_ptt,
2891 struct qed_vf_info *vf)
2892{
2893 int i;
2894
2895 /* Reset the SBs */
2896 for (i = 0; i < vf->num_sbs; i++)
2897 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2898 vf->igu_sbs[i],
2899 vf->opaque_fid, false);
2900
2901 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_INT_CLEANUP,
2902 sizeof(struct pfvf_def_resp_tlv),
2903 PFVF_STATUS_SUCCESS);
2904}
2905
2906static void qed_iov_vf_mbx_close(struct qed_hwfn *p_hwfn,
2907 struct qed_ptt *p_ptt, struct qed_vf_info *vf)
2908{
2909 u16 length = sizeof(struct pfvf_def_resp_tlv);
2910 u8 status = PFVF_STATUS_SUCCESS;
2911
2912 /* Disable Interrupts for VF */
2913 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 0);
2914
2915 /* Reset Permission table */
2916 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, 0);
2917
2918 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_CLOSE,
2919 length, status);
2920}
2921
2922static void qed_iov_vf_mbx_release(struct qed_hwfn *p_hwfn,
2923 struct qed_ptt *p_ptt,
2924 struct qed_vf_info *p_vf)
2925{
2926 u16 length = sizeof(struct pfvf_def_resp_tlv);
Yuval Mintz1fe614d2016-06-05 13:11:11 +03002927 u8 status = PFVF_STATUS_SUCCESS;
2928 int rc = 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +03002929
2930 qed_iov_vf_cleanup(p_hwfn, p_vf);
2931
Yuval Mintz1fe614d2016-06-05 13:11:11 +03002932 if (p_vf->state != VF_STOPPED && p_vf->state != VF_FREE) {
2933 /* Stopping the VF */
2934 rc = qed_sp_vf_stop(p_hwfn, p_vf->concrete_fid,
2935 p_vf->opaque_fid);
2936
2937 if (rc) {
2938 DP_ERR(p_hwfn, "qed_sp_vf_stop returned error %d\n",
2939 rc);
2940 status = PFVF_STATUS_FAILURE;
2941 }
2942
2943 p_vf->state = VF_STOPPED;
2944 }
2945
Yuval Mintz0b55e272016-05-11 16:36:15 +03002946 qed_iov_prepare_resp(p_hwfn, p_ptt, p_vf, CHANNEL_TLV_RELEASE,
Yuval Mintz1fe614d2016-06-05 13:11:11 +03002947 length, status);
Yuval Mintz0b55e272016-05-11 16:36:15 +03002948}
2949
2950static int
2951qed_iov_vf_flr_poll_dorq(struct qed_hwfn *p_hwfn,
2952 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
2953{
2954 int cnt;
2955 u32 val;
2956
2957 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_vf->concrete_fid);
2958
2959 for (cnt = 0; cnt < 50; cnt++) {
2960 val = qed_rd(p_hwfn, p_ptt, DORQ_REG_VF_USAGE_CNT);
2961 if (!val)
2962 break;
2963 msleep(20);
2964 }
2965 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
2966
2967 if (cnt == 50) {
2968 DP_ERR(p_hwfn,
2969 "VF[%d] - dorq failed to cleanup [usage 0x%08x]\n",
2970 p_vf->abs_vf_id, val);
2971 return -EBUSY;
2972 }
2973
2974 return 0;
2975}
2976
2977static int
2978qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
2979 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
2980{
2981 u32 cons[MAX_NUM_VOQS], distance[MAX_NUM_VOQS];
2982 int i, cnt;
2983
2984 /* Read initial consumers & producers */
2985 for (i = 0; i < MAX_NUM_VOQS; i++) {
2986 u32 prod;
2987
2988 cons[i] = qed_rd(p_hwfn, p_ptt,
2989 PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 +
2990 i * 0x40);
2991 prod = qed_rd(p_hwfn, p_ptt,
2992 PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 +
2993 i * 0x40);
2994 distance[i] = prod - cons[i];
2995 }
2996
2997 /* Wait for consumers to pass the producers */
2998 i = 0;
2999 for (cnt = 0; cnt < 50; cnt++) {
3000 for (; i < MAX_NUM_VOQS; i++) {
3001 u32 tmp;
3002
3003 tmp = qed_rd(p_hwfn, p_ptt,
3004 PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 +
3005 i * 0x40);
3006 if (distance[i] > tmp - cons[i])
3007 break;
3008 }
3009
3010 if (i == MAX_NUM_VOQS)
3011 break;
3012
3013 msleep(20);
3014 }
3015
3016 if (cnt == 50) {
3017 DP_ERR(p_hwfn, "VF[%d] - pbf polling failed on VOQ %d\n",
3018 p_vf->abs_vf_id, i);
3019 return -EBUSY;
3020 }
3021
3022 return 0;
3023}
3024
3025static int qed_iov_vf_flr_poll(struct qed_hwfn *p_hwfn,
3026 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
3027{
3028 int rc;
3029
3030 rc = qed_iov_vf_flr_poll_dorq(p_hwfn, p_vf, p_ptt);
3031 if (rc)
3032 return rc;
3033
3034 rc = qed_iov_vf_flr_poll_pbf(p_hwfn, p_vf, p_ptt);
3035 if (rc)
3036 return rc;
3037
3038 return 0;
3039}
3040
3041static int
3042qed_iov_execute_vf_flr_cleanup(struct qed_hwfn *p_hwfn,
3043 struct qed_ptt *p_ptt,
3044 u16 rel_vf_id, u32 *ack_vfs)
3045{
3046 struct qed_vf_info *p_vf;
3047 int rc = 0;
3048
3049 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, false);
3050 if (!p_vf)
3051 return 0;
3052
3053 if (p_hwfn->pf_iov_info->pending_flr[rel_vf_id / 64] &
3054 (1ULL << (rel_vf_id % 64))) {
3055 u16 vfid = p_vf->abs_vf_id;
3056
3057 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3058 "VF[%d] - Handling FLR\n", vfid);
3059
3060 qed_iov_vf_cleanup(p_hwfn, p_vf);
3061
3062 /* If VF isn't active, no need for anything but SW */
3063 if (!p_vf->b_init)
3064 goto cleanup;
3065
3066 rc = qed_iov_vf_flr_poll(p_hwfn, p_vf, p_ptt);
3067 if (rc)
3068 goto cleanup;
3069
3070 rc = qed_final_cleanup(p_hwfn, p_ptt, vfid, true);
3071 if (rc) {
3072 DP_ERR(p_hwfn, "Failed handle FLR of VF[%d]\n", vfid);
3073 return rc;
3074 }
3075
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003076 /* Workaround to make VF-PF channel ready, as FW
3077 * doesn't do that as a part of FLR.
3078 */
3079 REG_WR(p_hwfn,
3080 GTT_BAR0_MAP_REG_USDM_RAM +
3081 USTORM_VF_PF_CHANNEL_READY_OFFSET(vfid), 1);
3082
Yuval Mintz0b55e272016-05-11 16:36:15 +03003083 /* VF_STOPPED has to be set only after final cleanup
3084 * but prior to re-enabling the VF.
3085 */
3086 p_vf->state = VF_STOPPED;
3087
3088 rc = qed_iov_enable_vf_access(p_hwfn, p_ptt, p_vf);
3089 if (rc) {
3090 DP_ERR(p_hwfn, "Failed to re-enable VF[%d] acces\n",
3091 vfid);
3092 return rc;
3093 }
3094cleanup:
3095 /* Mark VF for ack and clean pending state */
3096 if (p_vf->state == VF_RESET)
3097 p_vf->state = VF_STOPPED;
Yuval Mintz1a635e42016-08-15 10:42:43 +03003098 ack_vfs[vfid / 32] |= BIT((vfid % 32));
Yuval Mintz0b55e272016-05-11 16:36:15 +03003099 p_hwfn->pf_iov_info->pending_flr[rel_vf_id / 64] &=
3100 ~(1ULL << (rel_vf_id % 64));
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003101 p_vf->vf_mbx.b_pending_msg = false;
Yuval Mintz0b55e272016-05-11 16:36:15 +03003102 }
3103
3104 return rc;
3105}
3106
Baoyou Xieba569472016-09-09 09:21:15 +08003107static int
3108qed_iov_vf_flr_cleanup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
Yuval Mintz0b55e272016-05-11 16:36:15 +03003109{
3110 u32 ack_vfs[VF_MAX_STATIC / 32];
3111 int rc = 0;
3112 u16 i;
3113
3114 memset(ack_vfs, 0, sizeof(u32) * (VF_MAX_STATIC / 32));
3115
3116 /* Since BRB <-> PRS interface can't be tested as part of the flr
3117 * polling due to HW limitations, simply sleep a bit. And since
3118 * there's no need to wait per-vf, do it before looping.
3119 */
3120 msleep(100);
3121
3122 for (i = 0; i < p_hwfn->cdev->p_iov_info->total_vfs; i++)
3123 qed_iov_execute_vf_flr_cleanup(p_hwfn, p_ptt, i, ack_vfs);
3124
3125 rc = qed_mcp_ack_vf_flr(p_hwfn, p_ptt, ack_vfs);
3126 return rc;
3127}
3128
3129int qed_iov_mark_vf_flr(struct qed_hwfn *p_hwfn, u32 *p_disabled_vfs)
3130{
3131 u16 i, found = 0;
3132
3133 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "Marking FLR-ed VFs\n");
3134 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
3135 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3136 "[%08x,...,%08x]: %08x\n",
3137 i * 32, (i + 1) * 32 - 1, p_disabled_vfs[i]);
3138
3139 if (!p_hwfn->cdev->p_iov_info) {
3140 DP_NOTICE(p_hwfn, "VF flr but no IOV\n");
3141 return 0;
3142 }
3143
3144 /* Mark VFs */
3145 for (i = 0; i < p_hwfn->cdev->p_iov_info->total_vfs; i++) {
3146 struct qed_vf_info *p_vf;
3147 u8 vfid;
3148
3149 p_vf = qed_iov_get_vf_info(p_hwfn, i, false);
3150 if (!p_vf)
3151 continue;
3152
3153 vfid = p_vf->abs_vf_id;
Yuval Mintz1a635e42016-08-15 10:42:43 +03003154 if (BIT((vfid % 32)) & p_disabled_vfs[vfid / 32]) {
Yuval Mintz0b55e272016-05-11 16:36:15 +03003155 u64 *p_flr = p_hwfn->pf_iov_info->pending_flr;
3156 u16 rel_vf_id = p_vf->relative_vf_id;
3157
3158 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3159 "VF[%d] [rel %d] got FLR-ed\n",
3160 vfid, rel_vf_id);
3161
3162 p_vf->state = VF_RESET;
3163
3164 /* No need to lock here, since pending_flr should
3165 * only change here and before ACKing MFw. Since
3166 * MFW will not trigger an additional attention for
3167 * VF flr until ACKs, we're safe.
3168 */
3169 p_flr[rel_vf_id / 64] |= 1ULL << (rel_vf_id % 64);
3170 found = 1;
3171 }
3172 }
3173
3174 return found;
3175}
3176
Yuval Mintz73390ac2016-05-11 16:36:24 +03003177static void qed_iov_get_link(struct qed_hwfn *p_hwfn,
3178 u16 vfid,
3179 struct qed_mcp_link_params *p_params,
3180 struct qed_mcp_link_state *p_link,
3181 struct qed_mcp_link_capabilities *p_caps)
3182{
3183 struct qed_vf_info *p_vf = qed_iov_get_vf_info(p_hwfn,
3184 vfid,
3185 false);
3186 struct qed_bulletin_content *p_bulletin;
3187
3188 if (!p_vf)
3189 return;
3190
3191 p_bulletin = p_vf->bulletin.p_virt;
3192
3193 if (p_params)
3194 __qed_vf_get_link_params(p_hwfn, p_params, p_bulletin);
3195 if (p_link)
3196 __qed_vf_get_link_state(p_hwfn, p_link, p_bulletin);
3197 if (p_caps)
3198 __qed_vf_get_link_caps(p_hwfn, p_caps, p_bulletin);
3199}
3200
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003201static void qed_iov_process_mbx_req(struct qed_hwfn *p_hwfn,
3202 struct qed_ptt *p_ptt, int vfid)
3203{
3204 struct qed_iov_vf_mbx *mbx;
3205 struct qed_vf_info *p_vf;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003206
3207 p_vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3208 if (!p_vf)
3209 return;
3210
3211 mbx = &p_vf->vf_mbx;
3212
3213 /* qed_iov_process_mbx_request */
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003214 if (!mbx->b_pending_msg) {
3215 DP_NOTICE(p_hwfn,
3216 "VF[%02x]: Trying to process mailbox message when none is pending\n",
3217 p_vf->abs_vf_id);
3218 return;
3219 }
3220 mbx->b_pending_msg = false;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003221
3222 mbx->first_tlv = mbx->req_virt->first_tlv;
3223
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003224 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3225 "VF[%02x]: Processing mailbox message [type %04x]\n",
3226 p_vf->abs_vf_id, mbx->first_tlv.tl.type);
3227
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003228 /* check if tlv type is known */
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003229 if (qed_iov_tlv_supported(mbx->first_tlv.tl.type) &&
3230 !p_vf->b_malicious) {
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003231 switch (mbx->first_tlv.tl.type) {
3232 case CHANNEL_TLV_ACQUIRE:
3233 qed_iov_vf_mbx_acquire(p_hwfn, p_ptt, p_vf);
3234 break;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03003235 case CHANNEL_TLV_VPORT_START:
3236 qed_iov_vf_mbx_start_vport(p_hwfn, p_ptt, p_vf);
3237 break;
3238 case CHANNEL_TLV_VPORT_TEARDOWN:
3239 qed_iov_vf_mbx_stop_vport(p_hwfn, p_ptt, p_vf);
3240 break;
3241 case CHANNEL_TLV_START_RXQ:
3242 qed_iov_vf_mbx_start_rxq(p_hwfn, p_ptt, p_vf);
3243 break;
3244 case CHANNEL_TLV_START_TXQ:
3245 qed_iov_vf_mbx_start_txq(p_hwfn, p_ptt, p_vf);
3246 break;
3247 case CHANNEL_TLV_STOP_RXQS:
3248 qed_iov_vf_mbx_stop_rxqs(p_hwfn, p_ptt, p_vf);
3249 break;
3250 case CHANNEL_TLV_STOP_TXQS:
3251 qed_iov_vf_mbx_stop_txqs(p_hwfn, p_ptt, p_vf);
3252 break;
Yuval Mintz17b235c2016-05-11 16:36:18 +03003253 case CHANNEL_TLV_UPDATE_RXQ:
3254 qed_iov_vf_mbx_update_rxqs(p_hwfn, p_ptt, p_vf);
3255 break;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03003256 case CHANNEL_TLV_VPORT_UPDATE:
3257 qed_iov_vf_mbx_vport_update(p_hwfn, p_ptt, p_vf);
3258 break;
3259 case CHANNEL_TLV_UCAST_FILTER:
3260 qed_iov_vf_mbx_ucast_filter(p_hwfn, p_ptt, p_vf);
3261 break;
Yuval Mintz0b55e272016-05-11 16:36:15 +03003262 case CHANNEL_TLV_CLOSE:
3263 qed_iov_vf_mbx_close(p_hwfn, p_ptt, p_vf);
3264 break;
3265 case CHANNEL_TLV_INT_CLEANUP:
3266 qed_iov_vf_mbx_int_cleanup(p_hwfn, p_ptt, p_vf);
3267 break;
3268 case CHANNEL_TLV_RELEASE:
3269 qed_iov_vf_mbx_release(p_hwfn, p_ptt, p_vf);
3270 break;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003271 }
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003272 } else if (qed_iov_tlv_supported(mbx->first_tlv.tl.type)) {
3273 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3274 "VF [%02x] - considered malicious; Ignoring TLV [%04x]\n",
3275 p_vf->abs_vf_id, mbx->first_tlv.tl.type);
3276
3277 qed_iov_prepare_resp(p_hwfn, p_ptt, p_vf,
3278 mbx->first_tlv.tl.type,
3279 sizeof(struct pfvf_def_resp_tlv),
3280 PFVF_STATUS_MALICIOUS);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003281 } else {
3282 /* unknown TLV - this may belong to a VF driver from the future
3283 * - a version written after this PF driver was written, which
3284 * supports features unknown as of yet. Too bad since we don't
3285 * support them. Or this may be because someone wrote a crappy
3286 * VF driver and is sending garbage over the channel.
3287 */
Yuval Mintz54fdd802016-06-05 13:11:16 +03003288 DP_NOTICE(p_hwfn,
3289 "VF[%02x]: unknown TLV. type %04x length %04x padding %08x reply address %llu\n",
3290 p_vf->abs_vf_id,
3291 mbx->first_tlv.tl.type,
3292 mbx->first_tlv.tl.length,
3293 mbx->first_tlv.padding, mbx->first_tlv.reply_address);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003294
Yuval Mintz54fdd802016-06-05 13:11:16 +03003295 /* Try replying in case reply address matches the acquisition's
3296 * posted address.
3297 */
3298 if (p_vf->acquire.first_tlv.reply_address &&
3299 (mbx->first_tlv.reply_address ==
3300 p_vf->acquire.first_tlv.reply_address)) {
3301 qed_iov_prepare_resp(p_hwfn, p_ptt, p_vf,
3302 mbx->first_tlv.tl.type,
3303 sizeof(struct pfvf_def_resp_tlv),
3304 PFVF_STATUS_NOT_SUPPORTED);
3305 } else {
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003306 DP_VERBOSE(p_hwfn,
3307 QED_MSG_IOV,
Yuval Mintz54fdd802016-06-05 13:11:16 +03003308 "VF[%02x]: Can't respond to TLV - no valid reply address\n",
3309 p_vf->abs_vf_id);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003310 }
3311 }
3312}
3313
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003314void qed_iov_pf_get_pending_events(struct qed_hwfn *p_hwfn, u64 *events)
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003315{
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003316 int i;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003317
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003318 memset(events, 0, sizeof(u64) * QED_VF_ARRAY_LENGTH);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003319
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003320 qed_for_each_vf(p_hwfn, i) {
3321 struct qed_vf_info *p_vf;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003322
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003323 p_vf = &p_hwfn->pf_iov_info->vfs_array[i];
3324 if (p_vf->vf_mbx.b_pending_msg)
3325 events[i / 64] |= 1ULL << (i % 64);
3326 }
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003327}
3328
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003329static struct qed_vf_info *qed_sriov_get_vf_from_absid(struct qed_hwfn *p_hwfn,
3330 u16 abs_vfid)
3331{
3332 u8 min = (u8) p_hwfn->cdev->p_iov_info->first_vf_in_pf;
3333
3334 if (!_qed_iov_pf_sanity_check(p_hwfn, (int)abs_vfid - min, false)) {
3335 DP_VERBOSE(p_hwfn,
3336 QED_MSG_IOV,
3337 "Got indication for VF [abs 0x%08x] that cannot be handled by PF\n",
3338 abs_vfid);
3339 return NULL;
3340 }
3341
3342 return &p_hwfn->pf_iov_info->vfs_array[(u8) abs_vfid - min];
3343}
3344
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003345static int qed_sriov_vfpf_msg(struct qed_hwfn *p_hwfn,
3346 u16 abs_vfid, struct regpair *vf_msg)
3347{
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003348 struct qed_vf_info *p_vf = qed_sriov_get_vf_from_absid(p_hwfn,
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003349 abs_vfid);
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003350
3351 if (!p_vf)
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003352 return 0;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003353
3354 /* List the physical address of the request so that handler
3355 * could later on copy the message from it.
3356 */
3357 p_vf->vf_mbx.pending_req = (((u64)vf_msg->hi) << 32) | vf_msg->lo;
3358
3359 /* Mark the event and schedule the workqueue */
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02003360 p_vf->vf_mbx.b_pending_msg = true;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003361 qed_schedule_iov(p_hwfn, QED_IOV_WQ_MSG_FLAG);
3362
3363 return 0;
3364}
3365
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003366static void qed_sriov_vfpf_malicious(struct qed_hwfn *p_hwfn,
3367 struct malicious_vf_eqe_data *p_data)
3368{
3369 struct qed_vf_info *p_vf;
3370
3371 p_vf = qed_sriov_get_vf_from_absid(p_hwfn, p_data->vf_id);
3372
3373 if (!p_vf)
3374 return;
3375
3376 DP_INFO(p_hwfn,
3377 "VF [%d] - Malicious behavior [%02x]\n",
3378 p_vf->abs_vf_id, p_data->err_id);
3379
3380 p_vf->b_malicious = true;
3381}
3382
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003383int qed_sriov_eqe_event(struct qed_hwfn *p_hwfn,
3384 u8 opcode, __le16 echo, union event_ring_data *data)
3385{
3386 switch (opcode) {
3387 case COMMON_EVENT_VF_PF_CHANNEL:
3388 return qed_sriov_vfpf_msg(p_hwfn, le16_to_cpu(echo),
3389 &data->vf_pf_channel.msg_addr);
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003390 case COMMON_EVENT_MALICIOUS_VF:
3391 qed_sriov_vfpf_malicious(p_hwfn, &data->malicious_vf);
3392 return 0;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003393 default:
3394 DP_INFO(p_hwfn->cdev, "Unknown sriov eqe event 0x%02x\n",
3395 opcode);
3396 return -EINVAL;
3397 }
3398}
3399
Yuval Mintz32a47e72016-05-11 16:36:12 +03003400u16 qed_iov_get_next_active_vf(struct qed_hwfn *p_hwfn, u16 rel_vf_id)
3401{
3402 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
3403 u16 i;
3404
3405 if (!p_iov)
3406 goto out;
3407
3408 for (i = rel_vf_id; i < p_iov->total_vfs; i++)
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003409 if (qed_iov_is_valid_vfid(p_hwfn, rel_vf_id, true, false))
Yuval Mintz32a47e72016-05-11 16:36:12 +03003410 return i;
3411
3412out:
3413 return MAX_NUM_VFS;
3414}
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003415
3416static int qed_iov_copy_vf_msg(struct qed_hwfn *p_hwfn, struct qed_ptt *ptt,
3417 int vfid)
3418{
3419 struct qed_dmae_params params;
3420 struct qed_vf_info *vf_info;
3421
3422 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3423 if (!vf_info)
3424 return -EINVAL;
3425
3426 memset(&params, 0, sizeof(struct qed_dmae_params));
3427 params.flags = QED_DMAE_FLAG_VF_SRC | QED_DMAE_FLAG_COMPLETION_DST;
3428 params.src_vfid = vf_info->abs_vf_id;
3429
3430 if (qed_dmae_host2host(p_hwfn, ptt,
3431 vf_info->vf_mbx.pending_req,
3432 vf_info->vf_mbx.req_phys,
3433 sizeof(union vfpf_tlvs) / 4, &params)) {
3434 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3435 "Failed to copy message from VF 0x%02x\n", vfid);
3436
3437 return -EIO;
3438 }
3439
3440 return 0;
3441}
3442
Yuval Mintzeff16962016-05-11 16:36:21 +03003443static void qed_iov_bulletin_set_forced_mac(struct qed_hwfn *p_hwfn,
3444 u8 *mac, int vfid)
3445{
3446 struct qed_vf_info *vf_info;
3447 u64 feature;
3448
3449 vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
3450 if (!vf_info) {
3451 DP_NOTICE(p_hwfn->cdev,
3452 "Can not set forced MAC, invalid vfid [%d]\n", vfid);
3453 return;
3454 }
3455
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003456 if (vf_info->b_malicious) {
3457 DP_NOTICE(p_hwfn->cdev,
3458 "Can't set forced MAC to malicious VF [%d]\n", vfid);
3459 return;
3460 }
3461
Yuval Mintzeff16962016-05-11 16:36:21 +03003462 feature = 1 << MAC_ADDR_FORCED;
3463 memcpy(vf_info->bulletin.p_virt->mac, mac, ETH_ALEN);
3464
3465 vf_info->bulletin.p_virt->valid_bitmap |= feature;
3466 /* Forced MAC will disable MAC_ADDR */
Yuval Mintz1a635e42016-08-15 10:42:43 +03003467 vf_info->bulletin.p_virt->valid_bitmap &= ~BIT(VFPF_BULLETIN_MAC_ADDR);
Yuval Mintzeff16962016-05-11 16:36:21 +03003468
3469 qed_iov_configure_vport_forced(p_hwfn, vf_info, feature);
3470}
3471
Baoyou Xieba569472016-09-09 09:21:15 +08003472static void qed_iov_bulletin_set_forced_vlan(struct qed_hwfn *p_hwfn,
3473 u16 pvid, int vfid)
Yuval Mintz08feecd2016-05-11 16:36:20 +03003474{
3475 struct qed_vf_info *vf_info;
3476 u64 feature;
3477
3478 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3479 if (!vf_info) {
3480 DP_NOTICE(p_hwfn->cdev,
3481 "Can not set forced MAC, invalid vfid [%d]\n", vfid);
3482 return;
3483 }
3484
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003485 if (vf_info->b_malicious) {
3486 DP_NOTICE(p_hwfn->cdev,
3487 "Can't set forced vlan to malicious VF [%d]\n", vfid);
3488 return;
3489 }
3490
Yuval Mintz08feecd2016-05-11 16:36:20 +03003491 feature = 1 << VLAN_ADDR_FORCED;
3492 vf_info->bulletin.p_virt->pvid = pvid;
3493 if (pvid)
3494 vf_info->bulletin.p_virt->valid_bitmap |= feature;
3495 else
3496 vf_info->bulletin.p_virt->valid_bitmap &= ~feature;
3497
3498 qed_iov_configure_vport_forced(p_hwfn, vf_info, feature);
3499}
3500
Yuval Mintz6ddc7602016-05-11 16:36:23 +03003501static bool qed_iov_vf_has_vport_instance(struct qed_hwfn *p_hwfn, int vfid)
3502{
3503 struct qed_vf_info *p_vf_info;
3504
3505 p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3506 if (!p_vf_info)
3507 return false;
3508
3509 return !!p_vf_info->vport_instance;
3510}
3511
Baoyou Xieba569472016-09-09 09:21:15 +08003512static bool qed_iov_is_vf_stopped(struct qed_hwfn *p_hwfn, int vfid)
Yuval Mintz0b55e272016-05-11 16:36:15 +03003513{
3514 struct qed_vf_info *p_vf_info;
3515
3516 p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3517 if (!p_vf_info)
3518 return true;
3519
3520 return p_vf_info->state == VF_STOPPED;
3521}
3522
Yuval Mintz73390ac2016-05-11 16:36:24 +03003523static bool qed_iov_spoofchk_get(struct qed_hwfn *p_hwfn, int vfid)
3524{
3525 struct qed_vf_info *vf_info;
3526
3527 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3528 if (!vf_info)
3529 return false;
3530
3531 return vf_info->spoof_chk;
3532}
3533
Baoyou Xieba569472016-09-09 09:21:15 +08003534static int qed_iov_spoofchk_set(struct qed_hwfn *p_hwfn, int vfid, bool val)
Yuval Mintz6ddc7602016-05-11 16:36:23 +03003535{
3536 struct qed_vf_info *vf;
3537 int rc = -EINVAL;
3538
3539 if (!qed_iov_pf_sanity_check(p_hwfn, vfid)) {
3540 DP_NOTICE(p_hwfn,
3541 "SR-IOV sanity check failed, can't set spoofchk\n");
3542 goto out;
3543 }
3544
3545 vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3546 if (!vf)
3547 goto out;
3548
3549 if (!qed_iov_vf_has_vport_instance(p_hwfn, vfid)) {
3550 /* After VF VPORT start PF will configure spoof check */
3551 vf->req_spoofchk_val = val;
3552 rc = 0;
3553 goto out;
3554 }
3555
3556 rc = __qed_iov_spoofchk_set(p_hwfn, vf, val);
3557
3558out:
3559 return rc;
3560}
3561
Yuval Mintzeff16962016-05-11 16:36:21 +03003562static u8 *qed_iov_bulletin_get_forced_mac(struct qed_hwfn *p_hwfn,
3563 u16 rel_vf_id)
3564{
3565 struct qed_vf_info *p_vf;
3566
3567 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
3568 if (!p_vf || !p_vf->bulletin.p_virt)
3569 return NULL;
3570
Yuval Mintz1a635e42016-08-15 10:42:43 +03003571 if (!(p_vf->bulletin.p_virt->valid_bitmap & BIT(MAC_ADDR_FORCED)))
Yuval Mintzeff16962016-05-11 16:36:21 +03003572 return NULL;
3573
3574 return p_vf->bulletin.p_virt->mac;
3575}
3576
Baoyou Xieba569472016-09-09 09:21:15 +08003577static u16
3578qed_iov_bulletin_get_forced_vlan(struct qed_hwfn *p_hwfn, u16 rel_vf_id)
Yuval Mintz08feecd2016-05-11 16:36:20 +03003579{
3580 struct qed_vf_info *p_vf;
3581
3582 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
3583 if (!p_vf || !p_vf->bulletin.p_virt)
3584 return 0;
3585
Yuval Mintz1a635e42016-08-15 10:42:43 +03003586 if (!(p_vf->bulletin.p_virt->valid_bitmap & BIT(VLAN_ADDR_FORCED)))
Yuval Mintz08feecd2016-05-11 16:36:20 +03003587 return 0;
3588
3589 return p_vf->bulletin.p_virt->pvid;
3590}
3591
Yuval Mintz733def62016-05-11 16:36:22 +03003592static int qed_iov_configure_tx_rate(struct qed_hwfn *p_hwfn,
3593 struct qed_ptt *p_ptt, int vfid, int val)
3594{
3595 struct qed_vf_info *vf;
3596 u8 abs_vp_id = 0;
3597 int rc;
3598
3599 vf = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
3600 if (!vf)
3601 return -EINVAL;
3602
3603 rc = qed_fw_vport(p_hwfn, vf->vport_id, &abs_vp_id);
3604 if (rc)
3605 return rc;
3606
3607 return qed_init_vport_rl(p_hwfn, p_ptt, abs_vp_id, (u32)val);
3608}
3609
Baoyou Xieba569472016-09-09 09:21:15 +08003610static int
3611qed_iov_configure_min_tx_rate(struct qed_dev *cdev, int vfid, u32 rate)
Yuval Mintz733def62016-05-11 16:36:22 +03003612{
3613 struct qed_vf_info *vf;
3614 u8 vport_id;
3615 int i;
3616
3617 for_each_hwfn(cdev, i) {
3618 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3619
3620 if (!qed_iov_pf_sanity_check(p_hwfn, vfid)) {
3621 DP_NOTICE(p_hwfn,
3622 "SR-IOV sanity check failed, can't set min rate\n");
3623 return -EINVAL;
3624 }
3625 }
3626
3627 vf = qed_iov_get_vf_info(QED_LEADING_HWFN(cdev), (u16)vfid, true);
3628 vport_id = vf->vport_id;
3629
3630 return qed_configure_vport_wfq(cdev, vport_id, rate);
3631}
3632
Yuval Mintz73390ac2016-05-11 16:36:24 +03003633static int qed_iov_get_vf_min_rate(struct qed_hwfn *p_hwfn, int vfid)
3634{
3635 struct qed_wfq_data *vf_vp_wfq;
3636 struct qed_vf_info *vf_info;
3637
3638 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3639 if (!vf_info)
3640 return 0;
3641
3642 vf_vp_wfq = &p_hwfn->qm_info.wfq_data[vf_info->vport_id];
3643
3644 if (vf_vp_wfq->configured)
3645 return vf_vp_wfq->min_speed;
3646 else
3647 return 0;
3648}
3649
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003650/**
3651 * qed_schedule_iov - schedules IOV task for VF and PF
3652 * @hwfn: hardware function pointer
3653 * @flag: IOV flag for VF/PF
3654 */
3655void qed_schedule_iov(struct qed_hwfn *hwfn, enum qed_iov_wq_flag flag)
3656{
3657 smp_mb__before_atomic();
3658 set_bit(flag, &hwfn->iov_task_flags);
3659 smp_mb__after_atomic();
3660 DP_VERBOSE(hwfn, QED_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag);
3661 queue_delayed_work(hwfn->iov_wq, &hwfn->iov_task, 0);
3662}
3663
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003664void qed_vf_start_iov_wq(struct qed_dev *cdev)
3665{
3666 int i;
3667
3668 for_each_hwfn(cdev, i)
3669 queue_delayed_work(cdev->hwfns[i].iov_wq,
3670 &cdev->hwfns[i].iov_task, 0);
3671}
3672
Yuval Mintz0b55e272016-05-11 16:36:15 +03003673int qed_sriov_disable(struct qed_dev *cdev, bool pci_enabled)
3674{
3675 int i, j;
3676
3677 for_each_hwfn(cdev, i)
3678 if (cdev->hwfns[i].iov_wq)
3679 flush_workqueue(cdev->hwfns[i].iov_wq);
3680
3681 /* Mark VFs for disablement */
3682 qed_iov_set_vfs_to_disable(cdev, true);
3683
3684 if (cdev->p_iov_info && cdev->p_iov_info->num_vfs && pci_enabled)
3685 pci_disable_sriov(cdev->pdev);
3686
3687 for_each_hwfn(cdev, i) {
3688 struct qed_hwfn *hwfn = &cdev->hwfns[i];
3689 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
3690
3691 /* Failure to acquire the ptt in 100g creates an odd error
3692 * where the first engine has already relased IOV.
3693 */
3694 if (!ptt) {
3695 DP_ERR(hwfn, "Failed to acquire ptt\n");
3696 return -EBUSY;
3697 }
3698
Yuval Mintz733def62016-05-11 16:36:22 +03003699 /* Clean WFQ db and configure equal weight for all vports */
3700 qed_clean_wfq_db(hwfn, ptt);
3701
Yuval Mintz0b55e272016-05-11 16:36:15 +03003702 qed_for_each_vf(hwfn, j) {
3703 int k;
3704
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003705 if (!qed_iov_is_valid_vfid(hwfn, j, true, false))
Yuval Mintz0b55e272016-05-11 16:36:15 +03003706 continue;
3707
3708 /* Wait until VF is disabled before releasing */
3709 for (k = 0; k < 100; k++) {
3710 if (!qed_iov_is_vf_stopped(hwfn, j))
3711 msleep(20);
3712 else
3713 break;
3714 }
3715
3716 if (k < 100)
3717 qed_iov_release_hw_for_vf(&cdev->hwfns[i],
3718 ptt, j);
3719 else
3720 DP_ERR(hwfn,
3721 "Timeout waiting for VF's FLR to end\n");
3722 }
3723
3724 qed_ptt_release(hwfn, ptt);
3725 }
3726
3727 qed_iov_set_vfs_to_disable(cdev, false);
3728
3729 return 0;
3730}
3731
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003732static void qed_sriov_enable_qid_config(struct qed_hwfn *hwfn,
3733 u16 vfid,
3734 struct qed_iov_vf_init_params *params)
3735{
3736 u16 base, i;
3737
3738 /* Since we have an equal resource distribution per-VF, and we assume
3739 * PF has acquired the QED_PF_L2_QUE first queues, we start setting
3740 * sequentially from there.
3741 */
3742 base = FEAT_NUM(hwfn, QED_PF_L2_QUE) + vfid * params->num_queues;
3743
3744 params->rel_vf_id = vfid;
3745 for (i = 0; i < params->num_queues; i++) {
3746 params->req_rx_queue[i] = base + i;
3747 params->req_tx_queue[i] = base + i;
3748 }
3749}
3750
Yuval Mintz0b55e272016-05-11 16:36:15 +03003751static int qed_sriov_enable(struct qed_dev *cdev, int num)
3752{
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003753 struct qed_iov_vf_init_params params;
Yuval Mintz0b55e272016-05-11 16:36:15 +03003754 int i, j, rc;
3755
3756 if (num >= RESC_NUM(&cdev->hwfns[0], QED_VPORT)) {
3757 DP_NOTICE(cdev, "Can start at most %d VFs\n",
3758 RESC_NUM(&cdev->hwfns[0], QED_VPORT) - 1);
3759 return -EINVAL;
3760 }
3761
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003762 memset(&params, 0, sizeof(params));
3763
Yuval Mintz0b55e272016-05-11 16:36:15 +03003764 /* Initialize HW for VF access */
3765 for_each_hwfn(cdev, j) {
3766 struct qed_hwfn *hwfn = &cdev->hwfns[j];
3767 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
Mintz, Yuval5a1f9652016-10-31 07:14:26 +02003768
3769 /* Make sure not to use more than 16 queues per VF */
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003770 params.num_queues = min_t(int,
3771 FEAT_NUM(hwfn, QED_VF_L2_QUE) / num,
3772 16);
Yuval Mintz0b55e272016-05-11 16:36:15 +03003773
3774 if (!ptt) {
3775 DP_ERR(hwfn, "Failed to acquire ptt\n");
3776 rc = -EBUSY;
3777 goto err;
3778 }
3779
Yuval Mintz0b55e272016-05-11 16:36:15 +03003780 for (i = 0; i < num; i++) {
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003781 if (!qed_iov_is_valid_vfid(hwfn, i, false, true))
Yuval Mintz0b55e272016-05-11 16:36:15 +03003782 continue;
3783
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003784 qed_sriov_enable_qid_config(hwfn, i, &params);
3785 rc = qed_iov_init_hw_for_vf(hwfn, ptt, &params);
Yuval Mintz0b55e272016-05-11 16:36:15 +03003786 if (rc) {
3787 DP_ERR(cdev, "Failed to enable VF[%d]\n", i);
3788 qed_ptt_release(hwfn, ptt);
3789 goto err;
3790 }
3791 }
3792
3793 qed_ptt_release(hwfn, ptt);
3794 }
3795
3796 /* Enable SRIOV PCIe functions */
3797 rc = pci_enable_sriov(cdev->pdev, num);
3798 if (rc) {
3799 DP_ERR(cdev, "Failed to enable sriov [%d]\n", rc);
3800 goto err;
3801 }
3802
3803 return num;
3804
3805err:
3806 qed_sriov_disable(cdev, false);
3807 return rc;
3808}
3809
3810static int qed_sriov_configure(struct qed_dev *cdev, int num_vfs_param)
3811{
3812 if (!IS_QED_SRIOV(cdev)) {
3813 DP_VERBOSE(cdev, QED_MSG_IOV, "SR-IOV is not supported\n");
3814 return -EOPNOTSUPP;
3815 }
3816
3817 if (num_vfs_param)
3818 return qed_sriov_enable(cdev, num_vfs_param);
3819 else
3820 return qed_sriov_disable(cdev, true);
3821}
3822
Yuval Mintzeff16962016-05-11 16:36:21 +03003823static int qed_sriov_pf_set_mac(struct qed_dev *cdev, u8 *mac, int vfid)
3824{
3825 int i;
3826
3827 if (!IS_QED_SRIOV(cdev) || !IS_PF_SRIOV_ALLOC(&cdev->hwfns[0])) {
3828 DP_VERBOSE(cdev, QED_MSG_IOV,
3829 "Cannot set a VF MAC; Sriov is not enabled\n");
3830 return -EINVAL;
3831 }
3832
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003833 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vfid, true, true)) {
Yuval Mintzeff16962016-05-11 16:36:21 +03003834 DP_VERBOSE(cdev, QED_MSG_IOV,
3835 "Cannot set VF[%d] MAC (VF is not active)\n", vfid);
3836 return -EINVAL;
3837 }
3838
3839 for_each_hwfn(cdev, i) {
3840 struct qed_hwfn *hwfn = &cdev->hwfns[i];
3841 struct qed_public_vf_info *vf_info;
3842
3843 vf_info = qed_iov_get_public_vf_info(hwfn, vfid, true);
3844 if (!vf_info)
3845 continue;
3846
3847 /* Set the forced MAC, and schedule the IOV task */
3848 ether_addr_copy(vf_info->forced_mac, mac);
3849 qed_schedule_iov(hwfn, QED_IOV_WQ_SET_UNICAST_FILTER_FLAG);
3850 }
3851
3852 return 0;
3853}
3854
Yuval Mintz08feecd2016-05-11 16:36:20 +03003855static int qed_sriov_pf_set_vlan(struct qed_dev *cdev, u16 vid, int vfid)
3856{
3857 int i;
3858
3859 if (!IS_QED_SRIOV(cdev) || !IS_PF_SRIOV_ALLOC(&cdev->hwfns[0])) {
3860 DP_VERBOSE(cdev, QED_MSG_IOV,
3861 "Cannot set a VF MAC; Sriov is not enabled\n");
3862 return -EINVAL;
3863 }
3864
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003865 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vfid, true, true)) {
Yuval Mintz08feecd2016-05-11 16:36:20 +03003866 DP_VERBOSE(cdev, QED_MSG_IOV,
3867 "Cannot set VF[%d] MAC (VF is not active)\n", vfid);
3868 return -EINVAL;
3869 }
3870
3871 for_each_hwfn(cdev, i) {
3872 struct qed_hwfn *hwfn = &cdev->hwfns[i];
3873 struct qed_public_vf_info *vf_info;
3874
3875 vf_info = qed_iov_get_public_vf_info(hwfn, vfid, true);
3876 if (!vf_info)
3877 continue;
3878
3879 /* Set the forced vlan, and schedule the IOV task */
3880 vf_info->forced_vlan = vid;
3881 qed_schedule_iov(hwfn, QED_IOV_WQ_SET_UNICAST_FILTER_FLAG);
3882 }
3883
3884 return 0;
3885}
3886
Yuval Mintz73390ac2016-05-11 16:36:24 +03003887static int qed_get_vf_config(struct qed_dev *cdev,
3888 int vf_id, struct ifla_vf_info *ivi)
3889{
3890 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
3891 struct qed_public_vf_info *vf_info;
3892 struct qed_mcp_link_state link;
3893 u32 tx_rate;
3894
3895 /* Sanitize request */
3896 if (IS_VF(cdev))
3897 return -EINVAL;
3898
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003899 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vf_id, true, false)) {
Yuval Mintz73390ac2016-05-11 16:36:24 +03003900 DP_VERBOSE(cdev, QED_MSG_IOV,
3901 "VF index [%d] isn't active\n", vf_id);
3902 return -EINVAL;
3903 }
3904
3905 vf_info = qed_iov_get_public_vf_info(hwfn, vf_id, true);
3906
3907 qed_iov_get_link(hwfn, vf_id, NULL, &link, NULL);
3908
3909 /* Fill information about VF */
3910 ivi->vf = vf_id;
3911
3912 if (is_valid_ether_addr(vf_info->forced_mac))
3913 ether_addr_copy(ivi->mac, vf_info->forced_mac);
3914 else
3915 ether_addr_copy(ivi->mac, vf_info->mac);
3916
3917 ivi->vlan = vf_info->forced_vlan;
3918 ivi->spoofchk = qed_iov_spoofchk_get(hwfn, vf_id);
3919 ivi->linkstate = vf_info->link_state;
3920 tx_rate = vf_info->tx_rate;
3921 ivi->max_tx_rate = tx_rate ? tx_rate : link.speed;
3922 ivi->min_tx_rate = qed_iov_get_vf_min_rate(hwfn, vf_id);
3923
3924 return 0;
3925}
3926
Yuval Mintz36558c32016-05-11 16:36:17 +03003927void qed_inform_vf_link_state(struct qed_hwfn *hwfn)
3928{
3929 struct qed_mcp_link_capabilities caps;
3930 struct qed_mcp_link_params params;
3931 struct qed_mcp_link_state link;
3932 int i;
3933
3934 if (!hwfn->pf_iov_info)
3935 return;
3936
3937 /* Update bulletin of all future possible VFs with link configuration */
3938 for (i = 0; i < hwfn->cdev->p_iov_info->total_vfs; i++) {
Yuval Mintz733def62016-05-11 16:36:22 +03003939 struct qed_public_vf_info *vf_info;
3940
3941 vf_info = qed_iov_get_public_vf_info(hwfn, i, false);
3942 if (!vf_info)
3943 continue;
3944
Yuval Mintz36558c32016-05-11 16:36:17 +03003945 memcpy(&params, qed_mcp_get_link_params(hwfn), sizeof(params));
3946 memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link));
3947 memcpy(&caps, qed_mcp_get_link_capabilities(hwfn),
3948 sizeof(caps));
3949
Yuval Mintz733def62016-05-11 16:36:22 +03003950 /* Modify link according to the VF's configured link state */
3951 switch (vf_info->link_state) {
3952 case IFLA_VF_LINK_STATE_DISABLE:
3953 link.link_up = false;
3954 break;
3955 case IFLA_VF_LINK_STATE_ENABLE:
3956 link.link_up = true;
3957 /* Set speed according to maximum supported by HW.
3958 * that is 40G for regular devices and 100G for CMT
3959 * mode devices.
3960 */
3961 link.speed = (hwfn->cdev->num_hwfns > 1) ?
3962 100000 : 40000;
3963 default:
3964 /* In auto mode pass PF link image to VF */
3965 break;
3966 }
3967
3968 if (link.link_up && vf_info->tx_rate) {
3969 struct qed_ptt *ptt;
3970 int rate;
3971
3972 rate = min_t(int, vf_info->tx_rate, link.speed);
3973
3974 ptt = qed_ptt_acquire(hwfn);
3975 if (!ptt) {
3976 DP_NOTICE(hwfn, "Failed to acquire PTT\n");
3977 return;
3978 }
3979
3980 if (!qed_iov_configure_tx_rate(hwfn, ptt, i, rate)) {
3981 vf_info->tx_rate = rate;
3982 link.speed = rate;
3983 }
3984
3985 qed_ptt_release(hwfn, ptt);
3986 }
3987
Yuval Mintz36558c32016-05-11 16:36:17 +03003988 qed_iov_set_link(hwfn, i, &params, &link, &caps);
3989 }
3990
3991 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
3992}
3993
Yuval Mintz733def62016-05-11 16:36:22 +03003994static int qed_set_vf_link_state(struct qed_dev *cdev,
3995 int vf_id, int link_state)
3996{
3997 int i;
3998
3999 /* Sanitize request */
4000 if (IS_VF(cdev))
4001 return -EINVAL;
4002
Yuval Mintz7eff82b2016-10-14 05:19:22 -04004003 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vf_id, true, true)) {
Yuval Mintz733def62016-05-11 16:36:22 +03004004 DP_VERBOSE(cdev, QED_MSG_IOV,
4005 "VF index [%d] isn't active\n", vf_id);
4006 return -EINVAL;
4007 }
4008
4009 /* Handle configuration of link state */
4010 for_each_hwfn(cdev, i) {
4011 struct qed_hwfn *hwfn = &cdev->hwfns[i];
4012 struct qed_public_vf_info *vf;
4013
4014 vf = qed_iov_get_public_vf_info(hwfn, vf_id, true);
4015 if (!vf)
4016 continue;
4017
4018 if (vf->link_state == link_state)
4019 continue;
4020
4021 vf->link_state = link_state;
4022 qed_inform_vf_link_state(&cdev->hwfns[i]);
4023 }
4024
4025 return 0;
4026}
4027
Yuval Mintz6ddc7602016-05-11 16:36:23 +03004028static int qed_spoof_configure(struct qed_dev *cdev, int vfid, bool val)
4029{
4030 int i, rc = -EINVAL;
4031
4032 for_each_hwfn(cdev, i) {
4033 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4034
4035 rc = qed_iov_spoofchk_set(p_hwfn, vfid, val);
4036 if (rc)
4037 break;
4038 }
4039
4040 return rc;
4041}
4042
Yuval Mintz733def62016-05-11 16:36:22 +03004043static int qed_configure_max_vf_rate(struct qed_dev *cdev, int vfid, int rate)
4044{
4045 int i;
4046
4047 for_each_hwfn(cdev, i) {
4048 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4049 struct qed_public_vf_info *vf;
4050
4051 if (!qed_iov_pf_sanity_check(p_hwfn, vfid)) {
4052 DP_NOTICE(p_hwfn,
4053 "SR-IOV sanity check failed, can't set tx rate\n");
4054 return -EINVAL;
4055 }
4056
4057 vf = qed_iov_get_public_vf_info(p_hwfn, vfid, true);
4058
4059 vf->tx_rate = rate;
4060
4061 qed_inform_vf_link_state(p_hwfn);
4062 }
4063
4064 return 0;
4065}
4066
4067static int qed_set_vf_rate(struct qed_dev *cdev,
4068 int vfid, u32 min_rate, u32 max_rate)
4069{
4070 int rc_min = 0, rc_max = 0;
4071
4072 if (max_rate)
4073 rc_max = qed_configure_max_vf_rate(cdev, vfid, max_rate);
4074
4075 if (min_rate)
4076 rc_min = qed_iov_configure_min_tx_rate(cdev, vfid, min_rate);
4077
4078 if (rc_max | rc_min)
4079 return -EINVAL;
4080
4081 return 0;
4082}
4083
Mintz, Yuvalf990c822017-01-01 13:57:08 +02004084static int qed_set_vf_trust(struct qed_dev *cdev, int vfid, bool trust)
4085{
4086 int i;
4087
4088 for_each_hwfn(cdev, i) {
4089 struct qed_hwfn *hwfn = &cdev->hwfns[i];
4090 struct qed_public_vf_info *vf;
4091
4092 if (!qed_iov_pf_sanity_check(hwfn, vfid)) {
4093 DP_NOTICE(hwfn,
4094 "SR-IOV sanity check failed, can't set trust\n");
4095 return -EINVAL;
4096 }
4097
4098 vf = qed_iov_get_public_vf_info(hwfn, vfid, true);
4099
4100 if (vf->is_trusted_request == trust)
4101 return 0;
4102 vf->is_trusted_request = trust;
4103
4104 qed_schedule_iov(hwfn, QED_IOV_WQ_TRUST_FLAG);
4105 }
4106
4107 return 0;
4108}
4109
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004110static void qed_handle_vf_msg(struct qed_hwfn *hwfn)
4111{
4112 u64 events[QED_VF_ARRAY_LENGTH];
4113 struct qed_ptt *ptt;
4114 int i;
4115
4116 ptt = qed_ptt_acquire(hwfn);
4117 if (!ptt) {
4118 DP_VERBOSE(hwfn, QED_MSG_IOV,
4119 "Can't acquire PTT; re-scheduling\n");
4120 qed_schedule_iov(hwfn, QED_IOV_WQ_MSG_FLAG);
4121 return;
4122 }
4123
Mintz, Yuvalfd3c6152017-02-27 11:06:32 +02004124 qed_iov_pf_get_pending_events(hwfn, events);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004125
4126 DP_VERBOSE(hwfn, QED_MSG_IOV,
4127 "Event mask of VF events: 0x%llx 0x%llx 0x%llx\n",
4128 events[0], events[1], events[2]);
4129
4130 qed_for_each_vf(hwfn, i) {
4131 /* Skip VFs with no pending messages */
4132 if (!(events[i / 64] & (1ULL << (i % 64))))
4133 continue;
4134
4135 DP_VERBOSE(hwfn, QED_MSG_IOV,
4136 "Handling VF message from VF 0x%02x [Abs 0x%02x]\n",
4137 i, hwfn->cdev->p_iov_info->first_vf_in_pf + i);
4138
4139 /* Copy VF's message to PF's request buffer for that VF */
4140 if (qed_iov_copy_vf_msg(hwfn, ptt, i))
4141 continue;
4142
4143 qed_iov_process_mbx_req(hwfn, ptt, i);
4144 }
4145
4146 qed_ptt_release(hwfn, ptt);
4147}
4148
Yuval Mintz08feecd2016-05-11 16:36:20 +03004149static void qed_handle_pf_set_vf_unicast(struct qed_hwfn *hwfn)
4150{
4151 int i;
4152
4153 qed_for_each_vf(hwfn, i) {
4154 struct qed_public_vf_info *info;
4155 bool update = false;
Yuval Mintzeff16962016-05-11 16:36:21 +03004156 u8 *mac;
Yuval Mintz08feecd2016-05-11 16:36:20 +03004157
4158 info = qed_iov_get_public_vf_info(hwfn, i, true);
4159 if (!info)
4160 continue;
4161
4162 /* Update data on bulletin board */
Yuval Mintzeff16962016-05-11 16:36:21 +03004163 mac = qed_iov_bulletin_get_forced_mac(hwfn, i);
4164 if (is_valid_ether_addr(info->forced_mac) &&
4165 (!mac || !ether_addr_equal(mac, info->forced_mac))) {
4166 DP_VERBOSE(hwfn,
4167 QED_MSG_IOV,
4168 "Handling PF setting of VF MAC to VF 0x%02x [Abs 0x%02x]\n",
4169 i,
4170 hwfn->cdev->p_iov_info->first_vf_in_pf + i);
4171
4172 /* Update bulletin board with forced MAC */
4173 qed_iov_bulletin_set_forced_mac(hwfn,
4174 info->forced_mac, i);
4175 update = true;
4176 }
Yuval Mintz08feecd2016-05-11 16:36:20 +03004177
4178 if (qed_iov_bulletin_get_forced_vlan(hwfn, i) ^
4179 info->forced_vlan) {
4180 DP_VERBOSE(hwfn,
4181 QED_MSG_IOV,
4182 "Handling PF setting of pvid [0x%04x] to VF 0x%02x [Abs 0x%02x]\n",
4183 info->forced_vlan,
4184 i,
4185 hwfn->cdev->p_iov_info->first_vf_in_pf + i);
4186 qed_iov_bulletin_set_forced_vlan(hwfn,
4187 info->forced_vlan, i);
4188 update = true;
4189 }
4190
4191 if (update)
4192 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
4193 }
4194}
4195
Yuval Mintz36558c32016-05-11 16:36:17 +03004196static void qed_handle_bulletin_post(struct qed_hwfn *hwfn)
4197{
4198 struct qed_ptt *ptt;
4199 int i;
4200
4201 ptt = qed_ptt_acquire(hwfn);
4202 if (!ptt) {
4203 DP_NOTICE(hwfn, "Failed allocating a ptt entry\n");
4204 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
4205 return;
4206 }
4207
4208 qed_for_each_vf(hwfn, i)
4209 qed_iov_post_vf_bulletin(hwfn, i, ptt);
4210
4211 qed_ptt_release(hwfn, ptt);
4212}
4213
Mintz, Yuvalf990c822017-01-01 13:57:08 +02004214static void qed_iov_handle_trust_change(struct qed_hwfn *hwfn)
4215{
4216 struct qed_sp_vport_update_params params;
4217 struct qed_filter_accept_flags *flags;
4218 struct qed_public_vf_info *vf_info;
4219 struct qed_vf_info *vf;
4220 u8 mask;
4221 int i;
4222
4223 mask = QED_ACCEPT_UCAST_UNMATCHED | QED_ACCEPT_MCAST_UNMATCHED;
4224 flags = &params.accept_flags;
4225
4226 qed_for_each_vf(hwfn, i) {
4227 /* Need to make sure current requested configuration didn't
4228 * flip so that we'll end up configuring something that's not
4229 * needed.
4230 */
4231 vf_info = qed_iov_get_public_vf_info(hwfn, i, true);
4232 if (vf_info->is_trusted_configured ==
4233 vf_info->is_trusted_request)
4234 continue;
4235 vf_info->is_trusted_configured = vf_info->is_trusted_request;
4236
4237 /* Validate that the VF has a configured vport */
4238 vf = qed_iov_get_vf_info(hwfn, i, true);
4239 if (!vf->vport_instance)
4240 continue;
4241
4242 memset(&params, 0, sizeof(params));
4243 params.opaque_fid = vf->opaque_fid;
4244 params.vport_id = vf->vport_id;
4245
4246 if (vf_info->rx_accept_mode & mask) {
4247 flags->update_rx_mode_config = 1;
4248 flags->rx_accept_filter = vf_info->rx_accept_mode;
4249 }
4250
4251 if (vf_info->tx_accept_mode & mask) {
4252 flags->update_tx_mode_config = 1;
4253 flags->tx_accept_filter = vf_info->tx_accept_mode;
4254 }
4255
4256 /* Remove if needed; Otherwise this would set the mask */
4257 if (!vf_info->is_trusted_configured) {
4258 flags->rx_accept_filter &= ~mask;
4259 flags->tx_accept_filter &= ~mask;
4260 }
4261
4262 if (flags->update_rx_mode_config ||
4263 flags->update_tx_mode_config)
4264 qed_sp_vport_update(hwfn, &params,
4265 QED_SPQ_MODE_EBLOCK, NULL);
4266 }
4267}
4268
Baoyou Xieba569472016-09-09 09:21:15 +08004269static void qed_iov_pf_task(struct work_struct *work)
4270
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004271{
4272 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
4273 iov_task.work);
Yuval Mintz0b55e272016-05-11 16:36:15 +03004274 int rc;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004275
4276 if (test_and_clear_bit(QED_IOV_WQ_STOP_WQ_FLAG, &hwfn->iov_task_flags))
4277 return;
4278
Yuval Mintz0b55e272016-05-11 16:36:15 +03004279 if (test_and_clear_bit(QED_IOV_WQ_FLR_FLAG, &hwfn->iov_task_flags)) {
4280 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
4281
4282 if (!ptt) {
4283 qed_schedule_iov(hwfn, QED_IOV_WQ_FLR_FLAG);
4284 return;
4285 }
4286
4287 rc = qed_iov_vf_flr_cleanup(hwfn, ptt);
4288 if (rc)
4289 qed_schedule_iov(hwfn, QED_IOV_WQ_FLR_FLAG);
4290
4291 qed_ptt_release(hwfn, ptt);
4292 }
4293
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004294 if (test_and_clear_bit(QED_IOV_WQ_MSG_FLAG, &hwfn->iov_task_flags))
4295 qed_handle_vf_msg(hwfn);
Yuval Mintz08feecd2016-05-11 16:36:20 +03004296
4297 if (test_and_clear_bit(QED_IOV_WQ_SET_UNICAST_FILTER_FLAG,
4298 &hwfn->iov_task_flags))
4299 qed_handle_pf_set_vf_unicast(hwfn);
4300
Yuval Mintz36558c32016-05-11 16:36:17 +03004301 if (test_and_clear_bit(QED_IOV_WQ_BULLETIN_UPDATE_FLAG,
4302 &hwfn->iov_task_flags))
4303 qed_handle_bulletin_post(hwfn);
Mintz, Yuvalf990c822017-01-01 13:57:08 +02004304
4305 if (test_and_clear_bit(QED_IOV_WQ_TRUST_FLAG, &hwfn->iov_task_flags))
4306 qed_iov_handle_trust_change(hwfn);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004307}
4308
4309void qed_iov_wq_stop(struct qed_dev *cdev, bool schedule_first)
4310{
4311 int i;
4312
4313 for_each_hwfn(cdev, i) {
4314 if (!cdev->hwfns[i].iov_wq)
4315 continue;
4316
4317 if (schedule_first) {
4318 qed_schedule_iov(&cdev->hwfns[i],
4319 QED_IOV_WQ_STOP_WQ_FLAG);
4320 cancel_delayed_work_sync(&cdev->hwfns[i].iov_task);
4321 }
4322
4323 flush_workqueue(cdev->hwfns[i].iov_wq);
4324 destroy_workqueue(cdev->hwfns[i].iov_wq);
4325 }
4326}
4327
4328int qed_iov_wq_start(struct qed_dev *cdev)
4329{
4330 char name[NAME_SIZE];
4331 int i;
4332
4333 for_each_hwfn(cdev, i) {
4334 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4335
Yuval Mintz36558c32016-05-11 16:36:17 +03004336 /* PFs needs a dedicated workqueue only if they support IOV.
4337 * VFs always require one.
4338 */
4339 if (IS_PF(p_hwfn->cdev) && !IS_PF_SRIOV(p_hwfn))
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004340 continue;
4341
4342 snprintf(name, NAME_SIZE, "iov-%02x:%02x.%02x",
4343 cdev->pdev->bus->number,
4344 PCI_SLOT(cdev->pdev->devfn), p_hwfn->abs_pf_id);
4345
4346 p_hwfn->iov_wq = create_singlethread_workqueue(name);
4347 if (!p_hwfn->iov_wq) {
4348 DP_NOTICE(p_hwfn, "Cannot create iov workqueue\n");
4349 return -ENOMEM;
4350 }
4351
Yuval Mintz36558c32016-05-11 16:36:17 +03004352 if (IS_PF(cdev))
4353 INIT_DELAYED_WORK(&p_hwfn->iov_task, qed_iov_pf_task);
4354 else
4355 INIT_DELAYED_WORK(&p_hwfn->iov_task, qed_iov_vf_task);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004356 }
4357
4358 return 0;
4359}
Yuval Mintz0b55e272016-05-11 16:36:15 +03004360
4361const struct qed_iov_hv_ops qed_iov_ops_pass = {
4362 .configure = &qed_sriov_configure,
Yuval Mintzeff16962016-05-11 16:36:21 +03004363 .set_mac = &qed_sriov_pf_set_mac,
Yuval Mintz08feecd2016-05-11 16:36:20 +03004364 .set_vlan = &qed_sriov_pf_set_vlan,
Yuval Mintz73390ac2016-05-11 16:36:24 +03004365 .get_config = &qed_get_vf_config,
Yuval Mintz733def62016-05-11 16:36:22 +03004366 .set_link_state = &qed_set_vf_link_state,
Yuval Mintz6ddc7602016-05-11 16:36:23 +03004367 .set_spoof = &qed_spoof_configure,
Yuval Mintz733def62016-05-11 16:36:22 +03004368 .set_rate = &qed_set_vf_rate,
Mintz, Yuvalf990c822017-01-01 13:57:08 +02004369 .set_trust = &qed_set_vf_trust,
Yuval Mintz0b55e272016-05-11 16:36:15 +03004370};