Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * drivers/net/ethernet/mellanox/mlxsw/spectrum.h |
| 3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. |
| 4 | * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> |
| 5 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> |
| 6 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions are met: |
| 10 | * |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. Neither the names of the copyright holders nor the names of its |
| 17 | * contributors may be used to endorse or promote products derived from |
| 18 | * this software without specific prior written permission. |
| 19 | * |
| 20 | * Alternatively, this software may be distributed under the terms of the |
| 21 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 22 | * Software Foundation. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 34 | * POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | |
| 37 | #ifndef _MLXSW_SPECTRUM_H |
| 38 | #define _MLXSW_SPECTRUM_H |
| 39 | |
| 40 | #include <linux/types.h> |
| 41 | #include <linux/netdevice.h> |
Jiri Pirko | 6cf3c97 | 2016-07-05 11:27:39 +0200 | [diff] [blame] | 42 | #include <linux/rhashtable.h> |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 43 | #include <linux/bitops.h> |
| 44 | #include <linux/if_vlan.h> |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 45 | #include <linux/list.h> |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 46 | #include <linux/dcbnl.h> |
Jiri Pirko | 5e9c16c | 2016-07-04 08:23:04 +0200 | [diff] [blame] | 47 | #include <linux/in6.h> |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 48 | #include <net/switchdev.h> |
| 49 | |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 50 | #include "port.h" |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 51 | #include "core.h" |
| 52 | |
| 53 | #define MLXSW_SP_VFID_BASE VLAN_N_VID |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 54 | #define MLXSW_SP_VFID_MAX 6656 /* Bridged VLAN interfaces */ |
| 55 | |
| 56 | #define MLXSW_SP_RFID_BASE 15360 |
| 57 | #define MLXSW_SP_RIF_MAX 800 |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 58 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 59 | #define MLXSW_SP_LAG_MAX 64 |
| 60 | #define MLXSW_SP_PORT_PER_LAG_MAX 16 |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 61 | |
Elad Raz | 53ae628 | 2016-01-10 21:06:26 +0100 | [diff] [blame] | 62 | #define MLXSW_SP_MID_MAX 7000 |
| 63 | |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 64 | #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4 |
| 65 | |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 66 | #define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */ |
| 67 | #define MLXSW_SP_LPM_TREE_MAX 22 |
| 68 | #define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN) |
| 69 | |
Jiri Pirko | 6b75c48 | 2016-07-04 08:23:09 +0200 | [diff] [blame] | 70 | #define MLXSW_SP_VIRTUAL_ROUTER_MAX 256 |
| 71 | |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 72 | #define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */ |
| 73 | |
Ido Schimmel | 1a19844 | 2016-04-06 17:10:02 +0200 | [diff] [blame] | 74 | #define MLXSW_SP_BYTES_PER_CELL 96 |
| 75 | |
| 76 | #define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL) |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 77 | #define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL) |
Ido Schimmel | 1a19844 | 2016-04-06 17:10:02 +0200 | [diff] [blame] | 78 | |
Jiri Pirko | c602242 | 2016-07-05 11:27:46 +0200 | [diff] [blame] | 79 | #define MLXSW_SP_KVD_LINEAR_SIZE 65536 /* entries */ |
| 80 | #define MLXSW_SP_KVD_HASH_SINGLE_SIZE 163840 /* entries */ |
| 81 | #define MLXSW_SP_KVD_HASH_DOUBLE_SIZE 32768 /* entries */ |
| 82 | |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 83 | /* Maximum delay buffer needed in case of PAUSE frames, in cells. |
| 84 | * Assumes 100m cable and maximum MTU. |
| 85 | */ |
| 86 | #define MLXSW_SP_PAUSE_DELAY 612 |
| 87 | |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 88 | #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ |
| 89 | |
| 90 | static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay) |
| 91 | { |
| 92 | delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE)); |
| 93 | return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu); |
| 94 | } |
| 95 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 96 | struct mlxsw_sp_port; |
| 97 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 98 | struct mlxsw_sp_upper { |
| 99 | struct net_device *dev; |
| 100 | unsigned int ref_count; |
| 101 | }; |
| 102 | |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 103 | struct mlxsw_sp_fid { |
Ido Schimmel | 1c80075 | 2016-06-20 23:04:20 +0200 | [diff] [blame] | 104 | void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport); |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 105 | struct list_head list; |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 106 | unsigned int ref_count; |
| 107 | struct net_device *dev; |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 108 | struct mlxsw_sp_rif *r; |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 109 | u16 fid; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 110 | }; |
| 111 | |
Ido Schimmel | fa3054f | 2016-07-02 11:00:16 +0200 | [diff] [blame] | 112 | struct mlxsw_sp_rif { |
| 113 | struct net_device *dev; |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 114 | unsigned int ref_count; |
Ido Schimmel | 6e095fd | 2016-07-04 08:23:13 +0200 | [diff] [blame] | 115 | struct mlxsw_sp_fid *f; |
| 116 | unsigned char addr[ETH_ALEN]; |
| 117 | int mtu; |
Ido Schimmel | fa3054f | 2016-07-02 11:00:16 +0200 | [diff] [blame] | 118 | u16 rif; |
| 119 | }; |
| 120 | |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 121 | struct mlxsw_sp_mid { |
| 122 | struct list_head list; |
| 123 | unsigned char addr[ETH_ALEN]; |
| 124 | u16 vid; |
| 125 | u16 mid; |
| 126 | unsigned int ref_count; |
| 127 | }; |
| 128 | |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 129 | static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid) |
| 130 | { |
| 131 | return MLXSW_SP_VFID_BASE + vfid; |
| 132 | } |
| 133 | |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 134 | static inline u16 mlxsw_sp_fid_to_vfid(u16 fid) |
| 135 | { |
| 136 | return fid - MLXSW_SP_VFID_BASE; |
| 137 | } |
| 138 | |
| 139 | static inline bool mlxsw_sp_fid_is_vfid(u16 fid) |
| 140 | { |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 141 | return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE; |
| 142 | } |
| 143 | |
| 144 | static inline bool mlxsw_sp_fid_is_rfid(u16 fid) |
| 145 | { |
| 146 | return fid >= MLXSW_SP_RFID_BASE; |
| 147 | } |
| 148 | |
| 149 | static inline u16 mlxsw_sp_rif_sp_to_fid(u16 rif) |
| 150 | { |
| 151 | return MLXSW_SP_RFID_BASE + rif; |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 152 | } |
| 153 | |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 154 | struct mlxsw_sp_sb_pr { |
| 155 | enum mlxsw_reg_sbpr_mode mode; |
| 156 | u32 size; |
| 157 | }; |
| 158 | |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 159 | struct mlxsw_cp_sb_occ { |
| 160 | u32 cur; |
| 161 | u32 max; |
| 162 | }; |
| 163 | |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 164 | struct mlxsw_sp_sb_cm { |
| 165 | u32 min_buff; |
| 166 | u32 max_buff; |
| 167 | u8 pool; |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 168 | struct mlxsw_cp_sb_occ occ; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 169 | }; |
| 170 | |
| 171 | struct mlxsw_sp_sb_pm { |
| 172 | u32 min_buff; |
| 173 | u32 max_buff; |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 174 | struct mlxsw_cp_sb_occ occ; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 175 | }; |
| 176 | |
| 177 | #define MLXSW_SP_SB_POOL_COUNT 4 |
| 178 | #define MLXSW_SP_SB_TC_COUNT 8 |
| 179 | |
| 180 | struct mlxsw_sp_sb { |
| 181 | struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT]; |
| 182 | struct { |
| 183 | struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT]; |
| 184 | struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT]; |
| 185 | } ports[MLXSW_PORT_MAX_PORTS]; |
| 186 | }; |
| 187 | |
Jiri Pirko | 5e9c16c | 2016-07-04 08:23:04 +0200 | [diff] [blame] | 188 | #define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE) |
| 189 | |
| 190 | struct mlxsw_sp_prefix_usage { |
| 191 | DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT); |
| 192 | }; |
| 193 | |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 194 | enum mlxsw_sp_l3proto { |
| 195 | MLXSW_SP_L3_PROTO_IPV4, |
| 196 | MLXSW_SP_L3_PROTO_IPV6, |
| 197 | }; |
| 198 | |
| 199 | struct mlxsw_sp_lpm_tree { |
| 200 | u8 id; /* tree ID */ |
| 201 | unsigned int ref_count; |
| 202 | enum mlxsw_sp_l3proto proto; |
| 203 | struct mlxsw_sp_prefix_usage prefix_usage; |
| 204 | }; |
| 205 | |
Jiri Pirko | 6b75c48 | 2016-07-04 08:23:09 +0200 | [diff] [blame] | 206 | struct mlxsw_sp_fib; |
| 207 | |
| 208 | struct mlxsw_sp_vr { |
| 209 | u16 id; /* virtual router ID */ |
| 210 | bool used; |
| 211 | enum mlxsw_sp_l3proto proto; |
| 212 | u32 tb_id; /* kernel fib table id */ |
| 213 | struct mlxsw_sp_lpm_tree *lpm_tree; |
| 214 | struct mlxsw_sp_fib *fib; |
| 215 | }; |
| 216 | |
Yotam Gigi | 763b4b7 | 2016-07-21 12:03:17 +0200 | [diff] [blame] | 217 | enum mlxsw_sp_span_type { |
| 218 | MLXSW_SP_SPAN_EGRESS, |
| 219 | MLXSW_SP_SPAN_INGRESS |
| 220 | }; |
| 221 | |
| 222 | struct mlxsw_sp_span_inspected_port { |
| 223 | struct list_head list; |
| 224 | enum mlxsw_sp_span_type type; |
| 225 | u8 local_port; |
| 226 | }; |
| 227 | |
| 228 | struct mlxsw_sp_span_entry { |
| 229 | u8 local_port; |
| 230 | bool used; |
| 231 | struct list_head bound_ports_list; |
| 232 | int ref_count; |
| 233 | int id; |
| 234 | }; |
| 235 | |
| 236 | enum mlxsw_sp_port_mall_action_type { |
| 237 | MLXSW_SP_PORT_MALL_MIRROR, |
| 238 | }; |
| 239 | |
| 240 | struct mlxsw_sp_port_mall_mirror_tc_entry { |
| 241 | u8 to_local_port; |
| 242 | bool ingress; |
| 243 | }; |
| 244 | |
| 245 | struct mlxsw_sp_port_mall_tc_entry { |
| 246 | struct list_head list; |
| 247 | unsigned long cookie; |
| 248 | enum mlxsw_sp_port_mall_action_type type; |
| 249 | union { |
| 250 | struct mlxsw_sp_port_mall_mirror_tc_entry mirror; |
| 251 | }; |
| 252 | }; |
| 253 | |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 254 | struct mlxsw_sp_router { |
| 255 | struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT]; |
Jiri Pirko | 6b75c48 | 2016-07-04 08:23:09 +0200 | [diff] [blame] | 256 | struct mlxsw_sp_vr vrs[MLXSW_SP_VIRTUAL_ROUTER_MAX]; |
Jiri Pirko | 6cf3c97 | 2016-07-05 11:27:39 +0200 | [diff] [blame] | 257 | struct rhashtable neigh_ht; |
Yotam Gigi | c723c735 | 2016-07-05 11:27:43 +0200 | [diff] [blame] | 258 | struct { |
| 259 | struct delayed_work dw; |
| 260 | unsigned long interval; /* ms */ |
| 261 | } neighs_update; |
Yotam Gigi | 0b2361d | 2016-07-05 11:27:52 +0200 | [diff] [blame] | 262 | struct delayed_work nexthop_probe_dw; |
| 263 | #define MLXSW_SP_UNRESOLVED_NH_PROBE_INTERVAL 5000 /* ms */ |
Jiri Pirko | a7ff87a | 2016-07-05 11:27:50 +0200 | [diff] [blame] | 264 | struct list_head nexthop_group_list; |
Yotam Gigi | b215714 | 2016-07-05 11:27:51 +0200 | [diff] [blame] | 265 | struct list_head nexthop_neighs_list; |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 266 | }; |
| 267 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 268 | struct mlxsw_sp { |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 269 | struct { |
| 270 | struct list_head list; |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 271 | DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX); |
Ido Schimmel | 3ba2ebf | 2016-07-04 08:23:15 +0200 | [diff] [blame] | 272 | } vfids; |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 273 | struct { |
| 274 | struct list_head list; |
Ido Schimmel | d8651fd | 2016-06-20 23:04:07 +0200 | [diff] [blame] | 275 | DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX); |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 276 | } br_mids; |
Ido Schimmel | 14d3946 | 2016-06-20 23:04:15 +0200 | [diff] [blame] | 277 | struct list_head fids; /* VLAN-aware bridge FIDs */ |
Ido Schimmel | fa3054f | 2016-07-02 11:00:16 +0200 | [diff] [blame] | 278 | struct mlxsw_sp_rif *rifs[MLXSW_SP_RIF_MAX]; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 279 | struct mlxsw_sp_port **ports; |
| 280 | struct mlxsw_core *core; |
| 281 | const struct mlxsw_bus_info *bus_info; |
| 282 | unsigned char base_mac[ETH_ALEN]; |
| 283 | struct { |
| 284 | struct delayed_work dw; |
| 285 | #define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100 |
| 286 | unsigned int interval; /* ms */ |
| 287 | } fdb_notify; |
Ido Schimmel | 869f63a | 2016-03-08 12:59:33 -0800 | [diff] [blame] | 288 | #define MLXSW_SP_MIN_AGEING_TIME 10 |
| 289 | #define MLXSW_SP_MAX_AGEING_TIME 1000000 |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 290 | #define MLXSW_SP_DEFAULT_AGEING_TIME 300 |
| 291 | u32 ageing_time; |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 292 | struct mlxsw_sp_upper master_bridge; |
| 293 | struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX]; |
Ido Schimmel | 558c2d5 | 2016-02-26 17:32:29 +0100 | [diff] [blame] | 294 | u8 port_to_module[MLXSW_PORT_MAX_PORTS]; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 295 | struct mlxsw_sp_sb sb; |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 296 | struct mlxsw_sp_router router; |
Jiri Pirko | b090ef0 | 2016-07-05 11:27:47 +0200 | [diff] [blame] | 297 | struct { |
| 298 | DECLARE_BITMAP(usage, MLXSW_SP_KVD_LINEAR_SIZE); |
| 299 | } kvdl; |
Yotam Gigi | 763b4b7 | 2016-07-21 12:03:17 +0200 | [diff] [blame] | 300 | |
| 301 | struct { |
| 302 | struct mlxsw_sp_span_entry *entries; |
| 303 | int entries_count; |
| 304 | } span; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 305 | }; |
| 306 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 307 | static inline struct mlxsw_sp_upper * |
| 308 | mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id) |
| 309 | { |
| 310 | return &mlxsw_sp->lags[lag_id]; |
| 311 | } |
| 312 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 313 | struct mlxsw_sp_port_pcpu_stats { |
| 314 | u64 rx_packets; |
| 315 | u64 rx_bytes; |
| 316 | u64 tx_packets; |
| 317 | u64 tx_bytes; |
| 318 | struct u64_stats_sync syncp; |
| 319 | u32 tx_dropped; |
| 320 | }; |
| 321 | |
| 322 | struct mlxsw_sp_port { |
Jiri Pirko | 932762b | 2016-04-08 19:11:21 +0200 | [diff] [blame] | 323 | struct mlxsw_core_port core_port; /* must be first */ |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 324 | struct net_device *dev; |
| 325 | struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats; |
| 326 | struct mlxsw_sp *mlxsw_sp; |
| 327 | u8 local_port; |
| 328 | u8 stp_state; |
Jiri Pirko | 0d9b970 | 2015-10-28 10:16:56 +0100 | [diff] [blame] | 329 | u8 learning:1, |
| 330 | learning_sync:1, |
Ido Schimmel | 0293038 | 2015-10-28 10:16:58 +0100 | [diff] [blame] | 331 | uc_flood:1, |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 332 | bridged:1, |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 333 | lagged:1, |
| 334 | split:1; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 335 | u16 pvid; |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 336 | u16 lag_id; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 337 | struct { |
| 338 | struct list_head list; |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 339 | struct mlxsw_sp_fid *f; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 340 | u16 vid; |
| 341 | } vport; |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 342 | struct { |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 343 | u8 tx_pause:1, |
| 344 | rx_pause:1; |
| 345 | } link; |
| 346 | struct { |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 347 | struct ieee_ets *ets; |
Ido Schimmel | cc7cf51 | 2016-04-06 17:10:11 +0200 | [diff] [blame] | 348 | struct ieee_maxrate *maxrate; |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 349 | struct ieee_pfc *pfc; |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 350 | } dcb; |
Ido Schimmel | d664b41 | 2016-06-09 09:51:40 +0200 | [diff] [blame] | 351 | struct { |
| 352 | u8 module; |
| 353 | u8 width; |
| 354 | u8 lane; |
| 355 | } mapping; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 356 | /* 802.1Q bridge VLANs */ |
Ido Schimmel | bd40e9d | 2015-12-15 16:03:36 +0100 | [diff] [blame] | 357 | unsigned long *active_vlans; |
Elad Raz | fc1273a | 2016-01-06 13:01:11 +0100 | [diff] [blame] | 358 | unsigned long *untagged_vlans; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 359 | /* VLAN interfaces */ |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 360 | struct list_head vports_list; |
Yotam Gigi | 763b4b7 | 2016-07-21 12:03:17 +0200 | [diff] [blame] | 361 | /* TC handles */ |
| 362 | struct list_head mall_tc_list; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 363 | }; |
| 364 | |
Jiri Pirko | 7ce856a | 2016-07-04 08:23:12 +0200 | [diff] [blame] | 365 | struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev); |
| 366 | void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port); |
| 367 | |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 368 | static inline bool |
| 369 | mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port) |
| 370 | { |
| 371 | return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause; |
| 372 | } |
| 373 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 374 | static inline struct mlxsw_sp_port * |
| 375 | mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index) |
| 376 | { |
| 377 | struct mlxsw_sp_port *mlxsw_sp_port; |
| 378 | u8 local_port; |
| 379 | |
| 380 | local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core, |
| 381 | lag_id, port_index); |
| 382 | mlxsw_sp_port = mlxsw_sp->ports[local_port]; |
| 383 | return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL; |
| 384 | } |
| 385 | |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 386 | static inline u16 |
| 387 | mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
| 388 | { |
| 389 | return mlxsw_sp_vport->vport.vid; |
| 390 | } |
| 391 | |
Ido Schimmel | 6381b3a | 2016-06-20 23:04:16 +0200 | [diff] [blame] | 392 | static inline bool |
| 393 | mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port) |
| 394 | { |
| 395 | u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port); |
| 396 | |
| 397 | return vid != 0; |
| 398 | } |
| 399 | |
Ido Schimmel | 41b996c | 2016-06-20 23:04:17 +0200 | [diff] [blame] | 400 | static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport, |
| 401 | struct mlxsw_sp_fid *f) |
| 402 | { |
| 403 | mlxsw_sp_vport->vport.f = f; |
| 404 | } |
| 405 | |
| 406 | static inline struct mlxsw_sp_fid * |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 407 | mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 408 | { |
Ido Schimmel | 41b996c | 2016-06-20 23:04:17 +0200 | [diff] [blame] | 409 | return mlxsw_sp_vport->vport.f; |
| 410 | } |
| 411 | |
| 412 | static inline struct net_device * |
Ido Schimmel | 3ba2ebf | 2016-07-04 08:23:15 +0200 | [diff] [blame] | 413 | mlxsw_sp_vport_dev_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
Ido Schimmel | 41b996c | 2016-06-20 23:04:17 +0200 | [diff] [blame] | 414 | { |
| 415 | struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport); |
| 416 | |
Ido Schimmel | 56918b6 | 2016-06-20 23:04:18 +0200 | [diff] [blame] | 417 | return f ? f->dev : NULL; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 418 | } |
| 419 | |
| 420 | static inline struct mlxsw_sp_port * |
| 421 | mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) |
| 422 | { |
| 423 | struct mlxsw_sp_port *mlxsw_sp_vport; |
| 424 | |
| 425 | list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list, |
| 426 | vport.list) { |
| 427 | if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid) |
| 428 | return mlxsw_sp_vport; |
| 429 | } |
| 430 | |
| 431 | return NULL; |
| 432 | } |
| 433 | |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 434 | static inline struct mlxsw_sp_port * |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 435 | mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port, |
| 436 | u16 fid) |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 437 | { |
| 438 | struct mlxsw_sp_port *mlxsw_sp_vport; |
| 439 | |
| 440 | list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list, |
| 441 | vport.list) { |
Ido Schimmel | 41b996c | 2016-06-20 23:04:17 +0200 | [diff] [blame] | 442 | struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport); |
| 443 | |
Ido Schimmel | 56918b6 | 2016-06-20 23:04:18 +0200 | [diff] [blame] | 444 | if (f && f->fid == fid) |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 445 | return mlxsw_sp_vport; |
| 446 | } |
| 447 | |
| 448 | return NULL; |
| 449 | } |
| 450 | |
Ido Schimmel | 701b186 | 2016-07-04 08:23:16 +0200 | [diff] [blame] | 451 | static inline struct mlxsw_sp_fid *mlxsw_sp_fid_find(struct mlxsw_sp *mlxsw_sp, |
| 452 | u16 fid) |
| 453 | { |
| 454 | struct mlxsw_sp_fid *f; |
| 455 | |
| 456 | list_for_each_entry(f, &mlxsw_sp->fids, list) |
| 457 | if (f->fid == fid) |
| 458 | return f; |
| 459 | |
| 460 | return NULL; |
| 461 | } |
| 462 | |
| 463 | static inline struct mlxsw_sp_fid * |
| 464 | mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, |
| 465 | const struct net_device *br_dev) |
| 466 | { |
| 467 | struct mlxsw_sp_fid *f; |
| 468 | |
| 469 | list_for_each_entry(f, &mlxsw_sp->vfids.list, list) |
| 470 | if (f->dev == br_dev) |
| 471 | return f; |
| 472 | |
| 473 | return NULL; |
| 474 | } |
| 475 | |
Ido Schimmel | fa3054f | 2016-07-02 11:00:16 +0200 | [diff] [blame] | 476 | static inline struct mlxsw_sp_rif * |
| 477 | mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp, |
| 478 | const struct net_device *dev) |
| 479 | { |
| 480 | int i; |
| 481 | |
| 482 | for (i = 0; i < MLXSW_SP_RIF_MAX; i++) |
| 483 | if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev) |
| 484 | return mlxsw_sp->rifs[i]; |
| 485 | |
| 486 | return NULL; |
| 487 | } |
| 488 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 489 | enum mlxsw_sp_flood_table { |
| 490 | MLXSW_SP_FLOOD_TABLE_UC, |
| 491 | MLXSW_SP_FLOOD_TABLE_BM, |
| 492 | }; |
| 493 | |
| 494 | int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp); |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 495 | void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 496 | int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port); |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 497 | int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core, |
| 498 | unsigned int sb_index, u16 pool_index, |
| 499 | struct devlink_sb_pool_info *pool_info); |
| 500 | int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core, |
| 501 | unsigned int sb_index, u16 pool_index, u32 size, |
| 502 | enum devlink_sb_threshold_type threshold_type); |
| 503 | int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port, |
| 504 | unsigned int sb_index, u16 pool_index, |
| 505 | u32 *p_threshold); |
| 506 | int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port, |
| 507 | unsigned int sb_index, u16 pool_index, |
| 508 | u32 threshold); |
| 509 | int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port, |
| 510 | unsigned int sb_index, u16 tc_index, |
| 511 | enum devlink_sb_pool_type pool_type, |
| 512 | u16 *p_pool_index, u32 *p_threshold); |
| 513 | int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port, |
| 514 | unsigned int sb_index, u16 tc_index, |
| 515 | enum devlink_sb_pool_type pool_type, |
| 516 | u16 pool_index, u32 threshold); |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 517 | int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core, |
| 518 | unsigned int sb_index); |
| 519 | int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core, |
| 520 | unsigned int sb_index); |
| 521 | int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port, |
| 522 | unsigned int sb_index, u16 pool_index, |
| 523 | u32 *p_cur, u32 *p_max); |
| 524 | int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port, |
| 525 | unsigned int sb_index, u16 tc_index, |
| 526 | enum devlink_sb_pool_type pool_type, |
| 527 | u32 *p_cur, u32 *p_max); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 528 | |
| 529 | int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp); |
| 530 | void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp); |
| 531 | int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 532 | void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 533 | void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port); |
| 534 | int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 535 | enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid, |
| 536 | u16 vid); |
| 537 | int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, |
| 538 | u16 vid_end, bool is_member, bool untagged); |
Ido Schimmel | e606002 | 2016-06-20 23:04:11 +0200 | [diff] [blame] | 539 | int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid, |
Ido Schimmel | 47a0a9e | 2016-06-20 23:04:08 +0200 | [diff] [blame] | 540 | bool set); |
Ido Schimmel | 4dc236c | 2016-01-27 15:20:16 +0100 | [diff] [blame] | 541 | void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port); |
Ido Schimmel | 28a01d2 | 2016-02-18 11:30:02 +0100 | [diff] [blame] | 542 | int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid); |
Ido Schimmel | fe3f6d1 | 2016-06-20 23:04:19 +0200 | [diff] [blame] | 543 | int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid); |
Ido Schimmel | 6e095fd | 2016-07-04 08:23:13 +0200 | [diff] [blame] | 544 | int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid, |
| 545 | bool adding); |
Ido Schimmel | 701b186 | 2016-07-04 08:23:16 +0200 | [diff] [blame] | 546 | struct mlxsw_sp_fid *mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid); |
| 547 | void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fid *f); |
Ido Schimmel | 99f44bb | 2016-07-04 08:23:17 +0200 | [diff] [blame] | 548 | void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp, |
| 549 | struct mlxsw_sp_rif *r); |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 550 | int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 551 | enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, |
| 552 | bool dwrr, u8 dwrr_weight); |
| 553 | int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 554 | u8 switch_prio, u8 tclass); |
| 555 | int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 556 | u8 *prio_tc, bool pause_en, |
| 557 | struct ieee_pfc *my_pfc); |
Ido Schimmel | cc7cf51 | 2016-04-06 17:10:11 +0200 | [diff] [blame] | 558 | int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 559 | enum mlxsw_reg_qeec_hr hr, u8 index, |
| 560 | u8 next_index, u32 maxrate); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 561 | |
Ido Schimmel | f00817d | 2016-04-06 17:10:09 +0200 | [diff] [blame] | 562 | #ifdef CONFIG_MLXSW_SPECTRUM_DCB |
| 563 | |
| 564 | int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 565 | void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port); |
| 566 | |
| 567 | #else |
| 568 | |
| 569 | static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port) |
| 570 | { |
| 571 | return 0; |
| 572 | } |
| 573 | |
| 574 | static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port) |
| 575 | {} |
| 576 | |
| 577 | #endif |
| 578 | |
Ido Schimmel | 464dce1 | 2016-07-02 11:00:15 +0200 | [diff] [blame] | 579 | int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp); |
| 580 | void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp); |
Jiri Pirko | 61c503f | 2016-07-04 08:23:11 +0200 | [diff] [blame] | 581 | int mlxsw_sp_router_fib4_add(struct mlxsw_sp_port *mlxsw_sp_port, |
| 582 | const struct switchdev_obj_ipv4_fib *fib4, |
| 583 | struct switchdev_trans *trans); |
| 584 | int mlxsw_sp_router_fib4_del(struct mlxsw_sp_port *mlxsw_sp_port, |
| 585 | const struct switchdev_obj_ipv4_fib *fib4); |
Jiri Pirko | 6cf3c97 | 2016-07-05 11:27:39 +0200 | [diff] [blame] | 586 | int mlxsw_sp_router_neigh_construct(struct net_device *dev, |
| 587 | struct neighbour *n); |
| 588 | void mlxsw_sp_router_neigh_destroy(struct net_device *dev, |
| 589 | struct neighbour *n); |
Jiri Pirko | e732263 | 2016-09-01 10:37:43 +0200 | [diff] [blame] | 590 | int mlxsw_sp_router_netevent_event(struct notifier_block *unused, |
| 591 | unsigned long event, void *ptr); |
Ido Schimmel | 464dce1 | 2016-07-02 11:00:15 +0200 | [diff] [blame] | 592 | |
Jiri Pirko | b090ef0 | 2016-07-05 11:27:47 +0200 | [diff] [blame] | 593 | int mlxsw_sp_kvdl_alloc(struct mlxsw_sp *mlxsw_sp, unsigned int entry_count); |
| 594 | void mlxsw_sp_kvdl_free(struct mlxsw_sp *mlxsw_sp, int entry_index); |
| 595 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 596 | #endif |