blob: f143113114a9cda9a08a650b98d6353a0eb2765e [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
29#include <mach/msm_xo.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070030#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "clock-local.h"
33#include "clock-rpm.h"
34#include "clock-voter.h"
35#include "clock-dss-8960.h"
36#include "devices.h"
37
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
44#define CE1_HCLK_CTL_REG REG(0x2720)
45#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou41515e22011-09-01 19:37:43 -070046#define CE3_HCLK_CTL_REG REG(0x36C4)
47#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
48#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070049#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou41515e22011-09-01 19:37:43 -070050#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
52#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
53#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
54#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070055/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
57#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070058#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070059#define CLK_TEST_REG REG(0x2FA0)
60#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
61#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
62#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
63#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
64#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
65#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070066#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070067/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070068#define BB_PLL_ENA_SC0_REG REG(0x34C0)
69#define BB_PLL0_STATUS_REG REG(0x30D8)
70#define BB_PLL5_STATUS_REG REG(0x30F8)
71#define BB_PLL6_STATUS_REG REG(0x3118)
72#define BB_PLL7_STATUS_REG REG(0x3138)
73#define BB_PLL8_L_VAL_REG REG(0x3144)
74#define BB_PLL8_M_VAL_REG REG(0x3148)
75#define BB_PLL8_MODE_REG REG(0x3140)
76#define BB_PLL8_N_VAL_REG REG(0x314C)
77#define BB_PLL8_STATUS_REG REG(0x3158)
78#define BB_PLL8_CONFIG_REG REG(0x3154)
79#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070080#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
81#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070082#define BB_PLL14_MODE_REG REG(0x31C0)
83#define BB_PLL14_L_VAL_REG REG(0x31C4)
84#define BB_PLL14_M_VAL_REG REG(0x31C8)
85#define BB_PLL14_N_VAL_REG REG(0x31CC)
86#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
87#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070088#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070089#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
90#define PMEM_ACLK_CTL_REG REG(0x25A0)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070091#define QDSS_AT_CLK_SRC0_NS_REG REG(0x2180)
92#define QDSS_AT_CLK_SRC1_NS_REG REG(0x2184)
93#define QDSS_AT_CLK_SRC_CTL_REG REG(0x2188)
94#define QDSS_AT_CLK_NS_REG REG(0x218C)
95#define QDSS_HCLK_CTL_REG REG(0x22A0)
96#define QDSS_RESETS_REG REG(0x2260)
97#define QDSS_STM_CLK_CTL_REG REG(0x2060)
98#define QDSS_TRACECLKIN_CLK_SRC0_NS_REG REG(0x21A0)
99#define QDSS_TRACECLKIN_CLK_SRC1_NS_REG REG(0x21A4)
100#define QDSS_TRACECLKIN_CLK_SRC_CTL_REG REG(0x21A8)
101#define QDSS_TRACECLKIN_CTL_REG REG(0x21AC)
102#define QDSS_TSCTR_CLK_SRC0_NS_REG REG(0x21C0)
103#define QDSS_TSCTR_CLK_SRC1_NS_REG REG(0x21C4)
104#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
105#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
106#define QDSS_TSCTR_CTL_REG REG(0x21CC)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700107#define RINGOSC_NS_REG REG(0x2DC0)
108#define RINGOSC_STATUS_REG REG(0x2DCC)
109#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
110#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
111#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
112#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
113#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
114#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
115#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
116#define TSIF_HCLK_CTL_REG REG(0x2700)
117#define TSIF_REF_CLK_MD_REG REG(0x270C)
118#define TSIF_REF_CLK_NS_REG REG(0x2710)
119#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700120#define SATA_CLK_SRC_NS_REG REG(0x2C08)
121#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
122#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
123#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
124#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700125#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
126#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
127#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
128#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
129#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
130#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700131#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700132#define USB_HS1_RESET_REG REG(0x2910)
133#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
134#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700135#define USB_HS3_HCLK_CTL_REG REG(0x3700)
136#define USB_HS3_HCLK_FS_REG REG(0x3704)
137#define USB_HS3_RESET_REG REG(0x3710)
138#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
139#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
140#define USB_HS4_HCLK_CTL_REG REG(0x3720)
141#define USB_HS4_HCLK_FS_REG REG(0x3724)
142#define USB_HS4_RESET_REG REG(0x3730)
143#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
144#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700145#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
146#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
147#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
148#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
149#define USB_HSIC_RESET_REG REG(0x2934)
150#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
151#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
152#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700153#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700154#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
155#define PCIE_HCLK_CTL_REG REG(0x22CC)
156#define GPLL1_MODE_REG REG(0x3160)
157#define GPLL1_L_VAL_REG REG(0x3164)
158#define GPLL1_M_VAL_REG REG(0x3168)
159#define GPLL1_N_VAL_REG REG(0x316C)
160#define GPLL1_CONFIG_REG REG(0x3174)
161#define GPLL1_STATUS_REG REG(0x3178)
162#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700163
164/* Multimedia clock registers. */
165#define AHB_EN_REG REG_MM(0x0008)
166#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700167#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700168#define AHB_NS_REG REG_MM(0x0004)
169#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700170#define CAMCLK0_NS_REG REG_MM(0x0148)
171#define CAMCLK0_CC_REG REG_MM(0x0140)
172#define CAMCLK0_MD_REG REG_MM(0x0144)
173#define CAMCLK1_NS_REG REG_MM(0x015C)
174#define CAMCLK1_CC_REG REG_MM(0x0154)
175#define CAMCLK1_MD_REG REG_MM(0x0158)
176#define CAMCLK2_NS_REG REG_MM(0x0228)
177#define CAMCLK2_CC_REG REG_MM(0x0220)
178#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700179#define CSI0_NS_REG REG_MM(0x0048)
180#define CSI0_CC_REG REG_MM(0x0040)
181#define CSI0_MD_REG REG_MM(0x0044)
182#define CSI1_NS_REG REG_MM(0x0010)
183#define CSI1_CC_REG REG_MM(0x0024)
184#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700185#define CSI2_NS_REG REG_MM(0x0234)
186#define CSI2_CC_REG REG_MM(0x022C)
187#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700188#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
189#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
190#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
191#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
192#define DSI1_BYTE_CC_REG REG_MM(0x0090)
193#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
194#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
195#define DSI1_ESC_NS_REG REG_MM(0x011C)
196#define DSI1_ESC_CC_REG REG_MM(0x00CC)
197#define DSI2_ESC_NS_REG REG_MM(0x0150)
198#define DSI2_ESC_CC_REG REG_MM(0x013C)
199#define DSI_PIXEL_CC_REG REG_MM(0x0130)
200#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
201#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
202#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
203#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
204#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
205#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
206#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
207#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
208#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
209#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700210#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700211#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
212#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
213#define GFX2D0_CC_REG REG_MM(0x0060)
214#define GFX2D0_MD0_REG REG_MM(0x0064)
215#define GFX2D0_MD1_REG REG_MM(0x0068)
216#define GFX2D0_NS_REG REG_MM(0x0070)
217#define GFX2D1_CC_REG REG_MM(0x0074)
218#define GFX2D1_MD0_REG REG_MM(0x0078)
219#define GFX2D1_MD1_REG REG_MM(0x006C)
220#define GFX2D1_NS_REG REG_MM(0x007C)
221#define GFX3D_CC_REG REG_MM(0x0080)
222#define GFX3D_MD0_REG REG_MM(0x0084)
223#define GFX3D_MD1_REG REG_MM(0x0088)
224#define GFX3D_NS_REG REG_MM(0x008C)
225#define IJPEG_CC_REG REG_MM(0x0098)
226#define IJPEG_MD_REG REG_MM(0x009C)
227#define IJPEG_NS_REG REG_MM(0x00A0)
228#define JPEGD_CC_REG REG_MM(0x00A4)
229#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700230#define VCAP_CC_REG REG_MM(0x0178)
231#define VCAP_NS_REG REG_MM(0x021C)
232#define VCAP_MD0_REG REG_MM(0x01EC)
233#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700234#define MAXI_EN_REG REG_MM(0x0018)
235#define MAXI_EN2_REG REG_MM(0x0020)
236#define MAXI_EN3_REG REG_MM(0x002C)
237#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700238#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700239#define MDP_CC_REG REG_MM(0x00C0)
240#define MDP_LUT_CC_REG REG_MM(0x016C)
241#define MDP_MD0_REG REG_MM(0x00C4)
242#define MDP_MD1_REG REG_MM(0x00C8)
243#define MDP_NS_REG REG_MM(0x00D0)
244#define MISC_CC_REG REG_MM(0x0058)
245#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700246#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700247#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700248#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
249#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
250#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
251#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
252#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
253#define MM_PLL1_STATUS_REG REG_MM(0x0334)
254#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700255#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
256#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
257#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
258#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
259#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
260#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700261#define ROT_CC_REG REG_MM(0x00E0)
262#define ROT_NS_REG REG_MM(0x00E8)
263#define SAXI_EN_REG REG_MM(0x0030)
264#define SW_RESET_AHB_REG REG_MM(0x020C)
265#define SW_RESET_AHB2_REG REG_MM(0x0200)
266#define SW_RESET_ALL_REG REG_MM(0x0204)
267#define SW_RESET_AXI_REG REG_MM(0x0208)
268#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700269#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700270#define TV_CC_REG REG_MM(0x00EC)
271#define TV_CC2_REG REG_MM(0x0124)
272#define TV_MD_REG REG_MM(0x00F0)
273#define TV_NS_REG REG_MM(0x00F4)
274#define VCODEC_CC_REG REG_MM(0x00F8)
275#define VCODEC_MD0_REG REG_MM(0x00FC)
276#define VCODEC_MD1_REG REG_MM(0x0128)
277#define VCODEC_NS_REG REG_MM(0x0100)
278#define VFE_CC_REG REG_MM(0x0104)
279#define VFE_MD_REG REG_MM(0x0108)
280#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700281#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700282#define VPE_CC_REG REG_MM(0x0110)
283#define VPE_NS_REG REG_MM(0x0118)
284
285/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700286#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700287#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
288#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
289#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
290#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
291#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
292#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
293#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
294#define LCC_MI2S_MD_REG REG_LPA(0x004C)
295#define LCC_MI2S_NS_REG REG_LPA(0x0048)
296#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
297#define LCC_PCM_MD_REG REG_LPA(0x0058)
298#define LCC_PCM_NS_REG REG_LPA(0x0054)
299#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
300#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700301#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
302#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
303#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
304#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
305#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
306#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
307#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
308#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
309#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
310#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
311
Matt Wagantall8b38f942011-08-02 18:23:18 -0700312#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
313
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700314/* MUX source input identifiers. */
315#define pxo_to_bb_mux 0
316#define cxo_to_bb_mux pxo_to_bb_mux
317#define pll0_to_bb_mux 2
318#define pll8_to_bb_mux 3
319#define pll6_to_bb_mux 4
320#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700321#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700322#define pxo_to_mm_mux 0
323#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700324#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
325#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700326#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700327#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700328#define gnd_to_mm_mux 4
Tianyi Gou41515e22011-09-01 19:37:43 -0700329#define pll3_to_mm_mux 5 /* used in 8960 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700330#define hdmi_pll_to_mm_mux 3
331#define cxo_to_xo_mux 0
332#define pxo_to_xo_mux 1
333#define gnd_to_xo_mux 3
334#define pxo_to_lpa_mux 0
335#define cxo_to_lpa_mux 1
336#define pll4_to_lpa_mux 2
337#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700338#define pxo_to_pcie_mux 0
339#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700340
341/* Test Vector Macros */
342#define TEST_TYPE_PER_LS 1
343#define TEST_TYPE_PER_HS 2
344#define TEST_TYPE_MM_LS 3
345#define TEST_TYPE_MM_HS 4
346#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700347#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700348#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700349#define TEST_TYPE_SHIFT 24
350#define TEST_CLK_SEL_MASK BM(23, 0)
351#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
352#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
353#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
354#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
355#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
356#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700357#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700358#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700359
360#define MN_MODE_DUAL_EDGE 0x2
361
362/* MD Registers */
363#define MD4(m_lsb, m, n_lsb, n) \
364 (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
365#define MD8(m_lsb, m, n_lsb, n) \
366 (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
367#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
368
369/* NS Registers */
370#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
371 (BVAL(n_msb, n_lsb, ~(n-m)) \
372 | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
373 | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
374
375#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
376 (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
377 | BVAL(s_msb, s_lsb, s))
378
379#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
380 (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
381
382#define NS_DIV(d_msb , d_lsb, d) \
383 BVAL(d_msb, d_lsb, (d-1))
384
385#define NS_SRC_SEL(s_msb, s_lsb, s) \
386 BVAL(s_msb, s_lsb, s)
387
388#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
389 (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
390 | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
391 | BVAL((s0_lsb+2), s0_lsb, s) \
392 | BVAL((s1_lsb+2), s1_lsb, s))
393
394#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
395 (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
396 | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
397 | BVAL((s0_lsb+2), s0_lsb, s) \
398 | BVAL((s1_lsb+2), s1_lsb, s))
399
400#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
401 s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
402 (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
403 | BVAL(s0_msb, s0_lsb, s) \
404 | BVAL(s1_msb, s1_lsb, s))
405
406/* CC Registers */
407#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
408#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
409 ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
410 | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
411 * !!(n))
412
413struct pll_rate {
414 const uint32_t l_val;
415 const uint32_t m_val;
416 const uint32_t n_val;
417 const uint32_t vco;
418 const uint32_t post_div;
419 const uint32_t i_bits;
420};
421#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
422
423/*
424 * Clock Descriptions
425 */
426
427static struct msm_xo_voter *xo_pxo, *xo_cxo;
428
429static int pxo_clk_enable(struct clk *clk)
430{
431 return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON);
432}
433
434static void pxo_clk_disable(struct clk *clk)
435{
Tianyi Gou41515e22011-09-01 19:37:43 -0700436 msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700437}
438
439static struct clk_ops clk_ops_pxo = {
440 .enable = pxo_clk_enable,
441 .disable = pxo_clk_disable,
442 .get_rate = fixed_clk_get_rate,
443 .is_local = local_clk_is_local,
444};
445
446static struct fixed_clk pxo_clk = {
447 .rate = 27000000,
448 .c = {
449 .dbg_name = "pxo_clk",
450 .ops = &clk_ops_pxo,
451 CLK_INIT(pxo_clk.c),
452 },
453};
454
455static int cxo_clk_enable(struct clk *clk)
456{
457 return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON);
458}
459
460static void cxo_clk_disable(struct clk *clk)
461{
462 msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF);
463}
464
465static struct clk_ops clk_ops_cxo = {
466 .enable = cxo_clk_enable,
467 .disable = cxo_clk_disable,
468 .get_rate = fixed_clk_get_rate,
469 .is_local = local_clk_is_local,
470};
471
472static struct fixed_clk cxo_clk = {
473 .rate = 19200000,
474 .c = {
475 .dbg_name = "cxo_clk",
476 .ops = &clk_ops_cxo,
477 CLK_INIT(cxo_clk.c),
478 },
479};
480
481static struct pll_clk pll2_clk = {
482 .rate = 800000000,
483 .mode_reg = MM_PLL1_MODE_REG,
484 .parent = &pxo_clk.c,
485 .c = {
486 .dbg_name = "pll2_clk",
487 .ops = &clk_ops_pll,
488 CLK_INIT(pll2_clk.c),
489 },
490};
491
Stephen Boyd94625ef2011-07-12 17:06:01 -0700492static struct pll_clk pll3_clk = {
493 .rate = 1200000000,
494 .mode_reg = BB_MMCC_PLL2_MODE_REG,
495 .parent = &pxo_clk.c,
496 .c = {
497 .dbg_name = "pll3_clk",
498 .ops = &clk_ops_pll,
499 CLK_INIT(pll3_clk.c),
500 },
501};
502
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700503static struct pll_vote_clk pll4_clk = {
504 .rate = 393216000,
505 .en_reg = BB_PLL_ENA_SC0_REG,
506 .en_mask = BIT(4),
507 .status_reg = LCC_PLL0_STATUS_REG,
508 .parent = &pxo_clk.c,
509 .c = {
510 .dbg_name = "pll4_clk",
511 .ops = &clk_ops_pll_vote,
512 CLK_INIT(pll4_clk.c),
513 },
514};
515
516static struct pll_vote_clk pll8_clk = {
517 .rate = 384000000,
518 .en_reg = BB_PLL_ENA_SC0_REG,
519 .en_mask = BIT(8),
520 .status_reg = BB_PLL8_STATUS_REG,
521 .parent = &pxo_clk.c,
522 .c = {
523 .dbg_name = "pll8_clk",
524 .ops = &clk_ops_pll_vote,
525 CLK_INIT(pll8_clk.c),
526 },
527};
528
Stephen Boyd94625ef2011-07-12 17:06:01 -0700529static struct pll_vote_clk pll14_clk = {
530 .rate = 480000000,
531 .en_reg = BB_PLL_ENA_SC0_REG,
532 .en_mask = BIT(14),
533 .status_reg = BB_PLL14_STATUS_REG,
534 .parent = &pxo_clk.c,
535 .c = {
536 .dbg_name = "pll14_clk",
537 .ops = &clk_ops_pll_vote,
538 CLK_INIT(pll14_clk.c),
539 },
540};
541
Tianyi Gou41515e22011-09-01 19:37:43 -0700542static struct pll_clk pll15_clk = {
543 .rate = 975000000,
544 .mode_reg = MM_PLL3_MODE_REG,
545 .parent = &pxo_clk.c,
546 .c = {
547 .dbg_name = "pll15_clk",
548 .ops = &clk_ops_pll,
549 CLK_INIT(pll15_clk.c),
550 },
551};
552
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700553/*
554 * SoC-specific functions required by clock-local driver
555 */
556
557/* Update the sys_vdd voltage given a level. */
558static int msm8960_update_sys_vdd(enum sys_vdd_level level)
559{
560 static const int vdd_uv[] = {
Matt Wagantallb6f30f02011-09-07 16:48:56 -0700561 [NONE] = 0,
562 [LOW] = 945000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700563 [NOMINAL] = 1050000,
564 [HIGH] = 1150000,
565 };
566
567 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
568 vdd_uv[level], vdd_uv[HIGH], 1);
569}
570
571static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
572{
573 return branch_reset(&to_rcg_clk(clk)->b, action);
574}
575
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700576static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700577 .enable = rcg_clk_enable,
578 .disable = rcg_clk_disable,
579 .auto_off = rcg_clk_auto_off,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700580 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700581 .set_rate = rcg_clk_set_rate,
582 .set_min_rate = rcg_clk_set_min_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700583 .get_rate = rcg_clk_get_rate,
584 .list_rate = rcg_clk_list_rate,
585 .is_enabled = rcg_clk_is_enabled,
586 .round_rate = rcg_clk_round_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700587 .reset = soc_clk_reset,
588 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700589 .get_parent = rcg_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700590};
591
592static struct clk_ops clk_ops_branch = {
593 .enable = branch_clk_enable,
594 .disable = branch_clk_disable,
595 .auto_off = branch_clk_auto_off,
596 .is_enabled = branch_clk_is_enabled,
597 .reset = branch_clk_reset,
598 .is_local = local_clk_is_local,
599 .get_parent = branch_clk_get_parent,
600 .set_parent = branch_clk_set_parent,
601};
602
603static struct clk_ops clk_ops_reset = {
604 .reset = branch_clk_reset,
605 .is_local = local_clk_is_local,
606};
607
608/* AXI Interfaces */
609static struct branch_clk gmem_axi_clk = {
610 .b = {
611 .ctl_reg = MAXI_EN_REG,
612 .en_mask = BIT(24),
613 .halt_reg = DBG_BUS_VEC_E_REG,
614 .halt_bit = 6,
615 },
616 .c = {
617 .dbg_name = "gmem_axi_clk",
618 .ops = &clk_ops_branch,
619 CLK_INIT(gmem_axi_clk.c),
620 },
621};
622
623static struct branch_clk ijpeg_axi_clk = {
624 .b = {
625 .ctl_reg = MAXI_EN_REG,
626 .en_mask = BIT(21),
627 .reset_reg = SW_RESET_AXI_REG,
628 .reset_mask = BIT(14),
629 .halt_reg = DBG_BUS_VEC_E_REG,
630 .halt_bit = 4,
631 },
632 .c = {
633 .dbg_name = "ijpeg_axi_clk",
634 .ops = &clk_ops_branch,
635 CLK_INIT(ijpeg_axi_clk.c),
636 },
637};
638
639static struct branch_clk imem_axi_clk = {
640 .b = {
641 .ctl_reg = MAXI_EN_REG,
642 .en_mask = BIT(22),
643 .reset_reg = SW_RESET_CORE_REG,
644 .reset_mask = BIT(10),
645 .halt_reg = DBG_BUS_VEC_E_REG,
646 .halt_bit = 7,
647 },
648 .c = {
649 .dbg_name = "imem_axi_clk",
650 .ops = &clk_ops_branch,
651 CLK_INIT(imem_axi_clk.c),
652 },
653};
654
655static struct branch_clk jpegd_axi_clk = {
656 .b = {
657 .ctl_reg = MAXI_EN_REG,
658 .en_mask = BIT(25),
659 .halt_reg = DBG_BUS_VEC_E_REG,
660 .halt_bit = 5,
661 },
662 .c = {
663 .dbg_name = "jpegd_axi_clk",
664 .ops = &clk_ops_branch,
665 CLK_INIT(jpegd_axi_clk.c),
666 },
667};
668
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700669static struct branch_clk vcodec_axi_b_clk = {
670 .b = {
671 .ctl_reg = MAXI_EN4_REG,
672 .en_mask = BIT(23),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700673 .halt_reg = DBG_BUS_VEC_I_REG,
674 .halt_bit = 25,
675 },
676 .c = {
677 .dbg_name = "vcodec_axi_b_clk",
678 .ops = &clk_ops_branch,
679 CLK_INIT(vcodec_axi_b_clk.c),
680 },
681};
682
Matt Wagantall91f42702011-07-14 12:01:15 -0700683static struct branch_clk vcodec_axi_a_clk = {
684 .b = {
685 .ctl_reg = MAXI_EN4_REG,
686 .en_mask = BIT(25),
Matt Wagantall91f42702011-07-14 12:01:15 -0700687 .halt_reg = DBG_BUS_VEC_I_REG,
688 .halt_bit = 26,
689 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700690 .c = {
691 .dbg_name = "vcodec_axi_a_clk",
692 .ops = &clk_ops_branch,
693 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700694 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700695 },
696};
697
698static struct branch_clk vcodec_axi_clk = {
699 .b = {
700 .ctl_reg = MAXI_EN_REG,
701 .en_mask = BIT(19),
702 .reset_reg = SW_RESET_AXI_REG,
Matt Wagantallfe2ee052011-07-14 13:33:44 -0700703 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700704 .halt_reg = DBG_BUS_VEC_E_REG,
705 .halt_bit = 3,
706 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700707 .c = {
708 .dbg_name = "vcodec_axi_clk",
709 .ops = &clk_ops_branch,
710 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700711 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700712 },
713};
714
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700715static struct branch_clk vfe_axi_clk = {
716 .b = {
717 .ctl_reg = MAXI_EN_REG,
718 .en_mask = BIT(18),
719 .reset_reg = SW_RESET_AXI_REG,
720 .reset_mask = BIT(9),
721 .halt_reg = DBG_BUS_VEC_E_REG,
722 .halt_bit = 0,
723 },
724 .c = {
725 .dbg_name = "vfe_axi_clk",
726 .ops = &clk_ops_branch,
727 CLK_INIT(vfe_axi_clk.c),
728 },
729};
730
731static struct branch_clk mdp_axi_clk = {
732 .b = {
733 .ctl_reg = MAXI_EN_REG,
734 .en_mask = BIT(23),
735 .reset_reg = SW_RESET_AXI_REG,
736 .reset_mask = BIT(13),
737 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700738 .halt_bit = 8,
739 },
740 .c = {
741 .dbg_name = "mdp_axi_clk",
742 .ops = &clk_ops_branch,
743 CLK_INIT(mdp_axi_clk.c),
744 },
745};
746
747static struct branch_clk rot_axi_clk = {
748 .b = {
749 .ctl_reg = MAXI_EN2_REG,
750 .en_mask = BIT(24),
751 .reset_reg = SW_RESET_AXI_REG,
752 .reset_mask = BIT(6),
753 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700754 .halt_bit = 2,
755 },
756 .c = {
757 .dbg_name = "rot_axi_clk",
758 .ops = &clk_ops_branch,
759 CLK_INIT(rot_axi_clk.c),
760 },
761};
762
763static struct branch_clk vpe_axi_clk = {
764 .b = {
765 .ctl_reg = MAXI_EN2_REG,
766 .en_mask = BIT(26),
767 .reset_reg = SW_RESET_AXI_REG,
768 .reset_mask = BIT(15),
769 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700770 .halt_bit = 1,
771 },
772 .c = {
773 .dbg_name = "vpe_axi_clk",
774 .ops = &clk_ops_branch,
775 CLK_INIT(vpe_axi_clk.c),
776 },
777};
778
Tianyi Gou41515e22011-09-01 19:37:43 -0700779static struct branch_clk vcap_axi_clk = {
780 .b = {
781 .ctl_reg = MAXI_EN5_REG,
782 .en_mask = BIT(12),
783 .reset_reg = SW_RESET_AXI_REG,
784 .reset_mask = BIT(16),
785 .halt_reg = DBG_BUS_VEC_J_REG,
786 .halt_bit = 20,
787 },
788 .c = {
789 .dbg_name = "vcap_axi_clk",
790 .ops = &clk_ops_branch,
791 CLK_INIT(vcap_axi_clk.c),
792 },
793};
794
Tianyi Gou621f8742011-09-01 21:45:01 -0700795/* For 8064, gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
796static struct branch_clk gfx3d_axi_clk = {
797 .b = {
798 .ctl_reg = MAXI_EN5_REG,
799 .en_mask = BIT(25),
800 .reset_reg = SW_RESET_AXI_REG,
801 .reset_mask = BIT(17),
802 .halt_reg = DBG_BUS_VEC_J_REG,
803 .halt_bit = 30,
804 },
805 .c = {
806 .dbg_name = "gfx3d_axi_clk",
807 .ops = &clk_ops_branch,
808 CLK_INIT(gfx3d_axi_clk.c),
809 },
810};
811
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700812/* AHB Interfaces */
813static struct branch_clk amp_p_clk = {
814 .b = {
815 .ctl_reg = AHB_EN_REG,
816 .en_mask = BIT(24),
817 .halt_reg = DBG_BUS_VEC_F_REG,
818 .halt_bit = 18,
819 },
820 .c = {
821 .dbg_name = "amp_p_clk",
822 .ops = &clk_ops_branch,
823 CLK_INIT(amp_p_clk.c),
824 },
825};
826
Matt Wagantallc23eee92011-08-16 23:06:52 -0700827static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700828 .b = {
829 .ctl_reg = AHB_EN_REG,
830 .en_mask = BIT(7),
831 .reset_reg = SW_RESET_AHB_REG,
832 .reset_mask = BIT(17),
833 .halt_reg = DBG_BUS_VEC_F_REG,
834 .halt_bit = 16,
835 },
836 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700837 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700838 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700839 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700840 },
841};
842
843static struct branch_clk dsi1_m_p_clk = {
844 .b = {
845 .ctl_reg = AHB_EN_REG,
846 .en_mask = BIT(9),
847 .reset_reg = SW_RESET_AHB_REG,
848 .reset_mask = BIT(6),
849 .halt_reg = DBG_BUS_VEC_F_REG,
850 .halt_bit = 19,
851 },
852 .c = {
853 .dbg_name = "dsi1_m_p_clk",
854 .ops = &clk_ops_branch,
855 CLK_INIT(dsi1_m_p_clk.c),
856 },
857};
858
859static struct branch_clk dsi1_s_p_clk = {
860 .b = {
861 .ctl_reg = AHB_EN_REG,
862 .en_mask = BIT(18),
863 .reset_reg = SW_RESET_AHB_REG,
864 .reset_mask = BIT(5),
865 .halt_reg = DBG_BUS_VEC_F_REG,
866 .halt_bit = 21,
867 },
868 .c = {
869 .dbg_name = "dsi1_s_p_clk",
870 .ops = &clk_ops_branch,
871 CLK_INIT(dsi1_s_p_clk.c),
872 },
873};
874
875static struct branch_clk dsi2_m_p_clk = {
876 .b = {
877 .ctl_reg = AHB_EN_REG,
878 .en_mask = BIT(17),
879 .reset_reg = SW_RESET_AHB2_REG,
880 .reset_mask = BIT(1),
881 .halt_reg = DBG_BUS_VEC_E_REG,
882 .halt_bit = 18,
883 },
884 .c = {
885 .dbg_name = "dsi2_m_p_clk",
886 .ops = &clk_ops_branch,
887 CLK_INIT(dsi2_m_p_clk.c),
888 },
889};
890
891static struct branch_clk dsi2_s_p_clk = {
892 .b = {
893 .ctl_reg = AHB_EN_REG,
894 .en_mask = BIT(22),
895 .reset_reg = SW_RESET_AHB2_REG,
896 .reset_mask = BIT(0),
897 .halt_reg = DBG_BUS_VEC_F_REG,
898 .halt_bit = 20,
899 },
900 .c = {
901 .dbg_name = "dsi2_s_p_clk",
902 .ops = &clk_ops_branch,
903 CLK_INIT(dsi2_s_p_clk.c),
904 },
905};
906
907static struct branch_clk gfx2d0_p_clk = {
908 .b = {
909 .ctl_reg = AHB_EN_REG,
910 .en_mask = BIT(19),
911 .reset_reg = SW_RESET_AHB_REG,
912 .reset_mask = BIT(12),
913 .halt_reg = DBG_BUS_VEC_F_REG,
914 .halt_bit = 2,
915 },
916 .c = {
917 .dbg_name = "gfx2d0_p_clk",
918 .ops = &clk_ops_branch,
919 CLK_INIT(gfx2d0_p_clk.c),
920 },
921};
922
923static struct branch_clk gfx2d1_p_clk = {
924 .b = {
925 .ctl_reg = AHB_EN_REG,
926 .en_mask = BIT(2),
927 .reset_reg = SW_RESET_AHB_REG,
928 .reset_mask = BIT(11),
929 .halt_reg = DBG_BUS_VEC_F_REG,
930 .halt_bit = 3,
931 },
932 .c = {
933 .dbg_name = "gfx2d1_p_clk",
934 .ops = &clk_ops_branch,
935 CLK_INIT(gfx2d1_p_clk.c),
936 },
937};
938
939static struct branch_clk gfx3d_p_clk = {
940 .b = {
941 .ctl_reg = AHB_EN_REG,
942 .en_mask = BIT(3),
943 .reset_reg = SW_RESET_AHB_REG,
944 .reset_mask = BIT(10),
945 .halt_reg = DBG_BUS_VEC_F_REG,
946 .halt_bit = 4,
947 },
948 .c = {
949 .dbg_name = "gfx3d_p_clk",
950 .ops = &clk_ops_branch,
951 CLK_INIT(gfx3d_p_clk.c),
952 },
953};
954
955static struct branch_clk hdmi_m_p_clk = {
956 .b = {
957 .ctl_reg = AHB_EN_REG,
958 .en_mask = BIT(14),
959 .reset_reg = SW_RESET_AHB_REG,
960 .reset_mask = BIT(9),
961 .halt_reg = DBG_BUS_VEC_F_REG,
962 .halt_bit = 5,
963 },
964 .c = {
965 .dbg_name = "hdmi_m_p_clk",
966 .ops = &clk_ops_branch,
967 CLK_INIT(hdmi_m_p_clk.c),
968 },
969};
970
971static struct branch_clk hdmi_s_p_clk = {
972 .b = {
973 .ctl_reg = AHB_EN_REG,
974 .en_mask = BIT(4),
975 .reset_reg = SW_RESET_AHB_REG,
976 .reset_mask = BIT(9),
977 .halt_reg = DBG_BUS_VEC_F_REG,
978 .halt_bit = 6,
979 },
980 .c = {
981 .dbg_name = "hdmi_s_p_clk",
982 .ops = &clk_ops_branch,
983 CLK_INIT(hdmi_s_p_clk.c),
984 },
985};
986
987static struct branch_clk ijpeg_p_clk = {
988 .b = {
989 .ctl_reg = AHB_EN_REG,
990 .en_mask = BIT(5),
991 .reset_reg = SW_RESET_AHB_REG,
992 .reset_mask = BIT(7),
993 .halt_reg = DBG_BUS_VEC_F_REG,
994 .halt_bit = 9,
995 },
996 .c = {
997 .dbg_name = "ijpeg_p_clk",
998 .ops = &clk_ops_branch,
999 CLK_INIT(ijpeg_p_clk.c),
1000 },
1001};
1002
1003static struct branch_clk imem_p_clk = {
1004 .b = {
1005 .ctl_reg = AHB_EN_REG,
1006 .en_mask = BIT(6),
1007 .reset_reg = SW_RESET_AHB_REG,
1008 .reset_mask = BIT(8),
1009 .halt_reg = DBG_BUS_VEC_F_REG,
1010 .halt_bit = 10,
1011 },
1012 .c = {
1013 .dbg_name = "imem_p_clk",
1014 .ops = &clk_ops_branch,
1015 CLK_INIT(imem_p_clk.c),
1016 },
1017};
1018
1019static struct branch_clk jpegd_p_clk = {
1020 .b = {
1021 .ctl_reg = AHB_EN_REG,
1022 .en_mask = BIT(21),
1023 .reset_reg = SW_RESET_AHB_REG,
1024 .reset_mask = BIT(4),
1025 .halt_reg = DBG_BUS_VEC_F_REG,
1026 .halt_bit = 7,
1027 },
1028 .c = {
1029 .dbg_name = "jpegd_p_clk",
1030 .ops = &clk_ops_branch,
1031 CLK_INIT(jpegd_p_clk.c),
1032 },
1033};
1034
1035static struct branch_clk mdp_p_clk = {
1036 .b = {
1037 .ctl_reg = AHB_EN_REG,
1038 .en_mask = BIT(10),
1039 .reset_reg = SW_RESET_AHB_REG,
1040 .reset_mask = BIT(3),
1041 .halt_reg = DBG_BUS_VEC_F_REG,
1042 .halt_bit = 11,
1043 },
1044 .c = {
1045 .dbg_name = "mdp_p_clk",
1046 .ops = &clk_ops_branch,
1047 CLK_INIT(mdp_p_clk.c),
1048 },
1049};
1050
1051static struct branch_clk rot_p_clk = {
1052 .b = {
1053 .ctl_reg = AHB_EN_REG,
1054 .en_mask = BIT(12),
1055 .reset_reg = SW_RESET_AHB_REG,
1056 .reset_mask = BIT(2),
1057 .halt_reg = DBG_BUS_VEC_F_REG,
1058 .halt_bit = 13,
1059 },
1060 .c = {
1061 .dbg_name = "rot_p_clk",
1062 .ops = &clk_ops_branch,
1063 CLK_INIT(rot_p_clk.c),
1064 },
1065};
1066
1067static struct branch_clk smmu_p_clk = {
1068 .b = {
1069 .ctl_reg = AHB_EN_REG,
1070 .en_mask = BIT(15),
1071 .halt_reg = DBG_BUS_VEC_F_REG,
1072 .halt_bit = 22,
1073 },
1074 .c = {
1075 .dbg_name = "smmu_p_clk",
1076 .ops = &clk_ops_branch,
1077 CLK_INIT(smmu_p_clk.c),
1078 },
1079};
1080
1081static struct branch_clk tv_enc_p_clk = {
1082 .b = {
1083 .ctl_reg = AHB_EN_REG,
1084 .en_mask = BIT(25),
1085 .reset_reg = SW_RESET_AHB_REG,
1086 .reset_mask = BIT(15),
1087 .halt_reg = DBG_BUS_VEC_F_REG,
1088 .halt_bit = 23,
1089 },
1090 .c = {
1091 .dbg_name = "tv_enc_p_clk",
1092 .ops = &clk_ops_branch,
1093 CLK_INIT(tv_enc_p_clk.c),
1094 },
1095};
1096
1097static struct branch_clk vcodec_p_clk = {
1098 .b = {
1099 .ctl_reg = AHB_EN_REG,
1100 .en_mask = BIT(11),
1101 .reset_reg = SW_RESET_AHB_REG,
1102 .reset_mask = BIT(1),
1103 .halt_reg = DBG_BUS_VEC_F_REG,
1104 .halt_bit = 12,
1105 },
1106 .c = {
1107 .dbg_name = "vcodec_p_clk",
1108 .ops = &clk_ops_branch,
1109 CLK_INIT(vcodec_p_clk.c),
1110 },
1111};
1112
1113static struct branch_clk vfe_p_clk = {
1114 .b = {
1115 .ctl_reg = AHB_EN_REG,
1116 .en_mask = BIT(13),
1117 .reset_reg = SW_RESET_AHB_REG,
1118 .reset_mask = BIT(0),
1119 .halt_reg = DBG_BUS_VEC_F_REG,
1120 .halt_bit = 14,
1121 },
1122 .c = {
1123 .dbg_name = "vfe_p_clk",
1124 .ops = &clk_ops_branch,
1125 CLK_INIT(vfe_p_clk.c),
1126 },
1127};
1128
1129static struct branch_clk vpe_p_clk = {
1130 .b = {
1131 .ctl_reg = AHB_EN_REG,
1132 .en_mask = BIT(16),
1133 .reset_reg = SW_RESET_AHB_REG,
1134 .reset_mask = BIT(14),
1135 .halt_reg = DBG_BUS_VEC_F_REG,
1136 .halt_bit = 15,
1137 },
1138 .c = {
1139 .dbg_name = "vpe_p_clk",
1140 .ops = &clk_ops_branch,
1141 CLK_INIT(vpe_p_clk.c),
1142 },
1143};
1144
Tianyi Gou41515e22011-09-01 19:37:43 -07001145static struct branch_clk vcap_p_clk = {
1146 .b = {
1147 .ctl_reg = AHB_EN3_REG,
1148 .en_mask = BIT(1),
1149 .reset_reg = SW_RESET_AHB2_REG,
1150 .reset_mask = BIT(2),
1151 .halt_reg = DBG_BUS_VEC_J_REG,
1152 .halt_bit = 23,
1153 },
1154 .c = {
1155 .dbg_name = "vcap_p_clk",
1156 .ops = &clk_ops_branch,
1157 CLK_INIT(vcap_p_clk.c),
1158 },
1159};
1160
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001161/*
1162 * Peripheral Clocks
1163 */
1164#define CLK_GSBI_UART(i, n, h_r, h_b) \
1165 struct rcg_clk i##_clk = { \
1166 .b = { \
1167 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1168 .en_mask = BIT(9), \
1169 .reset_reg = GSBIn_RESET_REG(n), \
1170 .reset_mask = BIT(0), \
1171 .halt_reg = h_r, \
1172 .halt_bit = h_b, \
1173 }, \
1174 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1175 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1176 .root_en_mask = BIT(11), \
1177 .ns_mask = (BM(31, 16) | BM(6, 0)), \
1178 .set_rate = set_rate_mnd, \
1179 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001180 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001181 .c = { \
1182 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001183 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001184 CLK_INIT(i##_clk.c), \
1185 }, \
1186 }
1187#define F_GSBI_UART(f, s, d, m, n, v) \
1188 { \
1189 .freq_hz = f, \
1190 .src_clk = &s##_clk.c, \
1191 .md_val = MD16(m, n), \
1192 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1193 .mnd_en_mask = BIT(8) * !!(n), \
1194 .sys_vdd = v, \
1195 }
1196static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
1197 F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
1198 F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
1199 F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
1200 F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
1201 F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
1202 F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
1203 F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
1204 F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
1205 F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
1206 F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
1207 F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
1208 F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
1209 F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
1210 F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
1211 F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
1212 F_END
1213};
1214
1215static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1216static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1217static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1218static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1219static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1220static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1221static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1222static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1223static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1224static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1225static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1226static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1227
1228#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1229 struct rcg_clk i##_clk = { \
1230 .b = { \
1231 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1232 .en_mask = BIT(9), \
1233 .reset_reg = GSBIn_RESET_REG(n), \
1234 .reset_mask = BIT(0), \
1235 .halt_reg = h_r, \
1236 .halt_bit = h_b, \
1237 }, \
1238 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1239 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1240 .root_en_mask = BIT(11), \
1241 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1242 .set_rate = set_rate_mnd, \
1243 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001244 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001245 .c = { \
1246 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001247 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001248 CLK_INIT(i##_clk.c), \
1249 }, \
1250 }
1251#define F_GSBI_QUP(f, s, d, m, n, v) \
1252 { \
1253 .freq_hz = f, \
1254 .src_clk = &s##_clk.c, \
1255 .md_val = MD8(16, m, 0, n), \
1256 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1257 .mnd_en_mask = BIT(8) * !!(n), \
1258 .sys_vdd = v, \
1259 }
1260static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
1261 F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
1262 F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
1263 F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
1264 F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
1265 F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
1266 F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
1267 F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
1268 F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
1269 F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
1270 F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
1271 F_END
1272};
1273
1274static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1275static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1276static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1277static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1278static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1279static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1280static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1281static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1282static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1283static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1284static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1285static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1286
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001287#define F_QDSS(f, s, d, v) \
1288 { \
1289 .freq_hz = f, \
1290 .src_clk = &s##_clk.c, \
1291 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
1292 .sys_vdd = v, \
1293 }
1294static struct clk_freq_tbl clk_tbl_qdss[] = {
Stephen Boydd4de6d72011-09-13 13:01:40 -07001295 F_QDSS( 27000000, pxo, 1, LOW),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001296 F_QDSS(128000000, pll8, 3, LOW),
1297 F_QDSS(300000000, pll3, 4, NOMINAL),
1298 F_END
1299};
1300
1301struct qdss_bank {
1302 const u32 bank_sel_mask;
1303 void __iomem *const ns_reg;
1304 const u32 ns_mask;
1305};
1306
Stephen Boydd4de6d72011-09-13 13:01:40 -07001307#define QDSS_CLK_ROOT_ENA BIT(1)
1308
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001309static int qdss_clk_handoff(struct clk *c)
Stephen Boydd4de6d72011-09-13 13:01:40 -07001310{
1311 struct rcg_clk *clk = to_rcg_clk(c);
1312 const struct qdss_bank *bank = clk->bank_info;
1313 u32 reg, ns_val, bank_sel;
1314 struct clk_freq_tbl *freq;
1315
1316 reg = readl_relaxed(clk->ns_reg);
1317 if (!(reg & QDSS_CLK_ROOT_ENA))
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001318 return 0;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001319
1320 bank_sel = reg & bank->bank_sel_mask;
1321 /* Force bank 1 to PXO if bank 0 is in use */
1322 if (bank_sel == 0)
1323 writel_relaxed(0, bank->ns_reg);
1324 ns_val = readl_relaxed(bank->ns_reg) & bank->ns_mask;
1325 for (freq = clk->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
1326 if ((freq->ns_val & bank->ns_mask) == ns_val) {
1327 pr_info("%s rate=%d\n", clk->c.dbg_name, freq->freq_hz);
1328 break;
1329 }
1330 }
1331 if (freq->freq_hz == FREQ_END)
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001332 return 0;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001333
1334 clk->current_freq = freq;
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001335
1336 return 1;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001337}
1338
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001339static void set_rate_qdss(struct rcg_clk *clk, struct clk_freq_tbl *nf)
1340{
1341 const struct qdss_bank *bank = clk->bank_info;
1342 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1343
1344 /* Switch to bank 0 (always sourced from PXO) */
1345 reg = readl_relaxed(clk->ns_reg);
1346 reg &= ~bank_sel_mask;
1347 writel_relaxed(reg, clk->ns_reg);
1348 /*
1349 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1350 * MUX to fully switch sources.
1351 */
1352 mb();
1353 udelay(1);
1354
1355 /* Set source and divider */
1356 reg = readl_relaxed(bank->ns_reg);
1357 reg &= ~bank->ns_mask;
1358 reg |= nf->ns_val;
1359 writel_relaxed(reg, bank->ns_reg);
1360
1361 /* Switch to reprogrammed bank */
1362 reg = readl_relaxed(clk->ns_reg);
1363 reg |= bank_sel_mask;
1364 writel_relaxed(reg, clk->ns_reg);
1365 /*
1366 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1367 * MUX to fully switch sources.
1368 */
1369 mb();
1370 udelay(1);
1371}
1372
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001373static int qdss_clk_enable(struct clk *c)
1374{
1375 struct rcg_clk *clk = to_rcg_clk(c);
1376 const struct qdss_bank *bank = clk->bank_info;
1377 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1378 int ret;
1379
1380 /* Switch to bank 1 */
1381 reg = readl_relaxed(clk->ns_reg);
1382 reg |= bank_sel_mask;
1383 writel_relaxed(reg, clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001384
1385 ret = rcg_clk_enable(c);
1386 if (ret) {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001387 /* Switch to bank 0 */
1388 reg &= ~bank_sel_mask;
1389 writel_relaxed(reg, clk->ns_reg);
1390 }
1391 return ret;
1392}
1393
1394static void qdss_clk_disable(struct clk *c)
1395{
1396 struct rcg_clk *clk = to_rcg_clk(c);
1397 const struct qdss_bank *bank = clk->bank_info;
1398 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1399
1400 rcg_clk_disable(c);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001401 /* Switch to bank 0 */
Stephen Boyddbeca472011-09-12 19:21:22 -07001402 reg = readl_relaxed(clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001403 reg &= ~bank_sel_mask;
1404 writel_relaxed(reg, clk->ns_reg);
1405}
1406
1407static void qdss_clk_auto_off(struct clk *c)
1408{
1409 struct rcg_clk *clk = to_rcg_clk(c);
1410 const struct qdss_bank *bank = clk->bank_info;
1411 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1412
1413 rcg_clk_auto_off(c);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001414 /* Switch to bank 0 */
Stephen Boyddbeca472011-09-12 19:21:22 -07001415 reg = readl_relaxed(clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001416 reg &= ~bank_sel_mask;
1417 writel_relaxed(reg, clk->ns_reg);
1418}
1419
1420static struct clk_ops clk_ops_qdss = {
1421 .enable = qdss_clk_enable,
1422 .disable = qdss_clk_disable,
1423 .auto_off = qdss_clk_auto_off,
Stephen Boydd4de6d72011-09-13 13:01:40 -07001424 .handoff = qdss_clk_handoff,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001425 .set_rate = rcg_clk_set_rate,
1426 .set_min_rate = rcg_clk_set_min_rate,
1427 .get_rate = rcg_clk_get_rate,
1428 .list_rate = rcg_clk_list_rate,
1429 .is_enabled = rcg_clk_is_enabled,
1430 .round_rate = rcg_clk_round_rate,
1431 .reset = soc_clk_reset,
1432 .is_local = local_clk_is_local,
1433 .get_parent = rcg_clk_get_parent,
1434};
1435
1436static struct qdss_bank bdiv_info_qdss = {
1437 .bank_sel_mask = BIT(0),
1438 .ns_reg = QDSS_AT_CLK_SRC1_NS_REG,
1439 .ns_mask = BM(6, 0),
1440};
1441
1442static struct rcg_clk qdss_at_clk = {
1443 .b = {
1444 .ctl_reg = QDSS_AT_CLK_NS_REG,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001445 .reset_reg = QDSS_RESETS_REG,
1446 .reset_mask = BIT(0),
Stephen Boydfcfd4dd2011-09-13 12:49:57 -07001447 .halt_check = NOCHECK,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001448 },
1449 .ns_reg = QDSS_AT_CLK_SRC_CTL_REG,
1450 .set_rate = set_rate_qdss,
1451 .freq_tbl = clk_tbl_qdss,
1452 .bank_info = &bdiv_info_qdss,
1453 .current_freq = &rcg_dummy_freq,
1454 .c = {
1455 .dbg_name = "qdss_at_clk",
1456 .ops = &clk_ops_qdss,
1457 CLK_INIT(qdss_at_clk.c),
1458 },
1459};
1460
1461static struct branch_clk qdss_pclkdbg_clk = {
1462 .b = {
1463 .ctl_reg = QDSS_AT_CLK_NS_REG,
1464 .en_mask = BIT(4),
1465 .reset_reg = QDSS_RESETS_REG,
1466 .reset_mask = BIT(0),
1467 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1468 .halt_bit = 9,
1469 .halt_check = HALT_VOTED
1470 },
1471 .parent = &qdss_at_clk.c,
1472 .c = {
1473 .dbg_name = "qdss_pclkdbg_clk",
1474 .ops = &clk_ops_branch,
1475 CLK_INIT(qdss_pclkdbg_clk.c),
1476 },
1477};
1478
1479static struct qdss_bank bdiv_info_qdss_trace = {
1480 .bank_sel_mask = BIT(0),
1481 .ns_reg = QDSS_TRACECLKIN_CLK_SRC1_NS_REG,
1482 .ns_mask = BM(6, 0),
1483};
1484
1485static struct rcg_clk qdss_traceclkin_clk = {
1486 .b = {
1487 .ctl_reg = QDSS_TRACECLKIN_CTL_REG,
1488 .en_mask = BIT(4),
1489 .reset_reg = QDSS_RESETS_REG,
1490 .reset_mask = BIT(0),
1491 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1492 .halt_bit = 8,
1493 .halt_check = HALT_VOTED,
1494 },
1495 .ns_reg = QDSS_TRACECLKIN_CLK_SRC_CTL_REG,
1496 .set_rate = set_rate_qdss,
1497 .freq_tbl = clk_tbl_qdss,
1498 .bank_info = &bdiv_info_qdss_trace,
1499 .current_freq = &rcg_dummy_freq,
1500 .c = {
1501 .dbg_name = "qdss_traceclkin_clk",
1502 .ops = &clk_ops_qdss,
1503 CLK_INIT(qdss_traceclkin_clk.c),
1504 },
1505};
1506
1507static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
Stephen Boydd4de6d72011-09-13 13:01:40 -07001508 F_QDSS( 27000000, pxo, 1, LOW),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001509 F_QDSS(200000000, pll3, 6, LOW),
1510 F_QDSS(400000000, pll3, 3, NOMINAL),
1511 F_END
1512};
1513
1514static struct qdss_bank bdiv_info_qdss_tsctr = {
1515 .bank_sel_mask = BIT(0),
1516 .ns_reg = QDSS_TSCTR_CLK_SRC1_NS_REG,
1517 .ns_mask = BM(6, 0),
1518};
1519
1520static struct rcg_clk qdss_tsctr_clk = {
1521 .b = {
1522 .ctl_reg = QDSS_TSCTR_CTL_REG,
1523 .en_mask = BIT(4),
1524 .reset_reg = QDSS_RESETS_REG,
1525 .reset_mask = BIT(3),
1526 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1527 .halt_bit = 7,
1528 .halt_check = HALT_VOTED,
1529 },
1530 .ns_reg = QDSS_TSCTR_CLK_SRC_CTL_REG,
1531 .set_rate = set_rate_qdss,
1532 .freq_tbl = clk_tbl_qdss_tsctr,
1533 .bank_info = &bdiv_info_qdss_tsctr,
1534 .current_freq = &rcg_dummy_freq,
1535 .c = {
1536 .dbg_name = "qdss_tsctr_clk",
1537 .ops = &clk_ops_qdss,
1538 CLK_INIT(qdss_tsctr_clk.c),
1539 },
1540};
1541
1542static struct branch_clk qdss_stm_clk = {
1543 .b = {
1544 .ctl_reg = QDSS_STM_CLK_CTL_REG,
1545 .en_mask = BIT(4),
1546 .reset_reg = QDSS_RESETS_REG,
1547 .reset_mask = BIT(1),
1548 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1549 .halt_bit = 20,
1550 .halt_check = HALT_VOTED,
1551 },
1552 .c = {
1553 .dbg_name = "qdss_stm_clk",
1554 .ops = &clk_ops_branch,
1555 CLK_INIT(qdss_stm_clk.c),
1556 },
1557};
1558
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001559#define F_PDM(f, s, d, v) \
1560 { \
1561 .freq_hz = f, \
1562 .src_clk = &s##_clk.c, \
1563 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
1564 .sys_vdd = v, \
1565 }
1566static struct clk_freq_tbl clk_tbl_pdm[] = {
1567 F_PDM( 0, gnd, 1, NONE),
1568 F_PDM(27000000, pxo, 1, LOW),
1569 F_END
1570};
1571
1572static struct rcg_clk pdm_clk = {
1573 .b = {
1574 .ctl_reg = PDM_CLK_NS_REG,
1575 .en_mask = BIT(9),
1576 .reset_reg = PDM_CLK_NS_REG,
1577 .reset_mask = BIT(12),
1578 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1579 .halt_bit = 3,
1580 },
1581 .ns_reg = PDM_CLK_NS_REG,
1582 .root_en_mask = BIT(11),
1583 .ns_mask = BM(1, 0),
1584 .set_rate = set_rate_nop,
1585 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001586 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001587 .c = {
1588 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001589 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001590 CLK_INIT(pdm_clk.c),
1591 },
1592};
1593
1594static struct branch_clk pmem_clk = {
1595 .b = {
1596 .ctl_reg = PMEM_ACLK_CTL_REG,
1597 .en_mask = BIT(4),
1598 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1599 .halt_bit = 20,
1600 },
1601 .c = {
1602 .dbg_name = "pmem_clk",
1603 .ops = &clk_ops_branch,
1604 CLK_INIT(pmem_clk.c),
1605 },
1606};
1607
1608#define F_PRNG(f, s, v) \
1609 { \
1610 .freq_hz = f, \
1611 .src_clk = &s##_clk.c, \
1612 .sys_vdd = v, \
1613 }
1614static struct clk_freq_tbl clk_tbl_prng[] = {
1615 F_PRNG(64000000, pll8, NOMINAL),
1616 F_END
1617};
1618
1619static struct rcg_clk prng_clk = {
1620 .b = {
1621 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1622 .en_mask = BIT(10),
1623 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1624 .halt_check = HALT_VOTED,
1625 .halt_bit = 10,
1626 },
1627 .set_rate = set_rate_nop,
1628 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001629 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001630 .c = {
1631 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001632 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001633 CLK_INIT(prng_clk.c),
1634 },
1635};
1636
Stephen Boyda78a7402011-08-02 11:23:39 -07001637#define CLK_SDC(name, n, h_b, f_table) \
1638 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001639 .b = { \
1640 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1641 .en_mask = BIT(9), \
1642 .reset_reg = SDCn_RESET_REG(n), \
1643 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001644 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001645 .halt_bit = h_b, \
1646 }, \
1647 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1648 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1649 .root_en_mask = BIT(11), \
1650 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1651 .set_rate = set_rate_mnd, \
Stephen Boyda78a7402011-08-02 11:23:39 -07001652 .freq_tbl = f_table, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001653 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001654 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001655 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001656 .ops = &clk_ops_rcg_8960, \
Stephen Boyda78a7402011-08-02 11:23:39 -07001657 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001658 }, \
1659 }
1660#define F_SDC(f, s, d, m, n, v) \
1661 { \
1662 .freq_hz = f, \
1663 .src_clk = &s##_clk.c, \
1664 .md_val = MD8(16, m, 0, n), \
1665 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1666 .mnd_en_mask = BIT(8) * !!(n), \
1667 .sys_vdd = v, \
1668 }
Stephen Boyda78a7402011-08-02 11:23:39 -07001669static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
1670 F_SDC( 0, gnd, 1, 0, 0, NONE),
1671 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1672 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1673 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1674 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1675 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1676 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1677 F_SDC( 48000000, pll8, 4, 1, 2, LOW),
1678 F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
1679 F_SDC( 96000000, pll8, 4, 0, 0, NOMINAL),
1680 F_END
1681};
1682
1683static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
1684static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
1685
1686static struct clk_freq_tbl clk_tbl_sdc3[] = {
1687 F_SDC( 0, gnd, 1, 0, 0, NONE),
1688 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1689 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1690 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1691 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1692 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1693 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1694 F_SDC( 48000000, pll8, 4, 1, 2, LOW),
1695 F_SDC( 64000000, pll8, 3, 1, 2, LOW),
1696 F_SDC( 96000000, pll8, 4, 0, 0, LOW),
1697 F_SDC(192000000, pll8, 2, 0, 0, NOMINAL),
1698 F_END
1699};
1700
1701static CLK_SDC(sdc3_clk, 3, 4, clk_tbl_sdc3);
1702
1703static struct clk_freq_tbl clk_tbl_sdc4_5[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001704 F_SDC( 0, gnd, 1, 0, 0, NONE),
1705 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1706 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1707 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1708 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1709 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1710 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1711 F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
1712 F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001713 F_END
1714};
1715
Stephen Boyda78a7402011-08-02 11:23:39 -07001716static CLK_SDC(sdc4_clk, 4, 3, clk_tbl_sdc4_5);
1717static CLK_SDC(sdc5_clk, 5, 2, clk_tbl_sdc4_5);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001718
1719#define F_TSIF_REF(f, s, d, m, n, v) \
1720 { \
1721 .freq_hz = f, \
1722 .src_clk = &s##_clk.c, \
1723 .md_val = MD16(m, n), \
1724 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1725 .mnd_en_mask = BIT(8) * !!(n), \
1726 .sys_vdd = v, \
1727 }
1728static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
1729 F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
1730 F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
1731 F_END
1732};
1733
1734static struct rcg_clk tsif_ref_clk = {
1735 .b = {
1736 .ctl_reg = TSIF_REF_CLK_NS_REG,
1737 .en_mask = BIT(9),
1738 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1739 .halt_bit = 5,
1740 },
1741 .ns_reg = TSIF_REF_CLK_NS_REG,
1742 .md_reg = TSIF_REF_CLK_MD_REG,
1743 .root_en_mask = BIT(11),
1744 .ns_mask = (BM(31, 16) | BM(6, 0)),
1745 .set_rate = set_rate_mnd,
1746 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001747 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001748 .c = {
1749 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001750 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001751 CLK_INIT(tsif_ref_clk.c),
1752 },
1753};
1754
1755#define F_TSSC(f, s, v) \
1756 { \
1757 .freq_hz = f, \
1758 .src_clk = &s##_clk.c, \
1759 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
1760 .sys_vdd = v, \
1761 }
1762static struct clk_freq_tbl clk_tbl_tssc[] = {
1763 F_TSSC( 0, gnd, NONE),
1764 F_TSSC(27000000, pxo, LOW),
1765 F_END
1766};
1767
1768static struct rcg_clk tssc_clk = {
1769 .b = {
1770 .ctl_reg = TSSC_CLK_CTL_REG,
1771 .en_mask = BIT(4),
1772 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1773 .halt_bit = 4,
1774 },
1775 .ns_reg = TSSC_CLK_CTL_REG,
1776 .ns_mask = BM(1, 0),
1777 .set_rate = set_rate_nop,
1778 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001779 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001780 .c = {
1781 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001782 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001783 CLK_INIT(tssc_clk.c),
1784 },
1785};
1786
Tianyi Gou41515e22011-09-01 19:37:43 -07001787#define CLK_USB_HS(name, n, h_b) \
1788 static struct rcg_clk name = { \
1789 .b = { \
1790 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1791 .en_mask = BIT(9), \
1792 .reset_reg = USB_HS##n##_RESET_REG, \
1793 .reset_mask = BIT(0), \
1794 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1795 .halt_bit = h_b, \
1796 }, \
1797 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1798 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1799 .root_en_mask = BIT(11), \
1800 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1801 .set_rate = set_rate_mnd, \
1802 .freq_tbl = clk_tbl_usb, \
1803 .current_freq = &rcg_dummy_freq, \
1804 .c = { \
1805 .dbg_name = #name, \
1806 .ops = &clk_ops_rcg_8960, \
1807 CLK_INIT(name.c), \
1808 }, \
1809}
1810
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001811#define F_USB(f, s, d, m, n, v) \
1812 { \
1813 .freq_hz = f, \
1814 .src_clk = &s##_clk.c, \
1815 .md_val = MD8(16, m, 0, n), \
1816 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1817 .mnd_en_mask = BIT(8) * !!(n), \
1818 .sys_vdd = v, \
1819 }
1820static struct clk_freq_tbl clk_tbl_usb[] = {
1821 F_USB( 0, gnd, 1, 0, 0, NONE),
1822 F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
1823 F_END
1824};
1825
Tianyi Gou41515e22011-09-01 19:37:43 -07001826CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1827CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1828CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001829
Stephen Boyd94625ef2011-07-12 17:06:01 -07001830static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
1831 F_USB( 0, gnd, 1, 0, 0, NONE),
1832 F_USB(60000000, pll8, 1, 5, 32, LOW),
1833 F_END
1834};
1835
1836static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1837 .b = {
1838 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1839 .en_mask = BIT(9),
1840 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1841 .halt_bit = 26,
1842 },
1843 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1844 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1845 .root_en_mask = BIT(11),
1846 .ns_mask = (BM(23, 16) | BM(6, 0)),
1847 .set_rate = set_rate_mnd,
1848 .freq_tbl = clk_tbl_usb_hsic,
1849 .current_freq = &rcg_dummy_freq,
1850 .c = {
1851 .dbg_name = "usb_hsic_xcvr_fs_clk",
1852 .ops = &clk_ops_rcg_8960,
1853 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1854 },
1855};
1856
1857static struct branch_clk usb_hsic_system_clk = {
1858 .b = {
1859 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1860 .en_mask = BIT(4),
1861 .reset_reg = USB_HSIC_RESET_REG,
1862 .reset_mask = BIT(0),
1863 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1864 .halt_bit = 24,
1865 },
1866 .parent = &usb_hsic_xcvr_fs_clk.c,
1867 .c = {
1868 .dbg_name = "usb_hsic_system_clk",
1869 .ops = &clk_ops_branch,
1870 CLK_INIT(usb_hsic_system_clk.c),
1871 },
1872};
1873
1874#define F_USB_HSIC(f, s, v) \
1875 { \
1876 .freq_hz = f, \
1877 .src_clk = &s##_clk.c, \
1878 .sys_vdd = v, \
1879 }
1880static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
1881 F_USB_HSIC(480000000, pll14, LOW),
1882 F_END
1883};
1884
1885static struct rcg_clk usb_hsic_hsic_src_clk = {
1886 .b = {
1887 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1888 .halt_check = NOCHECK,
1889 },
1890 .root_en_mask = BIT(0),
1891 .set_rate = set_rate_nop,
1892 .freq_tbl = clk_tbl_usb2_hsic,
1893 .current_freq = &rcg_dummy_freq,
1894 .c = {
1895 .dbg_name = "usb_hsic_hsic_src_clk",
1896 .ops = &clk_ops_rcg_8960,
1897 CLK_INIT(usb_hsic_hsic_src_clk.c),
1898 },
1899};
1900
1901static struct branch_clk usb_hsic_hsic_clk = {
1902 .b = {
1903 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1904 .en_mask = BIT(0),
1905 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1906 .halt_bit = 19,
1907 },
1908 .parent = &usb_hsic_hsic_src_clk.c,
1909 .c = {
1910 .dbg_name = "usb_hsic_hsic_clk",
1911 .ops = &clk_ops_branch,
1912 CLK_INIT(usb_hsic_hsic_clk.c),
1913 },
1914};
1915
1916#define F_USB_HSIO_CAL(f, s, v) \
1917 { \
1918 .freq_hz = f, \
1919 .src_clk = &s##_clk.c, \
1920 .sys_vdd = v, \
1921 }
1922static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
1923 F_USB_HSIO_CAL(9000000, pxo, LOW),
1924 F_END
1925};
1926
1927static struct rcg_clk usb_hsic_hsio_cal_clk = {
1928 .b = {
1929 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1930 .en_mask = BIT(0),
1931 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1932 .halt_bit = 23,
1933 },
1934 .set_rate = set_rate_nop,
1935 .freq_tbl = clk_tbl_usb_hsio_cal,
1936 .current_freq = &rcg_dummy_freq,
1937 .c = {
1938 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyda0e82ec2011-09-19 12:18:45 -07001939 .ops = &clk_ops_rcg_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07001940 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1941 },
1942};
1943
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001944static struct branch_clk usb_phy0_clk = {
1945 .b = {
1946 .reset_reg = USB_PHY0_RESET_REG,
1947 .reset_mask = BIT(0),
1948 },
1949 .c = {
1950 .dbg_name = "usb_phy0_clk",
1951 .ops = &clk_ops_reset,
1952 CLK_INIT(usb_phy0_clk.c),
1953 },
1954};
1955
1956#define CLK_USB_FS(i, n) \
1957 struct rcg_clk i##_clk = { \
1958 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1959 .b = { \
1960 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1961 .halt_check = NOCHECK, \
1962 }, \
1963 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1964 .root_en_mask = BIT(11), \
1965 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1966 .set_rate = set_rate_mnd, \
1967 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001968 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001969 .c = { \
1970 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001971 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001972 CLK_INIT(i##_clk.c), \
1973 }, \
1974 }
1975
1976static CLK_USB_FS(usb_fs1_src, 1);
1977static struct branch_clk usb_fs1_xcvr_clk = {
1978 .b = {
1979 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1980 .en_mask = BIT(9),
1981 .reset_reg = USB_FSn_RESET_REG(1),
1982 .reset_mask = BIT(1),
1983 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1984 .halt_bit = 15,
1985 },
1986 .parent = &usb_fs1_src_clk.c,
1987 .c = {
1988 .dbg_name = "usb_fs1_xcvr_clk",
1989 .ops = &clk_ops_branch,
1990 CLK_INIT(usb_fs1_xcvr_clk.c),
1991 },
1992};
1993
1994static struct branch_clk usb_fs1_sys_clk = {
1995 .b = {
1996 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1997 .en_mask = BIT(4),
1998 .reset_reg = USB_FSn_RESET_REG(1),
1999 .reset_mask = BIT(0),
2000 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2001 .halt_bit = 16,
2002 },
2003 .parent = &usb_fs1_src_clk.c,
2004 .c = {
2005 .dbg_name = "usb_fs1_sys_clk",
2006 .ops = &clk_ops_branch,
2007 CLK_INIT(usb_fs1_sys_clk.c),
2008 },
2009};
2010
2011static CLK_USB_FS(usb_fs2_src, 2);
2012static struct branch_clk usb_fs2_xcvr_clk = {
2013 .b = {
2014 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
2015 .en_mask = BIT(9),
2016 .reset_reg = USB_FSn_RESET_REG(2),
2017 .reset_mask = BIT(1),
2018 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2019 .halt_bit = 12,
2020 },
2021 .parent = &usb_fs2_src_clk.c,
2022 .c = {
2023 .dbg_name = "usb_fs2_xcvr_clk",
2024 .ops = &clk_ops_branch,
2025 CLK_INIT(usb_fs2_xcvr_clk.c),
2026 },
2027};
2028
2029static struct branch_clk usb_fs2_sys_clk = {
2030 .b = {
2031 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
2032 .en_mask = BIT(4),
2033 .reset_reg = USB_FSn_RESET_REG(2),
2034 .reset_mask = BIT(0),
2035 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2036 .halt_bit = 13,
2037 },
2038 .parent = &usb_fs2_src_clk.c,
2039 .c = {
2040 .dbg_name = "usb_fs2_sys_clk",
2041 .ops = &clk_ops_branch,
2042 CLK_INIT(usb_fs2_sys_clk.c),
2043 },
2044};
2045
2046/* Fast Peripheral Bus Clocks */
2047static struct branch_clk ce1_core_clk = {
2048 .b = {
2049 .ctl_reg = CE1_CORE_CLK_CTL_REG,
2050 .en_mask = BIT(4),
2051 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2052 .halt_bit = 27,
2053 },
2054 .c = {
2055 .dbg_name = "ce1_core_clk",
2056 .ops = &clk_ops_branch,
2057 CLK_INIT(ce1_core_clk.c),
2058 },
2059};
Tianyi Gou41515e22011-09-01 19:37:43 -07002060
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002061static struct branch_clk ce1_p_clk = {
2062 .b = {
2063 .ctl_reg = CE1_HCLK_CTL_REG,
2064 .en_mask = BIT(4),
2065 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2066 .halt_bit = 1,
2067 },
2068 .c = {
2069 .dbg_name = "ce1_p_clk",
2070 .ops = &clk_ops_branch,
2071 CLK_INIT(ce1_p_clk.c),
2072 },
2073};
2074
Tianyi Gou41515e22011-09-01 19:37:43 -07002075#define F_CE3(f, s, d, v) \
2076 { \
2077 .freq_hz = f, \
2078 .src_clk = &s##_clk.c, \
2079 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
2080 .sys_vdd = v, \
2081 }
2082
2083static struct clk_freq_tbl clk_tbl_ce3[] = {
2084 F_CE3( 0, gnd, 1, NONE),
2085 F_CE3( 48000000, pll8, 8, LOW),
2086 F_CE3(100000000, pll3, 12, NOMINAL),
2087 F_END
2088};
2089
2090static struct rcg_clk ce3_src_clk = {
2091 .b = {
2092 .ctl_reg = CE3_CLK_SRC_NS_REG,
2093 .halt_check = NOCHECK,
2094 },
2095 .ns_reg = CE3_CLK_SRC_NS_REG,
2096 .root_en_mask = BIT(7),
2097 .ns_mask = BM(6, 0),
2098 .set_rate = set_rate_nop,
2099 .freq_tbl = clk_tbl_ce3,
2100 .current_freq = &rcg_dummy_freq,
2101 .c = {
2102 .dbg_name = "ce3_src_clk",
2103 .ops = &clk_ops_rcg_8960,
2104 CLK_INIT(ce3_src_clk.c),
2105 },
2106};
2107
2108static struct branch_clk ce3_core_clk = {
2109 .b = {
2110 .ctl_reg = CE3_CORE_CLK_CTL_REG,
2111 .en_mask = BIT(4),
2112 .reset_reg = CE3_CORE_CLK_CTL_REG,
2113 .reset_mask = BIT(7),
2114 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2115 .halt_bit = 5,
2116 },
2117 .parent = &ce3_src_clk.c,
2118 .c = {
2119 .dbg_name = "ce3_core_clk",
2120 .ops = &clk_ops_branch,
2121 CLK_INIT(ce3_core_clk.c),
2122 }
2123};
2124
2125static struct branch_clk ce3_p_clk = {
2126 .b = {
2127 .ctl_reg = CE3_HCLK_CTL_REG,
2128 .en_mask = BIT(4),
2129 .reset_reg = CE3_HCLK_CTL_REG,
2130 .reset_mask = BIT(7),
2131 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
2132 .halt_bit = 16,
2133 },
2134 .parent = &ce3_src_clk.c,
2135 .c = {
2136 .dbg_name = "ce3_p_clk",
2137 .ops = &clk_ops_branch,
2138 CLK_INIT(ce3_p_clk.c),
2139 }
2140};
2141
2142static struct branch_clk sata_phy_ref_clk = {
2143 .b = {
2144 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
2145 .en_mask = BIT(4),
2146 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2147 .halt_bit = 24,
2148 },
2149 .parent = &pxo_clk.c,
2150 .c = {
2151 .dbg_name = "sata_phy_ref_clk",
2152 .ops = &clk_ops_branch,
2153 CLK_INIT(sata_phy_ref_clk.c),
2154 },
2155};
2156
2157static struct branch_clk pcie_p_clk = {
2158 .b = {
2159 .ctl_reg = PCIE_HCLK_CTL_REG,
2160 .en_mask = BIT(4),
2161 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2162 .halt_bit = 8,
2163 },
2164 .c = {
2165 .dbg_name = "pcie_p_clk",
2166 .ops = &clk_ops_branch,
2167 CLK_INIT(pcie_p_clk.c),
2168 },
2169};
2170
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002171static struct branch_clk dma_bam_p_clk = {
2172 .b = {
2173 .ctl_reg = DMA_BAM_HCLK_CTL,
2174 .en_mask = BIT(4),
2175 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2176 .halt_bit = 12,
2177 },
2178 .c = {
2179 .dbg_name = "dma_bam_p_clk",
2180 .ops = &clk_ops_branch,
2181 CLK_INIT(dma_bam_p_clk.c),
2182 },
2183};
2184
2185static struct branch_clk gsbi1_p_clk = {
2186 .b = {
2187 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
2188 .en_mask = BIT(4),
2189 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2190 .halt_bit = 11,
2191 },
2192 .c = {
2193 .dbg_name = "gsbi1_p_clk",
2194 .ops = &clk_ops_branch,
2195 CLK_INIT(gsbi1_p_clk.c),
2196 },
2197};
2198
2199static struct branch_clk gsbi2_p_clk = {
2200 .b = {
2201 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2202 .en_mask = BIT(4),
2203 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2204 .halt_bit = 7,
2205 },
2206 .c = {
2207 .dbg_name = "gsbi2_p_clk",
2208 .ops = &clk_ops_branch,
2209 CLK_INIT(gsbi2_p_clk.c),
2210 },
2211};
2212
2213static struct branch_clk gsbi3_p_clk = {
2214 .b = {
2215 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2216 .en_mask = BIT(4),
2217 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2218 .halt_bit = 3,
2219 },
2220 .c = {
2221 .dbg_name = "gsbi3_p_clk",
2222 .ops = &clk_ops_branch,
2223 CLK_INIT(gsbi3_p_clk.c),
2224 },
2225};
2226
2227static struct branch_clk gsbi4_p_clk = {
2228 .b = {
2229 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2230 .en_mask = BIT(4),
2231 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2232 .halt_bit = 27,
2233 },
2234 .c = {
2235 .dbg_name = "gsbi4_p_clk",
2236 .ops = &clk_ops_branch,
2237 CLK_INIT(gsbi4_p_clk.c),
2238 },
2239};
2240
2241static struct branch_clk gsbi5_p_clk = {
2242 .b = {
2243 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2244 .en_mask = BIT(4),
2245 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2246 .halt_bit = 23,
2247 },
2248 .c = {
2249 .dbg_name = "gsbi5_p_clk",
2250 .ops = &clk_ops_branch,
2251 CLK_INIT(gsbi5_p_clk.c),
2252 },
2253};
2254
2255static struct branch_clk gsbi6_p_clk = {
2256 .b = {
2257 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2258 .en_mask = BIT(4),
2259 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2260 .halt_bit = 19,
2261 },
2262 .c = {
2263 .dbg_name = "gsbi6_p_clk",
2264 .ops = &clk_ops_branch,
2265 CLK_INIT(gsbi6_p_clk.c),
2266 },
2267};
2268
2269static struct branch_clk gsbi7_p_clk = {
2270 .b = {
2271 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2272 .en_mask = BIT(4),
2273 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2274 .halt_bit = 15,
2275 },
2276 .c = {
2277 .dbg_name = "gsbi7_p_clk",
2278 .ops = &clk_ops_branch,
2279 CLK_INIT(gsbi7_p_clk.c),
2280 },
2281};
2282
2283static struct branch_clk gsbi8_p_clk = {
2284 .b = {
2285 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2286 .en_mask = BIT(4),
2287 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2288 .halt_bit = 11,
2289 },
2290 .c = {
2291 .dbg_name = "gsbi8_p_clk",
2292 .ops = &clk_ops_branch,
2293 CLK_INIT(gsbi8_p_clk.c),
2294 },
2295};
2296
2297static struct branch_clk gsbi9_p_clk = {
2298 .b = {
2299 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2300 .en_mask = BIT(4),
2301 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2302 .halt_bit = 7,
2303 },
2304 .c = {
2305 .dbg_name = "gsbi9_p_clk",
2306 .ops = &clk_ops_branch,
2307 CLK_INIT(gsbi9_p_clk.c),
2308 },
2309};
2310
2311static struct branch_clk gsbi10_p_clk = {
2312 .b = {
2313 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2314 .en_mask = BIT(4),
2315 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2316 .halt_bit = 3,
2317 },
2318 .c = {
2319 .dbg_name = "gsbi10_p_clk",
2320 .ops = &clk_ops_branch,
2321 CLK_INIT(gsbi10_p_clk.c),
2322 },
2323};
2324
2325static struct branch_clk gsbi11_p_clk = {
2326 .b = {
2327 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2328 .en_mask = BIT(4),
2329 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2330 .halt_bit = 18,
2331 },
2332 .c = {
2333 .dbg_name = "gsbi11_p_clk",
2334 .ops = &clk_ops_branch,
2335 CLK_INIT(gsbi11_p_clk.c),
2336 },
2337};
2338
2339static struct branch_clk gsbi12_p_clk = {
2340 .b = {
2341 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2342 .en_mask = BIT(4),
2343 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2344 .halt_bit = 14,
2345 },
2346 .c = {
2347 .dbg_name = "gsbi12_p_clk",
2348 .ops = &clk_ops_branch,
2349 CLK_INIT(gsbi12_p_clk.c),
2350 },
2351};
2352
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002353static struct branch_clk qdss_p_clk = {
2354 .b = {
2355 .ctl_reg = QDSS_HCLK_CTL_REG,
2356 .en_mask = BIT(4),
2357 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2358 .halt_bit = 11,
2359 .halt_check = HALT_VOTED,
2360 .reset_reg = QDSS_RESETS_REG,
2361 .reset_mask = BIT(2),
2362 },
2363 .c = {
2364 .dbg_name = "qdss_p_clk",
2365 .ops = &clk_ops_branch,
2366 CLK_INIT(qdss_p_clk.c),
Tianyi Gou41515e22011-09-01 19:37:43 -07002367 }
2368};
2369
2370static struct branch_clk sata_phy_cfg_clk = {
2371 .b = {
2372 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2373 .en_mask = BIT(4),
2374 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2375 .halt_bit = 12,
2376 },
2377 .c = {
2378 .dbg_name = "sata_phy_cfg_clk",
2379 .ops = &clk_ops_branch,
2380 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002381 },
2382};
2383
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002384static struct branch_clk tsif_p_clk = {
2385 .b = {
2386 .ctl_reg = TSIF_HCLK_CTL_REG,
2387 .en_mask = BIT(4),
2388 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2389 .halt_bit = 7,
2390 },
2391 .c = {
2392 .dbg_name = "tsif_p_clk",
2393 .ops = &clk_ops_branch,
2394 CLK_INIT(tsif_p_clk.c),
2395 },
2396};
2397
2398static struct branch_clk usb_fs1_p_clk = {
2399 .b = {
2400 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2401 .en_mask = BIT(4),
2402 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2403 .halt_bit = 17,
2404 },
2405 .c = {
2406 .dbg_name = "usb_fs1_p_clk",
2407 .ops = &clk_ops_branch,
2408 CLK_INIT(usb_fs1_p_clk.c),
2409 },
2410};
2411
2412static struct branch_clk usb_fs2_p_clk = {
2413 .b = {
2414 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2415 .en_mask = BIT(4),
2416 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2417 .halt_bit = 14,
2418 },
2419 .c = {
2420 .dbg_name = "usb_fs2_p_clk",
2421 .ops = &clk_ops_branch,
2422 CLK_INIT(usb_fs2_p_clk.c),
2423 },
2424};
2425
2426static struct branch_clk usb_hs1_p_clk = {
2427 .b = {
2428 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2429 .en_mask = BIT(4),
2430 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2431 .halt_bit = 1,
2432 },
2433 .c = {
2434 .dbg_name = "usb_hs1_p_clk",
2435 .ops = &clk_ops_branch,
2436 CLK_INIT(usb_hs1_p_clk.c),
2437 },
2438};
2439
Tianyi Gou41515e22011-09-01 19:37:43 -07002440static struct branch_clk usb_hs3_p_clk = {
2441 .b = {
2442 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2443 .en_mask = BIT(4),
2444 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2445 .halt_bit = 31,
2446 },
2447 .c = {
2448 .dbg_name = "usb_hs3_p_clk",
2449 .ops = &clk_ops_branch,
2450 CLK_INIT(usb_hs3_p_clk.c),
2451 },
2452};
2453
2454static struct branch_clk usb_hs4_p_clk = {
2455 .b = {
2456 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2457 .en_mask = BIT(4),
2458 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2459 .halt_bit = 7,
2460 },
2461 .c = {
2462 .dbg_name = "usb_hs4_p_clk",
2463 .ops = &clk_ops_branch,
2464 CLK_INIT(usb_hs4_p_clk.c),
2465 },
2466};
2467
Stephen Boyd94625ef2011-07-12 17:06:01 -07002468static struct branch_clk usb_hsic_p_clk = {
2469 .b = {
2470 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2471 .en_mask = BIT(4),
2472 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2473 .halt_bit = 28,
2474 },
2475 .c = {
2476 .dbg_name = "usb_hsic_p_clk",
2477 .ops = &clk_ops_branch,
2478 CLK_INIT(usb_hsic_p_clk.c),
2479 },
2480};
2481
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002482static struct branch_clk sdc1_p_clk = {
2483 .b = {
2484 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2485 .en_mask = BIT(4),
2486 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2487 .halt_bit = 11,
2488 },
2489 .c = {
2490 .dbg_name = "sdc1_p_clk",
2491 .ops = &clk_ops_branch,
2492 CLK_INIT(sdc1_p_clk.c),
2493 },
2494};
2495
2496static struct branch_clk sdc2_p_clk = {
2497 .b = {
2498 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2499 .en_mask = BIT(4),
2500 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2501 .halt_bit = 10,
2502 },
2503 .c = {
2504 .dbg_name = "sdc2_p_clk",
2505 .ops = &clk_ops_branch,
2506 CLK_INIT(sdc2_p_clk.c),
2507 },
2508};
2509
2510static struct branch_clk sdc3_p_clk = {
2511 .b = {
2512 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2513 .en_mask = BIT(4),
2514 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2515 .halt_bit = 9,
2516 },
2517 .c = {
2518 .dbg_name = "sdc3_p_clk",
2519 .ops = &clk_ops_branch,
2520 CLK_INIT(sdc3_p_clk.c),
2521 },
2522};
2523
2524static struct branch_clk sdc4_p_clk = {
2525 .b = {
2526 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2527 .en_mask = BIT(4),
2528 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2529 .halt_bit = 8,
2530 },
2531 .c = {
2532 .dbg_name = "sdc4_p_clk",
2533 .ops = &clk_ops_branch,
2534 CLK_INIT(sdc4_p_clk.c),
2535 },
2536};
2537
2538static struct branch_clk sdc5_p_clk = {
2539 .b = {
2540 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2541 .en_mask = BIT(4),
2542 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2543 .halt_bit = 7,
2544 },
2545 .c = {
2546 .dbg_name = "sdc5_p_clk",
2547 .ops = &clk_ops_branch,
2548 CLK_INIT(sdc5_p_clk.c),
2549 },
2550};
2551
2552/* HW-Voteable Clocks */
2553static struct branch_clk adm0_clk = {
2554 .b = {
2555 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2556 .en_mask = BIT(2),
2557 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2558 .halt_check = HALT_VOTED,
2559 .halt_bit = 14,
2560 },
2561 .c = {
2562 .dbg_name = "adm0_clk",
2563 .ops = &clk_ops_branch,
2564 CLK_INIT(adm0_clk.c),
2565 },
2566};
2567
2568static struct branch_clk adm0_p_clk = {
2569 .b = {
2570 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2571 .en_mask = BIT(3),
2572 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2573 .halt_check = HALT_VOTED,
2574 .halt_bit = 13,
2575 },
2576 .c = {
2577 .dbg_name = "adm0_p_clk",
2578 .ops = &clk_ops_branch,
2579 CLK_INIT(adm0_p_clk.c),
2580 },
2581};
2582
2583static struct branch_clk pmic_arb0_p_clk = {
2584 .b = {
2585 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2586 .en_mask = BIT(8),
2587 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2588 .halt_check = HALT_VOTED,
2589 .halt_bit = 22,
2590 },
2591 .c = {
2592 .dbg_name = "pmic_arb0_p_clk",
2593 .ops = &clk_ops_branch,
2594 CLK_INIT(pmic_arb0_p_clk.c),
2595 },
2596};
2597
2598static struct branch_clk pmic_arb1_p_clk = {
2599 .b = {
2600 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2601 .en_mask = BIT(9),
2602 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2603 .halt_check = HALT_VOTED,
2604 .halt_bit = 21,
2605 },
2606 .c = {
2607 .dbg_name = "pmic_arb1_p_clk",
2608 .ops = &clk_ops_branch,
2609 CLK_INIT(pmic_arb1_p_clk.c),
2610 },
2611};
2612
2613static struct branch_clk pmic_ssbi2_clk = {
2614 .b = {
2615 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2616 .en_mask = BIT(7),
2617 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2618 .halt_check = HALT_VOTED,
2619 .halt_bit = 23,
2620 },
2621 .c = {
2622 .dbg_name = "pmic_ssbi2_clk",
2623 .ops = &clk_ops_branch,
2624 CLK_INIT(pmic_ssbi2_clk.c),
2625 },
2626};
2627
2628static struct branch_clk rpm_msg_ram_p_clk = {
2629 .b = {
2630 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2631 .en_mask = BIT(6),
2632 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2633 .halt_check = HALT_VOTED,
2634 .halt_bit = 12,
2635 },
2636 .c = {
2637 .dbg_name = "rpm_msg_ram_p_clk",
2638 .ops = &clk_ops_branch,
2639 CLK_INIT(rpm_msg_ram_p_clk.c),
2640 },
2641};
2642
2643/*
2644 * Multimedia Clocks
2645 */
2646
2647static struct branch_clk amp_clk = {
2648 .b = {
2649 .reset_reg = SW_RESET_CORE_REG,
2650 .reset_mask = BIT(20),
2651 },
2652 .c = {
2653 .dbg_name = "amp_clk",
2654 .ops = &clk_ops_reset,
2655 CLK_INIT(amp_clk.c),
2656 },
2657};
2658
Stephen Boyd94625ef2011-07-12 17:06:01 -07002659#define CLK_CAM(name, n, hb) \
2660 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002661 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002662 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002663 .en_mask = BIT(0), \
2664 .halt_reg = DBG_BUS_VEC_I_REG, \
2665 .halt_bit = hb, \
2666 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002667 .ns_reg = CAMCLK##n##_NS_REG, \
2668 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002669 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002670 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002671 .ctl_mask = BM(7, 6), \
2672 .set_rate = set_rate_mnd_8, \
2673 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002674 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002675 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002676 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002677 .ops = &clk_ops_rcg_8960, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002678 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002679 }, \
2680 }
2681#define F_CAM(f, s, d, m, n, v) \
2682 { \
2683 .freq_hz = f, \
2684 .src_clk = &s##_clk.c, \
2685 .md_val = MD8(8, m, 0, n), \
2686 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2687 .ctl_val = CC(6, n), \
2688 .mnd_en_mask = BIT(5) * !!(n), \
2689 .sys_vdd = v, \
2690 }
2691static struct clk_freq_tbl clk_tbl_cam[] = {
2692 F_CAM( 0, gnd, 1, 0, 0, NONE),
2693 F_CAM( 6000000, pll8, 4, 1, 16, LOW),
2694 F_CAM( 8000000, pll8, 4, 1, 12, LOW),
2695 F_CAM( 12000000, pll8, 4, 1, 8, LOW),
2696 F_CAM( 16000000, pll8, 4, 1, 6, LOW),
2697 F_CAM( 19200000, pll8, 4, 1, 5, LOW),
2698 F_CAM( 24000000, pll8, 4, 1, 4, LOW),
2699 F_CAM( 32000000, pll8, 4, 1, 3, LOW),
2700 F_CAM( 48000000, pll8, 4, 1, 2, LOW),
2701 F_CAM( 64000000, pll8, 3, 1, 2, LOW),
2702 F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
2703 F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
2704 F_END
2705};
2706
Stephen Boyd94625ef2011-07-12 17:06:01 -07002707static CLK_CAM(cam0_clk, 0, 15);
2708static CLK_CAM(cam1_clk, 1, 16);
2709static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002710
2711#define F_CSI(f, s, d, m, n, v) \
2712 { \
2713 .freq_hz = f, \
2714 .src_clk = &s##_clk.c, \
2715 .md_val = MD8(8, m, 0, n), \
2716 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2717 .ctl_val = CC(6, n), \
2718 .mnd_en_mask = BIT(5) * !!(n), \
2719 .sys_vdd = v, \
2720 }
2721static struct clk_freq_tbl clk_tbl_csi[] = {
2722 F_CSI( 0, gnd, 1, 0, 0, NONE),
2723 F_CSI( 85330000, pll8, 1, 2, 9, LOW),
2724 F_CSI(177780000, pll2, 1, 2, 9, NOMINAL),
2725 F_END
2726};
2727
2728static struct rcg_clk csi0_src_clk = {
2729 .ns_reg = CSI0_NS_REG,
2730 .b = {
2731 .ctl_reg = CSI0_CC_REG,
2732 .halt_check = NOCHECK,
2733 },
2734 .md_reg = CSI0_MD_REG,
2735 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002736 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002737 .ctl_mask = BM(7, 6),
2738 .set_rate = set_rate_mnd,
2739 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002740 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002741 .c = {
2742 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002743 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002744 CLK_INIT(csi0_src_clk.c),
2745 },
2746};
2747
2748static struct branch_clk csi0_clk = {
2749 .b = {
2750 .ctl_reg = CSI0_CC_REG,
2751 .en_mask = BIT(0),
2752 .reset_reg = SW_RESET_CORE_REG,
2753 .reset_mask = BIT(8),
2754 .halt_reg = DBG_BUS_VEC_B_REG,
2755 .halt_bit = 13,
2756 },
2757 .parent = &csi0_src_clk.c,
2758 .c = {
2759 .dbg_name = "csi0_clk",
2760 .ops = &clk_ops_branch,
2761 CLK_INIT(csi0_clk.c),
2762 },
2763};
2764
2765static struct branch_clk csi0_phy_clk = {
2766 .b = {
2767 .ctl_reg = CSI0_CC_REG,
2768 .en_mask = BIT(8),
2769 .reset_reg = SW_RESET_CORE_REG,
2770 .reset_mask = BIT(29),
2771 .halt_reg = DBG_BUS_VEC_I_REG,
2772 .halt_bit = 9,
2773 },
2774 .parent = &csi0_src_clk.c,
2775 .c = {
2776 .dbg_name = "csi0_phy_clk",
2777 .ops = &clk_ops_branch,
2778 CLK_INIT(csi0_phy_clk.c),
2779 },
2780};
2781
2782static struct rcg_clk csi1_src_clk = {
2783 .ns_reg = CSI1_NS_REG,
2784 .b = {
2785 .ctl_reg = CSI1_CC_REG,
2786 .halt_check = NOCHECK,
2787 },
2788 .md_reg = CSI1_MD_REG,
2789 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002790 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002791 .ctl_mask = BM(7, 6),
2792 .set_rate = set_rate_mnd,
2793 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002794 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002795 .c = {
2796 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002797 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002798 CLK_INIT(csi1_src_clk.c),
2799 },
2800};
2801
2802static struct branch_clk csi1_clk = {
2803 .b = {
2804 .ctl_reg = CSI1_CC_REG,
2805 .en_mask = BIT(0),
2806 .reset_reg = SW_RESET_CORE_REG,
2807 .reset_mask = BIT(18),
2808 .halt_reg = DBG_BUS_VEC_B_REG,
2809 .halt_bit = 14,
2810 },
2811 .parent = &csi1_src_clk.c,
2812 .c = {
2813 .dbg_name = "csi1_clk",
2814 .ops = &clk_ops_branch,
2815 CLK_INIT(csi1_clk.c),
2816 },
2817};
2818
2819static struct branch_clk csi1_phy_clk = {
2820 .b = {
2821 .ctl_reg = CSI1_CC_REG,
2822 .en_mask = BIT(8),
2823 .reset_reg = SW_RESET_CORE_REG,
2824 .reset_mask = BIT(28),
2825 .halt_reg = DBG_BUS_VEC_I_REG,
2826 .halt_bit = 10,
2827 },
2828 .parent = &csi1_src_clk.c,
2829 .c = {
2830 .dbg_name = "csi1_phy_clk",
2831 .ops = &clk_ops_branch,
2832 CLK_INIT(csi1_phy_clk.c),
2833 },
2834};
2835
Stephen Boyd94625ef2011-07-12 17:06:01 -07002836static struct rcg_clk csi2_src_clk = {
2837 .ns_reg = CSI2_NS_REG,
2838 .b = {
2839 .ctl_reg = CSI2_CC_REG,
2840 .halt_check = NOCHECK,
2841 },
2842 .md_reg = CSI2_MD_REG,
2843 .root_en_mask = BIT(2),
2844 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
2845 .ctl_mask = BM(7, 6),
2846 .set_rate = set_rate_mnd,
2847 .freq_tbl = clk_tbl_csi,
2848 .current_freq = &rcg_dummy_freq,
2849 .c = {
2850 .dbg_name = "csi2_src_clk",
2851 .ops = &clk_ops_rcg_8960,
2852 CLK_INIT(csi2_src_clk.c),
2853 },
2854};
2855
2856static struct branch_clk csi2_clk = {
2857 .b = {
2858 .ctl_reg = CSI2_CC_REG,
2859 .en_mask = BIT(0),
2860 .reset_reg = SW_RESET_CORE2_REG,
2861 .reset_mask = BIT(2),
2862 .halt_reg = DBG_BUS_VEC_B_REG,
2863 .halt_bit = 29,
2864 },
2865 .parent = &csi2_src_clk.c,
2866 .c = {
2867 .dbg_name = "csi2_clk",
2868 .ops = &clk_ops_branch,
2869 CLK_INIT(csi2_clk.c),
2870 },
2871};
2872
2873static struct branch_clk csi2_phy_clk = {
2874 .b = {
2875 .ctl_reg = CSI2_CC_REG,
2876 .en_mask = BIT(8),
2877 .reset_reg = SW_RESET_CORE_REG,
2878 .reset_mask = BIT(31),
2879 .halt_reg = DBG_BUS_VEC_I_REG,
2880 .halt_bit = 29,
2881 },
2882 .parent = &csi2_src_clk.c,
2883 .c = {
2884 .dbg_name = "csi2_phy_clk",
2885 .ops = &clk_ops_branch,
2886 CLK_INIT(csi2_phy_clk.c),
2887 },
2888};
2889
2890/*
2891 * The csi pix and csi rdi clocks have two bits in two registers to control a
2892 * three input mux. So we have the generic rcg_clk_enable() path handle the
2893 * first bit, and this function handle the second bit.
2894 */
2895static void set_rate_pix_rdi(struct rcg_clk *clk, struct clk_freq_tbl *nf)
2896{
2897 u32 reg = readl_relaxed(MISC_CC3_REG);
2898 u32 bit = (u32)nf->extra_freq_data;
2899 if (nf->freq_hz == 2)
2900 reg |= bit;
2901 else
2902 reg &= ~bit;
2903 writel_relaxed(reg, MISC_CC3_REG);
2904}
2905
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002906#define F_CSI_PIX(s) \
2907 { \
2908 .src_clk = &csi##s##_clk.c, \
2909 .freq_hz = s, \
2910 .ns_val = BVAL(25, 25, s), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002911 .extra_freq_data = (void *)BIT(13), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002912 }
2913static struct clk_freq_tbl clk_tbl_csi_pix[] = {
2914 F_CSI_PIX(0), /* CSI0 source */
2915 F_CSI_PIX(1), /* CSI1 source */
Stephen Boyd94625ef2011-07-12 17:06:01 -07002916 F_CSI_PIX(2), /* CSI2 source */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002917 F_END
2918};
2919
2920static struct rcg_clk csi_pix_clk = {
2921 .b = {
2922 .ctl_reg = MISC_CC_REG,
2923 .en_mask = BIT(26),
2924 .halt_check = DELAY,
2925 .reset_reg = SW_RESET_CORE_REG,
2926 .reset_mask = BIT(26),
2927 },
2928 .ns_reg = MISC_CC_REG,
2929 .ns_mask = BIT(25),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002930 .set_rate = set_rate_pix_rdi,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002931 .freq_tbl = clk_tbl_csi_pix,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002932 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002933 .c = {
2934 .dbg_name = "csi_pix_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002935 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002936 CLK_INIT(csi_pix_clk.c),
2937 },
2938};
2939
Stephen Boyd94625ef2011-07-12 17:06:01 -07002940#define F_CSI_PIX1(s) \
2941 { \
2942 .src_clk = &csi##s##_clk.c, \
2943 .freq_hz = s, \
2944 .ns_val = BVAL(9, 8, s), \
2945 }
2946static struct clk_freq_tbl clk_tbl_csi_pix1[] = {
2947 F_CSI_PIX1(0), /* CSI0 source */
2948 F_CSI_PIX1(1), /* CSI1 source */
2949 F_CSI_PIX1(2), /* CSI2 source */
2950 F_END
2951};
2952
2953static struct rcg_clk csi_pix1_clk = {
2954 .b = {
2955 .ctl_reg = MISC_CC3_REG,
2956 .en_mask = BIT(10),
2957 .halt_check = DELAY,
2958 .reset_reg = SW_RESET_CORE_REG,
2959 .reset_mask = BIT(30),
2960 },
2961 .ns_reg = MISC_CC3_REG,
2962 .ns_mask = BM(9, 8),
2963 .set_rate = set_rate_nop,
2964 .freq_tbl = clk_tbl_csi_pix1,
2965 .current_freq = &rcg_dummy_freq,
2966 .c = {
2967 .dbg_name = "csi_pix1_clk",
2968 .ops = &clk_ops_rcg_8960,
2969 CLK_INIT(csi_pix1_clk.c),
2970 },
2971};
2972
2973#define F_CSI_RDI(s) \
2974 { \
2975 .src_clk = &csi##s##_clk.c, \
2976 .freq_hz = s, \
2977 .ns_val = BVAL(12, 12, s), \
2978 .extra_freq_data = (void *)BIT(12), \
2979 }
2980static struct clk_freq_tbl clk_tbl_csi_rdi[] = {
2981 F_CSI_RDI(0), /* CSI0 source */
2982 F_CSI_RDI(1), /* CSI1 source */
2983 F_CSI_RDI(2), /* CSI2 source */
2984 F_END
2985};
2986
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002987static struct rcg_clk csi_rdi_clk = {
2988 .b = {
2989 .ctl_reg = MISC_CC_REG,
2990 .en_mask = BIT(13),
2991 .halt_check = DELAY,
2992 .reset_reg = SW_RESET_CORE_REG,
2993 .reset_mask = BIT(27),
2994 },
2995 .ns_reg = MISC_CC_REG,
2996 .ns_mask = BIT(12),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002997 .set_rate = set_rate_pix_rdi,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002998 .freq_tbl = clk_tbl_csi_rdi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002999 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003000 .c = {
3001 .dbg_name = "csi_rdi_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003002 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003003 CLK_INIT(csi_rdi_clk.c),
3004 },
3005};
3006
Stephen Boyd94625ef2011-07-12 17:06:01 -07003007#define F_CSI_RDI1(s) \
3008 { \
3009 .src_clk = &csi##s##_clk.c, \
3010 .freq_hz = s, \
3011 .ns_val = BVAL(1, 0, s), \
3012 }
3013static struct clk_freq_tbl clk_tbl_csi_rdi1[] = {
3014 F_CSI_RDI1(0), /* CSI0 source */
3015 F_CSI_RDI1(1), /* CSI1 source */
3016 F_CSI_RDI1(2), /* CSI2 source */
3017 F_END
3018};
3019
3020static struct rcg_clk csi_rdi1_clk = {
3021 .b = {
3022 .ctl_reg = MISC_CC3_REG,
3023 .en_mask = BIT(2),
3024 .halt_check = DELAY,
3025 .reset_reg = SW_RESET_CORE2_REG,
3026 .reset_mask = BIT(1),
3027 },
3028 .ns_reg = MISC_CC3_REG,
3029 .ns_mask = BM(1, 0),
3030 .set_rate = set_rate_nop,
3031 .freq_tbl = clk_tbl_csi_rdi1,
3032 .current_freq = &rcg_dummy_freq,
3033 .c = {
3034 .dbg_name = "csi_rdi1_clk",
3035 .ops = &clk_ops_rcg_8960,
3036 CLK_INIT(csi_rdi1_clk.c),
3037 },
3038};
3039
3040#define F_CSI_RDI2(s) \
3041 { \
3042 .src_clk = &csi##s##_clk.c, \
3043 .freq_hz = s, \
3044 .ns_val = BVAL(5, 4, s), \
3045 }
3046static struct clk_freq_tbl clk_tbl_csi_rdi2[] = {
3047 F_CSI_RDI2(0), /* CSI0 source */
3048 F_CSI_RDI2(1), /* CSI1 source */
3049 F_CSI_RDI2(2), /* CSI2 source */
3050 F_END
3051};
3052
3053static struct rcg_clk csi_rdi2_clk = {
3054 .b = {
3055 .ctl_reg = MISC_CC3_REG,
3056 .en_mask = BIT(6),
3057 .halt_check = DELAY,
3058 .reset_reg = SW_RESET_CORE2_REG,
3059 .reset_mask = BIT(0),
3060 },
3061 .ns_reg = MISC_CC3_REG,
3062 .ns_mask = BM(5, 4),
3063 .set_rate = set_rate_nop,
3064 .freq_tbl = clk_tbl_csi_rdi2,
3065 .current_freq = &rcg_dummy_freq,
3066 .c = {
3067 .dbg_name = "csi_rdi2_clk",
3068 .ops = &clk_ops_rcg_8960,
3069 CLK_INIT(csi_rdi2_clk.c),
3070 },
3071};
3072
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003073#define F_CSI_PHYTIMER(f, s, d, m, n, v) \
3074 { \
3075 .freq_hz = f, \
3076 .src_clk = &s##_clk.c, \
3077 .md_val = MD8(8, m, 0, n), \
3078 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3079 .ctl_val = CC(6, n), \
3080 .mnd_en_mask = BIT(5) * !!(n), \
3081 .sys_vdd = v, \
3082 }
3083static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
3084 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0, NONE),
3085 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9, LOW),
3086 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9, NOMINAL),
3087 F_END
3088};
3089
3090static struct rcg_clk csiphy_timer_src_clk = {
3091 .ns_reg = CSIPHYTIMER_NS_REG,
3092 .b = {
3093 .ctl_reg = CSIPHYTIMER_CC_REG,
3094 .halt_check = NOCHECK,
3095 },
3096 .md_reg = CSIPHYTIMER_MD_REG,
3097 .root_en_mask = BIT(2),
3098 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
3099 .ctl_mask = BM(7, 6),
3100 .set_rate = set_rate_mnd_8,
3101 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003102 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003103 .c = {
3104 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003105 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003106 CLK_INIT(csiphy_timer_src_clk.c),
3107 },
3108};
3109
3110static struct branch_clk csi0phy_timer_clk = {
3111 .b = {
3112 .ctl_reg = CSIPHYTIMER_CC_REG,
3113 .en_mask = BIT(0),
3114 .halt_reg = DBG_BUS_VEC_I_REG,
3115 .halt_bit = 17,
3116 },
3117 .parent = &csiphy_timer_src_clk.c,
3118 .c = {
3119 .dbg_name = "csi0phy_timer_clk",
3120 .ops = &clk_ops_branch,
3121 CLK_INIT(csi0phy_timer_clk.c),
3122 },
3123};
3124
3125static struct branch_clk csi1phy_timer_clk = {
3126 .b = {
3127 .ctl_reg = CSIPHYTIMER_CC_REG,
3128 .en_mask = BIT(9),
3129 .halt_reg = DBG_BUS_VEC_I_REG,
3130 .halt_bit = 18,
3131 },
3132 .parent = &csiphy_timer_src_clk.c,
3133 .c = {
3134 .dbg_name = "csi1phy_timer_clk",
3135 .ops = &clk_ops_branch,
3136 CLK_INIT(csi1phy_timer_clk.c),
3137 },
3138};
3139
Stephen Boyd94625ef2011-07-12 17:06:01 -07003140static struct branch_clk csi2phy_timer_clk = {
3141 .b = {
3142 .ctl_reg = CSIPHYTIMER_CC_REG,
3143 .en_mask = BIT(11),
3144 .halt_reg = DBG_BUS_VEC_I_REG,
3145 .halt_bit = 30,
3146 },
3147 .parent = &csiphy_timer_src_clk.c,
3148 .c = {
3149 .dbg_name = "csi2phy_timer_clk",
3150 .ops = &clk_ops_branch,
3151 CLK_INIT(csi2phy_timer_clk.c),
3152 },
3153};
3154
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003155#define F_DSI(d) \
3156 { \
3157 .freq_hz = d, \
3158 .ns_val = BVAL(15, 12, (d-1)), \
3159 }
3160/*
3161 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3162 * without this clock driver knowing. So, overload the clk_set_rate() to set
3163 * the divider (1 to 16) of the clock with respect to the PLL rate.
3164 */
3165static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3166 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3167 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3168 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3169 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3170 F_END
3171};
3172
3173static struct rcg_clk dsi1_byte_clk = {
3174 .b = {
3175 .ctl_reg = DSI1_BYTE_CC_REG,
3176 .en_mask = BIT(0),
3177 .reset_reg = SW_RESET_CORE_REG,
3178 .reset_mask = BIT(7),
3179 .halt_reg = DBG_BUS_VEC_B_REG,
3180 .halt_bit = 21,
3181 },
3182 .ns_reg = DSI1_BYTE_NS_REG,
3183 .root_en_mask = BIT(2),
3184 .ns_mask = BM(15, 12),
3185 .set_rate = set_rate_nop,
3186 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003187 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003188 .c = {
3189 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003190 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003191 CLK_INIT(dsi1_byte_clk.c),
3192 },
3193};
3194
3195static struct rcg_clk dsi2_byte_clk = {
3196 .b = {
3197 .ctl_reg = DSI2_BYTE_CC_REG,
3198 .en_mask = BIT(0),
3199 .reset_reg = SW_RESET_CORE_REG,
3200 .reset_mask = BIT(25),
3201 .halt_reg = DBG_BUS_VEC_B_REG,
3202 .halt_bit = 20,
3203 },
3204 .ns_reg = DSI2_BYTE_NS_REG,
3205 .root_en_mask = BIT(2),
3206 .ns_mask = BM(15, 12),
3207 .set_rate = set_rate_nop,
3208 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003209 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003210 .c = {
3211 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003212 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003213 CLK_INIT(dsi2_byte_clk.c),
3214 },
3215};
3216
3217static struct rcg_clk dsi1_esc_clk = {
3218 .b = {
3219 .ctl_reg = DSI1_ESC_CC_REG,
3220 .en_mask = BIT(0),
3221 .reset_reg = SW_RESET_CORE_REG,
3222 .halt_reg = DBG_BUS_VEC_I_REG,
3223 .halt_bit = 1,
3224 },
3225 .ns_reg = DSI1_ESC_NS_REG,
3226 .root_en_mask = BIT(2),
3227 .ns_mask = BM(15, 12),
3228 .set_rate = set_rate_nop,
3229 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003230 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003231 .c = {
3232 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003233 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003234 CLK_INIT(dsi1_esc_clk.c),
3235 },
3236};
3237
3238static struct rcg_clk dsi2_esc_clk = {
3239 .b = {
3240 .ctl_reg = DSI2_ESC_CC_REG,
3241 .en_mask = BIT(0),
3242 .halt_reg = DBG_BUS_VEC_I_REG,
3243 .halt_bit = 3,
3244 },
3245 .ns_reg = DSI2_ESC_NS_REG,
3246 .root_en_mask = BIT(2),
3247 .ns_mask = BM(15, 12),
3248 .set_rate = set_rate_nop,
3249 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003250 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003251 .c = {
3252 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003253 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003254 CLK_INIT(dsi2_esc_clk.c),
3255 },
3256};
3257
3258#define F_GFX2D(f, s, m, n, v) \
3259 { \
3260 .freq_hz = f, \
3261 .src_clk = &s##_clk.c, \
3262 .md_val = MD4(4, m, 0, n), \
3263 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3264 .ctl_val = CC_BANKED(9, 6, n), \
3265 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3266 .sys_vdd = v, \
3267 }
3268static struct clk_freq_tbl clk_tbl_gfx2d[] = {
3269 F_GFX2D( 0, gnd, 0, 0, NONE),
3270 F_GFX2D( 27000000, pxo, 0, 0, LOW),
3271 F_GFX2D( 48000000, pll8, 1, 8, LOW),
3272 F_GFX2D( 54857000, pll8, 1, 7, LOW),
3273 F_GFX2D( 64000000, pll8, 1, 6, LOW),
3274 F_GFX2D( 76800000, pll8, 1, 5, LOW),
3275 F_GFX2D( 96000000, pll8, 1, 4, LOW),
3276 F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
3277 F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
3278 F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
3279 F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
3280 F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
3281 F_GFX2D(228571000, pll2, 2, 7, HIGH),
3282 F_END
3283};
3284
3285static struct bank_masks bmnd_info_gfx2d0 = {
3286 .bank_sel_mask = BIT(11),
3287 .bank0_mask = {
3288 .md_reg = GFX2D0_MD0_REG,
3289 .ns_mask = BM(23, 20) | BM(5, 3),
3290 .rst_mask = BIT(25),
3291 .mnd_en_mask = BIT(8),
3292 .mode_mask = BM(10, 9),
3293 },
3294 .bank1_mask = {
3295 .md_reg = GFX2D0_MD1_REG,
3296 .ns_mask = BM(19, 16) | BM(2, 0),
3297 .rst_mask = BIT(24),
3298 .mnd_en_mask = BIT(5),
3299 .mode_mask = BM(7, 6),
3300 },
3301};
3302
3303static struct rcg_clk gfx2d0_clk = {
3304 .b = {
3305 .ctl_reg = GFX2D0_CC_REG,
3306 .en_mask = BIT(0),
3307 .reset_reg = SW_RESET_CORE_REG,
3308 .reset_mask = BIT(14),
3309 .halt_reg = DBG_BUS_VEC_A_REG,
3310 .halt_bit = 9,
3311 },
3312 .ns_reg = GFX2D0_NS_REG,
3313 .root_en_mask = BIT(2),
3314 .set_rate = set_rate_mnd_banked,
3315 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003316 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003317 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003318 .c = {
3319 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003320 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003321 CLK_INIT(gfx2d0_clk.c),
3322 },
3323};
3324
3325static struct bank_masks bmnd_info_gfx2d1 = {
3326 .bank_sel_mask = BIT(11),
3327 .bank0_mask = {
3328 .md_reg = GFX2D1_MD0_REG,
3329 .ns_mask = BM(23, 20) | BM(5, 3),
3330 .rst_mask = BIT(25),
3331 .mnd_en_mask = BIT(8),
3332 .mode_mask = BM(10, 9),
3333 },
3334 .bank1_mask = {
3335 .md_reg = GFX2D1_MD1_REG,
3336 .ns_mask = BM(19, 16) | BM(2, 0),
3337 .rst_mask = BIT(24),
3338 .mnd_en_mask = BIT(5),
3339 .mode_mask = BM(7, 6),
3340 },
3341};
3342
3343static struct rcg_clk gfx2d1_clk = {
3344 .b = {
3345 .ctl_reg = GFX2D1_CC_REG,
3346 .en_mask = BIT(0),
3347 .reset_reg = SW_RESET_CORE_REG,
3348 .reset_mask = BIT(13),
3349 .halt_reg = DBG_BUS_VEC_A_REG,
3350 .halt_bit = 14,
3351 },
3352 .ns_reg = GFX2D1_NS_REG,
3353 .root_en_mask = BIT(2),
3354 .set_rate = set_rate_mnd_banked,
3355 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003356 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003357 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003358 .c = {
3359 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003360 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003361 CLK_INIT(gfx2d1_clk.c),
3362 },
3363};
3364
3365#define F_GFX3D(f, s, m, n, v) \
3366 { \
3367 .freq_hz = f, \
3368 .src_clk = &s##_clk.c, \
3369 .md_val = MD4(4, m, 0, n), \
3370 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3371 .ctl_val = CC_BANKED(9, 6, n), \
3372 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3373 .sys_vdd = v, \
3374 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003375
3376static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003377 F_GFX3D( 0, gnd, 0, 0, NONE),
3378 F_GFX3D( 27000000, pxo, 0, 0, LOW),
3379 F_GFX3D( 48000000, pll8, 1, 8, LOW),
3380 F_GFX3D( 54857000, pll8, 1, 7, LOW),
3381 F_GFX3D( 64000000, pll8, 1, 6, LOW),
3382 F_GFX3D( 76800000, pll8, 1, 5, LOW),
3383 F_GFX3D( 96000000, pll8, 1, 4, LOW),
Stephen Boydd7797422011-08-10 16:01:45 -07003384 F_GFX3D(128000000, pll8, 1, 3, LOW),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003385 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
3386 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
3387 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
3388 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
3389 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
3390 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
3391 F_GFX3D(320000000, pll2, 2, 5, HIGH),
3392 F_END
3393};
3394
Tianyi Gou41515e22011-09-01 19:37:43 -07003395static struct clk_freq_tbl clk_tbl_gfx3d_8960_v2[] = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003396 F_GFX3D( 0, gnd, 0, 0, NONE),
3397 F_GFX3D( 27000000, pxo, 0, 0, LOW),
3398 F_GFX3D( 48000000, pll8, 1, 8, LOW),
3399 F_GFX3D( 54857000, pll8, 1, 7, LOW),
3400 F_GFX3D( 64000000, pll8, 1, 6, LOW),
3401 F_GFX3D( 76800000, pll8, 1, 5, LOW),
3402 F_GFX3D( 96000000, pll8, 1, 4, LOW),
3403 F_GFX3D(128000000, pll8, 1, 3, LOW),
3404 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
3405 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
3406 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
3407 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
3408 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
3409 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
3410 F_GFX3D(300000000, pll3, 1, 4, NOMINAL),
3411 F_GFX3D(320000000, pll2, 2, 5, HIGH),
3412 F_GFX3D(400000000, pll2, 1, 2, HIGH),
3413 F_END
3414};
3415
Tianyi Gou621f8742011-09-01 21:45:01 -07003416/* TODO: need to add 325MHz back once it is fixed in the simulation model */
Tianyi Gou41515e22011-09-01 19:37:43 -07003417static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
3418 F_GFX3D( 0, gnd, 0, 0, NONE),
3419 F_GFX3D( 27000000, pxo, 0, 0, LOW),
3420 F_GFX3D( 48000000, pll8, 1, 8, LOW),
3421 F_GFX3D( 54857000, pll8, 1, 7, LOW),
3422 F_GFX3D( 64000000, pll8, 1, 6, LOW),
3423 F_GFX3D( 76800000, pll8, 1, 5, LOW),
3424 F_GFX3D( 96000000, pll8, 1, 4, LOW),
3425 F_GFX3D(128000000, pll8, 1, 3, LOW),
3426 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
3427 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
3428 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
3429 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
3430 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
3431 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
Tianyi Gou41515e22011-09-01 19:37:43 -07003432 F_GFX3D(400000000, pll2, 1, 2, HIGH),
3433 F_END
3434};
3435
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003436static struct bank_masks bmnd_info_gfx3d = {
3437 .bank_sel_mask = BIT(11),
3438 .bank0_mask = {
3439 .md_reg = GFX3D_MD0_REG,
3440 .ns_mask = BM(21, 18) | BM(5, 3),
3441 .rst_mask = BIT(23),
3442 .mnd_en_mask = BIT(8),
3443 .mode_mask = BM(10, 9),
3444 },
3445 .bank1_mask = {
3446 .md_reg = GFX3D_MD1_REG,
3447 .ns_mask = BM(17, 14) | BM(2, 0),
3448 .rst_mask = BIT(22),
3449 .mnd_en_mask = BIT(5),
3450 .mode_mask = BM(7, 6),
3451 },
3452};
3453
3454static struct rcg_clk gfx3d_clk = {
3455 .b = {
3456 .ctl_reg = GFX3D_CC_REG,
3457 .en_mask = BIT(0),
3458 .reset_reg = SW_RESET_CORE_REG,
3459 .reset_mask = BIT(12),
3460 .halt_reg = DBG_BUS_VEC_A_REG,
3461 .halt_bit = 4,
3462 },
3463 .ns_reg = GFX3D_NS_REG,
3464 .root_en_mask = BIT(2),
3465 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003466 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003467 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003468 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003469 .c = {
3470 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003471 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003472 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003473 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003474 },
3475};
3476
Tianyi Gou621f8742011-09-01 21:45:01 -07003477#define F_VCAP(f, s, m, n, v) \
3478 { \
3479 .freq_hz = f, \
3480 .src_clk = &s##_clk.c, \
3481 .md_val = MD4(4, m, 0, n), \
3482 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3483 .ctl_val = CC_BANKED(9, 6, n), \
3484 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3485 .sys_vdd = v, \
3486 }
3487
3488static struct clk_freq_tbl clk_tbl_vcap[] = {
3489 F_VCAP( 0, gnd, 0, 0, NONE),
3490 F_VCAP( 27000000, pxo, 0, 0, LOW),
3491 F_VCAP( 54860000, pll8, 1, 7, LOW),
3492 F_VCAP( 64000000, pll8, 1, 6, LOW),
3493 F_VCAP( 76800000, pll8, 1, 5, LOW),
3494 F_VCAP(128000000, pll8, 1, 3, NOMINAL),
3495 F_VCAP(160000000, pll2, 1, 5, NOMINAL),
3496 F_VCAP(200000000, pll2, 1, 4, NOMINAL),
3497 F_END
3498};
3499
3500static struct bank_masks bmnd_info_vcap = {
3501 .bank_sel_mask = BIT(11),
3502 .bank0_mask = {
3503 .md_reg = VCAP_MD0_REG,
3504 .ns_mask = BM(21, 18) | BM(5, 3),
3505 .rst_mask = BIT(23),
3506 .mnd_en_mask = BIT(8),
3507 .mode_mask = BM(10, 9),
3508 },
3509 .bank1_mask = {
3510 .md_reg = VCAP_MD1_REG,
3511 .ns_mask = BM(17, 14) | BM(2, 0),
3512 .rst_mask = BIT(22),
3513 .mnd_en_mask = BIT(5),
3514 .mode_mask = BM(7, 6),
3515 },
3516};
3517
3518static struct rcg_clk vcap_clk = {
3519 .b = {
3520 .ctl_reg = VCAP_CC_REG,
3521 .en_mask = BIT(0),
3522 .halt_reg = DBG_BUS_VEC_J_REG,
3523 .halt_bit = 15,
3524 },
3525 .ns_reg = VCAP_NS_REG,
3526 .root_en_mask = BIT(2),
3527 .set_rate = set_rate_mnd_banked,
3528 .freq_tbl = clk_tbl_vcap,
3529 .bank_info = &bmnd_info_vcap,
3530 .current_freq = &rcg_dummy_freq,
3531 .c = {
3532 .dbg_name = "vcap_clk",
3533 .ops = &clk_ops_rcg_8960,
3534 .depends = &vcap_axi_clk.c,
3535 CLK_INIT(vcap_clk.c),
3536 },
3537};
3538
3539static struct branch_clk vcap_npl_clk = {
3540 .b = {
3541 .ctl_reg = VCAP_CC_REG,
3542 .en_mask = BIT(13),
3543 .halt_reg = DBG_BUS_VEC_J_REG,
3544 .halt_bit = 25,
3545 },
3546 .parent = &vcap_clk.c,
3547 .c = {
3548 .dbg_name = "vcap_npl_clk",
3549 .ops = &clk_ops_branch,
3550 CLK_INIT(vcap_npl_clk.c),
3551 },
3552};
3553
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003554#define F_IJPEG(f, s, d, m, n, v) \
3555 { \
3556 .freq_hz = f, \
3557 .src_clk = &s##_clk.c, \
3558 .md_val = MD8(8, m, 0, n), \
3559 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3560 .ctl_val = CC(6, n), \
3561 .mnd_en_mask = BIT(5) * !!(n), \
3562 .sys_vdd = v, \
3563 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003564
3565static struct clk_freq_tbl clk_tbl_ijpeg_8960[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003566 F_IJPEG( 0, gnd, 1, 0, 0, NONE),
3567 F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
3568 F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
3569 F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
3570 F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
3571 F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
3572 F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
3573 F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
3574 F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
3575 F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
Matt Wagantall393bdb52011-09-07 10:15:28 -07003576 F_IJPEG(266667000, pll2, 1, 1, 3, NOMINAL),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003577 F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003578 F_END
3579};
3580
Tianyi Gou41515e22011-09-01 19:37:43 -07003581static struct clk_freq_tbl clk_tbl_ijpeg_8064[] = {
3582 F_IJPEG( 0, gnd, 1, 0, 0, NONE),
3583 F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
3584 F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
3585 F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
3586 F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
3587 F_IJPEG(128000000, pll8, 3, 0, 0, LOW),
3588 F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
3589 F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
Tianyi Gou621f8742011-09-01 21:45:01 -07003590 F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
Tianyi Gou41515e22011-09-01 19:37:43 -07003591 F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
3592 F_END
3593};
3594
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003595static struct rcg_clk ijpeg_clk = {
3596 .b = {
3597 .ctl_reg = IJPEG_CC_REG,
3598 .en_mask = BIT(0),
3599 .reset_reg = SW_RESET_CORE_REG,
3600 .reset_mask = BIT(9),
3601 .halt_reg = DBG_BUS_VEC_A_REG,
3602 .halt_bit = 24,
3603 },
3604 .ns_reg = IJPEG_NS_REG,
3605 .md_reg = IJPEG_MD_REG,
3606 .root_en_mask = BIT(2),
3607 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
3608 .ctl_mask = BM(7, 6),
3609 .set_rate = set_rate_mnd,
Tianyi Gou41515e22011-09-01 19:37:43 -07003610 .freq_tbl = clk_tbl_ijpeg_8960,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003611 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003612 .c = {
3613 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003614 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003615 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003616 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003617 },
3618};
3619
3620#define F_JPEGD(f, s, d, v) \
3621 { \
3622 .freq_hz = f, \
3623 .src_clk = &s##_clk.c, \
3624 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
3625 .sys_vdd = v, \
3626 }
3627static struct clk_freq_tbl clk_tbl_jpegd[] = {
3628 F_JPEGD( 0, gnd, 1, NONE),
3629 F_JPEGD( 64000000, pll8, 6, LOW),
3630 F_JPEGD( 76800000, pll8, 5, LOW),
3631 F_JPEGD( 96000000, pll8, 4, LOW),
3632 F_JPEGD(160000000, pll2, 5, NOMINAL),
3633 F_JPEGD(200000000, pll2, 4, NOMINAL),
3634 F_END
3635};
3636
3637static struct rcg_clk jpegd_clk = {
3638 .b = {
3639 .ctl_reg = JPEGD_CC_REG,
3640 .en_mask = BIT(0),
3641 .reset_reg = SW_RESET_CORE_REG,
3642 .reset_mask = BIT(19),
3643 .halt_reg = DBG_BUS_VEC_A_REG,
3644 .halt_bit = 19,
3645 },
3646 .ns_reg = JPEGD_NS_REG,
3647 .root_en_mask = BIT(2),
3648 .ns_mask = (BM(15, 12) | BM(2, 0)),
3649 .set_rate = set_rate_nop,
3650 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003651 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003652 .c = {
3653 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003654 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003655 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003656 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003657 },
3658};
3659
3660#define F_MDP(f, s, m, n, v) \
3661 { \
3662 .freq_hz = f, \
3663 .src_clk = &s##_clk.c, \
3664 .md_val = MD8(8, m, 0, n), \
3665 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3666 .ctl_val = CC_BANKED(9, 6, n), \
3667 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3668 .sys_vdd = v, \
3669 }
Tianyi Gou621f8742011-09-01 21:45:01 -07003670static struct clk_freq_tbl clk_tbl_mdp_8960[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003671 F_MDP( 0, gnd, 0, 0, NONE),
3672 F_MDP( 9600000, pll8, 1, 40, LOW),
3673 F_MDP( 13710000, pll8, 1, 28, LOW),
3674 F_MDP( 27000000, pxo, 0, 0, LOW),
3675 F_MDP( 29540000, pll8, 1, 13, LOW),
3676 F_MDP( 34910000, pll8, 1, 11, LOW),
3677 F_MDP( 38400000, pll8, 1, 10, LOW),
3678 F_MDP( 59080000, pll8, 2, 13, LOW),
3679 F_MDP( 76800000, pll8, 1, 5, LOW),
3680 F_MDP( 85330000, pll8, 2, 9, LOW),
3681 F_MDP( 96000000, pll8, 1, 4, NOMINAL),
3682 F_MDP(128000000, pll8, 1, 3, NOMINAL),
3683 F_MDP(160000000, pll2, 1, 5, NOMINAL),
3684 F_MDP(177780000, pll2, 2, 9, NOMINAL),
3685 F_MDP(200000000, pll2, 1, 4, NOMINAL),
3686 F_END
3687};
3688
Tianyi Gou621f8742011-09-01 21:45:01 -07003689static struct clk_freq_tbl clk_tbl_mdp_8064[] = {
3690 F_MDP( 0, gnd, 0, 0, NONE),
3691 F_MDP( 9600000, pll8, 1, 40, LOW),
3692 F_MDP( 13710000, pll8, 1, 28, LOW),
3693 F_MDP( 29540000, pll8, 1, 13, LOW),
3694 F_MDP( 34910000, pll8, 1, 11, LOW),
3695 F_MDP( 38400000, pll8, 1, 10, LOW),
3696 F_MDP( 59080000, pll8, 2, 13, LOW),
3697 F_MDP( 76800000, pll8, 1, 5, LOW),
3698 F_MDP( 85330000, pll8, 2, 9, LOW),
3699 F_MDP( 96000000, pll8, 1, 4, LOW),
3700 F_MDP(128000000, pll8, 1, 3, LOW),
3701 F_MDP(160000000, pll2, 1, 5, NOMINAL),
3702 F_MDP(177780000, pll2, 2, 9, NOMINAL),
3703 F_MDP(200000000, pll2, 1, 4, NOMINAL),
3704 F_MDP(266000000, pll2, 1, 3, NOMINAL),
3705 F_END
3706};
3707
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003708static struct bank_masks bmnd_info_mdp = {
3709 .bank_sel_mask = BIT(11),
3710 .bank0_mask = {
3711 .md_reg = MDP_MD0_REG,
3712 .ns_mask = BM(29, 22) | BM(5, 3),
3713 .rst_mask = BIT(31),
3714 .mnd_en_mask = BIT(8),
3715 .mode_mask = BM(10, 9),
3716 },
3717 .bank1_mask = {
3718 .md_reg = MDP_MD1_REG,
3719 .ns_mask = BM(21, 14) | BM(2, 0),
3720 .rst_mask = BIT(30),
3721 .mnd_en_mask = BIT(5),
3722 .mode_mask = BM(7, 6),
3723 },
3724};
3725
3726static struct rcg_clk mdp_clk = {
3727 .b = {
3728 .ctl_reg = MDP_CC_REG,
3729 .en_mask = BIT(0),
3730 .reset_reg = SW_RESET_CORE_REG,
3731 .reset_mask = BIT(21),
3732 .halt_reg = DBG_BUS_VEC_C_REG,
3733 .halt_bit = 10,
3734 },
3735 .ns_reg = MDP_NS_REG,
3736 .root_en_mask = BIT(2),
3737 .set_rate = set_rate_mnd_banked,
Tianyi Gou621f8742011-09-01 21:45:01 -07003738 .freq_tbl = clk_tbl_mdp_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003739 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003740 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003741 .c = {
3742 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003743 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003744 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003745 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003746 },
3747};
3748
3749static struct branch_clk lut_mdp_clk = {
3750 .b = {
3751 .ctl_reg = MDP_LUT_CC_REG,
3752 .en_mask = BIT(0),
3753 .halt_reg = DBG_BUS_VEC_I_REG,
3754 .halt_bit = 13,
3755 },
3756 .parent = &mdp_clk.c,
3757 .c = {
3758 .dbg_name = "lut_mdp_clk",
3759 .ops = &clk_ops_branch,
3760 CLK_INIT(lut_mdp_clk.c),
3761 },
3762};
3763
3764#define F_MDP_VSYNC(f, s, v) \
3765 { \
3766 .freq_hz = f, \
3767 .src_clk = &s##_clk.c, \
3768 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
3769 .sys_vdd = v, \
3770 }
3771static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
3772 F_MDP_VSYNC(27000000, pxo, LOW),
3773 F_END
3774};
3775
3776static struct rcg_clk mdp_vsync_clk = {
3777 .b = {
3778 .ctl_reg = MISC_CC_REG,
3779 .en_mask = BIT(6),
3780 .reset_reg = SW_RESET_CORE_REG,
3781 .reset_mask = BIT(3),
3782 .halt_reg = DBG_BUS_VEC_B_REG,
3783 .halt_bit = 22,
3784 },
3785 .ns_reg = MISC_CC2_REG,
3786 .ns_mask = BIT(13),
3787 .set_rate = set_rate_nop,
3788 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003789 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003790 .c = {
3791 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003792 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003793 CLK_INIT(mdp_vsync_clk.c),
3794 },
3795};
3796
3797#define F_ROT(f, s, d, v) \
3798 { \
3799 .freq_hz = f, \
3800 .src_clk = &s##_clk.c, \
3801 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3802 21, 19, 18, 16, s##_to_mm_mux), \
3803 .sys_vdd = v, \
3804 }
3805static struct clk_freq_tbl clk_tbl_rot[] = {
3806 F_ROT( 0, gnd, 1, NONE),
3807 F_ROT( 27000000, pxo, 1, LOW),
3808 F_ROT( 29540000, pll8, 13, LOW),
3809 F_ROT( 32000000, pll8, 12, LOW),
3810 F_ROT( 38400000, pll8, 10, LOW),
3811 F_ROT( 48000000, pll8, 8, LOW),
3812 F_ROT( 54860000, pll8, 7, LOW),
3813 F_ROT( 64000000, pll8, 6, LOW),
3814 F_ROT( 76800000, pll8, 5, LOW),
Matt Wagantall448db0f2011-09-07 10:17:40 -07003815 F_ROT( 96000000, pll8, 4, LOW),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003816 F_ROT(100000000, pll2, 8, NOMINAL),
3817 F_ROT(114290000, pll2, 7, NOMINAL),
3818 F_ROT(133330000, pll2, 6, NOMINAL),
3819 F_ROT(160000000, pll2, 5, NOMINAL),
Stephen Boyd8487f712011-08-29 12:10:09 -07003820 F_ROT(200000000, pll2, 4, NOMINAL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003821 F_END
3822};
3823
3824static struct bank_masks bdiv_info_rot = {
3825 .bank_sel_mask = BIT(30),
3826 .bank0_mask = {
3827 .ns_mask = BM(25, 22) | BM(18, 16),
3828 },
3829 .bank1_mask = {
3830 .ns_mask = BM(29, 26) | BM(21, 19),
3831 },
3832};
3833
3834static struct rcg_clk rot_clk = {
3835 .b = {
3836 .ctl_reg = ROT_CC_REG,
3837 .en_mask = BIT(0),
3838 .reset_reg = SW_RESET_CORE_REG,
3839 .reset_mask = BIT(2),
3840 .halt_reg = DBG_BUS_VEC_C_REG,
3841 .halt_bit = 15,
3842 },
3843 .ns_reg = ROT_NS_REG,
3844 .root_en_mask = BIT(2),
3845 .set_rate = set_rate_div_banked,
3846 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003847 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003848 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003849 .c = {
3850 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003851 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003852 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003853 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003854 },
3855};
3856
3857static int hdmi_pll_clk_enable(struct clk *clk)
3858{
3859 int ret;
3860 unsigned long flags;
3861 spin_lock_irqsave(&local_clock_reg_lock, flags);
3862 ret = hdmi_pll_enable();
3863 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3864 return ret;
3865}
3866
3867static void hdmi_pll_clk_disable(struct clk *clk)
3868{
3869 unsigned long flags;
3870 spin_lock_irqsave(&local_clock_reg_lock, flags);
3871 hdmi_pll_disable();
3872 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3873}
3874
3875static unsigned hdmi_pll_clk_get_rate(struct clk *clk)
3876{
3877 return hdmi_pll_get_rate();
3878}
3879
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003880static struct clk *hdmi_pll_clk_get_parent(struct clk *clk)
3881{
3882 return &pxo_clk.c;
3883}
3884
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003885static struct clk_ops clk_ops_hdmi_pll = {
3886 .enable = hdmi_pll_clk_enable,
3887 .disable = hdmi_pll_clk_disable,
3888 .get_rate = hdmi_pll_clk_get_rate,
3889 .is_local = local_clk_is_local,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003890 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003891};
3892
3893static struct clk hdmi_pll_clk = {
3894 .dbg_name = "hdmi_pll_clk",
3895 .ops = &clk_ops_hdmi_pll,
3896 CLK_INIT(hdmi_pll_clk),
3897};
3898
3899#define F_TV_GND(f, s, p_r, d, m, n, v) \
3900 { \
3901 .freq_hz = f, \
3902 .src_clk = &s##_clk.c, \
3903 .md_val = MD8(8, m, 0, n), \
3904 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3905 .ctl_val = CC(6, n), \
3906 .mnd_en_mask = BIT(5) * !!(n), \
3907 .sys_vdd = v, \
3908 }
3909#define F_TV(f, s, p_r, d, m, n, v) \
3910 { \
3911 .freq_hz = f, \
3912 .src_clk = &s##_clk, \
3913 .md_val = MD8(8, m, 0, n), \
3914 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3915 .ctl_val = CC(6, n), \
3916 .mnd_en_mask = BIT(5) * !!(n), \
3917 .sys_vdd = v, \
3918 .extra_freq_data = (void *)p_r, \
3919 }
3920/* Switching TV freqs requires PLL reconfiguration. */
3921static struct clk_freq_tbl clk_tbl_tv[] = {
3922 F_TV_GND( 0, gnd, 0, 1, 0, 0, NONE),
3923 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0, LOW),
3924 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0, LOW),
3925 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0, LOW),
3926 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0, NOMINAL),
3927 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0, NOMINAL),
3928 F_END
3929};
3930
3931/*
3932 * Unlike other clocks, the TV rate is adjusted through PLL
3933 * re-programming. It is also routed through an MND divider.
3934 */
3935void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3936{
3937 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3938 if (pll_rate)
3939 hdmi_pll_set_rate(pll_rate);
3940 set_rate_mnd(clk, nf);
3941}
3942
3943static struct rcg_clk tv_src_clk = {
3944 .ns_reg = TV_NS_REG,
3945 .b = {
3946 .ctl_reg = TV_CC_REG,
3947 .halt_check = NOCHECK,
3948 },
3949 .md_reg = TV_MD_REG,
3950 .root_en_mask = BIT(2),
3951 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
3952 .ctl_mask = BM(7, 6),
3953 .set_rate = set_rate_tv,
3954 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003955 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003956 .c = {
3957 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003958 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003959 CLK_INIT(tv_src_clk.c),
3960 },
3961};
3962
3963static struct branch_clk tv_enc_clk = {
3964 .b = {
3965 .ctl_reg = TV_CC_REG,
3966 .en_mask = BIT(8),
3967 .reset_reg = SW_RESET_CORE_REG,
3968 .reset_mask = BIT(0),
3969 .halt_reg = DBG_BUS_VEC_D_REG,
3970 .halt_bit = 9,
3971 },
3972 .parent = &tv_src_clk.c,
3973 .c = {
3974 .dbg_name = "tv_enc_clk",
3975 .ops = &clk_ops_branch,
3976 CLK_INIT(tv_enc_clk.c),
3977 },
3978};
3979
3980static struct branch_clk tv_dac_clk = {
3981 .b = {
3982 .ctl_reg = TV_CC_REG,
3983 .en_mask = BIT(10),
3984 .halt_reg = DBG_BUS_VEC_D_REG,
3985 .halt_bit = 10,
3986 },
3987 .parent = &tv_src_clk.c,
3988 .c = {
3989 .dbg_name = "tv_dac_clk",
3990 .ops = &clk_ops_branch,
3991 CLK_INIT(tv_dac_clk.c),
3992 },
3993};
3994
3995static struct branch_clk mdp_tv_clk = {
3996 .b = {
3997 .ctl_reg = TV_CC_REG,
3998 .en_mask = BIT(0),
3999 .reset_reg = SW_RESET_CORE_REG,
4000 .reset_mask = BIT(4),
4001 .halt_reg = DBG_BUS_VEC_D_REG,
4002 .halt_bit = 12,
4003 },
4004 .parent = &tv_src_clk.c,
4005 .c = {
4006 .dbg_name = "mdp_tv_clk",
4007 .ops = &clk_ops_branch,
4008 CLK_INIT(mdp_tv_clk.c),
4009 },
4010};
4011
4012static struct branch_clk hdmi_tv_clk = {
4013 .b = {
4014 .ctl_reg = TV_CC_REG,
4015 .en_mask = BIT(12),
4016 .reset_reg = SW_RESET_CORE_REG,
4017 .reset_mask = BIT(1),
4018 .halt_reg = DBG_BUS_VEC_D_REG,
4019 .halt_bit = 11,
4020 },
4021 .parent = &tv_src_clk.c,
4022 .c = {
4023 .dbg_name = "hdmi_tv_clk",
4024 .ops = &clk_ops_branch,
4025 CLK_INIT(hdmi_tv_clk.c),
4026 },
4027};
4028
4029static struct branch_clk hdmi_app_clk = {
4030 .b = {
4031 .ctl_reg = MISC_CC2_REG,
4032 .en_mask = BIT(11),
4033 .reset_reg = SW_RESET_CORE_REG,
4034 .reset_mask = BIT(11),
4035 .halt_reg = DBG_BUS_VEC_B_REG,
4036 .halt_bit = 25,
4037 },
4038 .c = {
4039 .dbg_name = "hdmi_app_clk",
4040 .ops = &clk_ops_branch,
4041 CLK_INIT(hdmi_app_clk.c),
4042 },
4043};
4044
4045static struct bank_masks bmnd_info_vcodec = {
4046 .bank_sel_mask = BIT(13),
4047 .bank0_mask = {
4048 .md_reg = VCODEC_MD0_REG,
4049 .ns_mask = BM(18, 11) | BM(2, 0),
4050 .rst_mask = BIT(31),
4051 .mnd_en_mask = BIT(5),
4052 .mode_mask = BM(7, 6),
4053 },
4054 .bank1_mask = {
4055 .md_reg = VCODEC_MD1_REG,
4056 .ns_mask = BM(26, 19) | BM(29, 27),
4057 .rst_mask = BIT(30),
4058 .mnd_en_mask = BIT(10),
4059 .mode_mask = BM(12, 11),
4060 },
4061};
4062#define F_VCODEC(f, s, m, n, v) \
4063 { \
4064 .freq_hz = f, \
4065 .src_clk = &s##_clk.c, \
4066 .md_val = MD8(8, m, 0, n), \
4067 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
4068 .ctl_val = CC_BANKED(6, 11, n), \
4069 .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
4070 .sys_vdd = v, \
4071 }
4072static struct clk_freq_tbl clk_tbl_vcodec[] = {
4073 F_VCODEC( 0, gnd, 0, 0, NONE),
4074 F_VCODEC( 27000000, pxo, 0, 0, LOW),
4075 F_VCODEC( 32000000, pll8, 1, 12, LOW),
4076 F_VCODEC( 48000000, pll8, 1, 8, LOW),
4077 F_VCODEC( 54860000, pll8, 1, 7, LOW),
4078 F_VCODEC( 96000000, pll8, 1, 4, LOW),
4079 F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
4080 F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
4081 F_VCODEC(228570000, pll2, 2, 7, HIGH),
4082 F_END
4083};
4084
4085static struct rcg_clk vcodec_clk = {
4086 .b = {
4087 .ctl_reg = VCODEC_CC_REG,
4088 .en_mask = BIT(0),
4089 .reset_reg = SW_RESET_CORE_REG,
4090 .reset_mask = BIT(6),
4091 .halt_reg = DBG_BUS_VEC_C_REG,
4092 .halt_bit = 29,
4093 },
4094 .ns_reg = VCODEC_NS_REG,
4095 .root_en_mask = BIT(2),
4096 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004097 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004098 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004099 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004100 .c = {
4101 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004102 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004103 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004104 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004105 },
4106};
4107
4108#define F_VPE(f, s, d, v) \
4109 { \
4110 .freq_hz = f, \
4111 .src_clk = &s##_clk.c, \
4112 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
4113 .sys_vdd = v, \
4114 }
4115static struct clk_freq_tbl clk_tbl_vpe[] = {
4116 F_VPE( 0, gnd, 1, NONE),
4117 F_VPE( 27000000, pxo, 1, LOW),
4118 F_VPE( 34909000, pll8, 11, LOW),
4119 F_VPE( 38400000, pll8, 10, LOW),
4120 F_VPE( 64000000, pll8, 6, LOW),
4121 F_VPE( 76800000, pll8, 5, LOW),
4122 F_VPE( 96000000, pll8, 4, NOMINAL),
4123 F_VPE(100000000, pll2, 8, NOMINAL),
4124 F_VPE(160000000, pll2, 5, NOMINAL),
4125 F_END
4126};
4127
4128static struct rcg_clk vpe_clk = {
4129 .b = {
4130 .ctl_reg = VPE_CC_REG,
4131 .en_mask = BIT(0),
4132 .reset_reg = SW_RESET_CORE_REG,
4133 .reset_mask = BIT(17),
4134 .halt_reg = DBG_BUS_VEC_A_REG,
4135 .halt_bit = 28,
4136 },
4137 .ns_reg = VPE_NS_REG,
4138 .root_en_mask = BIT(2),
4139 .ns_mask = (BM(15, 12) | BM(2, 0)),
4140 .set_rate = set_rate_nop,
4141 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004142 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004143 .c = {
4144 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004145 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004146 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004147 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004148 },
4149};
4150
4151#define F_VFE(f, s, d, m, n, v) \
4152 { \
4153 .freq_hz = f, \
4154 .src_clk = &s##_clk.c, \
4155 .md_val = MD8(8, m, 0, n), \
4156 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4157 .ctl_val = CC(6, n), \
4158 .mnd_en_mask = BIT(5) * !!(n), \
4159 .sys_vdd = v, \
4160 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004161
4162static struct clk_freq_tbl clk_tbl_vfe_8960[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004163 F_VFE( 0, gnd, 1, 0, 0, NONE),
4164 F_VFE( 13960000, pll8, 1, 2, 55, LOW),
4165 F_VFE( 27000000, pxo, 1, 0, 0, LOW),
4166 F_VFE( 36570000, pll8, 1, 2, 21, LOW),
4167 F_VFE( 38400000, pll8, 2, 1, 5, LOW),
4168 F_VFE( 45180000, pll8, 1, 2, 17, LOW),
4169 F_VFE( 48000000, pll8, 2, 1, 4, LOW),
4170 F_VFE( 54860000, pll8, 1, 1, 7, LOW),
4171 F_VFE( 64000000, pll8, 2, 1, 3, LOW),
4172 F_VFE( 76800000, pll8, 1, 1, 5, LOW),
4173 F_VFE( 96000000, pll8, 2, 1, 2, LOW),
4174 F_VFE(109710000, pll8, 1, 2, 7, LOW),
4175 F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
4176 F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
4177 F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
4178 F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
4179 F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
Stephen Boyd94625ef2011-07-12 17:06:01 -07004180 F_VFE(320000000, pll2, 1, 2, 5, HIGH),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004181 F_END
4182};
4183
Tianyi Gou41515e22011-09-01 19:37:43 -07004184static struct clk_freq_tbl clk_tbl_vfe_8064[] = {
4185 F_VFE( 0, gnd, 1, 0, 0, NONE),
4186 F_VFE( 13960000, pll8, 1, 2, 55, LOW),
4187 F_VFE( 36570000, pll8, 1, 2, 21, LOW),
4188 F_VFE( 38400000, pll8, 2, 1, 5, LOW),
4189 F_VFE( 45180000, pll8, 1, 2, 17, LOW),
4190 F_VFE( 48000000, pll8, 2, 1, 4, LOW),
4191 F_VFE( 54860000, pll8, 1, 1, 7, LOW),
4192 F_VFE( 64000000, pll8, 2, 1, 3, LOW),
4193 F_VFE( 76800000, pll8, 1, 1, 5, LOW),
4194 F_VFE( 96000000, pll8, 2, 1, 2, LOW),
4195 F_VFE(109710000, pll8, 1, 2, 7, LOW),
4196 F_VFE(128000000, pll8, 1, 1, 3, LOW),
4197 F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
4198 F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
4199 F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
4200 F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
4201 F_VFE(320000000, pll2, 1, 2, 5, HIGH),
4202 F_END
4203};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004204
4205static struct rcg_clk vfe_clk = {
4206 .b = {
4207 .ctl_reg = VFE_CC_REG,
4208 .reset_reg = SW_RESET_CORE_REG,
4209 .reset_mask = BIT(15),
4210 .halt_reg = DBG_BUS_VEC_B_REG,
4211 .halt_bit = 6,
4212 .en_mask = BIT(0),
4213 },
4214 .ns_reg = VFE_NS_REG,
4215 .md_reg = VFE_MD_REG,
4216 .root_en_mask = BIT(2),
4217 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
4218 .ctl_mask = BM(7, 6),
4219 .set_rate = set_rate_mnd,
Tianyi Gou41515e22011-09-01 19:37:43 -07004220 .freq_tbl = clk_tbl_vfe_8960,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004221 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004222 .c = {
4223 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004224 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004225 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004226 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004227 },
4228};
4229
Matt Wagantallc23eee92011-08-16 23:06:52 -07004230static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004231 .b = {
4232 .ctl_reg = VFE_CC_REG,
4233 .en_mask = BIT(12),
4234 .reset_reg = SW_RESET_CORE_REG,
4235 .reset_mask = BIT(24),
4236 .halt_reg = DBG_BUS_VEC_B_REG,
4237 .halt_bit = 8,
4238 },
4239 .parent = &vfe_clk.c,
4240 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004241 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004242 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004243 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004244 },
4245};
4246
4247/*
4248 * Low Power Audio Clocks
4249 */
4250#define F_AIF_OSR(f, s, d, m, n, v) \
4251 { \
4252 .freq_hz = f, \
4253 .src_clk = &s##_clk.c, \
4254 .md_val = MD8(8, m, 0, n), \
4255 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4256 .mnd_en_mask = BIT(8) * !!(n), \
4257 .sys_vdd = v, \
4258 }
4259static struct clk_freq_tbl clk_tbl_aif_osr[] = {
4260 F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
Vikram Mulukutla6abb4fc2011-08-23 11:08:00 -07004261 F_AIF_OSR( 512000, pll4, 4, 1, 192, LOW),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004262 F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
4263 F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
4264 F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
4265 F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
4266 F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
4267 F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
4268 F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
4269 F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
4270 F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
4271 F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
4272 F_END
4273};
4274
4275#define CLK_AIF_OSR(i, ns, md, h_r) \
4276 struct rcg_clk i##_clk = { \
4277 .b = { \
4278 .ctl_reg = ns, \
4279 .en_mask = BIT(17), \
4280 .reset_reg = ns, \
4281 .reset_mask = BIT(19), \
4282 .halt_reg = h_r, \
4283 .halt_check = ENABLE, \
4284 .halt_bit = 1, \
4285 }, \
4286 .ns_reg = ns, \
4287 .md_reg = md, \
4288 .root_en_mask = BIT(9), \
4289 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4290 .set_rate = set_rate_mnd, \
4291 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004292 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004293 .c = { \
4294 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004295 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004296 CLK_INIT(i##_clk.c), \
4297 }, \
4298 }
4299#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4300 struct rcg_clk i##_clk = { \
4301 .b = { \
4302 .ctl_reg = ns, \
4303 .en_mask = BIT(21), \
4304 .reset_reg = ns, \
4305 .reset_mask = BIT(23), \
4306 .halt_reg = h_r, \
4307 .halt_check = ENABLE, \
4308 .halt_bit = 1, \
4309 }, \
4310 .ns_reg = ns, \
4311 .md_reg = md, \
4312 .root_en_mask = BIT(9), \
4313 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4314 .set_rate = set_rate_mnd, \
4315 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004316 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004317 .c = { \
4318 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004319 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004320 CLK_INIT(i##_clk.c), \
4321 }, \
4322 }
4323
4324#define F_AIF_BIT(d, s) \
4325 { \
4326 .freq_hz = d, \
4327 .ns_val = (BVAL(14, 14, s) | BVAL(13, 10, (d-1))) \
4328 }
4329static struct clk_freq_tbl clk_tbl_aif_bit[] = {
4330 F_AIF_BIT(0, 1), /* Use external clock. */
4331 F_AIF_BIT(1, 0), F_AIF_BIT(2, 0), F_AIF_BIT(3, 0), F_AIF_BIT(4, 0),
4332 F_AIF_BIT(5, 0), F_AIF_BIT(6, 0), F_AIF_BIT(7, 0), F_AIF_BIT(8, 0),
4333 F_AIF_BIT(9, 0), F_AIF_BIT(10, 0), F_AIF_BIT(11, 0), F_AIF_BIT(12, 0),
4334 F_AIF_BIT(13, 0), F_AIF_BIT(14, 0), F_AIF_BIT(15, 0), F_AIF_BIT(16, 0),
4335 F_END
4336};
4337
4338#define CLK_AIF_BIT(i, ns, h_r) \
4339 struct rcg_clk i##_clk = { \
4340 .b = { \
4341 .ctl_reg = ns, \
4342 .en_mask = BIT(15), \
4343 .halt_reg = h_r, \
4344 .halt_check = DELAY, \
4345 }, \
4346 .ns_reg = ns, \
4347 .ns_mask = BM(14, 10), \
4348 .set_rate = set_rate_nop, \
4349 .freq_tbl = clk_tbl_aif_bit, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004350 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004351 .c = { \
4352 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004353 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004354 CLK_INIT(i##_clk.c), \
4355 }, \
4356 }
4357
4358#define F_AIF_BIT_D(d, s) \
4359 { \
4360 .freq_hz = d, \
4361 .ns_val = (BVAL(18, 18, s) | BVAL(17, 10, (d-1))) \
4362 }
4363static struct clk_freq_tbl clk_tbl_aif_bit_div[] = {
4364 F_AIF_BIT_D(0, 1), /* Use external clock. */
4365 F_AIF_BIT_D(1, 0), F_AIF_BIT_D(2, 0), F_AIF_BIT_D(3, 0),
4366 F_AIF_BIT_D(4, 0), F_AIF_BIT_D(5, 0), F_AIF_BIT_D(6, 0),
4367 F_AIF_BIT_D(7, 0), F_AIF_BIT_D(8, 0), F_AIF_BIT_D(9, 0),
4368 F_AIF_BIT_D(10, 0), F_AIF_BIT_D(11, 0), F_AIF_BIT_D(12, 0),
4369 F_AIF_BIT_D(13, 0), F_AIF_BIT_D(14, 0), F_AIF_BIT_D(15, 0),
4370 F_AIF_BIT_D(16, 0),
4371 F_END
4372};
4373
4374#define CLK_AIF_BIT_DIV(i, ns, h_r) \
4375 struct rcg_clk i##_clk = { \
4376 .b = { \
4377 .ctl_reg = ns, \
4378 .en_mask = BIT(19), \
4379 .halt_reg = h_r, \
4380 .halt_check = ENABLE, \
4381 }, \
4382 .ns_reg = ns, \
4383 .ns_mask = BM(18, 10), \
4384 .set_rate = set_rate_nop, \
4385 .freq_tbl = clk_tbl_aif_bit_div, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004386 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004387 .c = { \
4388 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004389 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004390 CLK_INIT(i##_clk.c), \
4391 }, \
4392 }
4393
4394static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4395 LCC_MI2S_STATUS_REG);
4396static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4397
4398static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4399 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4400static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4401 LCC_CODEC_I2S_MIC_STATUS_REG);
4402
4403static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4404 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4405static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4406 LCC_SPARE_I2S_MIC_STATUS_REG);
4407
4408static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4409 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4410static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4411 LCC_CODEC_I2S_SPKR_STATUS_REG);
4412
4413static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4414 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4415static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4416 LCC_SPARE_I2S_SPKR_STATUS_REG);
4417
4418#define F_PCM(f, s, d, m, n, v) \
4419 { \
4420 .freq_hz = f, \
4421 .src_clk = &s##_clk.c, \
4422 .md_val = MD16(m, n), \
4423 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4424 .mnd_en_mask = BIT(8) * !!(n), \
4425 .sys_vdd = v, \
4426 }
4427static struct clk_freq_tbl clk_tbl_pcm[] = {
4428 F_PCM( 0, gnd, 1, 0, 0, NONE),
4429 F_PCM( 512000, pll4, 4, 1, 192, LOW),
4430 F_PCM( 768000, pll4, 4, 1, 128, LOW),
4431 F_PCM( 1024000, pll4, 4, 1, 96, LOW),
4432 F_PCM( 1536000, pll4, 4, 1, 64, LOW),
4433 F_PCM( 2048000, pll4, 4, 1, 48, LOW),
4434 F_PCM( 3072000, pll4, 4, 1, 32, LOW),
4435 F_PCM( 4096000, pll4, 4, 1, 24, LOW),
4436 F_PCM( 6144000, pll4, 4, 1, 16, LOW),
4437 F_PCM( 8192000, pll4, 4, 1, 12, LOW),
4438 F_PCM(12288000, pll4, 4, 1, 8, LOW),
4439 F_PCM(24576000, pll4, 4, 1, 4, LOW),
4440 F_END
4441};
4442
4443static struct rcg_clk pcm_clk = {
4444 .b = {
4445 .ctl_reg = LCC_PCM_NS_REG,
4446 .en_mask = BIT(11),
4447 .reset_reg = LCC_PCM_NS_REG,
4448 .reset_mask = BIT(13),
4449 .halt_reg = LCC_PCM_STATUS_REG,
4450 .halt_check = ENABLE,
4451 .halt_bit = 0,
4452 },
4453 .ns_reg = LCC_PCM_NS_REG,
4454 .md_reg = LCC_PCM_MD_REG,
4455 .root_en_mask = BIT(9),
4456 .ns_mask = (BM(31, 16) | BM(6, 0)),
4457 .set_rate = set_rate_mnd,
4458 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004459 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004460 .c = {
4461 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004462 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004463 CLK_INIT(pcm_clk.c),
4464 },
4465};
4466
4467static struct rcg_clk audio_slimbus_clk = {
4468 .b = {
4469 .ctl_reg = LCC_SLIMBUS_NS_REG,
4470 .en_mask = BIT(10),
4471 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4472 .reset_mask = BIT(5),
4473 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4474 .halt_check = ENABLE,
4475 .halt_bit = 0,
4476 },
4477 .ns_reg = LCC_SLIMBUS_NS_REG,
4478 .md_reg = LCC_SLIMBUS_MD_REG,
4479 .root_en_mask = BIT(9),
4480 .ns_mask = (BM(31, 24) | BM(6, 0)),
4481 .set_rate = set_rate_mnd,
4482 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004483 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004484 .c = {
4485 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004486 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004487 CLK_INIT(audio_slimbus_clk.c),
4488 },
4489};
4490
4491static struct branch_clk sps_slimbus_clk = {
4492 .b = {
4493 .ctl_reg = LCC_SLIMBUS_NS_REG,
4494 .en_mask = BIT(12),
4495 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4496 .halt_check = ENABLE,
4497 .halt_bit = 1,
4498 },
4499 .parent = &audio_slimbus_clk.c,
4500 .c = {
4501 .dbg_name = "sps_slimbus_clk",
4502 .ops = &clk_ops_branch,
4503 CLK_INIT(sps_slimbus_clk.c),
4504 },
4505};
4506
4507static struct branch_clk slimbus_xo_src_clk = {
4508 .b = {
4509 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4510 .en_mask = BIT(2),
4511 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004512 .halt_bit = 28,
4513 },
4514 .parent = &sps_slimbus_clk.c,
4515 .c = {
4516 .dbg_name = "slimbus_xo_src_clk",
4517 .ops = &clk_ops_branch,
4518 CLK_INIT(slimbus_xo_src_clk.c),
4519 },
4520};
4521
Matt Wagantall735f01a2011-08-12 12:40:28 -07004522DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4523DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4524DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4525DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4526DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4527DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4528DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4529DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004530
4531static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4532static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
4533static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4534static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4535static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4536static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4537static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4538static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
4539
4540static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
4541/*
4542 * TODO: replace dummy_clk below with ebi1_clk.c once the
4543 * bus driver starts voting on ebi1 rates.
4544 */
4545static DEFINE_CLK_VOTER(ebi1_adm_clk, &dummy_clk);
4546
4547#ifdef CONFIG_DEBUG_FS
4548struct measure_sel {
4549 u32 test_vector;
4550 struct clk *clk;
4551};
4552
Matt Wagantall8b38f942011-08-02 18:23:18 -07004553static DEFINE_CLK_MEASURE(l2_m_clk);
4554static DEFINE_CLK_MEASURE(krait0_m_clk);
4555static DEFINE_CLK_MEASURE(krait1_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004556static DEFINE_CLK_MEASURE(q6sw_clk);
4557static DEFINE_CLK_MEASURE(q6fw_clk);
4558static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004559
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004560static struct measure_sel measure_mux[] = {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004561 { TEST_PER_LS(0x05), &qdss_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004562 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4563 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4564 { TEST_PER_LS(0x13), &sdc1_clk.c },
4565 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4566 { TEST_PER_LS(0x15), &sdc2_clk.c },
4567 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4568 { TEST_PER_LS(0x17), &sdc3_clk.c },
4569 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4570 { TEST_PER_LS(0x19), &sdc4_clk.c },
4571 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4572 { TEST_PER_LS(0x1B), &sdc5_clk.c },
4573 { TEST_PER_LS(0x25), &dfab_clk.c },
4574 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4575 { TEST_PER_LS(0x26), &pmem_clk.c },
4576 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4577 { TEST_PER_LS(0x33), &cfpb_clk.c },
4578 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4579 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4580 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4581 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4582 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4583 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4584 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4585 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4586 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4587 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4588 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4589 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4590 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4591 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4592 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4593 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4594 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4595 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4596 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4597 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4598 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4599 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4600 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4601 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4602 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4603 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4604 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4605 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4606 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4607 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4608 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4609 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4610 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4611 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4612 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4613 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4614 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004615 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4616 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4617 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4618 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4619 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4620 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4621 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4622 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4623 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004624 { TEST_PER_LS(0x78), &sfpb_clk.c },
4625 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4626 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4627 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4628 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4629 { TEST_PER_LS(0x7D), &prng_clk.c },
4630 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4631 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4632 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4633 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004634 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4635 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4636 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004637 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4638 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4639 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4640 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4641 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4642 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4643 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4644 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4645 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4646 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004647 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004648 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4649
4650 { TEST_PER_HS(0x07), &afab_clk.c },
4651 { TEST_PER_HS(0x07), &afab_a_clk.c },
4652 { TEST_PER_HS(0x18), &sfab_clk.c },
4653 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004654 { TEST_PER_HS(0x26), &q6sw_clk },
4655 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004656 { TEST_PER_HS(0x2A), &adm0_clk.c },
4657 { TEST_PER_HS(0x34), &ebi1_clk.c },
4658 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004659 { TEST_PER_HS(0x48), &qdss_at_clk.c },
4660 { TEST_PER_HS(0x49), &qdss_pclkdbg_clk.c },
4661 { TEST_PER_HS(0x4A), &qdss_traceclkin_clk.c },
4662 { TEST_PER_HS(0x4B), &qdss_tsctr_clk.c },
4663 { TEST_PER_HS(0x4F), &qdss_stm_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004664 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004665
4666 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4667 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4668 { TEST_MM_LS(0x02), &cam1_clk.c },
4669 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004670 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004671 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4672 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4673 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4674 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4675 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4676 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4677 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4678 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4679 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4680 { TEST_MM_LS(0x12), &imem_p_clk.c },
4681 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4682 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4683 { TEST_MM_LS(0x16), &rot_p_clk.c },
4684 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4685 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4686 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4687 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4688 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4689 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4690 { TEST_MM_LS(0x1D), &cam0_clk.c },
4691 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4692 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4693 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4694 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4695 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4696 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4697 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4698 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004699 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004700 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004701
4702 { TEST_MM_HS(0x00), &csi0_clk.c },
4703 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004704 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004705 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4706 { TEST_MM_HS(0x06), &vfe_clk.c },
4707 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4708 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4709 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4710 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4711 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4712 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4713 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4714 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4715 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4716 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4717 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4718 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4719 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4720 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4721 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4722 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4723 { TEST_MM_HS(0x1A), &mdp_clk.c },
4724 { TEST_MM_HS(0x1B), &rot_clk.c },
4725 { TEST_MM_HS(0x1C), &vpe_clk.c },
4726 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4727 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4728 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4729 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4730 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4731 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4732 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4733 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4734 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4735 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4736 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004737 { TEST_MM_HS(0x2D), &csi2_clk.c },
4738 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4739 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4740 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4741 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4742 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004743 { TEST_MM_HS(0x33), &vcap_clk.c },
4744 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004745 { TEST_MM_HS(0x36), &vcap_axi_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004746 { TEST_MM_HS(0x39), &gfx3d_axi_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004747
4748 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4749 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4750 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4751 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4752 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4753 { TEST_LPA(0x14), &pcm_clk.c },
4754 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004755
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004756 { TEST_LPA_HS(0x00), &q6_func_clk },
4757
Matt Wagantall8b38f942011-08-02 18:23:18 -07004758 { TEST_CPUL2(0x1), &l2_m_clk },
4759 { TEST_CPUL2(0x2), &krait0_m_clk },
4760 { TEST_CPUL2(0x3), &krait1_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004761};
4762
4763static struct measure_sel *find_measure_sel(struct clk *clk)
4764{
4765 int i;
4766
4767 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4768 if (measure_mux[i].clk == clk)
4769 return &measure_mux[i];
4770 return NULL;
4771}
4772
Matt Wagantall8b38f942011-08-02 18:23:18 -07004773static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004774{
4775 int ret = 0;
4776 u32 clk_sel;
4777 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004778 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004779 unsigned long flags;
4780
4781 if (!parent)
4782 return -EINVAL;
4783
4784 p = find_measure_sel(parent);
4785 if (!p)
4786 return -EINVAL;
4787
4788 spin_lock_irqsave(&local_clock_reg_lock, flags);
4789
Matt Wagantall8b38f942011-08-02 18:23:18 -07004790 /*
4791 * Program the test vector, measurement period (sample_ticks)
4792 * and scaling multiplier.
4793 */
4794 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004795 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004796 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004797 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4798 case TEST_TYPE_PER_LS:
4799 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4800 break;
4801 case TEST_TYPE_PER_HS:
4802 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4803 break;
4804 case TEST_TYPE_MM_LS:
4805 writel_relaxed(0x4030D97, CLK_TEST_REG);
4806 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4807 break;
4808 case TEST_TYPE_MM_HS:
4809 writel_relaxed(0x402B800, CLK_TEST_REG);
4810 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4811 break;
4812 case TEST_TYPE_LPA:
4813 writel_relaxed(0x4030D98, CLK_TEST_REG);
4814 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4815 LCC_CLK_LS_DEBUG_CFG_REG);
4816 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004817 case TEST_TYPE_LPA_HS:
4818 writel_relaxed(0x402BC00, CLK_TEST_REG);
4819 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4820 LCC_CLK_HS_DEBUG_CFG_REG);
4821 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004822 case TEST_TYPE_CPUL2:
4823 writel_relaxed(0x4030400, CLK_TEST_REG);
4824 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4825 clk->sample_ticks = 0x4000;
4826 clk->multiplier = 2;
4827 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004828 default:
4829 ret = -EPERM;
4830 }
4831 /* Make sure test vector is set before starting measurements. */
4832 mb();
4833
4834 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4835
4836 return ret;
4837}
4838
4839/* Sample clock for 'ticks' reference clock ticks. */
4840static u32 run_measurement(unsigned ticks)
4841{
4842 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004843 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4844
4845 /* Wait for timer to become ready. */
4846 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4847 cpu_relax();
4848
4849 /* Run measurement and wait for completion. */
4850 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4851 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4852 cpu_relax();
4853
4854 /* Stop counters. */
4855 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4856
4857 /* Return measured ticks. */
4858 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4859}
4860
4861
4862/* Perform a hardware rate measurement for a given clock.
4863 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004864static unsigned measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004865{
4866 unsigned long flags;
4867 u32 pdm_reg_backup, ringosc_reg_backup;
4868 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004869 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004870 unsigned ret;
4871
4872 spin_lock_irqsave(&local_clock_reg_lock, flags);
4873
4874 /* Enable CXO/4 and RINGOSC branch and root. */
4875 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4876 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4877 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4878 writel_relaxed(0xA00, RINGOSC_NS_REG);
4879
4880 /*
4881 * The ring oscillator counter will not reset if the measured clock
4882 * is not running. To detect this, run a short measurement before
4883 * the full measurement. If the raw results of the two are the same
4884 * then the clock must be off.
4885 */
4886
4887 /* Run a short measurement. (~1 ms) */
4888 raw_count_short = run_measurement(0x1000);
4889 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004890 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004891
4892 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4893 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4894
4895 /* Return 0 if the clock is off. */
4896 if (raw_count_full == raw_count_short)
4897 ret = 0;
4898 else {
4899 /* Compute rate in Hz. */
4900 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004901 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4902 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004903 }
4904
4905 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004906 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004907 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4908
4909 return ret;
4910}
4911#else /* !CONFIG_DEBUG_FS */
4912static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4913{
4914 return -EINVAL;
4915}
4916
4917static unsigned measure_clk_get_rate(struct clk *clk)
4918{
4919 return 0;
4920}
4921#endif /* CONFIG_DEBUG_FS */
4922
4923static struct clk_ops measure_clk_ops = {
4924 .set_parent = measure_clk_set_parent,
4925 .get_rate = measure_clk_get_rate,
4926 .is_local = local_clk_is_local,
4927};
4928
Matt Wagantall8b38f942011-08-02 18:23:18 -07004929static struct measure_clk measure_clk = {
4930 .c = {
4931 .dbg_name = "measure_clk",
4932 .ops = &measure_clk_ops,
4933 CLK_INIT(measure_clk.c),
4934 },
4935 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004936};
4937
Tianyi Gou41515e22011-09-01 19:37:43 -07004938static struct clk_lookup msm_clocks_8064[] __initdata = {
4939 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07004940 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07004941 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
4942 CLK_DUMMY("pll4", PLL4, NULL, 0),
4943 CLK_LOOKUP("measure", measure_clk.c, "debug"),
4944
4945 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
4946 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
4947 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
4948 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
4949 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
4950 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
4951 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
4952 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
4953 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
4954 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
4955 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
4956 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
4957 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
4958 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
4959 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
4960 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
4961
4962 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
4963 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
4964 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
4965 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
4966 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, NULL),
4967 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, NULL),
4968 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
4969 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, NULL),
4970 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
4971 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, NULL),
4972 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, NULL),
4973 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
4974 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
4975 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
4976 CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
4977 CLK_LOOKUP("pmem_clk", pmem_clk.c, NULL),
4978 CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
Tianyi Gou43208a02011-09-27 15:35:13 -07004979 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
4980 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
4981 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
4982 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004983 CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
4984 CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
Tianyi Gou4496fba2011-10-12 11:40:15 -07004985 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07004986 CLK_LOOKUP("core_clk", usb_hs3_xcvr_clk.c, NULL),
4987 CLK_LOOKUP("core_clk", usb_hs4_xcvr_clk.c, NULL),
Tianyi Gou4496fba2011-10-12 11:40:15 -07004988 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
4989 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
4990 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07004991 CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
4992 CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
4993 CLK_LOOKUP("sata_phy_ref_clk", sata_phy_ref_clk.c, NULL),
4994 CLK_LOOKUP("sata_phy_cfg_clk", sata_phy_cfg_clk.c, NULL),
4995 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
4996 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
4997 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
4998 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, NULL),
4999 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, NULL),
5000 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, NULL),
5001 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
5002 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
5003 CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
Tianyi Gou4496fba2011-10-12 11:40:15 -07005004 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
5005 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005006 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, NULL),
5007 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, NULL),
Tianyi Gou43208a02011-09-27 15:35:13 -07005008 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5009 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5010 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5011 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005012 CLK_LOOKUP("iface_clk", pcie_p_clk.c, NULL),
5013 CLK_LOOKUP("core_src_clk", ce3_src_clk.c, NULL),
5014 CLK_LOOKUP("core_clk", ce3_core_clk.c, NULL),
5015 CLK_LOOKUP("iface_clk", ce3_p_clk.c, NULL),
5016 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5017 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
5018 CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
5019 CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
5020 CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
5021 CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
5022 CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005023 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5024 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
5025 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5026 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5027 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005028 CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005029 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
5030 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
5031 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005032 CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005033 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
5034 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
5035 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5036 CLK_DUMMY("csi_phy_clk", CSI0_PHY_CLK, NULL, OFF),
5037 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
5038 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
5039 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005040 CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
5041 CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005042 CLK_DUMMY("csi_pix_clk", CSI_PIX1_CLK, NULL, OFF),
5043 CLK_DUMMY("csi_rdi_clk", CSI_RDI1_CLK, NULL, OFF),
5044 CLK_DUMMY("csi_rdi_clk", CSI_RDI2_CLK, NULL, OFF),
5045 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
5046 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, NULL),
5047 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, NULL),
5048 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, NULL),
5049 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5050 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5051 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5052 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
5053 CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
5054 CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
5055 CLK_LOOKUP("core_clk", gfx3d_clk.c, NULL),
5056 CLK_LOOKUP("iface_clk", vcap_p_clk.c, NULL),
5057 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, NULL),
5058 CLK_LOOKUP("core_clk", vcap_clk.c, NULL),
5059 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, NULL),
5060 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, NULL),
5061 CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
5062 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
5063 CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
5064 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
5065 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
5066 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
5067 CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005068 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005069 CLK_LOOKUP("core_clk", vcodec_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005070 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
5071 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005072 CLK_LOOKUP("core_clk", hdmi_app_clk.c, NULL),
5073 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
5074 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
5075 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
5076 CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
5077 CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c, NULL),
5078 CLK_LOOKUP("rot_axi_clk", rot_axi_clk.c, NULL),
5079 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, NULL),
5080 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, NULL),
5081 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, NULL),
5082 CLK_LOOKUP("vpe_axi_clk", vpe_axi_clk.c, NULL),
5083 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
5084 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
5085 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5086 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5087 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5088 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
5089 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, NULL),
5090 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, NULL),
5091 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, NULL),
5092 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
5093 CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
5094 CLK_LOOKUP("imem_pclk", imem_p_clk.c, NULL),
5095 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
5096 CLK_LOOKUP("iface_clk", smmu_p_clk.c, NULL),
5097 CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
5098 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, NULL),
5099 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
5100 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005101 CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
5102 CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
5103 CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
5104 CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
5105 CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
5106 CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
5107 CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
5108 CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
5109 CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
5110 CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
5111 CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
5112 CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005113 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, NULL),
5114 CLK_LOOKUP("core_clk", vpe_axi_clk.c, NULL),
5115 CLK_LOOKUP("core_clk", mdp_axi_clk.c, NULL),
5116 CLK_LOOKUP("core_clk", vcap_axi_clk.c, NULL),
5117 CLK_LOOKUP("core_clk", rot_axi_clk.c, NULL),
5118 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, NULL),
5119 CLK_LOOKUP("core_clk", vfe_axi_clk.c, NULL),
5120 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, NULL),
5121 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, NULL),
5122 CLK_DUMMY("core_clk", GFX3D_AXI_CLK, NULL, 0),
Tianyi Gou41515e22011-09-01 19:37:43 -07005123 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
5124 CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
5125 CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, NULL, 0),
5126 CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, NULL, 0),
5127 CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, NULL, 0),
5128 CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, NULL, 0),
5129 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
5130 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
5131 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
5132 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
5133 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
5134 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
5135
5136 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
5137 CLK_LOOKUP("ebi1_clk", ebi1_adm_clk.c, "msm_dmov"),
5138
5139 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
5140 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
5141 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
5142};
5143
Stephen Boyd94625ef2011-07-12 17:06:01 -07005144static struct clk_lookup msm_clocks_8960_v1[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005145 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
5146 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5147 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5148 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005149 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005150
5151 CLK_LOOKUP("afab_clk", afab_clk.c, NULL),
5152 CLK_LOOKUP("afab_a_clk", afab_a_clk.c, NULL),
5153 CLK_LOOKUP("cfpb_clk", cfpb_clk.c, NULL),
5154 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, NULL),
5155 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
5156 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
5157 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
5158 CLK_LOOKUP("ebi1_a_clk", ebi1_a_clk.c, NULL),
5159 CLK_LOOKUP("mmfab_clk", mmfab_clk.c, NULL),
5160 CLK_LOOKUP("mmfab_a_clk", mmfab_a_clk.c, NULL),
5161 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5162 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, NULL),
Stephen Boyda3787f32011-09-16 18:55:13 -07005163 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005164 CLK_LOOKUP("sfab_clk", sfab_clk.c, NULL),
5165 CLK_LOOKUP("sfab_a_clk", sfab_a_clk.c, NULL),
5166 CLK_LOOKUP("sfpb_clk", sfpb_clk.c, NULL),
5167 CLK_LOOKUP("sfpb_a_clk", sfpb_a_clk.c, NULL),
5168
Matt Wagantalle2522372011-08-17 14:52:21 -07005169 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
5170 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
5171 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
5172 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
5173 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5174 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
5175 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
5176 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, NULL),
5177 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, NULL),
5178 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, NULL),
5179 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, NULL),
5180 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005181 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005182 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005183 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5184 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005185 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
5186 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
5187 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
5188 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, NULL),
5189 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005190 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005191 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005192 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Joel Nider93c8c6a2011-10-16 16:58:18 +02005193 CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
5194 CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005195 CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005196 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005197 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005198 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5199 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5200 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5201 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5202 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005203 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07005204 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005205 CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
5206 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
5207 CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
5208 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
5209 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
5210 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
5211 CLK_LOOKUP("usb_fs_clk", usb_fs2_xcvr_clk.c, NULL),
5212 CLK_LOOKUP("usb_fs_sys_clk", usb_fs2_sys_clk.c, NULL),
5213 CLK_LOOKUP("usb_fs_src_clk", usb_fs2_src_clk.c, NULL),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005214 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005215 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005216 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005217 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005218 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005219 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005220 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005221 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5222 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005223 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5224 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005225 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
5226 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, NULL),
5227 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005228 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005229 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005230 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07005231 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005232 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
5233 CLK_LOOKUP("usb_fs_pclk", usb_fs2_p_clk.c, NULL),
5234 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005235 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5236 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5237 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5238 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5239 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005240 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5241 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005242 CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
5243 CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
5244 CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
5245 CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
5246 CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
5247 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5248 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
5249 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_imx074.0"),
5250 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_ov2720.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07005251 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005252 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, NULL),
5253 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
5254 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07005255 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005256 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_camera_ov2720.0"),
5257 CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
5258 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
5259 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07005260 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005261 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_camera_ov2720.0"),
5262 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, NULL),
5263 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
5264 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07005265 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005266 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_camera_ov2720.0"),
5267 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, NULL),
5268 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, NULL),
5269 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
5270 CLK_LOOKUP("csi0phy_timer_clk", csi0phy_timer_clk.c, NULL),
5271 CLK_LOOKUP("csi1phy_timer_clk", csi1phy_timer_clk.c, NULL),
5272 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5273 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5274 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5275 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005276 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005277 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005278 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005279 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005280 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005281 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5282 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005283 CLK_LOOKUP("imem_axi_clk", imem_axi_clk.c, NULL),
5284 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005285 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005286 CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
5287 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005288 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005289 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
5290 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07005291 CLK_LOOKUP("qdss_pclk", qdss_p_clk.c, NULL),
5292 CLK_LOOKUP("qdss_at_clk", qdss_at_clk.c, NULL),
5293 CLK_LOOKUP("qdss_pclkdbg_clk", qdss_pclkdbg_clk.c, NULL),
5294 CLK_LOOKUP("qdss_traceclkin_clk", qdss_traceclkin_clk.c, NULL),
5295 CLK_LOOKUP("qdss_tsctr_clk", qdss_tsctr_clk.c, NULL),
5296 CLK_LOOKUP("qdss_stm_clk", qdss_stm_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005297 CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005298 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005299 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
5300 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
5301 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005302 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005303 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005304 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
5305 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005306 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005307 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005308 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005309 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005310 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Matt Wagantallc23eee92011-08-16 23:06:52 -07005311 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005312 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5313 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5314 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5315 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5316 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5317 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5318 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005319 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Matt Wagantallc23eee92011-08-16 23:06:52 -07005320 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005321 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5322 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5323 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5324 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005325 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005326 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005327 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005328 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005329 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005330 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005331 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5332 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005333 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005334 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005335 CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005336 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005337 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005338 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005339 CLK_LOOKUP("smmu_pclk", smmu_p_clk.c, NULL),
5340 CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005341 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005342 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005343 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005344 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005345 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005346 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005347 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005348 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005349 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
5350 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
5351 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
5352 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
5353 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
5354 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
5355 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
5356 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
5357 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
5358 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
5359 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
5360 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5361 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
5362 CLK_LOOKUP("iommu_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5363 CLK_LOOKUP("iommu_clk", vpe_axi_clk.c, "msm_iommu.1"),
5364 CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.2"),
5365 CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.3"),
5366 CLK_LOOKUP("iommu_clk", rot_axi_clk.c, "msm_iommu.4"),
5367 CLK_LOOKUP("iommu_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5368 CLK_LOOKUP("iommu_clk", vfe_axi_clk.c, "msm_iommu.6"),
5369 CLK_LOOKUP("iommu_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5370 CLK_LOOKUP("iommu_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5371 CLK_LOOKUP("iommu_clk", gfx3d_clk.c, "msm_iommu.9"),
5372 CLK_LOOKUP("iommu_clk", gfx2d0_clk.c, "msm_iommu.10"),
5373 CLK_LOOKUP("iommu_clk", gfx2d1_clk.c, "msm_iommu.11"),
5374 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5375 CLK_LOOKUP("dfab_usb_hs_clk", dfab_usb_hs_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005376 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5377 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5378 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5379 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5380 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005381 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005382
5383 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005384 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005385
5386 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
5387 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
5388 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
Stephen Boyd3939c8d2011-08-29 17:36:22 -07005389 CLK_LOOKUP("q6sw_clk", q6sw_clk, NULL),
5390 CLK_LOOKUP("q6fw_clk", q6fw_clk, NULL),
5391 CLK_LOOKUP("q6_func_clk", q6_func_clk, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005392};
5393
Stephen Boyd94625ef2011-07-12 17:06:01 -07005394static struct clk_lookup msm_clocks_8960_v2[] __initdata = {
5395 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
5396 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5397 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5398 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, NULL),
5399 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, NULL),
5400 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, NULL),
5401 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5402 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
5403 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
5404 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
5405 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
5406 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
5407 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
5408};
5409
5410/* Add v2 clocks dynamically at runtime */
5411static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_v1) +
5412 ARRAY_SIZE(msm_clocks_8960_v2)];
5413
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005414/*
5415 * Miscellaneous clock register initializations
5416 */
5417
5418/* Read, modify, then write-back a register. */
5419static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5420{
5421 uint32_t regval = readl_relaxed(reg);
5422 regval &= ~mask;
5423 regval |= val;
5424 writel_relaxed(regval, reg);
5425}
5426
Tianyi Gou41515e22011-09-01 19:37:43 -07005427static void __init set_fsm_mode(void __iomem *mode_reg)
5428{
5429 u32 regval = readl_relaxed(mode_reg);
5430
5431 /*De-assert reset to FSM */
5432 regval &= ~BIT(21);
5433 writel_relaxed(regval, mode_reg);
5434
5435 /* Program bias count */
5436 regval &= ~BM(13, 8);
5437 regval |= BVAL(13, 8, 0x8);
5438 writel_relaxed(regval, mode_reg);
5439
5440 /*Enable PLL FSM voting */
5441 regval |= BIT(20);
5442 writel_relaxed(regval, mode_reg);
5443}
5444
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005445static void __init reg_init(void)
5446{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005447 /* Deassert MM SW_RESET_ALL signal. */
5448 writel_relaxed(0, SW_RESET_ALL_REG);
5449
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005450 /*
5451 * Some bits are only used on either 8960 or 8064 and are marked as
5452 * reserved bits on the other SoC. Writing to these reserved bits
5453 * should have no effect.
5454 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005455 /* Initialize MM AHB registers: Enable the FPB clock and disable HW
5456 * gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
5457 * prevent its memory from being collapsed when the clock is halted.
5458 * The sleep and wake-up delays are set to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005459 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
5460 writel_relaxed(0x000007F9, AHB_EN2_REG);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005461 if (cpu_is_apq8064())
5462 rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005463
5464 /* Deassert all locally-owned MM AHB resets. */
5465 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07005466 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005467
5468 /* Initialize MM AXI registers: Enable HW gating for all clocks that
5469 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
5470 * delays to safe values. */
5471 /* TODO: Enable HW Gating */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005472 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
5473 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
5474 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
5475 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005476 if (cpu_is_apq8064())
5477 rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005478 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005479
5480 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
5481 * memories retain state even when not clocked. Also, set sleep and
5482 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005483 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
5484 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
5485 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
5486 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
5487 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
5488 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005489 rmwreg(0x80FF0000, GFX3D_CC_REG, 0xE0FF0010);
5490 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
5491 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
5492 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
5493 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
5494 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005495 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
5496 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
5497 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005498 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005499 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005500 if (cpu_is_msm8960()) {
5501 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
5502 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
5503 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
5504 }
5505 if (cpu_is_apq8064()) {
5506 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07005507 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005508 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005509
Tianyi Gou41515e22011-09-01 19:37:43 -07005510 /*
5511 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
5512 * core remain active during halt state of the clk. Also, set sleep
5513 * and wake-up value to max.
5514 */
5515 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005516 if (cpu_is_apq8064()) {
5517 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
5518 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
5519 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005520
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005521 /* De-assert MM AXI resets to all hardware blocks. */
5522 writel_relaxed(0, SW_RESET_AXI_REG);
5523
5524 /* Deassert all MM core resets. */
5525 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005526 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005527
5528 /* Reset 3D core once more, with its clock enabled. This can
5529 * eventually be done as part of the GDFS footswitch driver. */
5530 clk_set_rate(&gfx3d_clk.c, 27000000);
5531 clk_enable(&gfx3d_clk.c);
5532 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
5533 mb();
5534 udelay(5);
5535 writel_relaxed(0, SW_RESET_CORE_REG);
5536 /* Make sure reset is de-asserted before clock is disabled. */
5537 mb();
5538 clk_disable(&gfx3d_clk.c);
5539
5540 /* Enable TSSC and PDM PXO sources. */
5541 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
5542 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
5543
5544 /* Source SLIMBus xo src from slimbus reference clock */
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005545 if (cpu_is_msm8960())
5546 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005547
5548 /* Source the dsi_byte_clks from the DSI PHY PLLs */
5549 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
5550 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07005551
5552 /* Source the sata_phy_ref_clk from PXO */
5553 if (cpu_is_apq8064())
5554 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
5555
5556 /*
5557 * TODO: Programming below PLLs is temporary and needs to be removed
5558 * after bootloaders program them.
5559 */
5560 if (cpu_is_apq8064()) {
5561 u32 regval, is_pll_enabled;
5562
5563 /* Program pxo_src_clk to source from PXO */
5564 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
5565
5566 /* Check if PLL8 is active */
5567 is_pll_enabled = readl_relaxed(BB_PLL8_STATUS_REG) & BIT(16);
5568 if (!is_pll_enabled) {
5569 /* Ref clk = 24.5MHz and program pll8 to 384MHz */
5570 writel_relaxed(0xF, BB_PLL8_L_VAL_REG);
5571 writel_relaxed(0x21, BB_PLL8_M_VAL_REG);
5572 writel_relaxed(0x31, BB_PLL8_N_VAL_REG);
5573
5574 regval = readl_relaxed(BB_PLL8_CONFIG_REG);
5575
5576 /* Enable the main output and the MN accumulator */
5577 regval |= BIT(23) | BIT(22);
5578
5579 /* Set pre-divider and post-divider values to 1 and 1 */
5580 regval &= ~BIT(19);
5581 regval &= ~BM(21, 20);
5582
5583 writel_relaxed(regval, BB_PLL8_CONFIG_REG);
5584
5585 /* Set VCO frequency */
5586 rmwreg(0x10000, BB_PLL8_CONFIG_REG, 0x30000);
5587
5588 /* Enable AUX output */
5589 regval = readl_relaxed(BB_PLL8_TEST_CTL_REG);
5590 regval |= BIT(12);
5591 writel_relaxed(regval, BB_PLL8_TEST_CTL_REG);
5592
5593 set_fsm_mode(BB_PLL8_MODE_REG);
5594 }
5595 /* Check if PLL3 is active */
5596 is_pll_enabled = readl_relaxed(GPLL1_STATUS_REG) & BIT(16);
5597 if (!is_pll_enabled) {
5598 /* Ref clk = 24.5MHz and program pll3 to 1200MHz */
5599 writel_relaxed(0x30, GPLL1_L_VAL_REG);
5600 writel_relaxed(0x30, GPLL1_M_VAL_REG);
5601 writel_relaxed(0x31, GPLL1_N_VAL_REG);
5602
5603 regval = readl_relaxed(GPLL1_CONFIG_REG);
5604
5605 /* Set pre-divider and post-divider values to 1 and 1 */
5606 regval &= ~BIT(15);
5607 regval |= BIT(16);
5608
5609 writel_relaxed(regval, GPLL1_CONFIG_REG);
5610
5611 /* Set VCO frequency */
5612 rmwreg(0x180, GPLL1_CONFIG_REG, 0x180);
5613 }
5614 /* Check if PLL14 is active */
5615 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
5616 if (!is_pll_enabled) {
5617 /* Ref clk = 24.5MHz and program pll14 to 480MHz */
5618 writel_relaxed(0x13, BB_PLL14_L_VAL_REG);
5619 writel_relaxed(0x1D, BB_PLL14_M_VAL_REG);
5620 writel_relaxed(0x31, BB_PLL14_N_VAL_REG);
5621
5622 regval = readl_relaxed(BB_PLL14_CONFIG_REG);
5623
5624 /* Enable the main output and the MN accumulator */
5625 regval |= BIT(23) | BIT(22);
5626
5627 /* Set pre-divider and post-divider values to 1 and 1 */
5628 regval &= ~BIT(19);
5629 regval &= ~BM(21, 20);
5630
5631 writel_relaxed(regval, BB_PLL14_CONFIG_REG);
5632
5633 /* Set VCO frequency */
5634 rmwreg(0x10000, BB_PLL14_CONFIG_REG, 0x30000);
5635
5636 /* Enable AUX output */
5637 regval = readl_relaxed(BB_PLL14_TEST_CTL_REG);
5638 regval |= BIT(12);
5639 writel_relaxed(regval, BB_PLL14_TEST_CTL_REG);
5640
5641 set_fsm_mode(BB_PLL14_MODE_REG);
5642 }
Tianyi Gou621f8742011-09-01 21:45:01 -07005643 /* Program PLL2 to 800MHz with ref clk = 27MHz */
5644 writel_relaxed(0x1D, MM_PLL1_L_VAL_REG);
5645 writel_relaxed(0x11, MM_PLL1_M_VAL_REG);
5646 writel_relaxed(0x1B, MM_PLL1_N_VAL_REG);
5647
5648 regval = readl_relaxed(MM_PLL1_CONFIG_REG);
5649
5650 /* Enable the main output and the MN accumulator */
5651 regval |= BIT(23) | BIT(22);
5652
5653 /* Set pre-divider and post-divider values to 1 and 1 */
5654 regval &= ~BIT(19);
5655 regval &= ~BM(21, 20);
5656
5657 writel_relaxed(regval, MM_PLL1_CONFIG_REG);
5658
5659 /* Set VCO frequency */
5660 rmwreg(0x20000, MM_PLL1_CONFIG_REG, 0x30000);
5661
5662 /* Enable AUX output */
5663 regval = readl_relaxed(MM_PLL1_TEST_CTL_REG);
5664 regval |= BIT(12);
5665 writel_relaxed(regval, MM_PLL1_TEST_CTL_REG);
5666
5667 /* Program PLL15 to 975MHz with ref clk = 27MHz */
5668 writel_relaxed(0x24, MM_PLL3_L_VAL_REG);
5669 writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
5670 writel_relaxed(0x9, MM_PLL3_N_VAL_REG);
5671
5672 regval = readl_relaxed(MM_PLL3_CONFIG_REG);
5673
5674 /* Enable the main output and the MN accumulator */
5675 regval |= BIT(23) | BIT(22);
5676
5677 /* Set pre-divider and post-divider values to 1 and 1 */
5678 regval &= ~BIT(19);
5679 regval &= ~BM(21, 20);
5680
5681 writel_relaxed(regval, MM_PLL3_CONFIG_REG);
5682
5683 /* Set VCO frequency */
5684 rmwreg(0x20000, MM_PLL3_CONFIG_REG, 0x30000);
5685
5686 /* Enable AUX output */
5687 regval = readl_relaxed(MM_PLL3_TEST_CTL_REG);
5688 regval |= BIT(12);
5689 writel_relaxed(regval, MM_PLL3_TEST_CTL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005690 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005691}
5692
Stephen Boyd94625ef2011-07-12 17:06:01 -07005693struct clock_init_data msm8960_clock_init_data __initdata;
5694
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005695/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07005696static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005697{
Stephen Boyd94625ef2011-07-12 17:06:01 -07005698 size_t num_lookups = ARRAY_SIZE(msm_clocks_8960_v1);
Tianyi Gou41515e22011-09-01 19:37:43 -07005699
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005700 xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960");
5701 if (IS_ERR(xo_pxo)) {
5702 pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
5703 BUG();
5704 }
5705 xo_cxo = msm_xo_get(MSM_XO_TCXO_D0, "clock-8960");
5706 if (IS_ERR(xo_cxo)) {
5707 pr_err("%s: msm_xo_get(CXO) failed.\n", __func__);
5708 BUG();
5709 }
5710
Tianyi Gou41515e22011-09-01 19:37:43 -07005711 if (cpu_is_msm8960()) {
5712 memcpy(msm_clocks_8960, msm_clocks_8960_v1,
5713 sizeof(msm_clocks_8960_v1));
5714 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
5715 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960_v2;
5716 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07005717 msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
Tianyi Gou41515e22011-09-01 19:37:43 -07005718 num_lookups = ARRAY_SIZE(msm_clocks_8960);
5719 }
5720 msm8960_clock_init_data.size = num_lookups;
Stephen Boyd94625ef2011-07-12 17:06:01 -07005721 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005722
5723 /*
5724 * Change the freq tables for gfx3d_clk, ijpeg_clk, mdp_clk,
Tianyi Gou621f8742011-09-01 21:45:01 -07005725 * tv_src_clk and vfe_clk at runtime and chain gmem_axi_clk
5726 * with gfx3d_axi_clk for 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07005727 */
5728 if (cpu_is_apq8064()) {
5729 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
5730 ijpeg_clk.freq_tbl = clk_tbl_ijpeg_8064;
Tianyi Gou621f8742011-09-01 21:45:01 -07005731 mdp_clk.freq_tbl = clk_tbl_mdp_8064;
Tianyi Gou41515e22011-09-01 19:37:43 -07005732 vfe_clk.freq_tbl = clk_tbl_vfe_8064;
Tianyi Gou621f8742011-09-01 21:45:01 -07005733 gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07005734 }
Stephen Boyd94625ef2011-07-12 17:06:01 -07005735
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005736 soc_update_sys_vdd = msm8960_update_sys_vdd;
5737 local_vote_sys_vdd(HIGH);
5738
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07005739 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005740
5741 /* Initialize clock registers. */
5742 reg_init();
5743
5744 /* Initialize rates for clocks that only support one. */
5745 clk_set_rate(&pdm_clk.c, 27000000);
5746 clk_set_rate(&prng_clk.c, 64000000);
5747 clk_set_rate(&mdp_vsync_clk.c, 27000000);
5748 clk_set_rate(&tsif_ref_clk.c, 105000);
5749 clk_set_rate(&tssc_clk.c, 27000000);
5750 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07005751 if (cpu_is_apq8064()) {
5752 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
5753 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
5754 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005755 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07005756 if (cpu_is_msm8960())
5757 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005758 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
5759 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
5760 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005761
5762 /*
5763 * The halt status bits for PDM and TSSC may be incorrect at boot.
5764 * Toggle these clocks on and off to refresh them.
5765 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07005766 rcg_clk_enable(&pdm_clk.c);
5767 rcg_clk_disable(&pdm_clk.c);
5768 rcg_clk_enable(&tssc_clk.c);
5769 rcg_clk_disable(&tssc_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005770
5771 if (machine_is_msm8960_sim()) {
5772 clk_set_rate(&sdc1_clk.c, 48000000);
5773 clk_enable(&sdc1_clk.c);
5774 clk_enable(&sdc1_p_clk.c);
5775 clk_set_rate(&sdc3_clk.c, 48000000);
5776 clk_enable(&sdc3_clk.c);
5777 clk_enable(&sdc3_p_clk.c);
5778 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005779}
5780
Stephen Boydbb600ae2011-08-02 20:11:40 -07005781static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005782{
Stephen Boyda3787f32011-09-16 18:55:13 -07005783 int rc;
5784 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
5785
5786 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
5787 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
5788 PTR_ERR(mmfpb_a_clk)))
5789 return PTR_ERR(mmfpb_a_clk);
5790 rc = clk_set_min_rate(mmfpb_a_clk, 76800000);
5791 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
5792 return rc;
5793 rc = clk_enable(mmfpb_a_clk);
5794 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
5795 return rc;
5796
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005797 return local_unvote_sys_vdd(HIGH);
5798}
Stephen Boydbb600ae2011-08-02 20:11:40 -07005799
5800struct clock_init_data msm8960_clock_init_data __initdata = {
5801 .table = msm_clocks_8960,
5802 .size = ARRAY_SIZE(msm_clocks_8960),
5803 .init = msm8960_clock_init,
5804 .late_init = msm8960_clock_late_init,
5805};
Tianyi Gou41515e22011-09-01 19:37:43 -07005806
5807struct clock_init_data apq8064_clock_init_data __initdata = {
5808 .table = msm_clocks_8064,
5809 .size = ARRAY_SIZE(msm_clocks_8064),
5810 .init = msm8960_clock_init,
5811 .late_init = msm8960_clock_late_init,
5812};