blob: 63baae9f67db135d594bb0b35eb758b039371925 [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070029#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070030
31#include "clock-local.h"
32#include "clock-rpm.h"
33#include "clock-voter.h"
34#include "clock-dss-8960.h"
35#include "devices.h"
36
37#define REG(off) (MSM_CLK_CTL_BASE + (off))
38#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
39#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070040#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070041
42/* Peripheral clock registers. */
Stephen Boyda52d7e32011-11-10 11:59:00 -080043#define ADM0_PBUS_CLK_CTL_REG REG(0x2208)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070044#define CE1_HCLK_CTL_REG REG(0x2720)
45#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou05e01102012-02-08 22:15:49 -080046#define PRNG_CLK_NS_REG REG(0x2E80)
Tianyi Gou41515e22011-09-01 19:37:43 -070047#define CE3_HCLK_CTL_REG REG(0x36C4)
48#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
49#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070050#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou41515e22011-09-01 19:37:43 -070051#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070052#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
53#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
54#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
55#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070056/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070057#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
58#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070059#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070060#define CLK_TEST_REG REG(0x2FA0)
Matt Wagantall7625a4c2011-11-01 16:17:53 -070061#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
62#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070063#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
64#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
65#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
66#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
67#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
68#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070069#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070070/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070071#define BB_PLL_ENA_SC0_REG REG(0x34C0)
Tianyi Gou59608a72012-01-31 22:19:30 -080072#define BB_PLL_ENA_RPM_REG REG(0x34A0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070073#define BB_PLL0_STATUS_REG REG(0x30D8)
74#define BB_PLL5_STATUS_REG REG(0x30F8)
75#define BB_PLL6_STATUS_REG REG(0x3118)
76#define BB_PLL7_STATUS_REG REG(0x3138)
77#define BB_PLL8_L_VAL_REG REG(0x3144)
78#define BB_PLL8_M_VAL_REG REG(0x3148)
79#define BB_PLL8_MODE_REG REG(0x3140)
80#define BB_PLL8_N_VAL_REG REG(0x314C)
81#define BB_PLL8_STATUS_REG REG(0x3158)
82#define BB_PLL8_CONFIG_REG REG(0x3154)
83#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070084#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
85#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070086#define BB_PLL14_MODE_REG REG(0x31C0)
87#define BB_PLL14_L_VAL_REG REG(0x31C4)
88#define BB_PLL14_M_VAL_REG REG(0x31C8)
89#define BB_PLL14_N_VAL_REG REG(0x31CC)
90#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
91#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070092#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070093#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
94#define PMEM_ACLK_CTL_REG REG(0x25A0)
95#define RINGOSC_NS_REG REG(0x2DC0)
96#define RINGOSC_STATUS_REG REG(0x2DCC)
97#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
Stephen Boyda52d7e32011-11-10 11:59:00 -080098#define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070099#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
100#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
101#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
102#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
103#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
104#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
105#define TSIF_HCLK_CTL_REG REG(0x2700)
106#define TSIF_REF_CLK_MD_REG REG(0x270C)
107#define TSIF_REF_CLK_NS_REG REG(0x2710)
108#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700109#define SATA_CLK_SRC_NS_REG REG(0x2C08)
110#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
111#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
112#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
113#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700114#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
115#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
116#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
117#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
118#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
119#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700120#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700121#define USB_HS1_RESET_REG REG(0x2910)
122#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
123#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700124#define USB_HS3_HCLK_CTL_REG REG(0x3700)
125#define USB_HS3_HCLK_FS_REG REG(0x3704)
126#define USB_HS3_RESET_REG REG(0x3710)
127#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
128#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
129#define USB_HS4_HCLK_CTL_REG REG(0x3720)
130#define USB_HS4_HCLK_FS_REG REG(0x3724)
131#define USB_HS4_RESET_REG REG(0x3730)
132#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
133#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700134#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
135#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
136#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
137#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
138#define USB_HSIC_RESET_REG REG(0x2934)
139#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
140#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
141#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700142#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700143#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
144#define PCIE_HCLK_CTL_REG REG(0x22CC)
145#define GPLL1_MODE_REG REG(0x3160)
146#define GPLL1_L_VAL_REG REG(0x3164)
147#define GPLL1_M_VAL_REG REG(0x3168)
148#define GPLL1_N_VAL_REG REG(0x316C)
149#define GPLL1_CONFIG_REG REG(0x3174)
150#define GPLL1_STATUS_REG REG(0x3178)
151#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700152
153/* Multimedia clock registers. */
154#define AHB_EN_REG REG_MM(0x0008)
155#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700156#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700157#define AHB_NS_REG REG_MM(0x0004)
158#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700159#define CAMCLK0_NS_REG REG_MM(0x0148)
160#define CAMCLK0_CC_REG REG_MM(0x0140)
161#define CAMCLK0_MD_REG REG_MM(0x0144)
162#define CAMCLK1_NS_REG REG_MM(0x015C)
163#define CAMCLK1_CC_REG REG_MM(0x0154)
164#define CAMCLK1_MD_REG REG_MM(0x0158)
165#define CAMCLK2_NS_REG REG_MM(0x0228)
166#define CAMCLK2_CC_REG REG_MM(0x0220)
167#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700168#define CSI0_NS_REG REG_MM(0x0048)
169#define CSI0_CC_REG REG_MM(0x0040)
170#define CSI0_MD_REG REG_MM(0x0044)
171#define CSI1_NS_REG REG_MM(0x0010)
172#define CSI1_CC_REG REG_MM(0x0024)
173#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700174#define CSI2_NS_REG REG_MM(0x0234)
175#define CSI2_CC_REG REG_MM(0x022C)
176#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700177#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
178#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
179#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
180#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
181#define DSI1_BYTE_CC_REG REG_MM(0x0090)
182#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
183#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
184#define DSI1_ESC_NS_REG REG_MM(0x011C)
185#define DSI1_ESC_CC_REG REG_MM(0x00CC)
186#define DSI2_ESC_NS_REG REG_MM(0x0150)
187#define DSI2_ESC_CC_REG REG_MM(0x013C)
188#define DSI_PIXEL_CC_REG REG_MM(0x0130)
189#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
190#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
191#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
192#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
193#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
194#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
195#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
196#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
197#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
198#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700199#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700200#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
201#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
202#define GFX2D0_CC_REG REG_MM(0x0060)
203#define GFX2D0_MD0_REG REG_MM(0x0064)
204#define GFX2D0_MD1_REG REG_MM(0x0068)
205#define GFX2D0_NS_REG REG_MM(0x0070)
206#define GFX2D1_CC_REG REG_MM(0x0074)
207#define GFX2D1_MD0_REG REG_MM(0x0078)
208#define GFX2D1_MD1_REG REG_MM(0x006C)
209#define GFX2D1_NS_REG REG_MM(0x007C)
210#define GFX3D_CC_REG REG_MM(0x0080)
211#define GFX3D_MD0_REG REG_MM(0x0084)
212#define GFX3D_MD1_REG REG_MM(0x0088)
213#define GFX3D_NS_REG REG_MM(0x008C)
214#define IJPEG_CC_REG REG_MM(0x0098)
215#define IJPEG_MD_REG REG_MM(0x009C)
216#define IJPEG_NS_REG REG_MM(0x00A0)
217#define JPEGD_CC_REG REG_MM(0x00A4)
218#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700219#define VCAP_CC_REG REG_MM(0x0178)
220#define VCAP_NS_REG REG_MM(0x021C)
221#define VCAP_MD0_REG REG_MM(0x01EC)
222#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700223#define MAXI_EN_REG REG_MM(0x0018)
224#define MAXI_EN2_REG REG_MM(0x0020)
225#define MAXI_EN3_REG REG_MM(0x002C)
226#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700227#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700228#define MDP_CC_REG REG_MM(0x00C0)
229#define MDP_LUT_CC_REG REG_MM(0x016C)
230#define MDP_MD0_REG REG_MM(0x00C4)
231#define MDP_MD1_REG REG_MM(0x00C8)
232#define MDP_NS_REG REG_MM(0x00D0)
233#define MISC_CC_REG REG_MM(0x0058)
234#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700235#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700236#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700237#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
238#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
239#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
240#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
241#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
242#define MM_PLL1_STATUS_REG REG_MM(0x0334)
243#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700244#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
245#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
246#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
247#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
248#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
249#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700250#define ROT_CC_REG REG_MM(0x00E0)
251#define ROT_NS_REG REG_MM(0x00E8)
252#define SAXI_EN_REG REG_MM(0x0030)
253#define SW_RESET_AHB_REG REG_MM(0x020C)
254#define SW_RESET_AHB2_REG REG_MM(0x0200)
255#define SW_RESET_ALL_REG REG_MM(0x0204)
256#define SW_RESET_AXI_REG REG_MM(0x0208)
257#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700258#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700259#define TV_CC_REG REG_MM(0x00EC)
260#define TV_CC2_REG REG_MM(0x0124)
261#define TV_MD_REG REG_MM(0x00F0)
262#define TV_NS_REG REG_MM(0x00F4)
263#define VCODEC_CC_REG REG_MM(0x00F8)
264#define VCODEC_MD0_REG REG_MM(0x00FC)
265#define VCODEC_MD1_REG REG_MM(0x0128)
266#define VCODEC_NS_REG REG_MM(0x0100)
267#define VFE_CC_REG REG_MM(0x0104)
268#define VFE_MD_REG REG_MM(0x0108)
269#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700270#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700271#define VPE_CC_REG REG_MM(0x0110)
272#define VPE_NS_REG REG_MM(0x0118)
273
274/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700275#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700276#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
277#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
278#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
279#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
280#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
281#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
282#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
283#define LCC_MI2S_MD_REG REG_LPA(0x004C)
284#define LCC_MI2S_NS_REG REG_LPA(0x0048)
285#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
286#define LCC_PCM_MD_REG REG_LPA(0x0058)
287#define LCC_PCM_NS_REG REG_LPA(0x0054)
288#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700289#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
290#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
291#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
292#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
293#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700294#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700295#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
296#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
297#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
298#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
299#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
300#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
301#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
302#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
303#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
304#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700305#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700306
Matt Wagantall8b38f942011-08-02 18:23:18 -0700307#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
308
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700309/* MUX source input identifiers. */
310#define pxo_to_bb_mux 0
Matt Wagantall7625a4c2011-11-01 16:17:53 -0700311#define cxo_to_bb_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700312#define pll0_to_bb_mux 2
313#define pll8_to_bb_mux 3
314#define pll6_to_bb_mux 4
315#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700316#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700317#define pxo_to_mm_mux 0
318#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700319#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
320#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700321#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700322#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700323#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700324#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700325#define hdmi_pll_to_mm_mux 3
326#define cxo_to_xo_mux 0
327#define pxo_to_xo_mux 1
328#define gnd_to_xo_mux 3
329#define pxo_to_lpa_mux 0
330#define cxo_to_lpa_mux 1
331#define pll4_to_lpa_mux 2
332#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700333#define pxo_to_pcie_mux 0
334#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700335
336/* Test Vector Macros */
337#define TEST_TYPE_PER_LS 1
338#define TEST_TYPE_PER_HS 2
339#define TEST_TYPE_MM_LS 3
340#define TEST_TYPE_MM_HS 4
341#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700342#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700343#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700344#define TEST_TYPE_SHIFT 24
345#define TEST_CLK_SEL_MASK BM(23, 0)
346#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
347#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
348#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
349#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
350#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
351#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700352#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700353#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700354
355#define MN_MODE_DUAL_EDGE 0x2
356
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700357struct pll_rate {
358 const uint32_t l_val;
359 const uint32_t m_val;
360 const uint32_t n_val;
361 const uint32_t vco;
362 const uint32_t post_div;
363 const uint32_t i_bits;
364};
365#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
366
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700367enum vdd_dig_levels {
368 VDD_DIG_NONE,
369 VDD_DIG_LOW,
370 VDD_DIG_NOMINAL,
371 VDD_DIG_HIGH
372};
373
Saravana Kannan298ec392012-02-08 19:21:47 -0800374static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700375{
376 static const int vdd_uv[] = {
377 [VDD_DIG_NONE] = 0,
378 [VDD_DIG_LOW] = 945000,
379 [VDD_DIG_NOMINAL] = 1050000,
380 [VDD_DIG_HIGH] = 1150000
381 };
Saravana Kannan298ec392012-02-08 19:21:47 -0800382 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700383 vdd_uv[level], 1150000, 1);
384}
385
Saravana Kannan298ec392012-02-08 19:21:47 -0800386static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig_8960);
387
388static int set_vdd_dig_8930(struct clk_vdd_class *vdd_class, int level)
389{
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800390 static const int vdd_corner[] = {
391 [VDD_DIG_NONE] = RPM_VREG_CORNER_NONE,
392 [VDD_DIG_LOW] = RPM_VREG_CORNER_LOW,
393 [VDD_DIG_NOMINAL] = RPM_VREG_CORNER_NOMINAL,
394 [VDD_DIG_HIGH] = RPM_VREG_CORNER_HIGH,
Saravana Kannan298ec392012-02-08 19:21:47 -0800395 };
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800396 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_VDD_DIG_CORNER,
397 RPM_VREG_VOTER3,
398 vdd_corner[level],
399 RPM_VREG_CORNER_HIGH, 1);
Saravana Kannan298ec392012-02-08 19:21:47 -0800400}
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700401
402#define VDD_DIG_FMAX_MAP1(l1, f1) \
403 .vdd_class = &vdd_dig, \
404 .fmax[VDD_DIG_##l1] = (f1)
405#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
406 .vdd_class = &vdd_dig, \
407 .fmax[VDD_DIG_##l1] = (f1), \
408 .fmax[VDD_DIG_##l2] = (f2)
409#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
410 .vdd_class = &vdd_dig, \
411 .fmax[VDD_DIG_##l1] = (f1), \
412 .fmax[VDD_DIG_##l2] = (f2), \
413 .fmax[VDD_DIG_##l3] = (f3)
414
Tianyi Goue1faaf22012-01-24 16:07:19 -0800415enum vdd_sr2_pll_levels {
416 VDD_SR2_PLL_OFF,
417 VDD_SR2_PLL_ON
Matt Wagantallc57577d2011-10-06 17:06:53 -0700418};
419
Saravana Kannan298ec392012-02-08 19:21:47 -0800420static int set_vdd_sr2_pll_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantallc57577d2011-10-06 17:06:53 -0700421{
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800422 int rc = 0;
Saravana Kannan298ec392012-02-08 19:21:47 -0800423
424 if (level == VDD_SR2_PLL_OFF) {
425 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
426 RPM_VREG_VOTER3, 0, 0, 1);
427 if (rc)
428 return rc;
429 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
430 RPM_VREG_VOTER3, 0, 0, 1);
431 if (rc)
432 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
433 RPM_VREG_VOTER3, 1800000, 1800000, 1);
Tianyi Goue1faaf22012-01-24 16:07:19 -0800434 } else {
Saravana Kannan298ec392012-02-08 19:21:47 -0800435 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
436 RPM_VREG_VOTER3, 2100000, 2100000, 1);
437 if (rc)
438 return rc;
439 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
440 RPM_VREG_VOTER3, 1800000, 1800000, 1);
441 if (rc)
442 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800443 RPM_VREG_VOTER3, 0, 0, 1);
Matt Wagantallc57577d2011-10-06 17:06:53 -0700444 }
445
446 return rc;
447}
448
Saravana Kannan298ec392012-02-08 19:21:47 -0800449static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll_8960);
450
451static int sr2_lreg_uv[] = {
452 [VDD_SR2_PLL_OFF] = 0,
453 [VDD_SR2_PLL_ON] = 1800000,
454};
455
456static int set_vdd_sr2_pll_8064(struct clk_vdd_class *vdd_class, int level)
457{
458 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_LVS7, RPM_VREG_VOTER3,
459 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
460}
461
462static int set_vdd_sr2_pll_8930(struct clk_vdd_class *vdd_class, int level)
463{
464 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23, RPM_VREG_VOTER3,
465 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
466}
Matt Wagantallc57577d2011-10-06 17:06:53 -0700467
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700468/*
469 * Clock Descriptions
470 */
471
Stephen Boyd72a80352012-01-26 15:57:38 -0800472DEFINE_CLK_RPM_BRANCH(pxo_clk, pxo_a_clk, PXO, 27000000);
473DEFINE_CLK_RPM_BRANCH(cxo_clk, cxo_a_clk, CXO, 19200000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700474
475static struct pll_clk pll2_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700476 .mode_reg = MM_PLL1_MODE_REG,
477 .parent = &pxo_clk.c,
478 .c = {
479 .dbg_name = "pll2_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800480 .rate = 800000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700481 .ops = &clk_ops_pll,
482 CLK_INIT(pll2_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800483 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700484 },
485};
486
Stephen Boyd94625ef2011-07-12 17:06:01 -0700487static struct pll_clk pll3_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700488 .mode_reg = BB_MMCC_PLL2_MODE_REG,
489 .parent = &pxo_clk.c,
490 .c = {
491 .dbg_name = "pll3_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800492 .rate = 1200000000,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700493 .ops = &clk_ops_pll,
Tianyi Goue1faaf22012-01-24 16:07:19 -0800494 .vdd_class = &vdd_sr2_pll,
495 .fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700496 CLK_INIT(pll3_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800497 .warned = true,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700498 },
499};
500
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700501static struct pll_vote_clk pll4_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700502 .en_reg = BB_PLL_ENA_SC0_REG,
503 .en_mask = BIT(4),
504 .status_reg = LCC_PLL0_STATUS_REG,
505 .parent = &pxo_clk.c,
506 .c = {
507 .dbg_name = "pll4_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800508 .rate = 393216000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700509 .ops = &clk_ops_pll_vote,
510 CLK_INIT(pll4_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800511 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700512 },
513};
514
515static struct pll_vote_clk pll8_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700516 .en_reg = BB_PLL_ENA_SC0_REG,
517 .en_mask = BIT(8),
518 .status_reg = BB_PLL8_STATUS_REG,
519 .parent = &pxo_clk.c,
520 .c = {
521 .dbg_name = "pll8_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800522 .rate = 384000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700523 .ops = &clk_ops_pll_vote,
524 CLK_INIT(pll8_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800525 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700526 },
527};
528
Stephen Boyd94625ef2011-07-12 17:06:01 -0700529static struct pll_vote_clk pll14_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700530 .en_reg = BB_PLL_ENA_SC0_REG,
531 .en_mask = BIT(14),
532 .status_reg = BB_PLL14_STATUS_REG,
533 .parent = &pxo_clk.c,
534 .c = {
535 .dbg_name = "pll14_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800536 .rate = 480000000,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700537 .ops = &clk_ops_pll_vote,
538 CLK_INIT(pll14_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800539 .warned = true,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700540 },
541};
542
Tianyi Gou41515e22011-09-01 19:37:43 -0700543static struct pll_clk pll15_clk = {
Tianyi Gou41515e22011-09-01 19:37:43 -0700544 .mode_reg = MM_PLL3_MODE_REG,
545 .parent = &pxo_clk.c,
546 .c = {
547 .dbg_name = "pll15_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800548 .rate = 975000000,
Tianyi Gou41515e22011-09-01 19:37:43 -0700549 .ops = &clk_ops_pll,
550 CLK_INIT(pll15_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800551 .warned = true,
Tianyi Gou41515e22011-09-01 19:37:43 -0700552 },
553};
554
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700555static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700556 .enable = rcg_clk_enable,
557 .disable = rcg_clk_disable,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800558 .enable_hwcg = rcg_clk_enable_hwcg,
559 .disable_hwcg = rcg_clk_disable_hwcg,
560 .in_hwcg_mode = rcg_clk_in_hwcg_mode,
Matt Wagantall41af0772011-09-17 12:21:39 -0700561 .auto_off = rcg_clk_disable,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700562 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700563 .set_rate = rcg_clk_set_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700564 .list_rate = rcg_clk_list_rate,
565 .is_enabled = rcg_clk_is_enabled,
566 .round_rate = rcg_clk_round_rate,
Stephen Boyd7bf28142011-12-07 00:30:52 -0800567 .reset = rcg_clk_reset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700568 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700569 .get_parent = rcg_clk_get_parent,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800570 .set_flags = rcg_clk_set_flags,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700571};
572
573static struct clk_ops clk_ops_branch = {
574 .enable = branch_clk_enable,
575 .disable = branch_clk_disable,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800576 .enable_hwcg = branch_clk_enable_hwcg,
577 .disable_hwcg = branch_clk_disable_hwcg,
578 .in_hwcg_mode = branch_clk_in_hwcg_mode,
Matt Wagantall41af0772011-09-17 12:21:39 -0700579 .auto_off = branch_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700580 .is_enabled = branch_clk_is_enabled,
581 .reset = branch_clk_reset,
582 .is_local = local_clk_is_local,
583 .get_parent = branch_clk_get_parent,
584 .set_parent = branch_clk_set_parent,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800585 .handoff = branch_clk_handoff,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800586 .set_flags = branch_clk_set_flags,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700587};
588
589static struct clk_ops clk_ops_reset = {
590 .reset = branch_clk_reset,
591 .is_local = local_clk_is_local,
592};
593
594/* AXI Interfaces */
595static struct branch_clk gmem_axi_clk = {
596 .b = {
597 .ctl_reg = MAXI_EN_REG,
598 .en_mask = BIT(24),
599 .halt_reg = DBG_BUS_VEC_E_REG,
600 .halt_bit = 6,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800601 .retain_reg = MAXI_EN2_REG,
602 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700603 },
604 .c = {
605 .dbg_name = "gmem_axi_clk",
606 .ops = &clk_ops_branch,
607 CLK_INIT(gmem_axi_clk.c),
608 },
609};
610
611static struct branch_clk ijpeg_axi_clk = {
612 .b = {
613 .ctl_reg = MAXI_EN_REG,
614 .en_mask = BIT(21),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800615 .hwcg_reg = MAXI_EN_REG,
616 .hwcg_mask = BIT(11),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700617 .reset_reg = SW_RESET_AXI_REG,
618 .reset_mask = BIT(14),
619 .halt_reg = DBG_BUS_VEC_E_REG,
620 .halt_bit = 4,
621 },
622 .c = {
623 .dbg_name = "ijpeg_axi_clk",
624 .ops = &clk_ops_branch,
625 CLK_INIT(ijpeg_axi_clk.c),
626 },
627};
628
629static struct branch_clk imem_axi_clk = {
630 .b = {
631 .ctl_reg = MAXI_EN_REG,
632 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800633 .hwcg_reg = MAXI_EN_REG,
634 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700635 .reset_reg = SW_RESET_CORE_REG,
636 .reset_mask = BIT(10),
637 .halt_reg = DBG_BUS_VEC_E_REG,
638 .halt_bit = 7,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800639 .retain_reg = MAXI_EN2_REG,
640 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700641 },
642 .c = {
643 .dbg_name = "imem_axi_clk",
644 .ops = &clk_ops_branch,
645 CLK_INIT(imem_axi_clk.c),
646 },
647};
648
649static struct branch_clk jpegd_axi_clk = {
650 .b = {
651 .ctl_reg = MAXI_EN_REG,
652 .en_mask = BIT(25),
653 .halt_reg = DBG_BUS_VEC_E_REG,
654 .halt_bit = 5,
655 },
656 .c = {
657 .dbg_name = "jpegd_axi_clk",
658 .ops = &clk_ops_branch,
659 CLK_INIT(jpegd_axi_clk.c),
660 },
661};
662
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700663static struct branch_clk vcodec_axi_b_clk = {
664 .b = {
665 .ctl_reg = MAXI_EN4_REG,
666 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800667 .hwcg_reg = MAXI_EN4_REG,
668 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700669 .halt_reg = DBG_BUS_VEC_I_REG,
670 .halt_bit = 25,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800671 .retain_reg = MAXI_EN4_REG,
672 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700673 },
674 .c = {
675 .dbg_name = "vcodec_axi_b_clk",
676 .ops = &clk_ops_branch,
677 CLK_INIT(vcodec_axi_b_clk.c),
678 },
679};
680
Matt Wagantall91f42702011-07-14 12:01:15 -0700681static struct branch_clk vcodec_axi_a_clk = {
682 .b = {
683 .ctl_reg = MAXI_EN4_REG,
684 .en_mask = BIT(25),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800685 .hwcg_reg = MAXI_EN4_REG,
686 .hwcg_mask = BIT(24),
Matt Wagantall91f42702011-07-14 12:01:15 -0700687 .halt_reg = DBG_BUS_VEC_I_REG,
688 .halt_bit = 26,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800689 .retain_reg = MAXI_EN4_REG,
690 .retain_mask = BIT(10),
Matt Wagantall91f42702011-07-14 12:01:15 -0700691 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700692 .c = {
693 .dbg_name = "vcodec_axi_a_clk",
694 .ops = &clk_ops_branch,
695 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700696 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700697 },
698};
699
700static struct branch_clk vcodec_axi_clk = {
701 .b = {
702 .ctl_reg = MAXI_EN_REG,
703 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800704 .hwcg_reg = MAXI_EN_REG,
705 .hwcg_mask = BIT(13),
Matt Wagantall91f42702011-07-14 12:01:15 -0700706 .reset_reg = SW_RESET_AXI_REG,
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -0800707 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700708 .halt_reg = DBG_BUS_VEC_E_REG,
709 .halt_bit = 3,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800710 .retain_reg = MAXI_EN2_REG,
711 .retain_mask = BIT(28),
Matt Wagantall91f42702011-07-14 12:01:15 -0700712 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700713 .c = {
714 .dbg_name = "vcodec_axi_clk",
715 .ops = &clk_ops_branch,
716 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700717 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700718 },
719};
720
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700721static struct branch_clk vfe_axi_clk = {
722 .b = {
723 .ctl_reg = MAXI_EN_REG,
724 .en_mask = BIT(18),
725 .reset_reg = SW_RESET_AXI_REG,
726 .reset_mask = BIT(9),
727 .halt_reg = DBG_BUS_VEC_E_REG,
728 .halt_bit = 0,
729 },
730 .c = {
731 .dbg_name = "vfe_axi_clk",
732 .ops = &clk_ops_branch,
733 CLK_INIT(vfe_axi_clk.c),
734 },
735};
736
737static struct branch_clk mdp_axi_clk = {
738 .b = {
739 .ctl_reg = MAXI_EN_REG,
740 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800741 .hwcg_reg = MAXI_EN_REG,
742 .hwcg_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700743 .reset_reg = SW_RESET_AXI_REG,
744 .reset_mask = BIT(13),
745 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700746 .halt_bit = 8,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800747 .retain_reg = MAXI_EN_REG,
748 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700749 },
750 .c = {
751 .dbg_name = "mdp_axi_clk",
752 .ops = &clk_ops_branch,
753 CLK_INIT(mdp_axi_clk.c),
754 },
755};
756
757static struct branch_clk rot_axi_clk = {
758 .b = {
759 .ctl_reg = MAXI_EN2_REG,
760 .en_mask = BIT(24),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800761 .hwcg_reg = MAXI_EN2_REG,
762 .hwcg_mask = BIT(25),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700763 .reset_reg = SW_RESET_AXI_REG,
764 .reset_mask = BIT(6),
765 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700766 .halt_bit = 2,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800767 .retain_reg = MAXI_EN3_REG,
768 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700769 },
770 .c = {
771 .dbg_name = "rot_axi_clk",
772 .ops = &clk_ops_branch,
773 CLK_INIT(rot_axi_clk.c),
774 },
775};
776
777static struct branch_clk vpe_axi_clk = {
778 .b = {
779 .ctl_reg = MAXI_EN2_REG,
780 .en_mask = BIT(26),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800781 .hwcg_reg = MAXI_EN2_REG,
782 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700783 .reset_reg = SW_RESET_AXI_REG,
784 .reset_mask = BIT(15),
785 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700786 .halt_bit = 1,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800787 .retain_reg = MAXI_EN3_REG,
788 .retain_mask = BIT(21),
789
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700790 },
791 .c = {
792 .dbg_name = "vpe_axi_clk",
793 .ops = &clk_ops_branch,
794 CLK_INIT(vpe_axi_clk.c),
795 },
796};
797
Tianyi Gou41515e22011-09-01 19:37:43 -0700798static struct branch_clk vcap_axi_clk = {
799 .b = {
800 .ctl_reg = MAXI_EN5_REG,
801 .en_mask = BIT(12),
802 .reset_reg = SW_RESET_AXI_REG,
803 .reset_mask = BIT(16),
804 .halt_reg = DBG_BUS_VEC_J_REG,
805 .halt_bit = 20,
806 },
807 .c = {
808 .dbg_name = "vcap_axi_clk",
809 .ops = &clk_ops_branch,
810 CLK_INIT(vcap_axi_clk.c),
811 },
812};
813
Tianyi Gou621f8742011-09-01 21:45:01 -0700814/* For 8064, gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
815static struct branch_clk gfx3d_axi_clk = {
816 .b = {
817 .ctl_reg = MAXI_EN5_REG,
818 .en_mask = BIT(25),
819 .reset_reg = SW_RESET_AXI_REG,
820 .reset_mask = BIT(17),
821 .halt_reg = DBG_BUS_VEC_J_REG,
822 .halt_bit = 30,
823 },
824 .c = {
825 .dbg_name = "gfx3d_axi_clk",
826 .ops = &clk_ops_branch,
827 CLK_INIT(gfx3d_axi_clk.c),
828 },
829};
830
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700831/* AHB Interfaces */
832static struct branch_clk amp_p_clk = {
833 .b = {
834 .ctl_reg = AHB_EN_REG,
835 .en_mask = BIT(24),
836 .halt_reg = DBG_BUS_VEC_F_REG,
837 .halt_bit = 18,
838 },
839 .c = {
840 .dbg_name = "amp_p_clk",
841 .ops = &clk_ops_branch,
842 CLK_INIT(amp_p_clk.c),
843 },
844};
845
Matt Wagantallc23eee92011-08-16 23:06:52 -0700846static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700847 .b = {
848 .ctl_reg = AHB_EN_REG,
849 .en_mask = BIT(7),
850 .reset_reg = SW_RESET_AHB_REG,
851 .reset_mask = BIT(17),
852 .halt_reg = DBG_BUS_VEC_F_REG,
853 .halt_bit = 16,
854 },
855 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700856 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700857 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700858 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700859 },
860};
861
862static struct branch_clk dsi1_m_p_clk = {
863 .b = {
864 .ctl_reg = AHB_EN_REG,
865 .en_mask = BIT(9),
866 .reset_reg = SW_RESET_AHB_REG,
867 .reset_mask = BIT(6),
868 .halt_reg = DBG_BUS_VEC_F_REG,
869 .halt_bit = 19,
870 },
871 .c = {
872 .dbg_name = "dsi1_m_p_clk",
873 .ops = &clk_ops_branch,
874 CLK_INIT(dsi1_m_p_clk.c),
875 },
876};
877
878static struct branch_clk dsi1_s_p_clk = {
879 .b = {
880 .ctl_reg = AHB_EN_REG,
881 .en_mask = BIT(18),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800882 .hwcg_reg = AHB_EN2_REG,
883 .hwcg_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700884 .reset_reg = SW_RESET_AHB_REG,
885 .reset_mask = BIT(5),
886 .halt_reg = DBG_BUS_VEC_F_REG,
887 .halt_bit = 21,
888 },
889 .c = {
890 .dbg_name = "dsi1_s_p_clk",
891 .ops = &clk_ops_branch,
892 CLK_INIT(dsi1_s_p_clk.c),
893 },
894};
895
896static struct branch_clk dsi2_m_p_clk = {
897 .b = {
898 .ctl_reg = AHB_EN_REG,
899 .en_mask = BIT(17),
900 .reset_reg = SW_RESET_AHB2_REG,
901 .reset_mask = BIT(1),
902 .halt_reg = DBG_BUS_VEC_E_REG,
903 .halt_bit = 18,
904 },
905 .c = {
906 .dbg_name = "dsi2_m_p_clk",
907 .ops = &clk_ops_branch,
908 CLK_INIT(dsi2_m_p_clk.c),
909 },
910};
911
912static struct branch_clk dsi2_s_p_clk = {
913 .b = {
914 .ctl_reg = AHB_EN_REG,
915 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800916 .hwcg_reg = AHB_EN2_REG,
917 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700918 .reset_reg = SW_RESET_AHB2_REG,
919 .reset_mask = BIT(0),
920 .halt_reg = DBG_BUS_VEC_F_REG,
921 .halt_bit = 20,
922 },
923 .c = {
924 .dbg_name = "dsi2_s_p_clk",
925 .ops = &clk_ops_branch,
926 CLK_INIT(dsi2_s_p_clk.c),
927 },
928};
929
930static struct branch_clk gfx2d0_p_clk = {
931 .b = {
932 .ctl_reg = AHB_EN_REG,
933 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800934 .hwcg_reg = AHB_EN2_REG,
935 .hwcg_mask = BIT(28),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700936 .reset_reg = SW_RESET_AHB_REG,
937 .reset_mask = BIT(12),
938 .halt_reg = DBG_BUS_VEC_F_REG,
939 .halt_bit = 2,
940 },
941 .c = {
942 .dbg_name = "gfx2d0_p_clk",
943 .ops = &clk_ops_branch,
944 CLK_INIT(gfx2d0_p_clk.c),
945 },
946};
947
948static struct branch_clk gfx2d1_p_clk = {
949 .b = {
950 .ctl_reg = AHB_EN_REG,
951 .en_mask = BIT(2),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800952 .hwcg_reg = AHB_EN2_REG,
953 .hwcg_mask = BIT(29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700954 .reset_reg = SW_RESET_AHB_REG,
955 .reset_mask = BIT(11),
956 .halt_reg = DBG_BUS_VEC_F_REG,
957 .halt_bit = 3,
958 },
959 .c = {
960 .dbg_name = "gfx2d1_p_clk",
961 .ops = &clk_ops_branch,
962 CLK_INIT(gfx2d1_p_clk.c),
963 },
964};
965
966static struct branch_clk gfx3d_p_clk = {
967 .b = {
968 .ctl_reg = AHB_EN_REG,
969 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800970 .hwcg_reg = AHB_EN2_REG,
971 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700972 .reset_reg = SW_RESET_AHB_REG,
973 .reset_mask = BIT(10),
974 .halt_reg = DBG_BUS_VEC_F_REG,
975 .halt_bit = 4,
976 },
977 .c = {
978 .dbg_name = "gfx3d_p_clk",
979 .ops = &clk_ops_branch,
980 CLK_INIT(gfx3d_p_clk.c),
981 },
982};
983
984static struct branch_clk hdmi_m_p_clk = {
985 .b = {
986 .ctl_reg = AHB_EN_REG,
987 .en_mask = BIT(14),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800988 .hwcg_reg = AHB_EN2_REG,
989 .hwcg_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700990 .reset_reg = SW_RESET_AHB_REG,
991 .reset_mask = BIT(9),
992 .halt_reg = DBG_BUS_VEC_F_REG,
993 .halt_bit = 5,
994 },
995 .c = {
996 .dbg_name = "hdmi_m_p_clk",
997 .ops = &clk_ops_branch,
998 CLK_INIT(hdmi_m_p_clk.c),
999 },
1000};
1001
1002static struct branch_clk hdmi_s_p_clk = {
1003 .b = {
1004 .ctl_reg = AHB_EN_REG,
1005 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001006 .hwcg_reg = AHB_EN2_REG,
1007 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001008 .reset_reg = SW_RESET_AHB_REG,
1009 .reset_mask = BIT(9),
1010 .halt_reg = DBG_BUS_VEC_F_REG,
1011 .halt_bit = 6,
1012 },
1013 .c = {
1014 .dbg_name = "hdmi_s_p_clk",
1015 .ops = &clk_ops_branch,
1016 CLK_INIT(hdmi_s_p_clk.c),
1017 },
1018};
1019
1020static struct branch_clk ijpeg_p_clk = {
1021 .b = {
1022 .ctl_reg = AHB_EN_REG,
1023 .en_mask = BIT(5),
1024 .reset_reg = SW_RESET_AHB_REG,
1025 .reset_mask = BIT(7),
1026 .halt_reg = DBG_BUS_VEC_F_REG,
1027 .halt_bit = 9,
1028 },
1029 .c = {
1030 .dbg_name = "ijpeg_p_clk",
1031 .ops = &clk_ops_branch,
1032 CLK_INIT(ijpeg_p_clk.c),
1033 },
1034};
1035
1036static struct branch_clk imem_p_clk = {
1037 .b = {
1038 .ctl_reg = AHB_EN_REG,
1039 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001040 .hwcg_reg = AHB_EN2_REG,
1041 .hwcg_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001042 .reset_reg = SW_RESET_AHB_REG,
1043 .reset_mask = BIT(8),
1044 .halt_reg = DBG_BUS_VEC_F_REG,
1045 .halt_bit = 10,
1046 },
1047 .c = {
1048 .dbg_name = "imem_p_clk",
1049 .ops = &clk_ops_branch,
1050 CLK_INIT(imem_p_clk.c),
1051 },
1052};
1053
1054static struct branch_clk jpegd_p_clk = {
1055 .b = {
1056 .ctl_reg = AHB_EN_REG,
1057 .en_mask = BIT(21),
1058 .reset_reg = SW_RESET_AHB_REG,
1059 .reset_mask = BIT(4),
1060 .halt_reg = DBG_BUS_VEC_F_REG,
1061 .halt_bit = 7,
1062 },
1063 .c = {
1064 .dbg_name = "jpegd_p_clk",
1065 .ops = &clk_ops_branch,
1066 CLK_INIT(jpegd_p_clk.c),
1067 },
1068};
1069
1070static struct branch_clk mdp_p_clk = {
1071 .b = {
1072 .ctl_reg = AHB_EN_REG,
1073 .en_mask = BIT(10),
1074 .reset_reg = SW_RESET_AHB_REG,
1075 .reset_mask = BIT(3),
1076 .halt_reg = DBG_BUS_VEC_F_REG,
1077 .halt_bit = 11,
1078 },
1079 .c = {
1080 .dbg_name = "mdp_p_clk",
1081 .ops = &clk_ops_branch,
1082 CLK_INIT(mdp_p_clk.c),
1083 },
1084};
1085
1086static struct branch_clk rot_p_clk = {
1087 .b = {
1088 .ctl_reg = AHB_EN_REG,
1089 .en_mask = BIT(12),
1090 .reset_reg = SW_RESET_AHB_REG,
1091 .reset_mask = BIT(2),
1092 .halt_reg = DBG_BUS_VEC_F_REG,
1093 .halt_bit = 13,
1094 },
1095 .c = {
1096 .dbg_name = "rot_p_clk",
1097 .ops = &clk_ops_branch,
1098 CLK_INIT(rot_p_clk.c),
1099 },
1100};
1101
1102static struct branch_clk smmu_p_clk = {
1103 .b = {
1104 .ctl_reg = AHB_EN_REG,
1105 .en_mask = BIT(15),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001106 .hwcg_reg = AHB_EN_REG,
1107 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001108 .halt_reg = DBG_BUS_VEC_F_REG,
1109 .halt_bit = 22,
1110 },
1111 .c = {
1112 .dbg_name = "smmu_p_clk",
1113 .ops = &clk_ops_branch,
1114 CLK_INIT(smmu_p_clk.c),
1115 },
1116};
1117
1118static struct branch_clk tv_enc_p_clk = {
1119 .b = {
1120 .ctl_reg = AHB_EN_REG,
1121 .en_mask = BIT(25),
1122 .reset_reg = SW_RESET_AHB_REG,
1123 .reset_mask = BIT(15),
1124 .halt_reg = DBG_BUS_VEC_F_REG,
1125 .halt_bit = 23,
1126 },
1127 .c = {
1128 .dbg_name = "tv_enc_p_clk",
1129 .ops = &clk_ops_branch,
1130 CLK_INIT(tv_enc_p_clk.c),
1131 },
1132};
1133
1134static struct branch_clk vcodec_p_clk = {
1135 .b = {
1136 .ctl_reg = AHB_EN_REG,
1137 .en_mask = BIT(11),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001138 .hwcg_reg = AHB_EN2_REG,
1139 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001140 .reset_reg = SW_RESET_AHB_REG,
1141 .reset_mask = BIT(1),
1142 .halt_reg = DBG_BUS_VEC_F_REG,
1143 .halt_bit = 12,
1144 },
1145 .c = {
1146 .dbg_name = "vcodec_p_clk",
1147 .ops = &clk_ops_branch,
1148 CLK_INIT(vcodec_p_clk.c),
1149 },
1150};
1151
1152static struct branch_clk vfe_p_clk = {
1153 .b = {
1154 .ctl_reg = AHB_EN_REG,
1155 .en_mask = BIT(13),
1156 .reset_reg = SW_RESET_AHB_REG,
1157 .reset_mask = BIT(0),
1158 .halt_reg = DBG_BUS_VEC_F_REG,
1159 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08001160 .retain_reg = AHB_EN2_REG,
1161 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001162 },
1163 .c = {
1164 .dbg_name = "vfe_p_clk",
1165 .ops = &clk_ops_branch,
1166 CLK_INIT(vfe_p_clk.c),
1167 },
1168};
1169
1170static struct branch_clk vpe_p_clk = {
1171 .b = {
1172 .ctl_reg = AHB_EN_REG,
1173 .en_mask = BIT(16),
1174 .reset_reg = SW_RESET_AHB_REG,
1175 .reset_mask = BIT(14),
1176 .halt_reg = DBG_BUS_VEC_F_REG,
1177 .halt_bit = 15,
1178 },
1179 .c = {
1180 .dbg_name = "vpe_p_clk",
1181 .ops = &clk_ops_branch,
1182 CLK_INIT(vpe_p_clk.c),
1183 },
1184};
1185
Tianyi Gou41515e22011-09-01 19:37:43 -07001186static struct branch_clk vcap_p_clk = {
1187 .b = {
1188 .ctl_reg = AHB_EN3_REG,
1189 .en_mask = BIT(1),
1190 .reset_reg = SW_RESET_AHB2_REG,
1191 .reset_mask = BIT(2),
1192 .halt_reg = DBG_BUS_VEC_J_REG,
1193 .halt_bit = 23,
1194 },
1195 .c = {
1196 .dbg_name = "vcap_p_clk",
1197 .ops = &clk_ops_branch,
1198 CLK_INIT(vcap_p_clk.c),
1199 },
1200};
1201
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001202/*
1203 * Peripheral Clocks
1204 */
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001205#define CLK_GP(i, n, h_r, h_b) \
1206 struct rcg_clk i##_clk = { \
1207 .b = { \
1208 .ctl_reg = GPn_NS_REG(n), \
1209 .en_mask = BIT(9), \
1210 .halt_reg = h_r, \
1211 .halt_bit = h_b, \
1212 }, \
1213 .ns_reg = GPn_NS_REG(n), \
1214 .md_reg = GPn_MD_REG(n), \
1215 .root_en_mask = BIT(11), \
1216 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001217 .mnd_en_mask = BIT(8), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001218 .set_rate = set_rate_mnd, \
1219 .freq_tbl = clk_tbl_gp, \
1220 .current_freq = &rcg_dummy_freq, \
1221 .c = { \
1222 .dbg_name = #i "_clk", \
1223 .ops = &clk_ops_rcg_8960, \
1224 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
1225 CLK_INIT(i##_clk.c), \
1226 }, \
1227 }
1228#define F_GP(f, s, d, m, n) \
1229 { \
1230 .freq_hz = f, \
1231 .src_clk = &s##_clk.c, \
1232 .md_val = MD8(16, m, 0, n), \
1233 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001234 }
1235static struct clk_freq_tbl clk_tbl_gp[] = {
1236 F_GP( 0, gnd, 1, 0, 0),
1237 F_GP( 9600000, cxo, 2, 0, 0),
1238 F_GP( 13500000, pxo, 2, 0, 0),
1239 F_GP( 19200000, cxo, 1, 0, 0),
1240 F_GP( 27000000, pxo, 1, 0, 0),
1241 F_GP( 64000000, pll8, 2, 1, 3),
1242 F_GP( 76800000, pll8, 1, 1, 5),
1243 F_GP( 96000000, pll8, 4, 0, 0),
1244 F_GP(128000000, pll8, 3, 0, 0),
1245 F_GP(192000000, pll8, 2, 0, 0),
1246 F_GP(384000000, pll8, 1, 0, 0),
1247 F_END
1248};
1249
1250static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
1251static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
1252static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
1253
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001254#define CLK_GSBI_UART(i, n, h_r, h_b) \
1255 struct rcg_clk i##_clk = { \
1256 .b = { \
1257 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1258 .en_mask = BIT(9), \
1259 .reset_reg = GSBIn_RESET_REG(n), \
1260 .reset_mask = BIT(0), \
1261 .halt_reg = h_r, \
1262 .halt_bit = h_b, \
1263 }, \
1264 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1265 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1266 .root_en_mask = BIT(11), \
1267 .ns_mask = (BM(31, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001268 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001269 .set_rate = set_rate_mnd, \
1270 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001271 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001272 .c = { \
1273 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001274 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001275 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001276 CLK_INIT(i##_clk.c), \
1277 }, \
1278 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001279#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001280 { \
1281 .freq_hz = f, \
1282 .src_clk = &s##_clk.c, \
1283 .md_val = MD16(m, n), \
1284 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001285 }
1286static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001287 F_GSBI_UART( 0, gnd, 1, 0, 0),
Matt Wagantall9a561f72012-01-19 16:13:12 -08001288 F_GSBI_UART( 1843200, pll8, 2, 6, 625),
1289 F_GSBI_UART( 3686400, pll8, 2, 12, 625),
1290 F_GSBI_UART( 7372800, pll8, 2, 24, 625),
1291 F_GSBI_UART(14745600, pll8, 2, 48, 625),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001292 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1293 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1294 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1295 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1296 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1297 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1298 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1299 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1300 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1301 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001302 F_END
1303};
1304
1305static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1306static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1307static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1308static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1309static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1310static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1311static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1312static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1313static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1314static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1315static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1316static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1317
1318#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1319 struct rcg_clk i##_clk = { \
1320 .b = { \
1321 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1322 .en_mask = BIT(9), \
1323 .reset_reg = GSBIn_RESET_REG(n), \
1324 .reset_mask = BIT(0), \
1325 .halt_reg = h_r, \
1326 .halt_bit = h_b, \
1327 }, \
1328 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1329 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1330 .root_en_mask = BIT(11), \
1331 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001332 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001333 .set_rate = set_rate_mnd, \
1334 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001335 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001336 .c = { \
1337 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001338 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001339 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001340 CLK_INIT(i##_clk.c), \
1341 }, \
1342 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001343#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001344 { \
1345 .freq_hz = f, \
1346 .src_clk = &s##_clk.c, \
1347 .md_val = MD8(16, m, 0, n), \
1348 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001349 }
1350static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001351 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1352 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1353 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1354 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1355 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1356 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1357 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1358 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1359 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1360 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001361 F_END
1362};
1363
1364static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1365static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1366static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1367static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1368static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1369static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1370static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1371static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1372static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1373static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1374static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1375static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1376
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001377#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001378 { \
1379 .freq_hz = f, \
1380 .src_clk = &s##_clk.c, \
1381 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001382 }
1383static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001384 F_PDM( 0, gnd, 1),
1385 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001386 F_END
1387};
1388
1389static struct rcg_clk pdm_clk = {
1390 .b = {
1391 .ctl_reg = PDM_CLK_NS_REG,
1392 .en_mask = BIT(9),
1393 .reset_reg = PDM_CLK_NS_REG,
1394 .reset_mask = BIT(12),
1395 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1396 .halt_bit = 3,
1397 },
1398 .ns_reg = PDM_CLK_NS_REG,
1399 .root_en_mask = BIT(11),
1400 .ns_mask = BM(1, 0),
1401 .set_rate = set_rate_nop,
1402 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001403 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001404 .c = {
1405 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001406 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001407 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001408 CLK_INIT(pdm_clk.c),
1409 },
1410};
1411
1412static struct branch_clk pmem_clk = {
1413 .b = {
1414 .ctl_reg = PMEM_ACLK_CTL_REG,
1415 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001416 .hwcg_reg = PMEM_ACLK_CTL_REG,
1417 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001418 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1419 .halt_bit = 20,
1420 },
1421 .c = {
1422 .dbg_name = "pmem_clk",
1423 .ops = &clk_ops_branch,
1424 CLK_INIT(pmem_clk.c),
1425 },
1426};
1427
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001428#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001429 { \
1430 .freq_hz = f, \
1431 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001432 }
1433static struct clk_freq_tbl clk_tbl_prng[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001434 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001435 F_END
1436};
1437
1438static struct rcg_clk prng_clk = {
1439 .b = {
1440 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1441 .en_mask = BIT(10),
1442 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1443 .halt_check = HALT_VOTED,
1444 .halt_bit = 10,
1445 },
1446 .set_rate = set_rate_nop,
1447 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001448 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001449 .c = {
1450 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001451 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001452 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001453 CLK_INIT(prng_clk.c),
1454 },
1455};
1456
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001457#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001458 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001459 .b = { \
1460 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1461 .en_mask = BIT(9), \
1462 .reset_reg = SDCn_RESET_REG(n), \
1463 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001464 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001465 .halt_bit = h_b, \
1466 }, \
1467 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1468 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1469 .root_en_mask = BIT(11), \
1470 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001471 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001472 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001473 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001474 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001475 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001476 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001477 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001478 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001479 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001480 }, \
1481 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001482#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001483 { \
1484 .freq_hz = f, \
1485 .src_clk = &s##_clk.c, \
1486 .md_val = MD8(16, m, 0, n), \
1487 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001488 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001489static struct clk_freq_tbl clk_tbl_sdc[] = {
1490 F_SDC( 0, gnd, 1, 0, 0),
1491 F_SDC( 144000, pxo, 3, 2, 125),
1492 F_SDC( 400000, pll8, 4, 1, 240),
1493 F_SDC( 16000000, pll8, 4, 1, 6),
1494 F_SDC( 17070000, pll8, 1, 2, 45),
1495 F_SDC( 20210000, pll8, 1, 1, 19),
1496 F_SDC( 24000000, pll8, 4, 1, 4),
1497 F_SDC( 48000000, pll8, 4, 1, 2),
1498 F_SDC( 64000000, pll8, 3, 1, 2),
1499 F_SDC( 96000000, pll8, 4, 0, 0),
Subhash Jadavanibd238ba2011-11-24 15:12:39 +05301500 F_SDC(192000000, pll8, 2, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001501 F_END
1502};
1503
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001504static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1505static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1506static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1507static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1508static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001509
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001510#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001511 { \
1512 .freq_hz = f, \
1513 .src_clk = &s##_clk.c, \
1514 .md_val = MD16(m, n), \
1515 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001516 }
1517static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001518 F_TSIF_REF( 0, gnd, 1, 0, 0),
1519 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001520 F_END
1521};
1522
1523static struct rcg_clk tsif_ref_clk = {
1524 .b = {
1525 .ctl_reg = TSIF_REF_CLK_NS_REG,
1526 .en_mask = BIT(9),
1527 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1528 .halt_bit = 5,
1529 },
1530 .ns_reg = TSIF_REF_CLK_NS_REG,
1531 .md_reg = TSIF_REF_CLK_MD_REG,
1532 .root_en_mask = BIT(11),
1533 .ns_mask = (BM(31, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001534 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001535 .set_rate = set_rate_mnd,
1536 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001537 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001538 .c = {
1539 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001540 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001541 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001542 CLK_INIT(tsif_ref_clk.c),
1543 },
1544};
1545
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001546#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001547 { \
1548 .freq_hz = f, \
1549 .src_clk = &s##_clk.c, \
1550 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001551 }
1552static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001553 F_TSSC( 0, gnd),
1554 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001555 F_END
1556};
1557
1558static struct rcg_clk tssc_clk = {
1559 .b = {
1560 .ctl_reg = TSSC_CLK_CTL_REG,
1561 .en_mask = BIT(4),
1562 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1563 .halt_bit = 4,
1564 },
1565 .ns_reg = TSSC_CLK_CTL_REG,
1566 .ns_mask = BM(1, 0),
1567 .set_rate = set_rate_nop,
1568 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001569 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001570 .c = {
1571 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001572 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001573 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001574 CLK_INIT(tssc_clk.c),
1575 },
1576};
1577
Tianyi Gou41515e22011-09-01 19:37:43 -07001578#define CLK_USB_HS(name, n, h_b) \
1579 static struct rcg_clk name = { \
1580 .b = { \
1581 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1582 .en_mask = BIT(9), \
1583 .reset_reg = USB_HS##n##_RESET_REG, \
1584 .reset_mask = BIT(0), \
1585 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1586 .halt_bit = h_b, \
1587 }, \
1588 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1589 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1590 .root_en_mask = BIT(11), \
1591 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001592 .mnd_en_mask = BIT(8), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001593 .set_rate = set_rate_mnd, \
1594 .freq_tbl = clk_tbl_usb, \
1595 .current_freq = &rcg_dummy_freq, \
1596 .c = { \
1597 .dbg_name = #name, \
1598 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001599 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001600 CLK_INIT(name.c), \
1601 }, \
1602}
1603
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001604#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001605 { \
1606 .freq_hz = f, \
1607 .src_clk = &s##_clk.c, \
1608 .md_val = MD8(16, m, 0, n), \
1609 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001610 }
1611static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001612 F_USB( 0, gnd, 1, 0, 0),
1613 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001614 F_END
1615};
1616
Tianyi Gou41515e22011-09-01 19:37:43 -07001617CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1618CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1619CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001620
Stephen Boyd94625ef2011-07-12 17:06:01 -07001621static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001622 F_USB( 0, gnd, 1, 0, 0),
1623 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001624 F_END
1625};
1626
1627static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1628 .b = {
1629 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1630 .en_mask = BIT(9),
1631 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1632 .halt_bit = 26,
1633 },
1634 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1635 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1636 .root_en_mask = BIT(11),
1637 .ns_mask = (BM(23, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001638 .mnd_en_mask = BIT(8),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001639 .set_rate = set_rate_mnd,
1640 .freq_tbl = clk_tbl_usb_hsic,
1641 .current_freq = &rcg_dummy_freq,
1642 .c = {
1643 .dbg_name = "usb_hsic_xcvr_fs_clk",
1644 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001645 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001646 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1647 },
1648};
1649
1650static struct branch_clk usb_hsic_system_clk = {
1651 .b = {
1652 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1653 .en_mask = BIT(4),
1654 .reset_reg = USB_HSIC_RESET_REG,
1655 .reset_mask = BIT(0),
1656 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1657 .halt_bit = 24,
1658 },
1659 .parent = &usb_hsic_xcvr_fs_clk.c,
1660 .c = {
1661 .dbg_name = "usb_hsic_system_clk",
1662 .ops = &clk_ops_branch,
1663 CLK_INIT(usb_hsic_system_clk.c),
1664 },
1665};
1666
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001667#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001668 { \
1669 .freq_hz = f, \
1670 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001671 }
1672static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001673 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001674 F_END
1675};
1676
1677static struct rcg_clk usb_hsic_hsic_src_clk = {
1678 .b = {
1679 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1680 .halt_check = NOCHECK,
1681 },
1682 .root_en_mask = BIT(0),
1683 .set_rate = set_rate_nop,
1684 .freq_tbl = clk_tbl_usb2_hsic,
1685 .current_freq = &rcg_dummy_freq,
1686 .c = {
1687 .dbg_name = "usb_hsic_hsic_src_clk",
1688 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001689 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001690 CLK_INIT(usb_hsic_hsic_src_clk.c),
1691 },
1692};
1693
1694static struct branch_clk usb_hsic_hsic_clk = {
1695 .b = {
1696 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1697 .en_mask = BIT(0),
1698 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1699 .halt_bit = 19,
1700 },
1701 .parent = &usb_hsic_hsic_src_clk.c,
1702 .c = {
1703 .dbg_name = "usb_hsic_hsic_clk",
1704 .ops = &clk_ops_branch,
1705 CLK_INIT(usb_hsic_hsic_clk.c),
1706 },
1707};
1708
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001709#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001710 { \
1711 .freq_hz = f, \
1712 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001713 }
1714static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001715 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001716 F_END
1717};
1718
1719static struct rcg_clk usb_hsic_hsio_cal_clk = {
1720 .b = {
1721 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1722 .en_mask = BIT(0),
1723 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1724 .halt_bit = 23,
1725 },
1726 .set_rate = set_rate_nop,
1727 .freq_tbl = clk_tbl_usb_hsio_cal,
1728 .current_freq = &rcg_dummy_freq,
1729 .c = {
1730 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyda0e82ec2011-09-19 12:18:45 -07001731 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001732 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001733 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1734 },
1735};
1736
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001737static struct branch_clk usb_phy0_clk = {
1738 .b = {
1739 .reset_reg = USB_PHY0_RESET_REG,
1740 .reset_mask = BIT(0),
1741 },
1742 .c = {
1743 .dbg_name = "usb_phy0_clk",
1744 .ops = &clk_ops_reset,
1745 CLK_INIT(usb_phy0_clk.c),
1746 },
1747};
1748
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001749#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001750 struct rcg_clk i##_clk = { \
1751 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1752 .b = { \
1753 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1754 .halt_check = NOCHECK, \
1755 }, \
1756 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1757 .root_en_mask = BIT(11), \
1758 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001759 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001760 .set_rate = set_rate_mnd, \
1761 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001762 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001763 .c = { \
1764 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001765 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001766 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001767 CLK_INIT(i##_clk.c), \
1768 }, \
1769 }
1770
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001771static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001772static struct branch_clk usb_fs1_xcvr_clk = {
1773 .b = {
1774 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1775 .en_mask = BIT(9),
1776 .reset_reg = USB_FSn_RESET_REG(1),
1777 .reset_mask = BIT(1),
1778 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1779 .halt_bit = 15,
1780 },
1781 .parent = &usb_fs1_src_clk.c,
1782 .c = {
1783 .dbg_name = "usb_fs1_xcvr_clk",
1784 .ops = &clk_ops_branch,
1785 CLK_INIT(usb_fs1_xcvr_clk.c),
1786 },
1787};
1788
1789static struct branch_clk usb_fs1_sys_clk = {
1790 .b = {
1791 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1792 .en_mask = BIT(4),
1793 .reset_reg = USB_FSn_RESET_REG(1),
1794 .reset_mask = BIT(0),
1795 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1796 .halt_bit = 16,
1797 },
1798 .parent = &usb_fs1_src_clk.c,
1799 .c = {
1800 .dbg_name = "usb_fs1_sys_clk",
1801 .ops = &clk_ops_branch,
1802 CLK_INIT(usb_fs1_sys_clk.c),
1803 },
1804};
1805
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001806static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001807static struct branch_clk usb_fs2_xcvr_clk = {
1808 .b = {
1809 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1810 .en_mask = BIT(9),
1811 .reset_reg = USB_FSn_RESET_REG(2),
1812 .reset_mask = BIT(1),
1813 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1814 .halt_bit = 12,
1815 },
1816 .parent = &usb_fs2_src_clk.c,
1817 .c = {
1818 .dbg_name = "usb_fs2_xcvr_clk",
1819 .ops = &clk_ops_branch,
1820 CLK_INIT(usb_fs2_xcvr_clk.c),
1821 },
1822};
1823
1824static struct branch_clk usb_fs2_sys_clk = {
1825 .b = {
1826 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1827 .en_mask = BIT(4),
1828 .reset_reg = USB_FSn_RESET_REG(2),
1829 .reset_mask = BIT(0),
1830 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1831 .halt_bit = 13,
1832 },
1833 .parent = &usb_fs2_src_clk.c,
1834 .c = {
1835 .dbg_name = "usb_fs2_sys_clk",
1836 .ops = &clk_ops_branch,
1837 CLK_INIT(usb_fs2_sys_clk.c),
1838 },
1839};
1840
1841/* Fast Peripheral Bus Clocks */
1842static struct branch_clk ce1_core_clk = {
1843 .b = {
1844 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1845 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001846 .hwcg_reg = CE1_CORE_CLK_CTL_REG,
1847 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001848 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1849 .halt_bit = 27,
1850 },
1851 .c = {
1852 .dbg_name = "ce1_core_clk",
1853 .ops = &clk_ops_branch,
1854 CLK_INIT(ce1_core_clk.c),
1855 },
1856};
Tianyi Gou41515e22011-09-01 19:37:43 -07001857
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001858static struct branch_clk ce1_p_clk = {
1859 .b = {
1860 .ctl_reg = CE1_HCLK_CTL_REG,
1861 .en_mask = BIT(4),
1862 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1863 .halt_bit = 1,
1864 },
1865 .c = {
1866 .dbg_name = "ce1_p_clk",
1867 .ops = &clk_ops_branch,
1868 CLK_INIT(ce1_p_clk.c),
1869 },
1870};
1871
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001872#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07001873 { \
1874 .freq_hz = f, \
1875 .src_clk = &s##_clk.c, \
1876 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001877 }
1878
1879static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001880 F_CE3( 0, gnd, 1),
1881 F_CE3( 48000000, pll8, 8),
1882 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07001883 F_END
1884};
1885
1886static struct rcg_clk ce3_src_clk = {
1887 .b = {
1888 .ctl_reg = CE3_CLK_SRC_NS_REG,
1889 .halt_check = NOCHECK,
1890 },
1891 .ns_reg = CE3_CLK_SRC_NS_REG,
1892 .root_en_mask = BIT(7),
1893 .ns_mask = BM(6, 0),
1894 .set_rate = set_rate_nop,
1895 .freq_tbl = clk_tbl_ce3,
1896 .current_freq = &rcg_dummy_freq,
1897 .c = {
1898 .dbg_name = "ce3_src_clk",
1899 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001900 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07001901 CLK_INIT(ce3_src_clk.c),
1902 },
1903};
1904
1905static struct branch_clk ce3_core_clk = {
1906 .b = {
1907 .ctl_reg = CE3_CORE_CLK_CTL_REG,
1908 .en_mask = BIT(4),
1909 .reset_reg = CE3_CORE_CLK_CTL_REG,
1910 .reset_mask = BIT(7),
1911 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1912 .halt_bit = 5,
1913 },
1914 .parent = &ce3_src_clk.c,
1915 .c = {
1916 .dbg_name = "ce3_core_clk",
1917 .ops = &clk_ops_branch,
1918 CLK_INIT(ce3_core_clk.c),
1919 }
1920};
1921
1922static struct branch_clk ce3_p_clk = {
1923 .b = {
1924 .ctl_reg = CE3_HCLK_CTL_REG,
1925 .en_mask = BIT(4),
1926 .reset_reg = CE3_HCLK_CTL_REG,
1927 .reset_mask = BIT(7),
1928 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1929 .halt_bit = 16,
1930 },
1931 .parent = &ce3_src_clk.c,
1932 .c = {
1933 .dbg_name = "ce3_p_clk",
1934 .ops = &clk_ops_branch,
1935 CLK_INIT(ce3_p_clk.c),
1936 }
1937};
1938
1939static struct branch_clk sata_phy_ref_clk = {
1940 .b = {
1941 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
1942 .en_mask = BIT(4),
1943 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1944 .halt_bit = 24,
1945 },
1946 .parent = &pxo_clk.c,
1947 .c = {
1948 .dbg_name = "sata_phy_ref_clk",
1949 .ops = &clk_ops_branch,
1950 CLK_INIT(sata_phy_ref_clk.c),
1951 },
1952};
1953
1954static struct branch_clk pcie_p_clk = {
1955 .b = {
1956 .ctl_reg = PCIE_HCLK_CTL_REG,
1957 .en_mask = BIT(4),
1958 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1959 .halt_bit = 8,
1960 },
1961 .c = {
1962 .dbg_name = "pcie_p_clk",
1963 .ops = &clk_ops_branch,
1964 CLK_INIT(pcie_p_clk.c),
1965 },
1966};
1967
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001968static struct branch_clk dma_bam_p_clk = {
1969 .b = {
1970 .ctl_reg = DMA_BAM_HCLK_CTL,
1971 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001972 .hwcg_reg = DMA_BAM_HCLK_CTL,
1973 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001974 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1975 .halt_bit = 12,
1976 },
1977 .c = {
1978 .dbg_name = "dma_bam_p_clk",
1979 .ops = &clk_ops_branch,
1980 CLK_INIT(dma_bam_p_clk.c),
1981 },
1982};
1983
1984static struct branch_clk gsbi1_p_clk = {
1985 .b = {
1986 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
1987 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001988 .hwcg_reg = GSBIn_HCLK_CTL_REG(1),
1989 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001990 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1991 .halt_bit = 11,
1992 },
1993 .c = {
1994 .dbg_name = "gsbi1_p_clk",
1995 .ops = &clk_ops_branch,
1996 CLK_INIT(gsbi1_p_clk.c),
1997 },
1998};
1999
2000static struct branch_clk gsbi2_p_clk = {
2001 .b = {
2002 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2003 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002004 .hwcg_reg = GSBIn_HCLK_CTL_REG(2),
2005 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002006 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2007 .halt_bit = 7,
2008 },
2009 .c = {
2010 .dbg_name = "gsbi2_p_clk",
2011 .ops = &clk_ops_branch,
2012 CLK_INIT(gsbi2_p_clk.c),
2013 },
2014};
2015
2016static struct branch_clk gsbi3_p_clk = {
2017 .b = {
2018 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2019 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002020 .hwcg_reg = GSBIn_HCLK_CTL_REG(3),
2021 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002022 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2023 .halt_bit = 3,
2024 },
2025 .c = {
2026 .dbg_name = "gsbi3_p_clk",
2027 .ops = &clk_ops_branch,
2028 CLK_INIT(gsbi3_p_clk.c),
2029 },
2030};
2031
2032static struct branch_clk gsbi4_p_clk = {
2033 .b = {
2034 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2035 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002036 .hwcg_reg = GSBIn_HCLK_CTL_REG(4),
2037 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002038 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2039 .halt_bit = 27,
2040 },
2041 .c = {
2042 .dbg_name = "gsbi4_p_clk",
2043 .ops = &clk_ops_branch,
2044 CLK_INIT(gsbi4_p_clk.c),
2045 },
2046};
2047
2048static struct branch_clk gsbi5_p_clk = {
2049 .b = {
2050 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2051 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002052 .hwcg_reg = GSBIn_HCLK_CTL_REG(5),
2053 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002054 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2055 .halt_bit = 23,
2056 },
2057 .c = {
2058 .dbg_name = "gsbi5_p_clk",
2059 .ops = &clk_ops_branch,
2060 CLK_INIT(gsbi5_p_clk.c),
2061 },
2062};
2063
2064static struct branch_clk gsbi6_p_clk = {
2065 .b = {
2066 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2067 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002068 .hwcg_reg = GSBIn_HCLK_CTL_REG(6),
2069 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002070 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2071 .halt_bit = 19,
2072 },
2073 .c = {
2074 .dbg_name = "gsbi6_p_clk",
2075 .ops = &clk_ops_branch,
2076 CLK_INIT(gsbi6_p_clk.c),
2077 },
2078};
2079
2080static struct branch_clk gsbi7_p_clk = {
2081 .b = {
2082 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2083 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002084 .hwcg_reg = GSBIn_HCLK_CTL_REG(7),
2085 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002086 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2087 .halt_bit = 15,
2088 },
2089 .c = {
2090 .dbg_name = "gsbi7_p_clk",
2091 .ops = &clk_ops_branch,
2092 CLK_INIT(gsbi7_p_clk.c),
2093 },
2094};
2095
2096static struct branch_clk gsbi8_p_clk = {
2097 .b = {
2098 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2099 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002100 .hwcg_reg = GSBIn_HCLK_CTL_REG(8),
2101 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002102 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2103 .halt_bit = 11,
2104 },
2105 .c = {
2106 .dbg_name = "gsbi8_p_clk",
2107 .ops = &clk_ops_branch,
2108 CLK_INIT(gsbi8_p_clk.c),
2109 },
2110};
2111
2112static struct branch_clk gsbi9_p_clk = {
2113 .b = {
2114 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2115 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002116 .hwcg_reg = GSBIn_HCLK_CTL_REG(9),
2117 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002118 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2119 .halt_bit = 7,
2120 },
2121 .c = {
2122 .dbg_name = "gsbi9_p_clk",
2123 .ops = &clk_ops_branch,
2124 CLK_INIT(gsbi9_p_clk.c),
2125 },
2126};
2127
2128static struct branch_clk gsbi10_p_clk = {
2129 .b = {
2130 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2131 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002132 .hwcg_reg = GSBIn_HCLK_CTL_REG(10),
2133 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002134 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2135 .halt_bit = 3,
2136 },
2137 .c = {
2138 .dbg_name = "gsbi10_p_clk",
2139 .ops = &clk_ops_branch,
2140 CLK_INIT(gsbi10_p_clk.c),
2141 },
2142};
2143
2144static struct branch_clk gsbi11_p_clk = {
2145 .b = {
2146 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2147 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002148 .hwcg_reg = GSBIn_HCLK_CTL_REG(11),
2149 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002150 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2151 .halt_bit = 18,
2152 },
2153 .c = {
2154 .dbg_name = "gsbi11_p_clk",
2155 .ops = &clk_ops_branch,
2156 CLK_INIT(gsbi11_p_clk.c),
2157 },
2158};
2159
2160static struct branch_clk gsbi12_p_clk = {
2161 .b = {
2162 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2163 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002164 .hwcg_reg = GSBIn_HCLK_CTL_REG(12),
2165 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002166 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2167 .halt_bit = 14,
2168 },
2169 .c = {
2170 .dbg_name = "gsbi12_p_clk",
2171 .ops = &clk_ops_branch,
2172 CLK_INIT(gsbi12_p_clk.c),
2173 },
2174};
2175
Tianyi Gou41515e22011-09-01 19:37:43 -07002176static struct branch_clk sata_phy_cfg_clk = {
2177 .b = {
2178 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2179 .en_mask = BIT(4),
2180 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2181 .halt_bit = 12,
2182 },
2183 .c = {
2184 .dbg_name = "sata_phy_cfg_clk",
2185 .ops = &clk_ops_branch,
2186 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002187 },
2188};
2189
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002190static struct branch_clk tsif_p_clk = {
2191 .b = {
2192 .ctl_reg = TSIF_HCLK_CTL_REG,
2193 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002194 .hwcg_reg = TSIF_HCLK_CTL_REG,
2195 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002196 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2197 .halt_bit = 7,
2198 },
2199 .c = {
2200 .dbg_name = "tsif_p_clk",
2201 .ops = &clk_ops_branch,
2202 CLK_INIT(tsif_p_clk.c),
2203 },
2204};
2205
2206static struct branch_clk usb_fs1_p_clk = {
2207 .b = {
2208 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2209 .en_mask = BIT(4),
2210 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2211 .halt_bit = 17,
2212 },
2213 .c = {
2214 .dbg_name = "usb_fs1_p_clk",
2215 .ops = &clk_ops_branch,
2216 CLK_INIT(usb_fs1_p_clk.c),
2217 },
2218};
2219
2220static struct branch_clk usb_fs2_p_clk = {
2221 .b = {
2222 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2223 .en_mask = BIT(4),
2224 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2225 .halt_bit = 14,
2226 },
2227 .c = {
2228 .dbg_name = "usb_fs2_p_clk",
2229 .ops = &clk_ops_branch,
2230 CLK_INIT(usb_fs2_p_clk.c),
2231 },
2232};
2233
2234static struct branch_clk usb_hs1_p_clk = {
2235 .b = {
2236 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2237 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002238 .hwcg_reg = USB_HS1_HCLK_CTL_REG,
2239 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002240 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2241 .halt_bit = 1,
2242 },
2243 .c = {
2244 .dbg_name = "usb_hs1_p_clk",
2245 .ops = &clk_ops_branch,
2246 CLK_INIT(usb_hs1_p_clk.c),
2247 },
2248};
2249
Tianyi Gou41515e22011-09-01 19:37:43 -07002250static struct branch_clk usb_hs3_p_clk = {
2251 .b = {
2252 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2253 .en_mask = BIT(4),
2254 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2255 .halt_bit = 31,
2256 },
2257 .c = {
2258 .dbg_name = "usb_hs3_p_clk",
2259 .ops = &clk_ops_branch,
2260 CLK_INIT(usb_hs3_p_clk.c),
2261 },
2262};
2263
2264static struct branch_clk usb_hs4_p_clk = {
2265 .b = {
2266 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2267 .en_mask = BIT(4),
2268 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2269 .halt_bit = 7,
2270 },
2271 .c = {
2272 .dbg_name = "usb_hs4_p_clk",
2273 .ops = &clk_ops_branch,
2274 CLK_INIT(usb_hs4_p_clk.c),
2275 },
2276};
2277
Stephen Boyd94625ef2011-07-12 17:06:01 -07002278static struct branch_clk usb_hsic_p_clk = {
2279 .b = {
2280 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2281 .en_mask = BIT(4),
2282 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2283 .halt_bit = 28,
2284 },
2285 .c = {
2286 .dbg_name = "usb_hsic_p_clk",
2287 .ops = &clk_ops_branch,
2288 CLK_INIT(usb_hsic_p_clk.c),
2289 },
2290};
2291
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002292static struct branch_clk sdc1_p_clk = {
2293 .b = {
2294 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2295 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002296 .hwcg_reg = SDCn_HCLK_CTL_REG(1),
2297 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002298 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2299 .halt_bit = 11,
2300 },
2301 .c = {
2302 .dbg_name = "sdc1_p_clk",
2303 .ops = &clk_ops_branch,
2304 CLK_INIT(sdc1_p_clk.c),
2305 },
2306};
2307
2308static struct branch_clk sdc2_p_clk = {
2309 .b = {
2310 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2311 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002312 .hwcg_reg = SDCn_HCLK_CTL_REG(2),
2313 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002314 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2315 .halt_bit = 10,
2316 },
2317 .c = {
2318 .dbg_name = "sdc2_p_clk",
2319 .ops = &clk_ops_branch,
2320 CLK_INIT(sdc2_p_clk.c),
2321 },
2322};
2323
2324static struct branch_clk sdc3_p_clk = {
2325 .b = {
2326 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2327 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002328 .hwcg_reg = SDCn_HCLK_CTL_REG(3),
2329 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002330 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2331 .halt_bit = 9,
2332 },
2333 .c = {
2334 .dbg_name = "sdc3_p_clk",
2335 .ops = &clk_ops_branch,
2336 CLK_INIT(sdc3_p_clk.c),
2337 },
2338};
2339
2340static struct branch_clk sdc4_p_clk = {
2341 .b = {
2342 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2343 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002344 .hwcg_reg = SDCn_HCLK_CTL_REG(4),
2345 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002346 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2347 .halt_bit = 8,
2348 },
2349 .c = {
2350 .dbg_name = "sdc4_p_clk",
2351 .ops = &clk_ops_branch,
2352 CLK_INIT(sdc4_p_clk.c),
2353 },
2354};
2355
2356static struct branch_clk sdc5_p_clk = {
2357 .b = {
2358 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2359 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002360 .hwcg_reg = SDCn_HCLK_CTL_REG(5),
2361 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002362 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2363 .halt_bit = 7,
2364 },
2365 .c = {
2366 .dbg_name = "sdc5_p_clk",
2367 .ops = &clk_ops_branch,
2368 CLK_INIT(sdc5_p_clk.c),
2369 },
2370};
2371
2372/* HW-Voteable Clocks */
2373static struct branch_clk adm0_clk = {
2374 .b = {
2375 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2376 .en_mask = BIT(2),
2377 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2378 .halt_check = HALT_VOTED,
2379 .halt_bit = 14,
2380 },
2381 .c = {
2382 .dbg_name = "adm0_clk",
2383 .ops = &clk_ops_branch,
2384 CLK_INIT(adm0_clk.c),
2385 },
2386};
2387
2388static struct branch_clk adm0_p_clk = {
2389 .b = {
2390 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2391 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002392 .hwcg_reg = ADM0_PBUS_CLK_CTL_REG,
2393 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002394 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2395 .halt_check = HALT_VOTED,
2396 .halt_bit = 13,
2397 },
2398 .c = {
2399 .dbg_name = "adm0_p_clk",
2400 .ops = &clk_ops_branch,
2401 CLK_INIT(adm0_p_clk.c),
2402 },
2403};
2404
2405static struct branch_clk pmic_arb0_p_clk = {
2406 .b = {
2407 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2408 .en_mask = BIT(8),
2409 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2410 .halt_check = HALT_VOTED,
2411 .halt_bit = 22,
2412 },
2413 .c = {
2414 .dbg_name = "pmic_arb0_p_clk",
2415 .ops = &clk_ops_branch,
2416 CLK_INIT(pmic_arb0_p_clk.c),
2417 },
2418};
2419
2420static struct branch_clk pmic_arb1_p_clk = {
2421 .b = {
2422 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2423 .en_mask = BIT(9),
2424 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2425 .halt_check = HALT_VOTED,
2426 .halt_bit = 21,
2427 },
2428 .c = {
2429 .dbg_name = "pmic_arb1_p_clk",
2430 .ops = &clk_ops_branch,
2431 CLK_INIT(pmic_arb1_p_clk.c),
2432 },
2433};
2434
2435static struct branch_clk pmic_ssbi2_clk = {
2436 .b = {
2437 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2438 .en_mask = BIT(7),
2439 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2440 .halt_check = HALT_VOTED,
2441 .halt_bit = 23,
2442 },
2443 .c = {
2444 .dbg_name = "pmic_ssbi2_clk",
2445 .ops = &clk_ops_branch,
2446 CLK_INIT(pmic_ssbi2_clk.c),
2447 },
2448};
2449
2450static struct branch_clk rpm_msg_ram_p_clk = {
2451 .b = {
2452 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2453 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002454 .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG,
2455 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002456 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2457 .halt_check = HALT_VOTED,
2458 .halt_bit = 12,
2459 },
2460 .c = {
2461 .dbg_name = "rpm_msg_ram_p_clk",
2462 .ops = &clk_ops_branch,
2463 CLK_INIT(rpm_msg_ram_p_clk.c),
2464 },
2465};
2466
2467/*
2468 * Multimedia Clocks
2469 */
2470
2471static struct branch_clk amp_clk = {
2472 .b = {
2473 .reset_reg = SW_RESET_CORE_REG,
2474 .reset_mask = BIT(20),
2475 },
2476 .c = {
2477 .dbg_name = "amp_clk",
2478 .ops = &clk_ops_reset,
2479 CLK_INIT(amp_clk.c),
2480 },
2481};
2482
Stephen Boyd94625ef2011-07-12 17:06:01 -07002483#define CLK_CAM(name, n, hb) \
2484 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002485 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002486 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002487 .en_mask = BIT(0), \
2488 .halt_reg = DBG_BUS_VEC_I_REG, \
2489 .halt_bit = hb, \
2490 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002491 .ns_reg = CAMCLK##n##_NS_REG, \
2492 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002493 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002494 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Matt Wagantall07c45472012-02-10 23:27:24 -08002495 .mnd_en_mask = BIT(5), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002496 .ctl_mask = BM(7, 6), \
2497 .set_rate = set_rate_mnd_8, \
2498 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002499 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002500 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002501 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002502 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002503 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002504 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002505 }, \
2506 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002507#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002508 { \
2509 .freq_hz = f, \
2510 .src_clk = &s##_clk.c, \
2511 .md_val = MD8(8, m, 0, n), \
2512 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2513 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002514 }
2515static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002516 F_CAM( 0, gnd, 1, 0, 0),
2517 F_CAM( 6000000, pll8, 4, 1, 16),
2518 F_CAM( 8000000, pll8, 4, 1, 12),
2519 F_CAM( 12000000, pll8, 4, 1, 8),
2520 F_CAM( 16000000, pll8, 4, 1, 6),
2521 F_CAM( 19200000, pll8, 4, 1, 5),
2522 F_CAM( 24000000, pll8, 4, 1, 4),
2523 F_CAM( 32000000, pll8, 4, 1, 3),
2524 F_CAM( 48000000, pll8, 4, 1, 2),
2525 F_CAM( 64000000, pll8, 3, 1, 2),
2526 F_CAM( 96000000, pll8, 4, 0, 0),
2527 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002528 F_END
2529};
2530
Stephen Boyd94625ef2011-07-12 17:06:01 -07002531static CLK_CAM(cam0_clk, 0, 15);
2532static CLK_CAM(cam1_clk, 1, 16);
2533static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002534
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002535#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002536 { \
2537 .freq_hz = f, \
2538 .src_clk = &s##_clk.c, \
2539 .md_val = MD8(8, m, 0, n), \
2540 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2541 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002542 }
2543static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002544 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002545 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002546 F_CSI( 85330000, pll8, 1, 2, 9),
2547 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002548 F_END
2549};
2550
2551static struct rcg_clk csi0_src_clk = {
2552 .ns_reg = CSI0_NS_REG,
2553 .b = {
2554 .ctl_reg = CSI0_CC_REG,
2555 .halt_check = NOCHECK,
2556 },
2557 .md_reg = CSI0_MD_REG,
2558 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002559 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002560 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002561 .ctl_mask = BM(7, 6),
2562 .set_rate = set_rate_mnd,
2563 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002564 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002565 .c = {
2566 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002567 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002568 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002569 CLK_INIT(csi0_src_clk.c),
2570 },
2571};
2572
2573static struct branch_clk csi0_clk = {
2574 .b = {
2575 .ctl_reg = CSI0_CC_REG,
2576 .en_mask = BIT(0),
2577 .reset_reg = SW_RESET_CORE_REG,
2578 .reset_mask = BIT(8),
2579 .halt_reg = DBG_BUS_VEC_B_REG,
2580 .halt_bit = 13,
2581 },
2582 .parent = &csi0_src_clk.c,
2583 .c = {
2584 .dbg_name = "csi0_clk",
2585 .ops = &clk_ops_branch,
2586 CLK_INIT(csi0_clk.c),
2587 },
2588};
2589
2590static struct branch_clk csi0_phy_clk = {
2591 .b = {
2592 .ctl_reg = CSI0_CC_REG,
2593 .en_mask = BIT(8),
2594 .reset_reg = SW_RESET_CORE_REG,
2595 .reset_mask = BIT(29),
2596 .halt_reg = DBG_BUS_VEC_I_REG,
2597 .halt_bit = 9,
2598 },
2599 .parent = &csi0_src_clk.c,
2600 .c = {
2601 .dbg_name = "csi0_phy_clk",
2602 .ops = &clk_ops_branch,
2603 CLK_INIT(csi0_phy_clk.c),
2604 },
2605};
2606
2607static struct rcg_clk csi1_src_clk = {
2608 .ns_reg = CSI1_NS_REG,
2609 .b = {
2610 .ctl_reg = CSI1_CC_REG,
2611 .halt_check = NOCHECK,
2612 },
2613 .md_reg = CSI1_MD_REG,
2614 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002615 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002616 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002617 .ctl_mask = BM(7, 6),
2618 .set_rate = set_rate_mnd,
2619 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002620 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002621 .c = {
2622 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002623 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002624 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002625 CLK_INIT(csi1_src_clk.c),
2626 },
2627};
2628
2629static struct branch_clk csi1_clk = {
2630 .b = {
2631 .ctl_reg = CSI1_CC_REG,
2632 .en_mask = BIT(0),
2633 .reset_reg = SW_RESET_CORE_REG,
2634 .reset_mask = BIT(18),
2635 .halt_reg = DBG_BUS_VEC_B_REG,
2636 .halt_bit = 14,
2637 },
2638 .parent = &csi1_src_clk.c,
2639 .c = {
2640 .dbg_name = "csi1_clk",
2641 .ops = &clk_ops_branch,
2642 CLK_INIT(csi1_clk.c),
2643 },
2644};
2645
2646static struct branch_clk csi1_phy_clk = {
2647 .b = {
2648 .ctl_reg = CSI1_CC_REG,
2649 .en_mask = BIT(8),
2650 .reset_reg = SW_RESET_CORE_REG,
2651 .reset_mask = BIT(28),
2652 .halt_reg = DBG_BUS_VEC_I_REG,
2653 .halt_bit = 10,
2654 },
2655 .parent = &csi1_src_clk.c,
2656 .c = {
2657 .dbg_name = "csi1_phy_clk",
2658 .ops = &clk_ops_branch,
2659 CLK_INIT(csi1_phy_clk.c),
2660 },
2661};
2662
Stephen Boyd94625ef2011-07-12 17:06:01 -07002663static struct rcg_clk csi2_src_clk = {
2664 .ns_reg = CSI2_NS_REG,
2665 .b = {
2666 .ctl_reg = CSI2_CC_REG,
2667 .halt_check = NOCHECK,
2668 },
2669 .md_reg = CSI2_MD_REG,
2670 .root_en_mask = BIT(2),
2671 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002672 .mnd_en_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002673 .ctl_mask = BM(7, 6),
2674 .set_rate = set_rate_mnd,
2675 .freq_tbl = clk_tbl_csi,
2676 .current_freq = &rcg_dummy_freq,
2677 .c = {
2678 .dbg_name = "csi2_src_clk",
2679 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002680 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002681 CLK_INIT(csi2_src_clk.c),
2682 },
2683};
2684
2685static struct branch_clk csi2_clk = {
2686 .b = {
2687 .ctl_reg = CSI2_CC_REG,
2688 .en_mask = BIT(0),
2689 .reset_reg = SW_RESET_CORE2_REG,
2690 .reset_mask = BIT(2),
2691 .halt_reg = DBG_BUS_VEC_B_REG,
2692 .halt_bit = 29,
2693 },
2694 .parent = &csi2_src_clk.c,
2695 .c = {
2696 .dbg_name = "csi2_clk",
2697 .ops = &clk_ops_branch,
2698 CLK_INIT(csi2_clk.c),
2699 },
2700};
2701
2702static struct branch_clk csi2_phy_clk = {
2703 .b = {
2704 .ctl_reg = CSI2_CC_REG,
2705 .en_mask = BIT(8),
2706 .reset_reg = SW_RESET_CORE_REG,
2707 .reset_mask = BIT(31),
2708 .halt_reg = DBG_BUS_VEC_I_REG,
2709 .halt_bit = 29,
2710 },
2711 .parent = &csi2_src_clk.c,
2712 .c = {
2713 .dbg_name = "csi2_phy_clk",
2714 .ops = &clk_ops_branch,
2715 CLK_INIT(csi2_phy_clk.c),
2716 },
2717};
2718
Stephen Boyd092fd182011-10-21 15:56:30 -07002719static struct clk *pix_rdi_mux_map[] = {
2720 [0] = &csi0_clk.c,
2721 [1] = &csi1_clk.c,
2722 [2] = &csi2_clk.c,
2723 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002724};
2725
Stephen Boyd092fd182011-10-21 15:56:30 -07002726struct pix_rdi_clk {
2727 bool enabled;
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002728 unsigned long cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002729
2730 void __iomem *const s_reg;
2731 u32 s_mask;
2732
2733 void __iomem *const s2_reg;
2734 u32 s2_mask;
2735
2736 struct branch b;
2737 struct clk c;
2738};
2739
2740static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk)
2741{
2742 return container_of(clk, struct pix_rdi_clk, c);
2743}
2744
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002745static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate)
Stephen Boyd092fd182011-10-21 15:56:30 -07002746{
2747 int ret, i;
2748 u32 reg;
2749 unsigned long flags;
2750 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2751 struct clk **mux_map = pix_rdi_mux_map;
2752
2753 /*
2754 * These clocks select three inputs via two muxes. One mux selects
2755 * between csi0 and csi1 and the second mux selects between that mux's
2756 * output and csi2. The source and destination selections for each
2757 * mux must be clocking for the switch to succeed so just turn on
2758 * all three sources because it's easier than figuring out what source
2759 * needs to be on at what time.
2760 */
2761 for (i = 0; mux_map[i]; i++) {
2762 ret = clk_enable(mux_map[i]);
2763 if (ret)
2764 goto err;
2765 }
2766 if (rate >= i) {
2767 ret = -EINVAL;
2768 goto err;
2769 }
2770 /* Keep the new source on when switching inputs of an enabled clock */
2771 if (clk->enabled) {
2772 clk_disable(mux_map[clk->cur_rate]);
2773 clk_enable(mux_map[rate]);
2774 }
2775 spin_lock_irqsave(&local_clock_reg_lock, flags);
2776 reg = readl_relaxed(clk->s2_reg);
2777 reg &= ~clk->s2_mask;
2778 reg |= rate == 2 ? clk->s2_mask : 0;
2779 writel_relaxed(reg, clk->s2_reg);
2780 /*
2781 * Wait at least 6 cycles of slowest clock
2782 * for the glitch-free MUX to fully switch sources.
2783 */
2784 mb();
2785 udelay(1);
2786 reg = readl_relaxed(clk->s_reg);
2787 reg &= ~clk->s_mask;
2788 reg |= rate == 1 ? clk->s_mask : 0;
2789 writel_relaxed(reg, clk->s_reg);
2790 /*
2791 * Wait at least 6 cycles of slowest clock
2792 * for the glitch-free MUX to fully switch sources.
2793 */
2794 mb();
2795 udelay(1);
2796 clk->cur_rate = rate;
2797 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2798err:
2799 for (i--; i >= 0; i--)
2800 clk_disable(mux_map[i]);
2801
2802 return 0;
2803}
2804
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002805static unsigned long pix_rdi_clk_get_rate(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002806{
2807 return to_pix_rdi_clk(c)->cur_rate;
2808}
2809
2810static int pix_rdi_clk_enable(struct clk *c)
2811{
2812 unsigned long flags;
2813 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2814
2815 spin_lock_irqsave(&local_clock_reg_lock, flags);
2816 __branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
2817 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2818 clk->enabled = true;
2819
2820 return 0;
2821}
2822
2823static void pix_rdi_clk_disable(struct clk *c)
2824{
2825 unsigned long flags;
2826 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2827
2828 spin_lock_irqsave(&local_clock_reg_lock, flags);
2829 __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
2830 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2831 clk->enabled = false;
2832}
2833
2834static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action)
2835{
2836 return branch_reset(&to_pix_rdi_clk(clk)->b, action);
2837}
2838
2839static struct clk *pix_rdi_clk_get_parent(struct clk *c)
2840{
2841 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2842
2843 return pix_rdi_mux_map[clk->cur_rate];
2844}
2845
2846static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
2847{
2848 if (pix_rdi_mux_map[n])
2849 return n;
2850 return -ENXIO;
2851}
2852
2853static int pix_rdi_clk_handoff(struct clk *c)
2854{
2855 u32 reg;
2856 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2857
2858 reg = readl_relaxed(clk->s_reg);
2859 clk->cur_rate = reg & clk->s_mask ? 1 : 0;
2860 reg = readl_relaxed(clk->s2_reg);
2861 clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate;
2862 return 0;
2863}
2864
2865static struct clk_ops clk_ops_pix_rdi_8960 = {
2866 .enable = pix_rdi_clk_enable,
2867 .disable = pix_rdi_clk_disable,
2868 .auto_off = pix_rdi_clk_disable,
2869 .handoff = pix_rdi_clk_handoff,
2870 .set_rate = pix_rdi_clk_set_rate,
2871 .get_rate = pix_rdi_clk_get_rate,
2872 .list_rate = pix_rdi_clk_list_rate,
2873 .reset = pix_rdi_clk_reset,
2874 .is_local = local_clk_is_local,
2875 .get_parent = pix_rdi_clk_get_parent,
2876};
2877
2878static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002879 .b = {
2880 .ctl_reg = MISC_CC_REG,
2881 .en_mask = BIT(26),
2882 .halt_check = DELAY,
2883 .reset_reg = SW_RESET_CORE_REG,
2884 .reset_mask = BIT(26),
2885 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002886 .s_reg = MISC_CC_REG,
2887 .s_mask = BIT(25),
2888 .s2_reg = MISC_CC3_REG,
2889 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002890 .c = {
2891 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002892 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002893 CLK_INIT(csi_pix_clk.c),
2894 },
2895};
2896
Stephen Boyd092fd182011-10-21 15:56:30 -07002897static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002898 .b = {
2899 .ctl_reg = MISC_CC3_REG,
2900 .en_mask = BIT(10),
2901 .halt_check = DELAY,
2902 .reset_reg = SW_RESET_CORE_REG,
2903 .reset_mask = BIT(30),
2904 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002905 .s_reg = MISC_CC3_REG,
2906 .s_mask = BIT(8),
2907 .s2_reg = MISC_CC3_REG,
2908 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002909 .c = {
2910 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002911 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002912 CLK_INIT(csi_pix1_clk.c),
2913 },
2914};
2915
Stephen Boyd092fd182011-10-21 15:56:30 -07002916static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002917 .b = {
2918 .ctl_reg = MISC_CC_REG,
2919 .en_mask = BIT(13),
2920 .halt_check = DELAY,
2921 .reset_reg = SW_RESET_CORE_REG,
2922 .reset_mask = BIT(27),
2923 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002924 .s_reg = MISC_CC_REG,
2925 .s_mask = BIT(12),
2926 .s2_reg = MISC_CC3_REG,
2927 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002928 .c = {
2929 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002930 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002931 CLK_INIT(csi_rdi_clk.c),
2932 },
2933};
2934
Stephen Boyd092fd182011-10-21 15:56:30 -07002935static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002936 .b = {
2937 .ctl_reg = MISC_CC3_REG,
2938 .en_mask = BIT(2),
2939 .halt_check = DELAY,
2940 .reset_reg = SW_RESET_CORE2_REG,
2941 .reset_mask = BIT(1),
2942 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002943 .s_reg = MISC_CC3_REG,
2944 .s_mask = BIT(0),
2945 .s2_reg = MISC_CC3_REG,
2946 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002947 .c = {
2948 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002949 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002950 CLK_INIT(csi_rdi1_clk.c),
2951 },
2952};
2953
Stephen Boyd092fd182011-10-21 15:56:30 -07002954static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002955 .b = {
2956 .ctl_reg = MISC_CC3_REG,
2957 .en_mask = BIT(6),
2958 .halt_check = DELAY,
2959 .reset_reg = SW_RESET_CORE2_REG,
2960 .reset_mask = BIT(0),
2961 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002962 .s_reg = MISC_CC3_REG,
2963 .s_mask = BIT(4),
2964 .s2_reg = MISC_CC3_REG,
2965 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002966 .c = {
2967 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002968 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002969 CLK_INIT(csi_rdi2_clk.c),
2970 },
2971};
2972
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002973#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002974 { \
2975 .freq_hz = f, \
2976 .src_clk = &s##_clk.c, \
2977 .md_val = MD8(8, m, 0, n), \
2978 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2979 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002980 }
2981static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002982 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
2983 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
2984 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002985 F_END
2986};
2987
2988static struct rcg_clk csiphy_timer_src_clk = {
2989 .ns_reg = CSIPHYTIMER_NS_REG,
2990 .b = {
2991 .ctl_reg = CSIPHYTIMER_CC_REG,
2992 .halt_check = NOCHECK,
2993 },
2994 .md_reg = CSIPHYTIMER_MD_REG,
2995 .root_en_mask = BIT(2),
2996 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08002997 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002998 .ctl_mask = BM(7, 6),
2999 .set_rate = set_rate_mnd_8,
3000 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003001 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003002 .c = {
3003 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003004 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003005 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003006 CLK_INIT(csiphy_timer_src_clk.c),
3007 },
3008};
3009
3010static struct branch_clk csi0phy_timer_clk = {
3011 .b = {
3012 .ctl_reg = CSIPHYTIMER_CC_REG,
3013 .en_mask = BIT(0),
3014 .halt_reg = DBG_BUS_VEC_I_REG,
3015 .halt_bit = 17,
3016 },
3017 .parent = &csiphy_timer_src_clk.c,
3018 .c = {
3019 .dbg_name = "csi0phy_timer_clk",
3020 .ops = &clk_ops_branch,
3021 CLK_INIT(csi0phy_timer_clk.c),
3022 },
3023};
3024
3025static struct branch_clk csi1phy_timer_clk = {
3026 .b = {
3027 .ctl_reg = CSIPHYTIMER_CC_REG,
3028 .en_mask = BIT(9),
3029 .halt_reg = DBG_BUS_VEC_I_REG,
3030 .halt_bit = 18,
3031 },
3032 .parent = &csiphy_timer_src_clk.c,
3033 .c = {
3034 .dbg_name = "csi1phy_timer_clk",
3035 .ops = &clk_ops_branch,
3036 CLK_INIT(csi1phy_timer_clk.c),
3037 },
3038};
3039
Stephen Boyd94625ef2011-07-12 17:06:01 -07003040static struct branch_clk csi2phy_timer_clk = {
3041 .b = {
3042 .ctl_reg = CSIPHYTIMER_CC_REG,
3043 .en_mask = BIT(11),
3044 .halt_reg = DBG_BUS_VEC_I_REG,
3045 .halt_bit = 30,
3046 },
3047 .parent = &csiphy_timer_src_clk.c,
3048 .c = {
3049 .dbg_name = "csi2phy_timer_clk",
3050 .ops = &clk_ops_branch,
3051 CLK_INIT(csi2phy_timer_clk.c),
3052 },
3053};
3054
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003055#define F_DSI(d) \
3056 { \
3057 .freq_hz = d, \
3058 .ns_val = BVAL(15, 12, (d-1)), \
3059 }
3060/*
3061 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3062 * without this clock driver knowing. So, overload the clk_set_rate() to set
3063 * the divider (1 to 16) of the clock with respect to the PLL rate.
3064 */
3065static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3066 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3067 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3068 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3069 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3070 F_END
3071};
3072
3073static struct rcg_clk dsi1_byte_clk = {
3074 .b = {
3075 .ctl_reg = DSI1_BYTE_CC_REG,
3076 .en_mask = BIT(0),
3077 .reset_reg = SW_RESET_CORE_REG,
3078 .reset_mask = BIT(7),
3079 .halt_reg = DBG_BUS_VEC_B_REG,
3080 .halt_bit = 21,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003081 .retain_reg = DSI1_BYTE_CC_REG,
3082 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003083 },
3084 .ns_reg = DSI1_BYTE_NS_REG,
3085 .root_en_mask = BIT(2),
3086 .ns_mask = BM(15, 12),
3087 .set_rate = set_rate_nop,
3088 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003089 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003090 .c = {
3091 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003092 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003093 CLK_INIT(dsi1_byte_clk.c),
3094 },
3095};
3096
3097static struct rcg_clk dsi2_byte_clk = {
3098 .b = {
3099 .ctl_reg = DSI2_BYTE_CC_REG,
3100 .en_mask = BIT(0),
3101 .reset_reg = SW_RESET_CORE_REG,
3102 .reset_mask = BIT(25),
3103 .halt_reg = DBG_BUS_VEC_B_REG,
3104 .halt_bit = 20,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003105 .retain_reg = DSI2_BYTE_CC_REG,
3106 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003107 },
3108 .ns_reg = DSI2_BYTE_NS_REG,
3109 .root_en_mask = BIT(2),
3110 .ns_mask = BM(15, 12),
3111 .set_rate = set_rate_nop,
3112 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003113 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003114 .c = {
3115 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003116 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003117 CLK_INIT(dsi2_byte_clk.c),
3118 },
3119};
3120
3121static struct rcg_clk dsi1_esc_clk = {
3122 .b = {
3123 .ctl_reg = DSI1_ESC_CC_REG,
3124 .en_mask = BIT(0),
3125 .reset_reg = SW_RESET_CORE_REG,
3126 .halt_reg = DBG_BUS_VEC_I_REG,
3127 .halt_bit = 1,
3128 },
3129 .ns_reg = DSI1_ESC_NS_REG,
3130 .root_en_mask = BIT(2),
3131 .ns_mask = BM(15, 12),
3132 .set_rate = set_rate_nop,
3133 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003134 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003135 .c = {
3136 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003137 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003138 CLK_INIT(dsi1_esc_clk.c),
3139 },
3140};
3141
3142static struct rcg_clk dsi2_esc_clk = {
3143 .b = {
3144 .ctl_reg = DSI2_ESC_CC_REG,
3145 .en_mask = BIT(0),
3146 .halt_reg = DBG_BUS_VEC_I_REG,
3147 .halt_bit = 3,
3148 },
3149 .ns_reg = DSI2_ESC_NS_REG,
3150 .root_en_mask = BIT(2),
3151 .ns_mask = BM(15, 12),
3152 .set_rate = set_rate_nop,
3153 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003154 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003155 .c = {
3156 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003157 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003158 CLK_INIT(dsi2_esc_clk.c),
3159 },
3160};
3161
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003162#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003163 { \
3164 .freq_hz = f, \
3165 .src_clk = &s##_clk.c, \
3166 .md_val = MD4(4, m, 0, n), \
3167 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3168 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003169 }
3170static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003171 F_GFX2D( 0, gnd, 0, 0),
3172 F_GFX2D( 27000000, pxo, 0, 0),
3173 F_GFX2D( 48000000, pll8, 1, 8),
3174 F_GFX2D( 54857000, pll8, 1, 7),
3175 F_GFX2D( 64000000, pll8, 1, 6),
3176 F_GFX2D( 76800000, pll8, 1, 5),
3177 F_GFX2D( 96000000, pll8, 1, 4),
3178 F_GFX2D(128000000, pll8, 1, 3),
3179 F_GFX2D(145455000, pll2, 2, 11),
3180 F_GFX2D(160000000, pll2, 1, 5),
3181 F_GFX2D(177778000, pll2, 2, 9),
3182 F_GFX2D(200000000, pll2, 1, 4),
3183 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003184 F_END
3185};
3186
3187static struct bank_masks bmnd_info_gfx2d0 = {
3188 .bank_sel_mask = BIT(11),
3189 .bank0_mask = {
3190 .md_reg = GFX2D0_MD0_REG,
3191 .ns_mask = BM(23, 20) | BM(5, 3),
3192 .rst_mask = BIT(25),
3193 .mnd_en_mask = BIT(8),
3194 .mode_mask = BM(10, 9),
3195 },
3196 .bank1_mask = {
3197 .md_reg = GFX2D0_MD1_REG,
3198 .ns_mask = BM(19, 16) | BM(2, 0),
3199 .rst_mask = BIT(24),
3200 .mnd_en_mask = BIT(5),
3201 .mode_mask = BM(7, 6),
3202 },
3203};
3204
3205static struct rcg_clk gfx2d0_clk = {
3206 .b = {
3207 .ctl_reg = GFX2D0_CC_REG,
3208 .en_mask = BIT(0),
3209 .reset_reg = SW_RESET_CORE_REG,
3210 .reset_mask = BIT(14),
3211 .halt_reg = DBG_BUS_VEC_A_REG,
3212 .halt_bit = 9,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003213 .retain_reg = GFX2D0_CC_REG,
3214 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003215 },
3216 .ns_reg = GFX2D0_NS_REG,
3217 .root_en_mask = BIT(2),
3218 .set_rate = set_rate_mnd_banked,
3219 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003220 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003221 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003222 .c = {
3223 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003224 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003225 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3226 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003227 CLK_INIT(gfx2d0_clk.c),
3228 },
3229};
3230
3231static struct bank_masks bmnd_info_gfx2d1 = {
3232 .bank_sel_mask = BIT(11),
3233 .bank0_mask = {
3234 .md_reg = GFX2D1_MD0_REG,
3235 .ns_mask = BM(23, 20) | BM(5, 3),
3236 .rst_mask = BIT(25),
3237 .mnd_en_mask = BIT(8),
3238 .mode_mask = BM(10, 9),
3239 },
3240 .bank1_mask = {
3241 .md_reg = GFX2D1_MD1_REG,
3242 .ns_mask = BM(19, 16) | BM(2, 0),
3243 .rst_mask = BIT(24),
3244 .mnd_en_mask = BIT(5),
3245 .mode_mask = BM(7, 6),
3246 },
3247};
3248
3249static struct rcg_clk gfx2d1_clk = {
3250 .b = {
3251 .ctl_reg = GFX2D1_CC_REG,
3252 .en_mask = BIT(0),
3253 .reset_reg = SW_RESET_CORE_REG,
3254 .reset_mask = BIT(13),
3255 .halt_reg = DBG_BUS_VEC_A_REG,
3256 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003257 .retain_reg = GFX2D1_CC_REG,
3258 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003259 },
3260 .ns_reg = GFX2D1_NS_REG,
3261 .root_en_mask = BIT(2),
3262 .set_rate = set_rate_mnd_banked,
3263 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003264 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003265 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003266 .c = {
3267 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003268 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003269 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3270 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003271 CLK_INIT(gfx2d1_clk.c),
3272 },
3273};
3274
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003275#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003276 { \
3277 .freq_hz = f, \
3278 .src_clk = &s##_clk.c, \
3279 .md_val = MD4(4, m, 0, n), \
3280 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3281 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003282 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003283
3284static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003285 F_GFX3D( 0, gnd, 0, 0),
3286 F_GFX3D( 27000000, pxo, 0, 0),
3287 F_GFX3D( 48000000, pll8, 1, 8),
3288 F_GFX3D( 54857000, pll8, 1, 7),
3289 F_GFX3D( 64000000, pll8, 1, 6),
3290 F_GFX3D( 76800000, pll8, 1, 5),
3291 F_GFX3D( 96000000, pll8, 1, 4),
3292 F_GFX3D(128000000, pll8, 1, 3),
3293 F_GFX3D(145455000, pll2, 2, 11),
3294 F_GFX3D(160000000, pll2, 1, 5),
3295 F_GFX3D(177778000, pll2, 2, 9),
3296 F_GFX3D(200000000, pll2, 1, 4),
3297 F_GFX3D(228571000, pll2, 2, 7),
3298 F_GFX3D(266667000, pll2, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003299 F_GFX3D(300000000, pll3, 1, 4),
3300 F_GFX3D(320000000, pll2, 2, 5),
3301 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003302 F_END
3303};
3304
Tianyi Gou41515e22011-09-01 19:37:43 -07003305static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003306 F_GFX3D( 0, gnd, 0, 0),
3307 F_GFX3D( 27000000, pxo, 0, 0),
3308 F_GFX3D( 48000000, pll8, 1, 8),
3309 F_GFX3D( 54857000, pll8, 1, 7),
3310 F_GFX3D( 64000000, pll8, 1, 6),
3311 F_GFX3D( 76800000, pll8, 1, 5),
3312 F_GFX3D( 96000000, pll8, 1, 4),
3313 F_GFX3D(128000000, pll8, 1, 3),
3314 F_GFX3D(145455000, pll2, 2, 11),
3315 F_GFX3D(160000000, pll2, 1, 5),
3316 F_GFX3D(177778000, pll2, 2, 9),
3317 F_GFX3D(200000000, pll2, 1, 4),
3318 F_GFX3D(228571000, pll2, 2, 7),
3319 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07003320 F_GFX3D(325000000, pll15, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003321 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003322 F_END
3323};
3324
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003325static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3326 [VDD_DIG_LOW] = 128000000,
3327 [VDD_DIG_NOMINAL] = 325000000,
3328 [VDD_DIG_HIGH] = 400000000
3329};
3330
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003331static struct bank_masks bmnd_info_gfx3d = {
3332 .bank_sel_mask = BIT(11),
3333 .bank0_mask = {
3334 .md_reg = GFX3D_MD0_REG,
3335 .ns_mask = BM(21, 18) | BM(5, 3),
3336 .rst_mask = BIT(23),
3337 .mnd_en_mask = BIT(8),
3338 .mode_mask = BM(10, 9),
3339 },
3340 .bank1_mask = {
3341 .md_reg = GFX3D_MD1_REG,
3342 .ns_mask = BM(17, 14) | BM(2, 0),
3343 .rst_mask = BIT(22),
3344 .mnd_en_mask = BIT(5),
3345 .mode_mask = BM(7, 6),
3346 },
3347};
3348
3349static struct rcg_clk gfx3d_clk = {
3350 .b = {
3351 .ctl_reg = GFX3D_CC_REG,
3352 .en_mask = BIT(0),
3353 .reset_reg = SW_RESET_CORE_REG,
3354 .reset_mask = BIT(12),
3355 .halt_reg = DBG_BUS_VEC_A_REG,
3356 .halt_bit = 4,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003357 .retain_reg = GFX3D_CC_REG,
3358 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003359 },
3360 .ns_reg = GFX3D_NS_REG,
3361 .root_en_mask = BIT(2),
3362 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003363 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003364 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003365 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003366 .c = {
3367 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003368 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003369 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000,
3370 HIGH, 400000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003371 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003372 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003373 },
3374};
3375
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003376#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003377 { \
3378 .freq_hz = f, \
3379 .src_clk = &s##_clk.c, \
3380 .md_val = MD4(4, m, 0, n), \
3381 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3382 .ctl_val = CC_BANKED(9, 6, n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003383 }
3384
3385static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003386 F_VCAP( 0, gnd, 0, 0),
3387 F_VCAP( 27000000, pxo, 0, 0),
3388 F_VCAP( 54860000, pll8, 1, 7),
3389 F_VCAP( 64000000, pll8, 1, 6),
3390 F_VCAP( 76800000, pll8, 1, 5),
3391 F_VCAP(128000000, pll8, 1, 3),
3392 F_VCAP(160000000, pll2, 1, 5),
3393 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003394 F_END
3395};
3396
3397static struct bank_masks bmnd_info_vcap = {
3398 .bank_sel_mask = BIT(11),
3399 .bank0_mask = {
3400 .md_reg = VCAP_MD0_REG,
3401 .ns_mask = BM(21, 18) | BM(5, 3),
3402 .rst_mask = BIT(23),
3403 .mnd_en_mask = BIT(8),
3404 .mode_mask = BM(10, 9),
3405 },
3406 .bank1_mask = {
3407 .md_reg = VCAP_MD1_REG,
3408 .ns_mask = BM(17, 14) | BM(2, 0),
3409 .rst_mask = BIT(22),
3410 .mnd_en_mask = BIT(5),
3411 .mode_mask = BM(7, 6),
3412 },
3413};
3414
3415static struct rcg_clk vcap_clk = {
3416 .b = {
3417 .ctl_reg = VCAP_CC_REG,
3418 .en_mask = BIT(0),
3419 .halt_reg = DBG_BUS_VEC_J_REG,
3420 .halt_bit = 15,
3421 },
3422 .ns_reg = VCAP_NS_REG,
3423 .root_en_mask = BIT(2),
3424 .set_rate = set_rate_mnd_banked,
3425 .freq_tbl = clk_tbl_vcap,
3426 .bank_info = &bmnd_info_vcap,
3427 .current_freq = &rcg_dummy_freq,
3428 .c = {
3429 .dbg_name = "vcap_clk",
3430 .ops = &clk_ops_rcg_8960,
3431 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003432 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003433 CLK_INIT(vcap_clk.c),
3434 },
3435};
3436
3437static struct branch_clk vcap_npl_clk = {
3438 .b = {
3439 .ctl_reg = VCAP_CC_REG,
3440 .en_mask = BIT(13),
3441 .halt_reg = DBG_BUS_VEC_J_REG,
3442 .halt_bit = 25,
3443 },
3444 .parent = &vcap_clk.c,
3445 .c = {
3446 .dbg_name = "vcap_npl_clk",
3447 .ops = &clk_ops_branch,
3448 CLK_INIT(vcap_npl_clk.c),
3449 },
3450};
3451
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003452#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003453 { \
3454 .freq_hz = f, \
3455 .src_clk = &s##_clk.c, \
3456 .md_val = MD8(8, m, 0, n), \
3457 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3458 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003459 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003460
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003461static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3462 F_IJPEG( 0, gnd, 1, 0, 0),
3463 F_IJPEG( 27000000, pxo, 1, 0, 0),
3464 F_IJPEG( 36570000, pll8, 1, 2, 21),
3465 F_IJPEG( 54860000, pll8, 7, 0, 0),
3466 F_IJPEG( 96000000, pll8, 4, 0, 0),
3467 F_IJPEG(109710000, pll8, 1, 2, 7),
3468 F_IJPEG(128000000, pll8, 3, 0, 0),
3469 F_IJPEG(153600000, pll8, 1, 2, 5),
3470 F_IJPEG(200000000, pll2, 4, 0, 0),
3471 F_IJPEG(228571000, pll2, 1, 2, 7),
3472 F_IJPEG(266667000, pll2, 1, 1, 3),
3473 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003474 F_END
3475};
3476
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003477static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3478 [VDD_DIG_LOW] = 128000000,
3479 [VDD_DIG_NOMINAL] = 266667000,
3480 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003481};
3482
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003483static struct rcg_clk ijpeg_clk = {
3484 .b = {
3485 .ctl_reg = IJPEG_CC_REG,
3486 .en_mask = BIT(0),
3487 .reset_reg = SW_RESET_CORE_REG,
3488 .reset_mask = BIT(9),
3489 .halt_reg = DBG_BUS_VEC_A_REG,
3490 .halt_bit = 24,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003491 .retain_reg = IJPEG_CC_REG,
3492 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003493 },
3494 .ns_reg = IJPEG_NS_REG,
3495 .md_reg = IJPEG_MD_REG,
3496 .root_en_mask = BIT(2),
3497 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003498 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003499 .ctl_mask = BM(7, 6),
3500 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003501 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003502 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003503 .c = {
3504 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003505 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003506 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
3507 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003508 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003509 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003510 },
3511};
3512
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003513#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003514 { \
3515 .freq_hz = f, \
3516 .src_clk = &s##_clk.c, \
3517 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003518 }
3519static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003520 F_JPEGD( 0, gnd, 1),
3521 F_JPEGD( 64000000, pll8, 6),
3522 F_JPEGD( 76800000, pll8, 5),
3523 F_JPEGD( 96000000, pll8, 4),
3524 F_JPEGD(160000000, pll2, 5),
3525 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003526 F_END
3527};
3528
3529static struct rcg_clk jpegd_clk = {
3530 .b = {
3531 .ctl_reg = JPEGD_CC_REG,
3532 .en_mask = BIT(0),
3533 .reset_reg = SW_RESET_CORE_REG,
3534 .reset_mask = BIT(19),
3535 .halt_reg = DBG_BUS_VEC_A_REG,
3536 .halt_bit = 19,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003537 .retain_reg = JPEGD_CC_REG,
3538 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003539 },
3540 .ns_reg = JPEGD_NS_REG,
3541 .root_en_mask = BIT(2),
3542 .ns_mask = (BM(15, 12) | BM(2, 0)),
3543 .set_rate = set_rate_nop,
3544 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003545 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003546 .c = {
3547 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003548 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003549 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003550 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003551 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003552 },
3553};
3554
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003555#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003556 { \
3557 .freq_hz = f, \
3558 .src_clk = &s##_clk.c, \
3559 .md_val = MD8(8, m, 0, n), \
3560 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3561 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003562 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003563static struct clk_freq_tbl clk_tbl_mdp[] = {
3564 F_MDP( 0, gnd, 0, 0),
3565 F_MDP( 9600000, pll8, 1, 40),
3566 F_MDP( 13710000, pll8, 1, 28),
3567 F_MDP( 27000000, pxo, 0, 0),
3568 F_MDP( 29540000, pll8, 1, 13),
3569 F_MDP( 34910000, pll8, 1, 11),
3570 F_MDP( 38400000, pll8, 1, 10),
3571 F_MDP( 59080000, pll8, 2, 13),
3572 F_MDP( 76800000, pll8, 1, 5),
3573 F_MDP( 85330000, pll8, 2, 9),
3574 F_MDP( 96000000, pll8, 1, 4),
3575 F_MDP(128000000, pll8, 1, 3),
3576 F_MDP(160000000, pll2, 1, 5),
3577 F_MDP(177780000, pll2, 2, 9),
3578 F_MDP(200000000, pll2, 1, 4),
3579 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003580 F_END
3581};
3582
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003583static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3584 [VDD_DIG_LOW] = 128000000,
3585 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003586};
3587
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003588static struct bank_masks bmnd_info_mdp = {
3589 .bank_sel_mask = BIT(11),
3590 .bank0_mask = {
3591 .md_reg = MDP_MD0_REG,
3592 .ns_mask = BM(29, 22) | BM(5, 3),
3593 .rst_mask = BIT(31),
3594 .mnd_en_mask = BIT(8),
3595 .mode_mask = BM(10, 9),
3596 },
3597 .bank1_mask = {
3598 .md_reg = MDP_MD1_REG,
3599 .ns_mask = BM(21, 14) | BM(2, 0),
3600 .rst_mask = BIT(30),
3601 .mnd_en_mask = BIT(5),
3602 .mode_mask = BM(7, 6),
3603 },
3604};
3605
3606static struct rcg_clk mdp_clk = {
3607 .b = {
3608 .ctl_reg = MDP_CC_REG,
3609 .en_mask = BIT(0),
3610 .reset_reg = SW_RESET_CORE_REG,
3611 .reset_mask = BIT(21),
3612 .halt_reg = DBG_BUS_VEC_C_REG,
3613 .halt_bit = 10,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003614 .retain_reg = MDP_CC_REG,
3615 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003616 },
3617 .ns_reg = MDP_NS_REG,
3618 .root_en_mask = BIT(2),
3619 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003620 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003621 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003622 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003623 .c = {
3624 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003625 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003626 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003627 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003628 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003629 },
3630};
3631
3632static struct branch_clk lut_mdp_clk = {
3633 .b = {
3634 .ctl_reg = MDP_LUT_CC_REG,
3635 .en_mask = BIT(0),
3636 .halt_reg = DBG_BUS_VEC_I_REG,
3637 .halt_bit = 13,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003638 .retain_reg = MDP_LUT_CC_REG,
3639 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003640 },
3641 .parent = &mdp_clk.c,
3642 .c = {
3643 .dbg_name = "lut_mdp_clk",
3644 .ops = &clk_ops_branch,
3645 CLK_INIT(lut_mdp_clk.c),
3646 },
3647};
3648
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003649#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003650 { \
3651 .freq_hz = f, \
3652 .src_clk = &s##_clk.c, \
3653 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003654 }
3655static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003656 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003657 F_END
3658};
3659
3660static struct rcg_clk mdp_vsync_clk = {
3661 .b = {
3662 .ctl_reg = MISC_CC_REG,
3663 .en_mask = BIT(6),
3664 .reset_reg = SW_RESET_CORE_REG,
3665 .reset_mask = BIT(3),
3666 .halt_reg = DBG_BUS_VEC_B_REG,
3667 .halt_bit = 22,
3668 },
3669 .ns_reg = MISC_CC2_REG,
3670 .ns_mask = BIT(13),
3671 .set_rate = set_rate_nop,
3672 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003673 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003674 .c = {
3675 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003676 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003677 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003678 CLK_INIT(mdp_vsync_clk.c),
3679 },
3680};
3681
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003682#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003683 { \
3684 .freq_hz = f, \
3685 .src_clk = &s##_clk.c, \
3686 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3687 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003688 }
3689static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003690 F_ROT( 0, gnd, 1),
3691 F_ROT( 27000000, pxo, 1),
3692 F_ROT( 29540000, pll8, 13),
3693 F_ROT( 32000000, pll8, 12),
3694 F_ROT( 38400000, pll8, 10),
3695 F_ROT( 48000000, pll8, 8),
3696 F_ROT( 54860000, pll8, 7),
3697 F_ROT( 64000000, pll8, 6),
3698 F_ROT( 76800000, pll8, 5),
3699 F_ROT( 96000000, pll8, 4),
3700 F_ROT(100000000, pll2, 8),
3701 F_ROT(114290000, pll2, 7),
3702 F_ROT(133330000, pll2, 6),
3703 F_ROT(160000000, pll2, 5),
3704 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003705 F_END
3706};
3707
3708static struct bank_masks bdiv_info_rot = {
3709 .bank_sel_mask = BIT(30),
3710 .bank0_mask = {
3711 .ns_mask = BM(25, 22) | BM(18, 16),
3712 },
3713 .bank1_mask = {
3714 .ns_mask = BM(29, 26) | BM(21, 19),
3715 },
3716};
3717
3718static struct rcg_clk rot_clk = {
3719 .b = {
3720 .ctl_reg = ROT_CC_REG,
3721 .en_mask = BIT(0),
3722 .reset_reg = SW_RESET_CORE_REG,
3723 .reset_mask = BIT(2),
3724 .halt_reg = DBG_BUS_VEC_C_REG,
3725 .halt_bit = 15,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003726 .retain_reg = ROT_CC_REG,
3727 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003728 },
3729 .ns_reg = ROT_NS_REG,
3730 .root_en_mask = BIT(2),
3731 .set_rate = set_rate_div_banked,
3732 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003733 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003734 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003735 .c = {
3736 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003737 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003738 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003739 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003740 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003741 },
3742};
3743
3744static int hdmi_pll_clk_enable(struct clk *clk)
3745{
3746 int ret;
3747 unsigned long flags;
3748 spin_lock_irqsave(&local_clock_reg_lock, flags);
3749 ret = hdmi_pll_enable();
3750 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3751 return ret;
3752}
3753
3754static void hdmi_pll_clk_disable(struct clk *clk)
3755{
3756 unsigned long flags;
3757 spin_lock_irqsave(&local_clock_reg_lock, flags);
3758 hdmi_pll_disable();
3759 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3760}
3761
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07003762static unsigned long hdmi_pll_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003763{
3764 return hdmi_pll_get_rate();
3765}
3766
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003767static struct clk *hdmi_pll_clk_get_parent(struct clk *clk)
3768{
3769 return &pxo_clk.c;
3770}
3771
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003772static struct clk_ops clk_ops_hdmi_pll = {
3773 .enable = hdmi_pll_clk_enable,
3774 .disable = hdmi_pll_clk_disable,
3775 .get_rate = hdmi_pll_clk_get_rate,
3776 .is_local = local_clk_is_local,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003777 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003778};
3779
3780static struct clk hdmi_pll_clk = {
3781 .dbg_name = "hdmi_pll_clk",
3782 .ops = &clk_ops_hdmi_pll,
3783 CLK_INIT(hdmi_pll_clk),
3784};
3785
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003786#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003787 { \
3788 .freq_hz = f, \
3789 .src_clk = &s##_clk.c, \
3790 .md_val = MD8(8, m, 0, n), \
3791 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3792 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003793 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003794#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003795 { \
3796 .freq_hz = f, \
3797 .src_clk = &s##_clk, \
3798 .md_val = MD8(8, m, 0, n), \
3799 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3800 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003801 .extra_freq_data = (void *)p_r, \
3802 }
3803/* Switching TV freqs requires PLL reconfiguration. */
3804static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003805 F_TV_GND( 0, gnd, 0, 1, 0, 0),
3806 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
3807 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
3808 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
3809 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
3810 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003811 F_END
3812};
3813
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003814static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
3815 [VDD_DIG_LOW] = 74250000,
3816 [VDD_DIG_NOMINAL] = 149000000
3817};
3818
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003819/*
3820 * Unlike other clocks, the TV rate is adjusted through PLL
3821 * re-programming. It is also routed through an MND divider.
3822 */
3823void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3824{
3825 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3826 if (pll_rate)
3827 hdmi_pll_set_rate(pll_rate);
3828 set_rate_mnd(clk, nf);
3829}
3830
3831static struct rcg_clk tv_src_clk = {
3832 .ns_reg = TV_NS_REG,
3833 .b = {
3834 .ctl_reg = TV_CC_REG,
3835 .halt_check = NOCHECK,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003836 .retain_reg = TV_CC_REG,
3837 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003838 },
3839 .md_reg = TV_MD_REG,
3840 .root_en_mask = BIT(2),
3841 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003842 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003843 .ctl_mask = BM(7, 6),
3844 .set_rate = set_rate_tv,
3845 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003846 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003847 .c = {
3848 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003849 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003850 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003851 CLK_INIT(tv_src_clk.c),
3852 },
3853};
3854
Tianyi Gou51918802012-01-26 14:05:43 -08003855static struct cdiv_clk tv_src_div_clk = {
3856 .b = {
3857 .ctl_reg = TV_NS_REG,
3858 .halt_check = NOCHECK,
3859 },
3860 .ns_reg = TV_NS_REG,
3861 .div_offset = 6,
3862 .max_div = 2,
3863 .c = {
3864 .dbg_name = "tv_src_div_clk",
3865 .ops = &clk_ops_cdiv,
3866 CLK_INIT(tv_src_div_clk.c),
3867 },
3868};
3869
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003870static struct branch_clk tv_enc_clk = {
3871 .b = {
3872 .ctl_reg = TV_CC_REG,
3873 .en_mask = BIT(8),
3874 .reset_reg = SW_RESET_CORE_REG,
3875 .reset_mask = BIT(0),
3876 .halt_reg = DBG_BUS_VEC_D_REG,
3877 .halt_bit = 9,
3878 },
3879 .parent = &tv_src_clk.c,
3880 .c = {
3881 .dbg_name = "tv_enc_clk",
3882 .ops = &clk_ops_branch,
3883 CLK_INIT(tv_enc_clk.c),
3884 },
3885};
3886
3887static struct branch_clk tv_dac_clk = {
3888 .b = {
3889 .ctl_reg = TV_CC_REG,
3890 .en_mask = BIT(10),
3891 .halt_reg = DBG_BUS_VEC_D_REG,
3892 .halt_bit = 10,
3893 },
3894 .parent = &tv_src_clk.c,
3895 .c = {
3896 .dbg_name = "tv_dac_clk",
3897 .ops = &clk_ops_branch,
3898 CLK_INIT(tv_dac_clk.c),
3899 },
3900};
3901
3902static struct branch_clk mdp_tv_clk = {
3903 .b = {
3904 .ctl_reg = TV_CC_REG,
3905 .en_mask = BIT(0),
3906 .reset_reg = SW_RESET_CORE_REG,
3907 .reset_mask = BIT(4),
3908 .halt_reg = DBG_BUS_VEC_D_REG,
3909 .halt_bit = 12,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003910 .retain_reg = TV_CC2_REG,
3911 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003912 },
3913 .parent = &tv_src_clk.c,
3914 .c = {
3915 .dbg_name = "mdp_tv_clk",
3916 .ops = &clk_ops_branch,
3917 CLK_INIT(mdp_tv_clk.c),
3918 },
3919};
3920
3921static struct branch_clk hdmi_tv_clk = {
3922 .b = {
3923 .ctl_reg = TV_CC_REG,
3924 .en_mask = BIT(12),
3925 .reset_reg = SW_RESET_CORE_REG,
3926 .reset_mask = BIT(1),
3927 .halt_reg = DBG_BUS_VEC_D_REG,
3928 .halt_bit = 11,
3929 },
3930 .parent = &tv_src_clk.c,
3931 .c = {
3932 .dbg_name = "hdmi_tv_clk",
3933 .ops = &clk_ops_branch,
3934 CLK_INIT(hdmi_tv_clk.c),
3935 },
3936};
3937
Tianyi Gou51918802012-01-26 14:05:43 -08003938static struct branch_clk rgb_tv_clk = {
3939 .b = {
3940 .ctl_reg = TV_CC2_REG,
3941 .en_mask = BIT(14),
3942 .halt_reg = DBG_BUS_VEC_J_REG,
3943 .halt_bit = 27,
3944 },
3945 .parent = &tv_src_clk.c,
3946 .c = {
3947 .dbg_name = "rgb_tv_clk",
3948 .ops = &clk_ops_branch,
3949 CLK_INIT(rgb_tv_clk.c),
3950 },
3951};
3952
3953static struct branch_clk npl_tv_clk = {
3954 .b = {
3955 .ctl_reg = TV_CC2_REG,
3956 .en_mask = BIT(16),
3957 .halt_reg = DBG_BUS_VEC_J_REG,
3958 .halt_bit = 26,
3959 },
3960 .parent = &tv_src_clk.c,
3961 .c = {
3962 .dbg_name = "npl_tv_clk",
3963 .ops = &clk_ops_branch,
3964 CLK_INIT(npl_tv_clk.c),
3965 },
3966};
3967
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003968static struct branch_clk hdmi_app_clk = {
3969 .b = {
3970 .ctl_reg = MISC_CC2_REG,
3971 .en_mask = BIT(11),
3972 .reset_reg = SW_RESET_CORE_REG,
3973 .reset_mask = BIT(11),
3974 .halt_reg = DBG_BUS_VEC_B_REG,
3975 .halt_bit = 25,
3976 },
3977 .c = {
3978 .dbg_name = "hdmi_app_clk",
3979 .ops = &clk_ops_branch,
3980 CLK_INIT(hdmi_app_clk.c),
3981 },
3982};
3983
3984static struct bank_masks bmnd_info_vcodec = {
3985 .bank_sel_mask = BIT(13),
3986 .bank0_mask = {
3987 .md_reg = VCODEC_MD0_REG,
3988 .ns_mask = BM(18, 11) | BM(2, 0),
3989 .rst_mask = BIT(31),
3990 .mnd_en_mask = BIT(5),
3991 .mode_mask = BM(7, 6),
3992 },
3993 .bank1_mask = {
3994 .md_reg = VCODEC_MD1_REG,
3995 .ns_mask = BM(26, 19) | BM(29, 27),
3996 .rst_mask = BIT(30),
3997 .mnd_en_mask = BIT(10),
3998 .mode_mask = BM(12, 11),
3999 },
4000};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004001#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004002 { \
4003 .freq_hz = f, \
4004 .src_clk = &s##_clk.c, \
4005 .md_val = MD8(8, m, 0, n), \
4006 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
4007 .ctl_val = CC_BANKED(6, 11, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004008 }
4009static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004010 F_VCODEC( 0, gnd, 0, 0),
4011 F_VCODEC( 27000000, pxo, 0, 0),
4012 F_VCODEC( 32000000, pll8, 1, 12),
4013 F_VCODEC( 48000000, pll8, 1, 8),
4014 F_VCODEC( 54860000, pll8, 1, 7),
4015 F_VCODEC( 96000000, pll8, 1, 4),
4016 F_VCODEC(133330000, pll2, 1, 6),
4017 F_VCODEC(200000000, pll2, 1, 4),
4018 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004019 F_END
4020};
4021
4022static struct rcg_clk vcodec_clk = {
4023 .b = {
4024 .ctl_reg = VCODEC_CC_REG,
4025 .en_mask = BIT(0),
4026 .reset_reg = SW_RESET_CORE_REG,
4027 .reset_mask = BIT(6),
4028 .halt_reg = DBG_BUS_VEC_C_REG,
4029 .halt_bit = 29,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004030 .retain_reg = VCODEC_CC_REG,
4031 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004032 },
4033 .ns_reg = VCODEC_NS_REG,
4034 .root_en_mask = BIT(2),
4035 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004036 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004037 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004038 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004039 .c = {
4040 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004041 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004042 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4043 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004044 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004045 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004046 },
4047};
4048
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004049#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004050 { \
4051 .freq_hz = f, \
4052 .src_clk = &s##_clk.c, \
4053 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004054 }
4055static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004056 F_VPE( 0, gnd, 1),
4057 F_VPE( 27000000, pxo, 1),
4058 F_VPE( 34909000, pll8, 11),
4059 F_VPE( 38400000, pll8, 10),
4060 F_VPE( 64000000, pll8, 6),
4061 F_VPE( 76800000, pll8, 5),
4062 F_VPE( 96000000, pll8, 4),
4063 F_VPE(100000000, pll2, 8),
4064 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004065 F_END
4066};
4067
4068static struct rcg_clk vpe_clk = {
4069 .b = {
4070 .ctl_reg = VPE_CC_REG,
4071 .en_mask = BIT(0),
4072 .reset_reg = SW_RESET_CORE_REG,
4073 .reset_mask = BIT(17),
4074 .halt_reg = DBG_BUS_VEC_A_REG,
4075 .halt_bit = 28,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004076 .retain_reg = VPE_CC_REG,
4077 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004078 },
4079 .ns_reg = VPE_NS_REG,
4080 .root_en_mask = BIT(2),
4081 .ns_mask = (BM(15, 12) | BM(2, 0)),
4082 .set_rate = set_rate_nop,
4083 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004084 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004085 .c = {
4086 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004087 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004088 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004089 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004090 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004091 },
4092};
4093
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004094#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004095 { \
4096 .freq_hz = f, \
4097 .src_clk = &s##_clk.c, \
4098 .md_val = MD8(8, m, 0, n), \
4099 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4100 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004101 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004102
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004103static struct clk_freq_tbl clk_tbl_vfe[] = {
4104 F_VFE( 0, gnd, 1, 0, 0),
4105 F_VFE( 13960000, pll8, 1, 2, 55),
4106 F_VFE( 27000000, pxo, 1, 0, 0),
4107 F_VFE( 36570000, pll8, 1, 2, 21),
4108 F_VFE( 38400000, pll8, 2, 1, 5),
4109 F_VFE( 45180000, pll8, 1, 2, 17),
4110 F_VFE( 48000000, pll8, 2, 1, 4),
4111 F_VFE( 54860000, pll8, 1, 1, 7),
4112 F_VFE( 64000000, pll8, 2, 1, 3),
4113 F_VFE( 76800000, pll8, 1, 1, 5),
4114 F_VFE( 96000000, pll8, 2, 1, 2),
4115 F_VFE(109710000, pll8, 1, 2, 7),
4116 F_VFE(128000000, pll8, 1, 1, 3),
4117 F_VFE(153600000, pll8, 1, 2, 5),
4118 F_VFE(200000000, pll2, 2, 1, 2),
4119 F_VFE(228570000, pll2, 1, 2, 7),
4120 F_VFE(266667000, pll2, 1, 1, 3),
4121 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004122 F_END
4123};
4124
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004125static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4126 [VDD_DIG_LOW] = 128000000,
4127 [VDD_DIG_NOMINAL] = 266667000,
4128 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004129};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004130
4131static struct rcg_clk vfe_clk = {
4132 .b = {
4133 .ctl_reg = VFE_CC_REG,
4134 .reset_reg = SW_RESET_CORE_REG,
4135 .reset_mask = BIT(15),
4136 .halt_reg = DBG_BUS_VEC_B_REG,
4137 .halt_bit = 6,
4138 .en_mask = BIT(0),
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004139 .retain_reg = VFE_CC2_REG,
4140 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004141 },
4142 .ns_reg = VFE_NS_REG,
4143 .md_reg = VFE_MD_REG,
4144 .root_en_mask = BIT(2),
4145 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004146 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004147 .ctl_mask = BM(7, 6),
4148 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004149 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004150 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004151 .c = {
4152 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004153 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08004154 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
4155 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004156 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004157 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004158 },
4159};
4160
Matt Wagantallc23eee92011-08-16 23:06:52 -07004161static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004162 .b = {
4163 .ctl_reg = VFE_CC_REG,
4164 .en_mask = BIT(12),
4165 .reset_reg = SW_RESET_CORE_REG,
4166 .reset_mask = BIT(24),
4167 .halt_reg = DBG_BUS_VEC_B_REG,
4168 .halt_bit = 8,
4169 },
4170 .parent = &vfe_clk.c,
4171 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004172 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004173 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004174 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004175 },
4176};
4177
4178/*
4179 * Low Power Audio Clocks
4180 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004181#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004182 { \
4183 .freq_hz = f, \
4184 .src_clk = &s##_clk.c, \
4185 .md_val = MD8(8, m, 0, n), \
4186 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004187 }
4188static struct clk_freq_tbl clk_tbl_aif_osr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004189 F_AIF_OSR( 0, gnd, 1, 0, 0),
4190 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4191 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4192 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4193 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4194 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4195 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4196 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4197 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4198 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4199 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4200 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004201 F_END
4202};
4203
4204#define CLK_AIF_OSR(i, ns, md, h_r) \
4205 struct rcg_clk i##_clk = { \
4206 .b = { \
4207 .ctl_reg = ns, \
4208 .en_mask = BIT(17), \
4209 .reset_reg = ns, \
4210 .reset_mask = BIT(19), \
4211 .halt_reg = h_r, \
4212 .halt_check = ENABLE, \
4213 .halt_bit = 1, \
4214 }, \
4215 .ns_reg = ns, \
4216 .md_reg = md, \
4217 .root_en_mask = BIT(9), \
4218 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004219 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004220 .set_rate = set_rate_mnd, \
4221 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004222 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004223 .c = { \
4224 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004225 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004226 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004227 CLK_INIT(i##_clk.c), \
4228 }, \
4229 }
4230#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4231 struct rcg_clk i##_clk = { \
4232 .b = { \
4233 .ctl_reg = ns, \
4234 .en_mask = BIT(21), \
4235 .reset_reg = ns, \
4236 .reset_mask = BIT(23), \
4237 .halt_reg = h_r, \
4238 .halt_check = ENABLE, \
4239 .halt_bit = 1, \
4240 }, \
4241 .ns_reg = ns, \
4242 .md_reg = md, \
4243 .root_en_mask = BIT(9), \
4244 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004245 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004246 .set_rate = set_rate_mnd, \
4247 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004248 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004249 .c = { \
4250 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004251 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004252 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004253 CLK_INIT(i##_clk.c), \
4254 }, \
4255 }
4256
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004257#define CLK_AIF_BIT(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004258 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004259 .b = { \
4260 .ctl_reg = ns, \
4261 .en_mask = BIT(15), \
4262 .halt_reg = h_r, \
4263 .halt_check = DELAY, \
4264 }, \
4265 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004266 .ext_mask = BIT(14), \
4267 .div_offset = 10, \
4268 .max_div = 16, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004269 .c = { \
4270 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004271 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004272 CLK_INIT(i##_clk.c), \
4273 }, \
4274 }
4275
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004276#define CLK_AIF_BIT_DIV(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004277 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004278 .b = { \
4279 .ctl_reg = ns, \
4280 .en_mask = BIT(19), \
4281 .halt_reg = h_r, \
Stephen Boyd7bb9cf82012-01-25 18:09:01 -08004282 .halt_check = DELAY, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004283 }, \
4284 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004285 .ext_mask = BIT(18), \
4286 .div_offset = 10, \
4287 .max_div = 256, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004288 .c = { \
4289 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004290 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004291 CLK_INIT(i##_clk.c), \
4292 }, \
4293 }
4294
4295static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4296 LCC_MI2S_STATUS_REG);
4297static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4298
4299static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4300 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4301static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4302 LCC_CODEC_I2S_MIC_STATUS_REG);
4303
4304static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4305 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4306static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4307 LCC_SPARE_I2S_MIC_STATUS_REG);
4308
4309static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4310 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4311static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4312 LCC_CODEC_I2S_SPKR_STATUS_REG);
4313
4314static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4315 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4316static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4317 LCC_SPARE_I2S_SPKR_STATUS_REG);
4318
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004319#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004320 { \
4321 .freq_hz = f, \
4322 .src_clk = &s##_clk.c, \
4323 .md_val = MD16(m, n), \
4324 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004325 }
4326static struct clk_freq_tbl clk_tbl_pcm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004327 F_PCM( 0, gnd, 1, 0, 0),
4328 F_PCM( 512000, pll4, 4, 1, 192),
4329 F_PCM( 768000, pll4, 4, 1, 128),
4330 F_PCM( 1024000, pll4, 4, 1, 96),
4331 F_PCM( 1536000, pll4, 4, 1, 64),
4332 F_PCM( 2048000, pll4, 4, 1, 48),
4333 F_PCM( 3072000, pll4, 4, 1, 32),
4334 F_PCM( 4096000, pll4, 4, 1, 24),
4335 F_PCM( 6144000, pll4, 4, 1, 16),
4336 F_PCM( 8192000, pll4, 4, 1, 12),
4337 F_PCM(12288000, pll4, 4, 1, 8),
4338 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004339 F_END
4340};
4341
4342static struct rcg_clk pcm_clk = {
4343 .b = {
4344 .ctl_reg = LCC_PCM_NS_REG,
4345 .en_mask = BIT(11),
4346 .reset_reg = LCC_PCM_NS_REG,
4347 .reset_mask = BIT(13),
4348 .halt_reg = LCC_PCM_STATUS_REG,
4349 .halt_check = ENABLE,
4350 .halt_bit = 0,
4351 },
4352 .ns_reg = LCC_PCM_NS_REG,
4353 .md_reg = LCC_PCM_MD_REG,
4354 .root_en_mask = BIT(9),
4355 .ns_mask = (BM(31, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004356 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004357 .set_rate = set_rate_mnd,
4358 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004359 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004360 .c = {
4361 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004362 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004363 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004364 CLK_INIT(pcm_clk.c),
4365 },
4366};
4367
4368static struct rcg_clk audio_slimbus_clk = {
4369 .b = {
4370 .ctl_reg = LCC_SLIMBUS_NS_REG,
4371 .en_mask = BIT(10),
4372 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4373 .reset_mask = BIT(5),
4374 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4375 .halt_check = ENABLE,
4376 .halt_bit = 0,
4377 },
4378 .ns_reg = LCC_SLIMBUS_NS_REG,
4379 .md_reg = LCC_SLIMBUS_MD_REG,
4380 .root_en_mask = BIT(9),
4381 .ns_mask = (BM(31, 24) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004382 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004383 .set_rate = set_rate_mnd,
4384 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004385 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004386 .c = {
4387 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004388 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004389 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004390 CLK_INIT(audio_slimbus_clk.c),
4391 },
4392};
4393
4394static struct branch_clk sps_slimbus_clk = {
4395 .b = {
4396 .ctl_reg = LCC_SLIMBUS_NS_REG,
4397 .en_mask = BIT(12),
4398 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4399 .halt_check = ENABLE,
4400 .halt_bit = 1,
4401 },
4402 .parent = &audio_slimbus_clk.c,
4403 .c = {
4404 .dbg_name = "sps_slimbus_clk",
4405 .ops = &clk_ops_branch,
4406 CLK_INIT(sps_slimbus_clk.c),
4407 },
4408};
4409
4410static struct branch_clk slimbus_xo_src_clk = {
4411 .b = {
4412 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4413 .en_mask = BIT(2),
4414 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004415 .halt_bit = 28,
4416 },
4417 .parent = &sps_slimbus_clk.c,
4418 .c = {
4419 .dbg_name = "slimbus_xo_src_clk",
4420 .ops = &clk_ops_branch,
4421 CLK_INIT(slimbus_xo_src_clk.c),
4422 },
4423};
4424
Matt Wagantall735f01a2011-08-12 12:40:28 -07004425DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4426DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4427DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4428DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4429DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4430DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4431DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4432DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004433
Stephen Boydd7a143a2012-02-16 17:59:26 -08004434static DEFINE_CLK_VOTER(sfab_msmbus_a_clk, &sfab_a_clk.c);
4435static DEFINE_CLK_VOTER(sfab_tmr_a_clk, &sfab_a_clk.c);
4436
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004437static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4438static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
Manu Gautam7483f172011-11-08 15:22:26 +05304439static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c);
4440static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004441static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4442static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4443static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4444static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4445static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4446static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
Stephen Boyd1c51a492011-10-26 12:11:47 -07004447static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c);
Stephen Boydef5d1c42011-12-15 20:47:14 -08004448static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c);
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08004449static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c);
Ramesh Masavarapueb6e9342012-02-13 19:59:50 -08004450static DEFINE_CLK_VOTER(dfab_tzcom_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004451
4452static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
Stephen Boyd36466ae2012-01-18 20:58:27 -08004453static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004454
4455#ifdef CONFIG_DEBUG_FS
4456struct measure_sel {
4457 u32 test_vector;
4458 struct clk *clk;
4459};
4460
Matt Wagantall8b38f942011-08-02 18:23:18 -07004461static DEFINE_CLK_MEASURE(l2_m_clk);
4462static DEFINE_CLK_MEASURE(krait0_m_clk);
4463static DEFINE_CLK_MEASURE(krait1_m_clk);
Tianyi Gou455c13c2012-02-02 16:33:24 -08004464static DEFINE_CLK_MEASURE(krait2_m_clk);
4465static DEFINE_CLK_MEASURE(krait3_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004466static DEFINE_CLK_MEASURE(q6sw_clk);
4467static DEFINE_CLK_MEASURE(q6fw_clk);
4468static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004469
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004470static struct measure_sel measure_mux[] = {
4471 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4472 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4473 { TEST_PER_LS(0x13), &sdc1_clk.c },
4474 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4475 { TEST_PER_LS(0x15), &sdc2_clk.c },
4476 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4477 { TEST_PER_LS(0x17), &sdc3_clk.c },
4478 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4479 { TEST_PER_LS(0x19), &sdc4_clk.c },
4480 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4481 { TEST_PER_LS(0x1B), &sdc5_clk.c },
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004482 { TEST_PER_LS(0x1F), &gp0_clk.c },
4483 { TEST_PER_LS(0x20), &gp1_clk.c },
4484 { TEST_PER_LS(0x21), &gp2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004485 { TEST_PER_LS(0x25), &dfab_clk.c },
4486 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4487 { TEST_PER_LS(0x26), &pmem_clk.c },
4488 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4489 { TEST_PER_LS(0x33), &cfpb_clk.c },
4490 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4491 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4492 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4493 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4494 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4495 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4496 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4497 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4498 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4499 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4500 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4501 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4502 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4503 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4504 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4505 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4506 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4507 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4508 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4509 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4510 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4511 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4512 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4513 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4514 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4515 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4516 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4517 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4518 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4519 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4520 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4521 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4522 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4523 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4524 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4525 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4526 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004527 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4528 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4529 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4530 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4531 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4532 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4533 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4534 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4535 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004536 { TEST_PER_LS(0x78), &sfpb_clk.c },
4537 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4538 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4539 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4540 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4541 { TEST_PER_LS(0x7D), &prng_clk.c },
4542 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4543 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4544 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4545 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004546 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4547 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4548 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004549 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4550 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4551 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4552 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4553 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4554 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4555 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4556 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4557 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4558 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004559 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004560 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4561
4562 { TEST_PER_HS(0x07), &afab_clk.c },
4563 { TEST_PER_HS(0x07), &afab_a_clk.c },
4564 { TEST_PER_HS(0x18), &sfab_clk.c },
4565 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004566 { TEST_PER_HS(0x26), &q6sw_clk },
4567 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004568 { TEST_PER_HS(0x2A), &adm0_clk.c },
4569 { TEST_PER_HS(0x34), &ebi1_clk.c },
4570 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004571 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004572
4573 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4574 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4575 { TEST_MM_LS(0x02), &cam1_clk.c },
4576 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004577 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004578 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4579 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4580 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4581 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4582 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4583 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4584 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4585 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4586 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4587 { TEST_MM_LS(0x12), &imem_p_clk.c },
4588 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4589 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4590 { TEST_MM_LS(0x16), &rot_p_clk.c },
4591 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4592 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4593 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4594 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4595 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4596 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4597 { TEST_MM_LS(0x1D), &cam0_clk.c },
4598 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4599 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4600 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4601 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4602 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4603 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4604 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4605 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004606 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004607 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004608
4609 { TEST_MM_HS(0x00), &csi0_clk.c },
4610 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004611 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004612 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4613 { TEST_MM_HS(0x06), &vfe_clk.c },
4614 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4615 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4616 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4617 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4618 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4619 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4620 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4621 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4622 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4623 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4624 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4625 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4626 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4627 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4628 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4629 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4630 { TEST_MM_HS(0x1A), &mdp_clk.c },
4631 { TEST_MM_HS(0x1B), &rot_clk.c },
4632 { TEST_MM_HS(0x1C), &vpe_clk.c },
4633 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4634 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4635 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4636 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4637 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4638 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4639 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4640 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4641 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4642 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4643 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004644 { TEST_MM_HS(0x2D), &csi2_clk.c },
4645 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4646 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4647 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4648 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4649 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004650 { TEST_MM_HS(0x33), &vcap_clk.c },
4651 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Gou7747a962012-02-03 15:03:55 -08004652 { TEST_MM_HS(0x35), &vcap_axi_clk.c },
Tianyi Gou51918802012-01-26 14:05:43 -08004653 { TEST_MM_HS(0x36), &rgb_tv_clk.c },
4654 { TEST_MM_HS(0x37), &npl_tv_clk.c },
Tianyi Gou7747a962012-02-03 15:03:55 -08004655 { TEST_MM_HS(0x38), &gfx3d_axi_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004656
4657 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4658 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4659 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4660 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4661 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4662 { TEST_LPA(0x14), &pcm_clk.c },
4663 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004664
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004665 { TEST_LPA_HS(0x00), &q6_func_clk },
4666
Stephen Boyd46fdf0d2011-11-22 12:25:09 -08004667 { TEST_CPUL2(0x2), &l2_m_clk },
4668 { TEST_CPUL2(0x0), &krait0_m_clk },
4669 { TEST_CPUL2(0x1), &krait1_m_clk },
Tianyi Gou455c13c2012-02-02 16:33:24 -08004670 { TEST_CPUL2(0x4), &krait2_m_clk },
4671 { TEST_CPUL2(0x5), &krait3_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004672};
4673
4674static struct measure_sel *find_measure_sel(struct clk *clk)
4675{
4676 int i;
4677
4678 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4679 if (measure_mux[i].clk == clk)
4680 return &measure_mux[i];
4681 return NULL;
4682}
4683
Matt Wagantall8b38f942011-08-02 18:23:18 -07004684static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004685{
4686 int ret = 0;
4687 u32 clk_sel;
4688 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004689 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004690 unsigned long flags;
4691
4692 if (!parent)
4693 return -EINVAL;
4694
4695 p = find_measure_sel(parent);
4696 if (!p)
4697 return -EINVAL;
4698
4699 spin_lock_irqsave(&local_clock_reg_lock, flags);
4700
Matt Wagantall8b38f942011-08-02 18:23:18 -07004701 /*
4702 * Program the test vector, measurement period (sample_ticks)
4703 * and scaling multiplier.
4704 */
4705 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004706 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004707 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004708 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4709 case TEST_TYPE_PER_LS:
4710 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4711 break;
4712 case TEST_TYPE_PER_HS:
4713 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4714 break;
4715 case TEST_TYPE_MM_LS:
4716 writel_relaxed(0x4030D97, CLK_TEST_REG);
4717 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4718 break;
4719 case TEST_TYPE_MM_HS:
4720 writel_relaxed(0x402B800, CLK_TEST_REG);
4721 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4722 break;
4723 case TEST_TYPE_LPA:
4724 writel_relaxed(0x4030D98, CLK_TEST_REG);
4725 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4726 LCC_CLK_LS_DEBUG_CFG_REG);
4727 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004728 case TEST_TYPE_LPA_HS:
4729 writel_relaxed(0x402BC00, CLK_TEST_REG);
4730 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4731 LCC_CLK_HS_DEBUG_CFG_REG);
4732 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004733 case TEST_TYPE_CPUL2:
4734 writel_relaxed(0x4030400, CLK_TEST_REG);
4735 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4736 clk->sample_ticks = 0x4000;
4737 clk->multiplier = 2;
4738 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004739 default:
4740 ret = -EPERM;
4741 }
4742 /* Make sure test vector is set before starting measurements. */
4743 mb();
4744
4745 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4746
4747 return ret;
4748}
4749
4750/* Sample clock for 'ticks' reference clock ticks. */
4751static u32 run_measurement(unsigned ticks)
4752{
4753 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004754 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4755
4756 /* Wait for timer to become ready. */
4757 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4758 cpu_relax();
4759
4760 /* Run measurement and wait for completion. */
4761 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4762 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4763 cpu_relax();
4764
4765 /* Stop counters. */
4766 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4767
4768 /* Return measured ticks. */
4769 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4770}
4771
4772
4773/* Perform a hardware rate measurement for a given clock.
4774 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004775static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004776{
4777 unsigned long flags;
4778 u32 pdm_reg_backup, ringosc_reg_backup;
4779 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004780 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004781 unsigned ret;
4782
Stephen Boyde334aeb2012-01-24 12:17:29 -08004783 ret = clk_prepare_enable(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004784 if (ret) {
4785 pr_warning("CXO clock failed to enable. Can't measure\n");
4786 return 0;
4787 }
4788
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004789 spin_lock_irqsave(&local_clock_reg_lock, flags);
4790
4791 /* Enable CXO/4 and RINGOSC branch and root. */
4792 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4793 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4794 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4795 writel_relaxed(0xA00, RINGOSC_NS_REG);
4796
4797 /*
4798 * The ring oscillator counter will not reset if the measured clock
4799 * is not running. To detect this, run a short measurement before
4800 * the full measurement. If the raw results of the two are the same
4801 * then the clock must be off.
4802 */
4803
4804 /* Run a short measurement. (~1 ms) */
4805 raw_count_short = run_measurement(0x1000);
4806 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004807 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004808
4809 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4810 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4811
4812 /* Return 0 if the clock is off. */
4813 if (raw_count_full == raw_count_short)
4814 ret = 0;
4815 else {
4816 /* Compute rate in Hz. */
4817 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004818 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4819 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004820 }
4821
4822 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004823 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004824 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4825
Stephen Boyde334aeb2012-01-24 12:17:29 -08004826 clk_disable_unprepare(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004827
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004828 return ret;
4829}
4830#else /* !CONFIG_DEBUG_FS */
4831static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4832{
4833 return -EINVAL;
4834}
4835
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004836static unsigned long measure_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004837{
4838 return 0;
4839}
4840#endif /* CONFIG_DEBUG_FS */
4841
4842static struct clk_ops measure_clk_ops = {
4843 .set_parent = measure_clk_set_parent,
4844 .get_rate = measure_clk_get_rate,
4845 .is_local = local_clk_is_local,
4846};
4847
Matt Wagantall8b38f942011-08-02 18:23:18 -07004848static struct measure_clk measure_clk = {
4849 .c = {
4850 .dbg_name = "measure_clk",
4851 .ops = &measure_clk_ops,
4852 CLK_INIT(measure_clk.c),
4853 },
4854 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004855};
4856
Tianyi Goua8b3cce2011-11-08 14:37:26 -08004857static struct clk_lookup msm_clocks_8064[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08004858 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
4859 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Stephen Boyd7dd22662012-01-26 16:09:31 -08004860 CLK_LOOKUP("xo", cxo_clk.c, "msm_otg"),
Stephen Boyded630b02012-01-26 15:26:47 -08004861 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
4862 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
4863 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
4864 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
4865 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Matt Wagantall292aace2012-01-26 19:12:34 -08004866 CLK_LOOKUP("xo", cxo_clk.c, "pil_gss"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08004867 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyded630b02012-01-26 15:26:47 -08004868 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
4869 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
4870 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
4871 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004872
Tianyi Gou21a0e802012-02-04 22:34:10 -08004873 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
4874 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
4875 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
4876 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
4877 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08004878 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08004879 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
4880 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
4881 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
4882 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
4883 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
4884 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08004885
Tianyi Gou21a0e802012-02-04 22:34:10 -08004886 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, ""),
4887 CLK_LOOKUP("dfab_clk", dfab_clk.c, ""),
4888 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, ""),
4889 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, ""),
4890 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
4891 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004892
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004893 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
4894 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
4895 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004896 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004897 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
4898 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
4899 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
4900 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""),
4901 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004902 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"),
David Keitel3c40fc52012-02-09 17:53:52 -08004903 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004904 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08004905 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08004906 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08004907 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004908 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
4909 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
4910 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Tianyi Gou50f23812012-02-06 16:04:19 -08004911 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Tianyi Gou05e01102012-02-08 22:15:49 -08004912 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004913 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
4914 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
4915 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
4916 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004917 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
4918 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08004919 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
4920 CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"),
4921 CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004922 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
4923 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
4924 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
4925 CLK_LOOKUP("iface_clk", ce1_p_clk.c, ""),
4926 CLK_LOOKUP("core_clk", ce1_core_clk.c, ""),
4927 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""),
4928 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07004929 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
4930 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
4931 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
4932 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
4933 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
4934 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004935 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004936 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"),
David Keitel3c40fc52012-02-09 17:53:52 -08004937 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004938 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08004939 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08004940 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08004941 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004942 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004943 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, "msm_serial_hsl.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004944 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
4945 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08004946 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Manu Gautam7483f172011-11-08 15:22:26 +05304947 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"),
4948 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004949 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
4950 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
4951 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
4952 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004953 CLK_LOOKUP("iface_clk", pcie_p_clk.c, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07004954 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
4955 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004956 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
4957 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
4958 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
4959 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
4960 CLK_LOOKUP("core_clk", amp_clk.c, ""),
Kevin Chand07220e2012-02-13 15:52:22 -08004961 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
Sreesudhan Ramakrish Ramkumar6c6f57c2012-02-21 15:12:44 -08004962 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"),
Kevin Chand07220e2012-02-13 15:52:22 -08004963 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"),
4964 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
4965 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
4966 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
4967 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
4968 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
4969 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
4970 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
4971 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
4972 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
4973 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
4974 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
4975 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
4976 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
4977 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
4978 CLK_LOOKUP("csiphy_timer_src_clk",
4979 csiphy_timer_src_clk.c, "msm_csiphy.0"),
4980 CLK_LOOKUP("csiphy_timer_src_clk",
4981 csiphy_timer_src_clk.c, "msm_csiphy.1"),
4982 CLK_LOOKUP("csiphy_timer_src_clk",
4983 csiphy_timer_src_clk.c, "msm_csiphy.2"),
4984 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
4985 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
4986 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08004987 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
4988 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
4989 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
4990 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Tianyi Gou51918802012-01-26 14:05:43 -08004991 CLK_LOOKUP("rgb_clk", rgb_tv_clk.c, ""),
4992 CLK_LOOKUP("npl_clk", npl_tv_clk.c, ""),
4993
Pu Chen86b4be92011-11-03 17:27:57 -07004994 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004995 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
4996 CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004997 CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004998 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
4999 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005000 CLK_LOOKUP("core_clk", vcap_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005001 CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005002 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005003 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005004 CLK_LOOKUP("mem_clk", imem_axi_clk.c, ""),
5005 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005006 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005007 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005008 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005009 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005010 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005011 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005012 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005013 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005014 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005015 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Matt Wagantall61286312012-02-22 15:55:09 -08005016 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005017 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
5018 CLK_LOOKUP("tv_src_div_clk", tv_src_div_clk.c, NULL),
Greg Griscofa47b532011-11-11 10:32:06 -08005019 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005020 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005021 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
Tianyi Gou51918802012-01-26 14:05:43 -08005022 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005023 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
5024 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
5025 CLK_LOOKUP("vpe_clk", vpe_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005026 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chand07220e2012-02-13 15:52:22 -08005027 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005028 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chand07220e2012-02-13 15:52:22 -08005029 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005030 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5031 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5032 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5033 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5034 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5035 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5036 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005037 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Kevin Chand07220e2012-02-13 15:52:22 -08005038 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5039 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
5040 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005041 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5042 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5043 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5044 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Pu Chen86b4be92011-11-03 17:27:57 -07005045 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005046 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005047 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5048 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005049 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005050 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005051 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005052 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005053 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005054 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005055 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005056 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005057 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Greg Griscofa47b532011-11-11 10:32:06 -08005058 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005059 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chand07220e2012-02-13 15:52:22 -08005060 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005061 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chanb20742b2012-02-27 15:47:35 -08005062 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall61286312012-02-22 15:55:09 -08005063 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005064
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005065 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
5066 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
5067 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5068 "msm-dai-q6.1"),
5069 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5070 "msm-dai-q6.1"),
5071 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5072 "msm-dai-q6.5"),
5073 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5074 "msm-dai-q6.5"),
5075 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5076 "msm-dai-q6.16384"),
5077 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5078 "msm-dai-q6.16384"),
5079 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5080 "msm-dai-q6.4"),
5081 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5082 "msm-dai-q6.4"),
5083 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005084 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005085 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005086 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""),
5087 CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""),
5088 CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""),
5089 CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""),
5090 CLK_LOOKUP("core_clk", rot_axi_clk.c, ""),
5091 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""),
5092 CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""),
5093 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""),
5094 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""),
5095 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005096
5097 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5098 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5099 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.0"),
5100 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.1"),
5101 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5102 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5103 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5104 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5105 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5106 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5107 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08005108 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
Ramesh Masavarapueb6e9342012-02-13 19:59:50 -08005109 CLK_LOOKUP("bus_clk", dfab_tzcom_clk.c, "tzcom"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005110
Manu Gautam5143b252012-01-05 19:25:23 -08005111 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5112 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5113 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5114 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5115 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005116
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005117 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5118 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5119 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5120 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5121 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5122 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5123 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5124 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5125 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5126 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.9"),
5127 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.10"),
5128 CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"),
5129
Jeff Ohlstein8c116c72011-10-27 17:34:48 -07005130 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005131
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005132 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5133 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5134 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
Tianyi Gou455c13c2012-02-02 16:33:24 -08005135 CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""),
5136 CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005137};
5138
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005139static struct clk_lookup msm_clocks_8960[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08005140 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
5141 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Stephen Boyd7dd22662012-01-26 16:09:31 -08005142 CLK_LOOKUP("xo", cxo_clk.c, "msm_otg"),
Stephen Boyded630b02012-01-26 15:26:47 -08005143 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5144 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5145 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5146 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5147 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08005148 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyded630b02012-01-26 15:26:47 -08005149 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5150 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5151 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5152 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005153
Matt Wagantallb2710b82011-11-16 19:55:17 -08005154 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
5155 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
5156 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5157 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5158 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08005159 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005160 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5161 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5162 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5163 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5164 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
5165 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
5166
5167 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
5168 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
5169 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
5170 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5171 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5172 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005173
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005174 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5175 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5176 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5177 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5178 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5179 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5180 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
Matt Wagantalle2522372011-08-17 14:52:21 -07005181 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5182 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005183 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
5184 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""),
5185 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
5186 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5187 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5188 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005189 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005190 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005191 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5192 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005193 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5194 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5195 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5196 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
Harini Jayaramanfe6ff4162012-03-14 11:25:40 -06005197 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"),
Matt Wagantallac294852011-08-17 15:44:58 -07005198 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005199 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005200 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005201 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005202 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005203 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005204 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5205 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5206 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5207 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5208 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005209 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005210 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5211 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005212 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5213 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005214 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5215 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5216 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5217 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5218 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5219 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005220 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5221 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5222 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5223 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5224 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005225 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005226 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005227 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005228 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005229 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005230 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005231 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005232 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5233 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005234 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5235 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005236 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
5237 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
Harini Jayaramanfe6ff4162012-03-14 11:25:40 -06005238 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"),
Matt Wagantallac294852011-08-17 15:44:58 -07005239 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005240 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005241 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005242 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
5243 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5244 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005245 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005246 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5247 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5248 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5249 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5250 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005251 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5252 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005253 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5254 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5255 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5256 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
5257 CLK_LOOKUP("core_clk", amp_clk.c, ""),
Kevin Chan09f4e662011-12-16 08:17:02 -08005258 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
5259 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
5260 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005261 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
Sreesudhan Ramakrish Ramkumar8f11b8b2012-01-04 17:09:05 -08005262 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005263 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5264 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005265 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005266 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5267 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005268 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005269 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5270 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005271 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
Kevin Chane12c6672011-10-26 11:55:26 -07005272 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5273 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005274 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5275 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5276 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5277 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5278 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5279 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5280 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
Kevin Chanf6216f22011-10-25 18:40:11 -07005281 CLK_LOOKUP("csiphy_timer_src_clk",
5282 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5283 CLK_LOOKUP("csiphy_timer_src_clk",
5284 csiphy_timer_src_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005285 CLK_LOOKUP("csiphy_timer_src_clk",
5286 csiphy_timer_src_clk.c, "msm_csiphy.2"),
Kevin Chanf6216f22011-10-25 18:40:11 -07005287 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5288 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005289 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005290 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5291 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5292 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5293 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005294 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005295 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005296 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005297 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005298 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005299 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5300 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Jignesh Mehta95dd6e12011-11-18 17:21:16 -08005301 CLK_LOOKUP("imem_clk", imem_axi_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005302 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005303 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005304 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005305 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005306 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005307 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005308 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005309 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005310 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005311 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005312 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005313 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005314 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005315 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
5316 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005317 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005318 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005319 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005320 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005321 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005322 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Kevin Chana0853122011-11-07 19:48:44 -08005323 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005324 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chan5827c552011-10-28 18:36:32 -07005325 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005326 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chan5827c552011-10-28 18:36:32 -07005327 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005328 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5329 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5330 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5331 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5332 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5333 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5334 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005335 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005336 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5337 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005338 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005339 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5340 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5341 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5342 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005343 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005344 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005345 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005346 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005347 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005348 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005349 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5350 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005351 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005352 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005353 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005354 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005355 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005356 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005357 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005358 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005359 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005360 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005361 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005362 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chan5827c552011-10-28 18:36:32 -07005363 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005364 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chana0853122011-11-07 19:48:44 -08005365 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005366 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005367 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
5368 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
5369 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5370 "msm-dai-q6.1"),
5371 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5372 "msm-dai-q6.1"),
5373 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5374 "msm-dai-q6.5"),
5375 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5376 "msm-dai-q6.5"),
5377 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5378 "msm-dai-q6.16384"),
5379 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5380 "msm-dai-q6.16384"),
5381 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5382 "msm-dai-q6.4"),
5383 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5384 "msm-dai-q6.4"),
5385 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005386 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005387 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005388 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5389 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5390 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5391 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5392 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5393 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5394 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5395 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5396 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5397 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
5398 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5399 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005400
5401 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5402 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5403 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5404 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5405 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
5406
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005407 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005408 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005409 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5410 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5411 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5412 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5413 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005414 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005415 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Stephen Boydef5d1c42011-12-15 20:47:14 -08005416 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08005417 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
Ramesh Masavarapueb6e9342012-02-13 19:59:50 -08005418 CLK_LOOKUP("bus_clk", dfab_tzcom_clk.c, "tzcom"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005419
Matt Wagantalle1a86062011-08-18 17:46:10 -07005420 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005421
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005422 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5423 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5424 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5425 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5426 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5427 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005428};
5429
5430/*
5431 * Miscellaneous clock register initializations
5432 */
5433
5434/* Read, modify, then write-back a register. */
5435static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5436{
5437 uint32_t regval = readl_relaxed(reg);
5438 regval &= ~mask;
5439 regval |= val;
5440 writel_relaxed(regval, reg);
5441}
5442
Tianyi Gou41515e22011-09-01 19:37:43 -07005443static void __init set_fsm_mode(void __iomem *mode_reg)
5444{
5445 u32 regval = readl_relaxed(mode_reg);
5446
5447 /*De-assert reset to FSM */
5448 regval &= ~BIT(21);
5449 writel_relaxed(regval, mode_reg);
5450
5451 /* Program bias count */
Tianyi Gou358c3862011-10-18 17:03:41 -07005452 regval &= ~BM(19, 14);
5453 regval |= BVAL(19, 14, 0x1);
5454 writel_relaxed(regval, mode_reg);
5455
5456 /* Program lock count */
Tianyi Gou41515e22011-09-01 19:37:43 -07005457 regval &= ~BM(13, 8);
5458 regval |= BVAL(13, 8, 0x8);
5459 writel_relaxed(regval, mode_reg);
5460
5461 /*Enable PLL FSM voting */
5462 regval |= BIT(20);
5463 writel_relaxed(regval, mode_reg);
5464}
5465
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005466static void __init reg_init(void)
5467{
Stephen Boydd471e7a2011-11-19 01:37:39 -08005468 void __iomem *imem_reg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005469 /* Deassert MM SW_RESET_ALL signal. */
5470 writel_relaxed(0, SW_RESET_ALL_REG);
5471
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005472 /*
5473 * Some bits are only used on either 8960 or 8064 and are marked as
5474 * reserved bits on the other SoC. Writing to these reserved bits
5475 * should have no effect.
5476 */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005477 /*
5478 * Initialize MM AHB registers: Enable the FPB clock and disable HW
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005479 * gating on non-8960 for all clocks. Also set VFE_AHB's
Stephen Boydd471e7a2011-11-19 01:37:39 -08005480 * FORCE_CORE_ON bit to prevent its memory from being collapsed when
5481 * the clock is halted. The sleep and wake-up delays are set to safe
5482 * values.
5483 */
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005484 if (cpu_is_msm8960()) {
Stephen Boydd471e7a2011-11-19 01:37:39 -08005485 rmwreg(0x44000000, AHB_EN_REG, 0x6C000103);
5486 writel_relaxed(0x3C7097F9, AHB_EN2_REG);
5487 } else {
5488 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
5489 writel_relaxed(0x000007F9, AHB_EN2_REG);
5490 }
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005491 if (cpu_is_apq8064())
5492 rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005493
5494 /* Deassert all locally-owned MM AHB resets. */
5495 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07005496 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005497
5498 /* Initialize MM AXI registers: Enable HW gating for all clocks that
5499 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
5500 * delays to safe values. */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005501 if (cpu_is_msm8960() &&
5502 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) {
5503 rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF);
5504 rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -08005505 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08005506 } else {
5507 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
5508 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
5509 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
5510 }
Matt Wagantall53d968f2011-07-19 13:22:53 -07005511 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005512 if (cpu_is_apq8064())
5513 rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005514 if (cpu_is_msm8960())
Stephen Boydd471e7a2011-11-19 01:37:39 -08005515 rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF);
5516 else
5517 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
5518
5519 /* Enable IMEM's clk_on signal */
5520 imem_reg = ioremap(0x04b00040, 4);
5521 if (imem_reg) {
5522 writel_relaxed(0x3, imem_reg);
5523 iounmap(imem_reg);
5524 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005525
5526 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
5527 * memories retain state even when not clocked. Also, set sleep and
5528 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005529 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
5530 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
5531 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
5532 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
5533 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
5534 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
Tarun Karra6fbc00a2011-12-13 09:23:47 -07005535 rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005536 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
5537 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
5538 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
5539 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
5540 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005541 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
5542 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
5543 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005544 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005545 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005546 if (cpu_is_msm8960() || cpu_is_msm8930()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005547 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
5548 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
5549 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
5550 }
5551 if (cpu_is_apq8064()) {
5552 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07005553 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005554 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005555
Tianyi Gou41515e22011-09-01 19:37:43 -07005556 /*
5557 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
5558 * core remain active during halt state of the clk. Also, set sleep
5559 * and wake-up value to max.
5560 */
5561 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005562 if (cpu_is_apq8064()) {
5563 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
5564 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
5565 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005566
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005567 /* De-assert MM AXI resets to all hardware blocks. */
5568 writel_relaxed(0, SW_RESET_AXI_REG);
5569
5570 /* Deassert all MM core resets. */
5571 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005572 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005573
5574 /* Reset 3D core once more, with its clock enabled. This can
5575 * eventually be done as part of the GDFS footswitch driver. */
5576 clk_set_rate(&gfx3d_clk.c, 27000000);
Stephen Boyde334aeb2012-01-24 12:17:29 -08005577 clk_prepare_enable(&gfx3d_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005578 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
5579 mb();
5580 udelay(5);
5581 writel_relaxed(0, SW_RESET_CORE_REG);
5582 /* Make sure reset is de-asserted before clock is disabled. */
5583 mb();
Stephen Boyde334aeb2012-01-24 12:17:29 -08005584 clk_disable_unprepare(&gfx3d_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005585
5586 /* Enable TSSC and PDM PXO sources. */
5587 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
5588 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
5589
5590 /* Source SLIMBus xo src from slimbus reference clock */
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005591 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005592 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005593
5594 /* Source the dsi_byte_clks from the DSI PHY PLLs */
5595 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
5596 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07005597
5598 /* Source the sata_phy_ref_clk from PXO */
5599 if (cpu_is_apq8064())
5600 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
5601
5602 /*
Tianyi Gou05e01102012-02-08 22:15:49 -08005603 * TODO: Programming below PLLs and prng_clk is temporary and
5604 * needs to be removed after bootloaders program them.
Tianyi Gou41515e22011-09-01 19:37:43 -07005605 */
5606 if (cpu_is_apq8064()) {
Tianyi Gou317aa862012-02-06 14:31:07 -08005607 u32 is_pll_enabled;
Tianyi Gou41515e22011-09-01 19:37:43 -07005608
5609 /* Program pxo_src_clk to source from PXO */
5610 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
5611
Tianyi Gou41515e22011-09-01 19:37:43 -07005612 /* Check if PLL14 is active */
5613 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
5614 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005615 /* Ref clk = 27MHz and program pll14 to 480MHz */
Tianyi Gou317aa862012-02-06 14:31:07 -08005616 writel_relaxed(0x00031011, BB_PLL14_L_VAL_REG);
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005617 writel_relaxed(0x7, BB_PLL14_M_VAL_REG);
5618 writel_relaxed(0x9, BB_PLL14_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005619
Tianyi Gou317aa862012-02-06 14:31:07 -08005620 /*
5621 * Enable the main output and the MN accumulator
5622 * Set pre-divider and post-divider values to 1 and 1
5623 */
5624 writel_relaxed(0x00C00000, BB_PLL14_CONFIG_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005625
Tianyi Gou41515e22011-09-01 19:37:43 -07005626 set_fsm_mode(BB_PLL14_MODE_REG);
5627 }
Tianyi Gou621f8742011-09-01 21:45:01 -07005628
Tianyi Gou621f8742011-09-01 21:45:01 -07005629 /* Program PLL15 to 975MHz with ref clk = 27MHz */
Tianyi Gou317aa862012-02-06 14:31:07 -08005630 writel_relaxed(0x31024, MM_PLL3_L_VAL_REG);
5631 writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
5632 writel_relaxed(0x9, MM_PLL3_N_VAL_REG);
Tianyi Gou621f8742011-09-01 21:45:01 -07005633
Tianyi Gou317aa862012-02-06 14:31:07 -08005634 writel_relaxed(0xC20000, MM_PLL3_CONFIG_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005635
5636 /* Check if PLL4 is active */
5637 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
5638 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005639 /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
5640 writel_relaxed(0xE, LCC_PLL0_L_VAL_REG);
5641 writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG);
5642 writel_relaxed(0x465, LCC_PLL0_N_VAL_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005643
Tianyi Gou317aa862012-02-06 14:31:07 -08005644 writel_relaxed(0xC00000, LCC_PLL0_CONFIG_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005645
5646 set_fsm_mode(LCC_PLL0_MODE_REG);
5647 }
5648
5649 /* Enable PLL4 source on the LPASS Primary PLL Mux */
5650 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou05e01102012-02-08 22:15:49 -08005651
5652 /* Program prng_clk to 64MHz if it isn't configured */
5653 if (!readl_relaxed(PRNG_CLK_NS_REG))
5654 writel_relaxed(0x2B, PRNG_CLK_NS_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005655 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005656}
5657
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005658/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07005659static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005660{
Stephen Boyd72a80352012-01-26 15:57:38 -08005661 /* Keep PXO on whenever APPS cpu is active */
5662 clk_prepare_enable(&pxo_a_clk.c);
Tianyi Gou41515e22011-09-01 19:37:43 -07005663
Saravana Kannan298ec392012-02-08 19:21:47 -08005664 if (cpu_is_apq8064()) {
5665 vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8064;
Tianyi Goue1faaf22012-01-24 16:07:19 -08005666 } else if (cpu_is_msm8930() || cpu_is_msm8627()) {
Saravana Kannan298ec392012-02-08 19:21:47 -08005667 vdd_dig.set_vdd = set_vdd_dig_8930;
5668 vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8930;
Tianyi Goue1faaf22012-01-24 16:07:19 -08005669 }
Tianyi Goubf3d0b12012-01-23 14:37:28 -08005670
Tianyi Gou41515e22011-09-01 19:37:43 -07005671 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005672 * Change the freq tables for and voltage requirements for
5673 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07005674 */
5675 if (cpu_is_apq8064()) {
5676 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005677
5678 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
5679 sizeof(gfx3d_clk.c.fmax));
5680 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
5681 sizeof(ijpeg_clk.c.fmax));
5682 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
5683 sizeof(ijpeg_clk.c.fmax));
5684 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
5685 sizeof(tv_src_clk.c.fmax));
5686 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
5687 sizeof(vfe_clk.c.fmax));
5688
Tianyi Gou621f8742011-09-01 21:45:01 -07005689 gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07005690 }
Stephen Boyd94625ef2011-07-12 17:06:01 -07005691
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005692 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005693
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07005694 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005695
5696 /* Initialize clock registers. */
5697 reg_init();
5698
5699 /* Initialize rates for clocks that only support one. */
5700 clk_set_rate(&pdm_clk.c, 27000000);
5701 clk_set_rate(&prng_clk.c, 64000000);
5702 clk_set_rate(&mdp_vsync_clk.c, 27000000);
5703 clk_set_rate(&tsif_ref_clk.c, 105000);
5704 clk_set_rate(&tssc_clk.c, 27000000);
5705 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07005706 if (cpu_is_apq8064()) {
5707 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
5708 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
5709 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005710 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005711 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou41515e22011-09-01 19:37:43 -07005712 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005713 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
5714 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
5715 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Lena Salman127823f2012-02-14 17:13:53 +02005716 clk_set_rate(&usb_hsic_system_clk.c, 60000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07005717 /*
5718 * Set the CSI rates to a safe default to avoid warnings when
5719 * switching csi pix and rdi clocks.
5720 */
5721 clk_set_rate(&csi0_src_clk.c, 27000000);
5722 clk_set_rate(&csi1_src_clk.c, 27000000);
5723 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005724
5725 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07005726 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005727 * Toggle these clocks on and off to refresh them.
5728 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07005729 rcg_clk_enable(&pdm_clk.c);
5730 rcg_clk_disable(&pdm_clk.c);
5731 rcg_clk_enable(&tssc_clk.c);
5732 rcg_clk_disable(&tssc_clk.c);
Stephen Boyde334aeb2012-01-24 12:17:29 -08005733 clk_prepare_enable(&usb_hsic_hsic_clk.c);
5734 clk_disable_unprepare(&usb_hsic_hsic_clk.c);
Stephen Boydd7a143a2012-02-16 17:59:26 -08005735
5736 /*
5737 * Keep sfab floor @ 54MHz so that Krait AHB is at least 27MHz at all
5738 * times when Apps CPU is active. This ensures the timer's requirement
5739 * of Krait AHB running 4 times as fast as the timer itself.
5740 */
5741 clk_set_rate(&sfab_tmr_a_clk.c, 54000000);
Stephen Boyde334aeb2012-01-24 12:17:29 -08005742 clk_prepare_enable(&sfab_tmr_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005743}
5744
Stephen Boydbb600ae2011-08-02 20:11:40 -07005745static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005746{
Stephen Boyda3787f32011-09-16 18:55:13 -07005747 int rc;
5748 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07005749 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07005750
5751 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
5752 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
5753 PTR_ERR(mmfpb_a_clk)))
5754 return PTR_ERR(mmfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08005755 rc = clk_set_rate(mmfpb_a_clk, 76800000);
Stephen Boyda3787f32011-09-16 18:55:13 -07005756 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
5757 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08005758 rc = clk_prepare_enable(mmfpb_a_clk);
Stephen Boyda3787f32011-09-16 18:55:13 -07005759 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
5760 return rc;
5761
Stephen Boyd85436132011-09-16 18:55:13 -07005762 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
5763 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
5764 PTR_ERR(cfpb_a_clk)))
5765 return PTR_ERR(cfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08005766 rc = clk_set_rate(cfpb_a_clk, 64000000);
Stephen Boyd85436132011-09-16 18:55:13 -07005767 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
5768 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08005769 rc = clk_prepare_enable(cfpb_a_clk);
Stephen Boyd85436132011-09-16 18:55:13 -07005770 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
5771 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005772
5773 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005774}
Stephen Boydbb600ae2011-08-02 20:11:40 -07005775
5776struct clock_init_data msm8960_clock_init_data __initdata = {
5777 .table = msm_clocks_8960,
5778 .size = ARRAY_SIZE(msm_clocks_8960),
5779 .init = msm8960_clock_init,
5780 .late_init = msm8960_clock_late_init,
5781};
Tianyi Gou41515e22011-09-01 19:37:43 -07005782
5783struct clock_init_data apq8064_clock_init_data __initdata = {
5784 .table = msm_clocks_8064,
5785 .size = ARRAY_SIZE(msm_clocks_8064),
5786 .init = msm8960_clock_init,
5787 .late_init = msm8960_clock_late_init,
5788};