blob: f173ef3bfc10c1fdc9a4d85794d763df13bd8d7a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaa7e16d2005-08-29 15:12:56 -04008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040022 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
Robert Hancockfbbb2622006-10-27 19:08:41 -070032 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
36 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 */
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/kernel.h>
40#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090041#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <linux/pci.h>
43#include <linux/init.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050047#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <scsi/scsi_host.h>
Robert Hancockfbbb2622006-10-27 19:08:41 -070049#include <scsi/scsi_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#include <linux/libata.h>
51
52#define DRV_NAME "sata_nv"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040053#define DRV_VERSION "3.5"
Robert Hancockfbbb2622006-10-27 19:08:41 -070054
55#define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Jeff Garzik10ad05d2006-03-22 23:50:50 -050057enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090058 NV_MMIO_BAR = 5,
59
Jeff Garzik10ad05d2006-03-22 23:50:50 -050060 NV_PORTS = 2,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +010061 NV_PIO_MASK = ATA_PIO4,
62 NV_MWDMA_MASK = ATA_MWDMA2,
63 NV_UDMA_MASK = ATA_UDMA6,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050064 NV_PORT0_SCR_REG_OFFSET = 0x00,
65 NV_PORT1_SCR_REG_OFFSET = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
Tejun Heo27e4b272006-06-17 15:49:55 +090067 /* INT_STATUS/ENABLE */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050068 NV_INT_STATUS = 0x10,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050069 NV_INT_ENABLE = 0x11,
Tejun Heo27e4b272006-06-17 15:49:55 +090070 NV_INT_STATUS_CK804 = 0x440,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050071 NV_INT_ENABLE_CK804 = 0x441,
Linus Torvalds1da177e2005-04-16 15:20:36 -070072
Tejun Heo27e4b272006-06-17 15:49:55 +090073 /* INT_STATUS/ENABLE bits */
74 NV_INT_DEV = 0x01,
75 NV_INT_PM = 0x02,
76 NV_INT_ADDED = 0x04,
77 NV_INT_REMOVED = 0x08,
78
79 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
80
Tejun Heo39f87582006-06-17 15:49:56 +090081 NV_INT_ALL = 0x0f,
Tejun Heo5a44eff2006-06-17 15:49:56 +090082 NV_INT_MASK = NV_INT_DEV |
83 NV_INT_ADDED | NV_INT_REMOVED,
Tejun Heo39f87582006-06-17 15:49:56 +090084
Tejun Heo27e4b272006-06-17 15:49:55 +090085 /* INT_CONFIG */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050086 NV_INT_CONFIG = 0x12,
87 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
Jeff Garzik10ad05d2006-03-22 23:50:50 -050089 // For PCI config register 20
90 NV_MCP_SATA_CFG_20 = 0x50,
91 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
Robert Hancockfbbb2622006-10-27 19:08:41 -070092 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
93 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
94 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
95 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
96
97 NV_ADMA_MAX_CPBS = 32,
98 NV_ADMA_CPB_SZ = 128,
99 NV_ADMA_APRD_SZ = 16,
100 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
101 NV_ADMA_APRD_SZ,
102 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
103 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
104 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
105 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
106
107 /* BAR5 offset to ADMA general registers */
108 NV_ADMA_GEN = 0x400,
109 NV_ADMA_GEN_CTL = 0x00,
110 NV_ADMA_NOTIFIER_CLEAR = 0x30,
111
112 /* BAR5 offset to ADMA ports */
113 NV_ADMA_PORT = 0x480,
114
115 /* size of ADMA port register space */
116 NV_ADMA_PORT_SIZE = 0x100,
117
118 /* ADMA port registers */
119 NV_ADMA_CTL = 0x40,
120 NV_ADMA_CPB_COUNT = 0x42,
121 NV_ADMA_NEXT_CPB_IDX = 0x43,
122 NV_ADMA_STAT = 0x44,
123 NV_ADMA_CPB_BASE_LOW = 0x48,
124 NV_ADMA_CPB_BASE_HIGH = 0x4C,
125 NV_ADMA_APPEND = 0x50,
126 NV_ADMA_NOTIFIER = 0x68,
127 NV_ADMA_NOTIFIER_ERROR = 0x6C,
128
129 /* NV_ADMA_CTL register bits */
130 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
131 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
132 NV_ADMA_CTL_GO = (1 << 7),
133 NV_ADMA_CTL_AIEN = (1 << 8),
134 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
135 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
136
137 /* CPB response flag bits */
138 NV_CPB_RESP_DONE = (1 << 0),
139 NV_CPB_RESP_ATA_ERR = (1 << 3),
140 NV_CPB_RESP_CMD_ERR = (1 << 4),
141 NV_CPB_RESP_CPB_ERR = (1 << 7),
142
143 /* CPB control flag bits */
144 NV_CPB_CTL_CPB_VALID = (1 << 0),
145 NV_CPB_CTL_QUEUE = (1 << 1),
146 NV_CPB_CTL_APRD_VALID = (1 << 2),
147 NV_CPB_CTL_IEN = (1 << 3),
148 NV_CPB_CTL_FPDMA = (1 << 4),
149
150 /* APRD flags */
151 NV_APRD_WRITE = (1 << 1),
152 NV_APRD_END = (1 << 2),
153 NV_APRD_CONT = (1 << 3),
154
155 /* NV_ADMA_STAT flags */
156 NV_ADMA_STAT_TIMEOUT = (1 << 0),
157 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
158 NV_ADMA_STAT_HOTPLUG = (1 << 2),
159 NV_ADMA_STAT_CPBERR = (1 << 4),
160 NV_ADMA_STAT_SERROR = (1 << 5),
161 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
162 NV_ADMA_STAT_IDLE = (1 << 8),
163 NV_ADMA_STAT_LEGACY = (1 << 9),
164 NV_ADMA_STAT_STOPPED = (1 << 10),
165 NV_ADMA_STAT_DONE = (1 << 12),
166 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400167 NV_ADMA_STAT_TIMEOUT,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700168
169 /* port flags */
170 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
Robert Hancock2dec7552006-11-26 14:20:19 -0600171 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700172
Kuan Luof140f0f2007-10-15 15:16:53 -0400173 /* MCP55 reg offset */
174 NV_CTL_MCP55 = 0x400,
175 NV_INT_STATUS_MCP55 = 0x440,
176 NV_INT_ENABLE_MCP55 = 0x444,
177 NV_NCQ_REG_MCP55 = 0x448,
178
179 /* MCP55 */
180 NV_INT_ALL_MCP55 = 0xffff,
181 NV_INT_PORT_SHIFT_MCP55 = 16, /* each port occupies 16 bits */
182 NV_INT_MASK_MCP55 = NV_INT_ALL_MCP55 & 0xfffd,
183
184 /* SWNCQ ENABLE BITS*/
185 NV_CTL_PRI_SWNCQ = 0x02,
186 NV_CTL_SEC_SWNCQ = 0x04,
187
188 /* SW NCQ status bits*/
189 NV_SWNCQ_IRQ_DEV = (1 << 0),
190 NV_SWNCQ_IRQ_PM = (1 << 1),
191 NV_SWNCQ_IRQ_ADDED = (1 << 2),
192 NV_SWNCQ_IRQ_REMOVED = (1 << 3),
193
194 NV_SWNCQ_IRQ_BACKOUT = (1 << 4),
195 NV_SWNCQ_IRQ_SDBFIS = (1 << 5),
196 NV_SWNCQ_IRQ_DHREGFIS = (1 << 6),
197 NV_SWNCQ_IRQ_DMASETUP = (1 << 7),
198
199 NV_SWNCQ_IRQ_HOTPLUG = NV_SWNCQ_IRQ_ADDED |
200 NV_SWNCQ_IRQ_REMOVED,
201
Jeff Garzik10ad05d2006-03-22 23:50:50 -0500202};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
Robert Hancockfbbb2622006-10-27 19:08:41 -0700204/* ADMA Physical Region Descriptor - one SG segment */
205struct nv_adma_prd {
206 __le64 addr;
207 __le32 len;
208 u8 flags;
209 u8 packet_len;
210 __le16 reserved;
211};
212
213enum nv_adma_regbits {
214 CMDEND = (1 << 15), /* end of command list */
215 WNB = (1 << 14), /* wait-not-BSY */
216 IGN = (1 << 13), /* ignore this entry */
217 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
218 DA2 = (1 << (2 + 8)),
219 DA1 = (1 << (1 + 8)),
220 DA0 = (1 << (0 + 8)),
221};
222
223/* ADMA Command Parameter Block
224 The first 5 SG segments are stored inside the Command Parameter Block itself.
225 If there are more than 5 segments the remainder are stored in a separate
226 memory area indicated by next_aprd. */
227struct nv_adma_cpb {
228 u8 resp_flags; /* 0 */
229 u8 reserved1; /* 1 */
230 u8 ctl_flags; /* 2 */
231 /* len is length of taskfile in 64 bit words */
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400232 u8 len; /* 3 */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700233 u8 tag; /* 4 */
234 u8 next_cpb_idx; /* 5 */
235 __le16 reserved2; /* 6-7 */
236 __le16 tf[12]; /* 8-31 */
237 struct nv_adma_prd aprd[5]; /* 32-111 */
238 __le64 next_aprd; /* 112-119 */
239 __le64 reserved3; /* 120-127 */
240};
241
242
243struct nv_adma_port_priv {
244 struct nv_adma_cpb *cpb;
245 dma_addr_t cpb_dma;
246 struct nv_adma_prd *aprd;
247 dma_addr_t aprd_dma;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400248 void __iomem *ctl_block;
249 void __iomem *gen_block;
250 void __iomem *notifier_clear_block;
Robert Hancock8959d302008-02-04 19:39:02 -0600251 u64 adma_dma_mask;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700252 u8 flags;
Robert Hancock5e5c74a2007-02-19 18:42:30 -0600253 int last_issue_ncq;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700254};
255
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600256struct nv_host_priv {
257 unsigned long type;
258};
259
Kuan Luof140f0f2007-10-15 15:16:53 -0400260struct defer_queue {
261 u32 defer_bits;
262 unsigned int head;
263 unsigned int tail;
264 unsigned int tag[ATA_MAX_QUEUE];
265};
266
267enum ncq_saw_flag_list {
268 ncq_saw_d2h = (1U << 0),
269 ncq_saw_dmas = (1U << 1),
270 ncq_saw_sdb = (1U << 2),
271 ncq_saw_backout = (1U << 3),
272};
273
274struct nv_swncq_port_priv {
Tejun Heof60d7012010-05-10 21:41:41 +0200275 struct ata_bmdma_prd *prd; /* our SG list */
Kuan Luof140f0f2007-10-15 15:16:53 -0400276 dma_addr_t prd_dma; /* and its DMA mapping */
277 void __iomem *sactive_block;
278 void __iomem *irq_block;
279 void __iomem *tag_block;
280 u32 qc_active;
281
282 unsigned int last_issue_tag;
283
284 /* fifo circular queue to store deferral command */
285 struct defer_queue defer_queue;
286
287 /* for NCQ interrupt analysis */
288 u32 dhfis_bits;
289 u32 dmafis_bits;
290 u32 sdbfis_bits;
291
292 unsigned int ncq_flags;
293};
294
295
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400296#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT)))))
Robert Hancockfbbb2622006-10-27 19:08:41 -0700297
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400298static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900299#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600300static int nv_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900301#endif
Jeff Garzikcca39742006-08-24 03:19:22 -0400302static void nv_ck804_host_stop(struct ata_host *host);
David Howells7d12e782006-10-05 14:55:46 +0100303static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
304static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
305static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
Tejun Heo82ef04f2008-07-31 17:02:40 +0900306static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
307static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308
Tejun Heo7f4774b2009-06-10 16:29:07 +0900309static int nv_hardreset(struct ata_link *link, unsigned int *class,
310 unsigned long deadline);
Tejun Heo39f87582006-06-17 15:49:56 +0900311static void nv_nf2_freeze(struct ata_port *ap);
312static void nv_nf2_thaw(struct ata_port *ap);
313static void nv_ck804_freeze(struct ata_port *ap);
314static void nv_ck804_thaw(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700315static int nv_adma_slave_config(struct scsi_device *sdev);
Robert Hancock2dec7552006-11-26 14:20:19 -0600316static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700317static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
318static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
319static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
320static void nv_adma_irq_clear(struct ata_port *ap);
321static int nv_adma_port_start(struct ata_port *ap);
322static void nv_adma_port_stop(struct ata_port *ap);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900323#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600324static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
325static int nv_adma_port_resume(struct ata_port *ap);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900326#endif
Robert Hancock53014e22007-05-05 15:36:36 -0600327static void nv_adma_freeze(struct ata_port *ap);
328static void nv_adma_thaw(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700329static void nv_adma_error_handler(struct ata_port *ap);
330static void nv_adma_host_stop(struct ata_host *host);
Robert Hancockf5ecac22007-02-20 21:49:10 -0600331static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
Robert Hancockf2fb3442007-03-26 21:43:36 -0800332static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
Tejun Heo39f87582006-06-17 15:49:56 +0900333
Kuan Luof140f0f2007-10-15 15:16:53 -0400334static void nv_mcp55_thaw(struct ata_port *ap);
335static void nv_mcp55_freeze(struct ata_port *ap);
336static void nv_swncq_error_handler(struct ata_port *ap);
337static int nv_swncq_slave_config(struct scsi_device *sdev);
338static int nv_swncq_port_start(struct ata_port *ap);
339static void nv_swncq_qc_prep(struct ata_queued_cmd *qc);
340static void nv_swncq_fill_sg(struct ata_queued_cmd *qc);
341static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc);
342static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis);
343static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance);
344#ifdef CONFIG_PM
345static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg);
346static int nv_swncq_port_resume(struct ata_port *ap);
347#endif
348
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349enum nv_host_type
350{
351 GENERIC,
352 NFORCE2,
Tejun Heo27e4b272006-06-17 15:49:55 +0900353 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700354 CK804,
Kuan Luof140f0f2007-10-15 15:16:53 -0400355 ADMA,
Tejun Heo2d775702009-01-25 11:29:38 +0900356 MCP5x,
Kuan Luof140f0f2007-10-15 15:16:53 -0400357 SWNCQ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358};
359
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500360static const struct pci_device_id nv_pci_tbl[] = {
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400361 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
362 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
363 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
364 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
365 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
366 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
367 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
Tejun Heo2d775702009-01-25 11:29:38 +0900368 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), MCP5x },
369 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), MCP5x },
370 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), MCP5x },
371 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), MCP5x },
Kuan Luoe2e031e2007-10-25 02:14:17 -0400372 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
373 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
374 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400375
376 { } /* terminate list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377};
378
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379static struct pci_driver nv_pci_driver = {
380 .name = DRV_NAME,
381 .id_table = nv_pci_tbl,
382 .probe = nv_init_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900383#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600384 .suspend = ata_pci_device_suspend,
385 .resume = nv_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900386#endif
Tejun Heo1daf9ce2007-05-17 13:13:57 +0200387 .remove = ata_pci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388};
389
Jeff Garzik193515d2005-11-07 00:59:37 -0500390static struct scsi_host_template nv_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900391 ATA_BMDMA_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392};
393
Robert Hancockfbbb2622006-10-27 19:08:41 -0700394static struct scsi_host_template nv_adma_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900395 ATA_NCQ_SHT(DRV_NAME),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700396 .can_queue = NV_ADMA_MAX_CPBS,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700397 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700398 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
399 .slave_configure = nv_adma_slave_config,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700400};
401
Kuan Luof140f0f2007-10-15 15:16:53 -0400402static struct scsi_host_template nv_swncq_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900403 ATA_NCQ_SHT(DRV_NAME),
Kuan Luof140f0f2007-10-15 15:16:53 -0400404 .can_queue = ATA_MAX_QUEUE,
Kuan Luof140f0f2007-10-15 15:16:53 -0400405 .sg_tablesize = LIBATA_MAX_PRD,
Kuan Luof140f0f2007-10-15 15:16:53 -0400406 .dma_boundary = ATA_DMA_BOUNDARY,
407 .slave_configure = nv_swncq_slave_config,
Kuan Luof140f0f2007-10-15 15:16:53 -0400408};
409
Tejun Heo7f4774b2009-06-10 16:29:07 +0900410/*
411 * NV SATA controllers have various different problems with hardreset
412 * protocol depending on the specific controller and device.
413 *
414 * GENERIC:
415 *
416 * bko11195 reports that link doesn't come online after hardreset on
417 * generic nv's and there have been several other similar reports on
418 * linux-ide.
419 *
420 * bko12351#c23 reports that warmplug on MCP61 doesn't work with
421 * softreset.
422 *
423 * NF2/3:
424 *
425 * bko3352 reports nf2/3 controllers can't determine device signature
426 * reliably after hardreset. The following thread reports detection
427 * failure on cold boot with the standard debouncing timing.
428 *
429 * http://thread.gmane.org/gmane.linux.ide/34098
430 *
431 * bko12176 reports that hardreset fails to bring up the link during
432 * boot on nf2.
433 *
434 * CK804:
435 *
436 * For initial probing after boot and hot plugging, hardreset mostly
437 * works fine on CK804 but curiously, reprobing on the initial port
438 * by rescanning or rmmod/insmod fails to acquire the initial D2H Reg
439 * FIS in somewhat undeterministic way.
440 *
441 * SWNCQ:
442 *
443 * bko12351 reports that when SWNCQ is enabled, for hotplug to work,
444 * hardreset should be used and hardreset can't report proper
445 * signature, which suggests that mcp5x is closer to nf2 as long as
446 * reset quirkiness is concerned.
447 *
448 * bko12703 reports that boot probing fails for intel SSD with
449 * hardreset. Link fails to come online. Softreset works fine.
450 *
451 * The failures are varied but the following patterns seem true for
452 * all flavors.
453 *
454 * - Softreset during boot always works.
455 *
456 * - Hardreset during boot sometimes fails to bring up the link on
457 * certain comibnations and device signature acquisition is
458 * unreliable.
459 *
460 * - Hardreset is often necessary after hotplug.
461 *
462 * So, preferring softreset for boot probing and error handling (as
463 * hardreset might bring down the link) but using hardreset for
464 * post-boot probing should work around the above issues in most
465 * cases. Define nv_hardreset() which only kicks in for post-boot
466 * probing and use it for all variants.
467 */
468static struct ata_port_operations nv_generic_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900469 .inherits = &ata_bmdma_port_ops,
Alan Coxc96f1732009-03-24 10:23:46 +0000470 .lost_interrupt = ATA_OP_NULL,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471 .scr_read = nv_scr_read,
472 .scr_write = nv_scr_write,
Tejun Heo7f4774b2009-06-10 16:29:07 +0900473 .hardreset = nv_hardreset,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474};
475
Tejun Heo029cfd62008-03-25 12:22:49 +0900476static struct ata_port_operations nv_nf2_ops = {
Tejun Heo7dac7452009-02-12 10:34:32 +0900477 .inherits = &nv_generic_ops,
Tejun Heo39f87582006-06-17 15:49:56 +0900478 .freeze = nv_nf2_freeze,
479 .thaw = nv_nf2_thaw,
Tejun Heoada364e2006-06-17 15:49:56 +0900480};
481
Tejun Heo029cfd62008-03-25 12:22:49 +0900482static struct ata_port_operations nv_ck804_ops = {
Tejun Heo7f4774b2009-06-10 16:29:07 +0900483 .inherits = &nv_generic_ops,
Tejun Heo39f87582006-06-17 15:49:56 +0900484 .freeze = nv_ck804_freeze,
485 .thaw = nv_ck804_thaw,
Tejun Heoada364e2006-06-17 15:49:56 +0900486 .host_stop = nv_ck804_host_stop,
487};
488
Tejun Heo029cfd62008-03-25 12:22:49 +0900489static struct ata_port_operations nv_adma_ops = {
Tejun Heo3c324282008-11-03 12:37:49 +0900490 .inherits = &nv_ck804_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +0900491
Robert Hancock2dec7552006-11-26 14:20:19 -0600492 .check_atapi_dma = nv_adma_check_atapi_dma,
Tejun Heo5682ed32008-04-07 22:47:16 +0900493 .sff_tf_read = nv_adma_tf_read,
Tejun Heo31cc23b2007-09-23 13:14:12 +0900494 .qc_defer = ata_std_qc_defer,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700495 .qc_prep = nv_adma_qc_prep,
496 .qc_issue = nv_adma_qc_issue,
Tejun Heo5682ed32008-04-07 22:47:16 +0900497 .sff_irq_clear = nv_adma_irq_clear,
Tejun Heo029cfd62008-03-25 12:22:49 +0900498
Robert Hancock53014e22007-05-05 15:36:36 -0600499 .freeze = nv_adma_freeze,
500 .thaw = nv_adma_thaw,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700501 .error_handler = nv_adma_error_handler,
Robert Hancockf5ecac22007-02-20 21:49:10 -0600502 .post_internal_cmd = nv_adma_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900503
Robert Hancockfbbb2622006-10-27 19:08:41 -0700504 .port_start = nv_adma_port_start,
505 .port_stop = nv_adma_port_stop,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900506#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600507 .port_suspend = nv_adma_port_suspend,
508 .port_resume = nv_adma_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900509#endif
Robert Hancockfbbb2622006-10-27 19:08:41 -0700510 .host_stop = nv_adma_host_stop,
511};
512
Tejun Heo029cfd62008-03-25 12:22:49 +0900513static struct ata_port_operations nv_swncq_ops = {
Tejun Heo7f4774b2009-06-10 16:29:07 +0900514 .inherits = &nv_generic_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +0900515
Kuan Luof140f0f2007-10-15 15:16:53 -0400516 .qc_defer = ata_std_qc_defer,
517 .qc_prep = nv_swncq_qc_prep,
518 .qc_issue = nv_swncq_qc_issue,
Tejun Heo029cfd62008-03-25 12:22:49 +0900519
Kuan Luof140f0f2007-10-15 15:16:53 -0400520 .freeze = nv_mcp55_freeze,
521 .thaw = nv_mcp55_thaw,
522 .error_handler = nv_swncq_error_handler,
Tejun Heo029cfd62008-03-25 12:22:49 +0900523
Kuan Luof140f0f2007-10-15 15:16:53 -0400524#ifdef CONFIG_PM
525 .port_suspend = nv_swncq_port_suspend,
526 .port_resume = nv_swncq_port_resume,
527#endif
528 .port_start = nv_swncq_port_start,
529};
530
Tejun Heo95947192008-03-25 12:22:49 +0900531struct nv_pi_priv {
532 irq_handler_t irq_handler;
533 struct scsi_host_template *sht;
534};
535
536#define NV_PI_PRIV(_irq_handler, _sht) \
537 &(struct nv_pi_priv){ .irq_handler = _irq_handler, .sht = _sht }
538
Tejun Heo1626aeb2007-05-04 12:43:58 +0200539static const struct ata_port_info nv_port_info[] = {
Tejun Heoada364e2006-06-17 15:49:56 +0900540 /* generic */
541 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300542 .flags = ATA_FLAG_SATA,
Tejun Heoada364e2006-06-17 15:49:56 +0900543 .pio_mask = NV_PIO_MASK,
544 .mwdma_mask = NV_MWDMA_MASK,
545 .udma_mask = NV_UDMA_MASK,
546 .port_ops = &nv_generic_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900547 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900548 },
549 /* nforce2/3 */
550 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300551 .flags = ATA_FLAG_SATA,
Tejun Heoada364e2006-06-17 15:49:56 +0900552 .pio_mask = NV_PIO_MASK,
553 .mwdma_mask = NV_MWDMA_MASK,
554 .udma_mask = NV_UDMA_MASK,
555 .port_ops = &nv_nf2_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900556 .private_data = NV_PI_PRIV(nv_nf2_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900557 },
558 /* ck804 */
559 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300560 .flags = ATA_FLAG_SATA,
Tejun Heoada364e2006-06-17 15:49:56 +0900561 .pio_mask = NV_PIO_MASK,
562 .mwdma_mask = NV_MWDMA_MASK,
563 .udma_mask = NV_UDMA_MASK,
564 .port_ops = &nv_ck804_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900565 .private_data = NV_PI_PRIV(nv_ck804_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900566 },
Robert Hancockfbbb2622006-10-27 19:08:41 -0700567 /* ADMA */
568 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300569 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700570 .pio_mask = NV_PIO_MASK,
571 .mwdma_mask = NV_MWDMA_MASK,
572 .udma_mask = NV_UDMA_MASK,
573 .port_ops = &nv_adma_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900574 .private_data = NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700575 },
Tejun Heo2d775702009-01-25 11:29:38 +0900576 /* MCP5x */
577 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300578 .flags = ATA_FLAG_SATA,
Tejun Heo2d775702009-01-25 11:29:38 +0900579 .pio_mask = NV_PIO_MASK,
580 .mwdma_mask = NV_MWDMA_MASK,
581 .udma_mask = NV_UDMA_MASK,
Tejun Heo7f4774b2009-06-10 16:29:07 +0900582 .port_ops = &nv_generic_ops,
Tejun Heo2d775702009-01-25 11:29:38 +0900583 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
584 },
Kuan Luof140f0f2007-10-15 15:16:53 -0400585 /* SWNCQ */
586 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300587 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
Kuan Luof140f0f2007-10-15 15:16:53 -0400588 .pio_mask = NV_PIO_MASK,
589 .mwdma_mask = NV_MWDMA_MASK,
590 .udma_mask = NV_UDMA_MASK,
591 .port_ops = &nv_swncq_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900592 .private_data = NV_PI_PRIV(nv_swncq_interrupt, &nv_swncq_sht),
Kuan Luof140f0f2007-10-15 15:16:53 -0400593 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594};
595
596MODULE_AUTHOR("NVIDIA");
597MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
598MODULE_LICENSE("GPL");
599MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
600MODULE_VERSION(DRV_VERSION);
601
Jeff Garzik06993d22008-04-04 03:34:45 -0400602static int adma_enabled;
Zoltan Boszormenyid21279f2008-03-28 14:33:46 -0700603static int swncq_enabled = 1;
Tony Vroon51c89492009-08-06 00:50:09 +0100604static int msi_enabled;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700605
Robert Hancock2dec7552006-11-26 14:20:19 -0600606static void nv_adma_register_mode(struct ata_port *ap)
607{
Robert Hancock2dec7552006-11-26 14:20:19 -0600608 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600609 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800610 u16 tmp, status;
611 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600612
613 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
614 return;
615
Robert Hancocka2cfe812007-02-05 16:26:03 -0800616 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400617 while (!(status & NV_ADMA_STAT_IDLE) && count < 20) {
Robert Hancocka2cfe812007-02-05 16:26:03 -0800618 ndelay(50);
619 status = readw(mmio + NV_ADMA_STAT);
620 count++;
621 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400622 if (count == 20)
Robert Hancocka2cfe812007-02-05 16:26:03 -0800623 ata_port_printk(ap, KERN_WARNING,
624 "timeout waiting for ADMA IDLE, stat=0x%hx\n",
625 status);
626
Robert Hancock2dec7552006-11-26 14:20:19 -0600627 tmp = readw(mmio + NV_ADMA_CTL);
628 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
629
Robert Hancocka2cfe812007-02-05 16:26:03 -0800630 count = 0;
631 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400632 while (!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
Robert Hancocka2cfe812007-02-05 16:26:03 -0800633 ndelay(50);
634 status = readw(mmio + NV_ADMA_STAT);
635 count++;
636 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400637 if (count == 20)
Robert Hancocka2cfe812007-02-05 16:26:03 -0800638 ata_port_printk(ap, KERN_WARNING,
639 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
640 status);
641
Robert Hancock2dec7552006-11-26 14:20:19 -0600642 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
643}
644
645static void nv_adma_mode(struct ata_port *ap)
646{
Robert Hancock2dec7552006-11-26 14:20:19 -0600647 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600648 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800649 u16 tmp, status;
650 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600651
652 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
653 return;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500654
Robert Hancock2dec7552006-11-26 14:20:19 -0600655 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
656
657 tmp = readw(mmio + NV_ADMA_CTL);
658 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
659
Robert Hancocka2cfe812007-02-05 16:26:03 -0800660 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400661 while (((status & NV_ADMA_STAT_LEGACY) ||
Robert Hancocka2cfe812007-02-05 16:26:03 -0800662 !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
663 ndelay(50);
664 status = readw(mmio + NV_ADMA_STAT);
665 count++;
666 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400667 if (count == 20)
Robert Hancocka2cfe812007-02-05 16:26:03 -0800668 ata_port_printk(ap, KERN_WARNING,
669 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
670 status);
671
Robert Hancock2dec7552006-11-26 14:20:19 -0600672 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
673}
674
Robert Hancockfbbb2622006-10-27 19:08:41 -0700675static int nv_adma_slave_config(struct scsi_device *sdev)
676{
677 struct ata_port *ap = ata_shost_to_port(sdev->host);
Robert Hancock2dec7552006-11-26 14:20:19 -0600678 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancock8959d302008-02-04 19:39:02 -0600679 struct nv_adma_port_priv *port0, *port1;
680 struct scsi_device *sdev0, *sdev1;
Robert Hancock2dec7552006-11-26 14:20:19 -0600681 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Robert Hancock8959d302008-02-04 19:39:02 -0600682 unsigned long segment_boundary, flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700683 unsigned short sg_tablesize;
684 int rc;
Robert Hancock2dec7552006-11-26 14:20:19 -0600685 int adma_enable;
686 u32 current_reg, new_reg, config_mask;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700687
688 rc = ata_scsi_slave_config(sdev);
689
690 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
691 /* Not a proper libata device, ignore */
692 return rc;
693
Robert Hancock8959d302008-02-04 19:39:02 -0600694 spin_lock_irqsave(ap->lock, flags);
695
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900696 if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700697 /*
698 * NVIDIA reports that ADMA mode does not support ATAPI commands.
699 * Therefore ATAPI commands are sent through the legacy interface.
700 * However, the legacy interface only supports 32-bit DMA.
701 * Restrict DMA parameters as required by the legacy interface
702 * when an ATAPI device is connected.
703 */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700704 segment_boundary = ATA_DMA_BOUNDARY;
705 /* Subtract 1 since an extra entry may be needed for padding, see
706 libata-scsi.c */
707 sg_tablesize = LIBATA_MAX_PRD - 1;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500708
Robert Hancock2dec7552006-11-26 14:20:19 -0600709 /* Since the legacy DMA engine is in use, we need to disable ADMA
710 on the port. */
711 adma_enable = 0;
712 nv_adma_register_mode(ap);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400713 } else {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700714 segment_boundary = NV_ADMA_DMA_BOUNDARY;
715 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
Robert Hancock2dec7552006-11-26 14:20:19 -0600716 adma_enable = 1;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700717 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500718
Robert Hancock2dec7552006-11-26 14:20:19 -0600719 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700720
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400721 if (ap->port_no == 1)
Robert Hancock2dec7552006-11-26 14:20:19 -0600722 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
723 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
724 else
725 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
726 NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500727
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400728 if (adma_enable) {
Robert Hancock2dec7552006-11-26 14:20:19 -0600729 new_reg = current_reg | config_mask;
730 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400731 } else {
Robert Hancock2dec7552006-11-26 14:20:19 -0600732 new_reg = current_reg & ~config_mask;
733 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
734 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500735
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400736 if (current_reg != new_reg)
Robert Hancock2dec7552006-11-26 14:20:19 -0600737 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500738
Robert Hancock8959d302008-02-04 19:39:02 -0600739 port0 = ap->host->ports[0]->private_data;
740 port1 = ap->host->ports[1]->private_data;
741 sdev0 = ap->host->ports[0]->link.device[0].sdev;
742 sdev1 = ap->host->ports[1]->link.device[0].sdev;
743 if ((port0->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
744 (port1->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)) {
745 /** We have to set the DMA mask to 32-bit if either port is in
746 ATAPI mode, since they are on the same PCI device which is
747 used for DMA mapping. If we set the mask we also need to set
748 the bounce limit on both ports to ensure that the block
749 layer doesn't feed addresses that cause DMA mapping to
750 choke. If either SCSI device is not allocated yet, it's OK
751 since that port will discover its correct setting when it
752 does get allocated.
753 Note: Setting 32-bit mask should not fail. */
754 if (sdev0)
755 blk_queue_bounce_limit(sdev0->request_queue,
756 ATA_DMA_MASK);
757 if (sdev1)
758 blk_queue_bounce_limit(sdev1->request_queue,
759 ATA_DMA_MASK);
760
761 pci_set_dma_mask(pdev, ATA_DMA_MASK);
762 } else {
763 /** This shouldn't fail as it was set to this value before */
764 pci_set_dma_mask(pdev, pp->adma_dma_mask);
765 if (sdev0)
766 blk_queue_bounce_limit(sdev0->request_queue,
767 pp->adma_dma_mask);
768 if (sdev1)
769 blk_queue_bounce_limit(sdev1->request_queue,
770 pp->adma_dma_mask);
771 }
772
Robert Hancockfbbb2622006-10-27 19:08:41 -0700773 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
Martin K. Petersen8a783622010-02-26 00:20:39 -0500774 blk_queue_max_segments(sdev->request_queue, sg_tablesize);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700775 ata_port_printk(ap, KERN_INFO,
Robert Hancock8959d302008-02-04 19:39:02 -0600776 "DMA mask 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
777 (unsigned long long)*ap->host->dev->dma_mask,
778 segment_boundary, sg_tablesize);
779
780 spin_unlock_irqrestore(ap->lock, flags);
781
Robert Hancockfbbb2622006-10-27 19:08:41 -0700782 return rc;
783}
784
Robert Hancock2dec7552006-11-26 14:20:19 -0600785static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
786{
787 struct nv_adma_port_priv *pp = qc->ap->private_data;
788 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
789}
790
Robert Hancockf2fb3442007-03-26 21:43:36 -0800791static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
792{
Robert Hancock3f3debd2007-11-25 16:59:36 -0600793 /* Other than when internal or pass-through commands are executed,
794 the only time this function will be called in ADMA mode will be
795 if a command fails. In the failure case we don't care about going
796 into register mode with ADMA commands pending, as the commands will
797 all shortly be aborted anyway. We assume that NCQ commands are not
798 issued via passthrough, which is the only way that switching into
799 ADMA mode could abort outstanding commands. */
Robert Hancockf2fb3442007-03-26 21:43:36 -0800800 nv_adma_register_mode(ap);
801
Tejun Heo9363c382008-04-07 22:47:16 +0900802 ata_sff_tf_read(ap, tf);
Robert Hancockf2fb3442007-03-26 21:43:36 -0800803}
804
Robert Hancock2dec7552006-11-26 14:20:19 -0600805static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700806{
807 unsigned int idx = 0;
808
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400809 if (tf->flags & ATA_TFLAG_ISADDR) {
Robert Hancockac3d6b82007-02-19 19:02:46 -0600810 if (tf->flags & ATA_TFLAG_LBA48) {
811 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB);
812 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
813 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
814 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
815 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
816 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
817 } else
818 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB);
Jeff Garzika84471f2007-02-26 05:51:33 -0500819
Robert Hancockac3d6b82007-02-19 19:02:46 -0600820 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
821 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
822 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
823 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700824 }
Jeff Garzika84471f2007-02-26 05:51:33 -0500825
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400826 if (tf->flags & ATA_TFLAG_DEVICE)
Robert Hancockac3d6b82007-02-19 19:02:46 -0600827 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700828
829 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
Jeff Garzika84471f2007-02-26 05:51:33 -0500830
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400831 while (idx < 12)
Robert Hancockac3d6b82007-02-19 19:02:46 -0600832 cpb[idx++] = cpu_to_le16(IGN);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700833
834 return idx;
835}
836
Robert Hancock5bd28a42007-02-05 16:26:01 -0800837static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700838{
839 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancock2dec7552006-11-26 14:20:19 -0600840 u8 flags = pp->cpb[cpb_num].resp_flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700841
842 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
843
Robert Hancock5bd28a42007-02-05 16:26:01 -0800844 if (unlikely((force_err ||
845 flags & (NV_CPB_RESP_ATA_ERR |
846 NV_CPB_RESP_CMD_ERR |
847 NV_CPB_RESP_CPB_ERR)))) {
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900848 struct ata_eh_info *ehi = &ap->link.eh_info;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800849 int freeze = 0;
850
851 ata_ehi_clear_desc(ehi);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400852 __ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags);
Robert Hancock5bd28a42007-02-05 16:26:01 -0800853 if (flags & NV_CPB_RESP_ATA_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900854 ata_ehi_push_desc(ehi, "ATA error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800855 ehi->err_mask |= AC_ERR_DEV;
856 } else if (flags & NV_CPB_RESP_CMD_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900857 ata_ehi_push_desc(ehi, "CMD error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800858 ehi->err_mask |= AC_ERR_DEV;
859 } else if (flags & NV_CPB_RESP_CPB_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900860 ata_ehi_push_desc(ehi, "CPB error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800861 ehi->err_mask |= AC_ERR_SYSTEM;
862 freeze = 1;
863 } else {
864 /* notifier error, but no error in CPB flags? */
Tejun Heob64bbc32007-07-16 14:29:39 +0900865 ata_ehi_push_desc(ehi, "unknown");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800866 ehi->err_mask |= AC_ERR_OTHER;
867 freeze = 1;
868 }
869 /* Kill all commands. EH will determine what actually failed. */
870 if (freeze)
871 ata_port_freeze(ap);
872 else
873 ata_port_abort(ap);
Tejun Heo1aadf5c2010-06-25 15:03:34 +0200874 return -1;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800875 }
876
Tejun Heo1aadf5c2010-06-25 15:03:34 +0200877 if (likely(flags & NV_CPB_RESP_DONE))
878 return 1;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800879 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700880}
881
Robert Hancock2dec7552006-11-26 14:20:19 -0600882static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
883{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900884 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
Robert Hancock2dec7552006-11-26 14:20:19 -0600885
886 /* freeze if hotplugged */
887 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
888 ata_port_freeze(ap);
889 return 1;
890 }
891
892 /* bail out if not our interrupt */
893 if (!(irq_stat & NV_INT_DEV))
894 return 0;
895
896 /* DEV interrupt w/ no active qc? */
897 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heo9363c382008-04-07 22:47:16 +0900898 ata_sff_check_status(ap);
Robert Hancock2dec7552006-11-26 14:20:19 -0600899 return 1;
900 }
901
902 /* handle interrupt */
Tejun Heoc3b28892010-05-19 22:10:21 +0200903 return ata_bmdma_port_intr(ap, qc);
Robert Hancock2dec7552006-11-26 14:20:19 -0600904}
905
Robert Hancockfbbb2622006-10-27 19:08:41 -0700906static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
907{
908 struct ata_host *host = dev_instance;
909 int i, handled = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600910 u32 notifier_clears[2];
Robert Hancockfbbb2622006-10-27 19:08:41 -0700911
912 spin_lock(&host->lock);
913
914 for (i = 0; i < host->n_ports; i++) {
915 struct ata_port *ap = host->ports[i];
Tejun Heo3e4ec342010-05-10 21:41:30 +0200916 struct nv_adma_port_priv *pp = ap->private_data;
917 void __iomem *mmio = pp->ctl_block;
918 u16 status;
919 u32 gen_ctl;
920 u32 notifier, notifier_error;
921
Robert Hancock2dec7552006-11-26 14:20:19 -0600922 notifier_clears[i] = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700923
Tejun Heo3e4ec342010-05-10 21:41:30 +0200924 /* if ADMA is disabled, use standard ata interrupt handler */
925 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
926 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
927 >> (NV_INT_PORT_SHIFT * i);
928 handled += nv_host_intr(ap, irq_stat);
929 continue;
930 }
Jeff Garzika617c092007-05-21 20:14:23 -0400931
Tejun Heo3e4ec342010-05-10 21:41:30 +0200932 /* if in ATA register mode, check for standard interrupts */
933 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
934 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
935 >> (NV_INT_PORT_SHIFT * i);
936 if (ata_tag_valid(ap->link.active_tag))
937 /** NV_INT_DEV indication seems unreliable
938 at times at least in ADMA mode. Force it
939 on always when a command is active, to
940 prevent losing interrupts. */
941 irq_stat |= NV_INT_DEV;
942 handled += nv_host_intr(ap, irq_stat);
943 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700944
Tejun Heo3e4ec342010-05-10 21:41:30 +0200945 notifier = readl(mmio + NV_ADMA_NOTIFIER);
946 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
947 notifier_clears[i] = notifier | notifier_error;
948
949 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
950
951 if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
952 !notifier_error)
953 /* Nothing to do */
954 continue;
955
956 status = readw(mmio + NV_ADMA_STAT);
957
958 /*
959 * Clear status. Ensure the controller sees the
960 * clearing before we start looking at any of the CPB
961 * statuses, so that any CPB completions after this
962 * point in the handler will raise another interrupt.
963 */
964 writew(status, mmio + NV_ADMA_STAT);
965 readw(mmio + NV_ADMA_STAT); /* flush posted write */
966 rmb();
967
968 handled++; /* irq handled if we got here */
969
970 /* freeze if hotplugged or controller error */
971 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
972 NV_ADMA_STAT_HOTUNPLUG |
973 NV_ADMA_STAT_TIMEOUT |
974 NV_ADMA_STAT_SERROR))) {
975 struct ata_eh_info *ehi = &ap->link.eh_info;
976
977 ata_ehi_clear_desc(ehi);
978 __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status);
979 if (status & NV_ADMA_STAT_TIMEOUT) {
980 ehi->err_mask |= AC_ERR_SYSTEM;
981 ata_ehi_push_desc(ehi, "timeout");
982 } else if (status & NV_ADMA_STAT_HOTPLUG) {
983 ata_ehi_hotplugged(ehi);
984 ata_ehi_push_desc(ehi, "hotplug");
985 } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
986 ata_ehi_hotplugged(ehi);
987 ata_ehi_push_desc(ehi, "hot unplug");
988 } else if (status & NV_ADMA_STAT_SERROR) {
989 /* let EH analyze SError and figure out cause */
990 ata_ehi_push_desc(ehi, "SError");
991 } else
992 ata_ehi_push_desc(ehi, "unknown");
993 ata_port_freeze(ap);
994 continue;
995 }
996
997 if (status & (NV_ADMA_STAT_DONE |
998 NV_ADMA_STAT_CPBERR |
999 NV_ADMA_STAT_CMD_COMPLETE)) {
1000 u32 check_commands = notifier_clears[i];
Tejun Heo1aadf5c2010-06-25 15:03:34 +02001001 u32 done_mask = 0;
Tejun Heo752e3862010-06-25 15:02:59 +02001002 int pos, rc;
Tejun Heo3e4ec342010-05-10 21:41:30 +02001003
1004 if (status & NV_ADMA_STAT_CPBERR) {
1005 /* check all active commands */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001006 if (ata_tag_valid(ap->link.active_tag))
Tejun Heo3e4ec342010-05-10 21:41:30 +02001007 check_commands = 1 <<
1008 ap->link.active_tag;
1009 else
1010 check_commands = ap->link.sactive;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001011 }
1012
Tejun Heo3e4ec342010-05-10 21:41:30 +02001013 /* check CPBs for completed commands */
Tejun Heo752e3862010-06-25 15:02:59 +02001014 while ((pos = ffs(check_commands))) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001015 pos--;
Tejun Heo752e3862010-06-25 15:02:59 +02001016 rc = nv_adma_check_cpb(ap, pos,
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001017 notifier_error & (1 << pos));
Tejun Heo1aadf5c2010-06-25 15:03:34 +02001018 if (rc > 0)
1019 done_mask |= 1 << pos;
1020 else if (unlikely(rc < 0))
Tejun Heo752e3862010-06-25 15:02:59 +02001021 check_commands = 0;
Tejun Heo3e4ec342010-05-10 21:41:30 +02001022 check_commands &= ~(1 << pos);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001023 }
Tejun Heo1aadf5c2010-06-25 15:03:34 +02001024 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001025 }
1026 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -05001027
Jeff Garzikb4479162007-10-25 20:47:30 -04001028 if (notifier_clears[0] || notifier_clears[1]) {
Robert Hancock2dec7552006-11-26 14:20:19 -06001029 /* Note: Both notifier clear registers must be written
1030 if either is set, even if one is zero, according to NVIDIA. */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001031 struct nv_adma_port_priv *pp = host->ports[0]->private_data;
1032 writel(notifier_clears[0], pp->notifier_clear_block);
1033 pp = host->ports[1]->private_data;
1034 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancock2dec7552006-11-26 14:20:19 -06001035 }
Robert Hancockfbbb2622006-10-27 19:08:41 -07001036
1037 spin_unlock(&host->lock);
1038
1039 return IRQ_RETVAL(handled);
1040}
1041
Robert Hancock53014e22007-05-05 15:36:36 -06001042static void nv_adma_freeze(struct ata_port *ap)
1043{
1044 struct nv_adma_port_priv *pp = ap->private_data;
1045 void __iomem *mmio = pp->ctl_block;
1046 u16 tmp;
1047
1048 nv_ck804_freeze(ap);
1049
1050 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1051 return;
1052
1053 /* clear any outstanding CK804 notifications */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001054 writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
Robert Hancock53014e22007-05-05 15:36:36 -06001055 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
1056
1057 /* Disable interrupt */
1058 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001059 writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
Robert Hancock53014e22007-05-05 15:36:36 -06001060 mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001061 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancock53014e22007-05-05 15:36:36 -06001062}
1063
1064static void nv_adma_thaw(struct ata_port *ap)
1065{
1066 struct nv_adma_port_priv *pp = ap->private_data;
1067 void __iomem *mmio = pp->ctl_block;
1068 u16 tmp;
1069
1070 nv_ck804_thaw(ap);
1071
1072 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1073 return;
1074
1075 /* Enable interrupt */
1076 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001077 writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
Robert Hancock53014e22007-05-05 15:36:36 -06001078 mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001079 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancock53014e22007-05-05 15:36:36 -06001080}
1081
Robert Hancockfbbb2622006-10-27 19:08:41 -07001082static void nv_adma_irq_clear(struct ata_port *ap)
1083{
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001084 struct nv_adma_port_priv *pp = ap->private_data;
1085 void __iomem *mmio = pp->ctl_block;
Robert Hancock53014e22007-05-05 15:36:36 -06001086 u32 notifier_clears[2];
1087
1088 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
Tejun Heo37f65b82010-05-19 22:10:20 +02001089 ata_bmdma_irq_clear(ap);
Robert Hancock53014e22007-05-05 15:36:36 -06001090 return;
1091 }
1092
1093 /* clear any outstanding CK804 notifications */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001094 writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
Robert Hancock53014e22007-05-05 15:36:36 -06001095 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001096
1097 /* clear ADMA status */
Robert Hancock53014e22007-05-05 15:36:36 -06001098 writew(0xffff, mmio + NV_ADMA_STAT);
Jeff Garzika617c092007-05-21 20:14:23 -04001099
Robert Hancock53014e22007-05-05 15:36:36 -06001100 /* clear notifiers - note both ports need to be written with
1101 something even though we are only clearing on one */
1102 if (ap->port_no == 0) {
1103 notifier_clears[0] = 0xFFFFFFFF;
1104 notifier_clears[1] = 0;
1105 } else {
1106 notifier_clears[0] = 0;
1107 notifier_clears[1] = 0xFFFFFFFF;
1108 }
1109 pp = ap->host->ports[0]->private_data;
1110 writel(notifier_clears[0], pp->notifier_clear_block);
1111 pp = ap->host->ports[1]->private_data;
1112 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001113}
1114
Robert Hancockf5ecac22007-02-20 21:49:10 -06001115static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001116{
Robert Hancockf5ecac22007-02-20 21:49:10 -06001117 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001118
Jeff Garzikb4479162007-10-25 20:47:30 -04001119 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
Tejun Heofe06e5f2010-05-10 21:41:39 +02001120 ata_bmdma_post_internal_cmd(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001121}
1122
1123static int nv_adma_port_start(struct ata_port *ap)
1124{
1125 struct device *dev = ap->host->dev;
1126 struct nv_adma_port_priv *pp;
1127 int rc;
1128 void *mem;
1129 dma_addr_t mem_dma;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001130 void __iomem *mmio;
Robert Hancock8959d302008-02-04 19:39:02 -06001131 struct pci_dev *pdev = to_pci_dev(dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001132 u16 tmp;
1133
1134 VPRINTK("ENTER\n");
1135
Robert Hancock8959d302008-02-04 19:39:02 -06001136 /* Ensure DMA mask is set to 32-bit before allocating legacy PRD and
1137 pad buffers */
1138 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1139 if (rc)
1140 return rc;
1141 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1142 if (rc)
1143 return rc;
1144
Tejun Heoc7087652010-05-10 21:41:34 +02001145 /* we might fallback to bmdma, allocate bmdma resources */
1146 rc = ata_bmdma_port_start(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001147 if (rc)
1148 return rc;
1149
Tejun Heo24dc5f32007-01-20 16:00:28 +09001150 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1151 if (!pp)
1152 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001153
Tejun Heo0d5ff562007-02-01 15:06:36 +09001154 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001155 ap->port_no * NV_ADMA_PORT_SIZE;
1156 pp->ctl_block = mmio;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001157 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001158 pp->notifier_clear_block = pp->gen_block +
1159 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
1160
Robert Hancock8959d302008-02-04 19:39:02 -06001161 /* Now that the legacy PRD and padding buffer are allocated we can
1162 safely raise the DMA mask to allocate the CPB/APRD table.
1163 These are allowed to fail since we store the value that ends up
1164 being used to set as the bounce limit in slave_config later if
1165 needed. */
1166 pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1167 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1168 pp->adma_dma_mask = *dev->dma_mask;
1169
Tejun Heo24dc5f32007-01-20 16:00:28 +09001170 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
1171 &mem_dma, GFP_KERNEL);
1172 if (!mem)
1173 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001174 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
1175
1176 /*
1177 * First item in chunk of DMA memory:
1178 * 128-byte command parameter block (CPB)
1179 * one for each command tag
1180 */
1181 pp->cpb = mem;
1182 pp->cpb_dma = mem_dma;
1183
1184 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001185 writel((mem_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001186
1187 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1188 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1189
1190 /*
1191 * Second item: block of ADMA_SGTBL_LEN s/g entries
1192 */
1193 pp->aprd = mem;
1194 pp->aprd_dma = mem_dma;
1195
1196 ap->private_data = pp;
1197
1198 /* clear any outstanding interrupt conditions */
1199 writew(0xffff, mmio + NV_ADMA_STAT);
1200
1201 /* initialize port variables */
1202 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1203
1204 /* clear CPB fetch count */
1205 writew(0, mmio + NV_ADMA_CPB_COUNT);
1206
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001207 /* clear GO for register mode, enable interrupt */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001208 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001209 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1210 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001211
1212 tmp = readw(mmio + NV_ADMA_CTL);
1213 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001214 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001215 udelay(1);
1216 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001217 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001218
1219 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001220}
1221
1222static void nv_adma_port_stop(struct ata_port *ap)
1223{
Robert Hancockfbbb2622006-10-27 19:08:41 -07001224 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001225 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001226
1227 VPRINTK("ENTER\n");
Robert Hancockfbbb2622006-10-27 19:08:41 -07001228 writew(0, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001229}
1230
Tejun Heo438ac6d2007-03-02 17:31:26 +09001231#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001232static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
1233{
1234 struct nv_adma_port_priv *pp = ap->private_data;
1235 void __iomem *mmio = pp->ctl_block;
1236
1237 /* Go to register mode - clears GO */
1238 nv_adma_register_mode(ap);
1239
1240 /* clear CPB fetch count */
1241 writew(0, mmio + NV_ADMA_CPB_COUNT);
1242
1243 /* disable interrupt, shut down port */
1244 writew(0, mmio + NV_ADMA_CTL);
1245
1246 return 0;
1247}
1248
1249static int nv_adma_port_resume(struct ata_port *ap)
1250{
1251 struct nv_adma_port_priv *pp = ap->private_data;
1252 void __iomem *mmio = pp->ctl_block;
1253 u16 tmp;
1254
1255 /* set CPB block location */
1256 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001257 writel((pp->cpb_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001258
1259 /* clear any outstanding interrupt conditions */
1260 writew(0xffff, mmio + NV_ADMA_STAT);
1261
1262 /* initialize port variables */
1263 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1264
1265 /* clear CPB fetch count */
1266 writew(0, mmio + NV_ADMA_CPB_COUNT);
1267
1268 /* clear GO for register mode, enable interrupt */
1269 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001270 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1271 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001272
1273 tmp = readw(mmio + NV_ADMA_CTL);
1274 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001275 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001276 udelay(1);
1277 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001278 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001279
1280 return 0;
1281}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001282#endif
Robert Hancockfbbb2622006-10-27 19:08:41 -07001283
Tejun Heo9a829cc2007-04-17 23:44:08 +09001284static void nv_adma_setup_port(struct ata_port *ap)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001285{
Tejun Heo9a829cc2007-04-17 23:44:08 +09001286 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1287 struct ata_ioports *ioport = &ap->ioaddr;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001288
1289 VPRINTK("ENTER\n");
1290
Tejun Heo9a829cc2007-04-17 23:44:08 +09001291 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001292
Tejun Heo0d5ff562007-02-01 15:06:36 +09001293 ioport->cmd_addr = mmio;
1294 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001295 ioport->error_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001296 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1297 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1298 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1299 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1300 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1301 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001302 ioport->status_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001303 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001304 ioport->altstatus_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001305 ioport->ctl_addr = mmio + 0x20;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001306}
1307
Tejun Heo9a829cc2007-04-17 23:44:08 +09001308static int nv_adma_host_init(struct ata_host *host)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001309{
Tejun Heo9a829cc2007-04-17 23:44:08 +09001310 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001311 unsigned int i;
1312 u32 tmp32;
1313
1314 VPRINTK("ENTER\n");
1315
1316 /* enable ADMA on the ports */
1317 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1318 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1319 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1320 NV_MCP_SATA_CFG_20_PORT1_EN |
1321 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1322
1323 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1324
Tejun Heo9a829cc2007-04-17 23:44:08 +09001325 for (i = 0; i < host->n_ports; i++)
1326 nv_adma_setup_port(host->ports[i]);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001327
Robert Hancockfbbb2622006-10-27 19:08:41 -07001328 return 0;
1329}
1330
1331static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1332 struct scatterlist *sg,
1333 int idx,
1334 struct nv_adma_prd *aprd)
1335{
Robert Hancock41949ed2007-02-19 19:02:27 -06001336 u8 flags = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001337 if (qc->tf.flags & ATA_TFLAG_WRITE)
1338 flags |= NV_APRD_WRITE;
1339 if (idx == qc->n_elem - 1)
1340 flags |= NV_APRD_END;
1341 else if (idx != 4)
1342 flags |= NV_APRD_CONT;
1343
1344 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1345 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
Robert Hancock2dec7552006-11-26 14:20:19 -06001346 aprd->flags = flags;
Robert Hancock41949ed2007-02-19 19:02:27 -06001347 aprd->packet_len = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001348}
1349
1350static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1351{
1352 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001353 struct nv_adma_prd *aprd;
1354 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001355 unsigned int si;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001356
1357 VPRINTK("ENTER\n");
1358
Tejun Heoff2aeb12007-12-05 16:43:11 +09001359 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1360 aprd = (si < 5) ? &cpb->aprd[si] :
1361 &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)];
1362 nv_adma_fill_aprd(qc, sg, si, aprd);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001363 }
Tejun Heoff2aeb12007-12-05 16:43:11 +09001364 if (si > 5)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001365 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
Robert Hancock41949ed2007-02-19 19:02:27 -06001366 else
1367 cpb->next_aprd = cpu_to_le64(0);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001368}
1369
Robert Hancock382a6652007-02-05 16:26:02 -08001370static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1371{
1372 struct nv_adma_port_priv *pp = qc->ap->private_data;
1373
1374 /* ADMA engine can only be used for non-ATAPI DMA commands,
Robert Hancock3f3debd2007-11-25 16:59:36 -06001375 or interrupt-driven no-data commands. */
Jeff Garzikb4479162007-10-25 20:47:30 -04001376 if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
Robert Hancock3f3debd2007-11-25 16:59:36 -06001377 (qc->tf.flags & ATA_TFLAG_POLLING))
Robert Hancock382a6652007-02-05 16:26:02 -08001378 return 1;
1379
Jeff Garzikb4479162007-10-25 20:47:30 -04001380 if ((qc->flags & ATA_QCFLAG_DMAMAP) ||
Robert Hancock382a6652007-02-05 16:26:02 -08001381 (qc->tf.protocol == ATA_PROT_NODATA))
1382 return 0;
1383
1384 return 1;
1385}
1386
Robert Hancockfbbb2622006-10-27 19:08:41 -07001387static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1388{
1389 struct nv_adma_port_priv *pp = qc->ap->private_data;
1390 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1391 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
Robert Hancockfbbb2622006-10-27 19:08:41 -07001392 NV_CPB_CTL_IEN;
1393
Robert Hancock382a6652007-02-05 16:26:02 -08001394 if (nv_adma_use_reg_mode(qc)) {
Robert Hancock3f3debd2007-11-25 16:59:36 -06001395 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1396 (qc->flags & ATA_QCFLAG_DMAMAP));
Robert Hancock2dec7552006-11-26 14:20:19 -06001397 nv_adma_register_mode(qc->ap);
Tejun Heof47451c2010-05-10 21:41:40 +02001398 ata_bmdma_qc_prep(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001399 return;
1400 }
1401
Robert Hancock41949ed2007-02-19 19:02:27 -06001402 cpb->resp_flags = NV_CPB_RESP_DONE;
1403 wmb();
1404 cpb->ctl_flags = 0;
1405 wmb();
Robert Hancockfbbb2622006-10-27 19:08:41 -07001406
1407 cpb->len = 3;
1408 cpb->tag = qc->tag;
1409 cpb->next_cpb_idx = 0;
1410
1411 /* turn on NCQ flags for NCQ commands */
1412 if (qc->tf.protocol == ATA_PROT_NCQ)
1413 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1414
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001415 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1416
Robert Hancockfbbb2622006-10-27 19:08:41 -07001417 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1418
Jeff Garzikb4479162007-10-25 20:47:30 -04001419 if (qc->flags & ATA_QCFLAG_DMAMAP) {
Robert Hancock382a6652007-02-05 16:26:02 -08001420 nv_adma_fill_sg(qc, cpb);
1421 ctl_flags |= NV_CPB_CTL_APRD_VALID;
1422 } else
1423 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001424
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001425 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID
1426 until we are finished filling in all of the contents */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001427 wmb();
1428 cpb->ctl_flags = ctl_flags;
Robert Hancock41949ed2007-02-19 19:02:27 -06001429 wmb();
1430 cpb->resp_flags = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001431}
1432
1433static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1434{
Robert Hancock2dec7552006-11-26 14:20:19 -06001435 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001436 void __iomem *mmio = pp->ctl_block;
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001437 int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001438
1439 VPRINTK("ENTER\n");
1440
Robert Hancock3f3debd2007-11-25 16:59:36 -06001441 /* We can't handle result taskfile with NCQ commands, since
1442 retrieving the taskfile switches us out of ADMA mode and would abort
1443 existing commands. */
1444 if (unlikely(qc->tf.protocol == ATA_PROT_NCQ &&
1445 (qc->flags & ATA_QCFLAG_RESULT_TF))) {
1446 ata_dev_printk(qc->dev, KERN_ERR,
1447 "NCQ w/ RESULT_TF not allowed\n");
1448 return AC_ERR_SYSTEM;
1449 }
1450
Robert Hancock382a6652007-02-05 16:26:02 -08001451 if (nv_adma_use_reg_mode(qc)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -07001452 /* use ATA register mode */
Robert Hancock382a6652007-02-05 16:26:02 -08001453 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
Robert Hancock3f3debd2007-11-25 16:59:36 -06001454 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1455 (qc->flags & ATA_QCFLAG_DMAMAP));
Robert Hancockfbbb2622006-10-27 19:08:41 -07001456 nv_adma_register_mode(qc->ap);
Tejun Heo360ff782010-05-10 21:41:42 +02001457 return ata_bmdma_qc_issue(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001458 } else
1459 nv_adma_mode(qc->ap);
1460
1461 /* write append register, command tag in lower 8 bits
1462 and (number of cpbs to append -1) in top 8 bits */
1463 wmb();
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001464
Jeff Garzikb4479162007-10-25 20:47:30 -04001465 if (curr_ncq != pp->last_issue_ncq) {
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001466 /* Seems to need some delay before switching between NCQ and
1467 non-NCQ commands, else we get command timeouts and such. */
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001468 udelay(20);
1469 pp->last_issue_ncq = curr_ncq;
1470 }
1471
Robert Hancockfbbb2622006-10-27 19:08:41 -07001472 writew(qc->tag, mmio + NV_ADMA_APPEND);
1473
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001474 DPRINTK("Issued tag %u\n", qc->tag);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001475
1476 return 0;
1477}
1478
David Howells7d12e782006-10-05 14:55:46 +01001479static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480{
Jeff Garzikcca39742006-08-24 03:19:22 -04001481 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 unsigned int i;
1483 unsigned int handled = 0;
1484 unsigned long flags;
1485
Jeff Garzikcca39742006-08-24 03:19:22 -04001486 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487
Jeff Garzikcca39742006-08-24 03:19:22 -04001488 for (i = 0; i < host->n_ports; i++) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001489 struct ata_port *ap = host->ports[i];
1490 struct ata_queued_cmd *qc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491
Tejun Heo3e4ec342010-05-10 21:41:30 +02001492 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1493 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heoc3b28892010-05-19 22:10:21 +02001494 handled += ata_bmdma_port_intr(ap, qc);
Tejun Heo3e4ec342010-05-10 21:41:30 +02001495 } else {
1496 /*
1497 * No request pending? Clear interrupt status
1498 * anyway, in case there's one pending.
1499 */
1500 ap->ops->sff_check_status(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502 }
1503
Jeff Garzikcca39742006-08-24 03:19:22 -04001504 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505
1506 return IRQ_RETVAL(handled);
1507}
1508
Jeff Garzikcca39742006-08-24 03:19:22 -04001509static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
Tejun Heoada364e2006-06-17 15:49:56 +09001510{
1511 int i, handled = 0;
1512
Jeff Garzikcca39742006-08-24 03:19:22 -04001513 for (i = 0; i < host->n_ports; i++) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001514 handled += nv_host_intr(host->ports[i], irq_stat);
Tejun Heoada364e2006-06-17 15:49:56 +09001515 irq_stat >>= NV_INT_PORT_SHIFT;
1516 }
1517
1518 return IRQ_RETVAL(handled);
1519}
1520
David Howells7d12e782006-10-05 14:55:46 +01001521static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001522{
Jeff Garzikcca39742006-08-24 03:19:22 -04001523 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001524 u8 irq_stat;
1525 irqreturn_t ret;
1526
Jeff Garzikcca39742006-08-24 03:19:22 -04001527 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001528 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
Jeff Garzikcca39742006-08-24 03:19:22 -04001529 ret = nv_do_interrupt(host, irq_stat);
1530 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001531
1532 return ret;
1533}
1534
David Howells7d12e782006-10-05 14:55:46 +01001535static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001536{
Jeff Garzikcca39742006-08-24 03:19:22 -04001537 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001538 u8 irq_stat;
1539 irqreturn_t ret;
1540
Jeff Garzikcca39742006-08-24 03:19:22 -04001541 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001542 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Jeff Garzikcca39742006-08-24 03:19:22 -04001543 ret = nv_do_interrupt(host, irq_stat);
1544 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001545
1546 return ret;
1547}
1548
Tejun Heo82ef04f2008-07-31 17:02:40 +09001549static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001550{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +09001552 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553
Tejun Heo82ef04f2008-07-31 17:02:40 +09001554 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg * 4));
Tejun Heoda3dbb12007-07-16 14:29:40 +09001555 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556}
1557
Tejun Heo82ef04f2008-07-31 17:02:40 +09001558static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001560 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +09001561 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562
Tejun Heo82ef04f2008-07-31 17:02:40 +09001563 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
Tejun Heoda3dbb12007-07-16 14:29:40 +09001564 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565}
1566
Tejun Heo7f4774b2009-06-10 16:29:07 +09001567static int nv_hardreset(struct ata_link *link, unsigned int *class,
1568 unsigned long deadline)
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001569{
Tejun Heo7f4774b2009-06-10 16:29:07 +09001570 struct ata_eh_context *ehc = &link->eh_context;
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001571
Tejun Heo7f4774b2009-06-10 16:29:07 +09001572 /* Do hardreset iff it's post-boot probing, please read the
1573 * comment above port ops for details.
1574 */
1575 if (!(link->ap->pflags & ATA_PFLAG_LOADING) &&
1576 !ata_dev_enabled(link->device))
1577 sata_link_hardreset(link, sata_deb_timing_hotplug, deadline,
1578 NULL, NULL);
Tejun Heo6489e322009-10-14 11:18:28 +09001579 else {
1580 const unsigned long *timing = sata_ehc_deb_timing(ehc);
1581 int rc;
1582
1583 if (!(ehc->i.flags & ATA_EHI_QUIET))
1584 ata_link_printk(link, KERN_INFO, "nv: skipping "
1585 "hardreset on occupied port\n");
1586
1587 /* make sure the link is online */
1588 rc = sata_link_resume(link, timing, deadline);
1589 /* whine about phy resume failure but proceed */
1590 if (rc && rc != -EOPNOTSUPP)
1591 ata_link_printk(link, KERN_WARNING, "failed to resume "
1592 "link (errno=%d)\n", rc);
1593 }
Tejun Heo7f4774b2009-06-10 16:29:07 +09001594
1595 /* device signature acquisition is unreliable */
1596 return -EAGAIN;
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001597}
1598
Tejun Heo39f87582006-06-17 15:49:56 +09001599static void nv_nf2_freeze(struct ata_port *ap)
1600{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001601 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001602 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1603 u8 mask;
1604
Tejun Heo0d5ff562007-02-01 15:06:36 +09001605 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001606 mask &= ~(NV_INT_ALL << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001607 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001608}
1609
1610static void nv_nf2_thaw(struct ata_port *ap)
1611{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001612 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001613 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1614 u8 mask;
1615
Tejun Heo0d5ff562007-02-01 15:06:36 +09001616 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
Tejun Heo39f87582006-06-17 15:49:56 +09001617
Tejun Heo0d5ff562007-02-01 15:06:36 +09001618 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001619 mask |= (NV_INT_MASK << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001620 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001621}
1622
1623static void nv_ck804_freeze(struct ata_port *ap)
1624{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001625 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001626 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1627 u8 mask;
1628
1629 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1630 mask &= ~(NV_INT_ALL << shift);
1631 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1632}
1633
1634static void nv_ck804_thaw(struct ata_port *ap)
1635{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001636 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001637 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1638 u8 mask;
1639
1640 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1641
1642 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1643 mask |= (NV_INT_MASK << shift);
1644 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1645}
1646
Kuan Luof140f0f2007-10-15 15:16:53 -04001647static void nv_mcp55_freeze(struct ata_port *ap)
1648{
1649 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1650 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
1651 u32 mask;
1652
1653 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
1654
1655 mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
1656 mask &= ~(NV_INT_ALL_MCP55 << shift);
1657 writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
Kuan Luof140f0f2007-10-15 15:16:53 -04001658}
1659
1660static void nv_mcp55_thaw(struct ata_port *ap)
1661{
1662 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1663 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
1664 u32 mask;
1665
1666 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
1667
1668 mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
1669 mask |= (NV_INT_MASK_MCP55 << shift);
1670 writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
Kuan Luof140f0f2007-10-15 15:16:53 -04001671}
1672
Robert Hancockfbbb2622006-10-27 19:08:41 -07001673static void nv_adma_error_handler(struct ata_port *ap)
1674{
1675 struct nv_adma_port_priv *pp = ap->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04001676 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001677 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001678 int i;
1679 u16 tmp;
Jeff Garzika84471f2007-02-26 05:51:33 -05001680
Jeff Garzikb4479162007-10-25 20:47:30 -04001681 if (ata_tag_valid(ap->link.active_tag) || ap->link.sactive) {
Robert Hancock2cb27852007-02-11 18:34:44 -06001682 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
1683 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
1684 u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1685 u32 status = readw(mmio + NV_ADMA_STAT);
Robert Hancock08af7412007-02-19 19:01:59 -06001686 u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
1687 u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
Robert Hancock2cb27852007-02-11 18:34:44 -06001688
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001689 ata_port_printk(ap, KERN_ERR,
1690 "EH in ADMA mode, notifier 0x%X "
Robert Hancock08af7412007-02-19 19:01:59 -06001691 "notifier_error 0x%X gen_ctl 0x%X status 0x%X "
1692 "next cpb count 0x%X next cpb idx 0x%x\n",
1693 notifier, notifier_error, gen_ctl, status,
1694 cpb_count, next_cpb_idx);
Robert Hancock2cb27852007-02-11 18:34:44 -06001695
Jeff Garzikb4479162007-10-25 20:47:30 -04001696 for (i = 0; i < NV_ADMA_MAX_CPBS; i++) {
Robert Hancock2cb27852007-02-11 18:34:44 -06001697 struct nv_adma_cpb *cpb = &pp->cpb[i];
Jeff Garzikb4479162007-10-25 20:47:30 -04001698 if ((ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) ||
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001699 ap->link.sactive & (1 << i))
Robert Hancock2cb27852007-02-11 18:34:44 -06001700 ata_port_printk(ap, KERN_ERR,
1701 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
1702 i, cpb->ctl_flags, cpb->resp_flags);
1703 }
1704 }
Robert Hancockfbbb2622006-10-27 19:08:41 -07001705
Robert Hancockfbbb2622006-10-27 19:08:41 -07001706 /* Push us back into port register mode for error handling. */
1707 nv_adma_register_mode(ap);
1708
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001709 /* Mark all of the CPBs as invalid to prevent them from
1710 being executed */
Jeff Garzikb4479162007-10-25 20:47:30 -04001711 for (i = 0; i < NV_ADMA_MAX_CPBS; i++)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001712 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1713
1714 /* clear CPB fetch count */
1715 writew(0, mmio + NV_ADMA_CPB_COUNT);
1716
1717 /* Reset channel */
1718 tmp = readw(mmio + NV_ADMA_CTL);
1719 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzikb4479162007-10-25 20:47:30 -04001720 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001721 udelay(1);
1722 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzikb4479162007-10-25 20:47:30 -04001723 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001724 }
1725
Tejun Heofe06e5f2010-05-10 21:41:39 +02001726 ata_bmdma_error_handler(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001727}
1728
Kuan Luof140f0f2007-10-15 15:16:53 -04001729static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
1730{
1731 struct nv_swncq_port_priv *pp = ap->private_data;
1732 struct defer_queue *dq = &pp->defer_queue;
1733
1734 /* queue is full */
1735 WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE);
1736 dq->defer_bits |= (1 << qc->tag);
1737 dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag;
1738}
1739
1740static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap)
1741{
1742 struct nv_swncq_port_priv *pp = ap->private_data;
1743 struct defer_queue *dq = &pp->defer_queue;
1744 unsigned int tag;
1745
1746 if (dq->head == dq->tail) /* null queue */
1747 return NULL;
1748
1749 tag = dq->tag[dq->head & (ATA_MAX_QUEUE - 1)];
1750 dq->tag[dq->head++ & (ATA_MAX_QUEUE - 1)] = ATA_TAG_POISON;
1751 WARN_ON(!(dq->defer_bits & (1 << tag)));
1752 dq->defer_bits &= ~(1 << tag);
1753
1754 return ata_qc_from_tag(ap, tag);
1755}
1756
1757static void nv_swncq_fis_reinit(struct ata_port *ap)
1758{
1759 struct nv_swncq_port_priv *pp = ap->private_data;
1760
1761 pp->dhfis_bits = 0;
1762 pp->dmafis_bits = 0;
1763 pp->sdbfis_bits = 0;
1764 pp->ncq_flags = 0;
1765}
1766
1767static void nv_swncq_pp_reinit(struct ata_port *ap)
1768{
1769 struct nv_swncq_port_priv *pp = ap->private_data;
1770 struct defer_queue *dq = &pp->defer_queue;
1771
1772 dq->head = 0;
1773 dq->tail = 0;
1774 dq->defer_bits = 0;
1775 pp->qc_active = 0;
1776 pp->last_issue_tag = ATA_TAG_POISON;
1777 nv_swncq_fis_reinit(ap);
1778}
1779
1780static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis)
1781{
1782 struct nv_swncq_port_priv *pp = ap->private_data;
1783
1784 writew(fis, pp->irq_block);
1785}
1786
1787static void __ata_bmdma_stop(struct ata_port *ap)
1788{
1789 struct ata_queued_cmd qc;
1790
1791 qc.ap = ap;
1792 ata_bmdma_stop(&qc);
1793}
1794
1795static void nv_swncq_ncq_stop(struct ata_port *ap)
1796{
1797 struct nv_swncq_port_priv *pp = ap->private_data;
1798 unsigned int i;
1799 u32 sactive;
1800 u32 done_mask;
1801
1802 ata_port_printk(ap, KERN_ERR,
1803 "EH in SWNCQ mode,QC:qc_active 0x%X sactive 0x%X\n",
1804 ap->qc_active, ap->link.sactive);
1805 ata_port_printk(ap, KERN_ERR,
1806 "SWNCQ:qc_active 0x%X defer_bits 0x%X last_issue_tag 0x%x\n "
1807 "dhfis 0x%X dmafis 0x%X sdbfis 0x%X\n",
1808 pp->qc_active, pp->defer_queue.defer_bits, pp->last_issue_tag,
1809 pp->dhfis_bits, pp->dmafis_bits, pp->sdbfis_bits);
1810
1811 ata_port_printk(ap, KERN_ERR, "ATA_REG 0x%X ERR_REG 0x%X\n",
Tejun Heo5682ed32008-04-07 22:47:16 +09001812 ap->ops->sff_check_status(ap),
Kuan Luof140f0f2007-10-15 15:16:53 -04001813 ioread8(ap->ioaddr.error_addr));
1814
1815 sactive = readl(pp->sactive_block);
1816 done_mask = pp->qc_active ^ sactive;
1817
1818 ata_port_printk(ap, KERN_ERR, "tag : dhfis dmafis sdbfis sacitve\n");
1819 for (i = 0; i < ATA_MAX_QUEUE; i++) {
1820 u8 err = 0;
1821 if (pp->qc_active & (1 << i))
1822 err = 0;
1823 else if (done_mask & (1 << i))
1824 err = 1;
1825 else
1826 continue;
1827
1828 ata_port_printk(ap, KERN_ERR,
1829 "tag 0x%x: %01x %01x %01x %01x %s\n", i,
1830 (pp->dhfis_bits >> i) & 0x1,
1831 (pp->dmafis_bits >> i) & 0x1,
1832 (pp->sdbfis_bits >> i) & 0x1,
1833 (sactive >> i) & 0x1,
1834 (err ? "error! tag doesn't exit" : " "));
1835 }
1836
1837 nv_swncq_pp_reinit(ap);
Tejun Heo5682ed32008-04-07 22:47:16 +09001838 ap->ops->sff_irq_clear(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001839 __ata_bmdma_stop(ap);
1840 nv_swncq_irq_clear(ap, 0xffff);
1841}
1842
1843static void nv_swncq_error_handler(struct ata_port *ap)
1844{
1845 struct ata_eh_context *ehc = &ap->link.eh_context;
1846
1847 if (ap->link.sactive) {
1848 nv_swncq_ncq_stop(ap);
Tejun Heocf480622008-01-24 00:05:14 +09001849 ehc->i.action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04001850 }
1851
Tejun Heofe06e5f2010-05-10 21:41:39 +02001852 ata_bmdma_error_handler(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001853}
1854
1855#ifdef CONFIG_PM
1856static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg)
1857{
1858 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1859 u32 tmp;
1860
1861 /* clear irq */
1862 writel(~0, mmio + NV_INT_STATUS_MCP55);
1863
1864 /* disable irq */
1865 writel(0, mmio + NV_INT_ENABLE_MCP55);
1866
1867 /* disable swncq */
1868 tmp = readl(mmio + NV_CTL_MCP55);
1869 tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ);
1870 writel(tmp, mmio + NV_CTL_MCP55);
1871
1872 return 0;
1873}
1874
1875static int nv_swncq_port_resume(struct ata_port *ap)
1876{
1877 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1878 u32 tmp;
1879
1880 /* clear irq */
1881 writel(~0, mmio + NV_INT_STATUS_MCP55);
1882
1883 /* enable irq */
1884 writel(0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
1885
1886 /* enable swncq */
1887 tmp = readl(mmio + NV_CTL_MCP55);
1888 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1889
1890 return 0;
1891}
1892#endif
1893
1894static void nv_swncq_host_init(struct ata_host *host)
1895{
1896 u32 tmp;
1897 void __iomem *mmio = host->iomap[NV_MMIO_BAR];
1898 struct pci_dev *pdev = to_pci_dev(host->dev);
1899 u8 regval;
1900
1901 /* disable ECO 398 */
1902 pci_read_config_byte(pdev, 0x7f, &regval);
1903 regval &= ~(1 << 7);
1904 pci_write_config_byte(pdev, 0x7f, regval);
1905
1906 /* enable swncq */
1907 tmp = readl(mmio + NV_CTL_MCP55);
1908 VPRINTK("HOST_CTL:0x%X\n", tmp);
1909 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1910
1911 /* enable irq intr */
1912 tmp = readl(mmio + NV_INT_ENABLE_MCP55);
1913 VPRINTK("HOST_ENABLE:0x%X\n", tmp);
1914 writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
1915
1916 /* clear port irq */
1917 writel(~0x0, mmio + NV_INT_STATUS_MCP55);
1918}
1919
1920static int nv_swncq_slave_config(struct scsi_device *sdev)
1921{
1922 struct ata_port *ap = ata_shost_to_port(sdev->host);
1923 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1924 struct ata_device *dev;
1925 int rc;
1926 u8 rev;
1927 u8 check_maxtor = 0;
1928 unsigned char model_num[ATA_ID_PROD_LEN + 1];
1929
1930 rc = ata_scsi_slave_config(sdev);
1931 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
1932 /* Not a proper libata device, ignore */
1933 return rc;
1934
1935 dev = &ap->link.device[sdev->id];
1936 if (!(ap->flags & ATA_FLAG_NCQ) || dev->class == ATA_DEV_ATAPI)
1937 return rc;
1938
1939 /* if MCP51 and Maxtor, then disable ncq */
1940 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA ||
1941 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2)
1942 check_maxtor = 1;
1943
1944 /* if MCP55 and rev <= a2 and Maxtor, then disable ncq */
1945 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA ||
1946 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2) {
1947 pci_read_config_byte(pdev, 0x8, &rev);
1948 if (rev <= 0xa2)
1949 check_maxtor = 1;
1950 }
1951
1952 if (!check_maxtor)
1953 return rc;
1954
1955 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
1956
1957 if (strncmp(model_num, "Maxtor", 6) == 0) {
Mike Christiee881a172009-10-15 17:46:39 -07001958 ata_scsi_change_queue_depth(sdev, 1, SCSI_QDEPTH_DEFAULT);
Kuan Luof140f0f2007-10-15 15:16:53 -04001959 ata_dev_printk(dev, KERN_NOTICE,
1960 "Disabling SWNCQ mode (depth %x)\n", sdev->queue_depth);
1961 }
1962
1963 return rc;
1964}
1965
1966static int nv_swncq_port_start(struct ata_port *ap)
1967{
1968 struct device *dev = ap->host->dev;
1969 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1970 struct nv_swncq_port_priv *pp;
1971 int rc;
1972
Tejun Heoc7087652010-05-10 21:41:34 +02001973 /* we might fallback to bmdma, allocate bmdma resources */
1974 rc = ata_bmdma_port_start(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001975 if (rc)
1976 return rc;
1977
1978 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1979 if (!pp)
1980 return -ENOMEM;
1981
1982 pp->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE,
1983 &pp->prd_dma, GFP_KERNEL);
1984 if (!pp->prd)
1985 return -ENOMEM;
1986 memset(pp->prd, 0, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE);
1987
1988 ap->private_data = pp;
1989 pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE;
1990 pp->irq_block = mmio + NV_INT_STATUS_MCP55 + ap->port_no * 2;
1991 pp->tag_block = mmio + NV_NCQ_REG_MCP55 + ap->port_no * 2;
1992
1993 return 0;
1994}
1995
1996static void nv_swncq_qc_prep(struct ata_queued_cmd *qc)
1997{
1998 if (qc->tf.protocol != ATA_PROT_NCQ) {
Tejun Heof47451c2010-05-10 21:41:40 +02001999 ata_bmdma_qc_prep(qc);
Kuan Luof140f0f2007-10-15 15:16:53 -04002000 return;
2001 }
2002
2003 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2004 return;
2005
2006 nv_swncq_fill_sg(qc);
2007}
2008
2009static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
2010{
2011 struct ata_port *ap = qc->ap;
2012 struct scatterlist *sg;
Kuan Luof140f0f2007-10-15 15:16:53 -04002013 struct nv_swncq_port_priv *pp = ap->private_data;
Tejun Heof60d7012010-05-10 21:41:41 +02002014 struct ata_bmdma_prd *prd;
Tejun Heoff2aeb12007-12-05 16:43:11 +09002015 unsigned int si, idx;
Kuan Luof140f0f2007-10-15 15:16:53 -04002016
2017 prd = pp->prd + ATA_MAX_PRD * qc->tag;
2018
2019 idx = 0;
Tejun Heoff2aeb12007-12-05 16:43:11 +09002020 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Kuan Luof140f0f2007-10-15 15:16:53 -04002021 u32 addr, offset;
2022 u32 sg_len, len;
2023
2024 addr = (u32)sg_dma_address(sg);
2025 sg_len = sg_dma_len(sg);
2026
2027 while (sg_len) {
2028 offset = addr & 0xffff;
2029 len = sg_len;
2030 if ((offset + sg_len) > 0x10000)
2031 len = 0x10000 - offset;
2032
2033 prd[idx].addr = cpu_to_le32(addr);
2034 prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2035
2036 idx++;
2037 sg_len -= len;
2038 addr += len;
2039 }
2040 }
2041
Tejun Heoff2aeb12007-12-05 16:43:11 +09002042 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
Kuan Luof140f0f2007-10-15 15:16:53 -04002043}
2044
2045static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap,
2046 struct ata_queued_cmd *qc)
2047{
2048 struct nv_swncq_port_priv *pp = ap->private_data;
2049
2050 if (qc == NULL)
2051 return 0;
2052
2053 DPRINTK("Enter\n");
2054
2055 writel((1 << qc->tag), pp->sactive_block);
2056 pp->last_issue_tag = qc->tag;
2057 pp->dhfis_bits &= ~(1 << qc->tag);
2058 pp->dmafis_bits &= ~(1 << qc->tag);
2059 pp->qc_active |= (0x1 << qc->tag);
2060
Tejun Heo5682ed32008-04-07 22:47:16 +09002061 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2062 ap->ops->sff_exec_command(ap, &qc->tf);
Kuan Luof140f0f2007-10-15 15:16:53 -04002063
2064 DPRINTK("Issued tag %u\n", qc->tag);
2065
2066 return 0;
2067}
2068
2069static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
2070{
2071 struct ata_port *ap = qc->ap;
2072 struct nv_swncq_port_priv *pp = ap->private_data;
2073
2074 if (qc->tf.protocol != ATA_PROT_NCQ)
Tejun Heo360ff782010-05-10 21:41:42 +02002075 return ata_bmdma_qc_issue(qc);
Kuan Luof140f0f2007-10-15 15:16:53 -04002076
2077 DPRINTK("Enter\n");
2078
2079 if (!pp->qc_active)
2080 nv_swncq_issue_atacmd(ap, qc);
2081 else
2082 nv_swncq_qc_to_dq(ap, qc); /* add qc to defer queue */
2083
2084 return 0;
2085}
2086
2087static void nv_swncq_hotplug(struct ata_port *ap, u32 fis)
2088{
2089 u32 serror;
2090 struct ata_eh_info *ehi = &ap->link.eh_info;
2091
2092 ata_ehi_clear_desc(ehi);
2093
2094 /* AHCI needs SError cleared; otherwise, it might lock up */
2095 sata_scr_read(&ap->link, SCR_ERROR, &serror);
2096 sata_scr_write(&ap->link, SCR_ERROR, serror);
2097
2098 /* analyze @irq_stat */
2099 if (fis & NV_SWNCQ_IRQ_ADDED)
2100 ata_ehi_push_desc(ehi, "hot plug");
2101 else if (fis & NV_SWNCQ_IRQ_REMOVED)
2102 ata_ehi_push_desc(ehi, "hot unplug");
2103
2104 ata_ehi_hotplugged(ehi);
2105
2106 /* okay, let's hand over to EH */
2107 ehi->serror |= serror;
2108
2109 ata_port_freeze(ap);
2110}
2111
2112static int nv_swncq_sdbfis(struct ata_port *ap)
2113{
2114 struct ata_queued_cmd *qc;
2115 struct nv_swncq_port_priv *pp = ap->private_data;
2116 struct ata_eh_info *ehi = &ap->link.eh_info;
2117 u32 sactive;
Kuan Luof140f0f2007-10-15 15:16:53 -04002118 u32 done_mask;
Kuan Luof140f0f2007-10-15 15:16:53 -04002119 u8 host_stat;
2120 u8 lack_dhfis = 0;
2121
2122 host_stat = ap->ops->bmdma_status(ap);
2123 if (unlikely(host_stat & ATA_DMA_ERR)) {
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002124 /* error when transferring data to/from memory */
Kuan Luof140f0f2007-10-15 15:16:53 -04002125 ata_ehi_clear_desc(ehi);
2126 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2127 ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002128 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002129 return -EINVAL;
2130 }
2131
Tejun Heo5682ed32008-04-07 22:47:16 +09002132 ap->ops->sff_irq_clear(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002133 __ata_bmdma_stop(ap);
2134
2135 sactive = readl(pp->sactive_block);
2136 done_mask = pp->qc_active ^ sactive;
2137
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002138 pp->qc_active &= ~done_mask;
2139 pp->dhfis_bits &= ~done_mask;
2140 pp->dmafis_bits &= ~done_mask;
2141 pp->sdbfis_bits |= done_mask;
2142 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
Kuan Luof140f0f2007-10-15 15:16:53 -04002143
2144 if (!ap->qc_active) {
2145 DPRINTK("over\n");
2146 nv_swncq_pp_reinit(ap);
Tejun Heo752e3862010-06-25 15:02:59 +02002147 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002148 }
2149
2150 if (pp->qc_active & pp->dhfis_bits)
Tejun Heo752e3862010-06-25 15:02:59 +02002151 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002152
2153 if ((pp->ncq_flags & ncq_saw_backout) ||
2154 (pp->qc_active ^ pp->dhfis_bits))
Tejun Heo752e3862010-06-25 15:02:59 +02002155 /* if the controller can't get a device to host register FIS,
Kuan Luof140f0f2007-10-15 15:16:53 -04002156 * The driver needs to reissue the new command.
2157 */
2158 lack_dhfis = 1;
2159
2160 DPRINTK("id 0x%x QC: qc_active 0x%x,"
2161 "SWNCQ:qc_active 0x%X defer_bits %X "
2162 "dhfis 0x%X dmafis 0x%X last_issue_tag %x\n",
2163 ap->print_id, ap->qc_active, pp->qc_active,
2164 pp->defer_queue.defer_bits, pp->dhfis_bits,
2165 pp->dmafis_bits, pp->last_issue_tag);
2166
2167 nv_swncq_fis_reinit(ap);
2168
2169 if (lack_dhfis) {
2170 qc = ata_qc_from_tag(ap, pp->last_issue_tag);
2171 nv_swncq_issue_atacmd(ap, qc);
Tejun Heo752e3862010-06-25 15:02:59 +02002172 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002173 }
2174
2175 if (pp->defer_queue.defer_bits) {
2176 /* send deferral queue command */
2177 qc = nv_swncq_qc_from_dq(ap);
2178 WARN_ON(qc == NULL);
2179 nv_swncq_issue_atacmd(ap, qc);
2180 }
2181
Tejun Heo752e3862010-06-25 15:02:59 +02002182 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002183}
2184
2185static inline u32 nv_swncq_tag(struct ata_port *ap)
2186{
2187 struct nv_swncq_port_priv *pp = ap->private_data;
2188 u32 tag;
2189
2190 tag = readb(pp->tag_block) >> 2;
2191 return (tag & 0x1f);
2192}
2193
Tejun Heo752e3862010-06-25 15:02:59 +02002194static void nv_swncq_dmafis(struct ata_port *ap)
Kuan Luof140f0f2007-10-15 15:16:53 -04002195{
2196 struct ata_queued_cmd *qc;
2197 unsigned int rw;
2198 u8 dmactl;
2199 u32 tag;
2200 struct nv_swncq_port_priv *pp = ap->private_data;
2201
2202 __ata_bmdma_stop(ap);
2203 tag = nv_swncq_tag(ap);
2204
2205 DPRINTK("dma setup tag 0x%x\n", tag);
2206 qc = ata_qc_from_tag(ap, tag);
2207
2208 if (unlikely(!qc))
Tejun Heo752e3862010-06-25 15:02:59 +02002209 return;
Kuan Luof140f0f2007-10-15 15:16:53 -04002210
2211 rw = qc->tf.flags & ATA_TFLAG_WRITE;
2212
2213 /* load PRD table addr. */
2214 iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag,
2215 ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2216
2217 /* specify data direction, triple-check start bit is clear */
2218 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2219 dmactl &= ~ATA_DMA_WR;
2220 if (!rw)
2221 dmactl |= ATA_DMA_WR;
2222
2223 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
Kuan Luof140f0f2007-10-15 15:16:53 -04002224}
2225
2226static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
2227{
2228 struct nv_swncq_port_priv *pp = ap->private_data;
2229 struct ata_queued_cmd *qc;
2230 struct ata_eh_info *ehi = &ap->link.eh_info;
2231 u32 serror;
2232 u8 ata_stat;
Kuan Luof140f0f2007-10-15 15:16:53 -04002233
Tejun Heo5682ed32008-04-07 22:47:16 +09002234 ata_stat = ap->ops->sff_check_status(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002235 nv_swncq_irq_clear(ap, fis);
2236 if (!fis)
2237 return;
2238
2239 if (ap->pflags & ATA_PFLAG_FROZEN)
2240 return;
2241
2242 if (fis & NV_SWNCQ_IRQ_HOTPLUG) {
2243 nv_swncq_hotplug(ap, fis);
2244 return;
2245 }
2246
2247 if (!pp->qc_active)
2248 return;
2249
Tejun Heo82ef04f2008-07-31 17:02:40 +09002250 if (ap->ops->scr_read(&ap->link, SCR_ERROR, &serror))
Kuan Luof140f0f2007-10-15 15:16:53 -04002251 return;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002252 ap->ops->scr_write(&ap->link, SCR_ERROR, serror);
Kuan Luof140f0f2007-10-15 15:16:53 -04002253
2254 if (ata_stat & ATA_ERR) {
2255 ata_ehi_clear_desc(ehi);
2256 ata_ehi_push_desc(ehi, "Ata error. fis:0x%X", fis);
2257 ehi->err_mask |= AC_ERR_DEV;
2258 ehi->serror |= serror;
Tejun Heocf480622008-01-24 00:05:14 +09002259 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002260 ata_port_freeze(ap);
2261 return;
2262 }
2263
2264 if (fis & NV_SWNCQ_IRQ_BACKOUT) {
2265 /* If the IRQ is backout, driver must issue
2266 * the new command again some time later.
2267 */
2268 pp->ncq_flags |= ncq_saw_backout;
2269 }
2270
2271 if (fis & NV_SWNCQ_IRQ_SDBFIS) {
2272 pp->ncq_flags |= ncq_saw_sdb;
2273 DPRINTK("id 0x%x SWNCQ: qc_active 0x%X "
2274 "dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
2275 ap->print_id, pp->qc_active, pp->dhfis_bits,
2276 pp->dmafis_bits, readl(pp->sactive_block));
Tejun Heo752e3862010-06-25 15:02:59 +02002277 if (nv_swncq_sdbfis(ap) < 0)
Kuan Luof140f0f2007-10-15 15:16:53 -04002278 goto irq_error;
2279 }
2280
2281 if (fis & NV_SWNCQ_IRQ_DHREGFIS) {
2282 /* The interrupt indicates the new command
2283 * was transmitted correctly to the drive.
2284 */
2285 pp->dhfis_bits |= (0x1 << pp->last_issue_tag);
2286 pp->ncq_flags |= ncq_saw_d2h;
2287 if (pp->ncq_flags & (ncq_saw_sdb | ncq_saw_backout)) {
2288 ata_ehi_push_desc(ehi, "illegal fis transaction");
2289 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002290 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002291 goto irq_error;
2292 }
2293
2294 if (!(fis & NV_SWNCQ_IRQ_DMASETUP) &&
2295 !(pp->ncq_flags & ncq_saw_dmas)) {
Tejun Heo5682ed32008-04-07 22:47:16 +09002296 ata_stat = ap->ops->sff_check_status(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002297 if (ata_stat & ATA_BUSY)
2298 goto irq_exit;
2299
2300 if (pp->defer_queue.defer_bits) {
2301 DPRINTK("send next command\n");
2302 qc = nv_swncq_qc_from_dq(ap);
2303 nv_swncq_issue_atacmd(ap, qc);
2304 }
2305 }
2306 }
2307
2308 if (fis & NV_SWNCQ_IRQ_DMASETUP) {
2309 /* program the dma controller with appropriate PRD buffers
2310 * and start the DMA transfer for requested command.
2311 */
2312 pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
2313 pp->ncq_flags |= ncq_saw_dmas;
Tejun Heo752e3862010-06-25 15:02:59 +02002314 nv_swncq_dmafis(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002315 }
2316
2317irq_exit:
2318 return;
2319irq_error:
2320 ata_ehi_push_desc(ehi, "fis:0x%x", fis);
2321 ata_port_freeze(ap);
2322 return;
2323}
2324
2325static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance)
2326{
2327 struct ata_host *host = dev_instance;
2328 unsigned int i;
2329 unsigned int handled = 0;
2330 unsigned long flags;
2331 u32 irq_stat;
2332
2333 spin_lock_irqsave(&host->lock, flags);
2334
2335 irq_stat = readl(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_MCP55);
2336
2337 for (i = 0; i < host->n_ports; i++) {
2338 struct ata_port *ap = host->ports[i];
2339
Tejun Heo3e4ec342010-05-10 21:41:30 +02002340 if (ap->link.sactive) {
2341 nv_swncq_host_interrupt(ap, (u16)irq_stat);
2342 handled = 1;
2343 } else {
2344 if (irq_stat) /* reserve Hotplug */
2345 nv_swncq_irq_clear(ap, 0xfff0);
Kuan Luof140f0f2007-10-15 15:16:53 -04002346
Tejun Heo3e4ec342010-05-10 21:41:30 +02002347 handled += nv_host_intr(ap, (u8)irq_stat);
Kuan Luof140f0f2007-10-15 15:16:53 -04002348 }
2349 irq_stat >>= NV_INT_PORT_SHIFT_MCP55;
2350 }
2351
2352 spin_unlock_irqrestore(&host->lock, flags);
2353
2354 return IRQ_RETVAL(handled);
2355}
2356
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002357static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002358{
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002359 static int printed_version;
Tejun Heo1626aeb2007-05-04 12:43:58 +02002360 const struct ata_port_info *ppi[] = { NULL, NULL };
Tejun Heo95947192008-03-25 12:22:49 +09002361 struct nv_pi_priv *ipriv;
Tejun Heo9a829cc2007-04-17 23:44:08 +09002362 struct ata_host *host;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002363 struct nv_host_priv *hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002364 int rc;
2365 u32 bar;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002366 void __iomem *base;
Robert Hancockfbbb2622006-10-27 19:08:41 -07002367 unsigned long type = ent->driver_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002368
2369 // Make sure this is a SATA controller by counting the number of bars
2370 // (NVIDIA SATA controllers will always have six bars). Otherwise,
2371 // it's an IDE controller and we ignore it.
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002372 for (bar = 0; bar < 6; bar++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002373 if (pci_resource_start(pdev, bar) == 0)
2374 return -ENODEV;
2375
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002376 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002377 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002378
Tejun Heo24dc5f32007-01-20 16:00:28 +09002379 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002380 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002381 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002382
Tejun Heo9a829cc2007-04-17 23:44:08 +09002383 /* determine type and allocate host */
Kuan Luof140f0f2007-10-15 15:16:53 -04002384 if (type == CK804 && adma_enabled) {
Robert Hancockfbbb2622006-10-27 19:08:41 -07002385 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
2386 type = ADMA;
Tejun Heo2d775702009-01-25 11:29:38 +09002387 } else if (type == MCP5x && swncq_enabled) {
2388 dev_printk(KERN_NOTICE, &pdev->dev, "Using SWNCQ mode\n");
2389 type = SWNCQ;
Jeff Garzik360737a2007-10-29 06:49:24 -04002390 }
2391
Tejun Heo1626aeb2007-05-04 12:43:58 +02002392 ppi[0] = &nv_port_info[type];
Tejun Heo95947192008-03-25 12:22:49 +09002393 ipriv = ppi[0]->private_data;
Tejun Heo1c5afdf2010-05-19 22:10:22 +02002394 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
Tejun Heo9a829cc2007-04-17 23:44:08 +09002395 if (rc)
2396 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002397
Tejun Heo24dc5f32007-01-20 16:00:28 +09002398 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002399 if (!hpriv)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002400 return -ENOMEM;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002401 hpriv->type = type;
Tejun Heo9a829cc2007-04-17 23:44:08 +09002402 host->private_data = hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002403
Tejun Heo9a829cc2007-04-17 23:44:08 +09002404 /* request and iomap NV_MMIO_BAR */
2405 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
2406 if (rc)
2407 return rc;
2408
2409 /* configure SCR access */
2410 base = host->iomap[NV_MMIO_BAR];
2411 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
2412 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
Jeff Garzik02cbd922006-03-22 23:59:46 -05002413
Tejun Heoada364e2006-06-17 15:49:56 +09002414 /* enable SATA space for CK804 */
Robert Hancockfbbb2622006-10-27 19:08:41 -07002415 if (type >= CK804) {
Tejun Heoada364e2006-06-17 15:49:56 +09002416 u8 regval;
2417
2418 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2419 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2420 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
2421 }
2422
Tejun Heo9a829cc2007-04-17 23:44:08 +09002423 /* init ADMA */
Robert Hancockfbbb2622006-10-27 19:08:41 -07002424 if (type == ADMA) {
Tejun Heo9a829cc2007-04-17 23:44:08 +09002425 rc = nv_adma_host_init(host);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002426 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002427 return rc;
Jeff Garzik360737a2007-10-29 06:49:24 -04002428 } else if (type == SWNCQ)
Kuan Luof140f0f2007-10-15 15:16:53 -04002429 nv_swncq_host_init(host);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002430
Tony Vroon51c89492009-08-06 00:50:09 +01002431 if (msi_enabled) {
2432 dev_printk(KERN_NOTICE, &pdev->dev, "Using MSI\n");
2433 pci_enable_msi(pdev);
2434 }
2435
Tejun Heo9a829cc2007-04-17 23:44:08 +09002436 pci_set_master(pdev);
Tejun Heo95cc2c72010-05-14 11:48:50 +02002437 return ata_pci_sff_activate_host(host, ipriv->irq_handler, ipriv->sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002438}
2439
Tejun Heo438ac6d2007-03-02 17:31:26 +09002440#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002441static int nv_pci_device_resume(struct pci_dev *pdev)
2442{
2443 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2444 struct nv_host_priv *hpriv = host->private_data;
Robert Hancockce053fa2007-02-05 16:26:04 -08002445 int rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002446
Robert Hancockce053fa2007-02-05 16:26:04 -08002447 rc = ata_pci_device_do_resume(pdev);
Jeff Garzikb4479162007-10-25 20:47:30 -04002448 if (rc)
Robert Hancockce053fa2007-02-05 16:26:04 -08002449 return rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002450
2451 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Jeff Garzikb4479162007-10-25 20:47:30 -04002452 if (hpriv->type >= CK804) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002453 u8 regval;
2454
2455 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2456 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2457 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
2458 }
Jeff Garzikb4479162007-10-25 20:47:30 -04002459 if (hpriv->type == ADMA) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002460 u32 tmp32;
2461 struct nv_adma_port_priv *pp;
2462 /* enable/disable ADMA on the ports appropriately */
2463 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
2464
2465 pp = host->ports[0]->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04002466 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002467 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002468 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002469 else
2470 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002471 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002472 pp = host->ports[1]->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04002473 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002474 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002475 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002476 else
2477 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002478 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002479
2480 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
2481 }
2482 }
2483
2484 ata_host_resume(host);
2485
2486 return 0;
2487}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002488#endif
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002489
Jeff Garzikcca39742006-08-24 03:19:22 -04002490static void nv_ck804_host_stop(struct ata_host *host)
Tejun Heoada364e2006-06-17 15:49:56 +09002491{
Jeff Garzikcca39742006-08-24 03:19:22 -04002492 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heoada364e2006-06-17 15:49:56 +09002493 u8 regval;
2494
2495 /* disable SATA space for CK804 */
2496 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2497 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2498 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
Tejun Heoada364e2006-06-17 15:49:56 +09002499}
2500
Robert Hancockfbbb2622006-10-27 19:08:41 -07002501static void nv_adma_host_stop(struct ata_host *host)
2502{
2503 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002504 u32 tmp32;
2505
Robert Hancockfbbb2622006-10-27 19:08:41 -07002506 /* disable ADMA on the ports */
2507 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
2508 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
2509 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
2510 NV_MCP_SATA_CFG_20_PORT1_EN |
2511 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
2512
2513 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
2514
2515 nv_ck804_host_stop(host);
2516}
2517
Linus Torvalds1da177e2005-04-16 15:20:36 -07002518static int __init nv_init(void)
2519{
Pavel Roskinb7887192006-08-10 18:13:18 +09002520 return pci_register_driver(&nv_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002521}
2522
2523static void __exit nv_exit(void)
2524{
2525 pci_unregister_driver(&nv_pci_driver);
2526}
2527
2528module_init(nv_init);
2529module_exit(nv_exit);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002530module_param_named(adma, adma_enabled, bool, 0444);
Brandon Ehle55f784c2009-03-01 00:02:49 -08002531MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: false)");
Kuan Luof140f0f2007-10-15 15:16:53 -04002532module_param_named(swncq, swncq_enabled, bool, 0444);
Zoltan Boszormenyid21279f2008-03-28 14:33:46 -07002533MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: true)");
Tony Vroon51c89492009-08-06 00:50:09 +01002534module_param_named(msi, msi_enabled, bool, 0444);
2535MODULE_PARM_DESC(msi, "Enable use of MSI (Default: false)");
Kuan Luof140f0f2007-10-15 15:16:53 -04002536