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gerrit-public.fairphone.software / kernel / msm / 3928fef1bbaef2029bbddc91857eac2fd31e7d9d / . / arch / arm / boot / dts / msm8610.dtsi
blob: 89c14e777572a35486aea76e981fe03437fbdbd0 [file] [log] [blame]
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Olav Haugan54166782013-01-28 16:59:51 -0800[diff] [blame]14/include/ "msm-iommu-v0.dtsi"
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]15/include/ "msm8610-ion.dtsi"
Lokesh Batra8d55eec2013-02-26 11:31:21 -0800[diff] [blame]16/include/ "msm8610-gpu.dtsi"
Matt Wagantall1bf56932012-11-29 15:03:29 -0800[diff] [blame]17/include/ "msm-gdsc.dtsi"
Aparna Dasd16555b2013-03-06 15:46:38 -0800[diff] [blame]18/include/ "msm8610-coresight.dtsi"
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]19/include/ "msm8610-pm.dtsi"
Jeff Hugo53dcf0f2013-03-20 12:37:50 -0600[diff] [blame]20/include/ "msm8610-smp2p.dtsi"
Gagan Macbced3872013-02-04 19:18:04 -0700[diff] [blame]21/include/ "msm8610-bus.dtsi"
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]22
23/ {
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]24 model = "Qualcomm MSM 8610";
25 compatible = "qcom,msm8610";
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]26 interrupt-parent = <&intc>;
27
28 intc: interrupt-controller@f9000000 {
29 compatible = "qcom,msm-qgic2";
30 interrupt-controller;
31 #interrupt-cells = <3>;
32 reg = <0xf9000000 0x1000>,
33 <0xf9002000 0x1000>;
34 };
35
36 msmgpio: gpio@fd510000 {
37 compatible = "qcom,msm-gpio";
38 interrupt-controller;
39 #interrupt-cells = <2>;
40 reg = <0xfd510000 0x4000>;
Syed Rameez Mustafa86cccfc2012-12-10 18:06:08 -0800[diff] [blame]41 gpio-controller;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]42 #gpio-cells = <2>;
Rohit Vaswani341c2032012-11-08 18:49:29 -0800[diff] [blame]43 ngpio = <102>;
Rohit Vaswanid2001522012-12-05 19:23:44 -0800[diff] [blame]44 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -0800[diff] [blame]45 qcom,direct-connect-irqs = <8>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]46 };
47
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]48 aliases {
49 spi0 = &spi_0;
Venkat Gopalakrishnana6ce5f22013-04-04 14:24:57 -0700[diff] [blame]50 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
51 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]52 };
53
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -0700[diff] [blame]54 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -0800[diff] [blame]55 compatible = "arm,armv7-timer";
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -0700[diff] [blame]56 interrupts = <1 2 0 1 3 0>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]57 clock-frequency = <19200000>;
58 };
59
Arun Menon2a7e3772013-01-17 12:06:59 -0800[diff] [blame]60 qcom,msm-adsp-loader {
61 compatible = "qcom,adsp-loader";
62 qcom,adsp-state = <0>;
63 };
64
Abhimanyu Kapur032b1f42013-01-18 00:10:50 -0800[diff] [blame]65 qcom,msm-imem@fe805000 {
66 compatible = "qcom,msm-imem";
67 reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
68 };
69
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]70 serial@f991f000 {
71 compatible = "qcom,msm-lsuart-v14";
72 reg = <0xf991f000 0x1000>;
73 interrupts = <0 109 0>;
74 status = "disabled";
75 };
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]76
Arun Menon8e25dd42013-01-11 14:11:54 -0800[diff] [blame]77 qcom,vidc@fdc00000 {
78 compatible = "qcom,msm-vidc";
Sachin Shah4e1c8fe2013-03-20 15:10:05 -0700[diff] [blame]79 qcom,vidc-ns-map = <0x40000000 0x40000000>;
80 qcom,iommu-groups = <&q6_domain_ns>;
81 qcom,iommu-group-buffer-types = <0xfff>;
82 qcom,buffer-type-tz-usage-map = <0x1 0x1>,
83 <0x1fe 0x2>;
84 qcom,hfi = "q6";
Deva Ramasubramanian74b1dda2013-03-27 13:16:17 -0700[diff] [blame]85 qcom,max-hw-load = <97200>; /* FWVGA @ 30 * 2 */
Arun Menon8e25dd42013-01-11 14:11:54 -0800[diff] [blame]86 };
87
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]88 usb@f9a55000 {
89 compatible = "qcom,hsusb-otg";
90 reg = <0xf9a55000 0x400>;
Mayank Rana33d26662013-01-17 10:22:25 +0530[diff] [blame]91 interrupts = <0 134 0>, <0 140 0>;
92 interrupt-names = "core_irq", "async_irq";
Mayank Rana76c6ce22012-11-07 17:07:58 +0530[diff] [blame]93 HSUSB_VDDCX-supply = <&pm8110_s1>;
94 HSUSB_1p8-supply = <&pm8110_l10>;
95 HSUSB_3p3-supply = <&pm8110_l20>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]96
97 qcom,hsusb-otg-phy-type = <2>;
98 qcom,hsusb-otg-mode = <1>;
Mayank Rana29bb9f22013-04-04 18:25:12 +0530[diff] [blame]99 qcom,hsusb-otg-otg-control = <2>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]100 qcom,hsusb-otg-disable-reset;
Mayank Ranaa5491122013-04-04 18:32:25 +0530[diff] [blame]101 qcom,dp-manual-pullup;
Mayank Ranaf9295802013-04-04 18:36:44 +0530[diff] [blame]102
103 qcom,msm-bus,name = "usb2";
104 qcom,msm-bus,num-cases = <2>;
105 qcom,msm-bus,active-only = <0>;
106 qcom,msm-bus,num-paths = <1>;
107 qcom,msm-bus,vectors-KBps =
108 <87 512 0 0>,
109 <87 512 60000 960000>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]110 };
111
Mayank Ranacc0c5452013-01-29 16:41:53 +0530[diff] [blame]112 android_usb@fe8050c8 {
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]113 compatible = "qcom,android-usb";
Mayank Ranacc0c5452013-01-29 16:41:53 +0530[diff] [blame]114 reg = <0xfe8050c8 0xc8>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]115 };
116
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]117 sdcc1: qcom,sdcc@f9824000 {
118 cell-index = <1>; /* SDC1 eMMC slot */
119 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800[diff] [blame]120 reg = <0xf9824000 0x800>,
121 <0xf9824800 0x100>,
122 <0xf9804000 0x7000>;
123 reg-names = "core_mem", "dml_mem", "bam_mem";
124 interrupts = <0 123 0>, <0 137 0>;
125 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]126
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]127 vdd-supply = <&pm8110_l17>;
128 qcom,vdd-always-on;
129 qcom,vdd-lpm-sup;
130 qcom,vdd-voltage-level = <2900000 2900000>;
131 qcom,vdd-current-level = <9000 400000>;
132
133 vdd-io-supply = <&pm8110_l6>;
134 qcom,vdd-io-always-on;
135 qcom,vdd-io-lpm-sup;
136 qcom,vdd-io-voltage-level = <1800000 1800000>;
137 qcom,vdd-io-current-level = <9000 60000>;
138
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]139 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
140 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
141 qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
142 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]143
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]144 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]145 qcom,sup-voltages = <2900 2900>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]146 qcom,bus-width = <8>;
147 qcom,nonremovable;
148 qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Venkat Gopalakrishnan587b2252013-04-05 12:16:50 -0700[diff] [blame]149
150 status = "disabled";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]151 };
152
153 sdcc2: qcom,sdcc@f98a4000 {
154 cell-index = <2>; /* SDC2 SD card slot */
155 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800[diff] [blame]156 reg = <0xf98a4000 0x800>,
157 <0xf98a4800 0x100>,
158 <0xf9884000 0x7000>;
159 reg-names = "core_mem", "dml_mem", "bam_mem";
160 interrupts = <0 125 0>, <0 220 0>;
161 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]162
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]163 vdd-supply = <&pm8110_l18>;
164 qcom,vdd-voltage-level = <2950000 2950000>;
165 qcom,vdd-current-level = <9000 400000>;
166
167 vdd-io-supply = <&pm8110_l21>;
168 qcom,vdd-io-voltage-level = <1800000 2950000>;
169 qcom,vdd-io-current-level = <9000 50000>;
170
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]171 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
172 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
173 qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
174 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]175
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]176 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
177 qcom,sup-voltages = <2950 2950>;
178 qcom,bus-width = <4>;
179 qcom,xpc;
180 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
181 qcom,current-limit = <800>;
Venkat Gopalakrishnan587b2252013-04-05 12:16:50 -0700[diff] [blame]182
183 status = "disabled";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]184 };
185
Venkat Gopalakrishnana6ce5f22013-04-04 14:24:57 -0700[diff] [blame]186 sdhc_1: sdhci@f9824900 {
187 compatible = "qcom,sdhci-msm";
188 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
189 reg-names = "hc_mem", "core_mem";
190
191 interrupts = <0 123 0>, <0 138 0>;
192 interrupt-names = "hc_irq", "pwr_irq";
193
194 qcom,bus-width = <8>;
195 status = "disabled";
196 };
197
198 sdhc_2: sdhci@f98a4900 {
199 compatible = "qcom,sdhci-msm";
200 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
201 reg-names = "hc_mem", "core_mem";
202
203 interrupts = <0 125 0>, <0 221 0>;
204 interrupt-names = "hc_irq", "pwr_irq";
205
206 qcom,bus-width = <4>;
207 status = "disabled";
208 };
209
Yan He6c7304c2012-11-09 22:07:08 -0800[diff] [blame]210 qcom,sps {
211 compatible = "qcom,msm_sps";
212 qcom,device-type = <3>;
213 };
214
Jeff Hugo6a289a32012-11-29 16:16:47 -0700[diff] [blame]215 qcom,smem@d600000 {
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]216 compatible = "qcom,smem";
Jeff Hugo6a289a32012-11-29 16:16:47 -0700[diff] [blame]217 reg = <0xd600000 0x200000>,
Stepan Moskovchenkod6ee8262013-02-06 11:26:05 -0800[diff] [blame]218 <0xf9011000 0x1000>,
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]219 <0xfc428000 0x4000>;
220 reg-names = "smem", "irq-reg-base", "aux-mem1";
221
222 qcom,smd-modem {
223 compatible = "qcom,smd";
224 qcom,smd-edge = <0>;
225 qcom,smd-irq-offset = <0x8>;
226 qcom,smd-irq-bitmask = <0x1000>;
227 qcom,pil-string = "modem";
228 interrupts = <0 25 1>;
229 };
230
231 qcom,smsm-modem {
232 compatible = "qcom,smsm";
233 qcom,smsm-edge = <0>;
234 qcom,smsm-irq-offset = <0x8>;
235 qcom,smsm-irq-bitmask = <0x2000>;
236 interrupts = <0 26 1>;
237 };
238
239 qcom,smd-adsp {
240 compatible = "qcom,smd";
241 qcom,smd-edge = <1>;
242 qcom,smd-irq-offset = <0x8>;
243 qcom,smd-irq-bitmask = <0x100>;
244 qcom,pil-string = "adsp";
245 interrupts = <0 156 1>;
246 };
247
248 qcom,smsm-adsp {
249 compatible = "qcom,smsm";
250 qcom,smsm-edge = <1>;
251 qcom,smsm-irq-offset = <0x8>;
252 qcom,smsm-irq-bitmask = <0x200>;
253 interrupts = <0 157 1>;
254 };
255
256 qcom,smd-wcnss {
257 compatible = "qcom,smd";
258 qcom,smd-edge = <6>;
259 qcom,smd-irq-offset = <0x8>;
260 qcom,smd-irq-bitmask = <0x20000>;
261 qcom,pil-string = "wcnss";
262 interrupts = <0 142 1>;
263 };
264
265 qcom,smsm-wcnss {
266 compatible = "qcom,smsm";
267 qcom,smsm-edge = <6>;
268 qcom,smsm-irq-offset = <0x8>;
269 qcom,smsm-irq-bitmask = <0x80000>;
270 interrupts = <0 144 1>;
271 };
272
273 qcom,smd-rpm {
274 compatible = "qcom,smd";
275 qcom,smd-edge = <15>;
276 qcom,smd-irq-offset = <0x8>;
277 qcom,smd-irq-bitmask = <0x1>;
278 interrupts = <0 168 1>;
279 qcom,irq-no-suspend;
280 };
David Ng5a3cb232012-12-03 16:42:53 -0800[diff] [blame]281 };
Hanumant Singh4e334c82012-11-14 10:16:39 -0800[diff] [blame]282
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]283 rpm_bus: qcom,rpm-smd {
284 compatible = "qcom,rpm-smd";
285 rpm-channel-name = "rpm_requests";
286 rpm-channel-type = <15>; /* SMD_APPS_RPM */
Priyanka Mathur6e993c92013-03-20 11:17:27 -0700[diff] [blame]287 rpm-standalone;
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]288 };
289
Olav Haugan8340d932013-01-25 12:03:11 -0800[diff] [blame]290 qcom,msm-mem-hole {
291 compatible = "qcom,msm-mem-hole";
Olav Hauganfcc860e2013-04-06 10:56:06 -0700[diff] [blame]292 qcom,memblock-remove = <0x07B00000 0x6400000>; /* Address and Size of Hole */
Olav Haugan8340d932013-01-25 12:03:11 -0800[diff] [blame]293 };
294
Hanumant Singh4e334c82012-11-14 10:16:39 -0800[diff] [blame]295 qcom,wdt@f9017000 {
296 compatible = "qcom,msm-watchdog";
297 reg = <0xf9017000 0x1000>;
298 interrupts = <0 3 0>, <0 4 0>;
299 qcom,bark-time = <11000>;
300 qcom,pet-time = <10000>;
Mitchel Humpherys1be23802012-11-16 15:52:32 -0800[diff] [blame]301 qcom,ipi-ping;
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]302 };
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]303
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800[diff] [blame]304 qcom,acpuclk@f9011050 {
305 compatible = "qcom,acpuclk-a7";
306 reg = <0xf9011050 0x8>;
307 reg-names = "rcg_base";
Patrick Dalyf9451d22013-03-20 14:20:12 -0700[diff] [blame]308 a7_cpu-supply = <&apc_vreg_corner>;
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800[diff] [blame]309 a7_mem-supply = <&pm8110_l3>;
310 };
311
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]312 spmi_bus: qcom,spmi@fc4c0000 {
313 cell-index = <0>;
314 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]315 reg-names = "core", "intr", "cnfg";
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]316 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]317 <0Xfc4cb000 0x1000>,
318 <0Xfc4ca000 0x1000>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]319 /* 190,ee0_krait_hlos_spmi_periph_irq */
320 /* 187,channel_0_krait_hlos_trans_done_irq */
321 interrupts = <0 190 0>, <0 187 0>;
322 qcom,not-wakeup;
323 qcom,pmic-arb-ee = <0>;
324 qcom,pmic-arb-channel = <0>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]325 };
326
Gilad Avidovf84f2792013-01-31 13:26:39 -0700[diff] [blame]327 i2c@f9925000 { /* BLSP-1 QUP-3 */
328 cell-index = <0>;
329 compatible = "qcom,i2c-qup";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 reg-names = "qup_phys_addr";
333 reg = <0xf9925000 0x1000>;
334 interrupt-names = "qup_err_intr";
335 interrupts = <0 97 0>;
336 qcom,i2c-bus-freq = <100000>;
337 };
338
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]339
340 spi_0: spi@f9923000 { /* BLSP1 QUP1 */
341 compatible = "qcom,spi-qup-v2";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 reg-names = "spi_physical", "spi_bam_physical";
345 reg = <0xf9923000 0x1000>,
346 <0xf9904000 0xF000>;
347 interrupt-names = "spi_irq", "spi_bam_irq";
348 interrupts = <0 95 0>, <0 238 0>;
349 spi-max-frequency = <19200000>;
350
351 gpios = <&msmgpio 3 0>, /* CLK */
352 <&msmgpio 1 0>, /* MISO */
353 <&msmgpio 0 0>; /* MOSI */
354 cs-gpios = <&msmgpio 2 0>;
355
356 qcom,infinite-mode = <0>;
357 qcom,use-bam;
358 qcom,ver-reg-exists;
359 qcom,bam-consumer-pipe-index = <12>;
360 qcom,bam-producer-pipe-index = <13>;
361 };
362
Vikram Mulukutla1ac32fd2013-01-28 10:03:58 -0800[diff] [blame]363 qcom,pronto@fb21b000 {
364 compatible = "qcom,pil-pronto";
365 reg = <0xfb21b000 0x3000>,
366 <0xfc401700 0x4>,
367 <0xfd485300 0xc>;
368 reg-names = "pmu_base", "clk_base", "halt_base";
369 interrupts = <0 149 1>;
370 vdd_pronto_pll-supply = <&pm8110_l10>;
371
372 qcom,firmware-name = "wcnss";
Sameer Thalappil7abeb222013-04-02 11:13:42 -0700[diff] [blame]373
374 /* GPIO input from wcnss */
375 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
376
377 /* GPIO output to wcnss */
378 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
Vikram Mulukutla1ac32fd2013-01-28 10:03:58 -0800[diff] [blame]379 };
380
Fred Oh92b18a02013-01-22 13:29:41 -0800[diff] [blame]381 sound {
382 compatible = "qcom,msm8x10-audio-codec";
383 qcom,model = "msm8x10-snd-card";
384 };
385
386 qcom,msm-pcm {
387 compatible = "qcom,msm-pcm-dsp";
388 };
389
390 qcom,msm-pcm-routing {
391 compatible = "qcom,msm-pcm-routing";
392 };
393
394 qcom,msm-pcm-lpa {
395 compatible = "qcom,msm-pcm-lpa";
396 };
397
398 qcom,msm-compr-dsp {
399 compatible = "qcom,msm-compr-dsp";
400 };
401
402 qcom,msm-voip-dsp {
403 compatible = "qcom,msm-voip-dsp";
404 };
405
406 qcom,msm-pcm-voice {
407 compatible = "qcom,msm-pcm-voice";
408 };
409
410 qcom,msm-stub-codec {
411 compatible = "qcom,msm-stub-codec";
412 };
413
414 qcom,msm-dai-fe {
415 compatible = "qcom,msm-dai-fe";
416 };
417
418 qcom,msm-pcm-afe {
419 compatible = "qcom,msm-pcm-afe";
420 };
421
422 qcom,msm-dai-mi2s {
423 compatible = "qcom,msm-dai-mi2s";
424 qcom,msm-dai-q6-mi2s-prim {
425 compatible = "qcom,msm-dai-q6-mi2s";
426 qcom,msm-dai-q6-mi2s-dev-id = <0>;
427 qcom,msm-mi2s-rx-lines = <1>;
428 qcom,msm-mi2s-tx-lines = <0>;
429 };
430
431 qcom,msm-dai-q6-mi2s-sec {
432 compatible = "qcom,msm-dai-q6-mi2s";
433 qcom,msm-dai-q6-mi2s-dev-id = <1>;
434 qcom,msm-mi2s-rx-lines = <0>;
435 qcom,msm-mi2s-tx-lines = <3>;
436 };
437 };
438
439 qcom,msm-dai-q6 {
440 compatible = "qcom,msm-dai-q6";
441 qcom,msm-dai-q6-bt-sco-rx {
442 compatible = "qcom,msm-dai-q6-dev";
443 qcom,msm-dai-q6-dev-id = <12288>;
444 };
445
446 qcom,msm-dai-q6-bt-sco-tx {
447 compatible = "qcom,msm-dai-q6-dev";
448 qcom,msm-dai-q6-dev-id = <12289>;
449 };
450
451 qcom,msm-dai-q6-int-fm-rx {
452 compatible = "qcom,msm-dai-q6-dev";
453 qcom,msm-dai-q6-dev-id = <12292>;
454 };
455
456 qcom,msm-dai-q6-int-fm-tx {
457 compatible = "qcom,msm-dai-q6-dev";
458 qcom,msm-dai-q6-dev-id = <12293>;
459 };
460
461 qcom,msm-dai-q6-be-afe-pcm-rx {
462 compatible = "qcom,msm-dai-q6-dev";
463 qcom,msm-dai-q6-dev-id = <224>;
464 };
465
466 qcom,msm-dai-q6-be-afe-pcm-tx {
467 compatible = "qcom,msm-dai-q6-dev";
468 qcom,msm-dai-q6-dev-id = <225>;
469 };
470
471 qcom,msm-dai-q6-afe-proxy-rx {
472 compatible = "qcom,msm-dai-q6-dev";
473 qcom,msm-dai-q6-dev-id = <241>;
474 };
475
476 qcom,msm-dai-q6-afe-proxy-tx {
477 compatible = "qcom,msm-dai-q6-dev";
478 qcom,msm-dai-q6-dev-id = <240>;
479 };
480 };
481
482 qcom,msm-pcm-hostless {
483 compatible = "qcom,msm-pcm-hostless";
484 };
485
Sameer Thalappil3928fef2013-04-08 11:51:15 -0700[diff] [blame^]486 qcom,wcnss-wlan@fb000000 {
487 compatible = "qcom,wcnss_wlan";
488 reg = <0xfb000000 0x280000>;
489 reg-names = "wcnss_mmio";
490 interrupts = <0 145 0>, <0 146 0>;
491 interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
492
493 qcom,pronto-vddmx-supply = <&pm8110_l3>;
494 qcom,pronto-vddcx-supply = <&pm8110_s1>;
495 qcom,pronto-vddpx-supply = <&pm8110_l6>;
496 qcom,iris-vddxo-supply = <&pm8110_l10>;
497 qcom,iris-vddrfa-supply = <&pm8110_l5>;
498 qcom,iris-vddpa-supply = <&pm8110_l16>;
499 qcom,iris-vdddig-supply = <&pm8110_l5>;
500
501 gpios = <&msmgpio 23 0>, <&msmgpio 24 0>, <&msmgpio 25 0>, <&msmgpio 26 0>, <&msmgpio 27 0>;
502 qcom,has_pronto_hw;
503 };
504
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]505 qcom,mss@fc880000 {
506 compatible = "qcom,pil-q6v5-mss";
507 reg = <0xfc880000 0x100>,
508 <0xfd485000 0x400>,
509 <0xfc820000 0x020>,
510 <0xfc401680 0x004>,
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]511 <0xfd485194 0x4>;
512 reg-names = "qdsp6_base", "halt_base", "rmb_base",
Matt Wagantall724b2bb2013-03-18 14:54:06 -0700[diff] [blame]513 "restart_reg", "cxrail_bhs_reg";
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]514
515 interrupts = <0 24 1>;
516 vdd_mss-supply = <&pm8110_s1>;
517 vdd_cx-supply = <&pm8110_s1_corner>;
518 vdd_mx-supply = <&pm8110_l3>;
519 vdd_pll-supply = <&pm8110_l10>;
520 qcom,vdd_pll = <1800000>;
521 qcom,is-loadable;
522 qcom,firmware-name = "mba";
523 qcom,pil-self-auth;
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700[diff] [blame]524
Seemanta Duttaa0f253e2013-01-16 18:54:40 -0800[diff] [blame]525 /* GPIO inputs from mss */
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700[diff] [blame]526 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
Seemanta Duttaa0f253e2013-01-16 18:54:40 -0800[diff] [blame]527 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700[diff] [blame]528
529 /* GPIO output to mss */
530 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]531 };
532
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]533 qcom,lpass@fe200000 {
534 compatible = "qcom,pil-q6v5-lpass";
535 reg = <0xfe200000 0x00100>,
Matt Wagantall015b50af2013-03-05 18:51:16 -0800[diff] [blame]536 <0xfd485100 0x00010>,
537 <0xfc4016c0 0x00004>;
538 reg-names = "qdsp6_base", "halt_base", "restart_reg";
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]539 interrupts = <0 162 1>;
Matt Wagantall6c515982013-01-29 14:58:43 -0800[diff] [blame]540 vdd_cx-supply = <&pm8110_s1_corner>;
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]541 qcom,firmware-name = "adsp";
542 };
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]543
544 tsens: tsens@fc4a8000 {
545 compatible = "qcom,msm-tsens";
546 reg = <0xfc4a8000 0x2000>,
547 <0xfc4b8000 0x1000>;
548 reg-names = "tsens_physical", "tsens_eeprom_physical";
549 interrupts = <0 184 0>;
550 qcom,sensors = <2>;
551 qcom,slope = <2901 2846>;
Siddartha Mohanadossb2f48982013-03-28 13:51:38 -0700[diff] [blame]552 qcom,calib-mode = "fuse_map3";
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]553 qcom,calibration-less-mode;
Siddartha Mohanadoss0ca83312013-03-14 11:43:18 -0700[diff] [blame]554 qcom,tsens-local-init;
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]555 };
556
Jennifer Liuf588d3a2013-04-05 10:11:48 -0700[diff] [blame]557 qcom,msm-thermal {
558 compatible = "qcom,msm-thermal";
559 qcom,sensor-id = <0>;
560 qcom,poll-ms = <250>;
561 qcom,limit-temp = <60>;
562 qcom,temp-hysteresis = <10>;
563 qcom,freq-step = <2>;
564 };
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]565};
David Collinsc6b34832012-10-24 12:57:57 -0700[diff] [blame]566
Matt Wagantall1bf56932012-11-29 15:03:29 -0800[diff] [blame]567&gdsc_vfe {
568 status = "ok";
569};
570
571&gdsc_oxili_cx {
572 status = "ok";
573};
574
Olav Haugan9c255522012-11-16 16:43:17 -0800[diff] [blame]575&lpass_iommu {
576 status = "ok";
577};
578
579&copss_iommu {
580 status = "ok";
581};
582
583&mdpe_iommu {
584 status = "ok";
585};
586
587&mdps_iommu {
588 status = "ok";
589};
590
591&gfx_iommu {
592 status = "ok";
593};
594
595&vfe_iommu {
596 status = "ok";
597};
598
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]599/include/ "msm8610-iommu-domains.dtsi"
Olav Haugan4bc4b692012-12-10 18:29:35 -0800[diff] [blame]600
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]601/include/ "msm-pm8110.dtsi"
Xiaozhe Shi1581a7b2013-02-21 15:17:57 -0800[diff] [blame]602/include/ "msm8610-regulator.dtsi"
Siddartha Mohanadoss0f664a82013-03-11 22:52:01 -0700[diff] [blame]603
604&pm8110_vadc {
605 chan@0 {
606 label = "usb_in";
607 reg = <0>;
608 qcom,decimation = <0>;
609 qcom,pre-div-channel-scaling = <4>;
610 qcom,calibration-type = "absolute";
611 qcom,scale-function = <0>;
612 qcom,hw-settle-time = <0>;
613 qcom,fast-avg-setup = <0>;
614 };
615
616 chan@2 {
617 label = "vchg_sns";
618 reg = <2>;
619 qcom,decimation = <0>;
620 qcom,pre-div-channel-scaling = <3>;
621 qcom,calibration-type = "absolute";
622 qcom,scale-function = <0>;
623 qcom,hw-settle-time = <0>;
624 qcom,fast-avg-setup = <0>;
625 };
626
627 chan@5 {
628 label = "vcoin";
629 reg = <5>;
630 qcom,decimation = <0>;
631 qcom,pre-div-channel-scaling = <1>;
632 qcom,calibration-type = "absolute";
633 qcom,scale-function = <0>;
634 qcom,hw-settle-time = <0>;
635 qcom,fast-avg-setup = <0>;
636 };
637
638 chan@6 {
639 label = "vbat_sns";
640 reg = <6>;
641 qcom,decimation = <0>;
642 qcom,pre-div-channel-scaling = <1>;
643 qcom,calibration-type = "absolute";
644 qcom,scale-function = <0>;
645 qcom,hw-settle-time = <0>;
646 qcom,fast-avg-setup = <0>;
647 };
648
649 chan@7 {
650 label = "vph_pwr";
651 reg = <7>;
652 qcom,decimation = <0>;
653 qcom,pre-div-channel-scaling = <1>;
654 qcom,calibration-type = "absolute";
655 qcom,scale-function = <0>;
656 qcom,hw-settle-time = <0>;
657 qcom,fast-avg-setup = <0>;
658 };
659
660 chan@30 {
661 label = "batt_therm";
662 reg = <0x30>;
663 qcom,decimation = <0>;
664 qcom,pre-div-channel-scaling = <0>;
665 qcom,calibration-type = "ratiometric";
666 qcom,scale-function = <1>;
667 qcom,hw-settle-time = <2>;
668 qcom,fast-avg-setup = <0>;
669 };
670
671 chan@31 {
672 label = "batt_id";
673 reg = <0x31>;
674 qcom,decimation = <0>;
675 qcom,pre-div-channel-scaling = <0>;
676 qcom,calibration-type = "ratiometric";
677 qcom,scale-function = <0>;
678 qcom,hw-settle-time = <2>;
679 qcom,fast-avg-setup = <0>;
680 };
681
682 chan@b2 {
683 label = "xo_therm_pu2";
684 reg = <0xb2>;
685 qcom,decimation = <0>;
686 qcom,pre-div-channel-scaling = <0>;
687 qcom,calibration-type = "ratiometric";
688 qcom,scale-function = <4>;
689 qcom,hw-settle-time = <2>;
690 qcom,fast-avg-setup = <0>;
691 };
692};
693
694