Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ahci.c - AHCI SATA support |
| 3 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2004-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
domen@coderock.org | 87507cf | 2005-04-08 09:53:06 +0200 | [diff] [blame] | 42 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 43 | #include <linux/device.h> |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 44 | #include <linux/dmi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 46 | #include <scsi/scsi_cmnd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | #include <linux/libata.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
| 49 | #define DRV_NAME "ahci" |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 50 | #define DRV_VERSION "3.0" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 52 | /* Enclosure Management Control */ |
| 53 | #define EM_CTRL_MSG_TYPE 0x000f0000 |
| 54 | |
| 55 | /* Enclosure Management LED Message Type */ |
| 56 | #define EM_MSG_LED_HBA_PORT 0x0000000f |
| 57 | #define EM_MSG_LED_PMP_SLOT 0x0000ff00 |
| 58 | #define EM_MSG_LED_VALUE 0xffff0000 |
| 59 | #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 |
| 60 | #define EM_MSG_LED_VALUE_OFF 0xfff80000 |
| 61 | #define EM_MSG_LED_VALUE_ON 0x00010000 |
| 62 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame] | 63 | static int ahci_skip_host_reset; |
Arjan van de Ven | f3d7f23 | 2009-01-26 02:05:44 -0800 | [diff] [blame] | 64 | static int ahci_ignore_sss; |
| 65 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame] | 66 | module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); |
| 67 | MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); |
| 68 | |
Arjan van de Ven | f3d7f23 | 2009-01-26 02:05:44 -0800 | [diff] [blame] | 69 | module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); |
| 70 | MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); |
| 71 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 72 | static int ahci_enable_alpm(struct ata_port *ap, |
| 73 | enum link_pm policy); |
| 74 | static void ahci_disable_alpm(struct ata_port *ap); |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 75 | static ssize_t ahci_led_show(struct ata_port *ap, char *buf); |
| 76 | static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, |
| 77 | size_t size); |
| 78 | static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, |
| 79 | ssize_t size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | |
| 81 | enum { |
| 82 | AHCI_PCI_BAR = 5, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 83 | AHCI_MAX_PORTS = 32, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 85 | AHCI_DMA_BOUNDARY = 0xffffffff, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 86 | AHCI_MAX_CMDS = 32, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 87 | AHCI_CMD_SZ = 32, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 88 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | AHCI_RX_FIS_SZ = 256, |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 90 | AHCI_CMD_TBL_CDB = 0x40, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 91 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
| 92 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
| 93 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
| 94 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | AHCI_RX_FIS_SZ, |
| 96 | AHCI_IRQ_ON_SG = (1 << 31), |
| 97 | AHCI_CMD_ATAPI = (1 << 5), |
| 98 | AHCI_CMD_WRITE = (1 << 6), |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 99 | AHCI_CMD_PREFETCH = (1 << 7), |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 100 | AHCI_CMD_RESET = (1 << 8), |
| 101 | AHCI_CMD_CLR_BUSY = (1 << 10), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | |
| 103 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 104 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 105 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | |
| 107 | board_ahci = 0, |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 108 | board_ahci_vt8251 = 1, |
| 109 | board_ahci_ign_iferr = 2, |
| 110 | board_ahci_sb600 = 3, |
| 111 | board_ahci_mv = 4, |
Shane Huang | e427fe0 | 2008-12-30 10:53:41 +0800 | [diff] [blame] | 112 | board_ahci_sb700 = 5, /* for SB700 and SB800 */ |
Tejun Heo | e297d99 | 2008-06-10 00:13:04 +0900 | [diff] [blame] | 113 | board_ahci_mcp65 = 6, |
Tejun Heo | 9a3b103 | 2008-06-18 20:56:58 -0400 | [diff] [blame] | 114 | board_ahci_nopmp = 7, |
Tejun Heo | aa431dd | 2009-04-08 14:25:31 -0700 | [diff] [blame] | 115 | board_ahci_yesncq = 8, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | |
| 117 | /* global controller registers */ |
| 118 | HOST_CAP = 0x00, /* host capabilities */ |
| 119 | HOST_CTL = 0x04, /* global host control */ |
| 120 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 121 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 122 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 123 | HOST_EM_LOC = 0x1c, /* Enclosure Management location */ |
| 124 | HOST_EM_CTL = 0x20, /* Enclosure Management Control */ |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 125 | HOST_CAP2 = 0x24, /* host capabilities, extended */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | |
| 127 | /* HOST_CTL bits */ |
| 128 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 129 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
| 130 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 131 | |
| 132 | /* HOST_CAP bits */ |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 133 | HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 134 | HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 135 | HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ |
| 136 | HOST_CAP_PART = (1 << 13), /* Partial state capable */ |
| 137 | HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ |
| 138 | HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ |
| 139 | HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 140 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 141 | HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 142 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 143 | HOST_CAP_LED = (1 << 25), /* Supports activity LED */ |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 144 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 145 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 146 | HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 147 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
Tejun Heo | 979db80 | 2006-05-15 21:03:52 +0900 | [diff] [blame] | 148 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 149 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 151 | /* HOST_CAP2 bits */ |
| 152 | HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ |
| 153 | HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ |
| 154 | HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ |
| 155 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | /* registers for each SATA port */ |
| 157 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 158 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 159 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 160 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 161 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 162 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 163 | PORT_CMD = 0x18, /* port command */ |
| 164 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 165 | PORT_SIG = 0x24, /* device TF signature */ |
| 166 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 168 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 169 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 170 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 171 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | |
| 173 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 174 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 175 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 176 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 177 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 178 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 179 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 180 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 181 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 182 | |
| 183 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 184 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 185 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 186 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 187 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 188 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 189 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 190 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 191 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 192 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 193 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
| 194 | PORT_IRQ_IF_ERR | |
| 195 | PORT_IRQ_CONNECT | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 196 | PORT_IRQ_PHYRDY | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 197 | PORT_IRQ_UNK_FIS | |
| 198 | PORT_IRQ_BAD_PMP, |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 199 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
| 200 | PORT_IRQ_TF_ERR | |
| 201 | PORT_IRQ_HBUS_DATA_ERR, |
| 202 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
| 203 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
| 204 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | |
| 206 | /* PORT_CMD bits */ |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 207 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
| 208 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 209 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 210 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 212 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 213 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 214 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 216 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 217 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 218 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 219 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 221 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 222 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 223 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 224 | /* hpriv->flags bits */ |
| 225 | AHCI_HFLAG_NO_NCQ = (1 << 0), |
| 226 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ |
| 227 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ |
| 228 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ |
| 229 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ |
| 230 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 231 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 232 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 233 | AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
Tejun Heo | e297d99 | 2008-06-10 00:13:04 +0900 | [diff] [blame] | 234 | AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ |
Tejun Heo | 9b10ae8 | 2009-05-30 20:50:12 +0900 | [diff] [blame] | 235 | AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ |
Tejun Heo | 5594639 | 2009-08-04 14:30:08 +0900 | [diff] [blame] | 236 | AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as |
| 237 | link offline */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 238 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 239 | /* ap->flags bits */ |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 240 | |
| 241 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 242 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 243 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
| 244 | ATA_FLAG_IPM, |
Tejun Heo | c4f7792 | 2007-12-06 15:09:43 +0900 | [diff] [blame] | 245 | |
| 246 | ICH_MAP = 0x90, /* ICH MAP register */ |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 247 | |
Tejun Heo | d50ce07 | 2009-05-12 10:57:41 +0900 | [diff] [blame] | 248 | /* em constants */ |
| 249 | EM_MAX_SLOTS = 8, |
| 250 | EM_MAX_RETRY = 5, |
| 251 | |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 252 | /* em_ctl bits */ |
| 253 | EM_CTL_RST = (1 << 9), /* Reset */ |
| 254 | EM_CTL_TM = (1 << 8), /* Transmit Message */ |
| 255 | EM_CTL_ALHD = (1 << 26), /* Activity LED */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | }; |
| 257 | |
| 258 | struct ahci_cmd_hdr { |
Al Viro | 4ca4e43 | 2007-12-30 09:32:22 +0000 | [diff] [blame] | 259 | __le32 opts; |
| 260 | __le32 status; |
| 261 | __le32 tbl_addr; |
| 262 | __le32 tbl_addr_hi; |
| 263 | __le32 reserved[4]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | }; |
| 265 | |
| 266 | struct ahci_sg { |
Al Viro | 4ca4e43 | 2007-12-30 09:32:22 +0000 | [diff] [blame] | 267 | __le32 addr; |
| 268 | __le32 addr_hi; |
| 269 | __le32 reserved; |
| 270 | __le32 flags_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | }; |
| 272 | |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 273 | struct ahci_em_priv { |
| 274 | enum sw_activity blink_policy; |
| 275 | struct timer_list timer; |
| 276 | unsigned long saved_activity; |
| 277 | unsigned long activity; |
| 278 | unsigned long led_state; |
| 279 | }; |
| 280 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | struct ahci_host_priv { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 282 | unsigned int flags; /* AHCI_HFLAG_* */ |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 283 | u32 cap; /* cap to use */ |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 284 | u32 cap2; /* cap2 to use */ |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 285 | u32 port_map; /* port map to use */ |
| 286 | u32 saved_cap; /* saved initial cap */ |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 287 | u32 saved_cap2; /* saved initial cap2 */ |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 288 | u32 saved_port_map; /* saved initial port_map */ |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 289 | u32 em_loc; /* enclosure management location */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | struct ahci_port_priv { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 293 | struct ata_link *active_link; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | struct ahci_cmd_hdr *cmd_slot; |
| 295 | dma_addr_t cmd_slot_dma; |
| 296 | void *cmd_tbl; |
| 297 | dma_addr_t cmd_tbl_dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 298 | void *rx_fis; |
| 299 | dma_addr_t rx_fis_dma; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 300 | /* for NCQ spurious interrupt analysis */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 301 | unsigned int ncq_saw_d2h:1; |
| 302 | unsigned int ncq_saw_dmas:1; |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 303 | unsigned int ncq_saw_sdb:1; |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 304 | u32 intr_mask; /* interrupts to enable */ |
Tejun Heo | d50ce07 | 2009-05-12 10:57:41 +0900 | [diff] [blame] | 305 | /* enclosure management info per PM slot */ |
| 306 | struct ahci_em_priv em_priv[EM_MAX_SLOTS]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 307 | }; |
| 308 | |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 309 | static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
| 310 | static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 311 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 312 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Tejun Heo | 4c9bf4e | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 313 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | static int ahci_port_start(struct ata_port *ap); |
| 315 | static void ahci_port_stop(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 317 | static void ahci_freeze(struct ata_port *ap); |
| 318 | static void ahci_thaw(struct ata_port *ap); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 319 | static void ahci_pmp_attach(struct ata_port *ap); |
| 320 | static void ahci_pmp_detach(struct ata_port *ap); |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 321 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
| 322 | unsigned long deadline); |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 323 | static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, |
| 324 | unsigned long deadline); |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 325 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
| 326 | unsigned long deadline); |
| 327 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
| 328 | unsigned long deadline); |
| 329 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
| 330 | unsigned long deadline); |
| 331 | static void ahci_postreset(struct ata_link *link, unsigned int *class); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 332 | static void ahci_error_handler(struct ata_port *ap); |
| 333 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 334 | static int ahci_port_resume(struct ata_port *ap); |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 335 | static void ahci_dev_config(struct ata_device *dev); |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 336 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 337 | u32 opts); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 338 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 339 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 340 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
| 341 | static int ahci_pci_device_resume(struct pci_dev *pdev); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 342 | #endif |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 343 | static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); |
| 344 | static ssize_t ahci_activity_store(struct ata_device *dev, |
| 345 | enum sw_activity val); |
| 346 | static void ahci_init_sw_activity(struct ata_link *link); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | |
Matthew Garrett | 77cdec1 | 2009-07-17 19:13:47 +0100 | [diff] [blame] | 348 | static ssize_t ahci_show_host_caps(struct device *dev, |
| 349 | struct device_attribute *attr, char *buf); |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 350 | static ssize_t ahci_show_host_cap2(struct device *dev, |
| 351 | struct device_attribute *attr, char *buf); |
Matthew Garrett | 77cdec1 | 2009-07-17 19:13:47 +0100 | [diff] [blame] | 352 | static ssize_t ahci_show_host_version(struct device *dev, |
| 353 | struct device_attribute *attr, char *buf); |
| 354 | static ssize_t ahci_show_port_cmd(struct device *dev, |
| 355 | struct device_attribute *attr, char *buf); |
| 356 | |
| 357 | DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 358 | DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); |
Matthew Garrett | 77cdec1 | 2009-07-17 19:13:47 +0100 | [diff] [blame] | 359 | DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); |
| 360 | DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); |
| 361 | |
Tony Jones | ee959b0 | 2008-02-22 00:13:36 +0100 | [diff] [blame] | 362 | static struct device_attribute *ahci_shost_attrs[] = { |
| 363 | &dev_attr_link_power_management_policy, |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 364 | &dev_attr_em_message_type, |
| 365 | &dev_attr_em_message, |
Matthew Garrett | 77cdec1 | 2009-07-17 19:13:47 +0100 | [diff] [blame] | 366 | &dev_attr_ahci_host_caps, |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 367 | &dev_attr_ahci_host_cap2, |
Matthew Garrett | 77cdec1 | 2009-07-17 19:13:47 +0100 | [diff] [blame] | 368 | &dev_attr_ahci_host_version, |
| 369 | &dev_attr_ahci_port_cmd, |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 370 | NULL |
| 371 | }; |
| 372 | |
| 373 | static struct device_attribute *ahci_sdev_attrs[] = { |
| 374 | &dev_attr_sw_activity, |
Elias Oltmanns | 45fabbb | 2008-09-21 11:54:08 +0200 | [diff] [blame] | 375 | &dev_attr_unload_heads, |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 376 | NULL |
| 377 | }; |
| 378 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 379 | static struct scsi_host_template ahci_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 380 | ATA_NCQ_SHT(DRV_NAME), |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 381 | .can_queue = AHCI_MAX_CMDS - 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | .sg_tablesize = AHCI_MAX_SG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | .dma_boundary = AHCI_DMA_BOUNDARY, |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 384 | .shost_attrs = ahci_shost_attrs, |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 385 | .sdev_attrs = ahci_sdev_attrs, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 386 | }; |
| 387 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 388 | static struct ata_port_operations ahci_ops = { |
| 389 | .inherits = &sata_pmp_port_ops, |
| 390 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 391 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | .qc_prep = ahci_qc_prep, |
| 393 | .qc_issue = ahci_qc_issue, |
Tejun Heo | 4c9bf4e | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 394 | .qc_fill_rtf = ahci_qc_fill_rtf, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 396 | .freeze = ahci_freeze, |
| 397 | .thaw = ahci_thaw, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 398 | .softreset = ahci_softreset, |
| 399 | .hardreset = ahci_hardreset, |
| 400 | .postreset = ahci_postreset, |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 401 | .pmp_softreset = ahci_softreset, |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 402 | .error_handler = ahci_error_handler, |
| 403 | .post_internal_cmd = ahci_post_internal_cmd, |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 404 | .dev_config = ahci_dev_config, |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 405 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 406 | .scr_read = ahci_scr_read, |
| 407 | .scr_write = ahci_scr_write, |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 408 | .pmp_attach = ahci_pmp_attach, |
| 409 | .pmp_detach = ahci_pmp_detach, |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 410 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 411 | .enable_pm = ahci_enable_alpm, |
| 412 | .disable_pm = ahci_disable_alpm, |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 413 | .em_show = ahci_led_show, |
| 414 | .em_store = ahci_led_store, |
| 415 | .sw_activity_show = ahci_activity_show, |
| 416 | .sw_activity_store = ahci_activity_store, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 417 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 418 | .port_suspend = ahci_port_suspend, |
| 419 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 420 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 421 | .port_start = ahci_port_start, |
| 422 | .port_stop = ahci_port_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 423 | }; |
| 424 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 425 | static struct ata_port_operations ahci_vt8251_ops = { |
| 426 | .inherits = &ahci_ops, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 427 | .hardreset = ahci_vt8251_hardreset, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 428 | }; |
| 429 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 430 | static struct ata_port_operations ahci_p5wdh_ops = { |
| 431 | .inherits = &ahci_ops, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 432 | .hardreset = ahci_p5wdh_hardreset, |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 433 | }; |
| 434 | |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 435 | static struct ata_port_operations ahci_sb600_ops = { |
| 436 | .inherits = &ahci_ops, |
| 437 | .softreset = ahci_sb600_softreset, |
| 438 | .pmp_softreset = ahci_sb600_softreset, |
| 439 | }; |
| 440 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 441 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
| 442 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 443 | static const struct ata_port_info ahci_port_info[] = { |
Jeff Garzik | 4da646b | 2009-04-08 02:00:13 -0400 | [diff] [blame] | 444 | [board_ahci] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 445 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 446 | .flags = AHCI_FLAG_COMMON, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 447 | .pio_mask = ATA_PIO4, |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 448 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | .port_ops = &ahci_ops, |
| 450 | }, |
Jeff Garzik | 4da646b | 2009-04-08 02:00:13 -0400 | [diff] [blame] | 451 | [board_ahci_vt8251] = |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 452 | { |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 453 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 454 | .flags = AHCI_FLAG_COMMON, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 455 | .pio_mask = ATA_PIO4, |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 456 | .udma_mask = ATA_UDMA6, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 457 | .port_ops = &ahci_vt8251_ops, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 458 | }, |
Jeff Garzik | 4da646b | 2009-04-08 02:00:13 -0400 | [diff] [blame] | 459 | [board_ahci_ign_iferr] = |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 460 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 461 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
| 462 | .flags = AHCI_FLAG_COMMON, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 463 | .pio_mask = ATA_PIO4, |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 464 | .udma_mask = ATA_UDMA6, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 465 | .port_ops = &ahci_ops, |
| 466 | }, |
Jeff Garzik | 4da646b | 2009-04-08 02:00:13 -0400 | [diff] [blame] | 467 | [board_ahci_sb600] = |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 468 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 469 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
Tejun Heo | 2fcad9d | 2009-10-03 18:27:29 +0900 | [diff] [blame] | 470 | AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | |
| 471 | AHCI_HFLAG_32BIT_ONLY), |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 472 | .flags = AHCI_FLAG_COMMON, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 473 | .pio_mask = ATA_PIO4, |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 474 | .udma_mask = ATA_UDMA6, |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 475 | .port_ops = &ahci_sb600_ops, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 476 | }, |
Jeff Garzik | 4da646b | 2009-04-08 02:00:13 -0400 | [diff] [blame] | 477 | [board_ahci_mv] = |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 478 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 479 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
Tejun Heo | 1724846 | 2008-08-29 16:03:59 +0200 | [diff] [blame] | 480 | AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 481 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 482 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 483 | .pio_mask = ATA_PIO4, |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 484 | .udma_mask = ATA_UDMA6, |
| 485 | .port_ops = &ahci_ops, |
| 486 | }, |
Jeff Garzik | 4da646b | 2009-04-08 02:00:13 -0400 | [diff] [blame] | 487 | [board_ahci_sb700] = /* for SB700 and SB800 */ |
Shane Huang | e39fc8c | 2008-02-22 05:00:31 -0800 | [diff] [blame] | 488 | { |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 489 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
Shane Huang | e39fc8c | 2008-02-22 05:00:31 -0800 | [diff] [blame] | 490 | .flags = AHCI_FLAG_COMMON, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 491 | .pio_mask = ATA_PIO4, |
Shane Huang | e39fc8c | 2008-02-22 05:00:31 -0800 | [diff] [blame] | 492 | .udma_mask = ATA_UDMA6, |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 493 | .port_ops = &ahci_sb600_ops, |
Shane Huang | e39fc8c | 2008-02-22 05:00:31 -0800 | [diff] [blame] | 494 | }, |
Jeff Garzik | 4da646b | 2009-04-08 02:00:13 -0400 | [diff] [blame] | 495 | [board_ahci_mcp65] = |
Tejun Heo | e297d99 | 2008-06-10 00:13:04 +0900 | [diff] [blame] | 496 | { |
| 497 | AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), |
| 498 | .flags = AHCI_FLAG_COMMON, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 499 | .pio_mask = ATA_PIO4, |
Tejun Heo | e297d99 | 2008-06-10 00:13:04 +0900 | [diff] [blame] | 500 | .udma_mask = ATA_UDMA6, |
| 501 | .port_ops = &ahci_ops, |
| 502 | }, |
Jeff Garzik | 4da646b | 2009-04-08 02:00:13 -0400 | [diff] [blame] | 503 | [board_ahci_nopmp] = |
Tejun Heo | 9a3b103 | 2008-06-18 20:56:58 -0400 | [diff] [blame] | 504 | { |
| 505 | AHCI_HFLAGS (AHCI_HFLAG_NO_PMP), |
| 506 | .flags = AHCI_FLAG_COMMON, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 507 | .pio_mask = ATA_PIO4, |
Tejun Heo | 9a3b103 | 2008-06-18 20:56:58 -0400 | [diff] [blame] | 508 | .udma_mask = ATA_UDMA6, |
| 509 | .port_ops = &ahci_ops, |
| 510 | }, |
Tejun Heo | aa431dd | 2009-04-08 14:25:31 -0700 | [diff] [blame] | 511 | /* board_ahci_yesncq */ |
| 512 | { |
| 513 | AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), |
| 514 | .flags = AHCI_FLAG_COMMON, |
| 515 | .pio_mask = ATA_PIO4, |
| 516 | .udma_mask = ATA_UDMA6, |
| 517 | .port_ops = &ahci_ops, |
| 518 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 519 | }; |
| 520 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 521 | static const struct pci_device_id ahci_pci_tbl[] = { |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 522 | /* Intel */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 523 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
| 524 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ |
| 525 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ |
| 526 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ |
| 527 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ |
Tejun Heo | 82490c0 | 2007-01-23 15:13:39 +0900 | [diff] [blame] | 528 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 529 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
| 530 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ |
| 531 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ |
| 532 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 533 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
| 534 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ |
| 535 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
| 536 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ |
| 537 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ |
| 538 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ |
| 539 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ |
| 540 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ |
| 541 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ |
| 542 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ |
| 543 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ |
| 544 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ |
| 545 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ |
| 546 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ |
| 547 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ |
| 548 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ |
| 549 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ |
Jason Gaston | d4155e6 | 2007-09-20 17:35:00 -0400 | [diff] [blame] | 550 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
| 551 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ |
Jason Gaston | 16ad1ad | 2008-01-28 17:34:14 -0800 | [diff] [blame] | 552 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
Mark Goodwin | b2dde6a | 2009-06-26 10:44:11 -0500 | [diff] [blame] | 553 | { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ |
Jason Gaston | 16ad1ad | 2008-01-28 17:34:14 -0800 | [diff] [blame] | 554 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ |
David Milburn | c1f57d9 | 2009-07-22 15:15:56 -0500 | [diff] [blame] | 555 | { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ |
| 556 | { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ |
Seth Heasley | adcb530 | 2008-08-11 17:03:09 -0700 | [diff] [blame] | 557 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ |
Seth Heasley | 8e48b6b | 2008-08-27 16:47:22 -0700 | [diff] [blame] | 558 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ |
David Milburn | c1f57d9 | 2009-07-22 15:15:56 -0500 | [diff] [blame] | 559 | { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ |
Seth Heasley | adcb530 | 2008-08-11 17:03:09 -0700 | [diff] [blame] | 560 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ |
Seth Heasley | 8e48b6b | 2008-08-27 16:47:22 -0700 | [diff] [blame] | 561 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ |
David Milburn | c1f57d9 | 2009-07-22 15:15:56 -0500 | [diff] [blame] | 562 | { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 563 | |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 564 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
| 565 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 566 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 567 | |
| 568 | /* ATI */ |
Conke Hu | c65ec1c | 2007-04-11 18:23:14 +0800 | [diff] [blame] | 569 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
Shane Huang | e39fc8c | 2008-02-22 05:00:31 -0800 | [diff] [blame] | 570 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 571 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 572 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 573 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 574 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 575 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 576 | |
Shane Huang | e2dd90b | 2009-07-29 11:34:49 +0800 | [diff] [blame] | 577 | /* AMD */ |
| 578 | { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD SB900 */ |
| 579 | /* AMD is using RAID class only for ahci controllers */ |
| 580 | { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 581 | PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, |
| 582 | |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 583 | /* VIA */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 584 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
Tejun Heo | bf33554 | 2007-04-11 17:27:14 +0900 | [diff] [blame] | 585 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 586 | |
| 587 | /* NVIDIA */ |
Tejun Heo | e297d99 | 2008-06-10 00:13:04 +0900 | [diff] [blame] | 588 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
| 589 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ |
| 590 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ |
| 591 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ |
| 592 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ |
| 593 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ |
| 594 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ |
| 595 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ |
Tejun Heo | aa431dd | 2009-04-08 14:25:31 -0700 | [diff] [blame] | 596 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */ |
| 597 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */ |
| 598 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */ |
| 599 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */ |
| 600 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */ |
| 601 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */ |
| 602 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */ |
| 603 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */ |
| 604 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */ |
| 605 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */ |
| 606 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */ |
| 607 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */ |
| 608 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */ |
| 609 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */ |
| 610 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */ |
| 611 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */ |
| 612 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */ |
| 613 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */ |
| 614 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */ |
| 615 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */ |
| 616 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */ |
| 617 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */ |
| 618 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */ |
| 619 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */ |
Peer Chen | 0522b28 | 2007-06-07 18:05:12 +0800 | [diff] [blame] | 620 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ |
| 621 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ |
| 622 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ |
| 623 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ |
| 624 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ |
| 625 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ |
| 626 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ |
| 627 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ |
| 628 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ |
| 629 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ |
| 630 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ |
| 631 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ |
peerchen | 6ba8695 | 2007-12-03 22:20:37 +0800 | [diff] [blame] | 632 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
| 633 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ |
| 634 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ |
| 635 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ |
Peer Chen | 7100819 | 2007-09-24 10:16:25 +0800 | [diff] [blame] | 636 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
| 637 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ |
| 638 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ |
| 639 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ |
| 640 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ |
| 641 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ |
| 642 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ |
| 643 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ |
peerchen | 7adbe46 | 2009-02-27 16:58:41 +0800 | [diff] [blame] | 644 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */ |
| 645 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */ |
| 646 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */ |
| 647 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */ |
| 648 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */ |
| 649 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */ |
| 650 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */ |
| 651 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */ |
| 652 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */ |
| 653 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */ |
| 654 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */ |
| 655 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 656 | |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 657 | /* SiS */ |
Tejun Heo | 20e2de4 | 2008-08-01 12:51:43 +0900 | [diff] [blame] | 658 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
| 659 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ |
| 660 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 661 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 662 | /* Marvell */ |
| 663 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ |
Jose Alberto Reguero | c40e7cb | 2008-03-13 23:22:24 +0100 | [diff] [blame] | 664 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 665 | |
Mark Nelson | c77a036 | 2008-10-23 14:08:16 +1100 | [diff] [blame] | 666 | /* Promise */ |
| 667 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ |
| 668 | |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 669 | /* Generic, PCI class code for AHCI */ |
| 670 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 671 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 672 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 673 | { } /* terminate list */ |
| 674 | }; |
| 675 | |
| 676 | |
| 677 | static struct pci_driver ahci_pci_driver = { |
| 678 | .name = DRV_NAME, |
| 679 | .id_table = ahci_pci_tbl, |
| 680 | .probe = ahci_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 681 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 682 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 683 | .suspend = ahci_pci_device_suspend, |
| 684 | .resume = ahci_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 685 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 686 | }; |
| 687 | |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 688 | static int ahci_em_messages = 1; |
| 689 | module_param(ahci_em_messages, int, 0444); |
| 690 | /* add other LED protocol types when they become supported */ |
| 691 | MODULE_PARM_DESC(ahci_em_messages, |
| 692 | "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | |
Alan Cox | 5b66c82 | 2008-09-03 14:48:34 +0100 | [diff] [blame] | 694 | #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) |
| 695 | static int marvell_enable; |
| 696 | #else |
| 697 | static int marvell_enable = 1; |
| 698 | #endif |
| 699 | module_param(marvell_enable, int, 0644); |
| 700 | MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); |
| 701 | |
| 702 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 703 | static inline int ahci_nr_ports(u32 cap) |
| 704 | { |
| 705 | return (cap & 0x1f) + 1; |
| 706 | } |
| 707 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 708 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
| 709 | unsigned int port_no) |
| 710 | { |
| 711 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 712 | |
| 713 | return mmio + 0x100 + (port_no * 0x80); |
| 714 | } |
| 715 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 716 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 717 | { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 718 | return __ahci_port_base(ap->host, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 719 | } |
| 720 | |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 721 | static void ahci_enable_ahci(void __iomem *mmio) |
| 722 | { |
Tejun Heo | 15fe982 | 2008-04-23 20:52:58 +0900 | [diff] [blame] | 723 | int i; |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 724 | u32 tmp; |
| 725 | |
| 726 | /* turn on AHCI_EN */ |
| 727 | tmp = readl(mmio + HOST_CTL); |
Tejun Heo | 15fe982 | 2008-04-23 20:52:58 +0900 | [diff] [blame] | 728 | if (tmp & HOST_AHCI_EN) |
| 729 | return; |
| 730 | |
| 731 | /* Some controllers need AHCI_EN to be written multiple times. |
| 732 | * Try a few times before giving up. |
| 733 | */ |
| 734 | for (i = 0; i < 5; i++) { |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 735 | tmp |= HOST_AHCI_EN; |
| 736 | writel(tmp, mmio + HOST_CTL); |
| 737 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ |
Tejun Heo | 15fe982 | 2008-04-23 20:52:58 +0900 | [diff] [blame] | 738 | if (tmp & HOST_AHCI_EN) |
| 739 | return; |
| 740 | msleep(10); |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 741 | } |
Tejun Heo | 15fe982 | 2008-04-23 20:52:58 +0900 | [diff] [blame] | 742 | |
| 743 | WARN_ON(1); |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 744 | } |
| 745 | |
Matthew Garrett | 77cdec1 | 2009-07-17 19:13:47 +0100 | [diff] [blame] | 746 | static ssize_t ahci_show_host_caps(struct device *dev, |
| 747 | struct device_attribute *attr, char *buf) |
| 748 | { |
| 749 | struct Scsi_Host *shost = class_to_shost(dev); |
| 750 | struct ata_port *ap = ata_shost_to_port(shost); |
| 751 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 752 | |
| 753 | return sprintf(buf, "%x\n", hpriv->cap); |
| 754 | } |
| 755 | |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 756 | static ssize_t ahci_show_host_cap2(struct device *dev, |
| 757 | struct device_attribute *attr, char *buf) |
| 758 | { |
| 759 | struct Scsi_Host *shost = class_to_shost(dev); |
| 760 | struct ata_port *ap = ata_shost_to_port(shost); |
| 761 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 762 | |
| 763 | return sprintf(buf, "%x\n", hpriv->cap2); |
| 764 | } |
| 765 | |
Matthew Garrett | 77cdec1 | 2009-07-17 19:13:47 +0100 | [diff] [blame] | 766 | static ssize_t ahci_show_host_version(struct device *dev, |
| 767 | struct device_attribute *attr, char *buf) |
| 768 | { |
| 769 | struct Scsi_Host *shost = class_to_shost(dev); |
| 770 | struct ata_port *ap = ata_shost_to_port(shost); |
| 771 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
| 772 | |
| 773 | return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); |
| 774 | } |
| 775 | |
| 776 | static ssize_t ahci_show_port_cmd(struct device *dev, |
| 777 | struct device_attribute *attr, char *buf) |
| 778 | { |
| 779 | struct Scsi_Host *shost = class_to_shost(dev); |
| 780 | struct ata_port *ap = ata_shost_to_port(shost); |
| 781 | void __iomem *port_mmio = ahci_port_base(ap); |
| 782 | |
| 783 | return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); |
| 784 | } |
| 785 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 786 | /** |
| 787 | * ahci_save_initial_config - Save and fixup initial config values |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 788 | * @pdev: target PCI device |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 789 | * @hpriv: host private area to store config values |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 790 | * |
| 791 | * Some registers containing configuration info might be setup by |
| 792 | * BIOS and might be cleared on reset. This function saves the |
| 793 | * initial values of those registers into @hpriv such that they |
| 794 | * can be restored after controller reset. |
| 795 | * |
| 796 | * If inconsistent, config values are fixed up by this function. |
| 797 | * |
| 798 | * LOCKING: |
| 799 | * None. |
| 800 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 801 | static void ahci_save_initial_config(struct pci_dev *pdev, |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 802 | struct ahci_host_priv *hpriv) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 803 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 804 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 805 | u32 cap, cap2, vers, port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 806 | int i; |
Jose Alberto Reguero | c40e7cb | 2008-03-13 23:22:24 +0100 | [diff] [blame] | 807 | int mv; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 808 | |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 809 | /* make sure AHCI mode is enabled before accessing CAP */ |
| 810 | ahci_enable_ahci(mmio); |
| 811 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 812 | /* Values prefixed with saved_ are written back to host after |
| 813 | * reset. Values without are used for driver operation. |
| 814 | */ |
| 815 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); |
| 816 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); |
| 817 | |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 818 | /* CAP2 register is only defined for AHCI 1.2 and later */ |
| 819 | vers = readl(mmio + HOST_VERSION); |
| 820 | if ((vers >> 16) > 1 || |
| 821 | ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) |
| 822 | hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); |
| 823 | else |
| 824 | hpriv->saved_cap2 = cap2 = 0; |
| 825 | |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 826 | /* some chips have errata preventing 64bit use */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 827 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 828 | dev_printk(KERN_INFO, &pdev->dev, |
| 829 | "controller can't do 64bit DMA, forcing 32bit\n"); |
| 830 | cap &= ~HOST_CAP_64; |
| 831 | } |
| 832 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 833 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 834 | dev_printk(KERN_INFO, &pdev->dev, |
| 835 | "controller can't do NCQ, turning off CAP_NCQ\n"); |
| 836 | cap &= ~HOST_CAP_NCQ; |
| 837 | } |
| 838 | |
Tejun Heo | e297d99 | 2008-06-10 00:13:04 +0900 | [diff] [blame] | 839 | if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { |
| 840 | dev_printk(KERN_INFO, &pdev->dev, |
| 841 | "controller can do NCQ, turning on CAP_NCQ\n"); |
| 842 | cap |= HOST_CAP_NCQ; |
| 843 | } |
| 844 | |
Roel Kluin | 258cd84 | 2008-03-09 21:42:40 +0100 | [diff] [blame] | 845 | if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 846 | dev_printk(KERN_INFO, &pdev->dev, |
| 847 | "controller can't do PMP, turning off CAP_PMP\n"); |
| 848 | cap &= ~HOST_CAP_PMP; |
| 849 | } |
| 850 | |
Tejun Heo | d799e08 | 2008-06-17 12:46:30 +0900 | [diff] [blame] | 851 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 && |
| 852 | port_map != 1) { |
| 853 | dev_printk(KERN_INFO, &pdev->dev, |
| 854 | "JMB361 has only one port, port_map 0x%x -> 0x%x\n", |
| 855 | port_map, 1); |
| 856 | port_map = 1; |
| 857 | } |
| 858 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 859 | /* |
| 860 | * Temporary Marvell 6145 hack: PATA port presence |
| 861 | * is asserted through the standard AHCI port |
| 862 | * presence register, as bit 4 (counting from 0) |
| 863 | */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 864 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
Jose Alberto Reguero | c40e7cb | 2008-03-13 23:22:24 +0100 | [diff] [blame] | 865 | if (pdev->device == 0x6121) |
| 866 | mv = 0x3; |
| 867 | else |
| 868 | mv = 0xf; |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 869 | dev_printk(KERN_ERR, &pdev->dev, |
| 870 | "MV_AHCI HACK: port_map %x -> %x\n", |
Jose Alberto Reguero | c40e7cb | 2008-03-13 23:22:24 +0100 | [diff] [blame] | 871 | port_map, |
| 872 | port_map & mv); |
Alan Cox | 5b66c82 | 2008-09-03 14:48:34 +0100 | [diff] [blame] | 873 | dev_printk(KERN_ERR, &pdev->dev, |
| 874 | "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 875 | |
Jose Alberto Reguero | c40e7cb | 2008-03-13 23:22:24 +0100 | [diff] [blame] | 876 | port_map &= mv; |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 877 | } |
| 878 | |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 879 | /* cross check port_map and cap.n_ports */ |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 880 | if (port_map) { |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 881 | int map_ports = 0; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 882 | |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 883 | for (i = 0; i < AHCI_MAX_PORTS; i++) |
| 884 | if (port_map & (1 << i)) |
| 885 | map_ports++; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 886 | |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 887 | /* If PI has more ports than n_ports, whine, clear |
| 888 | * port_map and let it be generated from n_ports. |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 889 | */ |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 890 | if (map_ports > ahci_nr_ports(cap)) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 891 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 892 | "implemented port map (0x%x) contains more " |
| 893 | "ports than nr_ports (%u), using nr_ports\n", |
| 894 | port_map, ahci_nr_ports(cap)); |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 895 | port_map = 0; |
| 896 | } |
| 897 | } |
| 898 | |
| 899 | /* fabricate port_map from cap.nr_ports */ |
| 900 | if (!port_map) { |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 901 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 902 | dev_printk(KERN_WARNING, &pdev->dev, |
| 903 | "forcing PORTS_IMPL to 0x%x\n", port_map); |
| 904 | |
| 905 | /* write the fixed up value to the PI register */ |
| 906 | hpriv->saved_port_map = port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 907 | } |
| 908 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 909 | /* record values to use during operation */ |
| 910 | hpriv->cap = cap; |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 911 | hpriv->cap2 = cap2; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 912 | hpriv->port_map = port_map; |
| 913 | } |
| 914 | |
| 915 | /** |
| 916 | * ahci_restore_initial_config - Restore initial config |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 917 | * @host: target ATA host |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 918 | * |
| 919 | * Restore initial config stored by ahci_save_initial_config(). |
| 920 | * |
| 921 | * LOCKING: |
| 922 | * None. |
| 923 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 924 | static void ahci_restore_initial_config(struct ata_host *host) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 925 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 926 | struct ahci_host_priv *hpriv = host->private_data; |
| 927 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 928 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 929 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 930 | if (hpriv->saved_cap2) |
| 931 | writel(hpriv->saved_cap2, mmio + HOST_CAP2); |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 932 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); |
| 933 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
| 934 | } |
| 935 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 936 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | { |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 938 | static const int offset[] = { |
| 939 | [SCR_STATUS] = PORT_SCR_STAT, |
| 940 | [SCR_CONTROL] = PORT_SCR_CTL, |
| 941 | [SCR_ERROR] = PORT_SCR_ERR, |
| 942 | [SCR_ACTIVE] = PORT_SCR_ACT, |
| 943 | [SCR_NOTIFICATION] = PORT_SCR_NTF, |
| 944 | }; |
| 945 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 946 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 947 | if (sc_reg < ARRAY_SIZE(offset) && |
| 948 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) |
| 949 | return offset[sc_reg]; |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 950 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 951 | } |
| 952 | |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 953 | static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 954 | { |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 955 | void __iomem *port_mmio = ahci_port_base(link->ap); |
| 956 | int offset = ahci_scr_offset(link->ap, sc_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 958 | if (offset) { |
| 959 | *val = readl(port_mmio + offset); |
| 960 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | } |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 962 | return -EINVAL; |
| 963 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 964 | |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 965 | static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 966 | { |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 967 | void __iomem *port_mmio = ahci_port_base(link->ap); |
| 968 | int offset = ahci_scr_offset(link->ap, sc_reg); |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 969 | |
| 970 | if (offset) { |
| 971 | writel(val, port_mmio + offset); |
| 972 | return 0; |
| 973 | } |
| 974 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | } |
| 976 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 977 | static void ahci_start_engine(struct ata_port *ap) |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 978 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 979 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 980 | u32 tmp; |
| 981 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 982 | /* start DMA */ |
Tejun Heo | 9f59205 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 983 | tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 984 | tmp |= PORT_CMD_START; |
| 985 | writel(tmp, port_mmio + PORT_CMD); |
| 986 | readl(port_mmio + PORT_CMD); /* flush */ |
| 987 | } |
| 988 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 989 | static int ahci_stop_engine(struct ata_port *ap) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 990 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 991 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 992 | u32 tmp; |
| 993 | |
| 994 | tmp = readl(port_mmio + PORT_CMD); |
| 995 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 996 | /* check if the HBA is idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 997 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
| 998 | return 0; |
| 999 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1000 | /* setting HBA to idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1001 | tmp &= ~PORT_CMD_START; |
| 1002 | writel(tmp, port_mmio + PORT_CMD); |
| 1003 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1004 | /* wait for engine to stop. This could be as long as 500 msec */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1005 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 1006 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1007 | if (tmp & PORT_CMD_LIST_ON) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1008 | return -EIO; |
| 1009 | |
| 1010 | return 0; |
| 1011 | } |
| 1012 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1013 | static void ahci_start_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1014 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1015 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1016 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 1017 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1018 | u32 tmp; |
| 1019 | |
| 1020 | /* set FIS registers */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1021 | if (hpriv->cap & HOST_CAP_64) |
| 1022 | writel((pp->cmd_slot_dma >> 16) >> 16, |
| 1023 | port_mmio + PORT_LST_ADDR_HI); |
| 1024 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1025 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1026 | if (hpriv->cap & HOST_CAP_64) |
| 1027 | writel((pp->rx_fis_dma >> 16) >> 16, |
| 1028 | port_mmio + PORT_FIS_ADDR_HI); |
| 1029 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1030 | |
| 1031 | /* enable FIS reception */ |
| 1032 | tmp = readl(port_mmio + PORT_CMD); |
| 1033 | tmp |= PORT_CMD_FIS_RX; |
| 1034 | writel(tmp, port_mmio + PORT_CMD); |
| 1035 | |
| 1036 | /* flush */ |
| 1037 | readl(port_mmio + PORT_CMD); |
| 1038 | } |
| 1039 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1040 | static int ahci_stop_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1041 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1042 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1043 | u32 tmp; |
| 1044 | |
| 1045 | /* disable FIS reception */ |
| 1046 | tmp = readl(port_mmio + PORT_CMD); |
| 1047 | tmp &= ~PORT_CMD_FIS_RX; |
| 1048 | writel(tmp, port_mmio + PORT_CMD); |
| 1049 | |
| 1050 | /* wait for completion, spec says 500ms, give it 1000 */ |
| 1051 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, |
| 1052 | PORT_CMD_FIS_ON, 10, 1000); |
| 1053 | if (tmp & PORT_CMD_FIS_ON) |
| 1054 | return -EBUSY; |
| 1055 | |
| 1056 | return 0; |
| 1057 | } |
| 1058 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1059 | static void ahci_power_up(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1060 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1061 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 1062 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1063 | u32 cmd; |
| 1064 | |
| 1065 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
| 1066 | |
| 1067 | /* spin up device */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1068 | if (hpriv->cap & HOST_CAP_SSS) { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1069 | cmd |= PORT_CMD_SPIN_UP; |
| 1070 | writel(cmd, port_mmio + PORT_CMD); |
| 1071 | } |
| 1072 | |
| 1073 | /* wake up link */ |
| 1074 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); |
| 1075 | } |
| 1076 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 1077 | static void ahci_disable_alpm(struct ata_port *ap) |
| 1078 | { |
| 1079 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 1080 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1081 | u32 cmd; |
| 1082 | struct ahci_port_priv *pp = ap->private_data; |
| 1083 | |
| 1084 | /* IPM bits should be disabled by libata-core */ |
| 1085 | /* get the existing command bits */ |
| 1086 | cmd = readl(port_mmio + PORT_CMD); |
| 1087 | |
| 1088 | /* disable ALPM and ASP */ |
| 1089 | cmd &= ~PORT_CMD_ASP; |
| 1090 | cmd &= ~PORT_CMD_ALPE; |
| 1091 | |
| 1092 | /* force the interface back to active */ |
| 1093 | cmd |= PORT_CMD_ICC_ACTIVE; |
| 1094 | |
| 1095 | /* write out new cmd value */ |
| 1096 | writel(cmd, port_mmio + PORT_CMD); |
| 1097 | cmd = readl(port_mmio + PORT_CMD); |
| 1098 | |
| 1099 | /* wait 10ms to be sure we've come out of any low power state */ |
| 1100 | msleep(10); |
| 1101 | |
| 1102 | /* clear out any PhyRdy stuff from interrupt status */ |
| 1103 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); |
| 1104 | |
| 1105 | /* go ahead and clean out PhyRdy Change from Serror too */ |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 1106 | ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 1107 | |
| 1108 | /* |
| 1109 | * Clear flag to indicate that we should ignore all PhyRdy |
| 1110 | * state changes |
| 1111 | */ |
| 1112 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; |
| 1113 | |
| 1114 | /* |
| 1115 | * Enable interrupts on Phy Ready. |
| 1116 | */ |
| 1117 | pp->intr_mask |= PORT_IRQ_PHYRDY; |
| 1118 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
| 1119 | |
| 1120 | /* |
| 1121 | * don't change the link pm policy - we can be called |
| 1122 | * just to turn of link pm temporarily |
| 1123 | */ |
| 1124 | } |
| 1125 | |
| 1126 | static int ahci_enable_alpm(struct ata_port *ap, |
| 1127 | enum link_pm policy) |
| 1128 | { |
| 1129 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 1130 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1131 | u32 cmd; |
| 1132 | struct ahci_port_priv *pp = ap->private_data; |
| 1133 | u32 asp; |
| 1134 | |
| 1135 | /* Make sure the host is capable of link power management */ |
| 1136 | if (!(hpriv->cap & HOST_CAP_ALPM)) |
| 1137 | return -EINVAL; |
| 1138 | |
| 1139 | switch (policy) { |
| 1140 | case MAX_PERFORMANCE: |
| 1141 | case NOT_AVAILABLE: |
| 1142 | /* |
| 1143 | * if we came here with NOT_AVAILABLE, |
| 1144 | * it just means this is the first time we |
| 1145 | * have tried to enable - default to max performance, |
| 1146 | * and let the user go to lower power modes on request. |
| 1147 | */ |
| 1148 | ahci_disable_alpm(ap); |
| 1149 | return 0; |
| 1150 | case MIN_POWER: |
| 1151 | /* configure HBA to enter SLUMBER */ |
| 1152 | asp = PORT_CMD_ASP; |
| 1153 | break; |
| 1154 | case MEDIUM_POWER: |
| 1155 | /* configure HBA to enter PARTIAL */ |
| 1156 | asp = 0; |
| 1157 | break; |
| 1158 | default: |
| 1159 | return -EINVAL; |
| 1160 | } |
| 1161 | |
| 1162 | /* |
| 1163 | * Disable interrupts on Phy Ready. This keeps us from |
| 1164 | * getting woken up due to spurious phy ready interrupts |
| 1165 | * TBD - Hot plug should be done via polling now, is |
| 1166 | * that even supported? |
| 1167 | */ |
| 1168 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; |
| 1169 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
| 1170 | |
| 1171 | /* |
| 1172 | * Set a flag to indicate that we should ignore all PhyRdy |
| 1173 | * state changes since these can happen now whenever we |
| 1174 | * change link state |
| 1175 | */ |
| 1176 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; |
| 1177 | |
| 1178 | /* get the existing command bits */ |
| 1179 | cmd = readl(port_mmio + PORT_CMD); |
| 1180 | |
| 1181 | /* |
| 1182 | * Set ASP based on Policy |
| 1183 | */ |
| 1184 | cmd |= asp; |
| 1185 | |
| 1186 | /* |
| 1187 | * Setting this bit will instruct the HBA to aggressively |
| 1188 | * enter a lower power link state when it's appropriate and |
| 1189 | * based on the value set above for ASP |
| 1190 | */ |
| 1191 | cmd |= PORT_CMD_ALPE; |
| 1192 | |
| 1193 | /* write out new cmd value */ |
| 1194 | writel(cmd, port_mmio + PORT_CMD); |
| 1195 | cmd = readl(port_mmio + PORT_CMD); |
| 1196 | |
| 1197 | /* IPM bits should be set by libata-core */ |
| 1198 | return 0; |
| 1199 | } |
| 1200 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1201 | #ifdef CONFIG_PM |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1202 | static void ahci_power_down(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1203 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1204 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 1205 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1206 | u32 cmd, scontrol; |
| 1207 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1208 | if (!(hpriv->cap & HOST_CAP_SSS)) |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 1209 | return; |
| 1210 | |
| 1211 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
| 1212 | scontrol = readl(port_mmio + PORT_SCR_CTL); |
| 1213 | scontrol &= ~0xf; |
| 1214 | writel(scontrol, port_mmio + PORT_SCR_CTL); |
| 1215 | |
| 1216 | /* then set PxCMD.SUD to 0 */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1217 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 1218 | cmd &= ~PORT_CMD_SPIN_UP; |
| 1219 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1220 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1221 | #endif |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1222 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1223 | static void ahci_start_port(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1224 | { |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1225 | struct ahci_port_priv *pp = ap->private_data; |
| 1226 | struct ata_link *link; |
| 1227 | struct ahci_em_priv *emp; |
David Milburn | 4c1e9aa | 2009-04-03 15:36:41 -0500 | [diff] [blame] | 1228 | ssize_t rc; |
| 1229 | int i; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1230 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1231 | /* enable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1232 | ahci_start_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1233 | |
| 1234 | /* enable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1235 | ahci_start_engine(ap); |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1236 | |
| 1237 | /* turn on LEDs */ |
| 1238 | if (ap->flags & ATA_FLAG_EM) { |
Tejun Heo | 1eca436 | 2008-11-03 20:03:17 +0900 | [diff] [blame] | 1239 | ata_for_each_link(link, ap, EDGE) { |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1240 | emp = &pp->em_priv[link->pmp]; |
David Milburn | 4c1e9aa | 2009-04-03 15:36:41 -0500 | [diff] [blame] | 1241 | |
| 1242 | /* EM Transmit bit maybe busy during init */ |
Tejun Heo | d50ce07 | 2009-05-12 10:57:41 +0900 | [diff] [blame] | 1243 | for (i = 0; i < EM_MAX_RETRY; i++) { |
David Milburn | 4c1e9aa | 2009-04-03 15:36:41 -0500 | [diff] [blame] | 1244 | rc = ahci_transmit_led_message(ap, |
| 1245 | emp->led_state, |
| 1246 | 4); |
| 1247 | if (rc == -EBUSY) |
Tejun Heo | d50ce07 | 2009-05-12 10:57:41 +0900 | [diff] [blame] | 1248 | msleep(1); |
David Milburn | 4c1e9aa | 2009-04-03 15:36:41 -0500 | [diff] [blame] | 1249 | else |
| 1250 | break; |
| 1251 | } |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1252 | } |
| 1253 | } |
| 1254 | |
| 1255 | if (ap->flags & ATA_FLAG_SW_ACTIVITY) |
Tejun Heo | 1eca436 | 2008-11-03 20:03:17 +0900 | [diff] [blame] | 1256 | ata_for_each_link(link, ap, EDGE) |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1257 | ahci_init_sw_activity(link); |
| 1258 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1259 | } |
| 1260 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1261 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1262 | { |
| 1263 | int rc; |
| 1264 | |
| 1265 | /* disable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1266 | rc = ahci_stop_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1267 | if (rc) { |
| 1268 | *emsg = "failed to stop engine"; |
| 1269 | return rc; |
| 1270 | } |
| 1271 | |
| 1272 | /* disable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1273 | rc = ahci_stop_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1274 | if (rc) { |
| 1275 | *emsg = "failed stop FIS RX"; |
| 1276 | return rc; |
| 1277 | } |
| 1278 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1279 | return 0; |
| 1280 | } |
| 1281 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1282 | static int ahci_reset_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1283 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1284 | struct pci_dev *pdev = to_pci_dev(host->dev); |
Tejun Heo | 49f2909 | 2007-11-19 16:03:44 +0900 | [diff] [blame] | 1285 | struct ahci_host_priv *hpriv = host->private_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1286 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 1287 | u32 tmp; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1288 | |
Jeff Garzik | 3cc3eb1 | 2007-09-26 00:02:41 -0400 | [diff] [blame] | 1289 | /* we must be in AHCI mode, before using anything |
| 1290 | * AHCI-specific, such as HOST_RESET. |
| 1291 | */ |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 1292 | ahci_enable_ahci(mmio); |
Jeff Garzik | 3cc3eb1 | 2007-09-26 00:02:41 -0400 | [diff] [blame] | 1293 | |
| 1294 | /* global controller reset */ |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame] | 1295 | if (!ahci_skip_host_reset) { |
| 1296 | tmp = readl(mmio + HOST_CTL); |
| 1297 | if ((tmp & HOST_RESET) == 0) { |
| 1298 | writel(tmp | HOST_RESET, mmio + HOST_CTL); |
| 1299 | readl(mmio + HOST_CTL); /* flush */ |
| 1300 | } |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1301 | |
Zhang Rui | 24920c8 | 2008-07-04 13:32:17 +0800 | [diff] [blame] | 1302 | /* |
| 1303 | * to perform host reset, OS should set HOST_RESET |
| 1304 | * and poll until this bit is read to be "0". |
| 1305 | * reset must complete within 1 second, or |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame] | 1306 | * the hardware should be considered fried. |
| 1307 | */ |
Zhang Rui | 24920c8 | 2008-07-04 13:32:17 +0800 | [diff] [blame] | 1308 | tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, |
| 1309 | HOST_RESET, 10, 1000); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1310 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame] | 1311 | if (tmp & HOST_RESET) { |
| 1312 | dev_printk(KERN_ERR, host->dev, |
| 1313 | "controller reset failed (0x%x)\n", tmp); |
| 1314 | return -EIO; |
| 1315 | } |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1316 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame] | 1317 | /* turn on AHCI mode */ |
| 1318 | ahci_enable_ahci(mmio); |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 1319 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame] | 1320 | /* Some registers might be cleared on reset. Restore |
| 1321 | * initial values. |
| 1322 | */ |
| 1323 | ahci_restore_initial_config(host); |
| 1324 | } else |
| 1325 | dev_printk(KERN_INFO, host->dev, |
| 1326 | "skipping global host reset\n"); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1327 | |
| 1328 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 1329 | u16 tmp16; |
| 1330 | |
| 1331 | /* configure PCS */ |
| 1332 | pci_read_config_word(pdev, 0x92, &tmp16); |
Tejun Heo | 49f2909 | 2007-11-19 16:03:44 +0900 | [diff] [blame] | 1333 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
| 1334 | tmp16 |= hpriv->port_map; |
| 1335 | pci_write_config_word(pdev, 0x92, tmp16); |
| 1336 | } |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1337 | } |
| 1338 | |
| 1339 | return 0; |
| 1340 | } |
| 1341 | |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1342 | static void ahci_sw_activity(struct ata_link *link) |
| 1343 | { |
| 1344 | struct ata_port *ap = link->ap; |
| 1345 | struct ahci_port_priv *pp = ap->private_data; |
| 1346 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; |
| 1347 | |
| 1348 | if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) |
| 1349 | return; |
| 1350 | |
| 1351 | emp->activity++; |
| 1352 | if (!timer_pending(&emp->timer)) |
| 1353 | mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); |
| 1354 | } |
| 1355 | |
| 1356 | static void ahci_sw_activity_blink(unsigned long arg) |
| 1357 | { |
| 1358 | struct ata_link *link = (struct ata_link *)arg; |
| 1359 | struct ata_port *ap = link->ap; |
| 1360 | struct ahci_port_priv *pp = ap->private_data; |
| 1361 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; |
| 1362 | unsigned long led_message = emp->led_state; |
| 1363 | u32 activity_led_state; |
David Milburn | eb40963 | 2008-10-16 09:26:19 -0500 | [diff] [blame] | 1364 | unsigned long flags; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1365 | |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1366 | led_message &= EM_MSG_LED_VALUE; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1367 | led_message |= ap->port_no | (link->pmp << 8); |
| 1368 | |
| 1369 | /* check to see if we've had activity. If so, |
| 1370 | * toggle state of LED and reset timer. If not, |
| 1371 | * turn LED to desired idle state. |
| 1372 | */ |
David Milburn | eb40963 | 2008-10-16 09:26:19 -0500 | [diff] [blame] | 1373 | spin_lock_irqsave(ap->lock, flags); |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1374 | if (emp->saved_activity != emp->activity) { |
| 1375 | emp->saved_activity = emp->activity; |
| 1376 | /* get the current LED state */ |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1377 | activity_led_state = led_message & EM_MSG_LED_VALUE_ON; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1378 | |
| 1379 | if (activity_led_state) |
| 1380 | activity_led_state = 0; |
| 1381 | else |
| 1382 | activity_led_state = 1; |
| 1383 | |
| 1384 | /* clear old state */ |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1385 | led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1386 | |
| 1387 | /* toggle state */ |
| 1388 | led_message |= (activity_led_state << 16); |
| 1389 | mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); |
| 1390 | } else { |
| 1391 | /* switch to idle */ |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1392 | led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1393 | if (emp->blink_policy == BLINK_OFF) |
| 1394 | led_message |= (1 << 16); |
| 1395 | } |
David Milburn | eb40963 | 2008-10-16 09:26:19 -0500 | [diff] [blame] | 1396 | spin_unlock_irqrestore(ap->lock, flags); |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1397 | ahci_transmit_led_message(ap, led_message, 4); |
| 1398 | } |
| 1399 | |
| 1400 | static void ahci_init_sw_activity(struct ata_link *link) |
| 1401 | { |
| 1402 | struct ata_port *ap = link->ap; |
| 1403 | struct ahci_port_priv *pp = ap->private_data; |
| 1404 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; |
| 1405 | |
| 1406 | /* init activity stats, setup timer */ |
| 1407 | emp->saved_activity = emp->activity = 0; |
| 1408 | setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); |
| 1409 | |
| 1410 | /* check our blink policy and set flag for link if it's enabled */ |
| 1411 | if (emp->blink_policy) |
| 1412 | link->flags |= ATA_LFLAG_SW_ACTIVITY; |
| 1413 | } |
| 1414 | |
| 1415 | static int ahci_reset_em(struct ata_host *host) |
| 1416 | { |
| 1417 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 1418 | u32 em_ctl; |
| 1419 | |
| 1420 | em_ctl = readl(mmio + HOST_EM_CTL); |
| 1421 | if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) |
| 1422 | return -EINVAL; |
| 1423 | |
| 1424 | writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); |
| 1425 | return 0; |
| 1426 | } |
| 1427 | |
| 1428 | static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, |
| 1429 | ssize_t size) |
| 1430 | { |
| 1431 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 1432 | struct ahci_port_priv *pp = ap->private_data; |
| 1433 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
| 1434 | u32 em_ctl; |
| 1435 | u32 message[] = {0, 0}; |
Linus Torvalds | 93082f0 | 2008-07-25 10:56:36 -0700 | [diff] [blame] | 1436 | unsigned long flags; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1437 | int pmp; |
| 1438 | struct ahci_em_priv *emp; |
| 1439 | |
| 1440 | /* get the slot number from the message */ |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1441 | pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; |
Tejun Heo | d50ce07 | 2009-05-12 10:57:41 +0900 | [diff] [blame] | 1442 | if (pmp < EM_MAX_SLOTS) |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1443 | emp = &pp->em_priv[pmp]; |
| 1444 | else |
| 1445 | return -EINVAL; |
| 1446 | |
| 1447 | spin_lock_irqsave(ap->lock, flags); |
| 1448 | |
| 1449 | /* |
| 1450 | * if we are still busy transmitting a previous message, |
| 1451 | * do not allow |
| 1452 | */ |
| 1453 | em_ctl = readl(mmio + HOST_EM_CTL); |
| 1454 | if (em_ctl & EM_CTL_TM) { |
| 1455 | spin_unlock_irqrestore(ap->lock, flags); |
David Milburn | 4c1e9aa | 2009-04-03 15:36:41 -0500 | [diff] [blame] | 1456 | return -EBUSY; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1457 | } |
| 1458 | |
| 1459 | /* |
| 1460 | * create message header - this is all zero except for |
| 1461 | * the message size, which is 4 bytes. |
| 1462 | */ |
| 1463 | message[0] |= (4 << 8); |
| 1464 | |
| 1465 | /* ignore 0:4 of byte zero, fill in port info yourself */ |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1466 | message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1467 | |
| 1468 | /* write message to EM_LOC */ |
| 1469 | writel(message[0], mmio + hpriv->em_loc); |
| 1470 | writel(message[1], mmio + hpriv->em_loc+4); |
| 1471 | |
| 1472 | /* save off new led state for port/slot */ |
David Milburn | 208f2a8 | 2009-03-20 14:14:23 -0500 | [diff] [blame] | 1473 | emp->led_state = state; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1474 | |
| 1475 | /* |
| 1476 | * tell hardware to transmit the message |
| 1477 | */ |
| 1478 | writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); |
| 1479 | |
| 1480 | spin_unlock_irqrestore(ap->lock, flags); |
| 1481 | return size; |
| 1482 | } |
| 1483 | |
| 1484 | static ssize_t ahci_led_show(struct ata_port *ap, char *buf) |
| 1485 | { |
| 1486 | struct ahci_port_priv *pp = ap->private_data; |
| 1487 | struct ata_link *link; |
| 1488 | struct ahci_em_priv *emp; |
| 1489 | int rc = 0; |
| 1490 | |
Tejun Heo | 1eca436 | 2008-11-03 20:03:17 +0900 | [diff] [blame] | 1491 | ata_for_each_link(link, ap, EDGE) { |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1492 | emp = &pp->em_priv[link->pmp]; |
| 1493 | rc += sprintf(buf, "%lx\n", emp->led_state); |
| 1494 | } |
| 1495 | return rc; |
| 1496 | } |
| 1497 | |
| 1498 | static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, |
| 1499 | size_t size) |
| 1500 | { |
| 1501 | int state; |
| 1502 | int pmp; |
| 1503 | struct ahci_port_priv *pp = ap->private_data; |
| 1504 | struct ahci_em_priv *emp; |
| 1505 | |
| 1506 | state = simple_strtoul(buf, NULL, 0); |
| 1507 | |
| 1508 | /* get the slot number from the message */ |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1509 | pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; |
Tejun Heo | d50ce07 | 2009-05-12 10:57:41 +0900 | [diff] [blame] | 1510 | if (pmp < EM_MAX_SLOTS) |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1511 | emp = &pp->em_priv[pmp]; |
| 1512 | else |
| 1513 | return -EINVAL; |
| 1514 | |
| 1515 | /* mask off the activity bits if we are in sw_activity |
| 1516 | * mode, user should turn off sw_activity before setting |
| 1517 | * activity led through em_message |
| 1518 | */ |
| 1519 | if (emp->blink_policy) |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1520 | state &= ~EM_MSG_LED_VALUE_ACTIVITY; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1521 | |
| 1522 | return ahci_transmit_led_message(ap, state, size); |
| 1523 | } |
| 1524 | |
| 1525 | static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) |
| 1526 | { |
| 1527 | struct ata_link *link = dev->link; |
| 1528 | struct ata_port *ap = link->ap; |
| 1529 | struct ahci_port_priv *pp = ap->private_data; |
| 1530 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; |
| 1531 | u32 port_led_state = emp->led_state; |
| 1532 | |
| 1533 | /* save the desired Activity LED behavior */ |
| 1534 | if (val == OFF) { |
| 1535 | /* clear LFLAG */ |
| 1536 | link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); |
| 1537 | |
| 1538 | /* set the LED to OFF */ |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1539 | port_led_state &= EM_MSG_LED_VALUE_OFF; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1540 | port_led_state |= (ap->port_no | (link->pmp << 8)); |
| 1541 | ahci_transmit_led_message(ap, port_led_state, 4); |
| 1542 | } else { |
| 1543 | link->flags |= ATA_LFLAG_SW_ACTIVITY; |
| 1544 | if (val == BLINK_OFF) { |
| 1545 | /* set LED to ON for idle */ |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1546 | port_led_state &= EM_MSG_LED_VALUE_OFF; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1547 | port_led_state |= (ap->port_no | (link->pmp << 8)); |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 1548 | port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 1549 | ahci_transmit_led_message(ap, port_led_state, 4); |
| 1550 | } |
| 1551 | } |
| 1552 | emp->blink_policy = val; |
| 1553 | return 0; |
| 1554 | } |
| 1555 | |
| 1556 | static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) |
| 1557 | { |
| 1558 | struct ata_link *link = dev->link; |
| 1559 | struct ata_port *ap = link->ap; |
| 1560 | struct ahci_port_priv *pp = ap->private_data; |
| 1561 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; |
| 1562 | |
| 1563 | /* display the saved value of activity behavior for this |
| 1564 | * disk. |
| 1565 | */ |
| 1566 | return sprintf(buf, "%d\n", emp->blink_policy); |
| 1567 | } |
| 1568 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 1569 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
| 1570 | int port_no, void __iomem *mmio, |
| 1571 | void __iomem *port_mmio) |
| 1572 | { |
| 1573 | const char *emsg = NULL; |
| 1574 | int rc; |
| 1575 | u32 tmp; |
| 1576 | |
| 1577 | /* make sure port is not active */ |
| 1578 | rc = ahci_deinit_port(ap, &emsg); |
| 1579 | if (rc) |
| 1580 | dev_printk(KERN_WARNING, &pdev->dev, |
| 1581 | "%s (%d)\n", emsg, rc); |
| 1582 | |
| 1583 | /* clear SError */ |
| 1584 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 1585 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); |
| 1586 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 1587 | |
| 1588 | /* clear port IRQ */ |
| 1589 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1590 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 1591 | if (tmp) |
| 1592 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 1593 | |
| 1594 | writel(1 << port_no, mmio + HOST_IRQ_STAT); |
| 1595 | } |
| 1596 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1597 | static void ahci_init_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1598 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1599 | struct ahci_host_priv *hpriv = host->private_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1600 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 1601 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 1602 | int i; |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 1603 | void __iomem *port_mmio; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1604 | u32 tmp; |
Jose Alberto Reguero | c40e7cb | 2008-03-13 23:22:24 +0100 | [diff] [blame] | 1605 | int mv; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1606 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1607 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
Jose Alberto Reguero | c40e7cb | 2008-03-13 23:22:24 +0100 | [diff] [blame] | 1608 | if (pdev->device == 0x6121) |
| 1609 | mv = 2; |
| 1610 | else |
| 1611 | mv = 4; |
| 1612 | port_mmio = __ahci_port_base(host, mv); |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 1613 | |
| 1614 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 1615 | |
| 1616 | /* clear port IRQ */ |
| 1617 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1618 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 1619 | if (tmp) |
| 1620 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 1621 | } |
| 1622 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1623 | for (i = 0; i < host->n_ports; i++) { |
| 1624 | struct ata_port *ap = host->ports[i]; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1625 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 1626 | port_mmio = ahci_port_base(ap); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1627 | if (ata_port_is_dummy(ap)) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1628 | continue; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1629 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 1630 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1631 | } |
| 1632 | |
| 1633 | tmp = readl(mmio + HOST_CTL); |
| 1634 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 1635 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 1636 | tmp = readl(mmio + HOST_CTL); |
| 1637 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 1638 | } |
| 1639 | |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 1640 | static void ahci_dev_config(struct ata_device *dev) |
| 1641 | { |
| 1642 | struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; |
| 1643 | |
Jeff Garzik | 4cde32f | 2008-03-24 22:40:40 -0400 | [diff] [blame] | 1644 | if (hpriv->flags & AHCI_HFLAG_SECT255) { |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 1645 | dev->max_sectors = 255; |
Jeff Garzik | 4cde32f | 2008-03-24 22:40:40 -0400 | [diff] [blame] | 1646 | ata_dev_printk(dev, KERN_INFO, |
| 1647 | "SB600 AHCI: limiting to 255 sectors per cmd\n"); |
| 1648 | } |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 1649 | } |
| 1650 | |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1651 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1652 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1653 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1654 | struct ata_taskfile tf; |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1655 | u32 tmp; |
| 1656 | |
| 1657 | tmp = readl(port_mmio + PORT_SIG); |
| 1658 | tf.lbah = (tmp >> 24) & 0xff; |
| 1659 | tf.lbam = (tmp >> 16) & 0xff; |
| 1660 | tf.lbal = (tmp >> 8) & 0xff; |
| 1661 | tf.nsect = (tmp) & 0xff; |
| 1662 | |
| 1663 | return ata_dev_classify(&tf); |
| 1664 | } |
| 1665 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1666 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 1667 | u32 opts) |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1668 | { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1669 | dma_addr_t cmd_tbl_dma; |
| 1670 | |
| 1671 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; |
| 1672 | |
| 1673 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); |
| 1674 | pp->cmd_slot[tag].status = 0; |
| 1675 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); |
| 1676 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1677 | } |
| 1678 | |
Shane Huang | 78d5ae3 | 2009-08-07 15:05:52 +0800 | [diff] [blame] | 1679 | static int ahci_kick_engine(struct ata_port *ap) |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1680 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 1681 | void __iomem *port_mmio = ahci_port_base(ap); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1682 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | 520d06f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 1683 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1684 | u32 tmp; |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1685 | int busy, rc; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1686 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1687 | /* stop engine */ |
| 1688 | rc = ahci_stop_engine(ap); |
| 1689 | if (rc) |
| 1690 | goto out_restart; |
| 1691 | |
Shane Huang | 78d5ae3 | 2009-08-07 15:05:52 +0800 | [diff] [blame] | 1692 | /* need to do CLO? |
| 1693 | * always do CLO if PMP is attached (AHCI-1.3 9.2) |
| 1694 | */ |
| 1695 | busy = status & (ATA_BUSY | ATA_DRQ); |
| 1696 | if (!busy && !sata_pmp_attached(ap)) { |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1697 | rc = 0; |
| 1698 | goto out_restart; |
| 1699 | } |
| 1700 | |
| 1701 | if (!(hpriv->cap & HOST_CAP_CLO)) { |
| 1702 | rc = -EOPNOTSUPP; |
| 1703 | goto out_restart; |
| 1704 | } |
| 1705 | |
| 1706 | /* perform CLO */ |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1707 | tmp = readl(port_mmio + PORT_CMD); |
| 1708 | tmp |= PORT_CMD_CLO; |
| 1709 | writel(tmp, port_mmio + PORT_CMD); |
| 1710 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1711 | rc = 0; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1712 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 1713 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); |
| 1714 | if (tmp & PORT_CMD_CLO) |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1715 | rc = -EIO; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1716 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1717 | /* restart engine */ |
| 1718 | out_restart: |
| 1719 | ahci_start_engine(ap); |
| 1720 | return rc; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1721 | } |
| 1722 | |
Tejun Heo | 91c4a2e | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1723 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
| 1724 | struct ata_taskfile *tf, int is_cmd, u16 flags, |
| 1725 | unsigned long timeout_msec) |
| 1726 | { |
| 1727 | const u32 cmd_fis_len = 5; /* five dwords */ |
| 1728 | struct ahci_port_priv *pp = ap->private_data; |
| 1729 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1730 | u8 *fis = pp->cmd_tbl; |
| 1731 | u32 tmp; |
| 1732 | |
| 1733 | /* prep the command */ |
| 1734 | ata_tf_to_fis(tf, pmp, is_cmd, fis); |
| 1735 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); |
| 1736 | |
| 1737 | /* issue & wait */ |
| 1738 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 1739 | |
| 1740 | if (timeout_msec) { |
| 1741 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, |
| 1742 | 1, timeout_msec); |
| 1743 | if (tmp & 0x1) { |
Shane Huang | 78d5ae3 | 2009-08-07 15:05:52 +0800 | [diff] [blame] | 1744 | ahci_kick_engine(ap); |
Tejun Heo | 91c4a2e | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1745 | return -EBUSY; |
| 1746 | } |
| 1747 | } else |
| 1748 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1749 | |
| 1750 | return 0; |
| 1751 | } |
| 1752 | |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 1753 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
| 1754 | int pmp, unsigned long deadline, |
| 1755 | int (*check_ready)(struct ata_link *link)) |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1756 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1757 | struct ata_port *ap = link->ap; |
Tejun Heo | 5594639 | 2009-08-04 14:30:08 +0900 | [diff] [blame] | 1758 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1759 | const char *reason = NULL; |
Tejun Heo | 2cbb79e | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1760 | unsigned long now, msecs; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1761 | struct ata_taskfile tf; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1762 | int rc; |
| 1763 | |
| 1764 | DPRINTK("ENTER\n"); |
| 1765 | |
| 1766 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
Shane Huang | 78d5ae3 | 2009-08-07 15:05:52 +0800 | [diff] [blame] | 1767 | rc = ahci_kick_engine(ap); |
Tejun Heo | 994056d | 2007-12-06 15:02:48 +0900 | [diff] [blame] | 1768 | if (rc && rc != -EOPNOTSUPP) |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1769 | ata_link_printk(link, KERN_WARNING, |
Tejun Heo | 994056d | 2007-12-06 15:02:48 +0900 | [diff] [blame] | 1770 | "failed to reset engine (errno=%d)\n", rc); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1771 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1772 | ata_tf_init(link->device, &tf); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1773 | |
| 1774 | /* issue the first D2H Register FIS */ |
Tejun Heo | 2cbb79e | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1775 | msecs = 0; |
| 1776 | now = jiffies; |
| 1777 | if (time_after(now, deadline)) |
| 1778 | msecs = jiffies_to_msecs(deadline - now); |
| 1779 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1780 | tf.ctl |= ATA_SRST; |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1781 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
Tejun Heo | 91c4a2e | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1782 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1783 | rc = -EIO; |
| 1784 | reason = "1st FIS failed"; |
| 1785 | goto fail; |
| 1786 | } |
| 1787 | |
| 1788 | /* spec says at least 5us, but be generous and sleep for 1ms */ |
| 1789 | msleep(1); |
| 1790 | |
| 1791 | /* issue the second D2H Register FIS */ |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1792 | tf.ctl &= ~ATA_SRST; |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1793 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1794 | |
Tejun Heo | 705e76b | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1795 | /* wait for link to become ready */ |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 1796 | rc = ata_wait_after_reset(link, deadline, check_ready); |
Tejun Heo | 5594639 | 2009-08-04 14:30:08 +0900 | [diff] [blame] | 1797 | if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { |
| 1798 | /* |
| 1799 | * Workaround for cases where link online status can't |
| 1800 | * be trusted. Treat device readiness timeout as link |
| 1801 | * offline. |
| 1802 | */ |
| 1803 | ata_link_printk(link, KERN_INFO, |
| 1804 | "device not ready, treating as offline\n"); |
| 1805 | *class = ATA_DEV_NONE; |
| 1806 | } else if (rc) { |
| 1807 | /* link occupied, -ENODEV too is an error */ |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1808 | reason = "device not ready"; |
| 1809 | goto fail; |
Tejun Heo | 5594639 | 2009-08-04 14:30:08 +0900 | [diff] [blame] | 1810 | } else |
| 1811 | *class = ahci_dev_classify(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1812 | |
| 1813 | DPRINTK("EXIT, class=%u\n", *class); |
| 1814 | return 0; |
| 1815 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1816 | fail: |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1817 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1818 | return rc; |
| 1819 | } |
| 1820 | |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 1821 | static int ahci_check_ready(struct ata_link *link) |
| 1822 | { |
| 1823 | void __iomem *port_mmio = ahci_port_base(link->ap); |
| 1824 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; |
| 1825 | |
| 1826 | return ata_check_ready(status); |
| 1827 | } |
| 1828 | |
| 1829 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
| 1830 | unsigned long deadline) |
| 1831 | { |
| 1832 | int pmp = sata_srst_pmp(link); |
| 1833 | |
| 1834 | DPRINTK("ENTER\n"); |
| 1835 | |
| 1836 | return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); |
| 1837 | } |
| 1838 | |
| 1839 | static int ahci_sb600_check_ready(struct ata_link *link) |
| 1840 | { |
| 1841 | void __iomem *port_mmio = ahci_port_base(link->ap); |
| 1842 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; |
| 1843 | u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); |
| 1844 | |
| 1845 | /* |
| 1846 | * There is no need to check TFDATA if BAD PMP is found due to HW bug, |
| 1847 | * which can save timeout delay. |
| 1848 | */ |
| 1849 | if (irq_status & PORT_IRQ_BAD_PMP) |
| 1850 | return -EIO; |
| 1851 | |
| 1852 | return ata_check_ready(status); |
| 1853 | } |
| 1854 | |
| 1855 | static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, |
| 1856 | unsigned long deadline) |
| 1857 | { |
| 1858 | struct ata_port *ap = link->ap; |
| 1859 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1860 | int pmp = sata_srst_pmp(link); |
| 1861 | int rc; |
| 1862 | u32 irq_sts; |
| 1863 | |
| 1864 | DPRINTK("ENTER\n"); |
| 1865 | |
| 1866 | rc = ahci_do_softreset(link, class, pmp, deadline, |
| 1867 | ahci_sb600_check_ready); |
| 1868 | |
| 1869 | /* |
| 1870 | * Soft reset fails on some ATI chips with IPMS set when PMP |
| 1871 | * is enabled but SATA HDD/ODD is connected to SATA port, |
| 1872 | * do soft reset again to port 0. |
| 1873 | */ |
| 1874 | if (rc == -EIO) { |
| 1875 | irq_sts = readl(port_mmio + PORT_IRQ_STAT); |
| 1876 | if (irq_sts & PORT_IRQ_BAD_PMP) { |
| 1877 | ata_link_printk(link, KERN_WARNING, |
Shane Huang | b6931c1 | 2009-08-05 10:10:41 +0800 | [diff] [blame] | 1878 | "applying SB600 PMP SRST workaround " |
| 1879 | "and retrying\n"); |
Shane Huang | bd17243 | 2008-06-10 15:52:04 +0800 | [diff] [blame] | 1880 | rc = ahci_do_softreset(link, class, 0, deadline, |
| 1881 | ahci_check_ready); |
| 1882 | } |
| 1883 | } |
| 1884 | |
| 1885 | return rc; |
| 1886 | } |
| 1887 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1888 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1889 | unsigned long deadline) |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1890 | { |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1891 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1892 | struct ata_port *ap = link->ap; |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1893 | struct ahci_port_priv *pp = ap->private_data; |
| 1894 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1895 | struct ata_taskfile tf; |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1896 | bool online; |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1897 | int rc; |
| 1898 | |
| 1899 | DPRINTK("ENTER\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1900 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1901 | ahci_stop_engine(ap); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1902 | |
| 1903 | /* clear D2H reception area to properly wait for D2H FIS */ |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1904 | ata_tf_init(link->device, &tf); |
Tejun Heo | dfd7a3d | 2007-01-26 15:37:20 +0900 | [diff] [blame] | 1905 | tf.command = 0x80; |
Tejun Heo | 9977126 | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1906 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1907 | |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1908 | rc = sata_link_hardreset(link, timing, deadline, &online, |
| 1909 | ahci_check_ready); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1910 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1911 | ahci_start_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1912 | |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1913 | if (online) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1914 | *class = ahci_dev_classify(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1915 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1916 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1917 | return rc; |
| 1918 | } |
| 1919 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1920 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1921 | unsigned long deadline) |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1922 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1923 | struct ata_port *ap = link->ap; |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1924 | bool online; |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1925 | int rc; |
| 1926 | |
| 1927 | DPRINTK("ENTER\n"); |
| 1928 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1929 | ahci_stop_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1930 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1931 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1932 | deadline, &online, NULL); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1933 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1934 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1935 | |
| 1936 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1937 | |
| 1938 | /* vt8251 doesn't clear BSY on signature FIS reception, |
| 1939 | * request follow-up softreset. |
| 1940 | */ |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1941 | return online ? -EAGAIN : rc; |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1942 | } |
| 1943 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 1944 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
| 1945 | unsigned long deadline) |
| 1946 | { |
| 1947 | struct ata_port *ap = link->ap; |
| 1948 | struct ahci_port_priv *pp = ap->private_data; |
| 1949 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1950 | struct ata_taskfile tf; |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1951 | bool online; |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 1952 | int rc; |
| 1953 | |
| 1954 | ahci_stop_engine(ap); |
| 1955 | |
| 1956 | /* clear D2H reception area to properly wait for D2H FIS */ |
| 1957 | ata_tf_init(link->device, &tf); |
| 1958 | tf.command = 0x80; |
| 1959 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
| 1960 | |
| 1961 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1962 | deadline, &online, NULL); |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 1963 | |
| 1964 | ahci_start_engine(ap); |
| 1965 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 1966 | /* The pseudo configuration device on SIMG4726 attached to |
| 1967 | * ASUS P5W-DH Deluxe doesn't send signature FIS after |
| 1968 | * hardreset if no device is attached to the first downstream |
| 1969 | * port && the pseudo device locks up on SRST w/ PMP==0. To |
| 1970 | * work around this, wait for !BSY only briefly. If BSY isn't |
| 1971 | * cleared, perform CLO and proceed to IDENTIFY (achieved by |
| 1972 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). |
| 1973 | * |
| 1974 | * Wait for two seconds. Devices attached to downstream port |
| 1975 | * which can't process the following IDENTIFY after this will |
| 1976 | * have to be reset again. For most cases, this should |
| 1977 | * suffice while making probing snappish enough. |
| 1978 | */ |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1979 | if (online) { |
| 1980 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, |
| 1981 | ahci_check_ready); |
| 1982 | if (rc) |
Shane Huang | 78d5ae3 | 2009-08-07 15:05:52 +0800 | [diff] [blame] | 1983 | ahci_kick_engine(ap); |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1984 | } |
Tejun Heo | 9dadd45 | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 1985 | return rc; |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 1986 | } |
| 1987 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1988 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1989 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1990 | struct ata_port *ap = link->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1991 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1992 | u32 new_tmp, tmp; |
| 1993 | |
Tejun Heo | 203c75b | 2008-04-07 22:47:18 +0900 | [diff] [blame] | 1994 | ata_std_postreset(link, class); |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1995 | |
| 1996 | /* Make sure port's ATAPI bit is set appropriately */ |
| 1997 | new_tmp = tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1998 | if (*class == ATA_DEV_ATAPI) |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1999 | new_tmp |= PORT_CMD_ATAPI; |
| 2000 | else |
| 2001 | new_tmp &= ~PORT_CMD_ATAPI; |
| 2002 | if (new_tmp != tmp) { |
| 2003 | writel(new_tmp, port_mmio + PORT_CMD); |
| 2004 | readl(port_mmio + PORT_CMD); /* flush */ |
| 2005 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2006 | } |
| 2007 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2008 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2009 | { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 2010 | struct scatterlist *sg; |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 2011 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
| 2012 | unsigned int si; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2013 | |
| 2014 | VPRINTK("ENTER\n"); |
| 2015 | |
| 2016 | /* |
| 2017 | * Next, the S/G list. |
| 2018 | */ |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 2019 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 2020 | dma_addr_t addr = sg_dma_address(sg); |
| 2021 | u32 sg_len = sg_dma_len(sg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2022 | |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 2023 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
| 2024 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 2025 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2026 | } |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 2027 | |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 2028 | return si; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2029 | } |
| 2030 | |
| 2031 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
| 2032 | { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 2033 | struct ata_port *ap = qc->ap; |
| 2034 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 405e66b | 2007-11-27 19:28:53 +0900 | [diff] [blame] | 2035 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2036 | void *cmd_tbl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2037 | u32 opts; |
| 2038 | const u32 cmd_fis_len = 5; /* five dwords */ |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 2039 | unsigned int n_elem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2040 | |
| 2041 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2042 | * Fill in command table information. First, the header, |
| 2043 | * a SATA Register - Host to Device command FIS. |
| 2044 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2045 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
| 2046 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2047 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 2048 | if (is_atapi) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2049 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
| 2050 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 2051 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2052 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 2053 | n_elem = 0; |
| 2054 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2055 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2056 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 2057 | /* |
| 2058 | * Fill in command slot information. |
| 2059 | */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2060 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 2061 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 2062 | opts |= AHCI_CMD_WRITE; |
| 2063 | if (is_atapi) |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 2064 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 2065 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2066 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2067 | } |
| 2068 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2069 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2070 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2071 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2072 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2073 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
| 2074 | struct ata_link *link = NULL; |
| 2075 | struct ata_queued_cmd *active_qc; |
| 2076 | struct ata_eh_info *active_ehi; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2077 | u32 serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2078 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2079 | /* determine active link */ |
Tejun Heo | 1eca436 | 2008-11-03 20:03:17 +0900 | [diff] [blame] | 2080 | ata_for_each_link(link, ap, EDGE) |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2081 | if (ata_link_active(link)) |
| 2082 | break; |
| 2083 | if (!link) |
| 2084 | link = &ap->link; |
| 2085 | |
| 2086 | active_qc = ata_qc_from_tag(ap, link->active_tag); |
| 2087 | active_ehi = &link->eh_info; |
| 2088 | |
| 2089 | /* record irq stat */ |
| 2090 | ata_ehi_clear_desc(host_ehi); |
| 2091 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 2092 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2093 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 2094 | ahci_scr_read(&ap->link, SCR_ERROR, &serror); |
| 2095 | ahci_scr_write(&ap->link, SCR_ERROR, serror); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2096 | host_ehi->serror |= serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2097 | |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 2098 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2099 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 2100 | irq_stat &= ~PORT_IRQ_IF_ERR; |
| 2101 | |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 2102 | if (irq_stat & PORT_IRQ_TF_ERR) { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2103 | /* If qc is active, charge it; otherwise, the active |
| 2104 | * link. There's no active qc on NCQ errors. It will |
| 2105 | * be determined by EH by reading log page 10h. |
| 2106 | */ |
| 2107 | if (active_qc) |
| 2108 | active_qc->err_mask |= AC_ERR_DEV; |
| 2109 | else |
| 2110 | active_ehi->err_mask |= AC_ERR_DEV; |
| 2111 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2112 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2113 | host_ehi->serror &= ~SERR_INTERNAL; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2114 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2115 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2116 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
| 2117 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2118 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2119 | active_ehi->err_mask |= AC_ERR_HSM; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 2120 | active_ehi->action |= ATA_EH_RESET; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2121 | ata_ehi_push_desc(active_ehi, |
| 2122 | "unknown FIS %08x %08x %08x %08x" , |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2123 | unk[0], unk[1], unk[2], unk[3]); |
| 2124 | } |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 2125 | |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 2126 | if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2127 | active_ehi->err_mask |= AC_ERR_HSM; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 2128 | active_ehi->action |= ATA_EH_RESET; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2129 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); |
| 2130 | } |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2131 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2132 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { |
| 2133 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 2134 | host_ehi->action |= ATA_EH_RESET; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2135 | ata_ehi_push_desc(host_ehi, "host bus error"); |
| 2136 | } |
| 2137 | |
| 2138 | if (irq_stat & PORT_IRQ_IF_ERR) { |
| 2139 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 2140 | host_ehi->action |= ATA_EH_RESET; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2141 | ata_ehi_push_desc(host_ehi, "interface fatal error"); |
| 2142 | } |
| 2143 | |
| 2144 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
| 2145 | ata_ehi_hotplugged(host_ehi); |
| 2146 | ata_ehi_push_desc(host_ehi, "%s", |
| 2147 | irq_stat & PORT_IRQ_CONNECT ? |
| 2148 | "connection status changed" : "PHY RDY changed"); |
| 2149 | } |
| 2150 | |
| 2151 | /* okay, let's hand over to EH */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2152 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2153 | if (irq_stat & PORT_IRQ_FREEZE) |
| 2154 | ata_port_freeze(ap); |
| 2155 | else |
| 2156 | ata_port_abort(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2157 | } |
| 2158 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 2159 | static void ahci_port_intr(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2160 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 2161 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 2162 | struct ata_eh_info *ehi = &ap->link.eh_info; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 2163 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 2164 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 2165 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2166 | u32 status, qc_active; |
Tejun Heo | 459ad68 | 2007-12-07 12:46:23 +0900 | [diff] [blame] | 2167 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2168 | |
| 2169 | status = readl(port_mmio + PORT_IRQ_STAT); |
| 2170 | writel(status, port_mmio + PORT_IRQ_STAT); |
| 2171 | |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 2172 | /* ignore BAD_PMP while resetting */ |
| 2173 | if (unlikely(resetting)) |
| 2174 | status &= ~PORT_IRQ_BAD_PMP; |
| 2175 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 2176 | /* If we are getting PhyRdy, this is |
| 2177 | * just a power state change, we should |
| 2178 | * clear out this, plus the PhyRdy/Comm |
| 2179 | * Wake bits from Serror |
| 2180 | */ |
| 2181 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && |
| 2182 | (status & PORT_IRQ_PHYRDY)) { |
| 2183 | status &= ~PORT_IRQ_PHYRDY; |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 2184 | ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 2185 | } |
| 2186 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2187 | if (unlikely(status & PORT_IRQ_ERROR)) { |
| 2188 | ahci_error_intr(ap, status); |
| 2189 | return; |
| 2190 | } |
| 2191 | |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 2192 | if (status & PORT_IRQ_SDB_FIS) { |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 2193 | /* If SNotification is available, leave notification |
| 2194 | * handling to sata_async_notification(). If not, |
| 2195 | * emulate it by snooping SDB FIS RX area. |
| 2196 | * |
| 2197 | * Snooping FIS RX area is probably cheaper than |
| 2198 | * poking SNotification but some constrollers which |
| 2199 | * implement SNotification, ICH9 for example, don't |
| 2200 | * store AN SDB FIS into receive area. |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 2201 | */ |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 2202 | if (hpriv->cap & HOST_CAP_SNTF) |
Tejun Heo | 7d77b24 | 2007-09-23 13:14:13 +0900 | [diff] [blame] | 2203 | sata_async_notification(ap); |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 2204 | else { |
| 2205 | /* If the 'N' bit in word 0 of the FIS is set, |
| 2206 | * we just received asynchronous notification. |
| 2207 | * Tell libata about it. |
| 2208 | */ |
| 2209 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
| 2210 | u32 f0 = le32_to_cpu(f[0]); |
| 2211 | |
| 2212 | if (f0 & (1 << 15)) |
| 2213 | sata_async_notification(ap); |
| 2214 | } |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 2215 | } |
| 2216 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2217 | /* pp->active_link is valid iff any command is in flight */ |
| 2218 | if (ap->qc_active && pp->active_link->sactive) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2219 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
| 2220 | else |
| 2221 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); |
| 2222 | |
Tejun Heo | 79f97da | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 2223 | rc = ata_qc_complete_multiple(ap, qc_active); |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 2224 | |
Tejun Heo | 459ad68 | 2007-12-07 12:46:23 +0900 | [diff] [blame] | 2225 | /* while resetting, invalid completions are expected */ |
| 2226 | if (unlikely(rc < 0 && !resetting)) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2227 | ehi->err_mask |= AC_ERR_HSM; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 2228 | ehi->action |= ATA_EH_RESET; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2229 | ata_port_freeze(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2230 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2231 | } |
| 2232 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 2233 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2234 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2235 | struct ata_host *host = dev_instance; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2236 | struct ahci_host_priv *hpriv; |
| 2237 | unsigned int i, handled = 0; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 2238 | void __iomem *mmio; |
Tejun Heo | d28f87a | 2008-07-05 13:10:50 +0900 | [diff] [blame] | 2239 | u32 irq_stat, irq_masked; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2240 | |
| 2241 | VPRINTK("ENTER\n"); |
| 2242 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2243 | hpriv = host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2244 | mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2245 | |
| 2246 | /* sigh. 0xffffffff is a valid return from h/w */ |
| 2247 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2248 | if (!irq_stat) |
| 2249 | return IRQ_NONE; |
| 2250 | |
Tejun Heo | d28f87a | 2008-07-05 13:10:50 +0900 | [diff] [blame] | 2251 | irq_masked = irq_stat & hpriv->port_map; |
| 2252 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2253 | spin_lock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2254 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2255 | for (i = 0; i < host->n_ports; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2256 | struct ata_port *ap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2257 | |
Tejun Heo | d28f87a | 2008-07-05 13:10:50 +0900 | [diff] [blame] | 2258 | if (!(irq_masked & (1 << i))) |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 2259 | continue; |
| 2260 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2261 | ap = host->ports[i]; |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 2262 | if (ap) { |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 2263 | ahci_port_intr(ap); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 2264 | VPRINTK("port %u\n", i); |
| 2265 | } else { |
| 2266 | VPRINTK("port %u (no irq)\n", i); |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 2267 | if (ata_ratelimit()) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2268 | dev_printk(KERN_WARNING, host->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2269 | "interrupt on disabled port %u\n", i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2270 | } |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 2271 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2272 | handled = 1; |
| 2273 | } |
| 2274 | |
Tejun Heo | d28f87a | 2008-07-05 13:10:50 +0900 | [diff] [blame] | 2275 | /* HOST_IRQ_STAT behaves as level triggered latch meaning that |
| 2276 | * it should be cleared after all the port events are cleared; |
| 2277 | * otherwise, it will raise a spurious interrupt after each |
| 2278 | * valid one. Please read section 10.6.2 of ahci 1.1 for more |
| 2279 | * information. |
| 2280 | * |
| 2281 | * Also, use the unmasked value to clear interrupt as spurious |
| 2282 | * pending event on a dummy port might cause screaming IRQ. |
| 2283 | */ |
Tejun Heo | ea0c62f | 2008-06-28 01:49:02 +0900 | [diff] [blame] | 2284 | writel(irq_stat, mmio + HOST_IRQ_STAT); |
| 2285 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2286 | spin_unlock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2287 | |
| 2288 | VPRINTK("EXIT\n"); |
| 2289 | |
| 2290 | return IRQ_RETVAL(handled); |
| 2291 | } |
| 2292 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 2293 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2294 | { |
| 2295 | struct ata_port *ap = qc->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2296 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2297 | struct ahci_port_priv *pp = ap->private_data; |
| 2298 | |
| 2299 | /* Keep track of the currently active link. It will be used |
| 2300 | * in completion path to determine whether NCQ phase is in |
| 2301 | * progress. |
| 2302 | */ |
| 2303 | pp->active_link = qc->dev->link; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2304 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2305 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 2306 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
| 2307 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2308 | |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 2309 | ahci_sw_activity(qc->dev->link); |
| 2310 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2311 | return 0; |
| 2312 | } |
| 2313 | |
Tejun Heo | 4c9bf4e | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 2314 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) |
| 2315 | { |
| 2316 | struct ahci_port_priv *pp = qc->ap->private_data; |
| 2317 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 2318 | |
| 2319 | ata_tf_from_fis(d2h_fis, &qc->result_tf); |
| 2320 | return true; |
| 2321 | } |
| 2322 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2323 | static void ahci_freeze(struct ata_port *ap) |
| 2324 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2325 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2326 | |
| 2327 | /* turn IRQ off */ |
| 2328 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 2329 | } |
| 2330 | |
| 2331 | static void ahci_thaw(struct ata_port *ap) |
| 2332 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2333 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2334 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2335 | u32 tmp; |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 2336 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2337 | |
| 2338 | /* clear IRQ */ |
| 2339 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 2340 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
Tejun Heo | a718728 | 2007-01-27 11:04:26 +0900 | [diff] [blame] | 2341 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2342 | |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 2343 | /* turn IRQ back on */ |
| 2344 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2345 | } |
| 2346 | |
| 2347 | static void ahci_error_handler(struct ata_port *ap) |
| 2348 | { |
Tejun Heo | b51e9e5 | 2006-06-29 01:29:30 +0900 | [diff] [blame] | 2349 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2350 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2351 | ahci_stop_engine(ap); |
| 2352 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2353 | } |
| 2354 | |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 2355 | sata_pmp_error_handler(ap); |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 2356 | } |
| 2357 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2358 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
| 2359 | { |
| 2360 | struct ata_port *ap = qc->ap; |
| 2361 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 2362 | /* make DMA engine forget about the failed command */ |
| 2363 | if (qc->flags & ATA_QCFLAG_FAILED) |
Shane Huang | 78d5ae3 | 2009-08-07 15:05:52 +0800 | [diff] [blame] | 2364 | ahci_kick_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 2365 | } |
| 2366 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2367 | static void ahci_pmp_attach(struct ata_port *ap) |
| 2368 | { |
| 2369 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 2370 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2371 | u32 cmd; |
| 2372 | |
| 2373 | cmd = readl(port_mmio + PORT_CMD); |
| 2374 | cmd |= PORT_CMD_PMP; |
| 2375 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 2376 | |
| 2377 | pp->intr_mask |= PORT_IRQ_BAD_PMP; |
| 2378 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2379 | } |
| 2380 | |
| 2381 | static void ahci_pmp_detach(struct ata_port *ap) |
| 2382 | { |
| 2383 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 2384 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2385 | u32 cmd; |
| 2386 | |
| 2387 | cmd = readl(port_mmio + PORT_CMD); |
| 2388 | cmd &= ~PORT_CMD_PMP; |
| 2389 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 2390 | |
| 2391 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; |
| 2392 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2393 | } |
| 2394 | |
Alexey Dobriyan | 028a259 | 2007-07-17 23:48:48 +0400 | [diff] [blame] | 2395 | static int ahci_port_resume(struct ata_port *ap) |
| 2396 | { |
| 2397 | ahci_power_up(ap); |
| 2398 | ahci_start_port(ap); |
| 2399 | |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 2400 | if (sata_pmp_attached(ap)) |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2401 | ahci_pmp_attach(ap); |
| 2402 | else |
| 2403 | ahci_pmp_detach(ap); |
| 2404 | |
Alexey Dobriyan | 028a259 | 2007-07-17 23:48:48 +0400 | [diff] [blame] | 2405 | return 0; |
| 2406 | } |
| 2407 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 2408 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2409 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
| 2410 | { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2411 | const char *emsg = NULL; |
| 2412 | int rc; |
| 2413 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2414 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 2415 | if (rc == 0) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2416 | ahci_power_down(ap); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 2417 | else { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2418 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 2419 | ahci_start_port(ap); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2420 | } |
| 2421 | |
| 2422 | return rc; |
| 2423 | } |
| 2424 | |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2425 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
| 2426 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2427 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | 9b10ae8 | 2009-05-30 20:50:12 +0900 | [diff] [blame] | 2428 | struct ahci_host_priv *hpriv = host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2429 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2430 | u32 ctl; |
| 2431 | |
Tejun Heo | 9b10ae8 | 2009-05-30 20:50:12 +0900 | [diff] [blame] | 2432 | if (mesg.event & PM_EVENT_SUSPEND && |
| 2433 | hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { |
| 2434 | dev_printk(KERN_ERR, &pdev->dev, |
| 2435 | "BIOS update required for suspend/resume\n"); |
| 2436 | return -EIO; |
| 2437 | } |
| 2438 | |
Rafael J. Wysocki | 3a2d5b7 | 2008-02-23 19:13:25 +0100 | [diff] [blame] | 2439 | if (mesg.event & PM_EVENT_SLEEP) { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2440 | /* AHCI spec rev1.1 section 8.3.3: |
| 2441 | * Software must disable interrupts prior to requesting a |
| 2442 | * transition of the HBA to D3 state. |
| 2443 | */ |
| 2444 | ctl = readl(mmio + HOST_CTL); |
| 2445 | ctl &= ~HOST_IRQ_EN; |
| 2446 | writel(ctl, mmio + HOST_CTL); |
| 2447 | readl(mmio + HOST_CTL); /* flush */ |
| 2448 | } |
| 2449 | |
| 2450 | return ata_pci_device_suspend(pdev, mesg); |
| 2451 | } |
| 2452 | |
| 2453 | static int ahci_pci_device_resume(struct pci_dev *pdev) |
| 2454 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2455 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2456 | int rc; |
| 2457 | |
Tejun Heo | 553c4aa | 2006-12-26 19:39:50 +0900 | [diff] [blame] | 2458 | rc = ata_pci_device_do_resume(pdev); |
| 2459 | if (rc) |
| 2460 | return rc; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2461 | |
| 2462 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2463 | rc = ahci_reset_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2464 | if (rc) |
| 2465 | return rc; |
| 2466 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2467 | ahci_init_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2468 | } |
| 2469 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2470 | ata_host_resume(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2471 | |
| 2472 | return 0; |
| 2473 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 2474 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2475 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2476 | static int ahci_port_start(struct ata_port *ap) |
| 2477 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2478 | struct device *dev = ap->host->dev; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2479 | struct ahci_port_priv *pp; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2480 | void *mem; |
| 2481 | dma_addr_t mem_dma; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2482 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2483 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2484 | if (!pp) |
| 2485 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2486 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2487 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
| 2488 | GFP_KERNEL); |
| 2489 | if (!mem) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2490 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2491 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 2492 | |
| 2493 | /* |
| 2494 | * First item in chunk of DMA memory: 32-slot command table, |
| 2495 | * 32 bytes each in size |
| 2496 | */ |
| 2497 | pp->cmd_slot = mem; |
| 2498 | pp->cmd_slot_dma = mem_dma; |
| 2499 | |
| 2500 | mem += AHCI_CMD_SLOT_SZ; |
| 2501 | mem_dma += AHCI_CMD_SLOT_SZ; |
| 2502 | |
| 2503 | /* |
| 2504 | * Second item: Received-FIS area |
| 2505 | */ |
| 2506 | pp->rx_fis = mem; |
| 2507 | pp->rx_fis_dma = mem_dma; |
| 2508 | |
| 2509 | mem += AHCI_RX_FIS_SZ; |
| 2510 | mem_dma += AHCI_RX_FIS_SZ; |
| 2511 | |
| 2512 | /* |
| 2513 | * Third item: data area for storing a single command |
| 2514 | * and its scatter-gather table |
| 2515 | */ |
| 2516 | pp->cmd_tbl = mem; |
| 2517 | pp->cmd_tbl_dma = mem_dma; |
| 2518 | |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 2519 | /* |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2520 | * Save off initial list of interrupts to be enabled. |
| 2521 | * This could be changed later |
| 2522 | */ |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 2523 | pp->intr_mask = DEF_PORT_IRQ; |
| 2524 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2525 | ap->private_data = pp; |
| 2526 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 2527 | /* engage engines, captain */ |
| 2528 | return ahci_port_resume(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2529 | } |
| 2530 | |
| 2531 | static void ahci_port_stop(struct ata_port *ap) |
| 2532 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2533 | const char *emsg = NULL; |
| 2534 | int rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2535 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2536 | /* de-initialize port */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2537 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2538 | if (rc) |
| 2539 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2540 | } |
| 2541 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2542 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2543 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2544 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2545 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2546 | if (using_dac && |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 2547 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
| 2548 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2549 | if (rc) { |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 2550 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2551 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2552 | dev_printk(KERN_ERR, &pdev->dev, |
| 2553 | "64-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2554 | return rc; |
| 2555 | } |
| 2556 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2557 | } else { |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 2558 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2559 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2560 | dev_printk(KERN_ERR, &pdev->dev, |
| 2561 | "32-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2562 | return rc; |
| 2563 | } |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 2564 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2565 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2566 | dev_printk(KERN_ERR, &pdev->dev, |
| 2567 | "32-bit consistent DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2568 | return rc; |
| 2569 | } |
| 2570 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2571 | return 0; |
| 2572 | } |
| 2573 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2574 | static void ahci_print_info(struct ata_host *host) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2575 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2576 | struct ahci_host_priv *hpriv = host->private_data; |
| 2577 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2578 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 2579 | u32 vers, cap, cap2, impl, speed; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2580 | const char *speed_s; |
| 2581 | u16 cc; |
| 2582 | const char *scc_s; |
| 2583 | |
| 2584 | vers = readl(mmio + HOST_VERSION); |
| 2585 | cap = hpriv->cap; |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 2586 | cap2 = hpriv->cap2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2587 | impl = hpriv->port_map; |
| 2588 | |
| 2589 | speed = (cap >> 20) & 0xf; |
| 2590 | if (speed == 1) |
| 2591 | speed_s = "1.5"; |
| 2592 | else if (speed == 2) |
| 2593 | speed_s = "3"; |
Shane Huang | 8522ee2 | 2008-12-30 11:00:37 +0800 | [diff] [blame] | 2594 | else if (speed == 3) |
| 2595 | speed_s = "6"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2596 | else |
| 2597 | speed_s = "?"; |
| 2598 | |
| 2599 | pci_read_config_word(pdev, 0x0a, &cc); |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2600 | if (cc == PCI_CLASS_STORAGE_IDE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2601 | scc_s = "IDE"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2602 | else if (cc == PCI_CLASS_STORAGE_SATA) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2603 | scc_s = "SATA"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2604 | else if (cc == PCI_CLASS_STORAGE_RAID) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2605 | scc_s = "RAID"; |
| 2606 | else |
| 2607 | scc_s = "unknown"; |
| 2608 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2609 | dev_printk(KERN_INFO, &pdev->dev, |
| 2610 | "AHCI %02x%02x.%02x%02x " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2611 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2612 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2613 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2614 | (vers >> 24) & 0xff, |
| 2615 | (vers >> 16) & 0xff, |
| 2616 | (vers >> 8) & 0xff, |
| 2617 | vers & 0xff, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2618 | |
| 2619 | ((cap >> 8) & 0x1f) + 1, |
| 2620 | (cap & 0x1f) + 1, |
| 2621 | speed_s, |
| 2622 | impl, |
| 2623 | scc_s); |
| 2624 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2625 | dev_printk(KERN_INFO, &pdev->dev, |
| 2626 | "flags: " |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2627 | "%s%s%s%s%s%s%s" |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 2628 | "%s%s%s%s%s%s%s" |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 2629 | "%s%s%s%s%s%s\n" |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2630 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2631 | |
Robert Hancock | 4c521c8 | 2009-09-20 17:02:31 -0600 | [diff] [blame^] | 2632 | cap & HOST_CAP_64 ? "64bit " : "", |
| 2633 | cap & HOST_CAP_NCQ ? "ncq " : "", |
| 2634 | cap & HOST_CAP_SNTF ? "sntf " : "", |
| 2635 | cap & HOST_CAP_MPS ? "ilck " : "", |
| 2636 | cap & HOST_CAP_SSS ? "stag " : "", |
| 2637 | cap & HOST_CAP_ALPM ? "pm " : "", |
| 2638 | cap & HOST_CAP_LED ? "led " : "", |
| 2639 | cap & HOST_CAP_CLO ? "clo " : "", |
| 2640 | cap & HOST_CAP_ONLY ? "only " : "", |
| 2641 | cap & HOST_CAP_PMP ? "pmp " : "", |
| 2642 | cap & HOST_CAP_FBS ? "fbs " : "", |
| 2643 | cap & HOST_CAP_PIO_MULTI ? "pio " : "", |
| 2644 | cap & HOST_CAP_SSC ? "slum " : "", |
| 2645 | cap & HOST_CAP_PART ? "part " : "", |
| 2646 | cap & HOST_CAP_CCC ? "ccc " : "", |
| 2647 | cap & HOST_CAP_EMS ? "ems " : "", |
| 2648 | cap & HOST_CAP_SXS ? "sxs " : "", |
| 2649 | cap2 & HOST_CAP2_APST ? "apst " : "", |
| 2650 | cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", |
| 2651 | cap2 & HOST_CAP2_BOH ? "boh " : "" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2652 | ); |
| 2653 | } |
| 2654 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 2655 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
| 2656 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't |
| 2657 | * support PMP and the 4726 either directly exports the device |
| 2658 | * attached to the first downstream port or acts as a hardware storage |
| 2659 | * controller and emulate a single ATA device (can be RAID 0/1 or some |
| 2660 | * other configuration). |
| 2661 | * |
| 2662 | * When there's no device attached to the first downstream port of the |
| 2663 | * 4726, "Config Disk" appears, which is a pseudo ATA device to |
| 2664 | * configure the 4726. However, ATA emulation of the device is very |
| 2665 | * lame. It doesn't send signature D2H Reg FIS after the initial |
| 2666 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. |
| 2667 | * |
| 2668 | * The following function works around the problem by always using |
| 2669 | * hardreset on the port and not depending on receiving signature FIS |
| 2670 | * afterward. If signature FIS isn't received soon, ATA class is |
| 2671 | * assumed without follow-up softreset. |
| 2672 | */ |
| 2673 | static void ahci_p5wdh_workaround(struct ata_host *host) |
| 2674 | { |
| 2675 | static struct dmi_system_id sysids[] = { |
| 2676 | { |
| 2677 | .ident = "P5W DH Deluxe", |
| 2678 | .matches = { |
| 2679 | DMI_MATCH(DMI_SYS_VENDOR, |
| 2680 | "ASUSTEK COMPUTER INC"), |
| 2681 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), |
| 2682 | }, |
| 2683 | }, |
| 2684 | { } |
| 2685 | }; |
| 2686 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2687 | |
| 2688 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && |
| 2689 | dmi_check_system(sysids)) { |
| 2690 | struct ata_port *ap = host->ports[1]; |
| 2691 | |
| 2692 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " |
| 2693 | "Deluxe on-board SIMG4726 workaround\n"); |
| 2694 | |
| 2695 | ap->ops = &ahci_p5wdh_ops; |
| 2696 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; |
| 2697 | } |
| 2698 | } |
| 2699 | |
Tejun Heo | 2fcad9d | 2009-10-03 18:27:29 +0900 | [diff] [blame] | 2700 | /* only some SB600 ahci controllers can do 64bit DMA */ |
| 2701 | static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2702 | { |
| 2703 | static const struct dmi_system_id sysids[] = { |
Tejun Heo | 03d783b | 2009-08-16 21:04:02 +0900 | [diff] [blame] | 2704 | /* |
| 2705 | * The oldest version known to be broken is 0901 and |
| 2706 | * working is 1501 which was released on 2007-10-26. |
Tejun Heo | 2fcad9d | 2009-10-03 18:27:29 +0900 | [diff] [blame] | 2707 | * Enable 64bit DMA on 1501 and anything newer. |
| 2708 | * |
Tejun Heo | 03d783b | 2009-08-16 21:04:02 +0900 | [diff] [blame] | 2709 | * Please read bko#9412 for more info. |
| 2710 | */ |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2711 | { |
| 2712 | .ident = "ASUS M2A-VM", |
| 2713 | .matches = { |
| 2714 | DMI_MATCH(DMI_BOARD_VENDOR, |
| 2715 | "ASUSTeK Computer INC."), |
| 2716 | DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), |
| 2717 | }, |
Tejun Heo | 03d783b | 2009-08-16 21:04:02 +0900 | [diff] [blame] | 2718 | .driver_data = "20071026", /* yyyymmdd */ |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2719 | }, |
| 2720 | { } |
| 2721 | }; |
Tejun Heo | 03d783b | 2009-08-16 21:04:02 +0900 | [diff] [blame] | 2722 | const struct dmi_system_id *match; |
Tejun Heo | 2fcad9d | 2009-10-03 18:27:29 +0900 | [diff] [blame] | 2723 | int year, month, date; |
| 2724 | char buf[9]; |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2725 | |
Tejun Heo | 03d783b | 2009-08-16 21:04:02 +0900 | [diff] [blame] | 2726 | match = dmi_first_match(sysids); |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2727 | if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || |
Tejun Heo | 03d783b | 2009-08-16 21:04:02 +0900 | [diff] [blame] | 2728 | !match) |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2729 | return false; |
| 2730 | |
Tejun Heo | 2fcad9d | 2009-10-03 18:27:29 +0900 | [diff] [blame] | 2731 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
| 2732 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2733 | |
Tejun Heo | 2fcad9d | 2009-10-03 18:27:29 +0900 | [diff] [blame] | 2734 | if (strcmp(buf, match->driver_data) >= 0) { |
| 2735 | dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n", |
| 2736 | match->ident); |
| 2737 | return true; |
| 2738 | } else { |
Tejun Heo | 03d783b | 2009-08-16 21:04:02 +0900 | [diff] [blame] | 2739 | dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, " |
| 2740 | "forcing 32bit DMA, update BIOS\n", match->ident); |
Tejun Heo | 2fcad9d | 2009-10-03 18:27:29 +0900 | [diff] [blame] | 2741 | return false; |
| 2742 | } |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2743 | } |
| 2744 | |
Rafael J. Wysocki | 1fd6843 | 2009-01-19 20:57:36 +0100 | [diff] [blame] | 2745 | static bool ahci_broken_system_poweroff(struct pci_dev *pdev) |
| 2746 | { |
| 2747 | static const struct dmi_system_id broken_systems[] = { |
| 2748 | { |
| 2749 | .ident = "HP Compaq nx6310", |
| 2750 | .matches = { |
| 2751 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), |
| 2752 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), |
| 2753 | }, |
| 2754 | /* PCI slot number of the controller */ |
| 2755 | .driver_data = (void *)0x1FUL, |
| 2756 | }, |
Maciej Rutecki | d2f9c06 | 2009-03-20 00:06:46 +0100 | [diff] [blame] | 2757 | { |
| 2758 | .ident = "HP Compaq 6720s", |
| 2759 | .matches = { |
| 2760 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), |
| 2761 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), |
| 2762 | }, |
| 2763 | /* PCI slot number of the controller */ |
| 2764 | .driver_data = (void *)0x1FUL, |
| 2765 | }, |
Rafael J. Wysocki | 1fd6843 | 2009-01-19 20:57:36 +0100 | [diff] [blame] | 2766 | |
| 2767 | { } /* terminate list */ |
| 2768 | }; |
| 2769 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); |
| 2770 | |
| 2771 | if (dmi) { |
| 2772 | unsigned long slot = (unsigned long)dmi->driver_data; |
| 2773 | /* apply the quirk only to on-board controllers */ |
| 2774 | return slot == PCI_SLOT(pdev->devfn); |
| 2775 | } |
| 2776 | |
| 2777 | return false; |
| 2778 | } |
| 2779 | |
Tejun Heo | 9b10ae8 | 2009-05-30 20:50:12 +0900 | [diff] [blame] | 2780 | static bool ahci_broken_suspend(struct pci_dev *pdev) |
| 2781 | { |
| 2782 | static const struct dmi_system_id sysids[] = { |
| 2783 | /* |
| 2784 | * On HP dv[4-6] and HDX18 with earlier BIOSen, link |
| 2785 | * to the harddisk doesn't become online after |
| 2786 | * resuming from STR. Warn and fail suspend. |
| 2787 | */ |
| 2788 | { |
| 2789 | .ident = "dv4", |
| 2790 | .matches = { |
| 2791 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), |
| 2792 | DMI_MATCH(DMI_PRODUCT_NAME, |
| 2793 | "HP Pavilion dv4 Notebook PC"), |
| 2794 | }, |
| 2795 | .driver_data = "F.30", /* cutoff BIOS version */ |
| 2796 | }, |
| 2797 | { |
| 2798 | .ident = "dv5", |
| 2799 | .matches = { |
| 2800 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), |
| 2801 | DMI_MATCH(DMI_PRODUCT_NAME, |
| 2802 | "HP Pavilion dv5 Notebook PC"), |
| 2803 | }, |
| 2804 | .driver_data = "F.16", /* cutoff BIOS version */ |
| 2805 | }, |
| 2806 | { |
| 2807 | .ident = "dv6", |
| 2808 | .matches = { |
| 2809 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), |
| 2810 | DMI_MATCH(DMI_PRODUCT_NAME, |
| 2811 | "HP Pavilion dv6 Notebook PC"), |
| 2812 | }, |
| 2813 | .driver_data = "F.21", /* cutoff BIOS version */ |
| 2814 | }, |
| 2815 | { |
| 2816 | .ident = "HDX18", |
| 2817 | .matches = { |
| 2818 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), |
| 2819 | DMI_MATCH(DMI_PRODUCT_NAME, |
| 2820 | "HP HDX18 Notebook PC"), |
| 2821 | }, |
| 2822 | .driver_data = "F.23", /* cutoff BIOS version */ |
| 2823 | }, |
| 2824 | { } /* terminate list */ |
| 2825 | }; |
| 2826 | const struct dmi_system_id *dmi = dmi_first_match(sysids); |
| 2827 | const char *ver; |
| 2828 | |
| 2829 | if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) |
| 2830 | return false; |
| 2831 | |
| 2832 | ver = dmi_get_system_info(DMI_BIOS_VERSION); |
| 2833 | |
| 2834 | return !ver || strcmp(ver, dmi->driver_data) < 0; |
| 2835 | } |
| 2836 | |
Tejun Heo | 5594639 | 2009-08-04 14:30:08 +0900 | [diff] [blame] | 2837 | static bool ahci_broken_online(struct pci_dev *pdev) |
| 2838 | { |
| 2839 | #define ENCODE_BUSDEVFN(bus, slot, func) \ |
| 2840 | (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) |
| 2841 | static const struct dmi_system_id sysids[] = { |
| 2842 | /* |
| 2843 | * There are several gigabyte boards which use |
| 2844 | * SIMG5723s configured as hardware RAID. Certain |
| 2845 | * 5723 firmware revisions shipped there keep the link |
| 2846 | * online but fail to answer properly to SRST or |
| 2847 | * IDENTIFY when no device is attached downstream |
| 2848 | * causing libata to retry quite a few times leading |
| 2849 | * to excessive detection delay. |
| 2850 | * |
| 2851 | * As these firmwares respond to the second reset try |
| 2852 | * with invalid device signature, considering unknown |
| 2853 | * sig as offline works around the problem acceptably. |
| 2854 | */ |
| 2855 | { |
| 2856 | .ident = "EP45-DQ6", |
| 2857 | .matches = { |
| 2858 | DMI_MATCH(DMI_BOARD_VENDOR, |
| 2859 | "Gigabyte Technology Co., Ltd."), |
| 2860 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), |
| 2861 | }, |
| 2862 | .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), |
| 2863 | }, |
| 2864 | { |
| 2865 | .ident = "EP45-DS5", |
| 2866 | .matches = { |
| 2867 | DMI_MATCH(DMI_BOARD_VENDOR, |
| 2868 | "Gigabyte Technology Co., Ltd."), |
| 2869 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), |
| 2870 | }, |
| 2871 | .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), |
| 2872 | }, |
| 2873 | { } /* terminate list */ |
| 2874 | }; |
| 2875 | #undef ENCODE_BUSDEVFN |
| 2876 | const struct dmi_system_id *dmi = dmi_first_match(sysids); |
| 2877 | unsigned int val; |
| 2878 | |
| 2879 | if (!dmi) |
| 2880 | return false; |
| 2881 | |
| 2882 | val = (unsigned long)dmi->driver_data; |
| 2883 | |
| 2884 | return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); |
| 2885 | } |
| 2886 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2887 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2888 | { |
| 2889 | static int printed_version; |
Tejun Heo | e297d99 | 2008-06-10 00:13:04 +0900 | [diff] [blame] | 2890 | unsigned int board_id = ent->driver_data; |
| 2891 | struct ata_port_info pi = ahci_port_info[board_id]; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2892 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2893 | struct device *dev = &pdev->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2894 | struct ahci_host_priv *hpriv; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2895 | struct ata_host *host; |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 2896 | int n_ports, i, rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2897 | |
| 2898 | VPRINTK("ENTER\n"); |
| 2899 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2900 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
| 2901 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2902 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2903 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2904 | |
Alan Cox | 5b66c82 | 2008-09-03 14:48:34 +0100 | [diff] [blame] | 2905 | /* The AHCI driver can only drive the SATA ports, the PATA driver |
| 2906 | can drive them all so if both drivers are selected make sure |
| 2907 | AHCI stays out of the way */ |
| 2908 | if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) |
| 2909 | return -ENODEV; |
| 2910 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2911 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2912 | rc = pcim_enable_device(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2913 | if (rc) |
| 2914 | return rc; |
| 2915 | |
Tejun Heo | dea5513 | 2008-03-11 19:52:31 +0900 | [diff] [blame] | 2916 | /* AHCI controllers often implement SFF compatible interface. |
| 2917 | * Grab all PCI BARs just in case. |
| 2918 | */ |
| 2919 | rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2920 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2921 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2922 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2923 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2924 | |
Tejun Heo | c4f7792 | 2007-12-06 15:09:43 +0900 | [diff] [blame] | 2925 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
| 2926 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { |
| 2927 | u8 map; |
| 2928 | |
| 2929 | /* ICH6s share the same PCI ID for both piix and ahci |
| 2930 | * modes. Enabling ahci mode while MAP indicates |
| 2931 | * combined mode is a bad idea. Yield to ata_piix. |
| 2932 | */ |
| 2933 | pci_read_config_byte(pdev, ICH_MAP, &map); |
| 2934 | if (map & 0x3) { |
| 2935 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " |
| 2936 | "combined mode, can't enable AHCI mode\n"); |
| 2937 | return -ENODEV; |
| 2938 | } |
| 2939 | } |
| 2940 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2941 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
| 2942 | if (!hpriv) |
| 2943 | return -ENOMEM; |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2944 | hpriv->flags |= (unsigned long)pi.private_data; |
| 2945 | |
Tejun Heo | e297d99 | 2008-06-10 00:13:04 +0900 | [diff] [blame] | 2946 | /* MCP65 revision A1 and A2 can't do MSI */ |
| 2947 | if (board_id == board_ahci_mcp65 && |
| 2948 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) |
| 2949 | hpriv->flags |= AHCI_HFLAG_NO_MSI; |
| 2950 | |
Shane Huang | e427fe0 | 2008-12-30 10:53:41 +0800 | [diff] [blame] | 2951 | /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ |
| 2952 | if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) |
| 2953 | hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; |
| 2954 | |
Tejun Heo | 2fcad9d | 2009-10-03 18:27:29 +0900 | [diff] [blame] | 2955 | /* only some SB600s can do 64bit DMA */ |
| 2956 | if (ahci_sb600_enable_64bit(pdev)) |
| 2957 | hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; |
Shane Huang | 58a09b3 | 2009-05-27 15:04:43 +0800 | [diff] [blame] | 2958 | |
Tejun Heo | 31b239a | 2009-09-17 00:34:39 +0900 | [diff] [blame] | 2959 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) |
| 2960 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2961 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2962 | /* save initial config */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2963 | ahci_save_initial_config(pdev, hpriv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2964 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2965 | /* prepare host */ |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2966 | if (hpriv->cap & HOST_CAP_NCQ) |
Shaohua Li | 388539f | 2009-07-27 09:24:35 +0800 | [diff] [blame] | 2967 | pi.flags |= ATA_FLAG_NCQ | ATA_FLAG_FPDMA_AA; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2968 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2969 | if (hpriv->cap & HOST_CAP_PMP) |
| 2970 | pi.flags |= ATA_FLAG_PMP; |
| 2971 | |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 2972 | if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) { |
| 2973 | u8 messages; |
| 2974 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
| 2975 | u32 em_loc = readl(mmio + HOST_EM_LOC); |
| 2976 | u32 em_ctl = readl(mmio + HOST_EM_CTL); |
| 2977 | |
David Milburn | 87943ac | 2008-10-13 14:38:36 -0500 | [diff] [blame] | 2978 | messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 2979 | |
| 2980 | /* we only support LED message type right now */ |
| 2981 | if ((messages & 0x01) && (ahci_em_messages == 1)) { |
| 2982 | /* store em_loc */ |
| 2983 | hpriv->em_loc = ((em_loc >> 16) * 4); |
| 2984 | pi.flags |= ATA_FLAG_EM; |
| 2985 | if (!(em_ctl & EM_CTL_ALHD)) |
| 2986 | pi.flags |= ATA_FLAG_SW_ACTIVITY; |
| 2987 | } |
| 2988 | } |
| 2989 | |
Rafael J. Wysocki | 1fd6843 | 2009-01-19 20:57:36 +0100 | [diff] [blame] | 2990 | if (ahci_broken_system_poweroff(pdev)) { |
| 2991 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; |
| 2992 | dev_info(&pdev->dev, |
| 2993 | "quirky BIOS, skipping spindown on poweroff\n"); |
| 2994 | } |
| 2995 | |
Tejun Heo | 9b10ae8 | 2009-05-30 20:50:12 +0900 | [diff] [blame] | 2996 | if (ahci_broken_suspend(pdev)) { |
| 2997 | hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; |
| 2998 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2999 | "BIOS update required for suspend/resume\n"); |
| 3000 | } |
| 3001 | |
Tejun Heo | 5594639 | 2009-08-04 14:30:08 +0900 | [diff] [blame] | 3002 | if (ahci_broken_online(pdev)) { |
| 3003 | hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; |
| 3004 | dev_info(&pdev->dev, |
| 3005 | "online status unreliable, applying workaround\n"); |
| 3006 | } |
| 3007 | |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 3008 | /* CAP.NP sometimes indicate the index of the last enabled |
| 3009 | * port, at other times, that of the last possible port, so |
| 3010 | * determining the maximum port number requires looking at |
| 3011 | * both CAP.NP and port_map. |
| 3012 | */ |
| 3013 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); |
| 3014 | |
| 3015 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3016 | if (!host) |
| 3017 | return -ENOMEM; |
| 3018 | host->iomap = pcim_iomap_table(pdev); |
| 3019 | host->private_data = hpriv; |
| 3020 | |
Arjan van de Ven | f3d7f23 | 2009-01-26 02:05:44 -0800 | [diff] [blame] | 3021 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
Arjan van de Ven | 886ad09 | 2009-01-09 15:54:07 -0800 | [diff] [blame] | 3022 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
Arjan van de Ven | f3d7f23 | 2009-01-26 02:05:44 -0800 | [diff] [blame] | 3023 | else |
| 3024 | printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); |
Arjan van de Ven | 886ad09 | 2009-01-09 15:54:07 -0800 | [diff] [blame] | 3025 | |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 3026 | if (pi.flags & ATA_FLAG_EM) |
| 3027 | ahci_reset_em(host); |
| 3028 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3029 | for (i = 0; i < host->n_ports; i++) { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 3030 | struct ata_port *ap = host->ports[i]; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3031 | |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 3032 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
| 3033 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, |
| 3034 | 0x100 + ap->port_no * 0x80, "port"); |
| 3035 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 3036 | /* set initial link pm policy */ |
| 3037 | ap->pm_policy = NOT_AVAILABLE; |
| 3038 | |
Kristen Carlson Accardi | 18f7ba4 | 2008-06-03 10:33:55 -0700 | [diff] [blame] | 3039 | /* set enclosure management message type */ |
| 3040 | if (ap->flags & ATA_FLAG_EM) |
| 3041 | ap->em_message_type = ahci_em_messages; |
| 3042 | |
| 3043 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 3044 | /* disabled/not-implemented port */ |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 3045 | if (!(hpriv->port_map & (1 << i))) |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 3046 | ap->ops = &ata_dummy_port_ops; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3047 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3048 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 3049 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
| 3050 | ahci_p5wdh_workaround(host); |
| 3051 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3052 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3053 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3054 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3055 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3056 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3057 | rc = ahci_reset_controller(host); |
| 3058 | if (rc) |
| 3059 | return rc; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 3060 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3061 | ahci_init_controller(host); |
| 3062 | ahci_print_info(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3063 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3064 | pci_set_master(pdev); |
| 3065 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, |
| 3066 | &ahci_sht); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 3067 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3068 | |
| 3069 | static int __init ahci_init(void) |
| 3070 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 3071 | return pci_register_driver(&ahci_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3072 | } |
| 3073 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3074 | static void __exit ahci_exit(void) |
| 3075 | { |
| 3076 | pci_unregister_driver(&ahci_pci_driver); |
| 3077 | } |
| 3078 | |
| 3079 | |
| 3080 | MODULE_AUTHOR("Jeff Garzik"); |
| 3081 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); |
| 3082 | MODULE_LICENSE("GPL"); |
| 3083 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
Jeff Garzik | 6885433 | 2005-08-23 02:53:51 -0400 | [diff] [blame] | 3084 | MODULE_VERSION(DRV_VERSION); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3085 | |
| 3086 | module_init(ahci_init); |
| 3087 | module_exit(ahci_exit); |