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gerrit-public.fairphone.software / kernel / msm / 5df326aca48b8631c9e3c90c76d7e9f0b466a721 / . / arch / blackfin / mach-bf548 / Kconfig
blob: 70189a0d1a1905d95dbf6c243f0f1c4e88d6e6d8 [file] [log] [blame]
Mike Frysinger5df326a2009-11-16 23:49:41 +0000[diff] [blame^]1config BF542
2 def_bool y
3 depends on BF542_std || BF542M
4config BF544
5 def_bool y
6 depends on BF544_std || BF544M
7config BF547
8 def_bool y
9 depends on BF547_std || BF547M
10config BF548
11 def_bool y
12 depends on BF548_std || BF548M
13config BF549
14 def_bool y
15 depends on BF549_std || BF549M
16
17config BF54xM
18 def_bool y
19 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
20
21config BF54x
22 def_bool y
23 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
24
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]25if (BF54x)
26
Mike Frysinger4f25eb82007-11-15 20:49:44 +0800[diff] [blame]27source "arch/blackfin/mach-bf548/boards/Kconfig"
28
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]29menu "BF548 Specific Configuration"
30
Michael Hennericha924db72007-08-03 17:43:29 +0800[diff] [blame]31config DEB_DMA_URGENT
32 bool "DMA has priority over core for ext. accesses"
33 depends on BF54x
Cliff Caib8aab6f2007-12-24 12:33:20 +0800[diff] [blame]34 default y
Michael Hennericha924db72007-08-03 17:43:29 +0800[diff] [blame]35 help
36 Treat any DEB1, DEB2 and DEB3 request as Urgent
37
Sonic Zhang8d5c2f02009-03-30 09:07:26 +0000[diff] [blame]38config BF548_ATAPI_ALTERNATIVE_PORT
39 bool "BF548 ATAPI alternative port via GPIO"
40 help
41 BF548 ATAPI data and address PINs can be routed through
42 async address or GPIO port F and G. Select y to route it
43 to GPIO.
44
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]45comment "Interrupt Priority Assignment"
46menu "Priority"
47
48config IRQ_PLL_WAKEUP
49 int "IRQ_PLL_WAKEUP"
50 default 7
51config IRQ_DMAC0_ERR
52 int "IRQ_DMAC0_ERR"
53 default 7
54config IRQ_EPPI0_ERR
55 int "IRQ_EPPI0_ERR"
56 default 7
57config IRQ_SPORT0_ERR
58 int "IRQ_SPORT0_ERR"
59 default 7
60config IRQ_SPORT1_ERR
61 int "IRQ_SPORT1_ERR"
62 default 7
63config IRQ_SPI0_ERR
64 int "IRQ_SPI0_ERR"
65 default 7
66config IRQ_UART0_ERR
67 int "IRQ_UART0_ERR"
68 default 7
69config IRQ_RTC
70 int "IRQ_RTC"
71 default 8
72config IRQ_EPPI0
73 int "IRQ_EPPI0"
74 default 8
75config IRQ_SPORT0_RX
76 int "IRQ_SPORT0_RX"
77 default 9
78config IRQ_SPORT0_TX
79 int "IRQ_SPORT0_TX"
80 default 9
81config IRQ_SPORT1_RX
82 int "IRQ_SPORT1_RX"
83 default 9
84config IRQ_SPORT1_TX
85 int "IRQ_SPORT1_TX"
86 default 9
87config IRQ_SPI0
88 int "IRQ_SPI0"
89 default 10
90config IRQ_UART0_RX
91 int "IRQ_UART0_RX"
92 default 10
93config IRQ_UART0_TX
94 int "IRQ_UART0_TX"
95 default 10
96config IRQ_TIMER8
97 int "IRQ_TIMER8"
98 default 11
99config IRQ_TIMER9
100 int "IRQ_TIMER9"
101 default 11
102config IRQ_TIMER10
103 int "IRQ_TIMER10"
104 default 11
105config IRQ_PINT0
106 int "IRQ_PINT0"
107 default 12
108config IRQ_PINT1
109 int "IRQ_PINT0"
110 default 12
111config IRQ_MDMAS0
112 int "IRQ_MDMAS0"
113 default 13
114config IRQ_MDMAS1
115 int "IRQ_DMDMAS1"
116 default 13
117config IRQ_WATCHDOG
118 int "IRQ_WATCHDOG"
119 default 13
120config IRQ_DMAC1_ERR
121 int "IRQ_DMAC1_ERR"
122 default 7
123config IRQ_SPORT2_ERR
124 int "IRQ_SPORT2_ERR"
125 default 7
126config IRQ_SPORT3_ERR
127 int "IRQ_SPORT3_ERR"
128 default 7
129config IRQ_MXVR_DATA
130 int "IRQ MXVR Data"
131 default 7
132config IRQ_SPI1_ERR
133 int "IRQ_SPI1_ERR"
134 default 7
135config IRQ_SPI2_ERR
136 int "IRQ_SPI2_ERR"
137 default 7
138config IRQ_UART1_ERR
139 int "IRQ_UART1_ERR"
140 default 7
141config IRQ_UART2_ERR
142 int "IRQ_UART2_ERR"
143 default 7
144config IRQ_CAN0_ERR
145 int "IRQ_CAN0_ERR"
146 default 7
147config IRQ_SPORT2_RX
148 int "IRQ_SPORT2_RX"
149 default 9
150config IRQ_SPORT2_TX
151 int "IRQ_SPORT2_TX"
152 default 9
153config IRQ_SPORT3_RX
154 int "IRQ_SPORT3_RX"
155 default 9
156config IRQ_SPORT3_TX
157 int "IRQ_SPORT3_TX"
158 default 9
159config IRQ_EPPI1
160 int "IRQ_EPPI1"
161 default 9
162config IRQ_EPPI2
163 int "IRQ_EPPI2"
164 default 9
165config IRQ_SPI1
166 int "IRQ_SPI1"
167 default 10
168config IRQ_SPI2
169 int "IRQ_SPI2"
170 default 10
171config IRQ_UART1_RX
172 int "IRQ_UART1_RX"
173 default 10
174config IRQ_UART1_TX
175 int "IRQ_UART1_TX"
176 default 10
177config IRQ_ATAPI_RX
178 int "IRQ_ATAPI_RX"
179 default 10
180config IRQ_ATAPI_TX
181 int "IRQ_ATAPI_TX"
182 default 10
183config IRQ_TWI0
184 int "IRQ_TWI0"
185 default 11
186config IRQ_TWI1
187 int "IRQ_TWI1"
188 default 11
189config IRQ_CAN0_RX
190 int "IRQ_CAN_RX"
191 default 11
192config IRQ_CAN0_TX
193 int "IRQ_CAN_TX"
194 default 11
195config IRQ_MDMAS2
196 int "IRQ_MDMAS2"
197 default 13
198config IRQ_MDMAS3
199 int "IRQ_DMMAS3"
200 default 13
201config IRQ_MXVR_ERR
202 int "IRQ_MXVR_ERR"
203 default 11
204config IRQ_MXVR_MSG
205 int "IRQ_MXVR_MSG"
206 default 11
207config IRQ_MXVR_PKT
208 int "IRQ_MXVR_PKT"
209 default 11
210config IRQ_EPPI1_ERR
211 int "IRQ_EPPI1_ERR"
212 default 7
213config IRQ_EPPI2_ERR
214 int "IRQ_EPPI2_ERR"
215 default 7
216config IRQ_UART3_ERR
217 int "IRQ_UART3_ERR"
218 default 7
219config IRQ_HOST_ERR
220 int "IRQ_HOST_ERR"
221 default 7
222config IRQ_PIXC_ERR
223 int "IRQ_PIXC_ERR"
224 default 7
225config IRQ_NFC_ERR
226 int "IRQ_NFC_ERR"
227 default 7
228config IRQ_ATAPI_ERR
229 int "IRQ_ATAPI_ERR"
230 default 7
231config IRQ_CAN1_ERR
232 int "IRQ_CAN1_ERR"
233 default 7
234config IRQ_HS_DMA_ERR
235 int "IRQ Handshake DMA Status"
236 default 7
237config IRQ_PIXC_IN0
238 int "IRQ PIXC IN0"
239 default 8
240config IRQ_PIXC_IN1
241 int "IRQ PIXC IN1"
242 default 8
243config IRQ_PIXC_OUT
244 int "IRQ PIXC OUT"
245 default 8
246config IRQ_SDH
247 int "IRQ SDH"
248 default 8
249config IRQ_CNT
250 int "IRQ CNT"
251 default 8
252config IRQ_KEY
253 int "IRQ KEY"
254 default 8
255config IRQ_CAN1_RX
256 int "IRQ CAN1 RX"
257 default 11
258config IRQ_CAN1_TX
259 int "IRQ_CAN1_TX"
260 default 11
261config IRQ_SDH_MASK0
262 int "IRQ_SDH_MASK0"
263 default 11
264config IRQ_SDH_MASK1
265 int "IRQ_SDH_MASK1"
266 default 11
267config IRQ_USB_INT0
268 int "IRQ USB INT0"
269 default 11
270config IRQ_USB_INT1
271 int "IRQ USB INT1"
272 default 11
273config IRQ_USB_INT2
274 int "IRQ USB INT2"
275 default 11
276config IRQ_USB_DMA
277 int "IRQ USB DMA"
278 default 11
279config IRQ_OTPSEC
280 int "IRQ OPTSEC"
281 default 11
282config IRQ_TIMER0
283 int "IRQ_TIMER0"
Graf Yang1fa9be72009-05-15 11:01:59 +0000[diff] [blame]284 default 7 if TICKSOURCE_GPTMR0
Yi Li6a01f232009-01-07 23:14:39 +0800[diff] [blame]285 default 8
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]286config IRQ_TIMER1
287 int "IRQ_TIMER1"
288 default 11
289config IRQ_TIMER2
290 int "IRQ_TIMER2"
291 default 11
292config IRQ_TIMER3
293 int "IRQ_TIMER3"
294 default 11
295config IRQ_TIMER4
296 int "IRQ_TIMER4"
297 default 11
298config IRQ_TIMER5
299 int "IRQ_TIMER5"
300 default 11
301config IRQ_TIMER6
302 int "IRQ_TIMER6"
303 default 11
304config IRQ_TIMER7
305 int "IRQ_TIMER7"
306 default 11
307config IRQ_PINT2
308 int "IRQ_PIN2"
309 default 11
310config IRQ_PINT3
311 int "IRQ_PIN3"
312 default 11
313
314 help
315 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
316 This applies to all the above. It is not recommended to assign the
317 highest priority number 7 to UART or any other device.
318
319endmenu
320
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]321comment "Pin Interrupt to Port Assignment"
322menu "Assignment"
323
324config PINTx_REASSIGN
325 bool "Reprogram PINT Assignment"
Michael Hennerich31430ba2007-07-24 16:27:25 +0800[diff] [blame]326 default y
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]327 help
328 The interrupt assignment registers controls the pin-to-interrupt
329 assignment in a byte-wide manner. Each option allows you to select
330 a set of pins (High/Low Byte) of an specific Port being mapped
331 to one of the four PIN Interrupts IRQ_PINTx.
332
333 You shouldn't change any of these unless you know exactly what you're doing.
334 Please consult the Blackfin BF54x Processor Hardware Reference Manual.
335
336config PINT0_ASSIGN
337 hex "PINT0_ASSIGN"
338 depends on PINTx_REASSIGN
339 default 0x00000101
340config PINT1_ASSIGN
341 hex "PINT1_ASSIGN"
342 depends on PINTx_REASSIGN
343 default 0x01010000
344config PINT2_ASSIGN
345 hex "PINT2_ASSIGN"
346 depends on PINTx_REASSIGN
Michael Hennerich31430ba2007-07-24 16:27:25 +0800[diff] [blame]347 default 0x07000101
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]348config PINT3_ASSIGN
349 hex "PINT3_ASSIGN"
350 depends on PINTx_REASSIGN
351 default 0x02020303
352
353endmenu
354
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]355endmenu
356
357endif