blob: 8839307a64cf52d14301f7a52b3af99ad565c4d6 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov265b7212009-04-14 18:39:14 +040011 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 * TODO
Sergei Shtylyovd44a65f2007-08-10 20:58:46 +040014 * Look into engine reset on timeout errors. Should not be required.
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/blkdev.h>
22#include <linux/delay.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25
26#define DRV_NAME "pata_hpt37x"
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +040027#define DRV_VERSION "0.6.15"
Jeff Garzik669a5db2006-08-29 18:12:40 -040028
29struct hpt_clock {
30 u8 xfer_speed;
31 u32 timing;
32};
33
34struct hpt_chip {
35 const char *name;
36 unsigned int base;
37 struct hpt_clock const *clocks[4];
38};
39
40/* key for bus clock timings
41 * bit
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040042 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
43 * cycles = value + 1
44 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
45 * cycles = value + 1
46 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040047 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040048 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040049 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040050 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
51 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
52 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
53 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040054 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040055 * 28 UDMA enable.
56 * 29 DMA enable.
57 * 30 PIO_MST enable. If set, the chip is in bus master mode during
58 * PIO xfer.
59 * 31 FIFO enable. Only for PIO.
Jeff Garzik669a5db2006-08-29 18:12:40 -040060 */
61
Alan Coxfcc2f692007-03-08 23:28:52 +000062static struct hpt_clock hpt37x_timings_33[] = {
63 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
64 { XFER_UDMA_5, 0x12446231 },
65 { XFER_UDMA_4, 0x12446231 },
66 { XFER_UDMA_3, 0x126c6231 },
67 { XFER_UDMA_2, 0x12486231 },
68 { XFER_UDMA_1, 0x124c6233 },
69 { XFER_UDMA_0, 0x12506297 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040070
Alan Coxfcc2f692007-03-08 23:28:52 +000071 { XFER_MW_DMA_2, 0x22406c31 },
72 { XFER_MW_DMA_1, 0x22406c33 },
73 { XFER_MW_DMA_0, 0x22406c97 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040074
Alan Coxfcc2f692007-03-08 23:28:52 +000075 { XFER_PIO_4, 0x06414e31 },
76 { XFER_PIO_3, 0x06414e42 },
77 { XFER_PIO_2, 0x06414e53 },
78 { XFER_PIO_1, 0x06814e93 },
79 { XFER_PIO_0, 0x06814ea7 }
Jeff Garzik669a5db2006-08-29 18:12:40 -040080};
81
Alan Coxfcc2f692007-03-08 23:28:52 +000082static struct hpt_clock hpt37x_timings_50[] = {
83 { XFER_UDMA_6, 0x12848242 },
84 { XFER_UDMA_5, 0x12848242 },
85 { XFER_UDMA_4, 0x12ac8242 },
86 { XFER_UDMA_3, 0x128c8242 },
87 { XFER_UDMA_2, 0x120c8242 },
88 { XFER_UDMA_1, 0x12148254 },
89 { XFER_UDMA_0, 0x121882ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040090
Alan Coxfcc2f692007-03-08 23:28:52 +000091 { XFER_MW_DMA_2, 0x22808242 },
92 { XFER_MW_DMA_1, 0x22808254 },
93 { XFER_MW_DMA_0, 0x228082ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040094
Alan Coxfcc2f692007-03-08 23:28:52 +000095 { XFER_PIO_4, 0x0a81f442 },
96 { XFER_PIO_3, 0x0a81f443 },
97 { XFER_PIO_2, 0x0a81f454 },
98 { XFER_PIO_1, 0x0ac1f465 },
99 { XFER_PIO_0, 0x0ac1f48a }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400100};
101
Alan Coxfcc2f692007-03-08 23:28:52 +0000102static struct hpt_clock hpt37x_timings_66[] = {
103 { XFER_UDMA_6, 0x1c869c62 },
104 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
105 { XFER_UDMA_4, 0x1c8a9c62 },
106 { XFER_UDMA_3, 0x1c8e9c62 },
107 { XFER_UDMA_2, 0x1c929c62 },
108 { XFER_UDMA_1, 0x1c9a9c62 },
109 { XFER_UDMA_0, 0x1c829c62 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400110
Alan Coxfcc2f692007-03-08 23:28:52 +0000111 { XFER_MW_DMA_2, 0x2c829c62 },
112 { XFER_MW_DMA_1, 0x2c829c66 },
113 { XFER_MW_DMA_0, 0x2c829d2e },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400114
Alan Coxfcc2f692007-03-08 23:28:52 +0000115 { XFER_PIO_4, 0x0c829c62 },
116 { XFER_PIO_3, 0x0c829c84 },
117 { XFER_PIO_2, 0x0c829ca6 },
118 { XFER_PIO_1, 0x0d029d26 },
119 { XFER_PIO_0, 0x0d029d5e }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400120};
121
Jeff Garzik669a5db2006-08-29 18:12:40 -0400122
123static const struct hpt_chip hpt370 = {
124 "HPT370",
125 48,
126 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000127 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400128 NULL,
129 NULL,
Alan Coxa4734462007-04-26 00:19:25 -0700130 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400131 }
132};
133
134static const struct hpt_chip hpt370a = {
135 "HPT370A",
136 48,
137 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000138 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400139 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000140 hpt37x_timings_50,
Alan Coxa4734462007-04-26 00:19:25 -0700141 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400142 }
143};
144
145static const struct hpt_chip hpt372 = {
146 "HPT372",
147 55,
148 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000149 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400150 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000151 hpt37x_timings_50,
152 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400153 }
154};
155
156static const struct hpt_chip hpt302 = {
157 "HPT302",
158 66,
159 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000160 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400161 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000162 hpt37x_timings_50,
163 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400164 }
165};
166
167static const struct hpt_chip hpt371 = {
168 "HPT371",
169 66,
170 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000171 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400172 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000173 hpt37x_timings_50,
174 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400175 }
176};
177
178static const struct hpt_chip hpt372a = {
179 "HPT372A",
180 66,
181 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000182 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400183 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000184 hpt37x_timings_50,
185 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186 }
187};
188
189static const struct hpt_chip hpt374 = {
190 "HPT374",
191 48,
192 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000193 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400194 NULL,
195 NULL,
196 NULL
197 }
198};
199
200/**
201 * hpt37x_find_mode - reset the hpt37x bus
202 * @ap: ATA port
203 * @speed: transfer mode
204 *
205 * Return the 32bit register programming information for this channel
206 * that matches the speed provided.
207 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400208
Jeff Garzik669a5db2006-08-29 18:12:40 -0400209static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
210{
211 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400212
Jeff Garzik669a5db2006-08-29 18:12:40 -0400213 while(clocks->xfer_speed) {
214 if (clocks->xfer_speed == speed)
215 return clocks->timing;
216 clocks++;
217 }
218 BUG();
219 return 0xffffffffU; /* silence compiler warning */
220}
221
222static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
223{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900224 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400225 int i = 0;
226
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900227 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400228
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900229 while (list[i] != NULL) {
230 if (!strcmp(list[i], model_num)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400231 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400232 modestr, list[i]);
233 return 1;
234 }
235 i++;
236 }
237 return 0;
238}
239
240static const char *bad_ata33[] = {
241 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
242 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
243 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
244 "Maxtor 90510D4",
245 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
246 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
247 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
248 NULL
249};
250
251static const char *bad_ata100_5[] = {
252 "IBM-DTLA-307075",
253 "IBM-DTLA-307060",
254 "IBM-DTLA-307045",
255 "IBM-DTLA-307030",
256 "IBM-DTLA-307020",
257 "IBM-DTLA-307015",
258 "IBM-DTLA-305040",
259 "IBM-DTLA-305030",
260 "IBM-DTLA-305020",
261 "IC35L010AVER07-0",
262 "IC35L020AVER07-0",
263 "IC35L030AVER07-0",
264 "IC35L040AVER07-0",
265 "IC35L060AVER07-0",
266 "WDC AC310200R",
267 NULL
268};
269
270/**
271 * hpt370_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400272 * @adev: ATA device
273 *
274 * Block UDMA on devices that cause trouble with this controller.
275 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400276
Alan Coxa76b62c2007-03-09 09:34:07 -0500277static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400278{
Alan6929da42007-01-05 16:37:01 -0800279 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400280 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
281 mask &= ~ATA_MASK_UDMA;
282 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800283 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400284 }
Tejun Heo9363c382008-04-07 22:47:16 +0900285 return ata_bmdma_mode_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400286}
287
288/**
289 * hpt370a_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400290 * @adev: ATA device
291 *
292 * Block UDMA on devices that cause trouble with this controller.
293 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400294
Alan Coxa76b62c2007-03-09 09:34:07 -0500295static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400296{
Alan Cox73946f92007-11-05 22:53:38 +0000297 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400298 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800299 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400300 }
Tejun Heo9363c382008-04-07 22:47:16 +0900301 return ata_bmdma_mode_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400302}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400303
Jeff Garzik669a5db2006-08-29 18:12:40 -0400304/**
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100305 * hpt37x_cable_detect - Detect the cable type
306 * @ap: ATA port to detect on
Jeff Garzik669a5db2006-08-29 18:12:40 -0400307 *
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100308 * Return the cable type attached to this port
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400310
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100311static int hpt37x_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400312{
Jeff Garzik669a5db2006-08-29 18:12:40 -0400313 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100314 u8 scr2, ata66;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500315
Jeff Garzik669a5db2006-08-29 18:12:40 -0400316 pci_read_config_byte(pdev, 0x5B, &scr2);
317 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
Bartlomiej Zolnierkiewicz10a9c962009-11-19 20:31:31 +0100318
319 udelay(10); /* debounce */
320
Jeff Garzik669a5db2006-08-29 18:12:40 -0400321 /* Cable register now active */
322 pci_read_config_byte(pdev, 0x5A, &ata66);
323 /* Restore state */
324 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400325
Alan Cox22d5c762007-11-19 14:39:13 +0000326 if (ata66 & (2 >> ap->port_no))
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100327 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400328 else
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100329 return ATA_CBL_PATA80;
330}
331
332/**
333 * hpt374_fn1_cable_detect - Detect the cable type
334 * @ap: ATA port to detect on
335 *
336 * Return the cable type attached to this port
337 */
338
339static int hpt374_fn1_cable_detect(struct ata_port *ap)
340{
341 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
342 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
343 u16 mcr3;
344 u8 ata66;
345
346 /* Do the extra channel work */
347 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
348 /* Set bit 15 of 0x52 to enable TCBLID as input */
349 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
350 pci_read_config_byte(pdev, 0x5A, &ata66);
351 /* Reset TCBLID/FCBLID to output */
352 pci_write_config_word(pdev, mcrbase + 2, mcr3);
353
354 if (ata66 & (2 >> ap->port_no))
355 return ATA_CBL_PATA40;
356 else
357 return ATA_CBL_PATA80;
358}
359
360/**
361 * hpt37x_pre_reset - reset the hpt37x bus
362 * @link: ATA link to reset
363 * @deadline: deadline jiffies for the operation
364 *
Bartlomiej Zolnierkiewiczab81a502009-11-19 19:12:24 +0100365 * Perform the initial reset handling for the HPT37x.
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100366 */
367
368static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
369{
370 struct ata_port *ap = link->ap;
371 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
372 static const struct pci_bits hpt37x_enable_bits[] = {
373 { 0x50, 1, 0x04, 0x04 },
374 { 0x54, 1, 0x04, 0x04 }
375 };
376 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
377 return -ENOENT;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400378
379 /* Reset the state machine */
Alan Coxfcc2f692007-03-08 23:28:52 +0000380 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400381 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400382
Tejun Heo9363c382008-04-07 22:47:16 +0900383 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400384}
385
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400386static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
387 u8 mode)
388{
389 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
390 u32 addr1, addr2;
391 u32 reg, timing, mask;
392 u8 fast;
393
394 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
395 addr2 = 0x51 + 4 * ap->port_no;
396
397 /* Fast interrupt prediction disable, hold off interrupt disable */
398 pci_read_config_byte(pdev, addr2, &fast);
399 fast &= ~0x02;
400 fast |= 0x01;
401 pci_write_config_byte(pdev, addr2, fast);
402
403 /* Determine timing mask and find matching mode entry */
404 if (mode < XFER_MW_DMA_0)
405 mask = 0xcfc3ffff;
406 else if (mode < XFER_UDMA_0)
407 mask = 0x31c001ff;
408 else
409 mask = 0x303c0000;
410
411 timing = hpt37x_find_mode(ap, mode);
412
413 pci_read_config_dword(pdev, addr1, &reg);
414 reg = (reg & ~mask) | (timing & mask);
415 pci_write_config_dword(pdev, addr1, reg);
416}
Jeff Garzik669a5db2006-08-29 18:12:40 -0400417/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400418 * hpt370_set_piomode - PIO setup
419 * @ap: ATA interface
420 * @adev: device on the interface
421 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400422 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400423 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400424
Jeff Garzik669a5db2006-08-29 18:12:40 -0400425static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
426{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400427 hpt370_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400428}
429
430/**
431 * hpt370_set_dmamode - DMA timing setup
432 * @ap: ATA interface
433 * @adev: Device being configured
434 *
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400435 * Set up the channel for MWDMA or UDMA modes.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400436 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400437
Jeff Garzik669a5db2006-08-29 18:12:40 -0400438static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
439{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400440 hpt370_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400441}
442
443/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400444 * hpt370_bmdma_end - DMA engine stop
445 * @qc: ATA command
446 *
447 * Work around the HPT370 DMA engine.
448 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400449
Jeff Garzik669a5db2006-08-29 18:12:40 -0400450static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
451{
452 struct ata_port *ap = qc->ap;
453 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900454 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400455 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
456 u8 dma_cmd;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400457
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400458 if (dma_stat & ATA_DMA_ACTIVE) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400459 udelay(20);
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400460 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400461 }
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400462 if (dma_stat & ATA_DMA_ACTIVE) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400463 /* Clear the engine */
464 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
465 udelay(10);
466 /* Stop DMA */
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400467 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
468 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400469 /* Clear Error */
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400470 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
471 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
472 bmdma + ATA_DMA_STATUS);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400473 /* Clear the engine */
474 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
475 udelay(10);
476 }
477 ata_bmdma_stop(qc);
478}
479
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400480static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
481 u8 mode)
482{
483 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
484 u32 addr1, addr2;
485 u32 reg, timing, mask;
486 u8 fast;
487
488 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
489 addr2 = 0x51 + 4 * ap->port_no;
490
491 /* Fast interrupt prediction disable, hold off interrupt disable */
492 pci_read_config_byte(pdev, addr2, &fast);
493 fast &= ~0x07;
494 pci_write_config_byte(pdev, addr2, fast);
495
496 /* Determine timing mask and find matching mode entry */
497 if (mode < XFER_MW_DMA_0)
498 mask = 0xcfc3ffff;
499 else if (mode < XFER_UDMA_0)
500 mask = 0x31c001ff;
501 else
502 mask = 0x303c0000;
503
504 timing = hpt37x_find_mode(ap, mode);
505
506 pci_read_config_dword(pdev, addr1, &reg);
507 reg = (reg & ~mask) | (timing & mask);
508 pci_write_config_dword(pdev, addr1, reg);
509}
510
Jeff Garzik669a5db2006-08-29 18:12:40 -0400511/**
512 * hpt372_set_piomode - PIO setup
513 * @ap: ATA interface
514 * @adev: device on the interface
515 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400516 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400517 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400518
Jeff Garzik669a5db2006-08-29 18:12:40 -0400519static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
520{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400521 hpt372_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400522}
523
524/**
525 * hpt372_set_dmamode - DMA timing setup
526 * @ap: ATA interface
527 * @adev: Device being configured
528 *
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400529 * Set up the channel for MWDMA or UDMA modes.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400530 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400531
Jeff Garzik669a5db2006-08-29 18:12:40 -0400532static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
533{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400534 hpt372_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400535}
536
537/**
538 * hpt37x_bmdma_end - DMA engine stop
539 * @qc: ATA command
540 *
541 * Clean up after the HPT372 and later DMA engine
542 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400543
Jeff Garzik669a5db2006-08-29 18:12:40 -0400544static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
545{
546 struct ata_port *ap = qc->ap;
547 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan6929da42007-01-05 16:37:01 -0800548 int mscreg = 0x50 + 4 * ap->port_no;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400549 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400550
Jeff Garzik669a5db2006-08-29 18:12:40 -0400551 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
552 pci_read_config_byte(pdev, mscreg, &msc_stat);
553 if (bwsr_stat & (1 << ap->port_no))
554 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
555 ata_bmdma_stop(qc);
556}
557
558
559static struct scsi_host_template hpt37x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900560 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400561};
562
563/*
564 * Configuration for HPT370
565 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400566
Jeff Garzik669a5db2006-08-29 18:12:40 -0400567static struct ata_port_operations hpt370_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900568 .inherits = &ata_bmdma_port_ops,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400569
Jeff Garzik669a5db2006-08-29 18:12:40 -0400570 .bmdma_stop = hpt370_bmdma_stop,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400571
Tejun Heo029cfd62008-03-25 12:22:49 +0900572 .mode_filter = hpt370_filter,
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100573 .cable_detect = hpt37x_cable_detect,
Tejun Heo029cfd62008-03-25 12:22:49 +0900574 .set_piomode = hpt370_set_piomode,
575 .set_dmamode = hpt370_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900576 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400577};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400578
579/*
580 * Configuration for HPT370A. Close to 370 but less filters
581 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400582
Jeff Garzik669a5db2006-08-29 18:12:40 -0400583static struct ata_port_operations hpt370a_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900584 .inherits = &hpt370_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400585 .mode_filter = hpt370a_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400586};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400587
588/*
589 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
590 * and DMA mode setting functionality.
591 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400592
Jeff Garzik669a5db2006-08-29 18:12:40 -0400593static struct ata_port_operations hpt372_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900594 .inherits = &ata_bmdma_port_ops,
595
596 .bmdma_stop = hpt37x_bmdma_stop,
597
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100598 .cable_detect = hpt37x_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400599 .set_piomode = hpt372_set_piomode,
600 .set_dmamode = hpt372_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900601 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400602};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400603
604/*
605 * Configuration for HPT374. Mode setting works like 372 and friends
Tejun Heoa1efdab2008-03-25 12:22:50 +0900606 * but we have a different cable detection procedure for function 1.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400607 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400608
Tejun Heoa1efdab2008-03-25 12:22:50 +0900609static struct ata_port_operations hpt374_fn1_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900610 .inherits = &hpt372_port_ops,
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100611 .cable_detect = hpt374_fn1_cable_detect,
Bartlomiej Zolnierkiewiczab81a502009-11-19 19:12:24 +0100612 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400613};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400614
615/**
Krzysztof Halasaad452d62009-09-20 16:22:51 +0200616 * hpt37x_clock_slot - Turn timing to PC clock entry
Jeff Garzik669a5db2006-08-29 18:12:40 -0400617 * @freq: Reported frequency timing
618 * @base: Base timing
619 *
620 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
621 * and 3 for 66Mhz)
622 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400623
Jeff Garzik669a5db2006-08-29 18:12:40 -0400624static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
625{
626 unsigned int f = (base * freq) / 192; /* Mhz */
627 if (f < 40)
628 return 0; /* 33Mhz slot */
629 if (f < 45)
630 return 1; /* 40Mhz slot */
631 if (f < 55)
632 return 2; /* 50Mhz slot */
633 return 3; /* 60Mhz slot */
634}
635
636/**
637 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400638 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400639 *
640 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
641 * succeeds
642 */
643
644static int hpt37x_calibrate_dpll(struct pci_dev *dev)
645{
646 u8 reg5b;
647 u32 reg5c;
648 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400649
Jeff Garzik669a5db2006-08-29 18:12:40 -0400650 for(tries = 0; tries < 0x5000; tries++) {
651 udelay(50);
652 pci_read_config_byte(dev, 0x5b, &reg5b);
653 if (reg5b & 0x80) {
654 /* See if it stays set */
655 for(tries = 0; tries < 0x1000; tries ++) {
656 pci_read_config_byte(dev, 0x5b, &reg5b);
657 /* Failed ? */
658 if ((reg5b & 0x80) == 0)
659 return 0;
660 }
661 /* Turn off tuning, we have the DPLL set */
662 pci_read_config_dword(dev, 0x5c, &reg5c);
663 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
664 return 1;
665 }
666 }
667 /* Never went stable */
668 return 0;
669}
Alan Cox73946f92007-11-05 22:53:38 +0000670
671static u32 hpt374_read_freq(struct pci_dev *pdev)
672{
673 u32 freq;
674 unsigned long io_base = pci_resource_start(pdev, 4);
675 if (PCI_FUNC(pdev->devfn) & 1) {
Andrew Morton40f46f12007-12-13 16:01:38 -0800676 struct pci_dev *pdev_0;
677
678 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
Alan Cox73946f92007-11-05 22:53:38 +0000679 /* Someone hot plugged the controller on us ? */
680 if (pdev_0 == NULL)
681 return 0;
682 io_base = pci_resource_start(pdev_0, 4);
683 freq = inl(io_base + 0x90);
684 pci_dev_put(pdev_0);
Andrew Morton40f46f12007-12-13 16:01:38 -0800685 } else
Alan Cox73946f92007-11-05 22:53:38 +0000686 freq = inl(io_base + 0x90);
687 return freq;
688}
689
Jeff Garzik669a5db2006-08-29 18:12:40 -0400690/**
691 * hpt37x_init_one - Initialise an HPT37X/302
692 * @dev: PCI device
693 * @id: Entry in match table
694 *
695 * Initialise an HPT37x device. There are some interesting complications
696 * here. Firstly the chip may report 366 and be one of several variants.
697 * Secondly all the timings depend on the clock for the chip which we must
698 * detect and look up
699 *
700 * This is the known chip mappings. It may be missing a couple of later
701 * releases.
702 *
703 * Chip version PCI Rev Notes
704 * HPT366 4 (HPT366) 0 Other driver
705 * HPT366 4 (HPT366) 1 Other driver
706 * HPT368 4 (HPT366) 2 Other driver
707 * HPT370 4 (HPT366) 3 UDMA100
708 * HPT370A 4 (HPT366) 4 UDMA100
709 * HPT372 4 (HPT366) 5 UDMA133 (1)
710 * HPT372N 4 (HPT366) 6 Other driver
711 * HPT372A 5 (HPT372) 1 UDMA133 (1)
712 * HPT372N 5 (HPT372) 2 Other driver
713 * HPT302 6 (HPT302) 1 UDMA133
714 * HPT302N 6 (HPT302) 2 Other driver
715 * HPT371 7 (HPT371) * UDMA133
716 * HPT374 8 (HPT374) * UDMA133 4 channel
717 * HPT372N 9 (HPT372N) * Other driver
718 *
719 * (1) UDMA133 support depends on the bus clock
720 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400721
Jeff Garzik669a5db2006-08-29 18:12:40 -0400722static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
723{
724 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200725 static const struct ata_port_info info_hpt370 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400726 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100727 .pio_mask = ATA_PIO4,
728 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400729 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400730 .port_ops = &hpt370_port_ops
731 };
732 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200733 static const struct ata_port_info info_hpt370a = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400734 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100735 .pio_mask = ATA_PIO4,
736 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400737 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400738 .port_ops = &hpt370a_port_ops
739 };
Alan Coxfcc2f692007-03-08 23:28:52 +0000740 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200741 static const struct ata_port_info info_hpt370_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400742 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100743 .pio_mask = ATA_PIO4,
744 .mwdma_mask = ATA_MWDMA2,
Alan Cox73946f92007-11-05 22:53:38 +0000745 .udma_mask = ATA_UDMA5,
Alan Coxfcc2f692007-03-08 23:28:52 +0000746 .port_ops = &hpt370_port_ops
747 };
748 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200749 static const struct ata_port_info info_hpt370a_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400750 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100751 .pio_mask = ATA_PIO4,
752 .mwdma_mask = ATA_MWDMA2,
Alan Cox73946f92007-11-05 22:53:38 +0000753 .udma_mask = ATA_UDMA5,
Alan Coxfcc2f692007-03-08 23:28:52 +0000754 .port_ops = &hpt370a_port_ops
755 };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400756 /* HPT371, 372 and friends - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200757 static const struct ata_port_info info_hpt372 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400758 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100759 .pio_mask = ATA_PIO4,
760 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400761 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400762 .port_ops = &hpt372_port_ops
763 };
Tejun Heoa1efdab2008-03-25 12:22:50 +0900764 /* HPT374 - UDMA100, function 1 uses different prereset method */
765 static const struct ata_port_info info_hpt374_fn0 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400766 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100767 .pio_mask = ATA_PIO4,
768 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400769 .udma_mask = ATA_UDMA5,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900770 .port_ops = &hpt372_port_ops
771 };
772 static const struct ata_port_info info_hpt374_fn1 = {
773 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100774 .pio_mask = ATA_PIO4,
775 .mwdma_mask = ATA_MWDMA2,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900776 .udma_mask = ATA_UDMA5,
777 .port_ops = &hpt374_fn1_port_ops
Jeff Garzik669a5db2006-08-29 18:12:40 -0400778 };
779
780 static const int MHz[4] = { 33, 40, 50, 66 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200781 void *private_data = NULL;
Tejun Heo887125e2008-03-25 12:22:49 +0900782 const struct ata_port_info *ppi[] = { NULL, NULL };
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400783 u8 rev = dev->revision;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400784 u8 irqmask;
Alan Coxfcc2f692007-03-08 23:28:52 +0000785 u8 mcr1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400786 u32 freq;
Alan Coxfcc2f692007-03-08 23:28:52 +0000787 int prefer_dpll = 1;
Jeff Garzika617c092007-05-21 20:14:23 -0400788
Alan Coxfcc2f692007-03-08 23:28:52 +0000789 unsigned long iobase = pci_resource_start(dev, 4);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400790
791 const struct hpt_chip *chip_table;
792 int clock_slot;
Tejun Heof08048e2008-03-25 12:22:47 +0900793 int rc;
794
795 rc = pcim_enable_device(dev);
796 if (rc)
797 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400798
Jeff Garzik669a5db2006-08-29 18:12:40 -0400799 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
800 /* May be a later chip in disguise. Check */
801 /* Older chips are in the HPT366 driver. Ignore them */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400802 if (rev < 3)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400803 return -ENODEV;
804 /* N series chips have their own driver. Ignore */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400805 if (rev == 6)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400806 return -ENODEV;
807
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400808 switch(rev) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400809 case 3:
Tejun Heo887125e2008-03-25 12:22:49 +0900810 ppi[0] = &info_hpt370;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400811 chip_table = &hpt370;
Alan Coxfcc2f692007-03-08 23:28:52 +0000812 prefer_dpll = 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400813 break;
814 case 4:
Tejun Heo887125e2008-03-25 12:22:49 +0900815 ppi[0] = &info_hpt370a;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400816 chip_table = &hpt370a;
Alan Coxfcc2f692007-03-08 23:28:52 +0000817 prefer_dpll = 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400818 break;
819 case 5:
Tejun Heo887125e2008-03-25 12:22:49 +0900820 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400821 chip_table = &hpt372;
822 break;
823 default:
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400824 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 "
825 "subtype, please report (%d).\n", rev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400826 return -ENODEV;
827 }
828 } else {
829 switch(dev->device) {
830 case PCI_DEVICE_ID_TTI_HPT372:
831 /* 372N if rev >= 2*/
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400832 if (rev >= 2)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400833 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900834 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400835 chip_table = &hpt372a;
836 break;
837 case PCI_DEVICE_ID_TTI_HPT302:
838 /* 302N if rev > 1 */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400839 if (rev > 1)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400840 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900841 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400842 /* Check this */
843 chip_table = &hpt302;
844 break;
845 case PCI_DEVICE_ID_TTI_HPT371:
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400846 if (rev > 1)
Alan Coxfcc2f692007-03-08 23:28:52 +0000847 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900848 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400849 chip_table = &hpt371;
Alan Coxa4734462007-04-26 00:19:25 -0700850 /* Single channel device, master is not present
851 but the BIOS (or us for non x86) must mark it
Alan Coxfcc2f692007-03-08 23:28:52 +0000852 absent */
853 pci_read_config_byte(dev, 0x50, &mcr1);
854 mcr1 &= ~0x04;
855 pci_write_config_byte(dev, 0x50, mcr1);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400856 break;
857 case PCI_DEVICE_ID_TTI_HPT374:
858 chip_table = &hpt374;
Tejun Heoa1efdab2008-03-25 12:22:50 +0900859 if (!(PCI_FUNC(dev->devfn) & 1))
860 *ppi = &info_hpt374_fn0;
861 else
862 *ppi = &info_hpt374_fn1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400863 break;
864 default:
865 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
866 return -ENODEV;
867 }
868 }
869 /* Ok so this is a chip we support */
870
871 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
872 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
873 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
874 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
875
876 pci_read_config_byte(dev, 0x5A, &irqmask);
877 irqmask &= ~0x10;
878 pci_write_config_byte(dev, 0x5a, irqmask);
879
880 /*
881 * default to pci clock. make sure MA15/16 are set to output
882 * to prevent drives having problems with 40-pin cables. Needed
883 * for some drives such as IBM-DTLA which will not enter ready
884 * state on reset when PDIAG is a input.
885 */
886
Jeff Garzik85cd7252006-08-31 00:03:49 -0400887 pci_write_config_byte(dev, 0x5b, 0x23);
Jeff Garzika617c092007-05-21 20:14:23 -0400888
Alan Coxfcc2f692007-03-08 23:28:52 +0000889 /*
890 * HighPoint does this for HPT372A.
891 * NOTE: This register is only writeable via I/O space.
892 */
893 if (chip_table == &hpt372a)
894 outb(0x0e, iobase + 0x9c);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400895
Alan Coxfcc2f692007-03-08 23:28:52 +0000896 /* Some devices do not let this value be accessed via PCI space
Alan Cox73946f92007-11-05 22:53:38 +0000897 according to the old driver. In addition we must use the value
898 from FN 0 on the HPT374 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000899
Alan Cox73946f92007-11-05 22:53:38 +0000900 if (chip_table == &hpt374) {
901 freq = hpt374_read_freq(dev);
902 if (freq == 0)
903 return -ENODEV;
904 } else
905 freq = inl(iobase + 0x90);
906
Jeff Garzik669a5db2006-08-29 18:12:40 -0400907 if ((freq >> 12) != 0xABCDE) {
908 int i;
909 u8 sr;
910 u32 total = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400911
Jeff Garzik669a5db2006-08-29 18:12:40 -0400912 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
Jeff Garzik85cd7252006-08-31 00:03:49 -0400913
Jeff Garzik669a5db2006-08-29 18:12:40 -0400914 /* This is the process the HPT371 BIOS is reported to use */
915 for(i = 0; i < 128; i++) {
916 pci_read_config_byte(dev, 0x78, &sr);
Alan Coxfcc2f692007-03-08 23:28:52 +0000917 total += sr & 0x1FF;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400918 udelay(15);
919 }
920 freq = total / 128;
921 }
922 freq &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400923
Jeff Garzik669a5db2006-08-29 18:12:40 -0400924 /*
925 * Turn the frequency check into a band and then find a timing
926 * table to match it.
927 */
Jeff Garzika617c092007-05-21 20:14:23 -0400928
Jeff Garzik669a5db2006-08-29 18:12:40 -0400929 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
Alan Coxfcc2f692007-03-08 23:28:52 +0000930 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400931 /*
932 * We need to try PLL mode instead
Alan Coxfcc2f692007-03-08 23:28:52 +0000933 *
934 * For non UDMA133 capable devices we should
935 * use a 50MHz DPLL by choice
Jeff Garzik669a5db2006-08-29 18:12:40 -0400936 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000937 unsigned int f_low, f_high;
Alan Cox960c8a12007-05-25 20:48:55 +0100938 int dpll, adjust;
Jeff Garzika617c092007-05-21 20:14:23 -0400939
Alan Cox960c8a12007-05-25 20:48:55 +0100940 /* Compute DPLL */
Tejun Heo887125e2008-03-25 12:22:49 +0900941 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
Jeff Garzika617c092007-05-21 20:14:23 -0400942
Alan Cox960c8a12007-05-25 20:48:55 +0100943 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
Alan Coxfcc2f692007-03-08 23:28:52 +0000944 f_high = f_low + 2;
Alan Cox960c8a12007-05-25 20:48:55 +0100945 if (clock_slot > 1)
946 f_high += 2;
Alan Coxfcc2f692007-03-08 23:28:52 +0000947
948 /* Select the DPLL clock. */
949 pci_write_config_byte(dev, 0x5b, 0x21);
Alan Cox64a81702007-07-24 15:17:48 +0100950 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400951
Jeff Garzik669a5db2006-08-29 18:12:40 -0400952 for(adjust = 0; adjust < 8; adjust++) {
953 if (hpt37x_calibrate_dpll(dev))
954 break;
955 /* See if it'll settle at a fractionally different clock */
Alan Cox64a81702007-07-24 15:17:48 +0100956 if (adjust & 1)
957 f_low -= adjust >> 1;
958 else
959 f_high += adjust >> 1;
960 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400961 }
962 if (adjust == 8) {
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400963 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
Jeff Garzik669a5db2006-08-29 18:12:40 -0400964 return -ENODEV;
965 }
Alan Cox960c8a12007-05-25 20:48:55 +0100966 if (dpll == 3)
Tejun Heo1626aeb2007-05-04 12:43:58 +0200967 private_data = (void *)hpt37x_timings_66;
Alan Coxfcc2f692007-03-08 23:28:52 +0000968 else
Tejun Heo1626aeb2007-05-04 12:43:58 +0200969 private_data = (void *)hpt37x_timings_50;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400970
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400971 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
972 MHz[clock_slot], MHz[dpll]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400973 } else {
Tejun Heo1626aeb2007-05-04 12:43:58 +0200974 private_data = (void *)chip_table->clocks[clock_slot];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400975 /*
Alan Coxa4734462007-04-26 00:19:25 -0700976 * Perform a final fixup. Note that we will have used the
977 * DPLL on the HPT372 which means we don't have to worry
978 * about lack of UDMA133 support on lower clocks
979 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400980
Tejun Heo887125e2008-03-25 12:22:49 +0900981 if (clock_slot < 2 && ppi[0] == &info_hpt370)
982 ppi[0] = &info_hpt370_33;
983 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
984 ppi[0] = &info_hpt370a_33;
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400985 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
986 chip_table->name, MHz[clock_slot]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400987 }
Alan Coxfcc2f692007-03-08 23:28:52 +0000988
Jeff Garzik669a5db2006-08-29 18:12:40 -0400989 /* Now kick off ATA set up */
Alan Cox16ea0fc2010-02-23 02:26:06 -0500990 return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400991}
992
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400993static const struct pci_device_id hpt37x[] = {
994 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
995 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
996 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
997 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
998 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
999
1000 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -04001001};
1002
1003static struct pci_driver hpt37x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001004 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -04001005 .id_table = hpt37x,
1006 .probe = hpt37x_init_one,
1007 .remove = ata_pci_remove_one
1008};
1009
1010static int __init hpt37x_init(void)
1011{
1012 return pci_register_driver(&hpt37x_pci_driver);
1013}
1014
Jeff Garzik669a5db2006-08-29 18:12:40 -04001015static void __exit hpt37x_exit(void)
1016{
1017 pci_unregister_driver(&hpt37x_pci_driver);
1018}
1019
Jeff Garzik669a5db2006-08-29 18:12:40 -04001020MODULE_AUTHOR("Alan Cox");
1021MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1022MODULE_LICENSE("GPL");
1023MODULE_DEVICE_TABLE(pci, hpt37x);
1024MODULE_VERSION(DRV_VERSION);
1025
1026module_init(hpt37x_init);
1027module_exit(hpt37x_exit);