Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 2 | * ata_piix.c - Intel PATA/SATA controllers |
| 3 | * |
| 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
| 7 | * |
| 8 | * |
| 9 | * Copyright 2003-2005 Red Hat Inc |
| 10 | * Copyright 2003-2005 Jeff Garzik |
| 11 | * |
| 12 | * |
| 13 | * Copyright header from piix.c: |
| 14 | * |
| 15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
| 16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
| 17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> |
| 18 | * |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2, or (at your option) |
| 23 | * any later version. |
| 24 | * |
| 25 | * This program is distributed in the hope that it will be useful, |
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 28 | * GNU General Public License for more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License |
| 31 | * along with this program; see the file COPYING. If not, write to |
| 32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 33 | * |
| 34 | * |
| 35 | * libata documentation is available via 'make {ps|pdf}docs', |
| 36 | * as Documentation/DocBook/libata.* |
| 37 | * |
| 38 | * Hardware documentation available at http://developer.intel.com/ |
| 39 | * |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 40 | * Documentation |
| 41 | * Publically available from Intel web site. Errata documentation |
| 42 | * is also publically available. As an aide to anyone hacking on this |
Alan | 2c5ff67 | 2006-12-04 16:33:20 +0000 | [diff] [blame] | 43 | * driver the list of errata that are relevant is below, going back to |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 44 | * PIIX4. Older device documentation is now a bit tricky to find. |
| 45 | * |
| 46 | * The chipsets all follow very much the same design. The orginal Triton |
| 47 | * series chipsets do _not_ support independant device timings, but this |
| 48 | * is fixed in Triton II. With the odd mobile exception the chips then |
| 49 | * change little except in gaining more modes until SATA arrives. This |
| 50 | * driver supports only the chips with independant timing (that is those |
| 51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix |
| 52 | * for the early chip drivers. |
| 53 | * |
| 54 | * Errata of note: |
| 55 | * |
| 56 | * Unfixable |
| 57 | * PIIX4 errata #9 - Only on ultra obscure hw |
| 58 | * ICH3 errata #13 - Not observed to affect real hw |
| 59 | * by Intel |
| 60 | * |
| 61 | * Things we must deal with |
| 62 | * PIIX4 errata #10 - BM IDE hang with non UDMA |
| 63 | * (must stop/start dma to recover) |
| 64 | * 440MX errata #15 - As PIIX4 errata #10 |
| 65 | * PIIX4 errata #15 - Must not read control registers |
| 66 | * during a PIO transfer |
| 67 | * 440MX errata #13 - As PIIX4 errata #15 |
| 68 | * ICH2 errata #21 - DMA mode 0 doesn't work right |
| 69 | * ICH0/1 errata #55 - As ICH2 errata #21 |
| 70 | * ICH2 spec c #9 - Extra operations needed to handle |
| 71 | * drive hotswap [NOT YET SUPPORTED] |
| 72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary |
| 73 | * and must be dword aligned |
| 74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 |
| 75 | * |
| 76 | * Should have been BIOS fixed: |
| 77 | * 450NX: errata #19 - DMA hangs on old 450NX |
| 78 | * 450NX: errata #20 - DMA hangs on old 450NX |
| 79 | * 450NX: errata #25 - Corruption with DMA on old 450NX |
| 80 | * ICH3 errata #15 - IDE deadlock under high load |
| 81 | * (BIOS must set dev 31 fn 0 bit 23) |
| 82 | * ICH3 errata #18 - Don't use native mode |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | */ |
| 84 | |
| 85 | #include <linux/kernel.h> |
| 86 | #include <linux/module.h> |
| 87 | #include <linux/pci.h> |
| 88 | #include <linux/init.h> |
| 89 | #include <linux/blkdev.h> |
| 90 | #include <linux/delay.h> |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 91 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | #include <scsi/scsi_host.h> |
| 93 | #include <linux/libata.h> |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 94 | #include <linux/dmi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | |
| 96 | #define DRV_NAME "ata_piix" |
Jeff Garzik | 2a3103c | 2007-08-31 04:54:06 -0400 | [diff] [blame] | 97 | #define DRV_VERSION "2.12" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | |
| 99 | enum { |
| 100 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ |
| 101 | ICH5_PMR = 0x90, /* port mapping register */ |
| 102 | ICH5_PCS = 0x92, /* port control and status */ |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 103 | PIIX_SCC = 0x0A, /* sub-class code register */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | |
Tejun Heo | d435804 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 105 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 106 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
| 107 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | |
Tejun Heo | 800b399 | 2006-12-03 21:34:13 +0900 | [diff] [blame] | 109 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
| 110 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 111 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | /* combined mode. if set, PATA is channel 0. |
| 113 | * if clear, PATA is channel 1. |
| 114 | */ |
Hannes Reinecke | 6a690df | 2005-06-28 17:30:38 -0700 | [diff] [blame] | 115 | PIIX_PORT_ENABLED = (1 << 0), |
| 116 | PIIX_PORT_PRESENT = (1 << 4), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | |
| 118 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
| 119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), |
| 120 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 121 | /* controller IDs */ |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 122 | piix_pata_33 = 0, /* PIIX4 at 33Mhz */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 123 | ich_pata_33 = 1, /* ICH up to UDMA 33 only */ |
| 124 | ich_pata_66 = 2, /* ICH up to 66 Mhz */ |
| 125 | ich_pata_100 = 3, /* ICH up to UDMA 100 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 126 | ich5_sata = 5, |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 127 | ich6_sata = 6, |
| 128 | ich6_sata_ahci = 7, |
| 129 | ich6m_sata_ahci = 8, |
| 130 | ich8_sata_ahci = 9, |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 131 | piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 132 | tolapai_sata_ahci = 11, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 133 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 134 | /* constants for mapping table */ |
| 135 | P0 = 0, /* port 0 */ |
| 136 | P1 = 1, /* port 1 */ |
| 137 | P2 = 2, /* port 2 */ |
| 138 | P3 = 3, /* port 3 */ |
| 139 | IDE = -1, /* IDE */ |
| 140 | NA = -2, /* not avaliable */ |
| 141 | RV = -3, /* reserved */ |
| 142 | |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 143 | PIIX_AHCI_DEVICE = 6, |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 144 | |
| 145 | /* host->flags bits */ |
| 146 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | }; |
| 148 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 149 | struct piix_map_db { |
| 150 | const u32 mask; |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 151 | const u16 port_enable; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 152 | const int map[][4]; |
| 153 | }; |
| 154 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 155 | struct piix_host_priv { |
| 156 | const int *map; |
| 157 | }; |
| 158 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | static int piix_init_one (struct pci_dev *pdev, |
| 160 | const struct pci_device_id *ent); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 161 | static void piix_pata_error_handler(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
| 163 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 164 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 165 | static int ich_pata_cable_detect(struct ata_port *ap); |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 166 | #ifdef CONFIG_PM |
| 167 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
| 168 | static int piix_pci_device_resume(struct pci_dev *pdev); |
| 169 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | |
| 171 | static unsigned int in_module_init = 1; |
| 172 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 173 | static const struct pci_device_id piix_pci_tbl[] = { |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 174 | /* Intel PIIX3 for the 430HX etc */ |
| 175 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 176 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
| 177 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ |
| 178 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 179 | /* Intel PIIX4 */ |
| 180 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 181 | /* Intel PIIX4 */ |
| 182 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 183 | /* Intel PIIX */ |
| 184 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 185 | /* Intel ICH (i810, i815, i840) UDMA 66*/ |
| 186 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, |
| 187 | /* Intel ICH0 : UDMA 33*/ |
| 188 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, |
| 189 | /* Intel ICH2M */ |
| 190 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 191 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ |
| 192 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 193 | /* Intel ICH3M */ |
| 194 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 195 | /* Intel ICH3 (E7500/1) UDMA 100 */ |
| 196 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 197 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ |
| 198 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 199 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 200 | /* Intel ICH5 */ |
Christian Lamparter | 2eb829e | 2007-08-10 13:59:51 -0700 | [diff] [blame] | 201 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 202 | /* C-ICH (i810E2) */ |
| 203 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 204 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 205 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 206 | /* ICH6 (and 6) (i915) UDMA 100 */ |
| 207 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 208 | /* ICH7/7-R (i945, i975) UDMA 100*/ |
Christian Lamparter | 2eb829e | 2007-08-10 13:59:51 -0700 | [diff] [blame] | 209 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 210 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Christian Lamparter | c1e6f28 | 2007-07-03 10:19:20 -0400 | [diff] [blame] | 211 | /* ICH8 Mobile PATA Controller */ |
| 212 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | |
| 214 | /* NOTE: The following PCI ids must be kept in sync with the |
| 215 | * list in drivers/pci/quirks.c. |
| 216 | */ |
| 217 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 218 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 220 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 222 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 223 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 224 | /* 6300ESB pretending RAID */ |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 225 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 226 | /* 82801FB/FW (ICH6/ICH6W) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 228 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 229 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 230 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
| 231 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
| 232 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 233 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 234 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 235 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 236 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 237 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 238 | /* SATA Controller 1 IDE (ICH8) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 239 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 240 | /* SATA Controller 2 IDE (ICH8) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 241 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 242 | /* Mobile SATA Controller IDE (ICH8M) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 243 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 244 | /* SATA Controller IDE (ICH9) */ |
| 245 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 246 | /* SATA Controller IDE (ICH9) */ |
| 247 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 248 | /* SATA Controller IDE (ICH9) */ |
| 249 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 250 | /* SATA Controller IDE (ICH9M) */ |
| 251 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 252 | /* SATA Controller IDE (ICH9M) */ |
| 253 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 254 | /* SATA Controller IDE (ICH9M) */ |
| 255 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 256 | /* SATA Controller IDE (Tolapai) */ |
| 257 | { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | |
| 259 | { } /* terminate list */ |
| 260 | }; |
| 261 | |
| 262 | static struct pci_driver piix_pci_driver = { |
| 263 | .name = DRV_NAME, |
| 264 | .id_table = piix_pci_tbl, |
| 265 | .probe = piix_init_one, |
| 266 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 267 | #ifdef CONFIG_PM |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 268 | .suspend = piix_pci_device_suspend, |
| 269 | .resume = piix_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 270 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | }; |
| 272 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 273 | static struct scsi_host_template piix_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | .module = THIS_MODULE, |
| 275 | .name = DRV_NAME, |
| 276 | .ioctl = ata_scsi_ioctl, |
| 277 | .queuecommand = ata_scsi_queuecmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | .can_queue = ATA_DEF_QUEUE, |
| 279 | .this_id = ATA_SHT_THIS_ID, |
| 280 | .sg_tablesize = LIBATA_MAX_PRD, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 282 | .emulated = ATA_SHT_EMULATED, |
| 283 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 284 | .proc_name = DRV_NAME, |
| 285 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 286 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 287 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | }; |
| 290 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 291 | static const struct ata_port_operations piix_pata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | .set_piomode = piix_set_piomode, |
| 293 | .set_dmamode = piix_set_dmamode, |
Albert Lee | 89bad58 | 2006-05-26 13:49:18 +0800 | [diff] [blame] | 294 | .mode_filter = ata_pci_default_filter, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | |
| 296 | .tf_load = ata_tf_load, |
| 297 | .tf_read = ata_tf_read, |
| 298 | .check_status = ata_check_status, |
| 299 | .exec_command = ata_exec_command, |
| 300 | .dev_select = ata_std_dev_select, |
| 301 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 302 | .bmdma_setup = ata_bmdma_setup, |
| 303 | .bmdma_start = ata_bmdma_start, |
| 304 | .bmdma_stop = ata_bmdma_stop, |
| 305 | .bmdma_status = ata_bmdma_status, |
| 306 | .qc_prep = ata_qc_prep, |
| 307 | .qc_issue = ata_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 308 | .data_xfer = ata_data_xfer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 309 | |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 310 | .freeze = ata_bmdma_freeze, |
| 311 | .thaw = ata_bmdma_thaw, |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 312 | .error_handler = piix_pata_error_handler, |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 313 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 314 | .cable_detect = ata_cable_40wire, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | |
| 316 | .irq_handler = ata_interrupt, |
| 317 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 318 | .irq_on = ata_irq_on, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 319 | |
| 320 | .port_start = ata_port_start, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | }; |
| 322 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 323 | static const struct ata_port_operations ich_pata_ops = { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 324 | .set_piomode = piix_set_piomode, |
| 325 | .set_dmamode = ich_set_dmamode, |
| 326 | .mode_filter = ata_pci_default_filter, |
| 327 | |
| 328 | .tf_load = ata_tf_load, |
| 329 | .tf_read = ata_tf_read, |
| 330 | .check_status = ata_check_status, |
| 331 | .exec_command = ata_exec_command, |
| 332 | .dev_select = ata_std_dev_select, |
| 333 | |
| 334 | .bmdma_setup = ata_bmdma_setup, |
| 335 | .bmdma_start = ata_bmdma_start, |
| 336 | .bmdma_stop = ata_bmdma_stop, |
| 337 | .bmdma_status = ata_bmdma_status, |
| 338 | .qc_prep = ata_qc_prep, |
| 339 | .qc_issue = ata_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 340 | .data_xfer = ata_data_xfer, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 341 | |
| 342 | .freeze = ata_bmdma_freeze, |
| 343 | .thaw = ata_bmdma_thaw, |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 344 | .error_handler = piix_pata_error_handler, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 345 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 346 | .cable_detect = ich_pata_cable_detect, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 347 | |
| 348 | .irq_handler = ata_interrupt, |
| 349 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 350 | .irq_on = ata_irq_on, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 351 | |
| 352 | .port_start = ata_port_start, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 353 | }; |
| 354 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 355 | static const struct ata_port_operations piix_sata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | .tf_load = ata_tf_load, |
| 357 | .tf_read = ata_tf_read, |
| 358 | .check_status = ata_check_status, |
| 359 | .exec_command = ata_exec_command, |
| 360 | .dev_select = ata_std_dev_select, |
| 361 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 362 | .bmdma_setup = ata_bmdma_setup, |
| 363 | .bmdma_start = ata_bmdma_start, |
| 364 | .bmdma_stop = ata_bmdma_stop, |
| 365 | .bmdma_status = ata_bmdma_status, |
| 366 | .qc_prep = ata_qc_prep, |
| 367 | .qc_issue = ata_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 368 | .data_xfer = ata_data_xfer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 369 | |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 370 | .freeze = ata_bmdma_freeze, |
| 371 | .thaw = ata_bmdma_thaw, |
Alan Cox | 2f91d81 | 2007-05-21 15:15:51 +0100 | [diff] [blame] | 372 | .error_handler = ata_bmdma_error_handler, |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 373 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | |
| 375 | .irq_handler = ata_interrupt, |
| 376 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 377 | .irq_on = ata_irq_on, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | |
| 379 | .port_start = ata_port_start, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | }; |
| 381 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 382 | static const struct piix_map_db ich5_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 383 | .mask = 0x7, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 384 | .port_enable = 0x3, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 385 | .map = { |
| 386 | /* PM PS SM SS MAP */ |
| 387 | { P0, NA, P1, NA }, /* 000b */ |
| 388 | { P1, NA, P0, NA }, /* 001b */ |
| 389 | { RV, RV, RV, RV }, |
| 390 | { RV, RV, RV, RV }, |
| 391 | { P0, P1, IDE, IDE }, /* 100b */ |
| 392 | { P1, P0, IDE, IDE }, /* 101b */ |
| 393 | { IDE, IDE, P0, P1 }, /* 110b */ |
| 394 | { IDE, IDE, P1, P0 }, /* 111b */ |
| 395 | }, |
| 396 | }; |
| 397 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 398 | static const struct piix_map_db ich6_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 399 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 400 | .port_enable = 0xf, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 401 | .map = { |
| 402 | /* PM PS SM SS MAP */ |
Tejun Heo | 79ea24e | 2006-03-31 20:01:50 +0900 | [diff] [blame] | 403 | { P0, P2, P1, P3 }, /* 00b */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 404 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 405 | { P0, P2, IDE, IDE }, /* 10b */ |
| 406 | { RV, RV, RV, RV }, |
| 407 | }, |
| 408 | }; |
| 409 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 410 | static const struct piix_map_db ich6m_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 411 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 412 | .port_enable = 0x5, |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 413 | |
| 414 | /* Map 01b isn't specified in the doc but some notebooks use |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 415 | * it anyway. MAP 01b have been spotted on both ICH6M and |
| 416 | * ICH7M. |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 417 | */ |
| 418 | .map = { |
| 419 | /* PM PS SM SS MAP */ |
Tejun Heo | e04b3b9 | 2007-07-10 17:58:21 +0900 | [diff] [blame] | 420 | { P0, P2, NA, NA }, /* 00b */ |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 421 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 422 | { P0, P2, IDE, IDE }, /* 10b */ |
| 423 | { RV, RV, RV, RV }, |
| 424 | }, |
| 425 | }; |
| 426 | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 427 | static const struct piix_map_db ich8_map_db = { |
| 428 | .mask = 0x3, |
| 429 | .port_enable = 0x3, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 430 | .map = { |
| 431 | /* PM PS SM SS MAP */ |
Kristen Carlson Accardi | 158f30c8 | 2006-10-19 13:27:39 -0700 | [diff] [blame] | 432 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 433 | { RV, RV, RV, RV }, |
Tejun Heo | ac2b043 | 2007-08-07 02:43:27 +0900 | [diff] [blame] | 434 | { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 435 | { RV, RV, RV, RV }, |
| 436 | }, |
| 437 | }; |
| 438 | |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 439 | static const struct piix_map_db tolapai_map_db = { |
Jason Gaston | e2d352a | 2007-09-07 17:21:03 -0700 | [diff] [blame] | 440 | .mask = 0x3, |
| 441 | .port_enable = 0x3, |
| 442 | .map = { |
| 443 | /* PM PS SM SS MAP */ |
| 444 | { P0, NA, P1, NA }, /* 00b */ |
| 445 | { RV, RV, RV, RV }, /* 01b */ |
| 446 | { RV, RV, RV, RV }, /* 10b */ |
| 447 | { RV, RV, RV, RV }, |
| 448 | }, |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 449 | }; |
| 450 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 451 | static const struct piix_map_db *piix_map_db_table[] = { |
| 452 | [ich5_sata] = &ich5_map_db, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 453 | [ich6_sata] = &ich6_map_db, |
| 454 | [ich6_sata_ahci] = &ich6_map_db, |
| 455 | [ich6m_sata_ahci] = &ich6m_map_db, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 456 | [ich8_sata_ahci] = &ich8_map_db, |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 457 | [tolapai_sata_ahci] = &tolapai_map_db, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 458 | }; |
| 459 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | static struct ata_port_info piix_port_info[] = { |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 461 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 462 | { |
| 463 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 464 | .flags = PIIX_PATA_FLAGS, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 465 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 466 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 467 | .udma_mask = ATA_UDMA_MASK_40C, |
| 468 | .port_ops = &piix_pata_ops, |
| 469 | }, |
| 470 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 471 | [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 472 | { |
| 473 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 474 | .flags = PIIX_PATA_FLAGS, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 475 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 476 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ |
| 477 | .udma_mask = ATA_UDMA2, /* UDMA33 */ |
| 478 | .port_ops = &ich_pata_ops, |
| 479 | }, |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 480 | |
| 481 | [ich_pata_66] = /* ICH controllers up to 66MHz */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 482 | { |
| 483 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 484 | .flags = PIIX_PATA_FLAGS, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 485 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 486 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ |
| 487 | .udma_mask = ATA_UDMA4, |
| 488 | .port_ops = &ich_pata_ops, |
| 489 | }, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 490 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 491 | [ich_pata_100] = |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 492 | { |
| 493 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 494 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | .pio_mask = 0x1f, /* pio0-4 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 496 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 497 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
| 498 | .port_ops = &ich_pata_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | }, |
| 500 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 501 | [ich5_sata] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 502 | { |
| 503 | .sht = &piix_sht, |
Tejun Heo | 228c159 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 504 | .flags = PIIX_SATA_FLAGS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | .pio_mask = 0x1f, /* pio0-4 */ |
| 506 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 507 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | .port_ops = &piix_sata_ops, |
| 509 | }, |
| 510 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 511 | [ich6_sata] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 512 | { |
| 513 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 514 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | .pio_mask = 0x1f, /* pio0-4 */ |
| 516 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 517 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 518 | .port_ops = &piix_sata_ops, |
| 519 | }, |
| 520 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 521 | [ich6_sata_ahci] = |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 522 | { |
| 523 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 524 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 525 | PIIX_FLAG_AHCI, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 526 | .pio_mask = 0x1f, /* pio0-4 */ |
| 527 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 528 | .udma_mask = ATA_UDMA6, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 529 | .port_ops = &piix_sata_ops, |
| 530 | }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 531 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 532 | [ich6m_sata_ahci] = |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 533 | { |
| 534 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 535 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 536 | PIIX_FLAG_AHCI, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 537 | .pio_mask = 0x1f, /* pio0-4 */ |
| 538 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 539 | .udma_mask = ATA_UDMA6, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 540 | .port_ops = &piix_sata_ops, |
| 541 | }, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 542 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 543 | [ich8_sata_ahci] = |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 544 | { |
| 545 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 546 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 547 | PIIX_FLAG_AHCI, |
| 548 | .pio_mask = 0x1f, /* pio0-4 */ |
| 549 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 550 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 551 | .port_ops = &piix_sata_ops, |
| 552 | }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 553 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 554 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 555 | { |
| 556 | .sht = &piix_sht, |
| 557 | .flags = PIIX_PATA_FLAGS, |
| 558 | .pio_mask = 0x1f, /* pio0-4 */ |
| 559 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
| 560 | .port_ops = &piix_pata_ops, |
| 561 | }, |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 562 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 563 | [tolapai_sata_ahci] = |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 564 | { |
| 565 | .sht = &piix_sht, |
| 566 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
| 567 | PIIX_FLAG_AHCI, |
| 568 | .pio_mask = 0x1f, /* pio0-4 */ |
| 569 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 570 | .udma_mask = ATA_UDMA6, |
| 571 | .port_ops = &piix_sata_ops, |
| 572 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 573 | }; |
| 574 | |
| 575 | static struct pci_bits piix_enable_bits[] = { |
| 576 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ |
| 577 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ |
| 578 | }; |
| 579 | |
| 580 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); |
| 581 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); |
| 582 | MODULE_LICENSE("GPL"); |
| 583 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); |
| 584 | MODULE_VERSION(DRV_VERSION); |
| 585 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 586 | struct ich_laptop { |
| 587 | u16 device; |
| 588 | u16 subvendor; |
| 589 | u16 subdevice; |
| 590 | }; |
| 591 | |
| 592 | /* |
| 593 | * List of laptops that use short cables rather than 80 wire |
| 594 | */ |
| 595 | |
| 596 | static const struct ich_laptop ich_laptop[] = { |
| 597 | /* devid, subvendor, subdev */ |
| 598 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ |
J J | babfb68 | 2007-01-09 02:26:30 +0900 | [diff] [blame] | 599 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
Robin H\. Johnson | 1234010 | 2007-03-28 18:02:07 -0700 | [diff] [blame] | 600 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
Jeff Garzik | 54174db | 2007-09-29 04:01:43 -0400 | [diff] [blame] | 601 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
Tejun Heo | b33620f | 2007-05-22 11:34:22 +0200 | [diff] [blame] | 602 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 603 | /* end marker */ |
| 604 | { 0, } |
| 605 | }; |
| 606 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | /** |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 608 | * ich_pata_cable_detect - Probe host controller cable detect info |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 609 | * @ap: Port for which cable detect info is desired |
| 610 | * |
| 611 | * Read 80c cable indicator from ATA PCI device's PCI config |
| 612 | * register. This register is normally set by firmware (BIOS). |
| 613 | * |
| 614 | * LOCKING: |
| 615 | * None (inherited from caller). |
| 616 | */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 617 | |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 618 | static int ich_pata_cable_detect(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 619 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 620 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 621 | const struct ich_laptop *lap = &ich_laptop[0]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | u8 tmp, mask; |
| 623 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 624 | /* Check for specials - Acer Aspire 5602WLMi */ |
| 625 | while (lap->device) { |
| 626 | if (lap->device == pdev->device && |
| 627 | lap->subvendor == pdev->subsystem_vendor && |
| 628 | lap->subdevice == pdev->subsystem_device) { |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 629 | return ATA_CBL_PATA40_SHORT; |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 630 | } |
| 631 | lap++; |
| 632 | } |
| 633 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | /* check BIOS cable detect results */ |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 635 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 636 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
| 637 | if ((tmp & mask) == 0) |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 638 | return ATA_CBL_PATA40; |
| 639 | return ATA_CBL_PATA80; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | } |
| 641 | |
| 642 | /** |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 643 | * piix_pata_prereset - prereset for PATA host controller |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 644 | * @link: Target link |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 645 | * @deadline: deadline jiffies for the operation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 646 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 647 | * LOCKING: |
| 648 | * None (inherited from caller). |
| 649 | */ |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 650 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 651 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 652 | struct ata_port *ap = link->ap; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 653 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 655 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
| 656 | return -ENOENT; |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 657 | return ata_std_prereset(link, deadline); |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 658 | } |
| 659 | |
| 660 | static void piix_pata_error_handler(struct ata_port *ap) |
| 661 | { |
| 662 | ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, |
| 663 | ata_std_postreset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 664 | } |
| 665 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | /** |
| 667 | * piix_set_piomode - Initialize host controller PATA PIO timings |
| 668 | * @ap: Port whose timings we are configuring |
| 669 | * @adev: um |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 670 | * |
| 671 | * Set PIO mode for device, in host controller PCI config space. |
| 672 | * |
| 673 | * LOCKING: |
| 674 | * None (inherited from caller). |
| 675 | */ |
| 676 | |
| 677 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) |
| 678 | { |
| 679 | unsigned int pio = adev->pio_mode - XFER_PIO_0; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 680 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 681 | unsigned int is_slave = (adev->devno != 0); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 682 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 683 | unsigned int slave_port = 0x44; |
| 684 | u16 master_data; |
| 685 | u8 slave_data; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 686 | u8 udma_enable; |
| 687 | int control = 0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 688 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 689 | /* |
| 690 | * See Intel Document 298600-004 for the timing programing rules |
| 691 | * for ICH controllers. |
| 692 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | |
| 694 | static const /* ISP RTC */ |
| 695 | u8 timings[][2] = { { 0, 0 }, |
| 696 | { 0, 0 }, |
| 697 | { 1, 0 }, |
| 698 | { 2, 1 }, |
| 699 | { 2, 3 }, }; |
| 700 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 701 | if (pio >= 2) |
| 702 | control |= 1; /* TIME1 enable */ |
| 703 | if (ata_pio_need_iordy(adev)) |
| 704 | control |= 2; /* IE enable */ |
| 705 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 706 | /* Intel specifies that the PPE functionality is for disk only */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 707 | if (adev->class == ATA_DEV_ATA) |
| 708 | control |= 4; /* PPE enable */ |
| 709 | |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 710 | /* PIO configuration clears DTE unconditionally. It will be |
| 711 | * programmed in set_dmamode which is guaranteed to be called |
| 712 | * after set_piomode if any DMA mode is available. |
| 713 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 714 | pci_read_config_word(dev, master_port, &master_data); |
| 715 | if (is_slave) { |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 716 | /* clear TIME1|IE1|PPE1|DTE1 */ |
| 717 | master_data &= 0xff0f; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 718 | /* Enable SITRE (seperate slave timing register) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 719 | master_data |= 0x4000; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 720 | /* enable PPE1, IE1 and TIME1 as needed */ |
| 721 | master_data |= (control << 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 722 | pci_read_config_byte(dev, slave_port, &slave_data); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 723 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 724 | /* Load the timing nibble for this slave */ |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 725 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
| 726 | << (ap->port_no ? 4 : 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | } else { |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 728 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
| 729 | master_data &= 0xccf0; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 730 | /* Enable PPE, IE and TIME as appropriate */ |
| 731 | master_data |= control; |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 732 | /* load ISP and RCT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | master_data |= |
| 734 | (timings[pio][0] << 12) | |
| 735 | (timings[pio][1] << 8); |
| 736 | } |
| 737 | pci_write_config_word(dev, master_port, master_data); |
| 738 | if (is_slave) |
| 739 | pci_write_config_byte(dev, slave_port, slave_data); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 740 | |
| 741 | /* Ensure the UDMA bit is off - it will be turned back on if |
| 742 | UDMA is selected */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 743 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 744 | if (ap->udma_mask) { |
| 745 | pci_read_config_byte(dev, 0x48, &udma_enable); |
| 746 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); |
| 747 | pci_write_config_byte(dev, 0x48, udma_enable); |
| 748 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 749 | } |
| 750 | |
| 751 | /** |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 752 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | * @ap: Port whose timings we are configuring |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 754 | * @adev: Drive in question |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | * @udma: udma mode, 0 - 6 |
Henne | c32a8fd | 2006-09-25 22:00:46 +0200 | [diff] [blame] | 756 | * @isich: set if the chip is an ICH device |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 757 | * |
| 758 | * Set UDMA mode for device, in host controller PCI config space. |
| 759 | * |
| 760 | * LOCKING: |
| 761 | * None (inherited from caller). |
| 762 | */ |
| 763 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 764 | static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 765 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 766 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 767 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
| 768 | u16 master_data; |
| 769 | u8 speed = adev->dma_mode; |
| 770 | int devid = adev->devno + 2 * ap->port_no; |
Andrew Morton | dedf61d | 2007-01-10 17:20:34 -0800 | [diff] [blame] | 771 | u8 udma_enable = 0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 772 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 773 | static const /* ISP RTC */ |
| 774 | u8 timings[][2] = { { 0, 0 }, |
| 775 | { 0, 0 }, |
| 776 | { 1, 0 }, |
| 777 | { 2, 1 }, |
| 778 | { 2, 3 }, }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 779 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 780 | pci_read_config_word(dev, master_port, &master_data); |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 781 | if (ap->udma_mask) |
| 782 | pci_read_config_byte(dev, 0x48, &udma_enable); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 783 | |
| 784 | if (speed >= XFER_UDMA_0) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 785 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
| 786 | u16 udma_timing; |
| 787 | u16 ideconf; |
| 788 | int u_clock, u_speed; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 789 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 790 | /* |
| 791 | * UDMA is handled by a combination of clock switching and |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 792 | * selection of dividers |
| 793 | * |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 794 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 795 | * except UDMA0 which is 00 |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 796 | */ |
| 797 | u_speed = min(2 - (udma & 1), udma); |
| 798 | if (udma == 5) |
| 799 | u_clock = 0x1000; /* 100Mhz */ |
| 800 | else if (udma > 2) |
| 801 | u_clock = 1; /* 66Mhz */ |
| 802 | else |
| 803 | u_clock = 0; /* 33Mhz */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 804 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 805 | udma_enable |= (1 << devid); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 806 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 807 | /* Load the CT/RP selection */ |
| 808 | pci_read_config_word(dev, 0x4A, &udma_timing); |
| 809 | udma_timing &= ~(3 << (4 * devid)); |
| 810 | udma_timing |= u_speed << (4 * devid); |
| 811 | pci_write_config_word(dev, 0x4A, udma_timing); |
| 812 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 813 | if (isich) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 814 | /* Select a 33/66/100Mhz clock */ |
| 815 | pci_read_config_word(dev, 0x54, &ideconf); |
| 816 | ideconf &= ~(0x1001 << devid); |
| 817 | ideconf |= u_clock << devid; |
| 818 | /* For ICH or later we should set bit 10 for better |
| 819 | performance (WR_PingPong_En) */ |
| 820 | pci_write_config_word(dev, 0x54, ideconf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 821 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 822 | } else { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 823 | /* |
| 824 | * MWDMA is driven by the PIO timings. We must also enable |
| 825 | * IORDY unconditionally along with TIME1. PPE has already |
| 826 | * been set when the PIO timing was set. |
| 827 | */ |
| 828 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; |
| 829 | unsigned int control; |
| 830 | u8 slave_data; |
| 831 | const unsigned int needed_pio[3] = { |
| 832 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 |
| 833 | }; |
| 834 | int pio = needed_pio[mwdma] - XFER_PIO_0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 835 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 836 | control = 3; /* IORDY|TIME1 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 837 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 838 | /* If the drive MWDMA is faster than it can do PIO then |
| 839 | we must force PIO into PIO0 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 840 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 841 | if (adev->pio_mode < needed_pio[mwdma]) |
| 842 | /* Enable DMA timing only */ |
| 843 | control |= 8; /* PIO cycles in PIO0 */ |
| 844 | |
| 845 | if (adev->devno) { /* Slave */ |
| 846 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ |
| 847 | master_data |= control << 4; |
| 848 | pci_read_config_byte(dev, 0x44, &slave_data); |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 849 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 850 | /* Load the matching timing */ |
| 851 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); |
| 852 | pci_write_config_byte(dev, 0x44, slave_data); |
| 853 | } else { /* Master */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 854 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 855 | and master timing bits */ |
| 856 | master_data |= control; |
| 857 | master_data |= |
| 858 | (timings[pio][0] << 12) | |
| 859 | (timings[pio][1] << 8); |
| 860 | } |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 861 | |
| 862 | if (ap->udma_mask) { |
| 863 | udma_enable &= ~(1 << devid); |
| 864 | pci_write_config_word(dev, master_port, master_data); |
| 865 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 866 | } |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 867 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
| 868 | if (ap->udma_mask) |
| 869 | pci_write_config_byte(dev, 0x48, udma_enable); |
| 870 | } |
| 871 | |
| 872 | /** |
| 873 | * piix_set_dmamode - Initialize host controller PATA DMA timings |
| 874 | * @ap: Port whose timings we are configuring |
| 875 | * @adev: um |
| 876 | * |
| 877 | * Set MW/UDMA mode for device, in host controller PCI config space. |
| 878 | * |
| 879 | * LOCKING: |
| 880 | * None (inherited from caller). |
| 881 | */ |
| 882 | |
| 883 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 884 | { |
| 885 | do_pata_set_dmamode(ap, adev, 0); |
| 886 | } |
| 887 | |
| 888 | /** |
| 889 | * ich_set_dmamode - Initialize host controller PATA DMA timings |
| 890 | * @ap: Port whose timings we are configuring |
| 891 | * @adev: um |
| 892 | * |
| 893 | * Set MW/UDMA mode for device, in host controller PCI config space. |
| 894 | * |
| 895 | * LOCKING: |
| 896 | * None (inherited from caller). |
| 897 | */ |
| 898 | |
| 899 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 900 | { |
| 901 | do_pata_set_dmamode(ap, adev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 902 | } |
| 903 | |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 904 | #ifdef CONFIG_PM |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 905 | static int piix_broken_suspend(void) |
| 906 | { |
Jeff Garzik | 1855256 | 2007-10-03 15:15:40 -0400 | [diff] [blame] | 907 | static const struct dmi_system_id sysids[] = { |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 908 | { |
Tejun Heo | 4c74d4e | 2007-09-30 01:11:20 -0700 | [diff] [blame] | 909 | .ident = "TECRA M3", |
| 910 | .matches = { |
| 911 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 912 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), |
| 913 | }, |
| 914 | }, |
| 915 | { |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 916 | .ident = "TECRA M5", |
| 917 | .matches = { |
| 918 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 919 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), |
| 920 | }, |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 921 | }, |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 922 | { |
Tejun Heo | 5c08ea0 | 2007-08-14 19:56:04 +0900 | [diff] [blame] | 923 | .ident = "TECRA M7", |
| 924 | .matches = { |
| 925 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 926 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), |
| 927 | }, |
| 928 | }, |
| 929 | { |
Tejun Heo | 3cc0b9d | 2007-08-25 08:31:02 +0900 | [diff] [blame] | 930 | .ident = "Satellite U200", |
| 931 | .matches = { |
| 932 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 933 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), |
| 934 | }, |
| 935 | }, |
| 936 | { |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 937 | .ident = "Satellite U205", |
| 938 | .matches = { |
| 939 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 940 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), |
| 941 | }, |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 942 | }, |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 943 | { |
| 944 | .ident = "Portege M500", |
| 945 | .matches = { |
| 946 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 947 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), |
| 948 | }, |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 949 | }, |
Jeff Garzik | 7d05154 | 2007-09-01 06:48:52 -0400 | [diff] [blame] | 950 | |
| 951 | { } /* terminate list */ |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 952 | }; |
Tejun Heo | 7abe79c | 2007-07-27 14:55:07 +0900 | [diff] [blame] | 953 | static const char *oemstrs[] = { |
| 954 | "Tecra M3,", |
| 955 | }; |
| 956 | int i; |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 957 | |
| 958 | if (dmi_check_system(sysids)) |
| 959 | return 1; |
| 960 | |
Tejun Heo | 7abe79c | 2007-07-27 14:55:07 +0900 | [diff] [blame] | 961 | for (i = 0; i < ARRAY_SIZE(oemstrs); i++) |
| 962 | if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) |
| 963 | return 1; |
| 964 | |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 965 | return 0; |
| 966 | } |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 967 | |
| 968 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
| 969 | { |
| 970 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
| 971 | unsigned long flags; |
| 972 | int rc = 0; |
| 973 | |
| 974 | rc = ata_host_suspend(host, mesg); |
| 975 | if (rc) |
| 976 | return rc; |
| 977 | |
| 978 | /* Some braindamaged ACPI suspend implementations expect the |
| 979 | * controller to be awake on entry; otherwise, it burns cpu |
| 980 | * cycles and power trying to do something to the sleeping |
| 981 | * beauty. |
| 982 | */ |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 983 | if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) { |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 984 | pci_save_state(pdev); |
| 985 | |
| 986 | /* mark its power state as "unknown", since we don't |
| 987 | * know if e.g. the BIOS will change its device state |
| 988 | * when we suspend. |
| 989 | */ |
| 990 | if (pdev->current_state == PCI_D0) |
| 991 | pdev->current_state = PCI_UNKNOWN; |
| 992 | |
| 993 | /* tell resume that it's waking up from broken suspend */ |
| 994 | spin_lock_irqsave(&host->lock, flags); |
| 995 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; |
| 996 | spin_unlock_irqrestore(&host->lock, flags); |
| 997 | } else |
| 998 | ata_pci_device_do_suspend(pdev, mesg); |
| 999 | |
| 1000 | return 0; |
| 1001 | } |
| 1002 | |
| 1003 | static int piix_pci_device_resume(struct pci_dev *pdev) |
| 1004 | { |
| 1005 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
| 1006 | unsigned long flags; |
| 1007 | int rc; |
| 1008 | |
| 1009 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { |
| 1010 | spin_lock_irqsave(&host->lock, flags); |
| 1011 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; |
| 1012 | spin_unlock_irqrestore(&host->lock, flags); |
| 1013 | |
| 1014 | pci_set_power_state(pdev, PCI_D0); |
| 1015 | pci_restore_state(pdev); |
| 1016 | |
| 1017 | /* PCI device wasn't disabled during suspend. Use |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 1018 | * pci_reenable_device() to avoid affecting the enable |
| 1019 | * count. |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1020 | */ |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 1021 | rc = pci_reenable_device(pdev); |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1022 | if (rc) |
| 1023 | dev_printk(KERN_ERR, &pdev->dev, "failed to enable " |
| 1024 | "device after resume (%d)\n", rc); |
| 1025 | } else |
| 1026 | rc = ata_pci_device_do_resume(pdev); |
| 1027 | |
| 1028 | if (rc == 0) |
| 1029 | ata_host_resume(host); |
| 1030 | |
| 1031 | return rc; |
| 1032 | } |
| 1033 | #endif |
| 1034 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1035 | #define AHCI_PCI_BAR 5 |
| 1036 | #define AHCI_GLOBAL_CTL 0x04 |
| 1037 | #define AHCI_ENABLE (1 << 31) |
| 1038 | static int piix_disable_ahci(struct pci_dev *pdev) |
| 1039 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1040 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1041 | u32 tmp; |
| 1042 | int rc = 0; |
| 1043 | |
| 1044 | /* BUG: pci_enable_device has not yet been called. This |
| 1045 | * works because this device is usually set up by BIOS. |
| 1046 | */ |
| 1047 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1048 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
| 1049 | !pci_resource_len(pdev, AHCI_PCI_BAR)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1050 | return 0; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1051 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1052 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1053 | if (!mmio) |
| 1054 | return -ENOMEM; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1055 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1056 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 1057 | if (tmp & AHCI_ENABLE) { |
| 1058 | tmp &= ~AHCI_ENABLE; |
| 1059 | writel(tmp, mmio + AHCI_GLOBAL_CTL); |
| 1060 | |
| 1061 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 1062 | if (tmp & AHCI_ENABLE) |
| 1063 | rc = -EIO; |
| 1064 | } |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1065 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1066 | pci_iounmap(pdev, mmio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1067 | return rc; |
| 1068 | } |
| 1069 | |
| 1070 | /** |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1071 | * piix_check_450nx_errata - Check for problem 450NX setup |
Randy Dunlap | c893a3a | 2006-01-28 13:15:32 -0500 | [diff] [blame] | 1072 | * @ata_dev: the PCI device to check |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1073 | * |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1074 | * Check for the present of 450NX errata #19 and errata #25. If |
| 1075 | * they are found return an error code so we can turn off DMA |
| 1076 | */ |
| 1077 | |
| 1078 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) |
| 1079 | { |
| 1080 | struct pci_dev *pdev = NULL; |
| 1081 | u16 cfg; |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1082 | int no_piix_dma = 0; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1083 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1084 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) |
| 1085 | { |
| 1086 | /* Look for 450NX PXB. Check for problem configurations |
| 1087 | A PCI quirk checks bit 6 already */ |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1088 | pci_read_config_word(pdev, 0x41, &cfg); |
| 1089 | /* Only on the original revision: IDE DMA can hang */ |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 1090 | if (pdev->revision == 0x00) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1091 | no_piix_dma = 1; |
| 1092 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 1093 | else if (cfg & (1<<14) && pdev->revision < 5) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1094 | no_piix_dma = 2; |
| 1095 | } |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 1096 | if (no_piix_dma) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1097 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 1098 | if (no_piix_dma == 2) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1099 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
| 1100 | return no_piix_dma; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1101 | } |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1102 | |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1103 | static void __devinit piix_init_pcs(struct pci_dev *pdev, |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 1104 | struct ata_port_info *pinfo, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1105 | const struct piix_map_db *map_db) |
| 1106 | { |
| 1107 | u16 pcs, new_pcs; |
| 1108 | |
| 1109 | pci_read_config_word(pdev, ICH5_PCS, &pcs); |
| 1110 | |
| 1111 | new_pcs = pcs | map_db->port_enable; |
| 1112 | |
| 1113 | if (new_pcs != pcs) { |
| 1114 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); |
| 1115 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); |
| 1116 | msleep(150); |
| 1117 | } |
| 1118 | } |
| 1119 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1120 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1121 | struct ata_port_info *pinfo, |
| 1122 | const struct piix_map_db *map_db) |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1123 | { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1124 | struct piix_host_priv *hpriv = pinfo[0].private_data; |
Al Viro | b4482a4 | 2007-10-14 19:35:40 +0100 | [diff] [blame] | 1125 | const int *map; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1126 | int i, invalid_map = 0; |
| 1127 | u8 map_value; |
| 1128 | |
| 1129 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); |
| 1130 | |
| 1131 | map = map_db->map[map_value & map_db->mask]; |
| 1132 | |
| 1133 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); |
| 1134 | for (i = 0; i < 4; i++) { |
| 1135 | switch (map[i]) { |
| 1136 | case RV: |
| 1137 | invalid_map = 1; |
| 1138 | printk(" XX"); |
| 1139 | break; |
| 1140 | |
| 1141 | case NA: |
| 1142 | printk(" --"); |
| 1143 | break; |
| 1144 | |
| 1145 | case IDE: |
| 1146 | WARN_ON((i & 1) || map[i + 1] != IDE); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 1147 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
Tejun Heo | f814b75 | 2006-08-05 03:59:13 +0900 | [diff] [blame] | 1148 | pinfo[i / 2].private_data = hpriv; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1149 | i++; |
| 1150 | printk(" IDE IDE"); |
| 1151 | break; |
| 1152 | |
| 1153 | default: |
| 1154 | printk(" P%d", map[i]); |
| 1155 | if (i & 1) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1156 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1157 | break; |
| 1158 | } |
| 1159 | } |
| 1160 | printk(" ]\n"); |
| 1161 | |
| 1162 | if (invalid_map) |
| 1163 | dev_printk(KERN_ERR, &pdev->dev, |
| 1164 | "invalid MAP value %u\n", map_value); |
| 1165 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1166 | hpriv->map = map; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1167 | } |
| 1168 | |
Tejun Heo | 43a98f0 | 2007-08-23 10:15:18 +0900 | [diff] [blame] | 1169 | static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) |
| 1170 | { |
Jeff Garzik | 1855256 | 2007-10-03 15:15:40 -0400 | [diff] [blame] | 1171 | static const struct dmi_system_id sysids[] = { |
Tejun Heo | 43a98f0 | 2007-08-23 10:15:18 +0900 | [diff] [blame] | 1172 | { |
| 1173 | /* Clevo M570U sets IOCFG bit 18 if the cdrom |
| 1174 | * isn't used to boot the system which |
| 1175 | * disables the channel. |
| 1176 | */ |
| 1177 | .ident = "M570U", |
| 1178 | .matches = { |
| 1179 | DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), |
| 1180 | DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), |
| 1181 | }, |
| 1182 | }, |
Jeff Garzik | 7d05154 | 2007-09-01 06:48:52 -0400 | [diff] [blame] | 1183 | |
| 1184 | { } /* terminate list */ |
Tejun Heo | 43a98f0 | 2007-08-23 10:15:18 +0900 | [diff] [blame] | 1185 | }; |
| 1186 | u32 iocfg; |
| 1187 | |
| 1188 | if (!dmi_check_system(sysids)) |
| 1189 | return; |
| 1190 | |
| 1191 | /* The datasheet says that bit 18 is NOOP but certain systems |
| 1192 | * seem to use it to disable a channel. Clear the bit on the |
| 1193 | * affected systems. |
| 1194 | */ |
| 1195 | pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); |
| 1196 | if (iocfg & (1 << 18)) { |
| 1197 | dev_printk(KERN_INFO, &pdev->dev, |
| 1198 | "applying IOCFG bit18 quirk\n"); |
| 1199 | iocfg &= ~(1 << 18); |
| 1200 | pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); |
| 1201 | } |
| 1202 | } |
| 1203 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1204 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1205 | * piix_init_one - Register PIIX ATA PCI device with kernel services |
| 1206 | * @pdev: PCI device to register |
| 1207 | * @ent: Entry in piix_pci_tbl matching with @pdev |
| 1208 | * |
| 1209 | * Called from kernel PCI layer. We probe for combined mode (sigh), |
| 1210 | * and then hand over control to libata, for it to do the rest. |
| 1211 | * |
| 1212 | * LOCKING: |
| 1213 | * Inherited from PCI layer (may sleep). |
| 1214 | * |
| 1215 | * RETURNS: |
| 1216 | * Zero on success, or -ERRNO value. |
| 1217 | */ |
| 1218 | |
| 1219 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1220 | { |
| 1221 | static int printed_version; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1222 | struct device *dev = &pdev->dev; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1223 | struct ata_port_info port_info[2]; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 1224 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1225 | struct piix_host_priv *hpriv; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1226 | unsigned long port_flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1227 | |
| 1228 | if (!printed_version++) |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 1229 | dev_printk(KERN_DEBUG, &pdev->dev, |
| 1230 | "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1231 | |
| 1232 | /* no hotplugging support (FIXME) */ |
| 1233 | if (!in_module_init) |
| 1234 | return -ENODEV; |
| 1235 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1236 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1237 | if (!hpriv) |
| 1238 | return -ENOMEM; |
| 1239 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1240 | port_info[0] = piix_port_info[ent->driver_data]; |
| 1241 | port_info[1] = piix_port_info[ent->driver_data]; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1242 | port_info[0].private_data = hpriv; |
| 1243 | port_info[1].private_data = hpriv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1244 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1245 | port_flags = port_info[0].flags; |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 1246 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1247 | if (port_flags & PIIX_FLAG_AHCI) { |
Jeff Garzik | 8a60a07 | 2005-07-31 13:13:24 -0400 | [diff] [blame] | 1248 | u8 tmp; |
| 1249 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); |
| 1250 | if (tmp == PIIX_AHCI_DEVICE) { |
| 1251 | int rc = piix_disable_ahci(pdev); |
| 1252 | if (rc) |
| 1253 | return rc; |
| 1254 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1255 | } |
| 1256 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1257 | /* Initialize SATA map */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1258 | if (port_flags & ATA_FLAG_SATA) { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1259 | piix_init_sata_map(pdev, port_info, |
| 1260 | piix_map_db_table[ent->driver_data]); |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 1261 | piix_init_pcs(pdev, port_info, |
| 1262 | piix_map_db_table[ent->driver_data]); |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1263 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1264 | |
Tejun Heo | 43a98f0 | 2007-08-23 10:15:18 +0900 | [diff] [blame] | 1265 | /* apply IOCFG bit18 quirk */ |
| 1266 | piix_iocfg_bit18_quirk(pdev); |
| 1267 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | /* On ICH5, some BIOSen disable the interrupt using the |
| 1269 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. |
| 1270 | * On ICH6, this bit has the same effect, but only when |
| 1271 | * MSI is disabled (and it is disabled, as we don't use |
| 1272 | * message-signalled interrupts currently). |
| 1273 | */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1274 | if (port_flags & PIIX_FLAG_CHECKINTR) |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1275 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1276 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1277 | if (piix_check_450nx_errata(pdev)) { |
| 1278 | /* This writes into the master table but it does not |
| 1279 | really matter for this errata as we will apply it to |
| 1280 | all the PIIX devices on the board */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1281 | port_info[0].mwdma_mask = 0; |
| 1282 | port_info[0].udma_mask = 0; |
| 1283 | port_info[1].mwdma_mask = 0; |
| 1284 | port_info[1].udma_mask = 0; |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1285 | } |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 1286 | return ata_pci_init_one(pdev, ppi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | } |
| 1288 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1289 | static int __init piix_init(void) |
| 1290 | { |
| 1291 | int rc; |
| 1292 | |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 1293 | DPRINTK("pci_register_driver\n"); |
| 1294 | rc = pci_register_driver(&piix_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1295 | if (rc) |
| 1296 | return rc; |
| 1297 | |
| 1298 | in_module_init = 0; |
| 1299 | |
| 1300 | DPRINTK("done\n"); |
| 1301 | return 0; |
| 1302 | } |
| 1303 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1304 | static void __exit piix_exit(void) |
| 1305 | { |
| 1306 | pci_unregister_driver(&piix_pci_driver); |
| 1307 | } |
| 1308 | |
| 1309 | module_init(piix_init); |
| 1310 | module_exit(piix_exit); |