blob: 841c899f5132841de3e2078cc8c6f174e4c59da3 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
29#include <mach/msm_xo.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070030#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "clock-local.h"
33#include "clock-rpm.h"
34#include "clock-voter.h"
35#include "clock-dss-8960.h"
36#include "devices.h"
37
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
44#define CE1_HCLK_CTL_REG REG(0x2720)
45#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou41515e22011-09-01 19:37:43 -070046#define CE3_HCLK_CTL_REG REG(0x36C4)
47#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
48#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070049#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou41515e22011-09-01 19:37:43 -070050#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
52#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
53#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
54#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070055/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
57#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070058#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070059#define CLK_TEST_REG REG(0x2FA0)
Matt Wagantall7625a4c2011-11-01 16:17:53 -070060#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
61#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070062#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
63#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
64#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
65#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
66#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
67#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070068#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070069/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070070#define BB_PLL_ENA_SC0_REG REG(0x34C0)
71#define BB_PLL0_STATUS_REG REG(0x30D8)
72#define BB_PLL5_STATUS_REG REG(0x30F8)
73#define BB_PLL6_STATUS_REG REG(0x3118)
74#define BB_PLL7_STATUS_REG REG(0x3138)
75#define BB_PLL8_L_VAL_REG REG(0x3144)
76#define BB_PLL8_M_VAL_REG REG(0x3148)
77#define BB_PLL8_MODE_REG REG(0x3140)
78#define BB_PLL8_N_VAL_REG REG(0x314C)
79#define BB_PLL8_STATUS_REG REG(0x3158)
80#define BB_PLL8_CONFIG_REG REG(0x3154)
81#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070082#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
83#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070084#define BB_PLL14_MODE_REG REG(0x31C0)
85#define BB_PLL14_L_VAL_REG REG(0x31C4)
86#define BB_PLL14_M_VAL_REG REG(0x31C8)
87#define BB_PLL14_N_VAL_REG REG(0x31CC)
88#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
89#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070090#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070091#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
92#define PMEM_ACLK_CTL_REG REG(0x25A0)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070093#define QDSS_AT_CLK_SRC0_NS_REG REG(0x2180)
94#define QDSS_AT_CLK_SRC1_NS_REG REG(0x2184)
95#define QDSS_AT_CLK_SRC_CTL_REG REG(0x2188)
96#define QDSS_AT_CLK_NS_REG REG(0x218C)
97#define QDSS_HCLK_CTL_REG REG(0x22A0)
98#define QDSS_RESETS_REG REG(0x2260)
99#define QDSS_STM_CLK_CTL_REG REG(0x2060)
100#define QDSS_TRACECLKIN_CLK_SRC0_NS_REG REG(0x21A0)
101#define QDSS_TRACECLKIN_CLK_SRC1_NS_REG REG(0x21A4)
102#define QDSS_TRACECLKIN_CLK_SRC_CTL_REG REG(0x21A8)
103#define QDSS_TRACECLKIN_CTL_REG REG(0x21AC)
104#define QDSS_TSCTR_CLK_SRC0_NS_REG REG(0x21C0)
105#define QDSS_TSCTR_CLK_SRC1_NS_REG REG(0x21C4)
106#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
107#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
108#define QDSS_TSCTR_CTL_REG REG(0x21CC)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700109#define RINGOSC_NS_REG REG(0x2DC0)
110#define RINGOSC_STATUS_REG REG(0x2DCC)
111#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
112#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
113#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
114#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
115#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
116#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
117#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
118#define TSIF_HCLK_CTL_REG REG(0x2700)
119#define TSIF_REF_CLK_MD_REG REG(0x270C)
120#define TSIF_REF_CLK_NS_REG REG(0x2710)
121#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700122#define SATA_CLK_SRC_NS_REG REG(0x2C08)
123#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
124#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
125#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
126#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700127#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
128#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
129#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
130#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
131#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
132#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700133#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700134#define USB_HS1_RESET_REG REG(0x2910)
135#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
136#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700137#define USB_HS3_HCLK_CTL_REG REG(0x3700)
138#define USB_HS3_HCLK_FS_REG REG(0x3704)
139#define USB_HS3_RESET_REG REG(0x3710)
140#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
141#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
142#define USB_HS4_HCLK_CTL_REG REG(0x3720)
143#define USB_HS4_HCLK_FS_REG REG(0x3724)
144#define USB_HS4_RESET_REG REG(0x3730)
145#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
146#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700147#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
148#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
149#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
150#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
151#define USB_HSIC_RESET_REG REG(0x2934)
152#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
153#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
154#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700155#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700156#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
157#define PCIE_HCLK_CTL_REG REG(0x22CC)
158#define GPLL1_MODE_REG REG(0x3160)
159#define GPLL1_L_VAL_REG REG(0x3164)
160#define GPLL1_M_VAL_REG REG(0x3168)
161#define GPLL1_N_VAL_REG REG(0x316C)
162#define GPLL1_CONFIG_REG REG(0x3174)
163#define GPLL1_STATUS_REG REG(0x3178)
164#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700165
166/* Multimedia clock registers. */
167#define AHB_EN_REG REG_MM(0x0008)
168#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700169#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700170#define AHB_NS_REG REG_MM(0x0004)
171#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700172#define CAMCLK0_NS_REG REG_MM(0x0148)
173#define CAMCLK0_CC_REG REG_MM(0x0140)
174#define CAMCLK0_MD_REG REG_MM(0x0144)
175#define CAMCLK1_NS_REG REG_MM(0x015C)
176#define CAMCLK1_CC_REG REG_MM(0x0154)
177#define CAMCLK1_MD_REG REG_MM(0x0158)
178#define CAMCLK2_NS_REG REG_MM(0x0228)
179#define CAMCLK2_CC_REG REG_MM(0x0220)
180#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700181#define CSI0_NS_REG REG_MM(0x0048)
182#define CSI0_CC_REG REG_MM(0x0040)
183#define CSI0_MD_REG REG_MM(0x0044)
184#define CSI1_NS_REG REG_MM(0x0010)
185#define CSI1_CC_REG REG_MM(0x0024)
186#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700187#define CSI2_NS_REG REG_MM(0x0234)
188#define CSI2_CC_REG REG_MM(0x022C)
189#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700190#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
191#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
192#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
193#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
194#define DSI1_BYTE_CC_REG REG_MM(0x0090)
195#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
196#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
197#define DSI1_ESC_NS_REG REG_MM(0x011C)
198#define DSI1_ESC_CC_REG REG_MM(0x00CC)
199#define DSI2_ESC_NS_REG REG_MM(0x0150)
200#define DSI2_ESC_CC_REG REG_MM(0x013C)
201#define DSI_PIXEL_CC_REG REG_MM(0x0130)
202#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
203#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
204#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
205#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
206#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
207#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
208#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
209#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
210#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
211#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700212#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700213#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
214#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
215#define GFX2D0_CC_REG REG_MM(0x0060)
216#define GFX2D0_MD0_REG REG_MM(0x0064)
217#define GFX2D0_MD1_REG REG_MM(0x0068)
218#define GFX2D0_NS_REG REG_MM(0x0070)
219#define GFX2D1_CC_REG REG_MM(0x0074)
220#define GFX2D1_MD0_REG REG_MM(0x0078)
221#define GFX2D1_MD1_REG REG_MM(0x006C)
222#define GFX2D1_NS_REG REG_MM(0x007C)
223#define GFX3D_CC_REG REG_MM(0x0080)
224#define GFX3D_MD0_REG REG_MM(0x0084)
225#define GFX3D_MD1_REG REG_MM(0x0088)
226#define GFX3D_NS_REG REG_MM(0x008C)
227#define IJPEG_CC_REG REG_MM(0x0098)
228#define IJPEG_MD_REG REG_MM(0x009C)
229#define IJPEG_NS_REG REG_MM(0x00A0)
230#define JPEGD_CC_REG REG_MM(0x00A4)
231#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700232#define VCAP_CC_REG REG_MM(0x0178)
233#define VCAP_NS_REG REG_MM(0x021C)
234#define VCAP_MD0_REG REG_MM(0x01EC)
235#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700236#define MAXI_EN_REG REG_MM(0x0018)
237#define MAXI_EN2_REG REG_MM(0x0020)
238#define MAXI_EN3_REG REG_MM(0x002C)
239#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700240#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700241#define MDP_CC_REG REG_MM(0x00C0)
242#define MDP_LUT_CC_REG REG_MM(0x016C)
243#define MDP_MD0_REG REG_MM(0x00C4)
244#define MDP_MD1_REG REG_MM(0x00C8)
245#define MDP_NS_REG REG_MM(0x00D0)
246#define MISC_CC_REG REG_MM(0x0058)
247#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700248#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700249#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700250#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
251#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
252#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
253#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
254#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
255#define MM_PLL1_STATUS_REG REG_MM(0x0334)
256#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700257#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
258#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
259#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
260#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
261#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
262#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700263#define ROT_CC_REG REG_MM(0x00E0)
264#define ROT_NS_REG REG_MM(0x00E8)
265#define SAXI_EN_REG REG_MM(0x0030)
266#define SW_RESET_AHB_REG REG_MM(0x020C)
267#define SW_RESET_AHB2_REG REG_MM(0x0200)
268#define SW_RESET_ALL_REG REG_MM(0x0204)
269#define SW_RESET_AXI_REG REG_MM(0x0208)
270#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700271#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700272#define TV_CC_REG REG_MM(0x00EC)
273#define TV_CC2_REG REG_MM(0x0124)
274#define TV_MD_REG REG_MM(0x00F0)
275#define TV_NS_REG REG_MM(0x00F4)
276#define VCODEC_CC_REG REG_MM(0x00F8)
277#define VCODEC_MD0_REG REG_MM(0x00FC)
278#define VCODEC_MD1_REG REG_MM(0x0128)
279#define VCODEC_NS_REG REG_MM(0x0100)
280#define VFE_CC_REG REG_MM(0x0104)
281#define VFE_MD_REG REG_MM(0x0108)
282#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700283#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700284#define VPE_CC_REG REG_MM(0x0110)
285#define VPE_NS_REG REG_MM(0x0118)
286
287/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700288#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700289#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
290#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
291#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
292#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
293#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
294#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
295#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
296#define LCC_MI2S_MD_REG REG_LPA(0x004C)
297#define LCC_MI2S_NS_REG REG_LPA(0x0048)
298#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
299#define LCC_PCM_MD_REG REG_LPA(0x0058)
300#define LCC_PCM_NS_REG REG_LPA(0x0054)
301#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700302#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
303#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
304#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
305#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
306#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700307#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700308#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
309#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
310#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
311#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
312#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
313#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
314#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
315#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
316#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
317#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700318#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700319
Matt Wagantall8b38f942011-08-02 18:23:18 -0700320#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
321
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700322/* MUX source input identifiers. */
323#define pxo_to_bb_mux 0
Matt Wagantall7625a4c2011-11-01 16:17:53 -0700324#define cxo_to_bb_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700325#define pll0_to_bb_mux 2
326#define pll8_to_bb_mux 3
327#define pll6_to_bb_mux 4
328#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700329#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700330#define pxo_to_mm_mux 0
331#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700332#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
333#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700334#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700335#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700336#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700337#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700338#define hdmi_pll_to_mm_mux 3
339#define cxo_to_xo_mux 0
340#define pxo_to_xo_mux 1
341#define gnd_to_xo_mux 3
342#define pxo_to_lpa_mux 0
343#define cxo_to_lpa_mux 1
344#define pll4_to_lpa_mux 2
345#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700346#define pxo_to_pcie_mux 0
347#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700348
349/* Test Vector Macros */
350#define TEST_TYPE_PER_LS 1
351#define TEST_TYPE_PER_HS 2
352#define TEST_TYPE_MM_LS 3
353#define TEST_TYPE_MM_HS 4
354#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700355#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700356#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700357#define TEST_TYPE_SHIFT 24
358#define TEST_CLK_SEL_MASK BM(23, 0)
359#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
360#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
361#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
362#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
363#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
364#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700365#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700366#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700367
368#define MN_MODE_DUAL_EDGE 0x2
369
370/* MD Registers */
371#define MD4(m_lsb, m, n_lsb, n) \
372 (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
373#define MD8(m_lsb, m, n_lsb, n) \
374 (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
375#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
376
377/* NS Registers */
378#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
379 (BVAL(n_msb, n_lsb, ~(n-m)) \
380 | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
381 | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
382
383#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
384 (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
385 | BVAL(s_msb, s_lsb, s))
386
387#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
388 (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
389
390#define NS_DIV(d_msb , d_lsb, d) \
391 BVAL(d_msb, d_lsb, (d-1))
392
393#define NS_SRC_SEL(s_msb, s_lsb, s) \
394 BVAL(s_msb, s_lsb, s)
395
396#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
397 (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
398 | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
399 | BVAL((s0_lsb+2), s0_lsb, s) \
400 | BVAL((s1_lsb+2), s1_lsb, s))
401
402#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
403 (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
404 | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
405 | BVAL((s0_lsb+2), s0_lsb, s) \
406 | BVAL((s1_lsb+2), s1_lsb, s))
407
408#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
409 s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
410 (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
411 | BVAL(s0_msb, s0_lsb, s) \
412 | BVAL(s1_msb, s1_lsb, s))
413
414/* CC Registers */
415#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
416#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
417 ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
418 | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
419 * !!(n))
420
421struct pll_rate {
422 const uint32_t l_val;
423 const uint32_t m_val;
424 const uint32_t n_val;
425 const uint32_t vco;
426 const uint32_t post_div;
427 const uint32_t i_bits;
428};
429#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
430
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700431enum vdd_dig_levels {
432 VDD_DIG_NONE,
433 VDD_DIG_LOW,
434 VDD_DIG_NOMINAL,
435 VDD_DIG_HIGH
436};
437
438static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
439{
440 static const int vdd_uv[] = {
441 [VDD_DIG_NONE] = 0,
442 [VDD_DIG_LOW] = 945000,
443 [VDD_DIG_NOMINAL] = 1050000,
444 [VDD_DIG_HIGH] = 1150000
445 };
446
447 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
448 vdd_uv[level], 1150000, 1);
449}
450
451static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
452
453#define VDD_DIG_FMAX_MAP1(l1, f1) \
454 .vdd_class = &vdd_dig, \
455 .fmax[VDD_DIG_##l1] = (f1)
456#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
457 .vdd_class = &vdd_dig, \
458 .fmax[VDD_DIG_##l1] = (f1), \
459 .fmax[VDD_DIG_##l2] = (f2)
460#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
461 .vdd_class = &vdd_dig, \
462 .fmax[VDD_DIG_##l1] = (f1), \
463 .fmax[VDD_DIG_##l2] = (f2), \
464 .fmax[VDD_DIG_##l3] = (f3)
465
Matt Wagantallc57577d2011-10-06 17:06:53 -0700466enum vdd_l23_levels {
467 VDD_L23_OFF,
468 VDD_L23_ON
469};
470
471static int set_vdd_l23(struct clk_vdd_class *vdd_class, int level)
472{
473 int rc;
474
475 if (level == VDD_L23_OFF) {
476 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
477 RPM_VREG_VOTER3, 0, 0, 1);
478 if (rc)
479 return rc;
480 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
481 RPM_VREG_VOTER3, 0, 0, 1);
482 if (rc)
483 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
484 RPM_VREG_VOTER3, 1800000, 1800000, 1);
485 } else {
486 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
487 RPM_VREG_VOTER3, 2200000, 2200000, 1);
488 if (rc)
489 return rc;
490 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
491 RPM_VREG_VOTER3, 1800000, 1800000, 1);
492 if (rc)
493 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
494 RPM_VREG_VOTER3, 0, 0, 1);
495 }
496
497 return rc;
498}
499
500static DEFINE_VDD_CLASS(vdd_l23, set_vdd_l23);
501
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700502/*
503 * Clock Descriptions
504 */
505
506static struct msm_xo_voter *xo_pxo, *xo_cxo;
507
508static int pxo_clk_enable(struct clk *clk)
509{
510 return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON);
511}
512
513static void pxo_clk_disable(struct clk *clk)
514{
Tianyi Gou41515e22011-09-01 19:37:43 -0700515 msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700516}
517
518static struct clk_ops clk_ops_pxo = {
519 .enable = pxo_clk_enable,
520 .disable = pxo_clk_disable,
521 .get_rate = fixed_clk_get_rate,
522 .is_local = local_clk_is_local,
523};
524
525static struct fixed_clk pxo_clk = {
526 .rate = 27000000,
527 .c = {
528 .dbg_name = "pxo_clk",
529 .ops = &clk_ops_pxo,
530 CLK_INIT(pxo_clk.c),
531 },
532};
533
534static int cxo_clk_enable(struct clk *clk)
535{
536 return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON);
537}
538
539static void cxo_clk_disable(struct clk *clk)
540{
541 msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF);
542}
543
544static struct clk_ops clk_ops_cxo = {
545 .enable = cxo_clk_enable,
546 .disable = cxo_clk_disable,
547 .get_rate = fixed_clk_get_rate,
548 .is_local = local_clk_is_local,
549};
550
551static struct fixed_clk cxo_clk = {
552 .rate = 19200000,
553 .c = {
554 .dbg_name = "cxo_clk",
555 .ops = &clk_ops_cxo,
556 CLK_INIT(cxo_clk.c),
557 },
558};
559
560static struct pll_clk pll2_clk = {
561 .rate = 800000000,
562 .mode_reg = MM_PLL1_MODE_REG,
563 .parent = &pxo_clk.c,
564 .c = {
565 .dbg_name = "pll2_clk",
566 .ops = &clk_ops_pll,
567 CLK_INIT(pll2_clk.c),
568 },
569};
570
Stephen Boyd94625ef2011-07-12 17:06:01 -0700571static struct pll_clk pll3_clk = {
572 .rate = 1200000000,
573 .mode_reg = BB_MMCC_PLL2_MODE_REG,
574 .parent = &pxo_clk.c,
575 .c = {
576 .dbg_name = "pll3_clk",
577 .ops = &clk_ops_pll,
Matt Wagantallc57577d2011-10-06 17:06:53 -0700578 .vdd_class = &vdd_l23,
579 .fmax[VDD_L23_ON] = ULONG_MAX,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700580 CLK_INIT(pll3_clk.c),
581 },
582};
583
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700584static struct pll_vote_clk pll4_clk = {
585 .rate = 393216000,
586 .en_reg = BB_PLL_ENA_SC0_REG,
587 .en_mask = BIT(4),
588 .status_reg = LCC_PLL0_STATUS_REG,
589 .parent = &pxo_clk.c,
590 .c = {
591 .dbg_name = "pll4_clk",
592 .ops = &clk_ops_pll_vote,
593 CLK_INIT(pll4_clk.c),
594 },
595};
596
597static struct pll_vote_clk pll8_clk = {
598 .rate = 384000000,
599 .en_reg = BB_PLL_ENA_SC0_REG,
600 .en_mask = BIT(8),
601 .status_reg = BB_PLL8_STATUS_REG,
602 .parent = &pxo_clk.c,
603 .c = {
604 .dbg_name = "pll8_clk",
605 .ops = &clk_ops_pll_vote,
606 CLK_INIT(pll8_clk.c),
607 },
608};
609
Stephen Boyd94625ef2011-07-12 17:06:01 -0700610static struct pll_vote_clk pll14_clk = {
611 .rate = 480000000,
612 .en_reg = BB_PLL_ENA_SC0_REG,
613 .en_mask = BIT(14),
614 .status_reg = BB_PLL14_STATUS_REG,
615 .parent = &pxo_clk.c,
616 .c = {
617 .dbg_name = "pll14_clk",
618 .ops = &clk_ops_pll_vote,
619 CLK_INIT(pll14_clk.c),
620 },
621};
622
Tianyi Gou41515e22011-09-01 19:37:43 -0700623static struct pll_clk pll15_clk = {
624 .rate = 975000000,
625 .mode_reg = MM_PLL3_MODE_REG,
626 .parent = &pxo_clk.c,
627 .c = {
628 .dbg_name = "pll15_clk",
629 .ops = &clk_ops_pll,
630 CLK_INIT(pll15_clk.c),
631 },
632};
633
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700634static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
635{
636 return branch_reset(&to_rcg_clk(clk)->b, action);
637}
638
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700639static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700640 .enable = rcg_clk_enable,
641 .disable = rcg_clk_disable,
Matt Wagantall41af0772011-09-17 12:21:39 -0700642 .auto_off = rcg_clk_disable,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700643 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700644 .set_rate = rcg_clk_set_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700645 .get_rate = rcg_clk_get_rate,
646 .list_rate = rcg_clk_list_rate,
647 .is_enabled = rcg_clk_is_enabled,
648 .round_rate = rcg_clk_round_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700649 .reset = soc_clk_reset,
650 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700651 .get_parent = rcg_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700652};
653
654static struct clk_ops clk_ops_branch = {
655 .enable = branch_clk_enable,
656 .disable = branch_clk_disable,
Matt Wagantall41af0772011-09-17 12:21:39 -0700657 .auto_off = branch_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700658 .is_enabled = branch_clk_is_enabled,
659 .reset = branch_clk_reset,
660 .is_local = local_clk_is_local,
661 .get_parent = branch_clk_get_parent,
662 .set_parent = branch_clk_set_parent,
663};
664
665static struct clk_ops clk_ops_reset = {
666 .reset = branch_clk_reset,
667 .is_local = local_clk_is_local,
668};
669
670/* AXI Interfaces */
671static struct branch_clk gmem_axi_clk = {
672 .b = {
673 .ctl_reg = MAXI_EN_REG,
674 .en_mask = BIT(24),
675 .halt_reg = DBG_BUS_VEC_E_REG,
676 .halt_bit = 6,
677 },
678 .c = {
679 .dbg_name = "gmem_axi_clk",
680 .ops = &clk_ops_branch,
681 CLK_INIT(gmem_axi_clk.c),
682 },
683};
684
685static struct branch_clk ijpeg_axi_clk = {
686 .b = {
687 .ctl_reg = MAXI_EN_REG,
688 .en_mask = BIT(21),
689 .reset_reg = SW_RESET_AXI_REG,
690 .reset_mask = BIT(14),
691 .halt_reg = DBG_BUS_VEC_E_REG,
692 .halt_bit = 4,
693 },
694 .c = {
695 .dbg_name = "ijpeg_axi_clk",
696 .ops = &clk_ops_branch,
697 CLK_INIT(ijpeg_axi_clk.c),
698 },
699};
700
701static struct branch_clk imem_axi_clk = {
702 .b = {
703 .ctl_reg = MAXI_EN_REG,
704 .en_mask = BIT(22),
705 .reset_reg = SW_RESET_CORE_REG,
706 .reset_mask = BIT(10),
707 .halt_reg = DBG_BUS_VEC_E_REG,
708 .halt_bit = 7,
709 },
710 .c = {
711 .dbg_name = "imem_axi_clk",
712 .ops = &clk_ops_branch,
713 CLK_INIT(imem_axi_clk.c),
714 },
715};
716
717static struct branch_clk jpegd_axi_clk = {
718 .b = {
719 .ctl_reg = MAXI_EN_REG,
720 .en_mask = BIT(25),
721 .halt_reg = DBG_BUS_VEC_E_REG,
722 .halt_bit = 5,
723 },
724 .c = {
725 .dbg_name = "jpegd_axi_clk",
726 .ops = &clk_ops_branch,
727 CLK_INIT(jpegd_axi_clk.c),
728 },
729};
730
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700731static struct branch_clk vcodec_axi_b_clk = {
732 .b = {
733 .ctl_reg = MAXI_EN4_REG,
734 .en_mask = BIT(23),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700735 .halt_reg = DBG_BUS_VEC_I_REG,
736 .halt_bit = 25,
737 },
738 .c = {
739 .dbg_name = "vcodec_axi_b_clk",
740 .ops = &clk_ops_branch,
741 CLK_INIT(vcodec_axi_b_clk.c),
742 },
743};
744
Matt Wagantall91f42702011-07-14 12:01:15 -0700745static struct branch_clk vcodec_axi_a_clk = {
746 .b = {
747 .ctl_reg = MAXI_EN4_REG,
748 .en_mask = BIT(25),
Matt Wagantall91f42702011-07-14 12:01:15 -0700749 .halt_reg = DBG_BUS_VEC_I_REG,
750 .halt_bit = 26,
751 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700752 .c = {
753 .dbg_name = "vcodec_axi_a_clk",
754 .ops = &clk_ops_branch,
755 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700756 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700757 },
758};
759
760static struct branch_clk vcodec_axi_clk = {
761 .b = {
762 .ctl_reg = MAXI_EN_REG,
763 .en_mask = BIT(19),
764 .reset_reg = SW_RESET_AXI_REG,
Matt Wagantallfe2ee052011-07-14 13:33:44 -0700765 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700766 .halt_reg = DBG_BUS_VEC_E_REG,
767 .halt_bit = 3,
768 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700769 .c = {
770 .dbg_name = "vcodec_axi_clk",
771 .ops = &clk_ops_branch,
772 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700773 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700774 },
775};
776
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700777static struct branch_clk vfe_axi_clk = {
778 .b = {
779 .ctl_reg = MAXI_EN_REG,
780 .en_mask = BIT(18),
781 .reset_reg = SW_RESET_AXI_REG,
782 .reset_mask = BIT(9),
783 .halt_reg = DBG_BUS_VEC_E_REG,
784 .halt_bit = 0,
785 },
786 .c = {
787 .dbg_name = "vfe_axi_clk",
788 .ops = &clk_ops_branch,
789 CLK_INIT(vfe_axi_clk.c),
790 },
791};
792
793static struct branch_clk mdp_axi_clk = {
794 .b = {
795 .ctl_reg = MAXI_EN_REG,
796 .en_mask = BIT(23),
797 .reset_reg = SW_RESET_AXI_REG,
798 .reset_mask = BIT(13),
799 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700800 .halt_bit = 8,
801 },
802 .c = {
803 .dbg_name = "mdp_axi_clk",
804 .ops = &clk_ops_branch,
805 CLK_INIT(mdp_axi_clk.c),
806 },
807};
808
809static struct branch_clk rot_axi_clk = {
810 .b = {
811 .ctl_reg = MAXI_EN2_REG,
812 .en_mask = BIT(24),
813 .reset_reg = SW_RESET_AXI_REG,
814 .reset_mask = BIT(6),
815 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700816 .halt_bit = 2,
817 },
818 .c = {
819 .dbg_name = "rot_axi_clk",
820 .ops = &clk_ops_branch,
821 CLK_INIT(rot_axi_clk.c),
822 },
823};
824
825static struct branch_clk vpe_axi_clk = {
826 .b = {
827 .ctl_reg = MAXI_EN2_REG,
828 .en_mask = BIT(26),
829 .reset_reg = SW_RESET_AXI_REG,
830 .reset_mask = BIT(15),
831 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700832 .halt_bit = 1,
833 },
834 .c = {
835 .dbg_name = "vpe_axi_clk",
836 .ops = &clk_ops_branch,
837 CLK_INIT(vpe_axi_clk.c),
838 },
839};
840
Tianyi Gou41515e22011-09-01 19:37:43 -0700841static struct branch_clk vcap_axi_clk = {
842 .b = {
843 .ctl_reg = MAXI_EN5_REG,
844 .en_mask = BIT(12),
845 .reset_reg = SW_RESET_AXI_REG,
846 .reset_mask = BIT(16),
847 .halt_reg = DBG_BUS_VEC_J_REG,
848 .halt_bit = 20,
849 },
850 .c = {
851 .dbg_name = "vcap_axi_clk",
852 .ops = &clk_ops_branch,
853 CLK_INIT(vcap_axi_clk.c),
854 },
855};
856
Tianyi Gou621f8742011-09-01 21:45:01 -0700857/* For 8064, gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
858static struct branch_clk gfx3d_axi_clk = {
859 .b = {
860 .ctl_reg = MAXI_EN5_REG,
861 .en_mask = BIT(25),
862 .reset_reg = SW_RESET_AXI_REG,
863 .reset_mask = BIT(17),
864 .halt_reg = DBG_BUS_VEC_J_REG,
865 .halt_bit = 30,
866 },
867 .c = {
868 .dbg_name = "gfx3d_axi_clk",
869 .ops = &clk_ops_branch,
870 CLK_INIT(gfx3d_axi_clk.c),
871 },
872};
873
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700874/* AHB Interfaces */
875static struct branch_clk amp_p_clk = {
876 .b = {
877 .ctl_reg = AHB_EN_REG,
878 .en_mask = BIT(24),
879 .halt_reg = DBG_BUS_VEC_F_REG,
880 .halt_bit = 18,
881 },
882 .c = {
883 .dbg_name = "amp_p_clk",
884 .ops = &clk_ops_branch,
885 CLK_INIT(amp_p_clk.c),
886 },
887};
888
Matt Wagantallc23eee92011-08-16 23:06:52 -0700889static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700890 .b = {
891 .ctl_reg = AHB_EN_REG,
892 .en_mask = BIT(7),
893 .reset_reg = SW_RESET_AHB_REG,
894 .reset_mask = BIT(17),
895 .halt_reg = DBG_BUS_VEC_F_REG,
896 .halt_bit = 16,
897 },
898 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700899 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700900 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700901 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700902 },
903};
904
905static struct branch_clk dsi1_m_p_clk = {
906 .b = {
907 .ctl_reg = AHB_EN_REG,
908 .en_mask = BIT(9),
909 .reset_reg = SW_RESET_AHB_REG,
910 .reset_mask = BIT(6),
911 .halt_reg = DBG_BUS_VEC_F_REG,
912 .halt_bit = 19,
913 },
914 .c = {
915 .dbg_name = "dsi1_m_p_clk",
916 .ops = &clk_ops_branch,
917 CLK_INIT(dsi1_m_p_clk.c),
918 },
919};
920
921static struct branch_clk dsi1_s_p_clk = {
922 .b = {
923 .ctl_reg = AHB_EN_REG,
924 .en_mask = BIT(18),
925 .reset_reg = SW_RESET_AHB_REG,
926 .reset_mask = BIT(5),
927 .halt_reg = DBG_BUS_VEC_F_REG,
928 .halt_bit = 21,
929 },
930 .c = {
931 .dbg_name = "dsi1_s_p_clk",
932 .ops = &clk_ops_branch,
933 CLK_INIT(dsi1_s_p_clk.c),
934 },
935};
936
937static struct branch_clk dsi2_m_p_clk = {
938 .b = {
939 .ctl_reg = AHB_EN_REG,
940 .en_mask = BIT(17),
941 .reset_reg = SW_RESET_AHB2_REG,
942 .reset_mask = BIT(1),
943 .halt_reg = DBG_BUS_VEC_E_REG,
944 .halt_bit = 18,
945 },
946 .c = {
947 .dbg_name = "dsi2_m_p_clk",
948 .ops = &clk_ops_branch,
949 CLK_INIT(dsi2_m_p_clk.c),
950 },
951};
952
953static struct branch_clk dsi2_s_p_clk = {
954 .b = {
955 .ctl_reg = AHB_EN_REG,
956 .en_mask = BIT(22),
957 .reset_reg = SW_RESET_AHB2_REG,
958 .reset_mask = BIT(0),
959 .halt_reg = DBG_BUS_VEC_F_REG,
960 .halt_bit = 20,
961 },
962 .c = {
963 .dbg_name = "dsi2_s_p_clk",
964 .ops = &clk_ops_branch,
965 CLK_INIT(dsi2_s_p_clk.c),
966 },
967};
968
969static struct branch_clk gfx2d0_p_clk = {
970 .b = {
971 .ctl_reg = AHB_EN_REG,
972 .en_mask = BIT(19),
973 .reset_reg = SW_RESET_AHB_REG,
974 .reset_mask = BIT(12),
975 .halt_reg = DBG_BUS_VEC_F_REG,
976 .halt_bit = 2,
977 },
978 .c = {
979 .dbg_name = "gfx2d0_p_clk",
980 .ops = &clk_ops_branch,
981 CLK_INIT(gfx2d0_p_clk.c),
982 },
983};
984
985static struct branch_clk gfx2d1_p_clk = {
986 .b = {
987 .ctl_reg = AHB_EN_REG,
988 .en_mask = BIT(2),
989 .reset_reg = SW_RESET_AHB_REG,
990 .reset_mask = BIT(11),
991 .halt_reg = DBG_BUS_VEC_F_REG,
992 .halt_bit = 3,
993 },
994 .c = {
995 .dbg_name = "gfx2d1_p_clk",
996 .ops = &clk_ops_branch,
997 CLK_INIT(gfx2d1_p_clk.c),
998 },
999};
1000
1001static struct branch_clk gfx3d_p_clk = {
1002 .b = {
1003 .ctl_reg = AHB_EN_REG,
1004 .en_mask = BIT(3),
1005 .reset_reg = SW_RESET_AHB_REG,
1006 .reset_mask = BIT(10),
1007 .halt_reg = DBG_BUS_VEC_F_REG,
1008 .halt_bit = 4,
1009 },
1010 .c = {
1011 .dbg_name = "gfx3d_p_clk",
1012 .ops = &clk_ops_branch,
1013 CLK_INIT(gfx3d_p_clk.c),
1014 },
1015};
1016
1017static struct branch_clk hdmi_m_p_clk = {
1018 .b = {
1019 .ctl_reg = AHB_EN_REG,
1020 .en_mask = BIT(14),
1021 .reset_reg = SW_RESET_AHB_REG,
1022 .reset_mask = BIT(9),
1023 .halt_reg = DBG_BUS_VEC_F_REG,
1024 .halt_bit = 5,
1025 },
1026 .c = {
1027 .dbg_name = "hdmi_m_p_clk",
1028 .ops = &clk_ops_branch,
1029 CLK_INIT(hdmi_m_p_clk.c),
1030 },
1031};
1032
1033static struct branch_clk hdmi_s_p_clk = {
1034 .b = {
1035 .ctl_reg = AHB_EN_REG,
1036 .en_mask = BIT(4),
1037 .reset_reg = SW_RESET_AHB_REG,
1038 .reset_mask = BIT(9),
1039 .halt_reg = DBG_BUS_VEC_F_REG,
1040 .halt_bit = 6,
1041 },
1042 .c = {
1043 .dbg_name = "hdmi_s_p_clk",
1044 .ops = &clk_ops_branch,
1045 CLK_INIT(hdmi_s_p_clk.c),
1046 },
1047};
1048
1049static struct branch_clk ijpeg_p_clk = {
1050 .b = {
1051 .ctl_reg = AHB_EN_REG,
1052 .en_mask = BIT(5),
1053 .reset_reg = SW_RESET_AHB_REG,
1054 .reset_mask = BIT(7),
1055 .halt_reg = DBG_BUS_VEC_F_REG,
1056 .halt_bit = 9,
1057 },
1058 .c = {
1059 .dbg_name = "ijpeg_p_clk",
1060 .ops = &clk_ops_branch,
1061 CLK_INIT(ijpeg_p_clk.c),
1062 },
1063};
1064
1065static struct branch_clk imem_p_clk = {
1066 .b = {
1067 .ctl_reg = AHB_EN_REG,
1068 .en_mask = BIT(6),
1069 .reset_reg = SW_RESET_AHB_REG,
1070 .reset_mask = BIT(8),
1071 .halt_reg = DBG_BUS_VEC_F_REG,
1072 .halt_bit = 10,
1073 },
1074 .c = {
1075 .dbg_name = "imem_p_clk",
1076 .ops = &clk_ops_branch,
1077 CLK_INIT(imem_p_clk.c),
1078 },
1079};
1080
1081static struct branch_clk jpegd_p_clk = {
1082 .b = {
1083 .ctl_reg = AHB_EN_REG,
1084 .en_mask = BIT(21),
1085 .reset_reg = SW_RESET_AHB_REG,
1086 .reset_mask = BIT(4),
1087 .halt_reg = DBG_BUS_VEC_F_REG,
1088 .halt_bit = 7,
1089 },
1090 .c = {
1091 .dbg_name = "jpegd_p_clk",
1092 .ops = &clk_ops_branch,
1093 CLK_INIT(jpegd_p_clk.c),
1094 },
1095};
1096
1097static struct branch_clk mdp_p_clk = {
1098 .b = {
1099 .ctl_reg = AHB_EN_REG,
1100 .en_mask = BIT(10),
1101 .reset_reg = SW_RESET_AHB_REG,
1102 .reset_mask = BIT(3),
1103 .halt_reg = DBG_BUS_VEC_F_REG,
1104 .halt_bit = 11,
1105 },
1106 .c = {
1107 .dbg_name = "mdp_p_clk",
1108 .ops = &clk_ops_branch,
1109 CLK_INIT(mdp_p_clk.c),
1110 },
1111};
1112
1113static struct branch_clk rot_p_clk = {
1114 .b = {
1115 .ctl_reg = AHB_EN_REG,
1116 .en_mask = BIT(12),
1117 .reset_reg = SW_RESET_AHB_REG,
1118 .reset_mask = BIT(2),
1119 .halt_reg = DBG_BUS_VEC_F_REG,
1120 .halt_bit = 13,
1121 },
1122 .c = {
1123 .dbg_name = "rot_p_clk",
1124 .ops = &clk_ops_branch,
1125 CLK_INIT(rot_p_clk.c),
1126 },
1127};
1128
1129static struct branch_clk smmu_p_clk = {
1130 .b = {
1131 .ctl_reg = AHB_EN_REG,
1132 .en_mask = BIT(15),
1133 .halt_reg = DBG_BUS_VEC_F_REG,
1134 .halt_bit = 22,
1135 },
1136 .c = {
1137 .dbg_name = "smmu_p_clk",
1138 .ops = &clk_ops_branch,
1139 CLK_INIT(smmu_p_clk.c),
1140 },
1141};
1142
1143static struct branch_clk tv_enc_p_clk = {
1144 .b = {
1145 .ctl_reg = AHB_EN_REG,
1146 .en_mask = BIT(25),
1147 .reset_reg = SW_RESET_AHB_REG,
1148 .reset_mask = BIT(15),
1149 .halt_reg = DBG_BUS_VEC_F_REG,
1150 .halt_bit = 23,
1151 },
1152 .c = {
1153 .dbg_name = "tv_enc_p_clk",
1154 .ops = &clk_ops_branch,
1155 CLK_INIT(tv_enc_p_clk.c),
1156 },
1157};
1158
1159static struct branch_clk vcodec_p_clk = {
1160 .b = {
1161 .ctl_reg = AHB_EN_REG,
1162 .en_mask = BIT(11),
1163 .reset_reg = SW_RESET_AHB_REG,
1164 .reset_mask = BIT(1),
1165 .halt_reg = DBG_BUS_VEC_F_REG,
1166 .halt_bit = 12,
1167 },
1168 .c = {
1169 .dbg_name = "vcodec_p_clk",
1170 .ops = &clk_ops_branch,
1171 CLK_INIT(vcodec_p_clk.c),
1172 },
1173};
1174
1175static struct branch_clk vfe_p_clk = {
1176 .b = {
1177 .ctl_reg = AHB_EN_REG,
1178 .en_mask = BIT(13),
1179 .reset_reg = SW_RESET_AHB_REG,
1180 .reset_mask = BIT(0),
1181 .halt_reg = DBG_BUS_VEC_F_REG,
1182 .halt_bit = 14,
1183 },
1184 .c = {
1185 .dbg_name = "vfe_p_clk",
1186 .ops = &clk_ops_branch,
1187 CLK_INIT(vfe_p_clk.c),
1188 },
1189};
1190
1191static struct branch_clk vpe_p_clk = {
1192 .b = {
1193 .ctl_reg = AHB_EN_REG,
1194 .en_mask = BIT(16),
1195 .reset_reg = SW_RESET_AHB_REG,
1196 .reset_mask = BIT(14),
1197 .halt_reg = DBG_BUS_VEC_F_REG,
1198 .halt_bit = 15,
1199 },
1200 .c = {
1201 .dbg_name = "vpe_p_clk",
1202 .ops = &clk_ops_branch,
1203 CLK_INIT(vpe_p_clk.c),
1204 },
1205};
1206
Tianyi Gou41515e22011-09-01 19:37:43 -07001207static struct branch_clk vcap_p_clk = {
1208 .b = {
1209 .ctl_reg = AHB_EN3_REG,
1210 .en_mask = BIT(1),
1211 .reset_reg = SW_RESET_AHB2_REG,
1212 .reset_mask = BIT(2),
1213 .halt_reg = DBG_BUS_VEC_J_REG,
1214 .halt_bit = 23,
1215 },
1216 .c = {
1217 .dbg_name = "vcap_p_clk",
1218 .ops = &clk_ops_branch,
1219 CLK_INIT(vcap_p_clk.c),
1220 },
1221};
1222
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001223/*
1224 * Peripheral Clocks
1225 */
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001226#define CLK_GP(i, n, h_r, h_b) \
1227 struct rcg_clk i##_clk = { \
1228 .b = { \
1229 .ctl_reg = GPn_NS_REG(n), \
1230 .en_mask = BIT(9), \
1231 .halt_reg = h_r, \
1232 .halt_bit = h_b, \
1233 }, \
1234 .ns_reg = GPn_NS_REG(n), \
1235 .md_reg = GPn_MD_REG(n), \
1236 .root_en_mask = BIT(11), \
1237 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1238 .set_rate = set_rate_mnd, \
1239 .freq_tbl = clk_tbl_gp, \
1240 .current_freq = &rcg_dummy_freq, \
1241 .c = { \
1242 .dbg_name = #i "_clk", \
1243 .ops = &clk_ops_rcg_8960, \
1244 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
1245 CLK_INIT(i##_clk.c), \
1246 }, \
1247 }
1248#define F_GP(f, s, d, m, n) \
1249 { \
1250 .freq_hz = f, \
1251 .src_clk = &s##_clk.c, \
1252 .md_val = MD8(16, m, 0, n), \
1253 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1254 .mnd_en_mask = BIT(8) * !!(n), \
1255 }
1256static struct clk_freq_tbl clk_tbl_gp[] = {
1257 F_GP( 0, gnd, 1, 0, 0),
1258 F_GP( 9600000, cxo, 2, 0, 0),
1259 F_GP( 13500000, pxo, 2, 0, 0),
1260 F_GP( 19200000, cxo, 1, 0, 0),
1261 F_GP( 27000000, pxo, 1, 0, 0),
1262 F_GP( 64000000, pll8, 2, 1, 3),
1263 F_GP( 76800000, pll8, 1, 1, 5),
1264 F_GP( 96000000, pll8, 4, 0, 0),
1265 F_GP(128000000, pll8, 3, 0, 0),
1266 F_GP(192000000, pll8, 2, 0, 0),
1267 F_GP(384000000, pll8, 1, 0, 0),
1268 F_END
1269};
1270
1271static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
1272static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
1273static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
1274
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001275#define CLK_GSBI_UART(i, n, h_r, h_b) \
1276 struct rcg_clk i##_clk = { \
1277 .b = { \
1278 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1279 .en_mask = BIT(9), \
1280 .reset_reg = GSBIn_RESET_REG(n), \
1281 .reset_mask = BIT(0), \
1282 .halt_reg = h_r, \
1283 .halt_bit = h_b, \
1284 }, \
1285 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1286 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1287 .root_en_mask = BIT(11), \
1288 .ns_mask = (BM(31, 16) | BM(6, 0)), \
1289 .set_rate = set_rate_mnd, \
1290 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001291 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001292 .c = { \
1293 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001294 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001295 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001296 CLK_INIT(i##_clk.c), \
1297 }, \
1298 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001299#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001300 { \
1301 .freq_hz = f, \
1302 .src_clk = &s##_clk.c, \
1303 .md_val = MD16(m, n), \
1304 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1305 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001306 }
1307static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001308 F_GSBI_UART( 0, gnd, 1, 0, 0),
1309 F_GSBI_UART( 1843200, pll8, 1, 3, 625),
1310 F_GSBI_UART( 3686400, pll8, 1, 6, 625),
1311 F_GSBI_UART( 7372800, pll8, 1, 12, 625),
1312 F_GSBI_UART(14745600, pll8, 1, 24, 625),
1313 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1314 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1315 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1316 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1317 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1318 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1319 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1320 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1321 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1322 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001323 F_END
1324};
1325
1326static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1327static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1328static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1329static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1330static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1331static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1332static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1333static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1334static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1335static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1336static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1337static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1338
1339#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1340 struct rcg_clk i##_clk = { \
1341 .b = { \
1342 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1343 .en_mask = BIT(9), \
1344 .reset_reg = GSBIn_RESET_REG(n), \
1345 .reset_mask = BIT(0), \
1346 .halt_reg = h_r, \
1347 .halt_bit = h_b, \
1348 }, \
1349 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1350 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1351 .root_en_mask = BIT(11), \
1352 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1353 .set_rate = set_rate_mnd, \
1354 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001355 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001356 .c = { \
1357 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001358 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001359 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001360 CLK_INIT(i##_clk.c), \
1361 }, \
1362 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001363#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001364 { \
1365 .freq_hz = f, \
1366 .src_clk = &s##_clk.c, \
1367 .md_val = MD8(16, m, 0, n), \
1368 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1369 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001370 }
1371static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001372 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1373 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1374 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1375 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1376 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1377 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1378 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1379 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1380 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1381 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001382 F_END
1383};
1384
1385static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1386static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1387static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1388static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1389static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1390static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1391static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1392static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1393static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1394static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1395static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1396static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1397
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001398#define F_QDSS(f, s, d) \
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001399 { \
1400 .freq_hz = f, \
1401 .src_clk = &s##_clk.c, \
1402 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001403 }
1404static struct clk_freq_tbl clk_tbl_qdss[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001405 F_QDSS( 27000000, pxo, 1),
1406 F_QDSS(128000000, pll8, 3),
1407 F_QDSS(300000000, pll3, 4),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001408 F_END
1409};
1410
1411struct qdss_bank {
1412 const u32 bank_sel_mask;
1413 void __iomem *const ns_reg;
1414 const u32 ns_mask;
1415};
1416
Stephen Boydd4de6d72011-09-13 13:01:40 -07001417#define QDSS_CLK_ROOT_ENA BIT(1)
1418
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001419static int qdss_clk_handoff(struct clk *c)
Stephen Boydd4de6d72011-09-13 13:01:40 -07001420{
1421 struct rcg_clk *clk = to_rcg_clk(c);
1422 const struct qdss_bank *bank = clk->bank_info;
1423 u32 reg, ns_val, bank_sel;
1424 struct clk_freq_tbl *freq;
1425
1426 reg = readl_relaxed(clk->ns_reg);
1427 if (!(reg & QDSS_CLK_ROOT_ENA))
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001428 return 0;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001429
1430 bank_sel = reg & bank->bank_sel_mask;
1431 /* Force bank 1 to PXO if bank 0 is in use */
1432 if (bank_sel == 0)
1433 writel_relaxed(0, bank->ns_reg);
1434 ns_val = readl_relaxed(bank->ns_reg) & bank->ns_mask;
1435 for (freq = clk->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
1436 if ((freq->ns_val & bank->ns_mask) == ns_val) {
1437 pr_info("%s rate=%d\n", clk->c.dbg_name, freq->freq_hz);
1438 break;
1439 }
1440 }
1441 if (freq->freq_hz == FREQ_END)
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001442 return 0;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001443
1444 clk->current_freq = freq;
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001445
1446 return 1;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001447}
1448
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001449static void set_rate_qdss(struct rcg_clk *clk, struct clk_freq_tbl *nf)
1450{
1451 const struct qdss_bank *bank = clk->bank_info;
1452 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1453
1454 /* Switch to bank 0 (always sourced from PXO) */
1455 reg = readl_relaxed(clk->ns_reg);
1456 reg &= ~bank_sel_mask;
1457 writel_relaxed(reg, clk->ns_reg);
1458 /*
1459 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1460 * MUX to fully switch sources.
1461 */
1462 mb();
1463 udelay(1);
1464
1465 /* Set source and divider */
1466 reg = readl_relaxed(bank->ns_reg);
1467 reg &= ~bank->ns_mask;
1468 reg |= nf->ns_val;
1469 writel_relaxed(reg, bank->ns_reg);
1470
1471 /* Switch to reprogrammed bank */
1472 reg = readl_relaxed(clk->ns_reg);
1473 reg |= bank_sel_mask;
1474 writel_relaxed(reg, clk->ns_reg);
1475 /*
1476 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1477 * MUX to fully switch sources.
1478 */
1479 mb();
1480 udelay(1);
1481}
1482
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001483static int qdss_clk_enable(struct clk *c)
1484{
1485 struct rcg_clk *clk = to_rcg_clk(c);
1486 const struct qdss_bank *bank = clk->bank_info;
1487 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1488 int ret;
1489
1490 /* Switch to bank 1 */
1491 reg = readl_relaxed(clk->ns_reg);
1492 reg |= bank_sel_mask;
1493 writel_relaxed(reg, clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001494
1495 ret = rcg_clk_enable(c);
1496 if (ret) {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001497 /* Switch to bank 0 */
1498 reg &= ~bank_sel_mask;
1499 writel_relaxed(reg, clk->ns_reg);
1500 }
1501 return ret;
1502}
1503
1504static void qdss_clk_disable(struct clk *c)
1505{
1506 struct rcg_clk *clk = to_rcg_clk(c);
1507 const struct qdss_bank *bank = clk->bank_info;
1508 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1509
1510 rcg_clk_disable(c);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001511 /* Switch to bank 0 */
Stephen Boyddbeca472011-09-12 19:21:22 -07001512 reg = readl_relaxed(clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001513 reg &= ~bank_sel_mask;
1514 writel_relaxed(reg, clk->ns_reg);
1515}
1516
1517static void qdss_clk_auto_off(struct clk *c)
1518{
1519 struct rcg_clk *clk = to_rcg_clk(c);
1520 const struct qdss_bank *bank = clk->bank_info;
1521 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1522
Matt Wagantall41af0772011-09-17 12:21:39 -07001523 rcg_clk_disable(c);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001524 /* Switch to bank 0 */
Stephen Boyddbeca472011-09-12 19:21:22 -07001525 reg = readl_relaxed(clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001526 reg &= ~bank_sel_mask;
1527 writel_relaxed(reg, clk->ns_reg);
1528}
1529
1530static struct clk_ops clk_ops_qdss = {
1531 .enable = qdss_clk_enable,
1532 .disable = qdss_clk_disable,
1533 .auto_off = qdss_clk_auto_off,
Stephen Boydd4de6d72011-09-13 13:01:40 -07001534 .handoff = qdss_clk_handoff,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001535 .set_rate = rcg_clk_set_rate,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001536 .get_rate = rcg_clk_get_rate,
1537 .list_rate = rcg_clk_list_rate,
1538 .is_enabled = rcg_clk_is_enabled,
1539 .round_rate = rcg_clk_round_rate,
1540 .reset = soc_clk_reset,
1541 .is_local = local_clk_is_local,
1542 .get_parent = rcg_clk_get_parent,
1543};
1544
1545static struct qdss_bank bdiv_info_qdss = {
1546 .bank_sel_mask = BIT(0),
1547 .ns_reg = QDSS_AT_CLK_SRC1_NS_REG,
1548 .ns_mask = BM(6, 0),
1549};
1550
1551static struct rcg_clk qdss_at_clk = {
1552 .b = {
1553 .ctl_reg = QDSS_AT_CLK_NS_REG,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001554 .reset_reg = QDSS_RESETS_REG,
1555 .reset_mask = BIT(0),
Stephen Boydfcfd4dd2011-09-13 12:49:57 -07001556 .halt_check = NOCHECK,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001557 },
1558 .ns_reg = QDSS_AT_CLK_SRC_CTL_REG,
1559 .set_rate = set_rate_qdss,
1560 .freq_tbl = clk_tbl_qdss,
1561 .bank_info = &bdiv_info_qdss,
1562 .current_freq = &rcg_dummy_freq,
1563 .c = {
1564 .dbg_name = "qdss_at_clk",
1565 .ops = &clk_ops_qdss,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001566 VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001567 CLK_INIT(qdss_at_clk.c),
1568 },
1569};
1570
1571static struct branch_clk qdss_pclkdbg_clk = {
1572 .b = {
1573 .ctl_reg = QDSS_AT_CLK_NS_REG,
1574 .en_mask = BIT(4),
1575 .reset_reg = QDSS_RESETS_REG,
1576 .reset_mask = BIT(0),
1577 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1578 .halt_bit = 9,
1579 .halt_check = HALT_VOTED
1580 },
1581 .parent = &qdss_at_clk.c,
1582 .c = {
1583 .dbg_name = "qdss_pclkdbg_clk",
1584 .ops = &clk_ops_branch,
1585 CLK_INIT(qdss_pclkdbg_clk.c),
1586 },
1587};
1588
1589static struct qdss_bank bdiv_info_qdss_trace = {
1590 .bank_sel_mask = BIT(0),
1591 .ns_reg = QDSS_TRACECLKIN_CLK_SRC1_NS_REG,
1592 .ns_mask = BM(6, 0),
1593};
1594
1595static struct rcg_clk qdss_traceclkin_clk = {
1596 .b = {
1597 .ctl_reg = QDSS_TRACECLKIN_CTL_REG,
1598 .en_mask = BIT(4),
1599 .reset_reg = QDSS_RESETS_REG,
1600 .reset_mask = BIT(0),
1601 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1602 .halt_bit = 8,
1603 .halt_check = HALT_VOTED,
1604 },
1605 .ns_reg = QDSS_TRACECLKIN_CLK_SRC_CTL_REG,
1606 .set_rate = set_rate_qdss,
1607 .freq_tbl = clk_tbl_qdss,
1608 .bank_info = &bdiv_info_qdss_trace,
1609 .current_freq = &rcg_dummy_freq,
1610 .c = {
1611 .dbg_name = "qdss_traceclkin_clk",
1612 .ops = &clk_ops_qdss,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001613 VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001614 CLK_INIT(qdss_traceclkin_clk.c),
1615 },
1616};
1617
1618static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001619 F_QDSS( 27000000, pxo, 1),
1620 F_QDSS(200000000, pll3, 6),
1621 F_QDSS(400000000, pll3, 3),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001622 F_END
1623};
1624
1625static struct qdss_bank bdiv_info_qdss_tsctr = {
1626 .bank_sel_mask = BIT(0),
1627 .ns_reg = QDSS_TSCTR_CLK_SRC1_NS_REG,
1628 .ns_mask = BM(6, 0),
1629};
1630
1631static struct rcg_clk qdss_tsctr_clk = {
1632 .b = {
1633 .ctl_reg = QDSS_TSCTR_CTL_REG,
1634 .en_mask = BIT(4),
1635 .reset_reg = QDSS_RESETS_REG,
1636 .reset_mask = BIT(3),
1637 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1638 .halt_bit = 7,
1639 .halt_check = HALT_VOTED,
1640 },
1641 .ns_reg = QDSS_TSCTR_CLK_SRC_CTL_REG,
1642 .set_rate = set_rate_qdss,
1643 .freq_tbl = clk_tbl_qdss_tsctr,
1644 .bank_info = &bdiv_info_qdss_tsctr,
1645 .current_freq = &rcg_dummy_freq,
1646 .c = {
1647 .dbg_name = "qdss_tsctr_clk",
1648 .ops = &clk_ops_qdss,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001649 VDD_DIG_FMAX_MAP2(LOW, 200000000, NOMINAL, 400000000),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001650 CLK_INIT(qdss_tsctr_clk.c),
1651 },
1652};
1653
1654static struct branch_clk qdss_stm_clk = {
1655 .b = {
1656 .ctl_reg = QDSS_STM_CLK_CTL_REG,
1657 .en_mask = BIT(4),
1658 .reset_reg = QDSS_RESETS_REG,
1659 .reset_mask = BIT(1),
1660 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1661 .halt_bit = 20,
1662 .halt_check = HALT_VOTED,
1663 },
1664 .c = {
1665 .dbg_name = "qdss_stm_clk",
1666 .ops = &clk_ops_branch,
1667 CLK_INIT(qdss_stm_clk.c),
1668 },
1669};
1670
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001671#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001672 { \
1673 .freq_hz = f, \
1674 .src_clk = &s##_clk.c, \
1675 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001676 }
1677static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001678 F_PDM( 0, gnd, 1),
1679 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001680 F_END
1681};
1682
1683static struct rcg_clk pdm_clk = {
1684 .b = {
1685 .ctl_reg = PDM_CLK_NS_REG,
1686 .en_mask = BIT(9),
1687 .reset_reg = PDM_CLK_NS_REG,
1688 .reset_mask = BIT(12),
1689 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1690 .halt_bit = 3,
1691 },
1692 .ns_reg = PDM_CLK_NS_REG,
1693 .root_en_mask = BIT(11),
1694 .ns_mask = BM(1, 0),
1695 .set_rate = set_rate_nop,
1696 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001697 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001698 .c = {
1699 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001700 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001701 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001702 CLK_INIT(pdm_clk.c),
1703 },
1704};
1705
1706static struct branch_clk pmem_clk = {
1707 .b = {
1708 .ctl_reg = PMEM_ACLK_CTL_REG,
1709 .en_mask = BIT(4),
1710 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1711 .halt_bit = 20,
1712 },
1713 .c = {
1714 .dbg_name = "pmem_clk",
1715 .ops = &clk_ops_branch,
1716 CLK_INIT(pmem_clk.c),
1717 },
1718};
1719
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001720#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001721 { \
1722 .freq_hz = f, \
1723 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001724 }
1725static struct clk_freq_tbl clk_tbl_prng[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001726 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001727 F_END
1728};
1729
1730static struct rcg_clk prng_clk = {
1731 .b = {
1732 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1733 .en_mask = BIT(10),
1734 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1735 .halt_check = HALT_VOTED,
1736 .halt_bit = 10,
1737 },
1738 .set_rate = set_rate_nop,
1739 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001740 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001741 .c = {
1742 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001743 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001744 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001745 CLK_INIT(prng_clk.c),
1746 },
1747};
1748
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001749#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001750 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001751 .b = { \
1752 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1753 .en_mask = BIT(9), \
1754 .reset_reg = SDCn_RESET_REG(n), \
1755 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001756 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001757 .halt_bit = h_b, \
1758 }, \
1759 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1760 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1761 .root_en_mask = BIT(11), \
1762 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1763 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001764 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001765 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001766 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001767 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001768 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001769 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001770 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001771 }, \
1772 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001773#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001774 { \
1775 .freq_hz = f, \
1776 .src_clk = &s##_clk.c, \
1777 .md_val = MD8(16, m, 0, n), \
1778 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1779 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001780 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001781static struct clk_freq_tbl clk_tbl_sdc[] = {
1782 F_SDC( 0, gnd, 1, 0, 0),
1783 F_SDC( 144000, pxo, 3, 2, 125),
1784 F_SDC( 400000, pll8, 4, 1, 240),
1785 F_SDC( 16000000, pll8, 4, 1, 6),
1786 F_SDC( 17070000, pll8, 1, 2, 45),
1787 F_SDC( 20210000, pll8, 1, 1, 19),
1788 F_SDC( 24000000, pll8, 4, 1, 4),
1789 F_SDC( 48000000, pll8, 4, 1, 2),
1790 F_SDC( 64000000, pll8, 3, 1, 2),
1791 F_SDC( 96000000, pll8, 4, 0, 0),
Subhash Jadavanibd238ba2011-11-24 15:12:39 +05301792 F_SDC(192000000, pll8, 2, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001793 F_END
1794};
1795
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001796static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1797static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1798static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1799static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1800static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001801
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001802#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001803 { \
1804 .freq_hz = f, \
1805 .src_clk = &s##_clk.c, \
1806 .md_val = MD16(m, n), \
1807 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1808 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001809 }
1810static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001811 F_TSIF_REF( 0, gnd, 1, 0, 0),
1812 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001813 F_END
1814};
1815
1816static struct rcg_clk tsif_ref_clk = {
1817 .b = {
1818 .ctl_reg = TSIF_REF_CLK_NS_REG,
1819 .en_mask = BIT(9),
1820 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1821 .halt_bit = 5,
1822 },
1823 .ns_reg = TSIF_REF_CLK_NS_REG,
1824 .md_reg = TSIF_REF_CLK_MD_REG,
1825 .root_en_mask = BIT(11),
1826 .ns_mask = (BM(31, 16) | BM(6, 0)),
1827 .set_rate = set_rate_mnd,
1828 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001829 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001830 .c = {
1831 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001832 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001833 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001834 CLK_INIT(tsif_ref_clk.c),
1835 },
1836};
1837
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001838#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001839 { \
1840 .freq_hz = f, \
1841 .src_clk = &s##_clk.c, \
1842 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001843 }
1844static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001845 F_TSSC( 0, gnd),
1846 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001847 F_END
1848};
1849
1850static struct rcg_clk tssc_clk = {
1851 .b = {
1852 .ctl_reg = TSSC_CLK_CTL_REG,
1853 .en_mask = BIT(4),
1854 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1855 .halt_bit = 4,
1856 },
1857 .ns_reg = TSSC_CLK_CTL_REG,
1858 .ns_mask = BM(1, 0),
1859 .set_rate = set_rate_nop,
1860 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001861 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001862 .c = {
1863 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001864 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001865 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001866 CLK_INIT(tssc_clk.c),
1867 },
1868};
1869
Tianyi Gou41515e22011-09-01 19:37:43 -07001870#define CLK_USB_HS(name, n, h_b) \
1871 static struct rcg_clk name = { \
1872 .b = { \
1873 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1874 .en_mask = BIT(9), \
1875 .reset_reg = USB_HS##n##_RESET_REG, \
1876 .reset_mask = BIT(0), \
1877 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1878 .halt_bit = h_b, \
1879 }, \
1880 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1881 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1882 .root_en_mask = BIT(11), \
1883 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1884 .set_rate = set_rate_mnd, \
1885 .freq_tbl = clk_tbl_usb, \
1886 .current_freq = &rcg_dummy_freq, \
1887 .c = { \
1888 .dbg_name = #name, \
1889 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001890 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001891 CLK_INIT(name.c), \
1892 }, \
1893}
1894
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001895#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001896 { \
1897 .freq_hz = f, \
1898 .src_clk = &s##_clk.c, \
1899 .md_val = MD8(16, m, 0, n), \
1900 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1901 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001902 }
1903static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001904 F_USB( 0, gnd, 1, 0, 0),
1905 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001906 F_END
1907};
1908
Tianyi Gou41515e22011-09-01 19:37:43 -07001909CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1910CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1911CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001912
Stephen Boyd94625ef2011-07-12 17:06:01 -07001913static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001914 F_USB( 0, gnd, 1, 0, 0),
1915 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001916 F_END
1917};
1918
1919static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1920 .b = {
1921 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1922 .en_mask = BIT(9),
1923 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1924 .halt_bit = 26,
1925 },
1926 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1927 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1928 .root_en_mask = BIT(11),
1929 .ns_mask = (BM(23, 16) | BM(6, 0)),
1930 .set_rate = set_rate_mnd,
1931 .freq_tbl = clk_tbl_usb_hsic,
1932 .current_freq = &rcg_dummy_freq,
1933 .c = {
1934 .dbg_name = "usb_hsic_xcvr_fs_clk",
1935 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001936 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001937 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1938 },
1939};
1940
1941static struct branch_clk usb_hsic_system_clk = {
1942 .b = {
1943 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1944 .en_mask = BIT(4),
1945 .reset_reg = USB_HSIC_RESET_REG,
1946 .reset_mask = BIT(0),
1947 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1948 .halt_bit = 24,
1949 },
1950 .parent = &usb_hsic_xcvr_fs_clk.c,
1951 .c = {
1952 .dbg_name = "usb_hsic_system_clk",
1953 .ops = &clk_ops_branch,
1954 CLK_INIT(usb_hsic_system_clk.c),
1955 },
1956};
1957
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001958#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001959 { \
1960 .freq_hz = f, \
1961 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001962 }
1963static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001964 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001965 F_END
1966};
1967
1968static struct rcg_clk usb_hsic_hsic_src_clk = {
1969 .b = {
1970 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1971 .halt_check = NOCHECK,
1972 },
1973 .root_en_mask = BIT(0),
1974 .set_rate = set_rate_nop,
1975 .freq_tbl = clk_tbl_usb2_hsic,
1976 .current_freq = &rcg_dummy_freq,
1977 .c = {
1978 .dbg_name = "usb_hsic_hsic_src_clk",
1979 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001980 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001981 CLK_INIT(usb_hsic_hsic_src_clk.c),
1982 },
1983};
1984
1985static struct branch_clk usb_hsic_hsic_clk = {
1986 .b = {
1987 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1988 .en_mask = BIT(0),
1989 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1990 .halt_bit = 19,
1991 },
1992 .parent = &usb_hsic_hsic_src_clk.c,
1993 .c = {
1994 .dbg_name = "usb_hsic_hsic_clk",
1995 .ops = &clk_ops_branch,
1996 CLK_INIT(usb_hsic_hsic_clk.c),
1997 },
1998};
1999
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002000#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002001 { \
2002 .freq_hz = f, \
2003 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002004 }
2005static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002006 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002007 F_END
2008};
2009
2010static struct rcg_clk usb_hsic_hsio_cal_clk = {
2011 .b = {
2012 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
2013 .en_mask = BIT(0),
2014 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2015 .halt_bit = 23,
2016 },
2017 .set_rate = set_rate_nop,
2018 .freq_tbl = clk_tbl_usb_hsio_cal,
2019 .current_freq = &rcg_dummy_freq,
2020 .c = {
2021 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyda0e82ec2011-09-19 12:18:45 -07002022 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002023 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002024 CLK_INIT(usb_hsic_hsio_cal_clk.c),
2025 },
2026};
2027
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002028static struct branch_clk usb_phy0_clk = {
2029 .b = {
2030 .reset_reg = USB_PHY0_RESET_REG,
2031 .reset_mask = BIT(0),
2032 },
2033 .c = {
2034 .dbg_name = "usb_phy0_clk",
2035 .ops = &clk_ops_reset,
2036 CLK_INIT(usb_phy0_clk.c),
2037 },
2038};
2039
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002040#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002041 struct rcg_clk i##_clk = { \
2042 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
2043 .b = { \
2044 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
2045 .halt_check = NOCHECK, \
2046 }, \
2047 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
2048 .root_en_mask = BIT(11), \
2049 .ns_mask = (BM(23, 16) | BM(6, 0)), \
2050 .set_rate = set_rate_mnd, \
2051 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002052 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002053 .c = { \
2054 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002055 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002056 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002057 CLK_INIT(i##_clk.c), \
2058 }, \
2059 }
2060
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002061static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002062static struct branch_clk usb_fs1_xcvr_clk = {
2063 .b = {
2064 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
2065 .en_mask = BIT(9),
2066 .reset_reg = USB_FSn_RESET_REG(1),
2067 .reset_mask = BIT(1),
2068 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2069 .halt_bit = 15,
2070 },
2071 .parent = &usb_fs1_src_clk.c,
2072 .c = {
2073 .dbg_name = "usb_fs1_xcvr_clk",
2074 .ops = &clk_ops_branch,
2075 CLK_INIT(usb_fs1_xcvr_clk.c),
2076 },
2077};
2078
2079static struct branch_clk usb_fs1_sys_clk = {
2080 .b = {
2081 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
2082 .en_mask = BIT(4),
2083 .reset_reg = USB_FSn_RESET_REG(1),
2084 .reset_mask = BIT(0),
2085 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2086 .halt_bit = 16,
2087 },
2088 .parent = &usb_fs1_src_clk.c,
2089 .c = {
2090 .dbg_name = "usb_fs1_sys_clk",
2091 .ops = &clk_ops_branch,
2092 CLK_INIT(usb_fs1_sys_clk.c),
2093 },
2094};
2095
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002096static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002097static struct branch_clk usb_fs2_xcvr_clk = {
2098 .b = {
2099 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
2100 .en_mask = BIT(9),
2101 .reset_reg = USB_FSn_RESET_REG(2),
2102 .reset_mask = BIT(1),
2103 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2104 .halt_bit = 12,
2105 },
2106 .parent = &usb_fs2_src_clk.c,
2107 .c = {
2108 .dbg_name = "usb_fs2_xcvr_clk",
2109 .ops = &clk_ops_branch,
2110 CLK_INIT(usb_fs2_xcvr_clk.c),
2111 },
2112};
2113
2114static struct branch_clk usb_fs2_sys_clk = {
2115 .b = {
2116 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
2117 .en_mask = BIT(4),
2118 .reset_reg = USB_FSn_RESET_REG(2),
2119 .reset_mask = BIT(0),
2120 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2121 .halt_bit = 13,
2122 },
2123 .parent = &usb_fs2_src_clk.c,
2124 .c = {
2125 .dbg_name = "usb_fs2_sys_clk",
2126 .ops = &clk_ops_branch,
2127 CLK_INIT(usb_fs2_sys_clk.c),
2128 },
2129};
2130
2131/* Fast Peripheral Bus Clocks */
2132static struct branch_clk ce1_core_clk = {
2133 .b = {
2134 .ctl_reg = CE1_CORE_CLK_CTL_REG,
2135 .en_mask = BIT(4),
2136 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2137 .halt_bit = 27,
2138 },
2139 .c = {
2140 .dbg_name = "ce1_core_clk",
2141 .ops = &clk_ops_branch,
2142 CLK_INIT(ce1_core_clk.c),
2143 },
2144};
Tianyi Gou41515e22011-09-01 19:37:43 -07002145
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002146static struct branch_clk ce1_p_clk = {
2147 .b = {
2148 .ctl_reg = CE1_HCLK_CTL_REG,
2149 .en_mask = BIT(4),
2150 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2151 .halt_bit = 1,
2152 },
2153 .c = {
2154 .dbg_name = "ce1_p_clk",
2155 .ops = &clk_ops_branch,
2156 CLK_INIT(ce1_p_clk.c),
2157 },
2158};
2159
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002160#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07002161 { \
2162 .freq_hz = f, \
2163 .src_clk = &s##_clk.c, \
2164 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07002165 }
2166
2167static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002168 F_CE3( 0, gnd, 1),
2169 F_CE3( 48000000, pll8, 8),
2170 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07002171 F_END
2172};
2173
2174static struct rcg_clk ce3_src_clk = {
2175 .b = {
2176 .ctl_reg = CE3_CLK_SRC_NS_REG,
2177 .halt_check = NOCHECK,
2178 },
2179 .ns_reg = CE3_CLK_SRC_NS_REG,
2180 .root_en_mask = BIT(7),
2181 .ns_mask = BM(6, 0),
2182 .set_rate = set_rate_nop,
2183 .freq_tbl = clk_tbl_ce3,
2184 .current_freq = &rcg_dummy_freq,
2185 .c = {
2186 .dbg_name = "ce3_src_clk",
2187 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002188 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07002189 CLK_INIT(ce3_src_clk.c),
2190 },
2191};
2192
2193static struct branch_clk ce3_core_clk = {
2194 .b = {
2195 .ctl_reg = CE3_CORE_CLK_CTL_REG,
2196 .en_mask = BIT(4),
2197 .reset_reg = CE3_CORE_CLK_CTL_REG,
2198 .reset_mask = BIT(7),
2199 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2200 .halt_bit = 5,
2201 },
2202 .parent = &ce3_src_clk.c,
2203 .c = {
2204 .dbg_name = "ce3_core_clk",
2205 .ops = &clk_ops_branch,
2206 CLK_INIT(ce3_core_clk.c),
2207 }
2208};
2209
2210static struct branch_clk ce3_p_clk = {
2211 .b = {
2212 .ctl_reg = CE3_HCLK_CTL_REG,
2213 .en_mask = BIT(4),
2214 .reset_reg = CE3_HCLK_CTL_REG,
2215 .reset_mask = BIT(7),
2216 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
2217 .halt_bit = 16,
2218 },
2219 .parent = &ce3_src_clk.c,
2220 .c = {
2221 .dbg_name = "ce3_p_clk",
2222 .ops = &clk_ops_branch,
2223 CLK_INIT(ce3_p_clk.c),
2224 }
2225};
2226
2227static struct branch_clk sata_phy_ref_clk = {
2228 .b = {
2229 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
2230 .en_mask = BIT(4),
2231 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2232 .halt_bit = 24,
2233 },
2234 .parent = &pxo_clk.c,
2235 .c = {
2236 .dbg_name = "sata_phy_ref_clk",
2237 .ops = &clk_ops_branch,
2238 CLK_INIT(sata_phy_ref_clk.c),
2239 },
2240};
2241
2242static struct branch_clk pcie_p_clk = {
2243 .b = {
2244 .ctl_reg = PCIE_HCLK_CTL_REG,
2245 .en_mask = BIT(4),
2246 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2247 .halt_bit = 8,
2248 },
2249 .c = {
2250 .dbg_name = "pcie_p_clk",
2251 .ops = &clk_ops_branch,
2252 CLK_INIT(pcie_p_clk.c),
2253 },
2254};
2255
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002256static struct branch_clk dma_bam_p_clk = {
2257 .b = {
2258 .ctl_reg = DMA_BAM_HCLK_CTL,
2259 .en_mask = BIT(4),
2260 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2261 .halt_bit = 12,
2262 },
2263 .c = {
2264 .dbg_name = "dma_bam_p_clk",
2265 .ops = &clk_ops_branch,
2266 CLK_INIT(dma_bam_p_clk.c),
2267 },
2268};
2269
2270static struct branch_clk gsbi1_p_clk = {
2271 .b = {
2272 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
2273 .en_mask = BIT(4),
2274 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2275 .halt_bit = 11,
2276 },
2277 .c = {
2278 .dbg_name = "gsbi1_p_clk",
2279 .ops = &clk_ops_branch,
2280 CLK_INIT(gsbi1_p_clk.c),
2281 },
2282};
2283
2284static struct branch_clk gsbi2_p_clk = {
2285 .b = {
2286 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2287 .en_mask = BIT(4),
2288 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2289 .halt_bit = 7,
2290 },
2291 .c = {
2292 .dbg_name = "gsbi2_p_clk",
2293 .ops = &clk_ops_branch,
2294 CLK_INIT(gsbi2_p_clk.c),
2295 },
2296};
2297
2298static struct branch_clk gsbi3_p_clk = {
2299 .b = {
2300 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2301 .en_mask = BIT(4),
2302 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2303 .halt_bit = 3,
2304 },
2305 .c = {
2306 .dbg_name = "gsbi3_p_clk",
2307 .ops = &clk_ops_branch,
2308 CLK_INIT(gsbi3_p_clk.c),
2309 },
2310};
2311
2312static struct branch_clk gsbi4_p_clk = {
2313 .b = {
2314 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2315 .en_mask = BIT(4),
2316 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2317 .halt_bit = 27,
2318 },
2319 .c = {
2320 .dbg_name = "gsbi4_p_clk",
2321 .ops = &clk_ops_branch,
2322 CLK_INIT(gsbi4_p_clk.c),
2323 },
2324};
2325
2326static struct branch_clk gsbi5_p_clk = {
2327 .b = {
2328 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2329 .en_mask = BIT(4),
2330 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2331 .halt_bit = 23,
2332 },
2333 .c = {
2334 .dbg_name = "gsbi5_p_clk",
2335 .ops = &clk_ops_branch,
2336 CLK_INIT(gsbi5_p_clk.c),
2337 },
2338};
2339
2340static struct branch_clk gsbi6_p_clk = {
2341 .b = {
2342 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2343 .en_mask = BIT(4),
2344 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2345 .halt_bit = 19,
2346 },
2347 .c = {
2348 .dbg_name = "gsbi6_p_clk",
2349 .ops = &clk_ops_branch,
2350 CLK_INIT(gsbi6_p_clk.c),
2351 },
2352};
2353
2354static struct branch_clk gsbi7_p_clk = {
2355 .b = {
2356 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2357 .en_mask = BIT(4),
2358 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2359 .halt_bit = 15,
2360 },
2361 .c = {
2362 .dbg_name = "gsbi7_p_clk",
2363 .ops = &clk_ops_branch,
2364 CLK_INIT(gsbi7_p_clk.c),
2365 },
2366};
2367
2368static struct branch_clk gsbi8_p_clk = {
2369 .b = {
2370 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2371 .en_mask = BIT(4),
2372 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2373 .halt_bit = 11,
2374 },
2375 .c = {
2376 .dbg_name = "gsbi8_p_clk",
2377 .ops = &clk_ops_branch,
2378 CLK_INIT(gsbi8_p_clk.c),
2379 },
2380};
2381
2382static struct branch_clk gsbi9_p_clk = {
2383 .b = {
2384 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2385 .en_mask = BIT(4),
2386 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2387 .halt_bit = 7,
2388 },
2389 .c = {
2390 .dbg_name = "gsbi9_p_clk",
2391 .ops = &clk_ops_branch,
2392 CLK_INIT(gsbi9_p_clk.c),
2393 },
2394};
2395
2396static struct branch_clk gsbi10_p_clk = {
2397 .b = {
2398 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2399 .en_mask = BIT(4),
2400 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2401 .halt_bit = 3,
2402 },
2403 .c = {
2404 .dbg_name = "gsbi10_p_clk",
2405 .ops = &clk_ops_branch,
2406 CLK_INIT(gsbi10_p_clk.c),
2407 },
2408};
2409
2410static struct branch_clk gsbi11_p_clk = {
2411 .b = {
2412 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2413 .en_mask = BIT(4),
2414 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2415 .halt_bit = 18,
2416 },
2417 .c = {
2418 .dbg_name = "gsbi11_p_clk",
2419 .ops = &clk_ops_branch,
2420 CLK_INIT(gsbi11_p_clk.c),
2421 },
2422};
2423
2424static struct branch_clk gsbi12_p_clk = {
2425 .b = {
2426 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2427 .en_mask = BIT(4),
2428 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2429 .halt_bit = 14,
2430 },
2431 .c = {
2432 .dbg_name = "gsbi12_p_clk",
2433 .ops = &clk_ops_branch,
2434 CLK_INIT(gsbi12_p_clk.c),
2435 },
2436};
2437
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002438static struct branch_clk qdss_p_clk = {
2439 .b = {
2440 .ctl_reg = QDSS_HCLK_CTL_REG,
2441 .en_mask = BIT(4),
2442 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2443 .halt_bit = 11,
2444 .halt_check = HALT_VOTED,
2445 .reset_reg = QDSS_RESETS_REG,
2446 .reset_mask = BIT(2),
2447 },
2448 .c = {
2449 .dbg_name = "qdss_p_clk",
2450 .ops = &clk_ops_branch,
2451 CLK_INIT(qdss_p_clk.c),
Tianyi Gou41515e22011-09-01 19:37:43 -07002452 }
2453};
2454
2455static struct branch_clk sata_phy_cfg_clk = {
2456 .b = {
2457 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2458 .en_mask = BIT(4),
2459 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2460 .halt_bit = 12,
2461 },
2462 .c = {
2463 .dbg_name = "sata_phy_cfg_clk",
2464 .ops = &clk_ops_branch,
2465 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002466 },
2467};
2468
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002469static struct branch_clk tsif_p_clk = {
2470 .b = {
2471 .ctl_reg = TSIF_HCLK_CTL_REG,
2472 .en_mask = BIT(4),
2473 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2474 .halt_bit = 7,
2475 },
2476 .c = {
2477 .dbg_name = "tsif_p_clk",
2478 .ops = &clk_ops_branch,
2479 CLK_INIT(tsif_p_clk.c),
2480 },
2481};
2482
2483static struct branch_clk usb_fs1_p_clk = {
2484 .b = {
2485 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2486 .en_mask = BIT(4),
2487 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2488 .halt_bit = 17,
2489 },
2490 .c = {
2491 .dbg_name = "usb_fs1_p_clk",
2492 .ops = &clk_ops_branch,
2493 CLK_INIT(usb_fs1_p_clk.c),
2494 },
2495};
2496
2497static struct branch_clk usb_fs2_p_clk = {
2498 .b = {
2499 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2500 .en_mask = BIT(4),
2501 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2502 .halt_bit = 14,
2503 },
2504 .c = {
2505 .dbg_name = "usb_fs2_p_clk",
2506 .ops = &clk_ops_branch,
2507 CLK_INIT(usb_fs2_p_clk.c),
2508 },
2509};
2510
2511static struct branch_clk usb_hs1_p_clk = {
2512 .b = {
2513 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2514 .en_mask = BIT(4),
2515 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2516 .halt_bit = 1,
2517 },
2518 .c = {
2519 .dbg_name = "usb_hs1_p_clk",
2520 .ops = &clk_ops_branch,
2521 CLK_INIT(usb_hs1_p_clk.c),
2522 },
2523};
2524
Tianyi Gou41515e22011-09-01 19:37:43 -07002525static struct branch_clk usb_hs3_p_clk = {
2526 .b = {
2527 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2528 .en_mask = BIT(4),
2529 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2530 .halt_bit = 31,
2531 },
2532 .c = {
2533 .dbg_name = "usb_hs3_p_clk",
2534 .ops = &clk_ops_branch,
2535 CLK_INIT(usb_hs3_p_clk.c),
2536 },
2537};
2538
2539static struct branch_clk usb_hs4_p_clk = {
2540 .b = {
2541 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2542 .en_mask = BIT(4),
2543 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2544 .halt_bit = 7,
2545 },
2546 .c = {
2547 .dbg_name = "usb_hs4_p_clk",
2548 .ops = &clk_ops_branch,
2549 CLK_INIT(usb_hs4_p_clk.c),
2550 },
2551};
2552
Stephen Boyd94625ef2011-07-12 17:06:01 -07002553static struct branch_clk usb_hsic_p_clk = {
2554 .b = {
2555 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2556 .en_mask = BIT(4),
2557 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2558 .halt_bit = 28,
2559 },
2560 .c = {
2561 .dbg_name = "usb_hsic_p_clk",
2562 .ops = &clk_ops_branch,
2563 CLK_INIT(usb_hsic_p_clk.c),
2564 },
2565};
2566
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002567static struct branch_clk sdc1_p_clk = {
2568 .b = {
2569 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2570 .en_mask = BIT(4),
2571 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2572 .halt_bit = 11,
2573 },
2574 .c = {
2575 .dbg_name = "sdc1_p_clk",
2576 .ops = &clk_ops_branch,
2577 CLK_INIT(sdc1_p_clk.c),
2578 },
2579};
2580
2581static struct branch_clk sdc2_p_clk = {
2582 .b = {
2583 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2584 .en_mask = BIT(4),
2585 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2586 .halt_bit = 10,
2587 },
2588 .c = {
2589 .dbg_name = "sdc2_p_clk",
2590 .ops = &clk_ops_branch,
2591 CLK_INIT(sdc2_p_clk.c),
2592 },
2593};
2594
2595static struct branch_clk sdc3_p_clk = {
2596 .b = {
2597 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2598 .en_mask = BIT(4),
2599 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2600 .halt_bit = 9,
2601 },
2602 .c = {
2603 .dbg_name = "sdc3_p_clk",
2604 .ops = &clk_ops_branch,
2605 CLK_INIT(sdc3_p_clk.c),
2606 },
2607};
2608
2609static struct branch_clk sdc4_p_clk = {
2610 .b = {
2611 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2612 .en_mask = BIT(4),
2613 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2614 .halt_bit = 8,
2615 },
2616 .c = {
2617 .dbg_name = "sdc4_p_clk",
2618 .ops = &clk_ops_branch,
2619 CLK_INIT(sdc4_p_clk.c),
2620 },
2621};
2622
2623static struct branch_clk sdc5_p_clk = {
2624 .b = {
2625 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2626 .en_mask = BIT(4),
2627 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2628 .halt_bit = 7,
2629 },
2630 .c = {
2631 .dbg_name = "sdc5_p_clk",
2632 .ops = &clk_ops_branch,
2633 CLK_INIT(sdc5_p_clk.c),
2634 },
2635};
2636
2637/* HW-Voteable Clocks */
2638static struct branch_clk adm0_clk = {
2639 .b = {
2640 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2641 .en_mask = BIT(2),
2642 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2643 .halt_check = HALT_VOTED,
2644 .halt_bit = 14,
2645 },
2646 .c = {
2647 .dbg_name = "adm0_clk",
2648 .ops = &clk_ops_branch,
2649 CLK_INIT(adm0_clk.c),
2650 },
2651};
2652
2653static struct branch_clk adm0_p_clk = {
2654 .b = {
2655 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2656 .en_mask = BIT(3),
2657 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2658 .halt_check = HALT_VOTED,
2659 .halt_bit = 13,
2660 },
2661 .c = {
2662 .dbg_name = "adm0_p_clk",
2663 .ops = &clk_ops_branch,
2664 CLK_INIT(adm0_p_clk.c),
2665 },
2666};
2667
2668static struct branch_clk pmic_arb0_p_clk = {
2669 .b = {
2670 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2671 .en_mask = BIT(8),
2672 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2673 .halt_check = HALT_VOTED,
2674 .halt_bit = 22,
2675 },
2676 .c = {
2677 .dbg_name = "pmic_arb0_p_clk",
2678 .ops = &clk_ops_branch,
2679 CLK_INIT(pmic_arb0_p_clk.c),
2680 },
2681};
2682
2683static struct branch_clk pmic_arb1_p_clk = {
2684 .b = {
2685 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2686 .en_mask = BIT(9),
2687 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2688 .halt_check = HALT_VOTED,
2689 .halt_bit = 21,
2690 },
2691 .c = {
2692 .dbg_name = "pmic_arb1_p_clk",
2693 .ops = &clk_ops_branch,
2694 CLK_INIT(pmic_arb1_p_clk.c),
2695 },
2696};
2697
2698static struct branch_clk pmic_ssbi2_clk = {
2699 .b = {
2700 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2701 .en_mask = BIT(7),
2702 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2703 .halt_check = HALT_VOTED,
2704 .halt_bit = 23,
2705 },
2706 .c = {
2707 .dbg_name = "pmic_ssbi2_clk",
2708 .ops = &clk_ops_branch,
2709 CLK_INIT(pmic_ssbi2_clk.c),
2710 },
2711};
2712
2713static struct branch_clk rpm_msg_ram_p_clk = {
2714 .b = {
2715 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2716 .en_mask = BIT(6),
2717 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2718 .halt_check = HALT_VOTED,
2719 .halt_bit = 12,
2720 },
2721 .c = {
2722 .dbg_name = "rpm_msg_ram_p_clk",
2723 .ops = &clk_ops_branch,
2724 CLK_INIT(rpm_msg_ram_p_clk.c),
2725 },
2726};
2727
2728/*
2729 * Multimedia Clocks
2730 */
2731
2732static struct branch_clk amp_clk = {
2733 .b = {
2734 .reset_reg = SW_RESET_CORE_REG,
2735 .reset_mask = BIT(20),
2736 },
2737 .c = {
2738 .dbg_name = "amp_clk",
2739 .ops = &clk_ops_reset,
2740 CLK_INIT(amp_clk.c),
2741 },
2742};
2743
Stephen Boyd94625ef2011-07-12 17:06:01 -07002744#define CLK_CAM(name, n, hb) \
2745 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002746 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002747 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002748 .en_mask = BIT(0), \
2749 .halt_reg = DBG_BUS_VEC_I_REG, \
2750 .halt_bit = hb, \
2751 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002752 .ns_reg = CAMCLK##n##_NS_REG, \
2753 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002754 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002755 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002756 .ctl_mask = BM(7, 6), \
2757 .set_rate = set_rate_mnd_8, \
2758 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002759 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002760 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002761 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002762 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002763 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002764 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002765 }, \
2766 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002767#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002768 { \
2769 .freq_hz = f, \
2770 .src_clk = &s##_clk.c, \
2771 .md_val = MD8(8, m, 0, n), \
2772 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2773 .ctl_val = CC(6, n), \
2774 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002775 }
2776static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002777 F_CAM( 0, gnd, 1, 0, 0),
2778 F_CAM( 6000000, pll8, 4, 1, 16),
2779 F_CAM( 8000000, pll8, 4, 1, 12),
2780 F_CAM( 12000000, pll8, 4, 1, 8),
2781 F_CAM( 16000000, pll8, 4, 1, 6),
2782 F_CAM( 19200000, pll8, 4, 1, 5),
2783 F_CAM( 24000000, pll8, 4, 1, 4),
2784 F_CAM( 32000000, pll8, 4, 1, 3),
2785 F_CAM( 48000000, pll8, 4, 1, 2),
2786 F_CAM( 64000000, pll8, 3, 1, 2),
2787 F_CAM( 96000000, pll8, 4, 0, 0),
2788 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002789 F_END
2790};
2791
Stephen Boyd94625ef2011-07-12 17:06:01 -07002792static CLK_CAM(cam0_clk, 0, 15);
2793static CLK_CAM(cam1_clk, 1, 16);
2794static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002795
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002796#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002797 { \
2798 .freq_hz = f, \
2799 .src_clk = &s##_clk.c, \
2800 .md_val = MD8(8, m, 0, n), \
2801 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2802 .ctl_val = CC(6, n), \
2803 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002804 }
2805static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002806 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002807 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002808 F_CSI( 85330000, pll8, 1, 2, 9),
2809 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002810 F_END
2811};
2812
2813static struct rcg_clk csi0_src_clk = {
2814 .ns_reg = CSI0_NS_REG,
2815 .b = {
2816 .ctl_reg = CSI0_CC_REG,
2817 .halt_check = NOCHECK,
2818 },
2819 .md_reg = CSI0_MD_REG,
2820 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002821 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002822 .ctl_mask = BM(7, 6),
2823 .set_rate = set_rate_mnd,
2824 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002825 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002826 .c = {
2827 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002828 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002829 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002830 CLK_INIT(csi0_src_clk.c),
2831 },
2832};
2833
2834static struct branch_clk csi0_clk = {
2835 .b = {
2836 .ctl_reg = CSI0_CC_REG,
2837 .en_mask = BIT(0),
2838 .reset_reg = SW_RESET_CORE_REG,
2839 .reset_mask = BIT(8),
2840 .halt_reg = DBG_BUS_VEC_B_REG,
2841 .halt_bit = 13,
2842 },
2843 .parent = &csi0_src_clk.c,
2844 .c = {
2845 .dbg_name = "csi0_clk",
2846 .ops = &clk_ops_branch,
2847 CLK_INIT(csi0_clk.c),
2848 },
2849};
2850
2851static struct branch_clk csi0_phy_clk = {
2852 .b = {
2853 .ctl_reg = CSI0_CC_REG,
2854 .en_mask = BIT(8),
2855 .reset_reg = SW_RESET_CORE_REG,
2856 .reset_mask = BIT(29),
2857 .halt_reg = DBG_BUS_VEC_I_REG,
2858 .halt_bit = 9,
2859 },
2860 .parent = &csi0_src_clk.c,
2861 .c = {
2862 .dbg_name = "csi0_phy_clk",
2863 .ops = &clk_ops_branch,
2864 CLK_INIT(csi0_phy_clk.c),
2865 },
2866};
2867
2868static struct rcg_clk csi1_src_clk = {
2869 .ns_reg = CSI1_NS_REG,
2870 .b = {
2871 .ctl_reg = CSI1_CC_REG,
2872 .halt_check = NOCHECK,
2873 },
2874 .md_reg = CSI1_MD_REG,
2875 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002876 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002877 .ctl_mask = BM(7, 6),
2878 .set_rate = set_rate_mnd,
2879 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002880 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002881 .c = {
2882 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002883 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002884 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002885 CLK_INIT(csi1_src_clk.c),
2886 },
2887};
2888
2889static struct branch_clk csi1_clk = {
2890 .b = {
2891 .ctl_reg = CSI1_CC_REG,
2892 .en_mask = BIT(0),
2893 .reset_reg = SW_RESET_CORE_REG,
2894 .reset_mask = BIT(18),
2895 .halt_reg = DBG_BUS_VEC_B_REG,
2896 .halt_bit = 14,
2897 },
2898 .parent = &csi1_src_clk.c,
2899 .c = {
2900 .dbg_name = "csi1_clk",
2901 .ops = &clk_ops_branch,
2902 CLK_INIT(csi1_clk.c),
2903 },
2904};
2905
2906static struct branch_clk csi1_phy_clk = {
2907 .b = {
2908 .ctl_reg = CSI1_CC_REG,
2909 .en_mask = BIT(8),
2910 .reset_reg = SW_RESET_CORE_REG,
2911 .reset_mask = BIT(28),
2912 .halt_reg = DBG_BUS_VEC_I_REG,
2913 .halt_bit = 10,
2914 },
2915 .parent = &csi1_src_clk.c,
2916 .c = {
2917 .dbg_name = "csi1_phy_clk",
2918 .ops = &clk_ops_branch,
2919 CLK_INIT(csi1_phy_clk.c),
2920 },
2921};
2922
Stephen Boyd94625ef2011-07-12 17:06:01 -07002923static struct rcg_clk csi2_src_clk = {
2924 .ns_reg = CSI2_NS_REG,
2925 .b = {
2926 .ctl_reg = CSI2_CC_REG,
2927 .halt_check = NOCHECK,
2928 },
2929 .md_reg = CSI2_MD_REG,
2930 .root_en_mask = BIT(2),
2931 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
2932 .ctl_mask = BM(7, 6),
2933 .set_rate = set_rate_mnd,
2934 .freq_tbl = clk_tbl_csi,
2935 .current_freq = &rcg_dummy_freq,
2936 .c = {
2937 .dbg_name = "csi2_src_clk",
2938 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002939 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002940 CLK_INIT(csi2_src_clk.c),
2941 },
2942};
2943
2944static struct branch_clk csi2_clk = {
2945 .b = {
2946 .ctl_reg = CSI2_CC_REG,
2947 .en_mask = BIT(0),
2948 .reset_reg = SW_RESET_CORE2_REG,
2949 .reset_mask = BIT(2),
2950 .halt_reg = DBG_BUS_VEC_B_REG,
2951 .halt_bit = 29,
2952 },
2953 .parent = &csi2_src_clk.c,
2954 .c = {
2955 .dbg_name = "csi2_clk",
2956 .ops = &clk_ops_branch,
2957 CLK_INIT(csi2_clk.c),
2958 },
2959};
2960
2961static struct branch_clk csi2_phy_clk = {
2962 .b = {
2963 .ctl_reg = CSI2_CC_REG,
2964 .en_mask = BIT(8),
2965 .reset_reg = SW_RESET_CORE_REG,
2966 .reset_mask = BIT(31),
2967 .halt_reg = DBG_BUS_VEC_I_REG,
2968 .halt_bit = 29,
2969 },
2970 .parent = &csi2_src_clk.c,
2971 .c = {
2972 .dbg_name = "csi2_phy_clk",
2973 .ops = &clk_ops_branch,
2974 CLK_INIT(csi2_phy_clk.c),
2975 },
2976};
2977
Stephen Boyd092fd182011-10-21 15:56:30 -07002978static struct clk *pix_rdi_mux_map[] = {
2979 [0] = &csi0_clk.c,
2980 [1] = &csi1_clk.c,
2981 [2] = &csi2_clk.c,
2982 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002983};
2984
Stephen Boyd092fd182011-10-21 15:56:30 -07002985struct pix_rdi_clk {
2986 bool enabled;
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002987 unsigned long cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002988
2989 void __iomem *const s_reg;
2990 u32 s_mask;
2991
2992 void __iomem *const s2_reg;
2993 u32 s2_mask;
2994
2995 struct branch b;
2996 struct clk c;
2997};
2998
2999static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk)
3000{
3001 return container_of(clk, struct pix_rdi_clk, c);
3002}
3003
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07003004static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate)
Stephen Boyd092fd182011-10-21 15:56:30 -07003005{
3006 int ret, i;
3007 u32 reg;
3008 unsigned long flags;
3009 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
3010 struct clk **mux_map = pix_rdi_mux_map;
3011
3012 /*
3013 * These clocks select three inputs via two muxes. One mux selects
3014 * between csi0 and csi1 and the second mux selects between that mux's
3015 * output and csi2. The source and destination selections for each
3016 * mux must be clocking for the switch to succeed so just turn on
3017 * all three sources because it's easier than figuring out what source
3018 * needs to be on at what time.
3019 */
3020 for (i = 0; mux_map[i]; i++) {
3021 ret = clk_enable(mux_map[i]);
3022 if (ret)
3023 goto err;
3024 }
3025 if (rate >= i) {
3026 ret = -EINVAL;
3027 goto err;
3028 }
3029 /* Keep the new source on when switching inputs of an enabled clock */
3030 if (clk->enabled) {
3031 clk_disable(mux_map[clk->cur_rate]);
3032 clk_enable(mux_map[rate]);
3033 }
3034 spin_lock_irqsave(&local_clock_reg_lock, flags);
3035 reg = readl_relaxed(clk->s2_reg);
3036 reg &= ~clk->s2_mask;
3037 reg |= rate == 2 ? clk->s2_mask : 0;
3038 writel_relaxed(reg, clk->s2_reg);
3039 /*
3040 * Wait at least 6 cycles of slowest clock
3041 * for the glitch-free MUX to fully switch sources.
3042 */
3043 mb();
3044 udelay(1);
3045 reg = readl_relaxed(clk->s_reg);
3046 reg &= ~clk->s_mask;
3047 reg |= rate == 1 ? clk->s_mask : 0;
3048 writel_relaxed(reg, clk->s_reg);
3049 /*
3050 * Wait at least 6 cycles of slowest clock
3051 * for the glitch-free MUX to fully switch sources.
3052 */
3053 mb();
3054 udelay(1);
3055 clk->cur_rate = rate;
3056 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3057err:
3058 for (i--; i >= 0; i--)
3059 clk_disable(mux_map[i]);
3060
3061 return 0;
3062}
3063
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07003064static unsigned long pix_rdi_clk_get_rate(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07003065{
3066 return to_pix_rdi_clk(c)->cur_rate;
3067}
3068
3069static int pix_rdi_clk_enable(struct clk *c)
3070{
3071 unsigned long flags;
3072 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
3073
3074 spin_lock_irqsave(&local_clock_reg_lock, flags);
3075 __branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
3076 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3077 clk->enabled = true;
3078
3079 return 0;
3080}
3081
3082static void pix_rdi_clk_disable(struct clk *c)
3083{
3084 unsigned long flags;
3085 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
3086
3087 spin_lock_irqsave(&local_clock_reg_lock, flags);
3088 __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
3089 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3090 clk->enabled = false;
3091}
3092
3093static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action)
3094{
3095 return branch_reset(&to_pix_rdi_clk(clk)->b, action);
3096}
3097
3098static struct clk *pix_rdi_clk_get_parent(struct clk *c)
3099{
3100 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
3101
3102 return pix_rdi_mux_map[clk->cur_rate];
3103}
3104
3105static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
3106{
3107 if (pix_rdi_mux_map[n])
3108 return n;
3109 return -ENXIO;
3110}
3111
3112static int pix_rdi_clk_handoff(struct clk *c)
3113{
3114 u32 reg;
3115 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
3116
3117 reg = readl_relaxed(clk->s_reg);
3118 clk->cur_rate = reg & clk->s_mask ? 1 : 0;
3119 reg = readl_relaxed(clk->s2_reg);
3120 clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate;
3121 return 0;
3122}
3123
3124static struct clk_ops clk_ops_pix_rdi_8960 = {
3125 .enable = pix_rdi_clk_enable,
3126 .disable = pix_rdi_clk_disable,
3127 .auto_off = pix_rdi_clk_disable,
3128 .handoff = pix_rdi_clk_handoff,
3129 .set_rate = pix_rdi_clk_set_rate,
3130 .get_rate = pix_rdi_clk_get_rate,
3131 .list_rate = pix_rdi_clk_list_rate,
3132 .reset = pix_rdi_clk_reset,
3133 .is_local = local_clk_is_local,
3134 .get_parent = pix_rdi_clk_get_parent,
3135};
3136
3137static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003138 .b = {
3139 .ctl_reg = MISC_CC_REG,
3140 .en_mask = BIT(26),
3141 .halt_check = DELAY,
3142 .reset_reg = SW_RESET_CORE_REG,
3143 .reset_mask = BIT(26),
3144 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003145 .s_reg = MISC_CC_REG,
3146 .s_mask = BIT(25),
3147 .s2_reg = MISC_CC3_REG,
3148 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003149 .c = {
3150 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003151 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003152 CLK_INIT(csi_pix_clk.c),
3153 },
3154};
3155
Stephen Boyd092fd182011-10-21 15:56:30 -07003156static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003157 .b = {
3158 .ctl_reg = MISC_CC3_REG,
3159 .en_mask = BIT(10),
3160 .halt_check = DELAY,
3161 .reset_reg = SW_RESET_CORE_REG,
3162 .reset_mask = BIT(30),
3163 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003164 .s_reg = MISC_CC3_REG,
3165 .s_mask = BIT(8),
3166 .s2_reg = MISC_CC3_REG,
3167 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003168 .c = {
3169 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003170 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003171 CLK_INIT(csi_pix1_clk.c),
3172 },
3173};
3174
Stephen Boyd092fd182011-10-21 15:56:30 -07003175static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003176 .b = {
3177 .ctl_reg = MISC_CC_REG,
3178 .en_mask = BIT(13),
3179 .halt_check = DELAY,
3180 .reset_reg = SW_RESET_CORE_REG,
3181 .reset_mask = BIT(27),
3182 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003183 .s_reg = MISC_CC_REG,
3184 .s_mask = BIT(12),
3185 .s2_reg = MISC_CC3_REG,
3186 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003187 .c = {
3188 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003189 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003190 CLK_INIT(csi_rdi_clk.c),
3191 },
3192};
3193
Stephen Boyd092fd182011-10-21 15:56:30 -07003194static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003195 .b = {
3196 .ctl_reg = MISC_CC3_REG,
3197 .en_mask = BIT(2),
3198 .halt_check = DELAY,
3199 .reset_reg = SW_RESET_CORE2_REG,
3200 .reset_mask = BIT(1),
3201 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003202 .s_reg = MISC_CC3_REG,
3203 .s_mask = BIT(0),
3204 .s2_reg = MISC_CC3_REG,
3205 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003206 .c = {
3207 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003208 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003209 CLK_INIT(csi_rdi1_clk.c),
3210 },
3211};
3212
Stephen Boyd092fd182011-10-21 15:56:30 -07003213static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003214 .b = {
3215 .ctl_reg = MISC_CC3_REG,
3216 .en_mask = BIT(6),
3217 .halt_check = DELAY,
3218 .reset_reg = SW_RESET_CORE2_REG,
3219 .reset_mask = BIT(0),
3220 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003221 .s_reg = MISC_CC3_REG,
3222 .s_mask = BIT(4),
3223 .s2_reg = MISC_CC3_REG,
3224 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003225 .c = {
3226 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003227 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003228 CLK_INIT(csi_rdi2_clk.c),
3229 },
3230};
3231
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003232#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003233 { \
3234 .freq_hz = f, \
3235 .src_clk = &s##_clk.c, \
3236 .md_val = MD8(8, m, 0, n), \
3237 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3238 .ctl_val = CC(6, n), \
3239 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003240 }
3241static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003242 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
3243 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
3244 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003245 F_END
3246};
3247
3248static struct rcg_clk csiphy_timer_src_clk = {
3249 .ns_reg = CSIPHYTIMER_NS_REG,
3250 .b = {
3251 .ctl_reg = CSIPHYTIMER_CC_REG,
3252 .halt_check = NOCHECK,
3253 },
3254 .md_reg = CSIPHYTIMER_MD_REG,
3255 .root_en_mask = BIT(2),
3256 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
3257 .ctl_mask = BM(7, 6),
3258 .set_rate = set_rate_mnd_8,
3259 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003260 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003261 .c = {
3262 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003263 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003264 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003265 CLK_INIT(csiphy_timer_src_clk.c),
3266 },
3267};
3268
3269static struct branch_clk csi0phy_timer_clk = {
3270 .b = {
3271 .ctl_reg = CSIPHYTIMER_CC_REG,
3272 .en_mask = BIT(0),
3273 .halt_reg = DBG_BUS_VEC_I_REG,
3274 .halt_bit = 17,
3275 },
3276 .parent = &csiphy_timer_src_clk.c,
3277 .c = {
3278 .dbg_name = "csi0phy_timer_clk",
3279 .ops = &clk_ops_branch,
3280 CLK_INIT(csi0phy_timer_clk.c),
3281 },
3282};
3283
3284static struct branch_clk csi1phy_timer_clk = {
3285 .b = {
3286 .ctl_reg = CSIPHYTIMER_CC_REG,
3287 .en_mask = BIT(9),
3288 .halt_reg = DBG_BUS_VEC_I_REG,
3289 .halt_bit = 18,
3290 },
3291 .parent = &csiphy_timer_src_clk.c,
3292 .c = {
3293 .dbg_name = "csi1phy_timer_clk",
3294 .ops = &clk_ops_branch,
3295 CLK_INIT(csi1phy_timer_clk.c),
3296 },
3297};
3298
Stephen Boyd94625ef2011-07-12 17:06:01 -07003299static struct branch_clk csi2phy_timer_clk = {
3300 .b = {
3301 .ctl_reg = CSIPHYTIMER_CC_REG,
3302 .en_mask = BIT(11),
3303 .halt_reg = DBG_BUS_VEC_I_REG,
3304 .halt_bit = 30,
3305 },
3306 .parent = &csiphy_timer_src_clk.c,
3307 .c = {
3308 .dbg_name = "csi2phy_timer_clk",
3309 .ops = &clk_ops_branch,
3310 CLK_INIT(csi2phy_timer_clk.c),
3311 },
3312};
3313
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003314#define F_DSI(d) \
3315 { \
3316 .freq_hz = d, \
3317 .ns_val = BVAL(15, 12, (d-1)), \
3318 }
3319/*
3320 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3321 * without this clock driver knowing. So, overload the clk_set_rate() to set
3322 * the divider (1 to 16) of the clock with respect to the PLL rate.
3323 */
3324static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3325 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3326 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3327 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3328 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3329 F_END
3330};
3331
3332static struct rcg_clk dsi1_byte_clk = {
3333 .b = {
3334 .ctl_reg = DSI1_BYTE_CC_REG,
3335 .en_mask = BIT(0),
3336 .reset_reg = SW_RESET_CORE_REG,
3337 .reset_mask = BIT(7),
3338 .halt_reg = DBG_BUS_VEC_B_REG,
3339 .halt_bit = 21,
3340 },
3341 .ns_reg = DSI1_BYTE_NS_REG,
3342 .root_en_mask = BIT(2),
3343 .ns_mask = BM(15, 12),
3344 .set_rate = set_rate_nop,
3345 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003346 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003347 .c = {
3348 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003349 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003350 CLK_INIT(dsi1_byte_clk.c),
3351 },
3352};
3353
3354static struct rcg_clk dsi2_byte_clk = {
3355 .b = {
3356 .ctl_reg = DSI2_BYTE_CC_REG,
3357 .en_mask = BIT(0),
3358 .reset_reg = SW_RESET_CORE_REG,
3359 .reset_mask = BIT(25),
3360 .halt_reg = DBG_BUS_VEC_B_REG,
3361 .halt_bit = 20,
3362 },
3363 .ns_reg = DSI2_BYTE_NS_REG,
3364 .root_en_mask = BIT(2),
3365 .ns_mask = BM(15, 12),
3366 .set_rate = set_rate_nop,
3367 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003368 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003369 .c = {
3370 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003371 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003372 CLK_INIT(dsi2_byte_clk.c),
3373 },
3374};
3375
3376static struct rcg_clk dsi1_esc_clk = {
3377 .b = {
3378 .ctl_reg = DSI1_ESC_CC_REG,
3379 .en_mask = BIT(0),
3380 .reset_reg = SW_RESET_CORE_REG,
3381 .halt_reg = DBG_BUS_VEC_I_REG,
3382 .halt_bit = 1,
3383 },
3384 .ns_reg = DSI1_ESC_NS_REG,
3385 .root_en_mask = BIT(2),
3386 .ns_mask = BM(15, 12),
3387 .set_rate = set_rate_nop,
3388 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003389 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003390 .c = {
3391 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003392 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003393 CLK_INIT(dsi1_esc_clk.c),
3394 },
3395};
3396
3397static struct rcg_clk dsi2_esc_clk = {
3398 .b = {
3399 .ctl_reg = DSI2_ESC_CC_REG,
3400 .en_mask = BIT(0),
3401 .halt_reg = DBG_BUS_VEC_I_REG,
3402 .halt_bit = 3,
3403 },
3404 .ns_reg = DSI2_ESC_NS_REG,
3405 .root_en_mask = BIT(2),
3406 .ns_mask = BM(15, 12),
3407 .set_rate = set_rate_nop,
3408 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003409 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003410 .c = {
3411 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003412 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003413 CLK_INIT(dsi2_esc_clk.c),
3414 },
3415};
3416
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003417#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003418 { \
3419 .freq_hz = f, \
3420 .src_clk = &s##_clk.c, \
3421 .md_val = MD4(4, m, 0, n), \
3422 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3423 .ctl_val = CC_BANKED(9, 6, n), \
3424 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003425 }
3426static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003427 F_GFX2D( 0, gnd, 0, 0),
3428 F_GFX2D( 27000000, pxo, 0, 0),
3429 F_GFX2D( 48000000, pll8, 1, 8),
3430 F_GFX2D( 54857000, pll8, 1, 7),
3431 F_GFX2D( 64000000, pll8, 1, 6),
3432 F_GFX2D( 76800000, pll8, 1, 5),
3433 F_GFX2D( 96000000, pll8, 1, 4),
3434 F_GFX2D(128000000, pll8, 1, 3),
3435 F_GFX2D(145455000, pll2, 2, 11),
3436 F_GFX2D(160000000, pll2, 1, 5),
3437 F_GFX2D(177778000, pll2, 2, 9),
3438 F_GFX2D(200000000, pll2, 1, 4),
3439 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003440 F_END
3441};
3442
3443static struct bank_masks bmnd_info_gfx2d0 = {
3444 .bank_sel_mask = BIT(11),
3445 .bank0_mask = {
3446 .md_reg = GFX2D0_MD0_REG,
3447 .ns_mask = BM(23, 20) | BM(5, 3),
3448 .rst_mask = BIT(25),
3449 .mnd_en_mask = BIT(8),
3450 .mode_mask = BM(10, 9),
3451 },
3452 .bank1_mask = {
3453 .md_reg = GFX2D0_MD1_REG,
3454 .ns_mask = BM(19, 16) | BM(2, 0),
3455 .rst_mask = BIT(24),
3456 .mnd_en_mask = BIT(5),
3457 .mode_mask = BM(7, 6),
3458 },
3459};
3460
3461static struct rcg_clk gfx2d0_clk = {
3462 .b = {
3463 .ctl_reg = GFX2D0_CC_REG,
3464 .en_mask = BIT(0),
3465 .reset_reg = SW_RESET_CORE_REG,
3466 .reset_mask = BIT(14),
3467 .halt_reg = DBG_BUS_VEC_A_REG,
3468 .halt_bit = 9,
3469 },
3470 .ns_reg = GFX2D0_NS_REG,
3471 .root_en_mask = BIT(2),
3472 .set_rate = set_rate_mnd_banked,
3473 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003474 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003475 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003476 .c = {
3477 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003478 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003479 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3480 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003481 CLK_INIT(gfx2d0_clk.c),
3482 },
3483};
3484
3485static struct bank_masks bmnd_info_gfx2d1 = {
3486 .bank_sel_mask = BIT(11),
3487 .bank0_mask = {
3488 .md_reg = GFX2D1_MD0_REG,
3489 .ns_mask = BM(23, 20) | BM(5, 3),
3490 .rst_mask = BIT(25),
3491 .mnd_en_mask = BIT(8),
3492 .mode_mask = BM(10, 9),
3493 },
3494 .bank1_mask = {
3495 .md_reg = GFX2D1_MD1_REG,
3496 .ns_mask = BM(19, 16) | BM(2, 0),
3497 .rst_mask = BIT(24),
3498 .mnd_en_mask = BIT(5),
3499 .mode_mask = BM(7, 6),
3500 },
3501};
3502
3503static struct rcg_clk gfx2d1_clk = {
3504 .b = {
3505 .ctl_reg = GFX2D1_CC_REG,
3506 .en_mask = BIT(0),
3507 .reset_reg = SW_RESET_CORE_REG,
3508 .reset_mask = BIT(13),
3509 .halt_reg = DBG_BUS_VEC_A_REG,
3510 .halt_bit = 14,
3511 },
3512 .ns_reg = GFX2D1_NS_REG,
3513 .root_en_mask = BIT(2),
3514 .set_rate = set_rate_mnd_banked,
3515 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003516 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003517 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003518 .c = {
3519 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003520 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003521 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3522 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003523 CLK_INIT(gfx2d1_clk.c),
3524 },
3525};
3526
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003527#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003528 { \
3529 .freq_hz = f, \
3530 .src_clk = &s##_clk.c, \
3531 .md_val = MD4(4, m, 0, n), \
3532 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3533 .ctl_val = CC_BANKED(9, 6, n), \
3534 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003535 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003536
3537static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003538 F_GFX3D( 0, gnd, 0, 0),
3539 F_GFX3D( 27000000, pxo, 0, 0),
3540 F_GFX3D( 48000000, pll8, 1, 8),
3541 F_GFX3D( 54857000, pll8, 1, 7),
3542 F_GFX3D( 64000000, pll8, 1, 6),
3543 F_GFX3D( 76800000, pll8, 1, 5),
3544 F_GFX3D( 96000000, pll8, 1, 4),
3545 F_GFX3D(128000000, pll8, 1, 3),
3546 F_GFX3D(145455000, pll2, 2, 11),
3547 F_GFX3D(160000000, pll2, 1, 5),
3548 F_GFX3D(177778000, pll2, 2, 9),
3549 F_GFX3D(200000000, pll2, 1, 4),
3550 F_GFX3D(228571000, pll2, 2, 7),
3551 F_GFX3D(266667000, pll2, 1, 3),
3552 F_GFX3D(320000000, pll2, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003553 F_END
3554};
3555
Tianyi Gou41515e22011-09-01 19:37:43 -07003556static struct clk_freq_tbl clk_tbl_gfx3d_8960_v2[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003557 F_GFX3D( 0, gnd, 0, 0),
3558 F_GFX3D( 27000000, pxo, 0, 0),
3559 F_GFX3D( 48000000, pll8, 1, 8),
3560 F_GFX3D( 54857000, pll8, 1, 7),
3561 F_GFX3D( 64000000, pll8, 1, 6),
3562 F_GFX3D( 76800000, pll8, 1, 5),
3563 F_GFX3D( 96000000, pll8, 1, 4),
3564 F_GFX3D(128000000, pll8, 1, 3),
3565 F_GFX3D(145455000, pll2, 2, 11),
3566 F_GFX3D(160000000, pll2, 1, 5),
3567 F_GFX3D(177778000, pll2, 2, 9),
3568 F_GFX3D(200000000, pll2, 1, 4),
3569 F_GFX3D(228571000, pll2, 2, 7),
3570 F_GFX3D(266667000, pll2, 1, 3),
3571 F_GFX3D(300000000, pll3, 1, 4),
3572 F_GFX3D(320000000, pll2, 2, 5),
3573 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003574 F_END
3575};
3576
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003577static unsigned long fmax_gfx3d_8960_v2[MAX_VDD_LEVELS] __initdata = {
3578 [VDD_DIG_LOW] = 128000000,
3579 [VDD_DIG_NOMINAL] = 300000000,
3580 [VDD_DIG_HIGH] = 400000000
3581};
3582
Tianyi Gou41515e22011-09-01 19:37:43 -07003583static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003584 F_GFX3D( 0, gnd, 0, 0),
3585 F_GFX3D( 27000000, pxo, 0, 0),
3586 F_GFX3D( 48000000, pll8, 1, 8),
3587 F_GFX3D( 54857000, pll8, 1, 7),
3588 F_GFX3D( 64000000, pll8, 1, 6),
3589 F_GFX3D( 76800000, pll8, 1, 5),
3590 F_GFX3D( 96000000, pll8, 1, 4),
3591 F_GFX3D(128000000, pll8, 1, 3),
3592 F_GFX3D(145455000, pll2, 2, 11),
3593 F_GFX3D(160000000, pll2, 1, 5),
3594 F_GFX3D(177778000, pll2, 2, 9),
3595 F_GFX3D(200000000, pll2, 1, 4),
3596 F_GFX3D(228571000, pll2, 2, 7),
3597 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07003598 F_GFX3D(325000000, pll15, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003599 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003600 F_END
3601};
3602
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003603static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3604 [VDD_DIG_LOW] = 128000000,
3605 [VDD_DIG_NOMINAL] = 325000000,
3606 [VDD_DIG_HIGH] = 400000000
3607};
3608
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003609static struct bank_masks bmnd_info_gfx3d = {
3610 .bank_sel_mask = BIT(11),
3611 .bank0_mask = {
3612 .md_reg = GFX3D_MD0_REG,
3613 .ns_mask = BM(21, 18) | BM(5, 3),
3614 .rst_mask = BIT(23),
3615 .mnd_en_mask = BIT(8),
3616 .mode_mask = BM(10, 9),
3617 },
3618 .bank1_mask = {
3619 .md_reg = GFX3D_MD1_REG,
3620 .ns_mask = BM(17, 14) | BM(2, 0),
3621 .rst_mask = BIT(22),
3622 .mnd_en_mask = BIT(5),
3623 .mode_mask = BM(7, 6),
3624 },
3625};
3626
3627static struct rcg_clk gfx3d_clk = {
3628 .b = {
3629 .ctl_reg = GFX3D_CC_REG,
3630 .en_mask = BIT(0),
3631 .reset_reg = SW_RESET_CORE_REG,
3632 .reset_mask = BIT(12),
3633 .halt_reg = DBG_BUS_VEC_A_REG,
3634 .halt_bit = 4,
3635 },
3636 .ns_reg = GFX3D_NS_REG,
3637 .root_en_mask = BIT(2),
3638 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003639 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003640 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003641 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003642 .c = {
3643 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003644 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003645 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 266667000,
3646 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003647 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003648 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003649 },
3650};
3651
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003652#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003653 { \
3654 .freq_hz = f, \
3655 .src_clk = &s##_clk.c, \
3656 .md_val = MD4(4, m, 0, n), \
3657 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3658 .ctl_val = CC_BANKED(9, 6, n), \
3659 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003660 }
3661
3662static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003663 F_VCAP( 0, gnd, 0, 0),
3664 F_VCAP( 27000000, pxo, 0, 0),
3665 F_VCAP( 54860000, pll8, 1, 7),
3666 F_VCAP( 64000000, pll8, 1, 6),
3667 F_VCAP( 76800000, pll8, 1, 5),
3668 F_VCAP(128000000, pll8, 1, 3),
3669 F_VCAP(160000000, pll2, 1, 5),
3670 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003671 F_END
3672};
3673
3674static struct bank_masks bmnd_info_vcap = {
3675 .bank_sel_mask = BIT(11),
3676 .bank0_mask = {
3677 .md_reg = VCAP_MD0_REG,
3678 .ns_mask = BM(21, 18) | BM(5, 3),
3679 .rst_mask = BIT(23),
3680 .mnd_en_mask = BIT(8),
3681 .mode_mask = BM(10, 9),
3682 },
3683 .bank1_mask = {
3684 .md_reg = VCAP_MD1_REG,
3685 .ns_mask = BM(17, 14) | BM(2, 0),
3686 .rst_mask = BIT(22),
3687 .mnd_en_mask = BIT(5),
3688 .mode_mask = BM(7, 6),
3689 },
3690};
3691
3692static struct rcg_clk vcap_clk = {
3693 .b = {
3694 .ctl_reg = VCAP_CC_REG,
3695 .en_mask = BIT(0),
3696 .halt_reg = DBG_BUS_VEC_J_REG,
3697 .halt_bit = 15,
3698 },
3699 .ns_reg = VCAP_NS_REG,
3700 .root_en_mask = BIT(2),
3701 .set_rate = set_rate_mnd_banked,
3702 .freq_tbl = clk_tbl_vcap,
3703 .bank_info = &bmnd_info_vcap,
3704 .current_freq = &rcg_dummy_freq,
3705 .c = {
3706 .dbg_name = "vcap_clk",
3707 .ops = &clk_ops_rcg_8960,
3708 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003709 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003710 CLK_INIT(vcap_clk.c),
3711 },
3712};
3713
3714static struct branch_clk vcap_npl_clk = {
3715 .b = {
3716 .ctl_reg = VCAP_CC_REG,
3717 .en_mask = BIT(13),
3718 .halt_reg = DBG_BUS_VEC_J_REG,
3719 .halt_bit = 25,
3720 },
3721 .parent = &vcap_clk.c,
3722 .c = {
3723 .dbg_name = "vcap_npl_clk",
3724 .ops = &clk_ops_branch,
3725 CLK_INIT(vcap_npl_clk.c),
3726 },
3727};
3728
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003729#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003730 { \
3731 .freq_hz = f, \
3732 .src_clk = &s##_clk.c, \
3733 .md_val = MD8(8, m, 0, n), \
3734 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3735 .ctl_val = CC(6, n), \
3736 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003737 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003738
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003739static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3740 F_IJPEG( 0, gnd, 1, 0, 0),
3741 F_IJPEG( 27000000, pxo, 1, 0, 0),
3742 F_IJPEG( 36570000, pll8, 1, 2, 21),
3743 F_IJPEG( 54860000, pll8, 7, 0, 0),
3744 F_IJPEG( 96000000, pll8, 4, 0, 0),
3745 F_IJPEG(109710000, pll8, 1, 2, 7),
3746 F_IJPEG(128000000, pll8, 3, 0, 0),
3747 F_IJPEG(153600000, pll8, 1, 2, 5),
3748 F_IJPEG(200000000, pll2, 4, 0, 0),
3749 F_IJPEG(228571000, pll2, 1, 2, 7),
3750 F_IJPEG(266667000, pll2, 1, 1, 3),
3751 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003752 F_END
3753};
3754
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003755static unsigned long fmax_ijpeg_8960_v2[MAX_VDD_LEVELS] __initdata = {
3756 [VDD_DIG_LOW] = 110000000,
3757 [VDD_DIG_NOMINAL] = 266667000,
3758 [VDD_DIG_HIGH] = 320000000
3759};
3760
3761static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3762 [VDD_DIG_LOW] = 128000000,
3763 [VDD_DIG_NOMINAL] = 266667000,
3764 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003765};
3766
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003767static struct rcg_clk ijpeg_clk = {
3768 .b = {
3769 .ctl_reg = IJPEG_CC_REG,
3770 .en_mask = BIT(0),
3771 .reset_reg = SW_RESET_CORE_REG,
3772 .reset_mask = BIT(9),
3773 .halt_reg = DBG_BUS_VEC_A_REG,
3774 .halt_bit = 24,
3775 },
3776 .ns_reg = IJPEG_NS_REG,
3777 .md_reg = IJPEG_MD_REG,
3778 .root_en_mask = BIT(2),
3779 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
3780 .ctl_mask = BM(7, 6),
3781 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003782 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003783 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003784 .c = {
3785 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003786 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003787 VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003788 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003789 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003790 },
3791};
3792
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003793#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003794 { \
3795 .freq_hz = f, \
3796 .src_clk = &s##_clk.c, \
3797 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003798 }
3799static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003800 F_JPEGD( 0, gnd, 1),
3801 F_JPEGD( 64000000, pll8, 6),
3802 F_JPEGD( 76800000, pll8, 5),
3803 F_JPEGD( 96000000, pll8, 4),
3804 F_JPEGD(160000000, pll2, 5),
3805 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003806 F_END
3807};
3808
3809static struct rcg_clk jpegd_clk = {
3810 .b = {
3811 .ctl_reg = JPEGD_CC_REG,
3812 .en_mask = BIT(0),
3813 .reset_reg = SW_RESET_CORE_REG,
3814 .reset_mask = BIT(19),
3815 .halt_reg = DBG_BUS_VEC_A_REG,
3816 .halt_bit = 19,
3817 },
3818 .ns_reg = JPEGD_NS_REG,
3819 .root_en_mask = BIT(2),
3820 .ns_mask = (BM(15, 12) | BM(2, 0)),
3821 .set_rate = set_rate_nop,
3822 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003823 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003824 .c = {
3825 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003826 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003827 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003828 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003829 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003830 },
3831};
3832
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003833#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003834 { \
3835 .freq_hz = f, \
3836 .src_clk = &s##_clk.c, \
3837 .md_val = MD8(8, m, 0, n), \
3838 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3839 .ctl_val = CC_BANKED(9, 6, n), \
3840 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003841 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003842static struct clk_freq_tbl clk_tbl_mdp[] = {
3843 F_MDP( 0, gnd, 0, 0),
3844 F_MDP( 9600000, pll8, 1, 40),
3845 F_MDP( 13710000, pll8, 1, 28),
3846 F_MDP( 27000000, pxo, 0, 0),
3847 F_MDP( 29540000, pll8, 1, 13),
3848 F_MDP( 34910000, pll8, 1, 11),
3849 F_MDP( 38400000, pll8, 1, 10),
3850 F_MDP( 59080000, pll8, 2, 13),
3851 F_MDP( 76800000, pll8, 1, 5),
3852 F_MDP( 85330000, pll8, 2, 9),
3853 F_MDP( 96000000, pll8, 1, 4),
3854 F_MDP(128000000, pll8, 1, 3),
3855 F_MDP(160000000, pll2, 1, 5),
3856 F_MDP(177780000, pll2, 2, 9),
3857 F_MDP(200000000, pll2, 1, 4),
3858 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003859 F_END
3860};
3861
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003862static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3863 [VDD_DIG_LOW] = 128000000,
3864 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003865};
3866
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003867static struct bank_masks bmnd_info_mdp = {
3868 .bank_sel_mask = BIT(11),
3869 .bank0_mask = {
3870 .md_reg = MDP_MD0_REG,
3871 .ns_mask = BM(29, 22) | BM(5, 3),
3872 .rst_mask = BIT(31),
3873 .mnd_en_mask = BIT(8),
3874 .mode_mask = BM(10, 9),
3875 },
3876 .bank1_mask = {
3877 .md_reg = MDP_MD1_REG,
3878 .ns_mask = BM(21, 14) | BM(2, 0),
3879 .rst_mask = BIT(30),
3880 .mnd_en_mask = BIT(5),
3881 .mode_mask = BM(7, 6),
3882 },
3883};
3884
3885static struct rcg_clk mdp_clk = {
3886 .b = {
3887 .ctl_reg = MDP_CC_REG,
3888 .en_mask = BIT(0),
3889 .reset_reg = SW_RESET_CORE_REG,
3890 .reset_mask = BIT(21),
3891 .halt_reg = DBG_BUS_VEC_C_REG,
3892 .halt_bit = 10,
3893 },
3894 .ns_reg = MDP_NS_REG,
3895 .root_en_mask = BIT(2),
3896 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003897 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003898 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003899 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003900 .c = {
3901 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003902 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003903 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003904 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003905 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003906 },
3907};
3908
3909static struct branch_clk lut_mdp_clk = {
3910 .b = {
3911 .ctl_reg = MDP_LUT_CC_REG,
3912 .en_mask = BIT(0),
3913 .halt_reg = DBG_BUS_VEC_I_REG,
3914 .halt_bit = 13,
3915 },
3916 .parent = &mdp_clk.c,
3917 .c = {
3918 .dbg_name = "lut_mdp_clk",
3919 .ops = &clk_ops_branch,
3920 CLK_INIT(lut_mdp_clk.c),
3921 },
3922};
3923
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003924#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003925 { \
3926 .freq_hz = f, \
3927 .src_clk = &s##_clk.c, \
3928 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003929 }
3930static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003931 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003932 F_END
3933};
3934
3935static struct rcg_clk mdp_vsync_clk = {
3936 .b = {
3937 .ctl_reg = MISC_CC_REG,
3938 .en_mask = BIT(6),
3939 .reset_reg = SW_RESET_CORE_REG,
3940 .reset_mask = BIT(3),
3941 .halt_reg = DBG_BUS_VEC_B_REG,
3942 .halt_bit = 22,
3943 },
3944 .ns_reg = MISC_CC2_REG,
3945 .ns_mask = BIT(13),
3946 .set_rate = set_rate_nop,
3947 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003948 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003949 .c = {
3950 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003951 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003952 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003953 CLK_INIT(mdp_vsync_clk.c),
3954 },
3955};
3956
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003957#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003958 { \
3959 .freq_hz = f, \
3960 .src_clk = &s##_clk.c, \
3961 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3962 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003963 }
3964static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003965 F_ROT( 0, gnd, 1),
3966 F_ROT( 27000000, pxo, 1),
3967 F_ROT( 29540000, pll8, 13),
3968 F_ROT( 32000000, pll8, 12),
3969 F_ROT( 38400000, pll8, 10),
3970 F_ROT( 48000000, pll8, 8),
3971 F_ROT( 54860000, pll8, 7),
3972 F_ROT( 64000000, pll8, 6),
3973 F_ROT( 76800000, pll8, 5),
3974 F_ROT( 96000000, pll8, 4),
3975 F_ROT(100000000, pll2, 8),
3976 F_ROT(114290000, pll2, 7),
3977 F_ROT(133330000, pll2, 6),
3978 F_ROT(160000000, pll2, 5),
3979 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003980 F_END
3981};
3982
3983static struct bank_masks bdiv_info_rot = {
3984 .bank_sel_mask = BIT(30),
3985 .bank0_mask = {
3986 .ns_mask = BM(25, 22) | BM(18, 16),
3987 },
3988 .bank1_mask = {
3989 .ns_mask = BM(29, 26) | BM(21, 19),
3990 },
3991};
3992
3993static struct rcg_clk rot_clk = {
3994 .b = {
3995 .ctl_reg = ROT_CC_REG,
3996 .en_mask = BIT(0),
3997 .reset_reg = SW_RESET_CORE_REG,
3998 .reset_mask = BIT(2),
3999 .halt_reg = DBG_BUS_VEC_C_REG,
4000 .halt_bit = 15,
4001 },
4002 .ns_reg = ROT_NS_REG,
4003 .root_en_mask = BIT(2),
4004 .set_rate = set_rate_div_banked,
4005 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004006 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004007 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004008 .c = {
4009 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004010 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004011 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004012 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004013 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004014 },
4015};
4016
4017static int hdmi_pll_clk_enable(struct clk *clk)
4018{
4019 int ret;
4020 unsigned long flags;
4021 spin_lock_irqsave(&local_clock_reg_lock, flags);
4022 ret = hdmi_pll_enable();
4023 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4024 return ret;
4025}
4026
4027static void hdmi_pll_clk_disable(struct clk *clk)
4028{
4029 unsigned long flags;
4030 spin_lock_irqsave(&local_clock_reg_lock, flags);
4031 hdmi_pll_disable();
4032 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4033}
4034
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004035static unsigned long hdmi_pll_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004036{
4037 return hdmi_pll_get_rate();
4038}
4039
Stephen Boyd5b35dee2011-09-21 12:17:38 -07004040static struct clk *hdmi_pll_clk_get_parent(struct clk *clk)
4041{
4042 return &pxo_clk.c;
4043}
4044
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004045static struct clk_ops clk_ops_hdmi_pll = {
4046 .enable = hdmi_pll_clk_enable,
4047 .disable = hdmi_pll_clk_disable,
4048 .get_rate = hdmi_pll_clk_get_rate,
4049 .is_local = local_clk_is_local,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07004050 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004051};
4052
4053static struct clk hdmi_pll_clk = {
4054 .dbg_name = "hdmi_pll_clk",
4055 .ops = &clk_ops_hdmi_pll,
4056 CLK_INIT(hdmi_pll_clk),
4057};
4058
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004059#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004060 { \
4061 .freq_hz = f, \
4062 .src_clk = &s##_clk.c, \
4063 .md_val = MD8(8, m, 0, n), \
4064 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
4065 .ctl_val = CC(6, n), \
4066 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004067 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004068#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004069 { \
4070 .freq_hz = f, \
4071 .src_clk = &s##_clk, \
4072 .md_val = MD8(8, m, 0, n), \
4073 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
4074 .ctl_val = CC(6, n), \
4075 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004076 .extra_freq_data = (void *)p_r, \
4077 }
4078/* Switching TV freqs requires PLL reconfiguration. */
4079static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004080 F_TV_GND( 0, gnd, 0, 1, 0, 0),
4081 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
4082 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
4083 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
4084 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
4085 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004086 F_END
4087};
4088
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004089static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
4090 [VDD_DIG_LOW] = 74250000,
4091 [VDD_DIG_NOMINAL] = 149000000
4092};
4093
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004094/*
4095 * Unlike other clocks, the TV rate is adjusted through PLL
4096 * re-programming. It is also routed through an MND divider.
4097 */
4098void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
4099{
4100 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
4101 if (pll_rate)
4102 hdmi_pll_set_rate(pll_rate);
4103 set_rate_mnd(clk, nf);
4104}
4105
4106static struct rcg_clk tv_src_clk = {
4107 .ns_reg = TV_NS_REG,
4108 .b = {
4109 .ctl_reg = TV_CC_REG,
4110 .halt_check = NOCHECK,
4111 },
4112 .md_reg = TV_MD_REG,
4113 .root_en_mask = BIT(2),
4114 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
4115 .ctl_mask = BM(7, 6),
4116 .set_rate = set_rate_tv,
4117 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004118 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004119 .c = {
4120 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004121 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004122 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004123 CLK_INIT(tv_src_clk.c),
4124 },
4125};
4126
4127static struct branch_clk tv_enc_clk = {
4128 .b = {
4129 .ctl_reg = TV_CC_REG,
4130 .en_mask = BIT(8),
4131 .reset_reg = SW_RESET_CORE_REG,
4132 .reset_mask = BIT(0),
4133 .halt_reg = DBG_BUS_VEC_D_REG,
4134 .halt_bit = 9,
4135 },
4136 .parent = &tv_src_clk.c,
4137 .c = {
4138 .dbg_name = "tv_enc_clk",
4139 .ops = &clk_ops_branch,
4140 CLK_INIT(tv_enc_clk.c),
4141 },
4142};
4143
4144static struct branch_clk tv_dac_clk = {
4145 .b = {
4146 .ctl_reg = TV_CC_REG,
4147 .en_mask = BIT(10),
4148 .halt_reg = DBG_BUS_VEC_D_REG,
4149 .halt_bit = 10,
4150 },
4151 .parent = &tv_src_clk.c,
4152 .c = {
4153 .dbg_name = "tv_dac_clk",
4154 .ops = &clk_ops_branch,
4155 CLK_INIT(tv_dac_clk.c),
4156 },
4157};
4158
4159static struct branch_clk mdp_tv_clk = {
4160 .b = {
4161 .ctl_reg = TV_CC_REG,
4162 .en_mask = BIT(0),
4163 .reset_reg = SW_RESET_CORE_REG,
4164 .reset_mask = BIT(4),
4165 .halt_reg = DBG_BUS_VEC_D_REG,
4166 .halt_bit = 12,
4167 },
4168 .parent = &tv_src_clk.c,
4169 .c = {
4170 .dbg_name = "mdp_tv_clk",
4171 .ops = &clk_ops_branch,
4172 CLK_INIT(mdp_tv_clk.c),
4173 },
4174};
4175
4176static struct branch_clk hdmi_tv_clk = {
4177 .b = {
4178 .ctl_reg = TV_CC_REG,
4179 .en_mask = BIT(12),
4180 .reset_reg = SW_RESET_CORE_REG,
4181 .reset_mask = BIT(1),
4182 .halt_reg = DBG_BUS_VEC_D_REG,
4183 .halt_bit = 11,
4184 },
4185 .parent = &tv_src_clk.c,
4186 .c = {
4187 .dbg_name = "hdmi_tv_clk",
4188 .ops = &clk_ops_branch,
4189 CLK_INIT(hdmi_tv_clk.c),
4190 },
4191};
4192
4193static struct branch_clk hdmi_app_clk = {
4194 .b = {
4195 .ctl_reg = MISC_CC2_REG,
4196 .en_mask = BIT(11),
4197 .reset_reg = SW_RESET_CORE_REG,
4198 .reset_mask = BIT(11),
4199 .halt_reg = DBG_BUS_VEC_B_REG,
4200 .halt_bit = 25,
4201 },
4202 .c = {
4203 .dbg_name = "hdmi_app_clk",
4204 .ops = &clk_ops_branch,
4205 CLK_INIT(hdmi_app_clk.c),
4206 },
4207};
4208
4209static struct bank_masks bmnd_info_vcodec = {
4210 .bank_sel_mask = BIT(13),
4211 .bank0_mask = {
4212 .md_reg = VCODEC_MD0_REG,
4213 .ns_mask = BM(18, 11) | BM(2, 0),
4214 .rst_mask = BIT(31),
4215 .mnd_en_mask = BIT(5),
4216 .mode_mask = BM(7, 6),
4217 },
4218 .bank1_mask = {
4219 .md_reg = VCODEC_MD1_REG,
4220 .ns_mask = BM(26, 19) | BM(29, 27),
4221 .rst_mask = BIT(30),
4222 .mnd_en_mask = BIT(10),
4223 .mode_mask = BM(12, 11),
4224 },
4225};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004226#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004227 { \
4228 .freq_hz = f, \
4229 .src_clk = &s##_clk.c, \
4230 .md_val = MD8(8, m, 0, n), \
4231 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
4232 .ctl_val = CC_BANKED(6, 11, n), \
4233 .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004234 }
4235static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004236 F_VCODEC( 0, gnd, 0, 0),
4237 F_VCODEC( 27000000, pxo, 0, 0),
4238 F_VCODEC( 32000000, pll8, 1, 12),
4239 F_VCODEC( 48000000, pll8, 1, 8),
4240 F_VCODEC( 54860000, pll8, 1, 7),
4241 F_VCODEC( 96000000, pll8, 1, 4),
4242 F_VCODEC(133330000, pll2, 1, 6),
4243 F_VCODEC(200000000, pll2, 1, 4),
4244 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004245 F_END
4246};
4247
4248static struct rcg_clk vcodec_clk = {
4249 .b = {
4250 .ctl_reg = VCODEC_CC_REG,
4251 .en_mask = BIT(0),
4252 .reset_reg = SW_RESET_CORE_REG,
4253 .reset_mask = BIT(6),
4254 .halt_reg = DBG_BUS_VEC_C_REG,
4255 .halt_bit = 29,
4256 },
4257 .ns_reg = VCODEC_NS_REG,
4258 .root_en_mask = BIT(2),
4259 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004260 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004261 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004262 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004263 .c = {
4264 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004265 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004266 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4267 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004268 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004269 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004270 },
4271};
4272
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004273#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004274 { \
4275 .freq_hz = f, \
4276 .src_clk = &s##_clk.c, \
4277 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004278 }
4279static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004280 F_VPE( 0, gnd, 1),
4281 F_VPE( 27000000, pxo, 1),
4282 F_VPE( 34909000, pll8, 11),
4283 F_VPE( 38400000, pll8, 10),
4284 F_VPE( 64000000, pll8, 6),
4285 F_VPE( 76800000, pll8, 5),
4286 F_VPE( 96000000, pll8, 4),
4287 F_VPE(100000000, pll2, 8),
4288 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004289 F_END
4290};
4291
4292static struct rcg_clk vpe_clk = {
4293 .b = {
4294 .ctl_reg = VPE_CC_REG,
4295 .en_mask = BIT(0),
4296 .reset_reg = SW_RESET_CORE_REG,
4297 .reset_mask = BIT(17),
4298 .halt_reg = DBG_BUS_VEC_A_REG,
4299 .halt_bit = 28,
4300 },
4301 .ns_reg = VPE_NS_REG,
4302 .root_en_mask = BIT(2),
4303 .ns_mask = (BM(15, 12) | BM(2, 0)),
4304 .set_rate = set_rate_nop,
4305 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004306 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004307 .c = {
4308 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004309 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004310 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004311 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004312 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004313 },
4314};
4315
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004316#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004317 { \
4318 .freq_hz = f, \
4319 .src_clk = &s##_clk.c, \
4320 .md_val = MD8(8, m, 0, n), \
4321 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4322 .ctl_val = CC(6, n), \
4323 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004324 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004325
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004326static struct clk_freq_tbl clk_tbl_vfe[] = {
4327 F_VFE( 0, gnd, 1, 0, 0),
4328 F_VFE( 13960000, pll8, 1, 2, 55),
4329 F_VFE( 27000000, pxo, 1, 0, 0),
4330 F_VFE( 36570000, pll8, 1, 2, 21),
4331 F_VFE( 38400000, pll8, 2, 1, 5),
4332 F_VFE( 45180000, pll8, 1, 2, 17),
4333 F_VFE( 48000000, pll8, 2, 1, 4),
4334 F_VFE( 54860000, pll8, 1, 1, 7),
4335 F_VFE( 64000000, pll8, 2, 1, 3),
4336 F_VFE( 76800000, pll8, 1, 1, 5),
4337 F_VFE( 96000000, pll8, 2, 1, 2),
4338 F_VFE(109710000, pll8, 1, 2, 7),
4339 F_VFE(128000000, pll8, 1, 1, 3),
4340 F_VFE(153600000, pll8, 1, 2, 5),
4341 F_VFE(200000000, pll2, 2, 1, 2),
4342 F_VFE(228570000, pll2, 1, 2, 7),
4343 F_VFE(266667000, pll2, 1, 1, 3),
4344 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004345 F_END
4346};
4347
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004348static unsigned long fmax_vfe_8960_v2[MAX_VDD_LEVELS] __initdata = {
4349 [VDD_DIG_LOW] = 110000000,
4350 [VDD_DIG_NOMINAL] = 266667000,
4351 [VDD_DIG_HIGH] = 320000000
4352};
4353
4354static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4355 [VDD_DIG_LOW] = 128000000,
4356 [VDD_DIG_NOMINAL] = 266667000,
4357 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004358};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004359
4360static struct rcg_clk vfe_clk = {
4361 .b = {
4362 .ctl_reg = VFE_CC_REG,
4363 .reset_reg = SW_RESET_CORE_REG,
4364 .reset_mask = BIT(15),
4365 .halt_reg = DBG_BUS_VEC_B_REG,
4366 .halt_bit = 6,
4367 .en_mask = BIT(0),
4368 },
4369 .ns_reg = VFE_NS_REG,
4370 .md_reg = VFE_MD_REG,
4371 .root_en_mask = BIT(2),
4372 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
4373 .ctl_mask = BM(7, 6),
4374 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004375 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004376 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004377 .c = {
4378 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004379 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004380 VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004381 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004382 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004383 },
4384};
4385
Matt Wagantallc23eee92011-08-16 23:06:52 -07004386static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004387 .b = {
4388 .ctl_reg = VFE_CC_REG,
4389 .en_mask = BIT(12),
4390 .reset_reg = SW_RESET_CORE_REG,
4391 .reset_mask = BIT(24),
4392 .halt_reg = DBG_BUS_VEC_B_REG,
4393 .halt_bit = 8,
4394 },
4395 .parent = &vfe_clk.c,
4396 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004397 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004398 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004399 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004400 },
4401};
4402
4403/*
4404 * Low Power Audio Clocks
4405 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004406#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004407 { \
4408 .freq_hz = f, \
4409 .src_clk = &s##_clk.c, \
4410 .md_val = MD8(8, m, 0, n), \
4411 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4412 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004413 }
4414static struct clk_freq_tbl clk_tbl_aif_osr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004415 F_AIF_OSR( 0, gnd, 1, 0, 0),
4416 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4417 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4418 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4419 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4420 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4421 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4422 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4423 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4424 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4425 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4426 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004427 F_END
4428};
4429
4430#define CLK_AIF_OSR(i, ns, md, h_r) \
4431 struct rcg_clk i##_clk = { \
4432 .b = { \
4433 .ctl_reg = ns, \
4434 .en_mask = BIT(17), \
4435 .reset_reg = ns, \
4436 .reset_mask = BIT(19), \
4437 .halt_reg = h_r, \
4438 .halt_check = ENABLE, \
4439 .halt_bit = 1, \
4440 }, \
4441 .ns_reg = ns, \
4442 .md_reg = md, \
4443 .root_en_mask = BIT(9), \
4444 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4445 .set_rate = set_rate_mnd, \
4446 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004447 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004448 .c = { \
4449 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004450 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004451 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004452 CLK_INIT(i##_clk.c), \
4453 }, \
4454 }
4455#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4456 struct rcg_clk i##_clk = { \
4457 .b = { \
4458 .ctl_reg = ns, \
4459 .en_mask = BIT(21), \
4460 .reset_reg = ns, \
4461 .reset_mask = BIT(23), \
4462 .halt_reg = h_r, \
4463 .halt_check = ENABLE, \
4464 .halt_bit = 1, \
4465 }, \
4466 .ns_reg = ns, \
4467 .md_reg = md, \
4468 .root_en_mask = BIT(9), \
4469 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4470 .set_rate = set_rate_mnd, \
4471 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004472 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004473 .c = { \
4474 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004475 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004476 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004477 CLK_INIT(i##_clk.c), \
4478 }, \
4479 }
4480
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004481#define CLK_AIF_BIT(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004482 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004483 .b = { \
4484 .ctl_reg = ns, \
4485 .en_mask = BIT(15), \
4486 .halt_reg = h_r, \
4487 .halt_check = DELAY, \
4488 }, \
4489 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004490 .ext_mask = BIT(14), \
4491 .div_offset = 10, \
4492 .max_div = 16, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004493 .c = { \
4494 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004495 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004496 CLK_INIT(i##_clk.c), \
4497 }, \
4498 }
4499
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004500#define CLK_AIF_BIT_DIV(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004501 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004502 .b = { \
4503 .ctl_reg = ns, \
4504 .en_mask = BIT(19), \
4505 .halt_reg = h_r, \
4506 .halt_check = ENABLE, \
4507 }, \
4508 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004509 .ext_mask = BIT(18), \
4510 .div_offset = 10, \
4511 .max_div = 256, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004512 .c = { \
4513 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004514 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004515 CLK_INIT(i##_clk.c), \
4516 }, \
4517 }
4518
4519static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4520 LCC_MI2S_STATUS_REG);
4521static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4522
4523static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4524 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4525static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4526 LCC_CODEC_I2S_MIC_STATUS_REG);
4527
4528static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4529 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4530static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4531 LCC_SPARE_I2S_MIC_STATUS_REG);
4532
4533static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4534 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4535static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4536 LCC_CODEC_I2S_SPKR_STATUS_REG);
4537
4538static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4539 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4540static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4541 LCC_SPARE_I2S_SPKR_STATUS_REG);
4542
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004543#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004544 { \
4545 .freq_hz = f, \
4546 .src_clk = &s##_clk.c, \
4547 .md_val = MD16(m, n), \
4548 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4549 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004550 }
4551static struct clk_freq_tbl clk_tbl_pcm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004552 F_PCM( 0, gnd, 1, 0, 0),
4553 F_PCM( 512000, pll4, 4, 1, 192),
4554 F_PCM( 768000, pll4, 4, 1, 128),
4555 F_PCM( 1024000, pll4, 4, 1, 96),
4556 F_PCM( 1536000, pll4, 4, 1, 64),
4557 F_PCM( 2048000, pll4, 4, 1, 48),
4558 F_PCM( 3072000, pll4, 4, 1, 32),
4559 F_PCM( 4096000, pll4, 4, 1, 24),
4560 F_PCM( 6144000, pll4, 4, 1, 16),
4561 F_PCM( 8192000, pll4, 4, 1, 12),
4562 F_PCM(12288000, pll4, 4, 1, 8),
4563 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004564 F_END
4565};
4566
4567static struct rcg_clk pcm_clk = {
4568 .b = {
4569 .ctl_reg = LCC_PCM_NS_REG,
4570 .en_mask = BIT(11),
4571 .reset_reg = LCC_PCM_NS_REG,
4572 .reset_mask = BIT(13),
4573 .halt_reg = LCC_PCM_STATUS_REG,
4574 .halt_check = ENABLE,
4575 .halt_bit = 0,
4576 },
4577 .ns_reg = LCC_PCM_NS_REG,
4578 .md_reg = LCC_PCM_MD_REG,
4579 .root_en_mask = BIT(9),
4580 .ns_mask = (BM(31, 16) | BM(6, 0)),
4581 .set_rate = set_rate_mnd,
4582 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004583 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004584 .c = {
4585 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004586 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004587 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004588 CLK_INIT(pcm_clk.c),
4589 },
4590};
4591
4592static struct rcg_clk audio_slimbus_clk = {
4593 .b = {
4594 .ctl_reg = LCC_SLIMBUS_NS_REG,
4595 .en_mask = BIT(10),
4596 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4597 .reset_mask = BIT(5),
4598 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4599 .halt_check = ENABLE,
4600 .halt_bit = 0,
4601 },
4602 .ns_reg = LCC_SLIMBUS_NS_REG,
4603 .md_reg = LCC_SLIMBUS_MD_REG,
4604 .root_en_mask = BIT(9),
4605 .ns_mask = (BM(31, 24) | BM(6, 0)),
4606 .set_rate = set_rate_mnd,
4607 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004608 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004609 .c = {
4610 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004611 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004612 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004613 CLK_INIT(audio_slimbus_clk.c),
4614 },
4615};
4616
4617static struct branch_clk sps_slimbus_clk = {
4618 .b = {
4619 .ctl_reg = LCC_SLIMBUS_NS_REG,
4620 .en_mask = BIT(12),
4621 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4622 .halt_check = ENABLE,
4623 .halt_bit = 1,
4624 },
4625 .parent = &audio_slimbus_clk.c,
4626 .c = {
4627 .dbg_name = "sps_slimbus_clk",
4628 .ops = &clk_ops_branch,
4629 CLK_INIT(sps_slimbus_clk.c),
4630 },
4631};
4632
4633static struct branch_clk slimbus_xo_src_clk = {
4634 .b = {
4635 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4636 .en_mask = BIT(2),
4637 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004638 .halt_bit = 28,
4639 },
4640 .parent = &sps_slimbus_clk.c,
4641 .c = {
4642 .dbg_name = "slimbus_xo_src_clk",
4643 .ops = &clk_ops_branch,
4644 CLK_INIT(slimbus_xo_src_clk.c),
4645 },
4646};
4647
Matt Wagantall735f01a2011-08-12 12:40:28 -07004648DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4649DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4650DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4651DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4652DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4653DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4654DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4655DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004656
4657static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4658static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
Manu Gautam7483f172011-11-08 15:22:26 +05304659static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c);
4660static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004661static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4662static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4663static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4664static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4665static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4666static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
Stephen Boyd1c51a492011-10-26 12:11:47 -07004667static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004668
4669static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
4670/*
4671 * TODO: replace dummy_clk below with ebi1_clk.c once the
4672 * bus driver starts voting on ebi1 rates.
4673 */
4674static DEFINE_CLK_VOTER(ebi1_adm_clk, &dummy_clk);
4675
4676#ifdef CONFIG_DEBUG_FS
4677struct measure_sel {
4678 u32 test_vector;
4679 struct clk *clk;
4680};
4681
Matt Wagantall8b38f942011-08-02 18:23:18 -07004682static DEFINE_CLK_MEASURE(l2_m_clk);
4683static DEFINE_CLK_MEASURE(krait0_m_clk);
4684static DEFINE_CLK_MEASURE(krait1_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004685static DEFINE_CLK_MEASURE(q6sw_clk);
4686static DEFINE_CLK_MEASURE(q6fw_clk);
4687static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004688
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004689static struct measure_sel measure_mux[] = {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004690 { TEST_PER_LS(0x05), &qdss_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004691 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4692 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4693 { TEST_PER_LS(0x13), &sdc1_clk.c },
4694 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4695 { TEST_PER_LS(0x15), &sdc2_clk.c },
4696 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4697 { TEST_PER_LS(0x17), &sdc3_clk.c },
4698 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4699 { TEST_PER_LS(0x19), &sdc4_clk.c },
4700 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4701 { TEST_PER_LS(0x1B), &sdc5_clk.c },
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004702 { TEST_PER_LS(0x1F), &gp0_clk.c },
4703 { TEST_PER_LS(0x20), &gp1_clk.c },
4704 { TEST_PER_LS(0x21), &gp2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004705 { TEST_PER_LS(0x25), &dfab_clk.c },
4706 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4707 { TEST_PER_LS(0x26), &pmem_clk.c },
4708 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4709 { TEST_PER_LS(0x33), &cfpb_clk.c },
4710 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4711 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4712 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4713 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4714 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4715 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4716 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4717 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4718 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4719 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4720 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4721 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4722 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4723 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4724 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4725 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4726 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4727 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4728 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4729 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4730 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4731 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4732 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4733 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4734 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4735 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4736 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4737 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4738 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4739 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4740 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4741 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4742 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4743 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4744 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4745 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4746 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004747 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4748 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4749 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4750 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4751 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4752 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4753 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4754 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4755 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004756 { TEST_PER_LS(0x78), &sfpb_clk.c },
4757 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4758 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4759 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4760 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4761 { TEST_PER_LS(0x7D), &prng_clk.c },
4762 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4763 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4764 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4765 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004766 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4767 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4768 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004769 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4770 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4771 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4772 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4773 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4774 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4775 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4776 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4777 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4778 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004779 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004780 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4781
4782 { TEST_PER_HS(0x07), &afab_clk.c },
4783 { TEST_PER_HS(0x07), &afab_a_clk.c },
4784 { TEST_PER_HS(0x18), &sfab_clk.c },
4785 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004786 { TEST_PER_HS(0x26), &q6sw_clk },
4787 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004788 { TEST_PER_HS(0x2A), &adm0_clk.c },
4789 { TEST_PER_HS(0x34), &ebi1_clk.c },
4790 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004791 { TEST_PER_HS(0x48), &qdss_at_clk.c },
4792 { TEST_PER_HS(0x49), &qdss_pclkdbg_clk.c },
4793 { TEST_PER_HS(0x4A), &qdss_traceclkin_clk.c },
4794 { TEST_PER_HS(0x4B), &qdss_tsctr_clk.c },
4795 { TEST_PER_HS(0x4F), &qdss_stm_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004796 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004797
4798 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4799 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4800 { TEST_MM_LS(0x02), &cam1_clk.c },
4801 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004802 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004803 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4804 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4805 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4806 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4807 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4808 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4809 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4810 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4811 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4812 { TEST_MM_LS(0x12), &imem_p_clk.c },
4813 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4814 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4815 { TEST_MM_LS(0x16), &rot_p_clk.c },
4816 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4817 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4818 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4819 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4820 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4821 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4822 { TEST_MM_LS(0x1D), &cam0_clk.c },
4823 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4824 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4825 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4826 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4827 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4828 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4829 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4830 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004831 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004832 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004833
4834 { TEST_MM_HS(0x00), &csi0_clk.c },
4835 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004836 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004837 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4838 { TEST_MM_HS(0x06), &vfe_clk.c },
4839 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4840 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4841 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4842 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4843 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4844 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4845 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4846 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4847 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4848 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4849 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4850 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4851 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4852 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4853 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4854 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4855 { TEST_MM_HS(0x1A), &mdp_clk.c },
4856 { TEST_MM_HS(0x1B), &rot_clk.c },
4857 { TEST_MM_HS(0x1C), &vpe_clk.c },
4858 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4859 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4860 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4861 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4862 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4863 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4864 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4865 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4866 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4867 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4868 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004869 { TEST_MM_HS(0x2D), &csi2_clk.c },
4870 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4871 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4872 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4873 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4874 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004875 { TEST_MM_HS(0x33), &vcap_clk.c },
4876 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004877 { TEST_MM_HS(0x36), &vcap_axi_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004878 { TEST_MM_HS(0x39), &gfx3d_axi_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004879
4880 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4881 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4882 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4883 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4884 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4885 { TEST_LPA(0x14), &pcm_clk.c },
4886 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004887
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004888 { TEST_LPA_HS(0x00), &q6_func_clk },
4889
Stephen Boyd46fdf0d2011-11-22 12:25:09 -08004890 { TEST_CPUL2(0x2), &l2_m_clk },
4891 { TEST_CPUL2(0x0), &krait0_m_clk },
4892 { TEST_CPUL2(0x1), &krait1_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004893};
4894
4895static struct measure_sel *find_measure_sel(struct clk *clk)
4896{
4897 int i;
4898
4899 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4900 if (measure_mux[i].clk == clk)
4901 return &measure_mux[i];
4902 return NULL;
4903}
4904
Matt Wagantall8b38f942011-08-02 18:23:18 -07004905static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004906{
4907 int ret = 0;
4908 u32 clk_sel;
4909 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004910 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004911 unsigned long flags;
4912
4913 if (!parent)
4914 return -EINVAL;
4915
4916 p = find_measure_sel(parent);
4917 if (!p)
4918 return -EINVAL;
4919
4920 spin_lock_irqsave(&local_clock_reg_lock, flags);
4921
Matt Wagantall8b38f942011-08-02 18:23:18 -07004922 /*
4923 * Program the test vector, measurement period (sample_ticks)
4924 * and scaling multiplier.
4925 */
4926 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004927 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004928 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004929 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4930 case TEST_TYPE_PER_LS:
4931 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4932 break;
4933 case TEST_TYPE_PER_HS:
4934 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4935 break;
4936 case TEST_TYPE_MM_LS:
4937 writel_relaxed(0x4030D97, CLK_TEST_REG);
4938 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4939 break;
4940 case TEST_TYPE_MM_HS:
4941 writel_relaxed(0x402B800, CLK_TEST_REG);
4942 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4943 break;
4944 case TEST_TYPE_LPA:
4945 writel_relaxed(0x4030D98, CLK_TEST_REG);
4946 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4947 LCC_CLK_LS_DEBUG_CFG_REG);
4948 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004949 case TEST_TYPE_LPA_HS:
4950 writel_relaxed(0x402BC00, CLK_TEST_REG);
4951 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4952 LCC_CLK_HS_DEBUG_CFG_REG);
4953 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004954 case TEST_TYPE_CPUL2:
4955 writel_relaxed(0x4030400, CLK_TEST_REG);
4956 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4957 clk->sample_ticks = 0x4000;
4958 clk->multiplier = 2;
4959 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004960 default:
4961 ret = -EPERM;
4962 }
4963 /* Make sure test vector is set before starting measurements. */
4964 mb();
4965
4966 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4967
4968 return ret;
4969}
4970
4971/* Sample clock for 'ticks' reference clock ticks. */
4972static u32 run_measurement(unsigned ticks)
4973{
4974 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004975 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4976
4977 /* Wait for timer to become ready. */
4978 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4979 cpu_relax();
4980
4981 /* Run measurement and wait for completion. */
4982 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4983 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4984 cpu_relax();
4985
4986 /* Stop counters. */
4987 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4988
4989 /* Return measured ticks. */
4990 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4991}
4992
4993
4994/* Perform a hardware rate measurement for a given clock.
4995 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004996static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004997{
4998 unsigned long flags;
4999 u32 pdm_reg_backup, ringosc_reg_backup;
5000 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07005001 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005002 unsigned ret;
5003
5004 spin_lock_irqsave(&local_clock_reg_lock, flags);
5005
5006 /* Enable CXO/4 and RINGOSC branch and root. */
5007 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
5008 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
5009 writel_relaxed(0x2898, PDM_CLK_NS_REG);
5010 writel_relaxed(0xA00, RINGOSC_NS_REG);
5011
5012 /*
5013 * The ring oscillator counter will not reset if the measured clock
5014 * is not running. To detect this, run a short measurement before
5015 * the full measurement. If the raw results of the two are the same
5016 * then the clock must be off.
5017 */
5018
5019 /* Run a short measurement. (~1 ms) */
5020 raw_count_short = run_measurement(0x1000);
5021 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07005022 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005023
5024 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
5025 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
5026
5027 /* Return 0 if the clock is off. */
5028 if (raw_count_full == raw_count_short)
5029 ret = 0;
5030 else {
5031 /* Compute rate in Hz. */
5032 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07005033 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
5034 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005035 }
5036
5037 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07005038 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005039 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
5040
5041 return ret;
5042}
5043#else /* !CONFIG_DEBUG_FS */
5044static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
5045{
5046 return -EINVAL;
5047}
5048
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07005049static unsigned long measure_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005050{
5051 return 0;
5052}
5053#endif /* CONFIG_DEBUG_FS */
5054
5055static struct clk_ops measure_clk_ops = {
5056 .set_parent = measure_clk_set_parent,
5057 .get_rate = measure_clk_get_rate,
5058 .is_local = local_clk_is_local,
5059};
5060
Matt Wagantall8b38f942011-08-02 18:23:18 -07005061static struct measure_clk measure_clk = {
5062 .c = {
5063 .dbg_name = "measure_clk",
5064 .ops = &measure_clk_ops,
5065 CLK_INIT(measure_clk.c),
5066 },
5067 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005068};
5069
Tianyi Goua8b3cce2011-11-08 14:37:26 -08005070static struct clk_lookup msm_clocks_8064[] = {
Tianyi Gou41515e22011-09-01 19:37:43 -07005071 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005072 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005073 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
Tianyi Gouc29c3242011-10-12 21:02:15 -07005074 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005075 CLK_LOOKUP("measure", measure_clk.c, "debug"),
5076
5077 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
5078 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
5079 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
5080 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
5081 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
5082 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
5083 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
5084 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
5085 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
5086 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
5087 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
5088 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
5089 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
5090 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
5091 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
5092 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
5093
Matt Wagantall7625a4c2011-11-01 16:17:53 -07005094 CLK_LOOKUP("core_clk", gp0_clk.c, NULL),
5095 CLK_LOOKUP("core_clk", gp1_clk.c, NULL),
5096 CLK_LOOKUP("core_clk", gp2_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005097 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
5098 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
5099 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
5100 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
5101 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, NULL),
5102 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, NULL),
5103 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
5104 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, NULL),
5105 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
5106 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, NULL),
5107 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, NULL),
5108 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
5109 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
5110 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005111 CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005112 CLK_LOOKUP("pmem_clk", pmem_clk.c, NULL),
Ramesh Masavarapuf46be1b2011-11-03 11:13:41 -07005113 CLK_DUMMY("core_clk", PRNG_CLK, "msm_rng.0", OFF),
Tianyi Gou43208a02011-09-27 15:35:13 -07005114 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5115 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5116 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5117 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005118 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
5119 CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
Tianyi Gou4496fba2011-10-12 11:40:15 -07005120 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
Manu Gautam7483f172011-11-08 15:22:26 +05305121 CLK_LOOKUP("core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"),
5122 CLK_LOOKUP("core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"),
Tianyi Gou4496fba2011-10-12 11:40:15 -07005123 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
5124 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
5125 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005126 CLK_LOOKUP("iface_clk", ce1_p_clk.c, NULL),
5127 CLK_LOOKUP("core_clk", ce1_core_clk.c, NULL),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07005128 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005129 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, NULL),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07005130 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
5131 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
5132 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
5133 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
5134 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
5135 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005136 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
5137 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
5138 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
5139 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, NULL),
5140 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, NULL),
5141 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, NULL),
5142 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
5143 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005144 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Tianyi Gou4496fba2011-10-12 11:40:15 -07005145 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
5146 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
Manu Gautam7483f172011-11-08 15:22:26 +05305147 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"),
5148 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"),
Tianyi Gou43208a02011-09-27 15:35:13 -07005149 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5150 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5151 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5152 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005153 CLK_LOOKUP("iface_clk", pcie_p_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005154 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5155 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005156 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
5157 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
5158 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
5159 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
5160 CLK_LOOKUP("core_clk", amp_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005161 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5162 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
5163 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5164 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5165 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07005166 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005167 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
5168 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
5169 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07005170 CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005171 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
5172 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
5173 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07005174 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005175 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
5176 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
5177 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07005178 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, NULL),
5179 CLK_LOOKUP("csi_pix_clk", csi_pix1_clk.c, NULL),
5180 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, NULL),
5181 CLK_LOOKUP("csi_rdi_clk", csi_rdi1_clk.c, NULL),
5182 CLK_LOOKUP("csi_rdi_clk", csi_rdi2_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005183 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
5184 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, NULL),
5185 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, NULL),
5186 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, NULL),
5187 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5188 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5189 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5190 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
5191 CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
5192 CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
Pu Chen86b4be92011-11-03 17:27:57 -07005193 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005194 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5195 CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005196 CLK_LOOKUP("iface_clk", vcap_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005197 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
5198 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005199 CLK_LOOKUP("core_clk", vcap_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005200 CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005201 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005202 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005203 CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
5204 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005205 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005206 CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005207 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005208 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005209 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
5210 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005211 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005212 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005213 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
Greg Griscofa47b532011-11-11 10:32:06 -08005214 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005215 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005216 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
5217 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005218 CLK_LOOKUP("core_clk", hdmi_app_clk.c, NULL),
5219 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005220 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005221 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005222 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005223 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005224 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5225 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5226 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5227 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5228 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5229 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5230 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005231 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
5232 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
5233 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5234 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5235 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5236 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Pu Chen86b4be92011-11-03 17:27:57 -07005237 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005238 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005239 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, NULL),
5240 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, NULL),
5241 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005242 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005243 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
5244 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005245 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005246 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005247 CLK_LOOKUP("iface_clk", smmu_p_clk.c, NULL),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005248 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005249 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Greg Griscofa47b532011-11-11 10:32:06 -08005250 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005251 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005252 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005253 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005254 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005255 CLK_LOOKUP("iface_pclk", vpe_p_clk.c, "footswitch-8x60.9"),
Tianyi Gouc29c3242011-10-12 21:02:15 -07005256 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
5257 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
5258 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
5259 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
5260 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
5261 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
5262 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
5263 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
5264 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
5265 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
5266 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
Tianyi Goudd8138a2011-10-20 15:46:00 -07005267 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5268 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005269 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, NULL),
5270 CLK_LOOKUP("core_clk", vpe_axi_clk.c, NULL),
5271 CLK_LOOKUP("core_clk", mdp_axi_clk.c, NULL),
5272 CLK_LOOKUP("core_clk", vcap_axi_clk.c, NULL),
5273 CLK_LOOKUP("core_clk", rot_axi_clk.c, NULL),
5274 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, NULL),
5275 CLK_LOOKUP("core_clk", vfe_axi_clk.c, NULL),
5276 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, NULL),
5277 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07005278 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005279 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
5280 CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
Manu Gautam7483f172011-11-08 15:22:26 +05305281 CLK_DUMMY("bus_clk", DFAB_USB_HS3_CLK, "msm_ehci_host.0", 0),
5282 CLK_DUMMY("bus_clk", DFAB_USB_HS4_CLK, "msm_ehci_host.1", 0),
Tianyi Gou41515e22011-09-01 19:37:43 -07005283 CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, NULL, 0),
5284 CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, NULL, 0),
5285 CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, NULL, 0),
5286 CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, NULL, 0),
5287 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
5288 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
5289 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
5290 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
5291 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
5292 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
5293
5294 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
Jeff Ohlstein8c116c72011-10-27 17:34:48 -07005295 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005296
5297 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
5298 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
5299 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
5300};
5301
Stephen Boyd94625ef2011-07-12 17:06:01 -07005302static struct clk_lookup msm_clocks_8960_v1[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005303 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
5304 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5305 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5306 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005307 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005308
5309 CLK_LOOKUP("afab_clk", afab_clk.c, NULL),
5310 CLK_LOOKUP("afab_a_clk", afab_a_clk.c, NULL),
5311 CLK_LOOKUP("cfpb_clk", cfpb_clk.c, NULL),
5312 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, NULL),
Stephen Boyd85436132011-09-16 18:55:13 -07005313 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005314 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
5315 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
5316 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
5317 CLK_LOOKUP("ebi1_a_clk", ebi1_a_clk.c, NULL),
5318 CLK_LOOKUP("mmfab_clk", mmfab_clk.c, NULL),
5319 CLK_LOOKUP("mmfab_a_clk", mmfab_a_clk.c, NULL),
5320 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5321 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, NULL),
Stephen Boyda3787f32011-09-16 18:55:13 -07005322 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005323 CLK_LOOKUP("sfab_clk", sfab_clk.c, NULL),
5324 CLK_LOOKUP("sfab_a_clk", sfab_a_clk.c, NULL),
5325 CLK_LOOKUP("sfpb_clk", sfpb_clk.c, NULL),
5326 CLK_LOOKUP("sfpb_a_clk", sfpb_a_clk.c, NULL),
5327
Matt Wagantall7625a4c2011-11-01 16:17:53 -07005328 CLK_LOOKUP("core_clk", gp0_clk.c, NULL),
5329 CLK_LOOKUP("core_clk", gp1_clk.c, NULL),
5330 CLK_LOOKUP("core_clk", gp2_clk.c, NULL),
Matt Wagantalle2522372011-08-17 14:52:21 -07005331 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
5332 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
5333 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
5334 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
5335 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5336 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
5337 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
5338 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, NULL),
5339 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, NULL),
5340 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, NULL),
5341 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, NULL),
5342 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005343 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005344 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005345 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5346 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005347 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
5348 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
5349 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
5350 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, NULL),
5351 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005352 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005353 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005354 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005355 CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005356 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005357 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005358 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5359 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5360 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5361 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5362 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005363 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07005364 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005365 CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005366 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
5367 CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
5368 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
5369 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
5370 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
5371 CLK_LOOKUP("usb_fs_clk", usb_fs2_xcvr_clk.c, NULL),
5372 CLK_LOOKUP("usb_fs_sys_clk", usb_fs2_sys_clk.c, NULL),
5373 CLK_LOOKUP("usb_fs_src_clk", usb_fs2_src_clk.c, NULL),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005374 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005375 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005376 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005377 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005378 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005379 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005380 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005381 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5382 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005383 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5384 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005385 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
5386 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, NULL),
5387 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005388 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005389 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005390 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07005391 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005392 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
5393 CLK_LOOKUP("usb_fs_pclk", usb_fs2_p_clk.c, NULL),
5394 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005395 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5396 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5397 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5398 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5399 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005400 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5401 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005402 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
5403 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
5404 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
5405 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
5406 CLK_LOOKUP("core_clk", amp_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005407 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5408 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
5409 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_imx074.0"),
Rajakumar Govindaram6bc004a2011-12-05 20:58:19 -08005410 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_mt9m114.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005411 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_ov2720.0"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005412 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5413 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5414 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5415 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5416 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5417 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
Kevin Chane12c6672011-10-26 11:55:26 -07005418 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5419 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
Kevin Chanf6216f22011-10-25 18:40:11 -07005420 CLK_LOOKUP("csiphy_timer_src_clk",
5421 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5422 CLK_LOOKUP("csiphy_timer_src_clk",
5423 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5424 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5425 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005426 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5427 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5428 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5429 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005430 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005431 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005432 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005433 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005434 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005435 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5436 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005437 CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005438 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005439 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005440 CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005441 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005442 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005443 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
5444 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07005445 CLK_LOOKUP("qdss_pclk", qdss_p_clk.c, NULL),
5446 CLK_LOOKUP("qdss_at_clk", qdss_at_clk.c, NULL),
5447 CLK_LOOKUP("qdss_pclkdbg_clk", qdss_pclkdbg_clk.c, NULL),
5448 CLK_LOOKUP("qdss_traceclkin_clk", qdss_traceclkin_clk.c, NULL),
5449 CLK_LOOKUP("qdss_tsctr_clk", qdss_tsctr_clk.c, NULL),
5450 CLK_LOOKUP("qdss_stm_clk", qdss_stm_clk.c, NULL),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005451 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005452 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005453 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
5454 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
5455 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005456 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005457 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005458 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
5459 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005460 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Kevin Chana0853122011-11-07 19:48:44 -08005461 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005462 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chan5827c552011-10-28 18:36:32 -07005463 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005464 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chan5827c552011-10-28 18:36:32 -07005465 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005466 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5467 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5468 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5469 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5470 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5471 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5472 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005473 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005474 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5475 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005476 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5477 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5478 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5479 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005480 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005481 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005482 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005483 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005484 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005485 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005486 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5487 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005488 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005489 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005490 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005491 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005492 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005493 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005494 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005495 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005496 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005497 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005498 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005499 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chan5827c552011-10-28 18:36:32 -07005500 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005501 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chana0853122011-11-07 19:48:44 -08005502 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005503 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005504 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
5505 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
5506 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
5507 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
5508 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
5509 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
5510 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
5511 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
5512 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
5513 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
5514 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
5515 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5516 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
Matt Wagantalle604d712011-10-21 15:38:18 -07005517 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5518 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5519 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5520 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5521 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5522 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5523 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5524 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5525 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5526 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
5527 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5528 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005529 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5530 CLK_LOOKUP("dfab_usb_hs_clk", dfab_usb_hs_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005531 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5532 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5533 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5534 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5535 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005536 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005537 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005538
5539 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005540 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005541
5542 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
5543 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
5544 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
Stephen Boyd3939c8d2011-08-29 17:36:22 -07005545 CLK_LOOKUP("q6sw_clk", q6sw_clk, NULL),
5546 CLK_LOOKUP("q6fw_clk", q6fw_clk, NULL),
5547 CLK_LOOKUP("q6_func_clk", q6_func_clk, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005548};
5549
Stephen Boyd94625ef2011-07-12 17:06:01 -07005550static struct clk_lookup msm_clocks_8960_v2[] __initdata = {
5551 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
5552 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5553 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
Kevin Chane12c6672011-10-26 11:55:26 -07005554 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5555 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5556 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
Stephen Boyd94625ef2011-07-12 17:06:01 -07005557 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5558 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
5559 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
5560 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
5561 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
5562 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
5563 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
5564};
5565
5566/* Add v2 clocks dynamically at runtime */
5567static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_v1) +
5568 ARRAY_SIZE(msm_clocks_8960_v2)];
5569
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005570/*
5571 * Miscellaneous clock register initializations
5572 */
5573
5574/* Read, modify, then write-back a register. */
5575static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5576{
5577 uint32_t regval = readl_relaxed(reg);
5578 regval &= ~mask;
5579 regval |= val;
5580 writel_relaxed(regval, reg);
5581}
5582
Tianyi Gou41515e22011-09-01 19:37:43 -07005583static void __init set_fsm_mode(void __iomem *mode_reg)
5584{
5585 u32 regval = readl_relaxed(mode_reg);
5586
5587 /*De-assert reset to FSM */
5588 regval &= ~BIT(21);
5589 writel_relaxed(regval, mode_reg);
5590
5591 /* Program bias count */
Tianyi Gou358c3862011-10-18 17:03:41 -07005592 regval &= ~BM(19, 14);
5593 regval |= BVAL(19, 14, 0x1);
5594 writel_relaxed(regval, mode_reg);
5595
5596 /* Program lock count */
Tianyi Gou41515e22011-09-01 19:37:43 -07005597 regval &= ~BM(13, 8);
5598 regval |= BVAL(13, 8, 0x8);
5599 writel_relaxed(regval, mode_reg);
5600
5601 /*Enable PLL FSM voting */
5602 regval |= BIT(20);
5603 writel_relaxed(regval, mode_reg);
5604}
5605
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005606static void __init reg_init(void)
5607{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005608 /* Deassert MM SW_RESET_ALL signal. */
5609 writel_relaxed(0, SW_RESET_ALL_REG);
5610
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005611 /*
5612 * Some bits are only used on either 8960 or 8064 and are marked as
5613 * reserved bits on the other SoC. Writing to these reserved bits
5614 * should have no effect.
5615 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005616 /* Initialize MM AHB registers: Enable the FPB clock and disable HW
5617 * gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
5618 * prevent its memory from being collapsed when the clock is halted.
5619 * The sleep and wake-up delays are set to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005620 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
5621 writel_relaxed(0x000007F9, AHB_EN2_REG);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005622 if (cpu_is_apq8064())
5623 rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005624
5625 /* Deassert all locally-owned MM AHB resets. */
5626 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07005627 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005628
5629 /* Initialize MM AXI registers: Enable HW gating for all clocks that
5630 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
5631 * delays to safe values. */
5632 /* TODO: Enable HW Gating */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005633 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
5634 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
5635 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
5636 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005637 if (cpu_is_apq8064())
5638 rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005639 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005640
5641 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
5642 * memories retain state even when not clocked. Also, set sleep and
5643 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005644 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
5645 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
5646 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
5647 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
5648 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
5649 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
Tarun Karra6fbc00a2011-12-13 09:23:47 -07005650 rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005651 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
5652 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
5653 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
5654 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
5655 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005656 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
5657 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
5658 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005659 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005660 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005661 if (cpu_is_msm8960() || cpu_is_msm8930()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005662 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
5663 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
5664 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
5665 }
5666 if (cpu_is_apq8064()) {
5667 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07005668 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005669 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005670
Tianyi Gou41515e22011-09-01 19:37:43 -07005671 /*
5672 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
5673 * core remain active during halt state of the clk. Also, set sleep
5674 * and wake-up value to max.
5675 */
5676 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005677 if (cpu_is_apq8064()) {
5678 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
5679 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
5680 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005681
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005682 /* De-assert MM AXI resets to all hardware blocks. */
5683 writel_relaxed(0, SW_RESET_AXI_REG);
5684
5685 /* Deassert all MM core resets. */
5686 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005687 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005688
5689 /* Reset 3D core once more, with its clock enabled. This can
5690 * eventually be done as part of the GDFS footswitch driver. */
5691 clk_set_rate(&gfx3d_clk.c, 27000000);
5692 clk_enable(&gfx3d_clk.c);
5693 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
5694 mb();
5695 udelay(5);
5696 writel_relaxed(0, SW_RESET_CORE_REG);
5697 /* Make sure reset is de-asserted before clock is disabled. */
5698 mb();
5699 clk_disable(&gfx3d_clk.c);
5700
5701 /* Enable TSSC and PDM PXO sources. */
5702 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
5703 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
5704
5705 /* Source SLIMBus xo src from slimbus reference clock */
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005706 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005707 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005708
5709 /* Source the dsi_byte_clks from the DSI PHY PLLs */
5710 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
5711 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07005712
5713 /* Source the sata_phy_ref_clk from PXO */
5714 if (cpu_is_apq8064())
5715 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
5716
5717 /*
5718 * TODO: Programming below PLLs is temporary and needs to be removed
5719 * after bootloaders program them.
5720 */
5721 if (cpu_is_apq8064()) {
5722 u32 regval, is_pll_enabled;
5723
5724 /* Program pxo_src_clk to source from PXO */
5725 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
5726
5727 /* Check if PLL8 is active */
5728 is_pll_enabled = readl_relaxed(BB_PLL8_STATUS_REG) & BIT(16);
5729 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005730 /* Ref clk = 27MHz and program pll8 to 384MHz */
5731 writel_relaxed(0xE, BB_PLL8_L_VAL_REG);
5732 writel_relaxed(0x2, BB_PLL8_M_VAL_REG);
5733 writel_relaxed(0x9, BB_PLL8_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005734
5735 regval = readl_relaxed(BB_PLL8_CONFIG_REG);
5736
5737 /* Enable the main output and the MN accumulator */
5738 regval |= BIT(23) | BIT(22);
5739
5740 /* Set pre-divider and post-divider values to 1 and 1 */
5741 regval &= ~BIT(19);
5742 regval &= ~BM(21, 20);
5743
5744 writel_relaxed(regval, BB_PLL8_CONFIG_REG);
5745
5746 /* Set VCO frequency */
5747 rmwreg(0x10000, BB_PLL8_CONFIG_REG, 0x30000);
5748
5749 /* Enable AUX output */
5750 regval = readl_relaxed(BB_PLL8_TEST_CTL_REG);
5751 regval |= BIT(12);
5752 writel_relaxed(regval, BB_PLL8_TEST_CTL_REG);
5753
5754 set_fsm_mode(BB_PLL8_MODE_REG);
5755 }
5756 /* Check if PLL3 is active */
5757 is_pll_enabled = readl_relaxed(GPLL1_STATUS_REG) & BIT(16);
5758 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005759 /* Ref clk = 27MHz and program pll3 to 1200MHz */
5760 writel_relaxed(0x2C, GPLL1_L_VAL_REG);
5761 writel_relaxed(0x4, GPLL1_M_VAL_REG);
5762 writel_relaxed(0x9, GPLL1_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005763
5764 regval = readl_relaxed(GPLL1_CONFIG_REG);
5765
5766 /* Set pre-divider and post-divider values to 1 and 1 */
5767 regval &= ~BIT(15);
5768 regval |= BIT(16);
5769
5770 writel_relaxed(regval, GPLL1_CONFIG_REG);
5771
5772 /* Set VCO frequency */
5773 rmwreg(0x180, GPLL1_CONFIG_REG, 0x180);
5774 }
5775 /* Check if PLL14 is active */
5776 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
5777 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005778 /* Ref clk = 27MHz and program pll14 to 480MHz */
5779 writel_relaxed(0x11, BB_PLL14_L_VAL_REG);
5780 writel_relaxed(0x7, BB_PLL14_M_VAL_REG);
5781 writel_relaxed(0x9, BB_PLL14_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005782
5783 regval = readl_relaxed(BB_PLL14_CONFIG_REG);
5784
5785 /* Enable the main output and the MN accumulator */
5786 regval |= BIT(23) | BIT(22);
5787
5788 /* Set pre-divider and post-divider values to 1 and 1 */
5789 regval &= ~BIT(19);
5790 regval &= ~BM(21, 20);
5791
5792 writel_relaxed(regval, BB_PLL14_CONFIG_REG);
5793
5794 /* Set VCO frequency */
5795 rmwreg(0x10000, BB_PLL14_CONFIG_REG, 0x30000);
5796
Tianyi Gou41515e22011-09-01 19:37:43 -07005797 set_fsm_mode(BB_PLL14_MODE_REG);
5798 }
Tianyi Gou621f8742011-09-01 21:45:01 -07005799 /* Program PLL2 to 800MHz with ref clk = 27MHz */
5800 writel_relaxed(0x1D, MM_PLL1_L_VAL_REG);
5801 writel_relaxed(0x11, MM_PLL1_M_VAL_REG);
5802 writel_relaxed(0x1B, MM_PLL1_N_VAL_REG);
5803
5804 regval = readl_relaxed(MM_PLL1_CONFIG_REG);
5805
5806 /* Enable the main output and the MN accumulator */
5807 regval |= BIT(23) | BIT(22);
5808
5809 /* Set pre-divider and post-divider values to 1 and 1 */
5810 regval &= ~BIT(19);
5811 regval &= ~BM(21, 20);
5812
5813 writel_relaxed(regval, MM_PLL1_CONFIG_REG);
5814
5815 /* Set VCO frequency */
5816 rmwreg(0x20000, MM_PLL1_CONFIG_REG, 0x30000);
5817
Tianyi Gou621f8742011-09-01 21:45:01 -07005818 /* Program PLL15 to 975MHz with ref clk = 27MHz */
5819 writel_relaxed(0x24, MM_PLL3_L_VAL_REG);
5820 writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
5821 writel_relaxed(0x9, MM_PLL3_N_VAL_REG);
5822
5823 regval = readl_relaxed(MM_PLL3_CONFIG_REG);
5824
5825 /* Enable the main output and the MN accumulator */
5826 regval |= BIT(23) | BIT(22);
5827
5828 /* Set pre-divider and post-divider values to 1 and 1 */
5829 regval &= ~BIT(19);
5830 regval &= ~BM(21, 20);
5831
5832 writel_relaxed(regval, MM_PLL3_CONFIG_REG);
5833
5834 /* Set VCO frequency */
5835 rmwreg(0x20000, MM_PLL3_CONFIG_REG, 0x30000);
5836
5837 /* Enable AUX output */
5838 regval = readl_relaxed(MM_PLL3_TEST_CTL_REG);
5839 regval |= BIT(12);
5840 writel_relaxed(regval, MM_PLL3_TEST_CTL_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005841
5842 /* Check if PLL4 is active */
5843 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
5844 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005845 /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
5846 writel_relaxed(0xE, LCC_PLL0_L_VAL_REG);
5847 writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG);
5848 writel_relaxed(0x465, LCC_PLL0_N_VAL_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005849
5850 regval = readl_relaxed(LCC_PLL0_CONFIG_REG);
5851
5852 /* Enable the main output and the MN accumulator */
5853 regval |= BIT(23) | BIT(22);
5854
5855 /* Set pre-divider and post-divider values to 1 and 1 */
5856 regval &= ~BIT(19);
5857 regval &= ~BM(21, 20);
5858
5859 /* Set VCO frequency */
5860 regval &= ~BM(17, 16);
5861 writel_relaxed(regval, LCC_PLL0_CONFIG_REG);
5862
5863 set_fsm_mode(LCC_PLL0_MODE_REG);
5864 }
5865
5866 /* Enable PLL4 source on the LPASS Primary PLL Mux */
5867 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005868 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005869}
5870
Stephen Boyd94625ef2011-07-12 17:06:01 -07005871struct clock_init_data msm8960_clock_init_data __initdata;
5872
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005873/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07005874static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005875{
Stephen Boyd94625ef2011-07-12 17:06:01 -07005876 size_t num_lookups = ARRAY_SIZE(msm_clocks_8960_v1);
Tianyi Gou41515e22011-09-01 19:37:43 -07005877
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005878 xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960");
5879 if (IS_ERR(xo_pxo)) {
5880 pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
5881 BUG();
5882 }
5883 xo_cxo = msm_xo_get(MSM_XO_TCXO_D0, "clock-8960");
5884 if (IS_ERR(xo_cxo)) {
5885 pr_err("%s: msm_xo_get(CXO) failed.\n", __func__);
5886 BUG();
5887 }
5888
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005889 if (cpu_is_msm8960() || cpu_is_msm8930()) {
Tianyi Gou41515e22011-09-01 19:37:43 -07005890 memcpy(msm_clocks_8960, msm_clocks_8960_v1,
5891 sizeof(msm_clocks_8960_v1));
5892 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
5893 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960_v2;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005894
5895 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8960_v2,
5896 sizeof(gfx3d_clk.c.fmax));
5897 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8960_v2,
5898 sizeof(ijpeg_clk.c.fmax));
5899 memcpy(vfe_clk.c.fmax, fmax_vfe_8960_v2,
5900 sizeof(vfe_clk.c.fmax));
5901
Tianyi Gou41515e22011-09-01 19:37:43 -07005902 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07005903 msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
Tianyi Gou41515e22011-09-01 19:37:43 -07005904 num_lookups = ARRAY_SIZE(msm_clocks_8960);
5905 }
5906 msm8960_clock_init_data.size = num_lookups;
Stephen Boyd94625ef2011-07-12 17:06:01 -07005907 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005908
5909 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005910 * Change the freq tables for and voltage requirements for
5911 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07005912 */
5913 if (cpu_is_apq8064()) {
5914 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005915
5916 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
5917 sizeof(gfx3d_clk.c.fmax));
5918 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
5919 sizeof(ijpeg_clk.c.fmax));
5920 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
5921 sizeof(ijpeg_clk.c.fmax));
5922 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
5923 sizeof(tv_src_clk.c.fmax));
5924 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
5925 sizeof(vfe_clk.c.fmax));
5926
Tianyi Gou621f8742011-09-01 21:45:01 -07005927 gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07005928 }
Stephen Boyd94625ef2011-07-12 17:06:01 -07005929
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005930 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005931
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07005932 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005933
5934 /* Initialize clock registers. */
5935 reg_init();
5936
5937 /* Initialize rates for clocks that only support one. */
5938 clk_set_rate(&pdm_clk.c, 27000000);
5939 clk_set_rate(&prng_clk.c, 64000000);
5940 clk_set_rate(&mdp_vsync_clk.c, 27000000);
5941 clk_set_rate(&tsif_ref_clk.c, 105000);
5942 clk_set_rate(&tssc_clk.c, 27000000);
5943 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07005944 if (cpu_is_apq8064()) {
5945 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
5946 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
5947 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005948 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005949 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou41515e22011-09-01 19:37:43 -07005950 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005951 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
5952 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
5953 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07005954 /*
5955 * Set the CSI rates to a safe default to avoid warnings when
5956 * switching csi pix and rdi clocks.
5957 */
5958 clk_set_rate(&csi0_src_clk.c, 27000000);
5959 clk_set_rate(&csi1_src_clk.c, 27000000);
5960 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005961
5962 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07005963 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005964 * Toggle these clocks on and off to refresh them.
5965 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07005966 rcg_clk_enable(&pdm_clk.c);
5967 rcg_clk_disable(&pdm_clk.c);
5968 rcg_clk_enable(&tssc_clk.c);
5969 rcg_clk_disable(&tssc_clk.c);
Stephen Boyd60496bb2011-10-17 13:51:37 -07005970 if (cpu_is_msm8960() &&
5971 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
5972 clk_enable(&usb_hsic_hsic_clk.c);
5973 clk_disable(&usb_hsic_hsic_clk.c);
Stephen Boyd092fd182011-10-21 15:56:30 -07005974 } else
5975 /* CSI2 hardware not present on 8960v1 devices */
5976 pix_rdi_mux_map[2] = NULL;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005977
5978 if (machine_is_msm8960_sim()) {
5979 clk_set_rate(&sdc1_clk.c, 48000000);
5980 clk_enable(&sdc1_clk.c);
5981 clk_enable(&sdc1_p_clk.c);
5982 clk_set_rate(&sdc3_clk.c, 48000000);
5983 clk_enable(&sdc3_clk.c);
5984 clk_enable(&sdc3_p_clk.c);
5985 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005986}
5987
Stephen Boydbb600ae2011-08-02 20:11:40 -07005988static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005989{
Stephen Boyda3787f32011-09-16 18:55:13 -07005990 int rc;
5991 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07005992 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07005993
5994 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
5995 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
5996 PTR_ERR(mmfpb_a_clk)))
5997 return PTR_ERR(mmfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08005998 rc = clk_set_rate(mmfpb_a_clk, 76800000);
Stephen Boyda3787f32011-09-16 18:55:13 -07005999 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
6000 return rc;
6001 rc = clk_enable(mmfpb_a_clk);
6002 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
6003 return rc;
6004
Stephen Boyd85436132011-09-16 18:55:13 -07006005 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
6006 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
6007 PTR_ERR(cfpb_a_clk)))
6008 return PTR_ERR(cfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006009 rc = clk_set_rate(cfpb_a_clk, 64000000);
Stephen Boyd85436132011-09-16 18:55:13 -07006010 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
6011 return rc;
6012 rc = clk_enable(cfpb_a_clk);
6013 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
6014 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006015
6016 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006017}
Stephen Boydbb600ae2011-08-02 20:11:40 -07006018
6019struct clock_init_data msm8960_clock_init_data __initdata = {
6020 .table = msm_clocks_8960,
6021 .size = ARRAY_SIZE(msm_clocks_8960),
6022 .init = msm8960_clock_init,
6023 .late_init = msm8960_clock_late_init,
6024};
Tianyi Gou41515e22011-09-01 19:37:43 -07006025
6026struct clock_init_data apq8064_clock_init_data __initdata = {
6027 .table = msm_clocks_8064,
6028 .size = ARRAY_SIZE(msm_clocks_8064),
6029 .init = msm8960_clock_init,
6030 .late_init = msm8960_clock_late_init,
6031};