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Jeyaprakash Soundrapandian2474e8f2012-01-03 15:59:57 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef __ASM__ARCH_CAMERA_H
15#define __ASM__ARCH_CAMERA_H
16
17#include <linux/list.h>
18#include <linux/poll.h>
19#include <linux/cdev.h>
20#include <linux/platform_device.h>
21#include <linux/wakelock.h>
Kevin Chaneb6b6072012-01-17 11:54:54 -080022#include <linux/regulator/consumer.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070023#include "linux/types.h"
24
25#include <mach/board.h>
26#include <media/msm_camera.h>
Ankit Premrajkac6864b82011-07-15 11:43:41 -070027#include <mach/msm_subsystem_map.h>
Ankit Premrajka748a70a2011-11-01 08:22:04 -070028#include <linux/ion.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029
30#define CONFIG_MSM_CAMERA_DEBUG
31#ifdef CONFIG_MSM_CAMERA_DEBUG
32#define CDBG(fmt, args...) pr_debug(fmt, ##args)
33#else
34#define CDBG(fmt, args...) do { } while (0)
35#endif
36
37#define PAD_TO_2K(a, b) ((!b) ? a : (((a)+2047) & ~2047))
38
39#define MSM_CAMERA_MSG 0
40#define MSM_CAMERA_EVT 1
41#define NUM_WB_EXP_NEUTRAL_REGION_LINES 4
42#define NUM_WB_EXP_STAT_OUTPUT_BUFFERS 3
43#define NUM_AUTOFOCUS_MULTI_WINDOW_GRIDS 16
44#define NUM_STAT_OUTPUT_BUFFERS 3
45#define NUM_AF_STAT_OUTPUT_BUFFERS 3
Mingcheng Zhu996be182011-10-16 16:04:23 -070046#define max_control_command_size 512
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070047#define CROP_LEN 36
48
49enum vfe_mode_of_operation{
50 VFE_MODE_OF_OPERATION_CONTINUOUS,
51 VFE_MODE_OF_OPERATION_SNAPSHOT,
52 VFE_MODE_OF_OPERATION_VIDEO,
53 VFE_MODE_OF_OPERATION_RAW_SNAPSHOT,
54 VFE_MODE_OF_OPERATION_ZSL,
Jignesh Mehta6cf8a742012-02-04 23:40:50 -080055 VFE_MODE_OF_OPERATION_JPEG_SNAPSHOT,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056 VFE_LAST_MODE_OF_OPERATION_ENUM
57};
58
59enum msm_queue {
60 MSM_CAM_Q_CTRL, /* control command or control command status */
61 MSM_CAM_Q_VFE_EVT, /* adsp event */
62 MSM_CAM_Q_VFE_MSG, /* adsp message */
63 MSM_CAM_Q_V4L2_REQ, /* v4l2 request */
64 MSM_CAM_Q_VPE_MSG, /* vpe message */
65 MSM_CAM_Q_PP_MSG, /* pp message */
66};
67
68enum vfe_resp_msg {
69 VFE_EVENT,
70 VFE_MSG_GENERAL,
71 VFE_MSG_SNAPSHOT,
72 VFE_MSG_OUTPUT_P, /* preview (continuous mode ) */
73 VFE_MSG_OUTPUT_T, /* thumbnail (snapshot mode )*/
74 VFE_MSG_OUTPUT_S, /* main image (snapshot mode )*/
75 VFE_MSG_OUTPUT_V, /* video (continuous mode ) */
76 VFE_MSG_STATS_AEC,
77 VFE_MSG_STATS_AF,
78 VFE_MSG_STATS_AWB,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080079 VFE_MSG_STATS_RS, /* 10 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070080 VFE_MSG_STATS_CS,
81 VFE_MSG_STATS_IHIST,
82 VFE_MSG_STATS_SKIN,
83 VFE_MSG_STATS_WE, /* AEC + AWB */
84 VFE_MSG_SYNC_TIMER0,
85 VFE_MSG_SYNC_TIMER1,
86 VFE_MSG_SYNC_TIMER2,
87 VFE_MSG_COMMON,
Kiran Kumar H N0fb9dcf2011-07-17 12:31:53 -070088 VFE_MSG_V32_START,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080089 VFE_MSG_V32_START_RECORDING, /* 20 */
Kiran Kumar H N0fb9dcf2011-07-17 12:31:53 -070090 VFE_MSG_V32_CAPTURE,
Jignesh Mehta6cf8a742012-02-04 23:40:50 -080091 VFE_MSG_V32_JPEG_CAPTURE,
Kiran Kumar H N0fb9dcf2011-07-17 12:31:53 -070092 VFE_MSG_OUTPUT_IRQ,
Suresh Vankadara055cb8e2012-01-18 00:50:04 +053093 VFE_MSG_V2X_PREVIEW,
94 VFE_MSG_V2X_CAPTURE,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080095 VFE_MSG_OUTPUT_PRIMARY,
96 VFE_MSG_OUTPUT_SECONDARY,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070097};
98
99enum vpe_resp_msg {
100 VPE_MSG_GENERAL,
101 VPE_MSG_OUTPUT_V, /* video (continuous mode ) */
102 VPE_MSG_OUTPUT_ST_L,
103 VPE_MSG_OUTPUT_ST_R,
104};
105
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700106enum msm_stereo_state {
107 STEREO_VIDEO_IDLE,
108 STEREO_VIDEO_ACTIVE,
109 STEREO_SNAP_IDLE,
110 STEREO_SNAP_STARTED,
111 STEREO_SNAP_BUFFER1_PROCESSING,
112 STEREO_SNAP_BUFFER2_PROCESSING,
113 STEREO_RAW_SNAP_IDLE,
114 STEREO_RAW_SNAP_STARTED,
115};
116
117enum msm_ispif_intftype {
118 PIX0,
119 RDI0,
120 PIX1,
121 RDI1,
122 PIX2,
123 RDI2,
124};
125
126enum msm_ispif_vc {
127 VC0,
128 VC1,
129 VC2,
130 VC3,
131};
132
133enum msm_ispif_cid {
134 CID0,
135 CID1,
136 CID2,
137 CID3,
138 CID4,
139 CID5,
140 CID6,
141 CID7,
142 CID8,
143 CID9,
144 CID10,
145 CID11,
146 CID12,
147 CID13,
148 CID14,
149 CID15,
150};
151
152struct msm_ispif_params {
153 uint8_t intftype;
154 uint16_t cid_mask;
155 uint8_t csid;
156};
Shuzhen Wanga3c1a122011-08-04 15:33:27 -0700157
158struct msm_ispif_params_list {
159 uint32_t len;
160 struct msm_ispif_params params[3];
161};
162
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700163struct msm_vpe_phy_info {
164 uint32_t sbuf_phy;
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530165 uint32_t planar0_off;
166 uint32_t planar1_off;
167 uint32_t planar2_off;
168 uint32_t p0_phy;
169 uint32_t p1_phy;
170 uint32_t p2_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700171 uint8_t output_id; /* VFE31_OUTPUT_MODE_PT/S/V */
172 uint32_t frame_id;
173};
174
175struct msm_camera_csid_vc_cfg {
176 uint8_t cid;
177 uint8_t dt;
178 uint8_t decode_format;
179};
180
181struct msm_camera_csid_lut_params {
182 uint8_t num_cid;
183 struct msm_camera_csid_vc_cfg *vc_cfg;
184};
185
186struct msm_camera_csid_params {
187 uint8_t lane_cnt;
188 uint8_t lane_assign;
189 struct msm_camera_csid_lut_params lut_params;
190};
191
192struct msm_camera_csiphy_params {
193 uint8_t lane_cnt;
194 uint8_t settle_cnt;
195};
196
Kevin Chana980f392011-08-01 20:55:00 -0700197struct msm_camera_csi2_params {
198 struct msm_camera_csid_params csid_params;
199 struct msm_camera_csiphy_params csiphy_params;
200};
201
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700202#define VFE31_OUTPUT_MODE_PT (0x1 << 0)
203#define VFE31_OUTPUT_MODE_S (0x1 << 1)
204#define VFE31_OUTPUT_MODE_V (0x1 << 2)
205#define VFE31_OUTPUT_MODE_P (0x1 << 3)
206#define VFE31_OUTPUT_MODE_T (0x1 << 4)
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530207#define VFE31_OUTPUT_MODE_P_ALL_CHNLS (0x1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700208
209#define CSI_EMBED_DATA 0x12
Rajakumar Govindaram6bc004a2011-12-05 20:58:19 -0800210#define CSI_YUV422_8 0x1E
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700211#define CSI_RAW8 0x2A
212#define CSI_RAW10 0x2B
213#define CSI_RAW12 0x2C
214
215#define CSI_DECODE_6BIT 0
216#define CSI_DECODE_8BIT 1
217#define CSI_DECODE_10BIT 2
Sreesudhan Ramakrish Ramkumar8f11b8b2012-01-04 17:09:05 -0800218#define CSI_DECODE_DPCM_10_8_10 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700219
220struct msm_vfe_phy_info {
221 uint32_t sbuf_phy;
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530222 uint32_t planar0_off;
223 uint32_t planar1_off;
224 uint32_t planar2_off;
225 uint32_t p0_phy;
226 uint32_t p1_phy;
227 uint32_t p2_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700228 uint8_t output_id; /* VFE31_OUTPUT_MODE_PT/S/V */
229 uint32_t frame_id;
230};
231
232struct msm_vfe_stats_msg {
Lakshmi Narayana Kalavala4ab97a92011-07-26 15:30:14 -0700233 uint8_t awb_ymin;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700234 uint32_t aec_buff;
235 uint32_t awb_buff;
236 uint32_t af_buff;
237 uint32_t ihist_buff;
238 uint32_t rs_buff;
239 uint32_t cs_buff;
240 uint32_t skin_buff;
241 uint32_t status_bits;
242 uint32_t frame_id;
243};
244
245struct video_crop_t{
246 uint32_t in1_w;
247 uint32_t out1_w;
248 uint32_t in1_h;
249 uint32_t out1_h;
250 uint32_t in2_w;
251 uint32_t out2_w;
252 uint32_t in2_h;
253 uint32_t out2_h;
254 uint8_t update_flag;
255};
256
257struct msm_vpe_buf_info {
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530258 uint32_t p0_phy;
259 uint32_t p1_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700260 struct timespec ts;
261 uint32_t frame_id;
262 struct video_crop_t vpe_crop;
263};
264
265struct msm_vfe_resp {
266 enum vfe_resp_msg type;
267 struct msm_cam_evt_msg evt_msg;
268 struct msm_vfe_phy_info phy;
269 struct msm_vfe_stats_msg stats_msg;
270 struct msm_vpe_buf_info vpe_bf;
271 void *extdata;
272 int32_t extlen;
273};
274
275struct msm_vpe_resp {
276 enum vpe_resp_msg type;
277 struct msm_cam_evt_msg evt_msg;
278 struct msm_vpe_phy_info phy;
279 void *extdata;
280 int32_t extlen;
281};
282
283struct msm_vpe_callback {
284 void (*vpe_resp)(struct msm_vpe_resp *,
285 enum msm_queue, void *syncdata,
286 void *time_stamp, gfp_t gfp);
287 void* (*vpe_alloc)(int, void *syncdata, gfp_t gfp);
288 void (*vpe_free)(void *ptr);
289};
290
291struct msm_vfe_callback {
292 void (*vfe_resp)(struct msm_vfe_resp *,
293 enum msm_queue, void *syncdata,
294 gfp_t gfp);
295 void* (*vfe_alloc)(int, void *syncdata, gfp_t gfp);
296 void (*vfe_free)(void *ptr);
297};
298
299struct msm_camvfe_fn {
300 int (*vfe_init)(struct msm_vfe_callback *,
301 struct platform_device *);
302 int (*vfe_enable)(struct camera_enable_cmd *);
303 int (*vfe_config)(struct msm_vfe_cfg_cmd *, void *);
304 int (*vfe_disable)(struct camera_enable_cmd *,
305 struct platform_device *dev);
306 void (*vfe_release)(struct platform_device *);
307 void (*vfe_stop)(void);
308};
309
310struct msm_camvfe_params {
311 struct msm_vfe_cfg_cmd *vfe_cfg;
312 void *data;
313};
314
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700315struct msm_mctl_pp_params {
316 struct msm_mctl_pp_cmd *cmd;
317 void *data;
318};
319
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700320struct msm_camvpe_fn {
321 int (*vpe_reg)(struct msm_vpe_callback *);
322 int (*vpe_cfg_update) (void *);
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530323 void (*send_frame_to_vpe) (uint32_t planar0_off, uint32_t planar1_off,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700324 struct timespec *ts, int output_id);
325 int (*vpe_config)(struct msm_vpe_cfg_cmd *, void *);
326 void (*vpe_cfg_offset)(int frame_pack, uint32_t pyaddr,
327 uint32_t pcbcraddr, struct timespec *ts, int output_id,
328 struct msm_st_half st_half, int frameid);
329 int *dis;
330};
331
332struct msm_sensor_ctrl {
333 int (*s_init)(const struct msm_camera_sensor_info *);
334 int (*s_release)(void);
335 int (*s_config)(void __user *);
336 enum msm_camera_type s_camera_type;
337 uint32_t s_mount_angle;
338 enum msm_st_frame_packing s_video_packing;
339 enum msm_st_frame_packing s_snap_packing;
340};
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700341
342struct msm_actuator_ctrl {
343 int (*a_init_table)(void);
Rajakumar Govindaramdf6af9c2011-12-01 21:26:20 -0800344 int (*a_power_up)(void *);
345 int (*a_power_down)(void *);
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700346 int (*a_create_subdevice)(void *, void *);
347 int (*a_config)(void __user *);
348};
349
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700350struct msm_strobe_flash_ctrl {
351 int (*strobe_flash_init)
352 (struct msm_camera_sensor_strobe_flash_data *);
353 int (*strobe_flash_release)
354 (struct msm_camera_sensor_strobe_flash_data *, int32_t);
355 int (*strobe_flash_charge)(int32_t, int32_t, uint32_t);
356};
357
358/* this structure is used in kernel */
359struct msm_queue_cmd {
360 struct list_head list_config;
361 struct list_head list_control;
362 struct list_head list_frame;
363 struct list_head list_pict;
364 struct list_head list_vpe_frame;
365 enum msm_queue type;
366 void *command;
367 atomic_t on_heap;
368 struct timespec ts;
369 uint32_t error_code;
370};
371
372struct msm_device_queue {
373 struct list_head list;
374 spinlock_t lock;
375 wait_queue_head_t wait;
376 int max;
377 int len;
378 const char *name;
379};
380
381struct msm_sync {
382 /* These two queues are accessed from a process context only
383 * They contain pmem descriptors for the preview frames and the stats
384 * coming from the camera sensor.
385 */
386 struct hlist_head pmem_frames;
387 struct hlist_head pmem_stats;
388
389 /* The message queue is used by the control thread to send commands
390 * to the config thread, and also by the DSP to send messages to the
391 * config thread. Thus it is the only queue that is accessed from
392 * both interrupt and process context.
393 */
394 struct msm_device_queue event_q;
395
396 /* This queue contains preview frames. It is accessed by the DSP (in
397 * in interrupt context, and by the frame thread.
398 */
399 struct msm_device_queue frame_q;
400 int unblock_poll_frame;
401 int unblock_poll_pic_frame;
402
403 /* This queue contains snapshot frames. It is accessed by the DSP (in
404 * interrupt context, and by the control thread.
405 */
406 struct msm_device_queue pict_q;
407 int get_pic_abort;
408 struct msm_device_queue vpe_q;
409
410 struct msm_camera_sensor_info *sdata;
411 struct msm_camvfe_fn vfefn;
412 struct msm_camvpe_fn vpefn;
413 struct msm_sensor_ctrl sctrl;
414 struct msm_strobe_flash_ctrl sfctrl;
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700415 struct msm_actuator_ctrl actctrl;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700416 struct wake_lock wake_lock;
417 struct platform_device *pdev;
418 int16_t ignore_qcmd_type;
419 uint8_t ignore_qcmd;
420 uint8_t opencnt;
421 void *cropinfo;
422 int croplen;
423 int core_powered_on;
424
425 struct fd_roi_info fdroiinfo;
426
427 atomic_t vpe_enable;
428 uint32_t pp_mask;
429 uint8_t pp_frame_avail;
430 struct msm_queue_cmd *pp_prev;
431 struct msm_queue_cmd *pp_snap;
432 struct msm_queue_cmd *pp_thumb;
433 int video_fd;
434
435 const char *apps_id;
436
437 struct mutex lock;
438 struct list_head list;
439 uint8_t liveshot_enabled;
440 struct msm_cam_v4l2_device *pcam_sync;
441
442 uint8_t stereocam_enabled;
443 struct msm_queue_cmd *pp_stereocam;
444 struct msm_queue_cmd *pp_stereocam2;
445 struct msm_queue_cmd *pp_stereosnap;
446 enum msm_stereo_state stereo_state;
447 int stcam_quality_ind;
448 uint32_t stcam_conv_value;
449
450 spinlock_t pmem_frame_spinlock;
451 spinlock_t pmem_stats_spinlock;
452 spinlock_t abort_pict_lock;
453 int snap_count;
454 int thumb_count;
455};
456
457#define MSM_APPS_ID_V4L2 "msm_v4l2"
458#define MSM_APPS_ID_PROP "msm_qct"
459
460struct msm_cam_device {
461 struct msm_sync *sync; /* most-frequently accessed */
462 struct device *device;
463 struct cdev cdev;
464 /* opened is meaningful only for the config and frame nodes,
465 * which may be opened only once.
466 */
467 atomic_t opened;
468};
469
470struct msm_control_device {
471 struct msm_cam_device *pmsm;
472
473 /* Used for MSM_CAM_IOCTL_CTRL_CMD_DONE responses */
474 uint8_t ctrl_data[max_control_command_size];
475 struct msm_ctrl_cmd ctrl;
476 struct msm_queue_cmd qcmd;
477
478 /* This queue used by the config thread to send responses back to the
479 * control thread. It is accessed only from a process context.
480 */
481 struct msm_device_queue ctrl_q;
482};
483
484struct register_address_value_pair {
485 uint16_t register_address;
486 uint16_t register_value;
487};
488
489struct msm_pmem_region {
490 struct hlist_node list;
491 unsigned long paddr;
492 unsigned long len;
493 struct file *file;
494 struct msm_pmem_info info;
Ankit Premrajkac6864b82011-07-15 11:43:41 -0700495 struct msm_mapped_buffer *msm_buffer;
496 int subsys_id;
Ankit Premrajka748a70a2011-11-01 08:22:04 -0700497 struct ion_handle *handle;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700498};
499
500struct axidata {
501 uint32_t bufnum1;
502 uint32_t bufnum2;
503 uint32_t bufnum3;
504 struct msm_pmem_region *region;
505};
506
507#ifdef CONFIG_MSM_CAMERA_FLASH
508int msm_camera_flash_set_led_state(
509 struct msm_camera_sensor_flash_data *fdata,
510 unsigned led_state);
511int msm_strobe_flash_init(struct msm_sync *sync, uint32_t sftype);
512int msm_flash_ctrl(struct msm_camera_sensor_info *sdata,
513 struct flash_ctrl_data *flash_info);
514#else
515static inline int msm_camera_flash_set_led_state(
516 struct msm_camera_sensor_flash_data *fdata,
517 unsigned led_state)
518{
519 return -ENOTSUPP;
520}
521static inline int msm_strobe_flash_init(
522 struct msm_sync *sync, uint32_t sftype)
523{
524 return -ENOTSUPP;
525}
526static inline int msm_flash_ctrl(
527 struct msm_camera_sensor_info *sdata,
528 struct flash_ctrl_data *flash_info)
529{
530 return -ENOTSUPP;
531}
532#endif
533
534
535
536void msm_camvfe_init(void);
537int msm_camvfe_check(void *);
538void msm_camvfe_fn_init(struct msm_camvfe_fn *, void *);
539void msm_camvpe_fn_init(struct msm_camvpe_fn *, void *);
540int msm_camera_drv_start(struct platform_device *dev,
541 int (*sensor_probe)(const struct msm_camera_sensor_info *,
542 struct msm_sensor_ctrl *));
543
544enum msm_camio_clk_type {
545 CAMIO_VFE_MDC_CLK,
546 CAMIO_MDC_CLK,
547 CAMIO_VFE_CLK,
548 CAMIO_VFE_AXI_CLK,
549
550 CAMIO_VFE_CAMIF_CLK,
551 CAMIO_VFE_PBDG_CLK,
552 CAMIO_CAM_MCLK_CLK,
553 CAMIO_CAMIF_PAD_PBDG_CLK,
554
555 CAMIO_CSI0_VFE_CLK,
556 CAMIO_CSI1_VFE_CLK,
557 CAMIO_VFE_PCLK,
558
559 CAMIO_CSI_SRC_CLK,
560 CAMIO_CSI0_CLK,
561 CAMIO_CSI1_CLK,
562 CAMIO_CSI0_PCLK,
563 CAMIO_CSI1_PCLK,
564
565 CAMIO_CSI1_SRC_CLK,
566 CAMIO_CSI_PIX_CLK,
Sreesudhan Ramakrish Ramkumard6e9cb92011-10-12 17:55:18 -0700567 CAMIO_CSI_PIX1_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700568 CAMIO_CSI_RDI_CLK,
Sreesudhan Ramakrish Ramkumard6e9cb92011-10-12 17:55:18 -0700569 CAMIO_CSI_RDI1_CLK,
570 CAMIO_CSI_RDI2_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700571 CAMIO_CSIPHY0_TIMER_CLK,
572 CAMIO_CSIPHY1_TIMER_CLK,
573
574 CAMIO_JPEG_CLK,
575 CAMIO_JPEG_PCLK,
576 CAMIO_VPE_CLK,
577 CAMIO_VPE_PCLK,
578
579 CAMIO_CSI0_PHY_CLK,
580 CAMIO_CSI1_PHY_CLK,
581 CAMIO_CSIPHY_TIMER_SRC_CLK,
Jignesh Mehta95dd6e12011-11-18 17:21:16 -0800582 CAMIO_IMEM_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700583
584 CAMIO_MAX_CLK
585};
586
587enum msm_camio_clk_src_type {
588 MSM_CAMIO_CLK_SRC_INTERNAL,
589 MSM_CAMIO_CLK_SRC_EXTERNAL,
590 MSM_CAMIO_CLK_SRC_MAX
591};
592
593enum msm_s_test_mode {
594 S_TEST_OFF,
595 S_TEST_1,
596 S_TEST_2,
597 S_TEST_3
598};
599
600enum msm_s_resolution {
601 S_QTR_SIZE,
602 S_FULL_SIZE,
603 S_INVALID_SIZE
604};
605
606enum msm_s_reg_update {
607 /* Sensor egisters that need to be updated during initialization */
608 S_REG_INIT,
609 /* Sensor egisters that needs periodic I2C writes */
610 S_UPDATE_PERIODIC,
611 /* All the sensor Registers will be updated */
612 S_UPDATE_ALL,
613 /* Not valid update */
614 S_UPDATE_INVALID
615};
616
617enum msm_s_setting {
618 S_RES_PREVIEW,
619 S_RES_CAPTURE
620};
621
622enum msm_bus_perf_setting {
623 S_INIT,
624 S_PREVIEW,
625 S_VIDEO,
626 S_CAPTURE,
627 S_ZSL,
628 S_STEREO_VIDEO,
629 S_STEREO_CAPTURE,
630 S_DEFAULT,
631 S_EXIT
632};
633
Kevin Chan85af4552011-10-25 15:07:58 -0700634struct msm_cam_clk_info {
635 const char *clk_name;
636 long clk_rate;
637};
638
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700639int msm_camio_enable(struct platform_device *dev);
640int msm_camio_jpeg_clk_enable(void);
641int msm_camio_jpeg_clk_disable(void);
642int msm_camio_vpe_clk_enable(uint32_t);
643int msm_camio_vpe_clk_disable(void);
644
Kevin Chanbb8ef862012-02-14 13:03:04 -0800645void msm_camio_mode_config(enum msm_camera_i2c_mux_mode mode);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700646int msm_camio_clk_enable(enum msm_camio_clk_type clk);
647int msm_camio_clk_disable(enum msm_camio_clk_type clk);
648int msm_camio_clk_config(uint32_t freq);
649void msm_camio_clk_rate_set(int rate);
Shuzhen Wange49436a2011-09-28 16:07:27 -0700650int msm_camio_vfe_clk_rate_set(int rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700651void msm_camio_clk_rate_set_2(struct clk *clk, int rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700652void msm_camio_clk_axi_rate_set(int rate);
653void msm_disable_io_gpio_clk(struct platform_device *);
654
655void msm_camio_camif_pad_reg_reset(void);
656void msm_camio_camif_pad_reg_reset_2(void);
657
658void msm_camio_vfe_blk_reset(void);
659
Nishant Pandit24153d82011-08-27 16:05:13 +0530660int32_t msm_camio_3d_enable(const struct msm_camera_sensor_info *sinfo);
661void msm_camio_3d_disable(void);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700662void msm_camio_clk_sel(enum msm_camio_clk_src_type);
663void msm_camio_disable(struct platform_device *);
664int msm_camio_probe_on(struct platform_device *);
665int msm_camio_probe_off(struct platform_device *);
666int msm_camio_sensor_clk_off(struct platform_device *);
667int msm_camio_sensor_clk_on(struct platform_device *);
668int msm_camio_csi_config(struct msm_camera_csi_params *csi_params);
669int msm_camio_csiphy_config(struct msm_camera_csiphy_params *csiphy_params);
670int msm_camio_csid_config(struct msm_camera_csid_params *csid_params);
671void msm_io_read_interrupt(void);
672int add_axi_qos(void);
673int update_axi_qos(uint32_t freq);
674void release_axi_qos(void);
675void msm_io_w(u32 data, void __iomem *addr);
676void msm_io_w_mb(u32 data, void __iomem *addr);
677u32 msm_io_r(void __iomem *addr);
678u32 msm_io_r_mb(void __iomem *addr);
679void msm_io_dump(void __iomem *addr, int size);
680void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len);
681void msm_camio_set_perf_lvl(enum msm_bus_perf_setting);
Kevin Chan09f4e662011-12-16 08:17:02 -0800682void msm_camio_bus_scale_cfg(
683 struct msm_bus_scale_pdata *, enum msm_bus_perf_setting);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700684
Shuzhen Wanga3c1a122011-08-04 15:33:27 -0700685void *msm_isp_sync_alloc(int size, gfp_t gfp);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700686
687void msm_isp_sync_free(void *ptr);
Kevin Chan85af4552011-10-25 15:07:58 -0700688
689int msm_cam_clk_enable(struct device *dev, struct msm_cam_clk_info *clk_info,
690 struct clk **clk_ptr, int num_clk, int enable);
Jeyaprakash Soundrapandian2474e8f2012-01-03 15:59:57 -0800691int msm_cam_core_reset(void);
Kevin Chaneb6b6072012-01-17 11:54:54 -0800692
693int msm_camera_config_vreg(struct device *dev, struct camera_vreg_t *cam_vreg,
694 int num_vreg, struct regulator **reg_ptr, int config);
695int msm_camera_enable_vreg(struct device *dev, struct camera_vreg_t *cam_vreg,
696 int num_vreg, struct regulator **reg_ptr, int enable);
697
698int msm_camera_config_gpio_table
699 (struct msm_camera_sensor_info *sinfo, int gpio_en);
700int msm_camera_request_gpio_table
701 (struct msm_camera_sensor_info *sinfo, int gpio_en);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700702#endif