Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |
| 19 | |
| 20 | #include "arm64_lir.h" |
| 21 | #include "dex/compiler_internals.h" |
Andreas Gampe | 53c913b | 2014-08-12 23:19:23 -0700 | [diff] [blame] | 22 | #include "dex/quick/mir_to_lir.h" |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 23 | |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 24 | #include <map> |
| 25 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 26 | namespace art { |
| 27 | |
Andreas Gampe | 4b537a8 | 2014-06-30 22:24:53 -0700 | [diff] [blame] | 28 | class Arm64Mir2Lir FINAL : public Mir2Lir { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 29 | protected: |
| 30 | // TODO: consolidate 64-bit target support. |
| 31 | class InToRegStorageMapper { |
| 32 | public: |
Zheng Xu | 949cd97 | 2014-06-23 18:33:08 +0800 | [diff] [blame] | 33 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 34 | virtual ~InToRegStorageMapper() {} |
| 35 | }; |
| 36 | |
| 37 | class InToRegStorageArm64Mapper : public InToRegStorageMapper { |
| 38 | public: |
| 39 | InToRegStorageArm64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} |
| 40 | virtual ~InToRegStorageArm64Mapper() {} |
Zheng Xu | 949cd97 | 2014-06-23 18:33:08 +0800 | [diff] [blame] | 41 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 42 | private: |
| 43 | int cur_core_reg_; |
| 44 | int cur_fp_reg_; |
| 45 | }; |
| 46 | |
| 47 | class InToRegStorageMapping { |
| 48 | public: |
| 49 | InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), |
| 50 | initialized_(false) {} |
| 51 | void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); |
| 52 | int GetMaxMappedIn() { return max_mapped_in_; } |
| 53 | bool IsThereStackMapped() { return is_there_stack_mapped_; } |
| 54 | RegStorage Get(int in_position); |
| 55 | bool IsInitialized() { return initialized_; } |
| 56 | private: |
| 57 | std::map<int, RegStorage> mapping_; |
| 58 | int max_mapped_in_; |
| 59 | bool is_there_stack_mapped_; |
| 60 | bool initialized_; |
| 61 | }; |
| 62 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 63 | public: |
| 64 | Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 65 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 66 | // Required for target - codegen helpers. |
| 67 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
| 68 | RegLocation rl_dest, int lit) OVERRIDE; |
| 69 | bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, |
| 70 | RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
| 71 | bool HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div, |
| 72 | RegLocation rl_src, RegLocation rl_dest, int64_t lit); |
| 73 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
| 74 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
| 75 | RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; |
| 76 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
| 77 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
| 78 | LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
| 79 | VolatileKind is_volatile) OVERRIDE; |
| 80 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
| 81 | OpSize size) OVERRIDE; |
| 82 | LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) |
| 83 | OVERRIDE; |
| 84 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE; |
| 85 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value) OVERRIDE; |
| 86 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, |
| 87 | VolatileKind is_volatile) OVERRIDE; |
| 88 | LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile) |
| 89 | OVERRIDE; |
| 90 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
| 91 | OpSize size) OVERRIDE; |
| 92 | LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) OVERRIDE; |
| 93 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; |
| 94 | LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
| 95 | int offset, int check_value, LIR* target, LIR** compare) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 96 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 97 | // Required for target - register utilities. |
| 98 | RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; |
| 99 | RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { |
| 100 | if (wide_kind == kWide || wide_kind == kRef) { |
Matteo Franchin | ed7a0f2 | 2014-06-10 19:23:45 +0100 | [diff] [blame] | 101 | return As64BitReg(TargetReg(symbolic_reg)); |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 102 | } else { |
| 103 | return Check32BitReg(TargetReg(symbolic_reg)); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 104 | } |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 105 | } |
| 106 | RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { |
| 107 | return As64BitReg(TargetReg(symbolic_reg)); |
| 108 | } |
| 109 | RegStorage GetArgMappingToPhysicalReg(int arg_num) OVERRIDE; |
| 110 | RegLocation GetReturnAlt() OVERRIDE; |
| 111 | RegLocation GetReturnWideAlt() OVERRIDE; |
| 112 | RegLocation LocCReturn() OVERRIDE; |
| 113 | RegLocation LocCReturnRef() OVERRIDE; |
| 114 | RegLocation LocCReturnDouble() OVERRIDE; |
| 115 | RegLocation LocCReturnFloat() OVERRIDE; |
| 116 | RegLocation LocCReturnWide() OVERRIDE; |
| 117 | ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; |
| 118 | void AdjustSpillMask() OVERRIDE; |
| 119 | void ClobberCallerSave() OVERRIDE; |
| 120 | void FreeCallTemps() OVERRIDE; |
| 121 | void LockCallTemps() OVERRIDE; |
| 122 | void CompilerInitializeRegAlloc() OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 123 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 124 | // Required for target - miscellaneous. |
| 125 | void AssembleLIR() OVERRIDE; |
| 126 | void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; |
| 127 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 128 | ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; |
| 129 | const char* GetTargetInstFmt(int opcode) OVERRIDE; |
| 130 | const char* GetTargetInstName(int opcode) OVERRIDE; |
| 131 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE; |
| 132 | ResourceMask GetPCUseDefEncoding() const OVERRIDE; |
| 133 | uint64_t GetTargetInstFlags(int opcode) OVERRIDE; |
| 134 | size_t GetInsnSize(LIR* lir) OVERRIDE; |
| 135 | bool IsUnconditionalBranch(LIR* lir) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 136 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 137 | // Get the register class for load/store of a field. |
| 138 | RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 139 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 140 | // Required for target - Dalvik-level generators. |
| 141 | void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 142 | RegLocation lr_shift) OVERRIDE; |
| 143 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 144 | RegLocation rl_src2, int flags) OVERRIDE; |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 145 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
| 146 | RegLocation rl_dest, int scale) OVERRIDE; |
| 147 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
| 148 | RegLocation rl_src, int scale, bool card_mark) OVERRIDE; |
| 149 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 150 | RegLocation rl_shift, int flags) OVERRIDE; |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 151 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 152 | RegLocation rl_src2) OVERRIDE; |
| 153 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 154 | RegLocation rl_src2) OVERRIDE; |
| 155 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 156 | RegLocation rl_src2) OVERRIDE; |
| 157 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 158 | bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE; |
| 159 | bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; |
| 160 | bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; |
| 161 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE; |
| 162 | bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE; |
| 163 | bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE; |
| 164 | bool GenInlinedSqrt(CallInfo* info) OVERRIDE; |
| 165 | bool GenInlinedCeil(CallInfo* info) OVERRIDE; |
| 166 | bool GenInlinedFloor(CallInfo* info) OVERRIDE; |
| 167 | bool GenInlinedRint(CallInfo* info) OVERRIDE; |
| 168 | bool GenInlinedRound(CallInfo* info, bool is_double) OVERRIDE; |
| 169 | bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE; |
| 170 | bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE; |
Martyn Capewell | 9a8a506 | 2014-08-07 11:31:48 +0100 | [diff] [blame] | 171 | bool GenInlinedAbsInt(CallInfo* info) OVERRIDE; |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 172 | bool GenInlinedAbsLong(CallInfo* info) OVERRIDE; |
Zheng Xu | 947717a | 2014-08-07 14:05:23 +0800 | [diff] [blame] | 173 | bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 174 | void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 175 | void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 176 | RegLocation rl_src2, int flags) OVERRIDE; |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 177 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div) |
| 178 | OVERRIDE; |
| 179 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) |
| 180 | OVERRIDE; |
| 181 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) OVERRIDE; |
| 182 | void GenDivZeroCheckWide(RegStorage reg) OVERRIDE; |
| 183 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; |
| 184 | void GenExitSequence() OVERRIDE; |
| 185 | void GenSpecialExitSequence() OVERRIDE; |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 186 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; |
| 187 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; |
| 188 | void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; |
| 189 | void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 190 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
| 191 | int dest_reg_class) OVERRIDE; |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 192 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 193 | bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE; |
| 194 | void GenMonitorEnter(int opt_flags, RegLocation rl_src) OVERRIDE; |
| 195 | void GenMonitorExit(int opt_flags, RegLocation rl_src) OVERRIDE; |
| 196 | void GenMoveException(RegLocation rl_dest) OVERRIDE; |
| 197 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 198 | int first_bit, int second_bit) OVERRIDE; |
| 199 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 200 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
Andreas Gampe | 48971b3 | 2014-08-06 10:09:01 -0700 | [diff] [blame] | 201 | void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
| 202 | void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 203 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 204 | // Required for target - single operation generators. |
| 205 | LIR* OpUnconditionalBranch(LIR* target) OVERRIDE; |
| 206 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE; |
| 207 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE; |
| 208 | LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE; |
| 209 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE; |
| 210 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 211 | LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE; |
| 212 | void OpEndIT(LIR* it) OVERRIDE; |
| 213 | LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; |
| 214 | LIR* OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE; |
| 215 | LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE; |
| 216 | void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 217 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 218 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE; |
| 219 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE; |
| 220 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE; |
| 221 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; |
| 222 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 223 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE; |
| 224 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE; |
| 225 | LIR* OpTestSuspend(LIR* target) OVERRIDE; |
| 226 | LIR* OpVldm(RegStorage r_base, int count) OVERRIDE; |
| 227 | LIR* OpVstm(RegStorage r_base, int count) OVERRIDE; |
| 228 | void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE; |
Andreas Gampe | f29ecd6 | 2014-07-29 00:35:00 -0700 | [diff] [blame] | 229 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 230 | bool InexpensiveConstantInt(int32_t value) OVERRIDE; |
Matteo Franchin | c763e35 | 2014-07-04 12:53:27 +0100 | [diff] [blame] | 231 | bool InexpensiveConstantInt(int32_t value, Instruction::Code opcode) OVERRIDE; |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 232 | bool InexpensiveConstantFloat(int32_t value) OVERRIDE; |
| 233 | bool InexpensiveConstantLong(int64_t value) OVERRIDE; |
| 234 | bool InexpensiveConstantDouble(int64_t value) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 235 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 236 | void FlushIns(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 237 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 238 | int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 239 | NextCallInsn next_call_insn, |
| 240 | const MethodReference& target_method, |
| 241 | uint32_t vtable_idx, |
| 242 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 243 | bool skip_this) OVERRIDE; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 244 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 245 | int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, |
| 246 | NextCallInsn next_call_insn, |
| 247 | const MethodReference& target_method, |
| 248 | uint32_t vtable_idx, |
| 249 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
| 250 | bool skip_this) OVERRIDE; |
Serguei Katkov | 59a42af | 2014-07-05 00:55:46 +0700 | [diff] [blame] | 251 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 252 | bool WideGPRsAreAliases() OVERRIDE { |
| 253 | return true; // 64b architecture. |
| 254 | } |
| 255 | bool WideFPRsAreAliases() OVERRIDE { |
| 256 | return true; // 64b architecture. |
| 257 | } |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 258 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 259 | size_t GetInstructionOffset(LIR* lir) OVERRIDE; |
| 260 | |
Vladimir Marko | 7c2ad5a | 2014-09-24 12:42:55 +0100 | [diff] [blame] | 261 | NextCallInsn GetNextSDCallInsn() OVERRIDE; |
| 262 | |
| 263 | /* |
| 264 | * @brief Generate a relative call to the method that will be patched at link time. |
| 265 | * @param target_method The MethodReference of the method to be invoked. |
| 266 | * @param type How the method will be invoked. |
| 267 | * @returns Call instruction |
| 268 | */ |
| 269 | LIR* CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); |
| 270 | |
| 271 | /* |
| 272 | * @brief Generate the actual call insn based on the method info. |
| 273 | * @param method_info the lowering info for the method call. |
| 274 | * @returns Call instruction |
| 275 | */ |
| 276 | virtual LIR* GenCallInsn(const MirMethodLoweringInfo& method_info) OVERRIDE; |
| 277 | |
| 278 | /* |
| 279 | * @brief Handle ARM specific literals. |
| 280 | */ |
| 281 | void InstallLiteralPools() OVERRIDE; |
| 282 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 283 | LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; |
| 284 | |
| 285 | private: |
| 286 | /** |
| 287 | * @brief Given register xNN (dNN), returns register wNN (sNN). |
| 288 | * @param reg #RegStorage containing a Solo64 input register (e.g. @c x1 or @c d2). |
| 289 | * @return A Solo32 with the same register number as the @p reg (e.g. @c w1 or @c s2). |
| 290 | * @see As64BitReg |
| 291 | */ |
| 292 | RegStorage As32BitReg(RegStorage reg) { |
| 293 | DCHECK(!reg.IsPair()); |
| 294 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { |
| 295 | if (kFailOnSizeError) { |
| 296 | LOG(FATAL) << "Expected 64b register"; |
| 297 | } else { |
| 298 | LOG(WARNING) << "Expected 64b register"; |
| 299 | return reg; |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 300 | } |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 301 | } |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 302 | RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, |
| 303 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 304 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) |
| 305 | ->GetReg().GetReg(), |
| 306 | ret_val.GetReg()); |
| 307 | return ret_val; |
| 308 | } |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 309 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 310 | RegStorage Check32BitReg(RegStorage reg) { |
| 311 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { |
| 312 | if (kFailOnSizeError) { |
| 313 | LOG(FATAL) << "Checked for 32b register"; |
| 314 | } else { |
| 315 | LOG(WARNING) << "Checked for 32b register"; |
| 316 | return As32BitReg(reg); |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 317 | } |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 318 | } |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 319 | return reg; |
| 320 | } |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 321 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 322 | /** |
| 323 | * @brief Given register wNN (sNN), returns register xNN (dNN). |
| 324 | * @param reg #RegStorage containing a Solo32 input register (e.g. @c w1 or @c s2). |
| 325 | * @return A Solo64 with the same register number as the @p reg (e.g. @c x1 or @c d2). |
| 326 | * @see As32BitReg |
| 327 | */ |
| 328 | RegStorage As64BitReg(RegStorage reg) { |
| 329 | DCHECK(!reg.IsPair()); |
| 330 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { |
| 331 | if (kFailOnSizeError) { |
| 332 | LOG(FATAL) << "Expected 32b register"; |
| 333 | } else { |
| 334 | LOG(WARNING) << "Expected 32b register"; |
| 335 | return reg; |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 336 | } |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 337 | } |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 338 | RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, |
| 339 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 340 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) |
| 341 | ->GetReg().GetReg(), |
| 342 | ret_val.GetReg()); |
| 343 | return ret_val; |
| 344 | } |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 345 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 346 | RegStorage Check64BitReg(RegStorage reg) { |
| 347 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { |
| 348 | if (kFailOnSizeError) { |
| 349 | LOG(FATAL) << "Checked for 64b register"; |
| 350 | } else { |
| 351 | LOG(WARNING) << "Checked for 64b register"; |
| 352 | return As64BitReg(reg); |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 353 | } |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 354 | } |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 355 | return reg; |
| 356 | } |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 357 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 358 | int32_t EncodeImmSingle(uint32_t bits); |
| 359 | int32_t EncodeImmDouble(uint64_t bits); |
| 360 | LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value); |
| 361 | LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value); |
| 362 | void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); |
| 363 | void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); |
| 364 | void AssignDataOffsets(); |
| 365 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 366 | bool is_div, int flags) OVERRIDE; |
| 367 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) OVERRIDE; |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 368 | size_t GetLoadStoreSize(LIR* lir); |
| 369 | |
| 370 | bool SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
| 371 | RegLocation rl_dest, int64_t lit); |
| 372 | |
| 373 | uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); |
| 374 | int AssignInsnOffsets(); |
| 375 | void AssignOffsets(); |
| 376 | uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); |
| 377 | |
| 378 | // Spill core and FP registers. Returns the SP difference: either spill size, or whole |
| 379 | // frame size. |
| 380 | int SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size); |
| 381 | |
| 382 | // Unspill core and FP registers. |
| 383 | void UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size); |
| 384 | |
| 385 | void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| 386 | |
| 387 | LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value); |
| 388 | LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value); |
| 389 | |
| 390 | LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); |
| 391 | LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, |
| 392 | int shift); |
| 393 | int EncodeShift(int code, int amount); |
| 394 | |
| 395 | LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, |
| 396 | A64RegExtEncodings ext, uint8_t amount); |
| 397 | LIR* OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, |
| 398 | A64RegExtEncodings ext, uint8_t amount); |
| 399 | int EncodeExtend(int extend_type, int amount); |
| 400 | bool IsExtendEncoding(int encoded_value); |
| 401 | |
| 402 | LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); |
| 403 | LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); |
| 404 | |
| 405 | int EncodeLogicalImmediate(bool is_wide, uint64_t value); |
| 406 | uint64_t DecodeLogicalImmediate(bool is_wide, int value); |
| 407 | ArmConditionCode ArmConditionEncoding(ConditionCode code); |
| 408 | |
| 409 | // Helper used in the two GenSelect variants. |
| 410 | void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest, |
| 411 | int result_reg_class); |
| 412 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 413 | void GenNotLong(RegLocation rl_dest, RegLocation rl_src); |
| 414 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 415 | void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 416 | RegLocation rl_src2, bool is_div, int flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 417 | |
Serban Constantinescu | 2eba1fa | 2014-07-31 19:07:17 +0100 | [diff] [blame] | 418 | InToRegStorageMapping in_to_reg_storage_mapping_; |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 419 | static const A64EncodingMap EncodingMap[kA64Last]; |
Vladimir Marko | 7c2ad5a | 2014-09-24 12:42:55 +0100 | [diff] [blame] | 420 | |
| 421 | ArenaVector<LIR*> call_method_insns_; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 422 | }; |
| 423 | |
| 424 | } // namespace art |
| 425 | |
| 426 | #endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |