Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "dex/compiler_internals.h" |
Andreas Gampe | 53c913b | 2014-08-12 23:19:23 -0700 | [diff] [blame] | 21 | #include "dex/quick/mir_to_lir.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 22 | #include "x86_lir.h" |
| 23 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 24 | #include <map> |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 25 | #include <vector> |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 26 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | namespace art { |
| 28 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 29 | class X86Mir2Lir : public Mir2Lir { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 30 | protected: |
| 31 | class InToRegStorageMapper { |
| 32 | public: |
Serguei Katkov | 407a9d2 | 2014-07-05 03:09:32 +0700 | [diff] [blame] | 33 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 34 | virtual ~InToRegStorageMapper() {} |
| 35 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 36 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 37 | class InToRegStorageX86_64Mapper : public InToRegStorageMapper { |
| 38 | public: |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 39 | explicit InToRegStorageX86_64Mapper(Mir2Lir* ml) : ml_(ml), cur_core_reg_(0), cur_fp_reg_(0) {} |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 40 | virtual ~InToRegStorageX86_64Mapper() {} |
Serguei Katkov | 407a9d2 | 2014-07-05 03:09:32 +0700 | [diff] [blame] | 41 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 42 | protected: |
| 43 | Mir2Lir* ml_; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 44 | private: |
| 45 | int cur_core_reg_; |
| 46 | int cur_fp_reg_; |
| 47 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 48 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 49 | class InToRegStorageMapping { |
| 50 | public: |
| 51 | InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), |
| 52 | initialized_(false) {} |
| 53 | void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); |
| 54 | int GetMaxMappedIn() { return max_mapped_in_; } |
| 55 | bool IsThereStackMapped() { return is_there_stack_mapped_; } |
| 56 | RegStorage Get(int in_position); |
| 57 | bool IsInitialized() { return initialized_; } |
| 58 | private: |
| 59 | std::map<int, RegStorage> mapping_; |
| 60 | int max_mapped_in_; |
| 61 | bool is_there_stack_mapped_; |
| 62 | bool initialized_; |
| 63 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 64 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 65 | class ExplicitTempRegisterLock { |
| 66 | public: |
| 67 | ExplicitTempRegisterLock(X86Mir2Lir* mir_to_lir, int n_regs, ...); |
| 68 | ~ExplicitTempRegisterLock(); |
| 69 | protected: |
| 70 | std::vector<RegStorage> temp_regs_; |
| 71 | X86Mir2Lir* const mir_to_lir_; |
| 72 | }; |
| 73 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 74 | public: |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 75 | X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 76 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 77 | // Required for target - codegen helpers. |
| 78 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 79 | RegLocation rl_dest, int lit) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 80 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
| 81 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 82 | RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 83 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 84 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 85 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 86 | OpSize size) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 87 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 88 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 89 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 90 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 91 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
| 92 | OpSize size) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 93 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; |
| 94 | void GenImplicitNullCheck(RegStorage reg, int opt_flags) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 95 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 96 | // Required for target - register utilities. |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 97 | RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 98 | RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { |
| 99 | if (wide_kind == kWide) { |
| 100 | if (cu_->target64) { |
| 101 | return As64BitReg(TargetReg32(symbolic_reg)); |
| 102 | } else { |
| 103 | // x86: construct a pair. |
| 104 | DCHECK((kArg0 <= symbolic_reg && symbolic_reg < kArg3) || |
| 105 | (kFArg0 <= symbolic_reg && symbolic_reg < kFArg3) || |
| 106 | (kRet0 == symbolic_reg)); |
| 107 | return RegStorage::MakeRegPair(TargetReg32(symbolic_reg), |
| 108 | TargetReg32(static_cast<SpecialTargetRegister>(symbolic_reg + 1))); |
| 109 | } |
| 110 | } else if (wide_kind == kRef && cu_->target64) { |
| 111 | return As64BitReg(TargetReg32(symbolic_reg)); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 112 | } else { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 113 | return TargetReg32(symbolic_reg); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 114 | } |
| 115 | } |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 116 | RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 117 | return TargetReg(symbolic_reg, cu_->target64 ? kWide : kNotWide); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 118 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 119 | |
| 120 | RegStorage GetArgMappingToPhysicalReg(int arg_num) OVERRIDE; |
| 121 | |
| 122 | RegLocation GetReturnAlt() OVERRIDE; |
| 123 | RegLocation GetReturnWideAlt() OVERRIDE; |
| 124 | RegLocation LocCReturn() OVERRIDE; |
| 125 | RegLocation LocCReturnRef() OVERRIDE; |
| 126 | RegLocation LocCReturnDouble() OVERRIDE; |
| 127 | RegLocation LocCReturnFloat() OVERRIDE; |
| 128 | RegLocation LocCReturnWide() OVERRIDE; |
| 129 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 130 | ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 131 | void AdjustSpillMask() OVERRIDE; |
| 132 | void ClobberCallerSave() OVERRIDE; |
| 133 | void FreeCallTemps() OVERRIDE; |
| 134 | void LockCallTemps() OVERRIDE; |
| 135 | |
| 136 | void CompilerInitializeRegAlloc() OVERRIDE; |
| 137 | int VectorRegisterSize() OVERRIDE; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 138 | int NumReservableVectorRegisters(bool long_or_fp) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 139 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 140 | // Required for target - miscellaneous. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 141 | void AssembleLIR() OVERRIDE; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 142 | void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; |
| 143 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 144 | ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 145 | const char* GetTargetInstFmt(int opcode) OVERRIDE; |
| 146 | const char* GetTargetInstName(int opcode) OVERRIDE; |
| 147 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 148 | ResourceMask GetPCUseDefEncoding() const OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 149 | uint64_t GetTargetInstFlags(int opcode) OVERRIDE; |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 150 | size_t GetInsnSize(LIR* lir) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 151 | bool IsUnconditionalBranch(LIR* lir) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 152 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 153 | // Get the register class for load/store of a field. |
| 154 | RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 155 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 156 | // Required for target - Dalvik-level generators. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 157 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 158 | RegLocation rl_dest, int scale) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 159 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 160 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) OVERRIDE; |
| 161 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 162 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 163 | RegLocation rl_src2) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 164 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 165 | RegLocation rl_src2) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 166 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 167 | RegLocation rl_src2) OVERRIDE; |
| 168 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 169 | |
| 170 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE; |
| 171 | bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE; |
| 172 | bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE; |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 173 | bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 174 | bool GenInlinedSqrt(CallInfo* info) OVERRIDE; |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 175 | bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; |
| 176 | bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 177 | bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE; |
| 178 | bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE; |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 179 | bool GenInlinedCharAt(CallInfo* info) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 180 | |
| 181 | // Long instructions. |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 182 | void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 183 | RegLocation rl_src2, int flags) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 184 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 185 | RegLocation rl_src2, int flags) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 186 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 187 | RegLocation rl_src1, RegLocation rl_shift, int flags) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 188 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) OVERRIDE; |
| 189 | void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 190 | void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 191 | RegLocation rl_src1, RegLocation rl_shift) OVERRIDE; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 192 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 193 | /* |
| 194 | * @brief Generate a two address long operation with a constant value |
| 195 | * @param rl_dest location of result |
| 196 | * @param rl_src constant source operand |
| 197 | * @param op Opcode to be generated |
| 198 | * @return success or not |
| 199 | */ |
| 200 | bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 201 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 202 | /* |
| 203 | * @brief Generate a three address long operation with a constant value |
| 204 | * @param rl_dest location of result |
| 205 | * @param rl_src1 source operand |
| 206 | * @param rl_src2 constant source operand |
| 207 | * @param op Opcode to be generated |
| 208 | * @return success or not |
| 209 | */ |
| 210 | bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 211 | Instruction::Code op); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 212 | /** |
| 213 | * @brief Generate a long arithmetic operation. |
| 214 | * @param rl_dest The destination. |
| 215 | * @param rl_src1 First operand. |
| 216 | * @param rl_src2 Second operand. |
| 217 | * @param op The DEX opcode for the operation. |
| 218 | * @param is_commutative The sources can be swapped if needed. |
| 219 | */ |
| 220 | virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 221 | Instruction::Code op, bool is_commutative); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 222 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 223 | /** |
| 224 | * @brief Generate a two operand long arithmetic operation. |
| 225 | * @param rl_dest The destination. |
| 226 | * @param rl_src Second operand. |
| 227 | * @param op The DEX opcode for the operation. |
| 228 | */ |
| 229 | void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 230 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 231 | /** |
| 232 | * @brief Generate a long operation. |
| 233 | * @param rl_dest The destination. Must be in a register |
| 234 | * @param rl_src The other operand. May be in a register or in memory. |
| 235 | * @param op The DEX opcode for the operation. |
| 236 | */ |
| 237 | virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 238 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 239 | |
| 240 | // TODO: collapse reg_lo, reg_hi |
| 241 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div) |
| 242 | OVERRIDE; |
| 243 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) OVERRIDE; |
| 244 | void GenDivZeroCheckWide(RegStorage reg) OVERRIDE; |
| 245 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; |
| 246 | void GenExitSequence() OVERRIDE; |
| 247 | void GenSpecialExitSequence() OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 248 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; |
| 249 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; |
| 250 | void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; |
| 251 | void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 252 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
| 253 | int dest_reg_class) OVERRIDE; |
| 254 | bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE; |
| 255 | void GenMoveException(RegLocation rl_dest) OVERRIDE; |
| 256 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 257 | int first_bit, int second_bit) OVERRIDE; |
| 258 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 259 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
Andreas Gampe | 48971b3 | 2014-08-06 10:09:01 -0700 | [diff] [blame] | 260 | void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
| 261 | void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 262 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 263 | /** |
| 264 | * @brief Implement instanceof a final class with x86 specific code. |
| 265 | * @param use_declaring_class 'true' if we can use the class itself. |
| 266 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 267 | * @param rl_dest Result to be set to 0 or 1. |
| 268 | * @param rl_src Object to be tested. |
| 269 | */ |
| 270 | void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 271 | RegLocation rl_src) OVERRIDE; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 272 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 273 | // Single operation generators. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 274 | LIR* OpUnconditionalBranch(LIR* target) OVERRIDE; |
| 275 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE; |
| 276 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE; |
| 277 | LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE; |
| 278 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE; |
| 279 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 280 | LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE; |
| 281 | void OpEndIT(LIR* it) OVERRIDE; |
| 282 | LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; |
| 283 | LIR* OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE; |
| 284 | LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE; |
| 285 | void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 286 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 287 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE; |
| 288 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE; |
| 289 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE; |
| 290 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; |
| 291 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 292 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE; |
| 293 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE; |
| 294 | LIR* OpTestSuspend(LIR* target) OVERRIDE; |
| 295 | LIR* OpVldm(RegStorage r_base, int count) OVERRIDE; |
| 296 | LIR* OpVstm(RegStorage r_base, int count) OVERRIDE; |
| 297 | void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE; |
| 298 | bool GenInlinedCurrentThread(CallInfo* info) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 299 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 300 | bool InexpensiveConstantInt(int32_t value) OVERRIDE; |
| 301 | bool InexpensiveConstantFloat(int32_t value) OVERRIDE; |
| 302 | bool InexpensiveConstantLong(int64_t value) OVERRIDE; |
| 303 | bool InexpensiveConstantDouble(int64_t value) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 304 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 305 | /* |
| 306 | * @brief Should try to optimize for two address instructions? |
| 307 | * @return true if we try to avoid generating three operand instructions. |
| 308 | */ |
| 309 | virtual bool GenerateTwoOperandInstructions() const { return true; } |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 310 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 311 | /* |
| 312 | * @brief x86 specific codegen for int operations. |
| 313 | * @param opcode Operation to perform. |
| 314 | * @param rl_dest Destination for the result. |
| 315 | * @param rl_lhs Left hand operand. |
| 316 | * @param rl_rhs Right hand operand. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 317 | * @param flags The instruction optimization flags. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 318 | */ |
| 319 | void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 320 | RegLocation rl_rhs, int flags) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 321 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 322 | /* |
| 323 | * @brief Load the Method* of a dex method into the register. |
| 324 | * @param target_method The MethodReference of the method to be invoked. |
| 325 | * @param type How the method will be invoked. |
| 326 | * @param register that will contain the code address. |
| 327 | * @note register will be passed to TargetReg to get physical register. |
| 328 | */ |
| 329 | void LoadMethodAddress(const MethodReference& target_method, InvokeType type, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 330 | SpecialTargetRegister symbolic_reg) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 331 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 332 | /* |
| 333 | * @brief Load the Class* of a Dex Class type into the register. |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 334 | * @param dex DexFile that contains the class type. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 335 | * @param type How the method will be invoked. |
| 336 | * @param register that will contain the code address. |
| 337 | * @note register will be passed to TargetReg to get physical register. |
| 338 | */ |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 339 | void LoadClassType(const DexFile& dex_file, uint32_t type_idx, |
| 340 | SpecialTargetRegister symbolic_reg) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 341 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 342 | void FlushIns(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 343 | |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 344 | NextCallInsn GetNextSDCallInsn() OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 345 | int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 346 | NextCallInsn next_call_insn, |
| 347 | const MethodReference& target_method, |
| 348 | uint32_t vtable_idx, |
| 349 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 350 | bool skip_this) OVERRIDE; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 351 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 352 | int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, |
| 353 | NextCallInsn next_call_insn, |
| 354 | const MethodReference& target_method, |
| 355 | uint32_t vtable_idx, |
| 356 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 357 | bool skip_this) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 358 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 359 | /* |
| 360 | * @brief Generate a relative call to the method that will be patched at link time. |
| 361 | * @param target_method The MethodReference of the method to be invoked. |
| 362 | * @param type How the method will be invoked. |
| 363 | * @returns Call instruction |
| 364 | */ |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 365 | LIR* CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); |
| 366 | |
| 367 | /* |
| 368 | * @brief Generate the actual call insn based on the method info. |
| 369 | * @param method_info the lowering info for the method call. |
| 370 | * @returns Call instruction |
| 371 | */ |
| 372 | LIR* GenCallInsn(const MirMethodLoweringInfo& method_info) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 373 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 374 | /* |
| 375 | * @brief Handle x86 specific literals |
| 376 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 377 | void InstallLiteralPools() OVERRIDE; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 378 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 379 | /* |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 380 | * @brief Generate the debug_frame FDE information. |
| 381 | * @returns pointer to vector containing CFE information |
| 382 | */ |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 383 | std::vector<uint8_t>* ReturnFrameDescriptionEntry() OVERRIDE; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 384 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 385 | LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; |
| 386 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 387 | protected: |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 388 | RegStorage TargetReg32(SpecialTargetRegister reg); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 389 | // Casting of RegStorage |
| 390 | RegStorage As32BitReg(RegStorage reg) { |
| 391 | DCHECK(!reg.IsPair()); |
| 392 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { |
| 393 | if (kFailOnSizeError) { |
| 394 | LOG(FATAL) << "Expected 64b register " << reg.GetReg(); |
| 395 | } else { |
| 396 | LOG(WARNING) << "Expected 64b register " << reg.GetReg(); |
| 397 | return reg; |
| 398 | } |
| 399 | } |
| 400 | RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, |
| 401 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 402 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) |
| 403 | ->GetReg().GetReg(), |
| 404 | ret_val.GetReg()); |
| 405 | return ret_val; |
| 406 | } |
| 407 | |
| 408 | RegStorage As64BitReg(RegStorage reg) { |
| 409 | DCHECK(!reg.IsPair()); |
| 410 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { |
| 411 | if (kFailOnSizeError) { |
| 412 | LOG(FATAL) << "Expected 32b register " << reg.GetReg(); |
| 413 | } else { |
| 414 | LOG(WARNING) << "Expected 32b register " << reg.GetReg(); |
| 415 | return reg; |
| 416 | } |
| 417 | } |
| 418 | RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, |
| 419 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 420 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) |
| 421 | ->GetReg().GetReg(), |
| 422 | ret_val.GetReg()); |
| 423 | return ret_val; |
| 424 | } |
| 425 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 426 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
| 427 | RegStorage r_dest, OpSize size); |
| 428 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 429 | RegStorage r_src, OpSize size, int opt_flags = 0); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 430 | |
| 431 | RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); |
| 432 | |
| 433 | int AssignInsnOffsets(); |
| 434 | void AssignOffsets(); |
| 435 | AssemblerStatus AssembleInstructions(CodeOffset start_addr); |
| 436 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 437 | size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 438 | int32_t raw_base, int32_t displacement); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 439 | void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); |
| 440 | void EmitPrefix(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 441 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 442 | void EmitOpcode(const X86EncodingMap* entry); |
| 443 | void EmitPrefixAndOpcode(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 444 | int32_t reg_r, int32_t reg_x, int32_t reg_b); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 445 | void EmitDisp(uint8_t base, int32_t disp); |
| 446 | void EmitModrmThread(uint8_t reg_or_opcode); |
| 447 | void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); |
| 448 | void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, |
| 449 | int32_t disp); |
| 450 | void EmitImm(const X86EncodingMap* entry, int64_t imm); |
| 451 | void EmitNullary(const X86EncodingMap* entry); |
| 452 | void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); |
| 453 | void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); |
| 454 | void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 455 | void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 456 | int32_t disp); |
| 457 | void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); |
| 458 | void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); |
| 459 | void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 460 | int32_t raw_index, int scale, int32_t disp); |
| 461 | void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 462 | int32_t disp, int32_t raw_reg); |
| 463 | void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 464 | void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 465 | int32_t raw_disp, int32_t imm); |
| 466 | void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); |
| 467 | void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); |
| 468 | void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); |
| 469 | void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 470 | int32_t imm); |
| 471 | void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, |
| 472 | int32_t imm); |
| 473 | void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 474 | void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); |
| 475 | void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); |
| 476 | void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 477 | void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); |
| 478 | void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 479 | void EmitShiftRegRegCl(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, |
| 480 | int32_t raw_cl); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 481 | void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 482 | void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); |
| 483 | void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); |
| 484 | void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); |
| 485 | void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 486 | int32_t cc); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 487 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 488 | void EmitJmp(const X86EncodingMap* entry, int32_t rel); |
| 489 | void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); |
| 490 | void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 491 | void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); |
| 492 | void EmitCallThread(const X86EncodingMap* entry, int32_t disp); |
| 493 | void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, |
| 494 | int32_t raw_index, int scale, int32_t table_or_disp); |
| 495 | void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); |
| 496 | void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); |
| 497 | void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 498 | int64_t val, ConditionCode ccode); |
| 499 | void GenConstWide(RegLocation rl_dest, int64_t value); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 500 | void GenMultiplyVectorSignedByte(RegStorage rs_dest_src1, RegStorage rs_src2); |
| 501 | void GenMultiplyVectorLong(RegStorage rs_dest_src1, RegStorage rs_src2); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 502 | void GenShiftByteVector(BasicBlock *bb, MIR *mir); |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 503 | void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, |
| 504 | uint32_t m4); |
| 505 | void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, |
| 506 | uint32_t m3, uint32_t m4); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 507 | void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); |
Mark Mendell | 0a1174e | 2014-09-11 14:51:02 -0400 | [diff] [blame] | 508 | virtual void LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, OpSize opsize, |
| 509 | int op_mov); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 510 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 511 | static bool ProvidesFullMemoryBarrier(X86OpCode opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 512 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 513 | /* |
| 514 | * @brief Ensure that a temporary register is byte addressable. |
| 515 | * @returns a temporary guarenteed to be byte addressable. |
| 516 | */ |
| 517 | virtual RegStorage AllocateByteRegister(); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 518 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 519 | /* |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 520 | * @brief Use a wide temporary as a 128-bit register |
| 521 | * @returns a 128-bit temporary register. |
| 522 | */ |
| 523 | virtual RegStorage Get128BitRegister(RegStorage reg); |
| 524 | |
| 525 | /* |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 526 | * @brief Check if a register is byte addressable. |
| 527 | * @returns true if a register is byte addressable. |
| 528 | */ |
| 529 | bool IsByteRegister(RegStorage reg); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 530 | |
| 531 | void GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, int64_t imm, bool is_div); |
| 532 | |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 533 | bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 534 | |
| 535 | /* |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 536 | * @brief generate inline code for fast case of Strng.indexOf. |
| 537 | * @param info Call parameters |
| 538 | * @param zero_based 'true' if the index into the string is 0. |
| 539 | * @returns 'true' if the call was inlined, 'false' if a regular call needs to be |
| 540 | * generated. |
| 541 | */ |
| 542 | bool GenInlinedIndexOf(CallInfo* info, bool zero_based); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 543 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 544 | /** |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 545 | * @brief Used to reserve a range of vector registers. |
| 546 | * @see kMirOpReserveVectorRegisters |
| 547 | * @param mir The extended MIR for reservation. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 548 | */ |
| 549 | void ReserveVectorRegisters(MIR* mir); |
| 550 | |
| 551 | /** |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 552 | * @brief Used to return a range of vector registers. |
| 553 | * @see kMirOpReturnVectorRegisters |
| 554 | * @param mir The extended MIR for returning vector regs. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 555 | */ |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 556 | void ReturnVectorRegisters(MIR* mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 557 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 558 | /* |
| 559 | * @brief Load 128 bit constant into vector register. |
| 560 | * @param bb The basic block in which the MIR is from. |
| 561 | * @param mir The MIR whose opcode is kMirConstVector |
| 562 | * @note vA is the TypeSize for the register. |
| 563 | * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. |
| 564 | */ |
| 565 | void GenConst128(BasicBlock* bb, MIR* mir); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 566 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 567 | /* |
| 568 | * @brief MIR to move a vectorized register to another. |
| 569 | * @param bb The basic block in which the MIR is from. |
| 570 | * @param mir The MIR whose opcode is kMirConstVector. |
| 571 | * @note vA: TypeSize |
| 572 | * @note vB: destination |
| 573 | * @note vC: source |
| 574 | */ |
| 575 | void GenMoveVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 576 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 577 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 578 | * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know |
| 579 | * the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 580 | * @param bb The basic block in which the MIR is from. |
| 581 | * @param mir The MIR whose opcode is kMirConstVector. |
| 582 | * @note vA: TypeSize |
| 583 | * @note vB: destination and source |
| 584 | * @note vC: source |
| 585 | */ |
| 586 | void GenMultiplyVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 587 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 588 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 589 | * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the |
| 590 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 591 | * @param bb The basic block in which the MIR is from. |
| 592 | * @param mir The MIR whose opcode is kMirConstVector. |
| 593 | * @note vA: TypeSize |
| 594 | * @note vB: destination and source |
| 595 | * @note vC: source |
| 596 | */ |
| 597 | void GenAddVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 598 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 599 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 600 | * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the |
| 601 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 602 | * @param bb The basic block in which the MIR is from. |
| 603 | * @param mir The MIR whose opcode is kMirConstVector. |
| 604 | * @note vA: TypeSize |
| 605 | * @note vB: destination and source |
| 606 | * @note vC: source |
| 607 | */ |
| 608 | void GenSubtractVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 609 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 610 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 611 | * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the |
| 612 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 613 | * @param bb The basic block in which the MIR is from. |
| 614 | * @param mir The MIR whose opcode is kMirConstVector. |
| 615 | * @note vA: TypeSize |
| 616 | * @note vB: destination and source |
| 617 | * @note vC: immediate |
| 618 | */ |
| 619 | void GenShiftLeftVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 620 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 621 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 622 | * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to |
| 623 | * know the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 624 | * @param bb The basic block in which the MIR is from. |
| 625 | * @param mir The MIR whose opcode is kMirConstVector. |
| 626 | * @note vA: TypeSize |
| 627 | * @note vB: destination and source |
| 628 | * @note vC: immediate |
| 629 | */ |
| 630 | void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 631 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 632 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 633 | * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA |
| 634 | * to know the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 635 | * @param bb The basic block in which the MIR is from.. |
| 636 | * @param mir The MIR whose opcode is kMirConstVector. |
| 637 | * @note vA: TypeSize |
| 638 | * @note vB: destination and source |
| 639 | * @note vC: immediate |
| 640 | */ |
| 641 | void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 642 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 643 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 644 | * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the |
| 645 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 646 | * @note vA: TypeSize |
| 647 | * @note vB: destination and source |
| 648 | * @note vC: source |
| 649 | */ |
| 650 | void GenAndVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 651 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 652 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 653 | * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the |
| 654 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 655 | * @param bb The basic block in which the MIR is from. |
| 656 | * @param mir The MIR whose opcode is kMirConstVector. |
| 657 | * @note vA: TypeSize |
| 658 | * @note vB: destination and source |
| 659 | * @note vC: source |
| 660 | */ |
| 661 | void GenOrVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 662 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 663 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 664 | * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the |
| 665 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 666 | * @param bb The basic block in which the MIR is from. |
| 667 | * @param mir The MIR whose opcode is kMirConstVector. |
| 668 | * @note vA: TypeSize |
| 669 | * @note vB: destination and source |
| 670 | * @note vC: source |
| 671 | */ |
| 672 | void GenXorVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 673 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 674 | /* |
| 675 | * @brief Reduce a 128-bit packed element into a single VR by taking lower bits |
| 676 | * @param bb The basic block in which the MIR is from. |
| 677 | * @param mir The MIR whose opcode is kMirConstVector. |
| 678 | * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. |
| 679 | * @note vA: TypeSize |
| 680 | * @note vB: destination and source VR (not vector register) |
| 681 | * @note vC: source (vector register) |
| 682 | */ |
| 683 | void GenAddReduceVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 684 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 685 | /* |
| 686 | * @brief Extract a packed element into a single VR. |
| 687 | * @param bb The basic block in which the MIR is from. |
| 688 | * @param mir The MIR whose opcode is kMirConstVector. |
| 689 | * @note vA: TypeSize |
| 690 | * @note vB: destination VR (not vector register) |
| 691 | * @note vC: source (vector register) |
| 692 | * @note arg[0]: The index to use for extraction from vector register (which packed element). |
| 693 | */ |
| 694 | void GenReduceVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 695 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 696 | /* |
| 697 | * @brief Create a vector value, with all TypeSize values equal to vC |
| 698 | * @param bb The basic block in which the MIR is from. |
| 699 | * @param mir The MIR whose opcode is kMirConstVector. |
| 700 | * @note vA: TypeSize. |
| 701 | * @note vB: destination vector register. |
| 702 | * @note vC: source VR (not vector register). |
| 703 | */ |
| 704 | void GenSetVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 705 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 706 | /** |
| 707 | * @brief Used to generate code for kMirOpPackedArrayGet. |
| 708 | * @param bb The basic block of MIR. |
| 709 | * @param mir The mir whose opcode is kMirOpPackedArrayGet. |
| 710 | */ |
| 711 | void GenPackedArrayGet(BasicBlock *bb, MIR *mir); |
| 712 | |
| 713 | /** |
| 714 | * @brief Used to generate code for kMirOpPackedArrayPut. |
| 715 | * @param bb The basic block of MIR. |
| 716 | * @param mir The mir whose opcode is kMirOpPackedArrayPut. |
| 717 | */ |
| 718 | void GenPackedArrayPut(BasicBlock *bb, MIR *mir); |
| 719 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 720 | /* |
| 721 | * @brief Generate code for a vector opcode. |
| 722 | * @param bb The basic block in which the MIR is from. |
| 723 | * @param mir The MIR whose opcode is a non-standard opcode. |
| 724 | */ |
| 725 | void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 726 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 727 | /* |
| 728 | * @brief Return the correct x86 opcode for the Dex operation |
| 729 | * @param op Dex opcode for the operation |
| 730 | * @param loc Register location of the operand |
| 731 | * @param is_high_op 'true' if this is an operation on the high word |
| 732 | * @param value Immediate value for the operation. Used for byte variants |
| 733 | * @returns the correct x86 opcode to perform the operation |
| 734 | */ |
| 735 | X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 736 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 737 | /* |
| 738 | * @brief Return the correct x86 opcode for the Dex operation |
| 739 | * @param op Dex opcode for the operation |
| 740 | * @param dest location of the destination. May be register or memory. |
| 741 | * @param rhs Location for the rhs of the operation. May be in register or memory. |
| 742 | * @param is_high_op 'true' if this is an operation on the high word |
| 743 | * @returns the correct x86 opcode to perform the operation |
| 744 | * @note at most one location may refer to memory |
| 745 | */ |
| 746 | X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 747 | bool is_high_op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 748 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 749 | /* |
| 750 | * @brief Is this operation a no-op for this opcode and value |
| 751 | * @param op Dex opcode for the operation |
| 752 | * @param value Immediate value for the operation. |
| 753 | * @returns 'true' if the operation will have no effect |
| 754 | */ |
| 755 | bool IsNoOp(Instruction::Code op, int32_t value); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 756 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 757 | /** |
| 758 | * @brief Calculate magic number and shift for a given divisor |
| 759 | * @param divisor divisor number for calculation |
| 760 | * @param magic hold calculated magic number |
| 761 | * @param shift hold calculated shift |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 762 | * @param is_long 'true' if divisor is jlong, 'false' for jint. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 763 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 764 | void CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 765 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 766 | /* |
| 767 | * @brief Generate an integer div or rem operation. |
| 768 | * @param rl_dest Destination Location. |
| 769 | * @param rl_src1 Numerator Location. |
| 770 | * @param rl_src2 Divisor Location. |
| 771 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 772 | * @param flags The instruction optimization flags. It can include information |
| 773 | * if exception check can be elided. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 774 | */ |
| 775 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 776 | bool is_div, int flags); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 777 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 778 | /* |
| 779 | * @brief Generate an integer div or rem operation by a literal. |
| 780 | * @param rl_dest Destination Location. |
| 781 | * @param rl_src Numerator Location. |
| 782 | * @param lit Divisor. |
| 783 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 784 | */ |
| 785 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 786 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 787 | /* |
| 788 | * Generate code to implement long shift operations. |
| 789 | * @param opcode The DEX opcode to specify the shift type. |
| 790 | * @param rl_dest The destination. |
| 791 | * @param rl_src The value to be shifted. |
| 792 | * @param shift_amount How much to shift. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 793 | * @param flags The instruction optimization flags. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 794 | * @returns the RegLocation of the result. |
| 795 | */ |
| 796 | RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 797 | RegLocation rl_src, int shift_amount, int flags); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 798 | /* |
| 799 | * Generate an imul of a register by a constant or a better sequence. |
| 800 | * @param dest Destination Register. |
| 801 | * @param src Source Register. |
| 802 | * @param val Constant multiplier. |
| 803 | */ |
| 804 | void GenImulRegImm(RegStorage dest, RegStorage src, int val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 805 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 806 | /* |
| 807 | * Generate an imul of a memory location by a constant or a better sequence. |
| 808 | * @param dest Destination Register. |
| 809 | * @param sreg Symbolic register. |
| 810 | * @param displacement Displacement on stack of Symbolic Register. |
| 811 | * @param val Constant multiplier. |
| 812 | */ |
| 813 | void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 814 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 815 | /* |
| 816 | * @brief Compare memory to immediate, and branch if condition true. |
| 817 | * @param cond The condition code that when true will branch to the target. |
| 818 | * @param temp_reg A temporary register that can be used if compare memory is not |
| 819 | * supported by the architecture. |
| 820 | * @param base_reg The register holding the base address. |
| 821 | * @param offset The offset from the base. |
| 822 | * @param check_value The immediate to compare to. |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 823 | * @param target branch target (or nullptr) |
| 824 | * @param compare output for getting LIR for comparison (or nullptr) |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 825 | */ |
| 826 | LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 827 | int offset, int check_value, LIR* target, LIR** compare); |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 828 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 829 | void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); |
| 830 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 831 | /* |
| 832 | * Can this operation be using core registers without temporaries? |
| 833 | * @param rl_lhs Left hand operand. |
| 834 | * @param rl_rhs Right hand operand. |
| 835 | * @returns 'true' if the operation can proceed without needing temporary regs. |
| 836 | */ |
| 837 | bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 838 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 839 | /** |
| 840 | * @brief Generates inline code for conversion of long to FP by using x87/ |
| 841 | * @param rl_dest The destination of the FP. |
| 842 | * @param rl_src The source of the long. |
| 843 | * @param is_double 'true' if dealing with double, 'false' for float. |
| 844 | */ |
| 845 | virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 846 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 847 | void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); |
| 848 | void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); |
| 849 | |
| 850 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 851 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); |
| 852 | LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); |
| 853 | LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); |
| 854 | LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset); |
| 855 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); |
| 856 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); |
| 857 | void OpTlsCmp(ThreadOffset<4> offset, int val); |
| 858 | void OpTlsCmp(ThreadOffset<8> offset, int val); |
| 859 | |
| 860 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 861 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 862 | // Try to do a long multiplication where rl_src2 is a constant. This simplified setup might fail, |
| 863 | // in which case false will be returned. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 864 | bool GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val, int flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 865 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 866 | RegLocation rl_src2, int flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 867 | void GenNotLong(RegLocation rl_dest, RegLocation rl_src); |
| 868 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 869 | void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 870 | RegLocation rl_src2, bool is_div, int flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 871 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 872 | void SpillCoreRegs(); |
| 873 | void UnSpillCoreRegs(); |
| 874 | void UnSpillFPRegs(); |
| 875 | void SpillFPRegs(); |
| 876 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 877 | /* |
| 878 | * @brief Perform MIR analysis before compiling method. |
| 879 | * @note Invokes Mir2LiR::Materialize after analysis. |
| 880 | */ |
| 881 | void Materialize(); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 882 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 883 | /* |
| 884 | * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register |
| 885 | * without regard to data type. In practice, this can result in UpdateLoc returning a |
| 886 | * location record for a Dalvik float value in a core register, and vis-versa. For targets |
| 887 | * which can inexpensively move data between core and float registers, this can often be a win. |
| 888 | * However, for x86 this is generally not a win. These variants of UpdateLoc() |
| 889 | * take a register class argument - and will return an in-register location record only if |
| 890 | * the value is live in a temp register of the correct class. Additionally, if the value is in |
| 891 | * a temp register of the wrong register class, it will be clobbered. |
| 892 | */ |
| 893 | RegLocation UpdateLocTyped(RegLocation loc, int reg_class); |
| 894 | RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 895 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 896 | /* |
| 897 | * @brief Analyze MIR before generating code, to prepare for the code generation. |
| 898 | */ |
| 899 | void AnalyzeMIR(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 900 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 901 | /* |
| 902 | * @brief Analyze one basic block. |
| 903 | * @param bb Basic block to analyze. |
| 904 | */ |
| 905 | void AnalyzeBB(BasicBlock * bb); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 906 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 907 | /* |
| 908 | * @brief Analyze one extended MIR instruction |
| 909 | * @param opcode MIR instruction opcode. |
| 910 | * @param bb Basic block containing instruction. |
| 911 | * @param mir Extended instruction to analyze. |
| 912 | */ |
| 913 | void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 914 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 915 | /* |
| 916 | * @brief Analyze one MIR instruction |
| 917 | * @param opcode MIR instruction opcode. |
| 918 | * @param bb Basic block containing instruction. |
| 919 | * @param mir Instruction to analyze. |
| 920 | */ |
| 921 | virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 922 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 923 | /* |
| 924 | * @brief Analyze one MIR float/double instruction |
| 925 | * @param opcode MIR instruction opcode. |
| 926 | * @param bb Basic block containing instruction. |
| 927 | * @param mir Instruction to analyze. |
| 928 | */ |
Mark Mendell | 0a1174e | 2014-09-11 14:51:02 -0400 | [diff] [blame] | 929 | virtual void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 930 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 931 | /* |
| 932 | * @brief Analyze one use of a double operand. |
| 933 | * @param rl_use Double RegLocation for the operand. |
| 934 | */ |
| 935 | void AnalyzeDoubleUse(RegLocation rl_use); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 936 | |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 937 | /* |
| 938 | * @brief Analyze one invoke-static MIR instruction |
| 939 | * @param opcode MIR instruction opcode. |
| 940 | * @param bb Basic block containing instruction. |
| 941 | * @param mir Instruction to analyze. |
| 942 | */ |
| 943 | void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); |
| 944 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 945 | // Information derived from analysis of MIR |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 946 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 947 | // The compiler temporary for the code address of the method. |
| 948 | CompilerTemp *base_of_code_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 949 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 950 | // Have we decided to compute a ptr to code and store in temporary VR? |
| 951 | bool store_method_addr_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 952 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 953 | // Have we used the stored method address? |
| 954 | bool store_method_addr_used_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 955 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 956 | // Instructions to remove if we didn't use the stored method address. |
| 957 | LIR* setup_method_address_[2]; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 958 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 959 | // Instructions needing patching with Method* values. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 960 | ArenaVector<LIR*> method_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 961 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 962 | // Instructions needing patching with Class Type* values. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 963 | ArenaVector<LIR*> class_type_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 964 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 965 | // Instructions needing patching with PC relative code addresses. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 966 | ArenaVector<LIR*> call_method_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 967 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 968 | // Prologue decrement of stack pointer. |
| 969 | LIR* stack_decrement_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 970 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 971 | // Epilogue increment of stack pointer. |
| 972 | LIR* stack_increment_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 973 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 974 | // The list of const vector literals. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 975 | LIR* const_vectors_; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 976 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 977 | /* |
| 978 | * @brief Search for a matching vector literal |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 979 | * @param constants An array of size 4 which contains all of 32-bit constants. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 980 | * @returns pointer to matching LIR constant, or nullptr if not found. |
| 981 | */ |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 982 | LIR* ScanVectorLiteral(int32_t* constants); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 983 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 984 | /* |
| 985 | * @brief Add a constant vector literal |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 986 | * @param constants An array of size 4 which contains all of 32-bit constants. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 987 | */ |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 988 | LIR* AddVectorLiteral(int32_t* constants); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 989 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 990 | InToRegStorageMapping in_to_reg_storage_mapping_; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 991 | |
Serguei Katkov | 59a42af | 2014-07-05 00:55:46 +0700 | [diff] [blame] | 992 | bool WideGPRsAreAliases() OVERRIDE { |
| 993 | return cu_->target64; // On 64b, we have 64b GPRs. |
| 994 | } |
| 995 | bool WideFPRsAreAliases() OVERRIDE { |
| 996 | return true; // xmm registers have 64b views even on x86. |
| 997 | } |
| 998 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 999 | /* |
| 1000 | * @brief Dump a RegLocation using printf |
| 1001 | * @param loc Register location to dump |
| 1002 | */ |
| 1003 | static void DumpRegLocation(RegLocation loc); |
| 1004 | |
| 1005 | static const X86EncodingMap EncodingMap[kX86Last]; |
| 1006 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1007 | private: |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 1008 | void SwapBits(RegStorage result_reg, int shift, int32_t value); |
| 1009 | void SwapBits64(RegStorage result_reg, int shift, int64_t value); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1010 | }; |
| 1011 | |
| 1012 | } // namespace art |
| 1013 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 1014 | #endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |