Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_x86.h" |
| 18 | #include "dex/quick/mir_to_lir-inl.h" |
| 19 | #include "x86_lir.h" |
| 20 | |
| 21 | namespace art { |
| 22 | |
| 23 | #define MAX_ASSEMBLER_RETRIES 50 |
| 24 | |
| 25 | const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 26 | { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4, false }, "data", "0x!0d" }, |
| 27 | { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0, false }, "int 3", "" }, |
| 28 | { kX86Nop, kNop, NO_OPERAND, { 0, 0, 0x90, 0, 0, 0, 0, 0, false }, "nop", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | |
| 30 | #define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ |
| 31 | rm8_r8, rm32_r32, \ |
| 32 | r8_rm8, r32_rm32, \ |
| 33 | ax8_i8, ax32_i32, \ |
| 34 | rm8_i8, rm8_i8_modrm, \ |
| 35 | rm32_i32, rm32_i32_modrm, \ |
| 36 | rm32_i8, rm32_i8_modrm) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 37 | { kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8MR", "[!0r+!1d],!2r" }, \ |
Mark Mendell | 2bc4770 | 2014-07-31 14:36:54 -0400 | [diff] [blame] | 38 | { kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 39 | { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \ |
| 40 | { kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RR", "!0r,!1r" }, \ |
| 41 | { kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RM", "!0r,[!1r+!2d]" }, \ |
| 42 | { kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 43 | { kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RT", "!0r,fs:[!1d]" }, \ |
| 44 | { kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1, true }, #opname "8RI", "!0r,!1d" }, \ |
Mark Mendell | fd0c237 | 2014-07-31 13:20:21 -0400 | [diff] [blame] | 45 | { kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8MI", "[!0r+!1d],!2d" }, \ |
| 46 | { kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 47 | { kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8TI", "fs:[!0d],!1d" }, \ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 48 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 49 | { kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16MR", "[!0r+!1d],!2r" }, \ |
| 50 | { kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 51 | { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \ |
| 52 | { kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RR", "!0r,!1r" }, \ |
| 53 | { kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RM", "!0r,[!1r+!2d]" }, \ |
| 54 | { kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 55 | { kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RT", "!0r,fs:[!1d]" }, \ |
| 56 | { kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2, false }, #opname "16RI", "!0r,!1d" }, \ |
| 57 | { kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ |
| 58 | { kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 59 | { kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16TI", "fs:[!0d],!1d" }, \ |
| 60 | { kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16RI8", "!0r,!1d" }, \ |
| 61 | { kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16MI8", "[!0r+!1d],!2d" }, \ |
| 62 | { kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 63 | { kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16TI8", "fs:[!0d],!1d" }, \ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 64 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 65 | { kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32MR", "[!0r+!1d],!2r" }, \ |
| 66 | { kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 67 | { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \ |
| 68 | { kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RR", "!0r,!1r" }, \ |
| 69 | { kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RM", "!0r,[!1r+!2d]" }, \ |
| 70 | { kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 71 | { kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RT", "!0r,fs:[!1d]" }, \ |
| 72 | { kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "32RI", "!0r,!1d" }, \ |
| 73 | { kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ |
| 74 | { kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 75 | { kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32TI", "fs:[!0d],!1d" }, \ |
| 76 | { kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32RI8", "!0r,!1d" }, \ |
| 77 | { kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32MI8", "[!0r+!1d],!2d" }, \ |
| 78 | { kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 79 | { kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32TI8", "fs:[!0d],!1d" }, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 80 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 81 | { kX86 ## opname ## 64MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64MR", "[!0r+!1d],!2r" }, \ |
| 82 | { kX86 ## opname ## 64AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 83 | { kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \ |
| 84 | { kX86 ## opname ## 64RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RR", "!0r,!1r" }, \ |
| 85 | { kX86 ## opname ## 64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RM", "!0r,[!1r+!2d]" }, \ |
| 86 | { kX86 ## opname ## 64RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 87 | { kX86 ## opname ## 64RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RT", "!0r,fs:[!1d]" }, \ |
| 88 | { kX86 ## opname ## 64RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "64RI", "!0r,!1d" }, \ |
| 89 | { kX86 ## opname ## 64MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ |
| 90 | { kX86 ## opname ## 64AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 91 | { kX86 ## opname ## 64TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64TI", "fs:[!0d],!1d" }, \ |
| 92 | { kX86 ## opname ## 64RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64RI8", "!0r,!1d" }, \ |
| 93 | { kX86 ## opname ## 64MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64MI8", "[!0r+!1d],!2d" }, \ |
| 94 | { kX86 ## opname ## 64AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 95 | { kX86 ## opname ## 64TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64TI8", "fs:[!0d],!1d" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 96 | |
| 97 | ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 98 | 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, |
| 99 | 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, |
| 100 | 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, |
| 101 | 0x80, 0x0 /* RegMem8/imm8 */, |
| 102 | 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), |
| 103 | ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 104 | 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, |
| 105 | 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, |
| 106 | 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, |
| 107 | 0x80, 0x1 /* RegMem8/imm8 */, |
| 108 | 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), |
| 109 | ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, |
| 110 | 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, |
| 111 | 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, |
| 112 | 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, |
| 113 | 0x80, 0x2 /* RegMem8/imm8 */, |
| 114 | 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), |
| 115 | ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, |
| 116 | 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, |
| 117 | 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, |
| 118 | 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, |
| 119 | 0x80, 0x3 /* RegMem8/imm8 */, |
| 120 | 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), |
| 121 | ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 122 | 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, |
| 123 | 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, |
| 124 | 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, |
| 125 | 0x80, 0x4 /* RegMem8/imm8 */, |
| 126 | 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), |
| 127 | ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 128 | 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, |
| 129 | 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, |
| 130 | 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, |
| 131 | 0x80, 0x5 /* RegMem8/imm8 */, |
| 132 | 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), |
| 133 | ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 134 | 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, |
| 135 | 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, |
| 136 | 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, |
| 137 | 0x80, 0x6 /* RegMem8/imm8 */, |
| 138 | 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), |
| 139 | ENCODING_MAP(Cmp, IS_LOAD, 0, 0, |
| 140 | 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, |
| 141 | 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, |
| 142 | 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, |
| 143 | 0x80, 0x7 /* RegMem8/imm8 */, |
| 144 | 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), |
| 145 | #undef ENCODING_MAP |
| 146 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 147 | { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RRI", "!0r,!1r,!2d" }, |
| 148 | { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, |
| 149 | { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 150 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 151 | { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RRI", "!0r,!1r,!2d" }, |
| 152 | { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, |
| 153 | { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 154 | { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RRI8", "!0r,!1r,!2d" }, |
| 155 | { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, |
| 156 | { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 157 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 158 | { kX86Imul64RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RRI", "!0r,!1r,!2d" }, |
| 159 | { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RMI", "!0r,[!1r+!2d],!3d" }, |
| 160 | { kX86Imul64RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 161 | { kX86Imul64RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RRI8", "!0r,!1r,!2d" }, |
| 162 | { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" }, |
| 163 | { kX86Imul64RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 164 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 165 | { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8MR", "[!0r+!1d],!2r" }, |
| 166 | { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 167 | { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8TR", "fs:[!0d],!1r" }, |
| 168 | { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RR", "!0r,!1r" }, |
| 169 | { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RM", "!0r,[!1r+!2d]" }, |
| 170 | { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 171 | { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RT", "!0r,fs:[!1d]" }, |
| 172 | { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1, true }, "Mov8RI", "!0r,!1d" }, |
Mark Mendell | fd0c237 | 2014-07-31 13:20:21 -0400 | [diff] [blame] | 173 | { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8MI", "[!0r+!1d],!2d" }, |
| 174 | { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 175 | { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8TI", "fs:[!0d],!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 176 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 177 | { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16MR", "[!0r+!1d],!2r" }, |
| 178 | { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 179 | { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0, false }, "Mov16TR", "fs:[!0d],!1r" }, |
| 180 | { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RR", "!0r,!1r" }, |
| 181 | { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RM", "!0r,[!1r+!2d]" }, |
| 182 | { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 183 | { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RT", "!0r,fs:[!1d]" }, |
| 184 | { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2, false }, "Mov16RI", "!0r,!1d" }, |
| 185 | { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16MI", "[!0r+!1d],!2d" }, |
| 186 | { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 187 | { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16TI", "fs:[!0d],!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 188 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 189 | { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32MR", "[!0r+!1d],!2r" }, |
| 190 | { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame^] | 191 | { kX86Movnti32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0F, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Movnti32MR", "[!0r+!1d],!2r" }, |
| 192 | { kX86Movnti32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0F, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Movnti32AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 193 | { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32TR", "fs:[!0d],!1r" }, |
| 194 | { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RR", "!0r,!1r" }, |
| 195 | { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RM", "!0r,[!1r+!2d]" }, |
| 196 | { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 197 | { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RT", "!0r,fs:[!1d]" }, |
| 198 | { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "Mov32RI", "!0r,!1d" }, |
| 199 | { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32MI", "[!0r+!1d],!2d" }, |
| 200 | { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 201 | { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32TI", "fs:[!0d],!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 202 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 203 | { kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RM", "!0r,[!1r+!2d]" }, |
| 204 | { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 205 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 206 | { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64MR", "[!0r+!1d],!2r" }, |
| 207 | { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame^] | 208 | { kX86Movnti64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0F, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Movnti64MR", "[!0r+!1d],!2r" }, |
| 209 | { kX86Movnti64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0F, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Movnti64AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 210 | { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0, false }, "Mov64TR", "fs:[!0d],!1r" }, |
| 211 | { kX86Mov64RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RR", "!0r,!1r" }, |
| 212 | { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" }, |
| 213 | { kX86Mov64RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 214 | { kX86Mov64RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RT", "!0r,fs:[!1d]" }, |
Yixin Shou | 5192cbb | 2014-07-01 13:48:17 -0400 | [diff] [blame] | 215 | { kX86Mov64RI32, kRegImm, IS_BINARY_OP | REG_DEF0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64RI32", "!0r,!1d" }, |
| 216 | { kX86Mov64RI64, kMovRegQuadImm, IS_TERTIARY_OP | REG_DEF0, { REX_W, 0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI64", "!0r,!1q" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 217 | { kX86Mov64MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64MI", "[!0r+!1d],!2d" }, |
| 218 | { kX86Mov64AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 219 | { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64TI", "fs:[!0d],!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 220 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 221 | { kX86Lea64RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RM", "!0r,[!1r+!2d]" }, |
| 222 | { kX86Lea64RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 223 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 224 | { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RR", "!2c !0r,!1r" }, |
| 225 | { kX86Cmov64RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RR", "!2c !0r,!1r" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 226 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 227 | { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" }, |
| 228 | { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" }, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 229 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 230 | #define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 231 | { kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8RI", "!0r,!1d" }, \ |
| 232 | { kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \ |
| 233 | { kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 234 | { kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8RC", "!0r,cl" }, \ |
| 235 | { kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8MC", "[!0r+!1d],cl" }, \ |
| 236 | { kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 237 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 238 | { kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16RI", "!0r,!1d" }, \ |
| 239 | { kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ |
| 240 | { kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 241 | { kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16RC", "!0r,cl" }, \ |
| 242 | { kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16MC", "[!0r+!1d],cl" }, \ |
| 243 | { kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 244 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 245 | { kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32RI", "!0r,!1d" }, \ |
| 246 | { kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ |
| 247 | { kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 248 | { kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32RC", "!0r,cl" }, \ |
| 249 | { kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32MC", "[!0r+!1d],cl" }, \ |
| 250 | { kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 251 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 252 | { kX86 ## opname ## 64RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64RI", "!0r,!1d" }, \ |
| 253 | { kX86 ## opname ## 64MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ |
| 254 | { kX86 ## opname ## 64AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 255 | { kX86 ## opname ## 64RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64RC", "!0r,cl" }, \ |
| 256 | { kX86 ## opname ## 64MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64MC", "[!0r+!1d],cl" }, \ |
| 257 | { kX86 ## opname ## 64AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64AC", "[!0r+!1r<<!2d+!3d],cl" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 258 | |
| 259 | SHIFT_ENCODING_MAP(Rol, 0x0), |
| 260 | SHIFT_ENCODING_MAP(Ror, 0x1), |
| 261 | SHIFT_ENCODING_MAP(Rcl, 0x2), |
| 262 | SHIFT_ENCODING_MAP(Rcr, 0x3), |
| 263 | SHIFT_ENCODING_MAP(Sal, 0x4), |
| 264 | SHIFT_ENCODING_MAP(Shr, 0x5), |
| 265 | SHIFT_ENCODING_MAP(Sar, 0x7), |
| 266 | #undef SHIFT_ENCODING_MAP |
| 267 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 268 | { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0, false }, "Cmc", "" }, |
| 269 | { kX86Shld32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32RRI", "!0r,!1r,!2d" }, |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 270 | { kX86Shld32RRC, kShiftRegRegCl, IS_TERTIARY_OP | REG_DEF0_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0x0F, 0xA5, 0, 0, 0, 0, false }, "Shld32RRC", "!0r,!1r,cl" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 271 | { kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32MRI", "[!0r+!1d],!2r,!3d" }, |
| 272 | { kX86Shrd32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32RRI", "!0r,!1r,!2d" }, |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 273 | { kX86Shrd32RRC, kShiftRegRegCl, IS_TERTIARY_OP | REG_DEF0_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0x0F, 0xAD, 0, 0, 0, 0, false }, "Shrd32RRC", "!0r,!1r,cl" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 274 | { kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32MRI", "[!0r+!1d],!2r,!3d" }, |
| 275 | { kX86Shld64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64RRI", "!0r,!1r,!2d" }, |
| 276 | { kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64MRI", "[!0r+!1d],!2r,!3d" }, |
| 277 | { kX86Shrd64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64RRI", "!0r,!1r,!2d" }, |
| 278 | { kX86Shrd64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64MRI", "[!0r+!1d],!2r,!3d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 279 | |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 280 | { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8RI", "!0r,!1d" }, |
| 281 | { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8MI", "[!0r+!1d],!2d" }, |
| 282 | { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 283 | { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16RI", "!0r,!1d" }, |
| 284 | { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16MI", "[!0r+!1d],!2d" }, |
| 285 | { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 286 | { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32RI", "!0r,!1d" }, |
| 287 | { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32MI", "[!0r+!1d],!2d" }, |
| 288 | { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 289 | { kX86Test64RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64RI", "!0r,!1d" }, |
| 290 | { kX86Test64MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64MI", "[!0r+!1d],!2d" }, |
| 291 | { kX86Test64AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 292 | |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 293 | { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RR", "!0r,!1r" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 294 | { kX86Test64RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test64RR", "!0r,!1r" }, |
Chao-ying Fu | cf81841 | 2014-07-24 12:08:28 -0700 | [diff] [blame] | 295 | { kX86Test32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RM", "!0r,[!1r+!2d]" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 296 | |
| 297 | #define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ |
| 298 | reg, reg_kind, reg_flags, \ |
| 299 | mem, mem_kind, mem_flags, \ |
| 300 | arr, arr_kind, arr_flags, imm, \ |
| 301 | b_flags, hw_flags, w_flags, \ |
| 302 | b_format, hw_format, w_format) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 303 | { kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \ |
| 304 | { kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \ |
| 305 | { kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 306 | { kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \ |
| 307 | { kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \ |
| 308 | { kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 309 | { kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \ |
| 310 | { kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \ |
| 311 | { kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 312 | { kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #reg, w_format "!0r" }, \ |
| 313 | { kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #mem, w_format "[!0r+!1d]" }, \ |
| 314 | { kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 315 | |
| 316 | UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), |
| 317 | UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), |
| 318 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 319 | UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), |
| 320 | UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), |
| 321 | UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), |
| 322 | UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 323 | #undef UNARY_ENCODING_MAP |
| 324 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 325 | { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cdq", "" }, |
| 326 | { kx86Cqo64Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { REX_W, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cqo", "" }, |
| 327 | { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap32R", "!0r" }, |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 328 | { kX86Bswap64R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { REX_W, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap64R", "!0r" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 329 | { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0, false }, "Push32R", "!0r" }, |
| 330 | { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0, false }, "Pop32R", "!0r" }, |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 331 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 332 | #define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 333 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ |
| 334 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 335 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 336 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 337 | // This is a special encoding with r8_form on the second register only |
| 338 | // for Movzx8 and Movsx8. |
| 339 | #define EXT_0F_R8_FORM_ENCODING_MAP(opname, prefix, opcode, reg_def) \ |
| 340 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, true }, #opname "RR", "!0r,!1r" }, \ |
| 341 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 342 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
| 343 | |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 344 | #define EXT_0F_REX_W_ENCODING_MAP(opname, prefix, opcode, reg_def) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 345 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ |
| 346 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 347 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 348 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 349 | #define EXT_0F_ENCODING2_MAP(opname, prefix, opcode, opcode2, reg_def) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 350 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ |
| 351 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 352 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 353 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 354 | EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 355 | { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdMR", "[!0r+!1d],!2r" }, |
| 356 | { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 357 | |
| 358 | EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 359 | { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssMR", "[!0r+!1d],!2r" }, |
| 360 | { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 361 | |
| 362 | EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), |
| 363 | EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 364 | EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2sd, 0xF2, 0x2A, REG_DEF0), |
| 365 | EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2ss, 0xF3, 0x2A, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 366 | EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), |
| 367 | EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 368 | EXT_0F_REX_W_ENCODING_MAP(Cvttsd2sqi, 0xF2, 0x2C, REG_DEF0), |
| 369 | EXT_0F_REX_W_ENCODING_MAP(Cvttss2sqi, 0xF3, 0x2C, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 370 | EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), |
| 371 | EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 372 | EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0), |
| 373 | EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0), |
| 374 | EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0), |
| 375 | EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0), |
Alexei Zavjalov | 1222c96 | 2014-07-16 00:54:13 +0700 | [diff] [blame] | 376 | EXT_0F_ENCODING_MAP(Orpd, 0x66, 0x56, REG_DEF0_USE0), |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 377 | EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0), |
Alexei Zavjalov | 1222c96 | 2014-07-16 00:54:13 +0700 | [diff] [blame] | 378 | EXT_0F_ENCODING_MAP(Andpd, 0x66, 0x54, REG_DEF0_USE0), |
| 379 | EXT_0F_ENCODING_MAP(Andps, 0x00, 0x54, REG_DEF0_USE0), |
| 380 | EXT_0F_ENCODING_MAP(Xorpd, 0x66, 0x57, REG_DEF0_USE0), |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 381 | EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0), |
| 382 | EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0), |
| 383 | EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0), |
| 384 | EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0), |
| 385 | EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 386 | EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), |
| 387 | EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 388 | EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0), |
| 389 | EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0), |
| 390 | EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0), |
| 391 | EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0), |
| 392 | EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0), |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 393 | EXT_0F_ENCODING_MAP(Sqrtsd, 0xF2, 0x51, REG_DEF0_USE0), |
| 394 | EXT_0F_ENCODING2_MAP(Pmulld, 0x66, 0x38, 0x40, REG_DEF0_USE0), |
| 395 | EXT_0F_ENCODING_MAP(Pmullw, 0x66, 0xD5, REG_DEF0_USE0), |
| 396 | EXT_0F_ENCODING_MAP(Mulps, 0x00, 0x59, REG_DEF0_USE0), |
| 397 | EXT_0F_ENCODING_MAP(Mulpd, 0x66, 0x59, REG_DEF0_USE0), |
| 398 | EXT_0F_ENCODING_MAP(Paddb, 0x66, 0xFC, REG_DEF0_USE0), |
| 399 | EXT_0F_ENCODING_MAP(Paddw, 0x66, 0xFD, REG_DEF0_USE0), |
| 400 | EXT_0F_ENCODING_MAP(Paddd, 0x66, 0xFE, REG_DEF0_USE0), |
| 401 | EXT_0F_ENCODING_MAP(Addps, 0x00, 0x58, REG_DEF0_USE0), |
| 402 | EXT_0F_ENCODING_MAP(Addpd, 0xF2, 0x58, REG_DEF0_USE0), |
| 403 | EXT_0F_ENCODING_MAP(Psubb, 0x66, 0xF8, REG_DEF0_USE0), |
| 404 | EXT_0F_ENCODING_MAP(Psubw, 0x66, 0xF9, REG_DEF0_USE0), |
| 405 | EXT_0F_ENCODING_MAP(Psubd, 0x66, 0xFA, REG_DEF0_USE0), |
| 406 | EXT_0F_ENCODING_MAP(Subps, 0x00, 0x5C, REG_DEF0_USE0), |
| 407 | EXT_0F_ENCODING_MAP(Subpd, 0x66, 0x5C, REG_DEF0_USE0), |
| 408 | EXT_0F_ENCODING_MAP(Pand, 0x66, 0xDB, REG_DEF0_USE0), |
| 409 | EXT_0F_ENCODING_MAP(Por, 0x66, 0xEB, REG_DEF0_USE0), |
| 410 | EXT_0F_ENCODING_MAP(Pxor, 0x66, 0xEF, REG_DEF0_USE0), |
| 411 | EXT_0F_ENCODING2_MAP(Phaddw, 0x66, 0x38, 0x01, REG_DEF0_USE0), |
| 412 | EXT_0F_ENCODING2_MAP(Phaddd, 0x66, 0x38, 0x02, REG_DEF0_USE0), |
Olivier Come | fb0fecf | 2014-06-20 11:46:16 +0200 | [diff] [blame] | 413 | EXT_0F_ENCODING_MAP(Haddpd, 0x66, 0x7C, REG_DEF0_USE0), |
| 414 | EXT_0F_ENCODING_MAP(Haddps, 0xF2, 0x7C, REG_DEF0_USE0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 415 | |
Serguei Katkov | 3569063 | 2014-07-16 15:52:59 +0700 | [diff] [blame] | 416 | { kX86PextrbRRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x14, 0, 0, 1, false }, "PextbRRI", "!0r,!1r,!2d" }, |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 417 | { kX86PextrwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC5, 0x00, 0, 0, 1, false }, "PextwRRI", "!0r,!1r,!2d" }, |
Serguei Katkov | 3569063 | 2014-07-16 15:52:59 +0700 | [diff] [blame] | 418 | { kX86PextrdRRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextdRRI", "!0r,!1r,!2d" }, |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 419 | { kX86PextrbMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrbMRI", "[!0r+!1d],!2r,!3d" }, |
| 420 | { kX86PextrwMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrwMRI", "[!0r+!1d],!2r,!3d" }, |
| 421 | { kX86PextrdMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrdMRI", "[!0r+!1d],!2r,!3d" }, |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 422 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 423 | { kX86PshuflwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0xF2, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuflwRRI", "!0r,!1r,!2d" }, |
| 424 | { kX86PshufdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuffRRI", "!0r,!1r,!2d" }, |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 425 | |
Olivier Come | fb0fecf | 2014-06-20 11:46:16 +0200 | [diff] [blame] | 426 | { kX86ShufpsRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x00, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "kX86ShufpsRRI", "!0r,!1r,!2d" }, |
| 427 | { kX86ShufpdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "kX86ShufpdRRI", "!0r,!1r,!2d" }, |
| 428 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 429 | { kX86PsrawRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 4, 0, 1, false }, "PsrawRI", "!0r,!1d" }, |
| 430 | { kX86PsradRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 4, 0, 1, false }, "PsradRI", "!0r,!1d" }, |
| 431 | { kX86PsrlwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 2, 0, 1, false }, "PsrlwRI", "!0r,!1d" }, |
| 432 | { kX86PsrldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 2, 0, 1, false }, "PsrldRI", "!0r,!1d" }, |
| 433 | { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1, false }, "PsrlqRI", "!0r,!1d" }, |
| 434 | { kX86PsllwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 6, 0, 1, false }, "PsllwRI", "!0r,!1d" }, |
| 435 | { kX86PslldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 6, 0, 1, false }, "PslldRI", "!0r,!1d" }, |
| 436 | { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1, false }, "PsllqRI", "!0r,!1d" }, |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 437 | |
Alexei Zavjalov | bd3682e | 2014-06-12 03:08:01 +0700 | [diff] [blame] | 438 | { kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0, false }, "Fild32M", "[!0r,!1d]" }, |
| 439 | { kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0, false }, "Fild64M", "[!0r,!1d]" }, |
| 440 | { kX86Fld32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 0, 0, 0, false }, "Fld32M", "[!0r,!1d]" }, |
| 441 | { kX86Fld64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 0, 0, 0, false }, "Fld64M", "[!0r,!1d]" }, |
| 442 | { kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0, false }, "Fstps32M", "[!0r,!1d]" }, |
| 443 | { kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0, false }, "Fstpd64M", "[!0r,!1d]" }, |
Serguei Katkov | e63d9d4 | 2014-06-25 00:25:35 +0700 | [diff] [blame] | 444 | { kX86Fst32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 2, 0, 0, false }, "Fsts32M", "[!0r,!1d]" }, |
| 445 | { kX86Fst64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 2, 0, 0, false }, "Fstd64M", "[!0r,!1d]" }, |
Alexei Zavjalov | bd3682e | 2014-06-12 03:08:01 +0700 | [diff] [blame] | 446 | { kX86Fprem, kNullary, NO_OPERAND | USE_FP_STACK, { 0xD9, 0, 0xF8, 0, 0, 0, 0, 0, false }, "Fprem64", "" }, |
| 447 | { kX86Fucompp, kNullary, NO_OPERAND | USE_FP_STACK, { 0xDA, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Fucompp", "" }, |
Mark Mendell | 01a50d6 | 2014-07-06 12:24:40 -0400 | [diff] [blame] | 448 | { kX86Fstsw16R, kNullary, NO_OPERAND | REG_DEFA | USE_FP_STACK, { 0x9B, 0xDF, 0xE0, 0, 0, 0, 0, 0, false }, "Fstsw16R", "ax" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 449 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 450 | EXT_0F_ENCODING_MAP(Mova128, 0x66, 0x6F, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 451 | { kX86Mova128MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128MR", "[!0r+!1d],!2r" }, |
| 452 | { kX86Mova128AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 453 | |
| 454 | |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 455 | EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 456 | { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsMR", "[!0r+!1d],!2r" }, |
| 457 | { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 458 | |
| 459 | EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 460 | { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsMR", "[!0r+!1d],!2r" }, |
| 461 | { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 462 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 463 | { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRM", "!0r,[!1r+!2d]" }, |
| 464 | { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 465 | { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsMR", "[!0r+!1d],!2r" }, |
| 466 | { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 467 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 468 | { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRM", "!0r,[!1r+!2d]" }, |
| 469 | { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 470 | { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsMR", "[!0r+!1d],!2r" }, |
| 471 | { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 472 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 473 | EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 474 | EXT_0F_REX_W_ENCODING_MAP(Movqxr, 0x66, 0x6E, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 475 | { kX86MovqrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxRR", "!0r,!1r" }, |
| 476 | { kX86MovqrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxMR", "[!0r+!1d],!2r" }, |
| 477 | { kX86MovqrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 478 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 479 | { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxRR", "!0r,!1r" }, |
| 480 | { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxMR", "[!0r+!1d],!2r" }, |
| 481 | { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 482 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 483 | { kX86MovsxdRR, kRegReg, IS_BINARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRR", "!0r,!1r" }, |
| 484 | { kX86MovsxdRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRM", "!0r,[!1r+!2d]" }, |
| 485 | { kX86MovsxdRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE12, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 486 | |
Mark Mendell | 2bc4770 | 2014-07-31 14:36:54 -0400 | [diff] [blame] | 487 | { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, true }, "Set8R", "!1c !0r" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 488 | { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8M", "!2c [!0r+!1d]" }, |
| 489 | { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 490 | |
| 491 | // TODO: load/store? |
| 492 | // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame^] | 493 | { kX86Lfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 5, 0, 0, false }, "Lfence", "" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 494 | { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0, false }, "Mfence", "" }, |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame^] | 495 | { kX86Sfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 7, 0, 0, false }, "Sfence", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 496 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 497 | EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
| 498 | EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 499 | EXT_0F_ENCODING_MAP(Imul64, REX_W, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 500 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 501 | { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "!0r,!1r" }, |
| 502 | { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1d],!2r" }, |
| 503 | { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 504 | { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, |
| 505 | { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 506 | { kX86LockCmpxchg64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, REX_W, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 507 | { kX86LockCmpxchg64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1d]" }, |
| 508 | { kX86LockCmpxchg64A, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" }, |
| 509 | { kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0, false }, "Xchg", "[!0r+!1d],!2r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 510 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 511 | EXT_0F_R8_FORM_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 512 | EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 513 | EXT_0F_R8_FORM_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 514 | EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), |
Serguei Katkov | 94f3eb0 | 2014-06-24 13:23:17 +0700 | [diff] [blame] | 515 | EXT_0F_ENCODING_MAP(Movzx8q, REX_W, 0xB6, REG_DEF0), |
| 516 | EXT_0F_ENCODING_MAP(Movzx16q, REX_W, 0xB7, REG_DEF0), |
| 517 | EXT_0F_ENCODING_MAP(Movsx8q, REX, 0xBE, REG_DEF0), |
| 518 | EXT_0F_ENCODING_MAP(Movsx16q, REX_W, 0xBF, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 519 | #undef EXT_0F_ENCODING_MAP |
| 520 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 521 | { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0, false }, "Jcc8", "!1c !0t" }, |
| 522 | { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0, false }, "Jcc32", "!1c !0t" }, |
| 523 | { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0, false }, "Jmp8", "!0t" }, |
| 524 | { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Jmp32", "!0t" }, |
| 525 | { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpR", "!0r" }, |
| 526 | { kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0, false }, "Jecxz", "!0t" }, |
| 527 | { kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpT", "fs:[!0d]" }, |
| 528 | { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0, false }, "CallR", "!0r" }, |
| 529 | { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallM", "[!0r+!1d]" }, |
| 530 | { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallA", "[!0r+!1r<<!2d+!3d]" }, |
| 531 | { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallT", "fs:[!0d]" }, |
| 532 | { kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4, false }, "CallI", "!0d" }, |
| 533 | { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Ret", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 534 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 535 | { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0, false }, "StartOfMethod", "!0r" }, |
| 536 | { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, |
Haitao Feng | e70f179 | 2014-08-09 08:31:02 +0800 | [diff] [blame] | 537 | { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "PcRelAdr", "!0r,!1p" }, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 538 | { kX86RepneScasw, kNullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0, false }, "RepNE ScasW", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 539 | }; |
| 540 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 541 | static bool NeedsRex(int32_t raw_reg) { |
| 542 | return RegStorage::RegNum(raw_reg) > 7; |
| 543 | } |
| 544 | |
| 545 | static uint8_t LowRegisterBits(int32_t raw_reg) { |
| 546 | uint8_t low_reg = RegStorage::RegNum(raw_reg) & kRegNumMask32; // 3 bits |
| 547 | DCHECK_LT(low_reg, 8); |
| 548 | return low_reg; |
| 549 | } |
| 550 | |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 551 | static bool HasModrm(const X86EncodingMap* entry) { |
| 552 | switch (entry->kind) { |
| 553 | case kNullary: return false; |
| 554 | case kRegOpcode: return false; |
| 555 | default: return true; |
| 556 | } |
| 557 | } |
| 558 | |
| 559 | static bool HasSib(const X86EncodingMap* entry) { |
| 560 | switch (entry->kind) { |
| 561 | case kArray: return true; |
| 562 | case kArrayReg: return true; |
| 563 | case kRegArray: return true; |
| 564 | case kArrayImm: return true; |
| 565 | case kRegArrayImm: return true; |
| 566 | case kShiftArrayImm: return true; |
| 567 | case kShiftArrayCl: return true; |
| 568 | case kArrayCond: return true; |
| 569 | case kCall: |
| 570 | switch (entry->opcode) { |
| 571 | case kX86CallA: return true; |
| 572 | default: return false; |
| 573 | } |
| 574 | case kPcRel: return true; |
| 575 | switch (entry->opcode) { |
| 576 | case kX86PcRelLoadRA: return true; |
| 577 | default: return false; |
| 578 | } |
| 579 | default: return false; |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | static bool ModrmIsRegReg(const X86EncodingMap* entry) { |
| 584 | switch (entry->kind) { |
| 585 | // There is no modrm for this kind of instruction, therefore the reg doesn't form part of the |
| 586 | // modrm: |
| 587 | case kNullary: return true; |
| 588 | case kRegOpcode: return true; |
| 589 | case kMovRegImm: return true; |
| 590 | // Regular modrm value of 3 cases, when there is one register the other register holds an |
| 591 | // opcode so the base register is special. |
| 592 | case kReg: return true; |
| 593 | case kRegReg: return true; |
| 594 | case kRegRegStore: return true; |
| 595 | case kRegImm: return true; |
| 596 | case kRegRegImm: return true; |
| 597 | case kRegRegImmStore: return true; |
| 598 | case kShiftRegImm: return true; |
| 599 | case kShiftRegCl: return true; |
| 600 | case kRegCond: return true; |
| 601 | case kRegRegCond: return true; |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 602 | case kShiftRegRegCl: return true; |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 603 | case kJmp: |
| 604 | switch (entry->opcode) { |
| 605 | case kX86JmpR: return true; |
| 606 | default: return false; |
| 607 | } |
| 608 | case kCall: |
| 609 | switch (entry->opcode) { |
| 610 | case kX86CallR: return true; |
| 611 | default: return false; |
| 612 | } |
| 613 | default: return false; |
| 614 | } |
| 615 | } |
| 616 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 617 | static bool IsByteSecondOperand(const X86EncodingMap* entry) { |
| 618 | return StartsWith(entry->name, "Movzx8") || StartsWith(entry->name, "Movsx8"); |
| 619 | } |
| 620 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 621 | size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 622 | int32_t raw_base, int32_t displacement) { |
| 623 | bool has_modrm = HasModrm(entry); |
| 624 | bool has_sib = HasSib(entry); |
| 625 | bool r8_form = entry->skeleton.r8_form; |
| 626 | bool modrm_is_reg_reg = ModrmIsRegReg(entry); |
| 627 | if (has_sib) { |
| 628 | DCHECK(!modrm_is_reg_reg); |
| 629 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 630 | size_t size = 0; |
| 631 | if (entry->skeleton.prefix1 > 0) { |
| 632 | ++size; |
| 633 | if (entry->skeleton.prefix2 > 0) { |
| 634 | ++size; |
| 635 | } |
| 636 | } |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 637 | if (cu_->target64 || kIsDebugBuild) { |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 638 | bool registers_need_rex_prefix = NeedsRex(raw_reg) || NeedsRex(raw_index) || NeedsRex(raw_base); |
| 639 | if (r8_form) { |
| 640 | // Do we need an empty REX prefix to normalize byte registers? |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 641 | registers_need_rex_prefix = registers_need_rex_prefix || |
| 642 | (RegStorage::RegNum(raw_reg) >= 4 && !IsByteSecondOperand(entry)); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 643 | registers_need_rex_prefix = registers_need_rex_prefix || |
| 644 | (modrm_is_reg_reg && (RegStorage::RegNum(raw_base) >= 4)); |
| 645 | } |
| 646 | if (registers_need_rex_prefix) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 647 | DCHECK(cu_->target64) << "Attempt to use a 64-bit only addressable register " |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 648 | << RegStorage::RegNum(raw_reg) << " with instruction " << entry->name; |
Serguei Katkov | 94f3eb0 | 2014-06-24 13:23:17 +0700 | [diff] [blame] | 649 | if (entry->skeleton.prefix1 != REX_W && entry->skeleton.prefix2 != REX_W |
| 650 | && entry->skeleton.prefix1 != REX && entry->skeleton.prefix2 != REX) { |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 651 | ++size; // rex |
| 652 | } |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 653 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 654 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 655 | ++size; // opcode |
| 656 | if (entry->skeleton.opcode == 0x0F) { |
| 657 | ++size; |
| 658 | if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { |
| 659 | ++size; |
| 660 | } |
| 661 | } |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 662 | if (has_modrm) { |
| 663 | ++size; // modrm |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 664 | } |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 665 | if (!modrm_is_reg_reg) { |
| 666 | if (has_sib || LowRegisterBits(raw_base) == rs_rX86_SP.GetRegNum() |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 667 | || (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX)) { |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 668 | // SP requires a SIB byte. |
| 669 | // GS access also needs a SIB byte for absolute adressing in 64-bit mode. |
| 670 | ++size; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 671 | } |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 672 | if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) { |
| 673 | // BP requires an explicit displacement, even when it's 0. |
| 674 | if (entry->opcode != kX86Lea32RA && entry->opcode != kX86Lea64RA) { |
| 675 | DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), UINT64_C(0)) << entry->name; |
| 676 | } |
| 677 | size += IS_SIMM8(displacement) ? 1 : 4; |
| 678 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 679 | } |
| 680 | size += entry->skeleton.immediate_bytes; |
| 681 | return size; |
| 682 | } |
| 683 | |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 684 | size_t X86Mir2Lir::GetInsnSize(LIR* lir) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 685 | DCHECK(!IsPseudoLirOp(lir->opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 686 | const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 687 | DCHECK_EQ(entry->opcode, lir->opcode) << entry->name; |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 688 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 689 | switch (entry->kind) { |
| 690 | case kData: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 691 | return 4; // 4 bytes of data. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 692 | case kNop: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 693 | return lir->operands[0]; // Length of nop is sole operand. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 694 | case kNullary: |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 695 | return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0); |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 696 | case kRegOpcode: // lir operands - 0: reg |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 697 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 698 | case kReg: // lir operands - 0: reg |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 699 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 700 | case kMem: // lir operands - 0: base, 1: disp |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 701 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 702 | case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 703 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 704 | case kMemReg: // lir operands - 0: base, 1: disp, 2: reg |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 705 | return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 706 | case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 707 | return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 708 | case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 709 | return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 710 | lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 711 | case kThreadReg: // lir operands - 0: disp, 1: reg |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 712 | // Thread displacement size is always 32bit. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 713 | return ComputeSize(entry, lir->operands[1], NO_REG, NO_REG, 0x12345678); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 714 | case kRegReg: // lir operands - 0: reg1, 1: reg2 |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 715 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 716 | case kRegRegStore: // lir operands - 0: reg2, 1: reg1 |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 717 | return ComputeSize(entry, lir->operands[1], NO_REG, lir->operands[0], 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 718 | case kRegMem: // lir operands - 0: reg, 1: base, 2: disp |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 719 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 720 | case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 721 | return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 722 | lir->operands[4]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 723 | case kRegThread: // lir operands - 0: reg, 1: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 724 | // Thread displacement size is always 32bit. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 725 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0x12345678); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 726 | case kRegImm: { // lir operands - 0: reg, 1: immediate |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 727 | size_t size = ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 728 | // AX opcodes don't require the modrm byte. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 729 | if (entry->skeleton.ax_opcode == 0) { |
| 730 | return size; |
| 731 | } else { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 732 | return size - (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 733 | } |
| 734 | } |
| 735 | case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 736 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 737 | case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 738 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 739 | case kThreadImm: // lir operands - 0: disp, 1: imm |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 740 | // Thread displacement size is always 32bit. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 741 | return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 742 | case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm |
| 743 | // Note: RegRegImm form passes reg2 as index but encodes it using base. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 744 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, 0); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 745 | case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm |
| 746 | // Note: RegRegImmStore form passes reg1 as index but encodes it using base. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 747 | return ComputeSize(entry, lir->operands[1], lir->operands[0], NO_REG, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 748 | case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 749 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 750 | case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 751 | return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 752 | lir->operands[4]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 753 | case kMovRegImm: // lir operands - 0: reg, 1: immediate |
Yixin Shou | 5192cbb | 2014-07-01 13:48:17 -0400 | [diff] [blame] | 754 | case kMovRegQuadImm: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 755 | return ((entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])) ? 1 : 0) + 1 + |
| 756 | entry->skeleton.immediate_bytes; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 757 | case kShiftRegImm: // lir operands - 0: reg, 1: immediate |
| 758 | // Shift by immediate one has a shorter opcode. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 759 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0) - |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 760 | (lir->operands[1] == 1 ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 761 | case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
| 762 | // Shift by immediate one has a shorter opcode. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 763 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]) - |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 764 | (lir->operands[2] == 1 ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 765 | case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate |
| 766 | // Shift by immediate one has a shorter opcode. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 767 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]) - |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 768 | (lir->operands[4] == 1 ? 1 : 0); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 769 | case kShiftRegCl: // lir operands - 0: reg, 1: cl |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 770 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[1])); |
| 771 | // Note: ShiftRegCl form passes reg as reg but encodes it using base. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 772 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 773 | case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 774 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2])); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 775 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 776 | case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cl |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 777 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[4])); |
| 778 | return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 779 | lir->operands[3]); |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 780 | case kShiftRegRegCl: // lir operands - 0: reg1, 1: reg2, 2: cl |
| 781 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2])); |
| 782 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 783 | case kRegCond: // lir operands - 0: reg, 1: cond |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 784 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 785 | case kMemCond: // lir operands - 0: base, 1: disp, 2: cond |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 786 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 787 | case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 788 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 789 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 790 | case kRegRegCond: // lir operands - 0: reg1, 1: reg2, 2: cond |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 791 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 792 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 793 | case kRegMemCond: // lir operands - 0: reg, 1: base, 2: disp, 3:cond |
| 794 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 795 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 796 | case kJcc: |
| 797 | if (lir->opcode == kX86Jcc8) { |
| 798 | return 2; // opcode + rel8 |
| 799 | } else { |
| 800 | DCHECK(lir->opcode == kX86Jcc32); |
| 801 | return 6; // 2 byte opcode + rel32 |
| 802 | } |
| 803 | case kJmp: |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 804 | if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 805 | return 2; // opcode + rel8 |
| 806 | } else if (lir->opcode == kX86Jmp32) { |
| 807 | return 5; // opcode + rel32 |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 808 | } else if (lir->opcode == kX86JmpT) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 809 | // Thread displacement size is always 32bit. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 810 | return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 811 | } else { |
| 812 | DCHECK(lir->opcode == kX86JmpR); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 813 | if (NeedsRex(lir->operands[0])) { |
| 814 | return 3; // REX.B + opcode + modrm |
| 815 | } else { |
| 816 | return 2; // opcode + modrm |
| 817 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 818 | } |
| 819 | case kCall: |
| 820 | switch (lir->opcode) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 821 | case kX86CallI: return 5; // opcode 0:disp |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 822 | case kX86CallR: return 2; // opcode modrm |
| 823 | case kX86CallM: // lir operands - 0: base, 1: disp |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 824 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 825 | case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 826 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 827 | case kX86CallT: // lir operands - 0: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 828 | // Thread displacement size is always 32bit. |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 829 | return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 830 | default: |
| 831 | break; |
| 832 | } |
| 833 | break; |
| 834 | case kPcRel: |
| 835 | if (entry->opcode == kX86PcRelLoadRA) { |
| 836 | // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 837 | // Force the displacement size to 32bit, it will hold a computed offset later. |
| 838 | return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 839 | 0x12345678); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 840 | } else { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 841 | DCHECK_EQ(entry->opcode, kX86PcRelAdr); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 842 | return 5; // opcode with reg + 4 byte immediate |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 843 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 844 | case kMacro: // lir operands - 0: reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 845 | DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); |
| 846 | return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 847 | ComputeSize(&X86Mir2Lir::EncodingMap[cu_->target64 ? kX86Sub64RI : kX86Sub32RI], |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 848 | lir->operands[0], NO_REG, NO_REG, 0) - |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 849 | // Shorter ax encoding. |
| 850 | (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); |
| 851 | case kUnimplemented: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 852 | break; |
| 853 | } |
| 854 | UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; |
| 855 | return 0; |
| 856 | } |
| 857 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 858 | static uint8_t ModrmForDisp(int base, int disp) { |
| 859 | // BP requires an explicit disp, so do not omit it in the 0 case |
| 860 | if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { |
| 861 | return 0; |
| 862 | } else if (IS_SIMM8(disp)) { |
| 863 | return 1; |
| 864 | } else { |
| 865 | return 2; |
| 866 | } |
| 867 | } |
| 868 | |
| 869 | void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) { |
| 870 | if (kIsDebugBuild) { |
| 871 | // Sanity check r8_form is correctly specified. |
| 872 | if (entry->skeleton.r8_form) { |
| 873 | CHECK(strchr(entry->name, '8') != nullptr) << entry->name; |
| 874 | } else { |
| 875 | if (entry->skeleton.immediate_bytes != 1) { // Ignore ...I8 instructions. |
Serguei Katkov | 1c55703 | 2014-06-23 13:23:38 +0700 | [diff] [blame] | 876 | if (!StartsWith(entry->name, "Movzx8") && !StartsWith(entry->name, "Movsx8") |
| 877 | && !StartsWith(entry->name, "Movzx8q") && !StartsWith(entry->name, "Movsx8q")) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 878 | CHECK(strchr(entry->name, '8') == nullptr) << entry->name; |
| 879 | } |
| 880 | } |
| 881 | } |
| 882 | if (RegStorage::RegNum(raw_reg) >= 4) { |
| 883 | // ah, bh, ch and dh are not valid registers in 32-bit. |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 884 | CHECK(cu_->target64 || !entry->skeleton.r8_form) |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 885 | << "Invalid register " << static_cast<int>(RegStorage::RegNum(raw_reg)) |
| 886 | << " for instruction " << entry->name << " in " |
| 887 | << PrettyMethod(cu_->method_idx, *cu_->dex_file); |
| 888 | } |
| 889 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 890 | } |
| 891 | |
| 892 | void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 893 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 894 | // REX.WRXB |
| 895 | // W - 64-bit operand |
| 896 | // R - MODRM.reg |
| 897 | // X - SIB.index |
| 898 | // B - MODRM.rm/SIB.base |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 899 | bool w = (entry->skeleton.prefix1 == REX_W) || (entry->skeleton.prefix2 == REX_W); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 900 | bool r = NeedsRex(raw_reg_r); |
| 901 | bool x = NeedsRex(raw_reg_x); |
| 902 | bool b = NeedsRex(raw_reg_b); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 903 | bool r8_form = entry->skeleton.r8_form; |
| 904 | bool modrm_is_reg_reg = ModrmIsRegReg(entry); |
| 905 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 906 | uint8_t rex = 0; |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 907 | if (r8_form) { |
| 908 | // Do we need an empty REX prefix to normalize byte register addressing? |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 909 | if (RegStorage::RegNum(raw_reg_r) >= 4 && !IsByteSecondOperand(entry)) { |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 910 | rex |= 0x40; // REX.0000 |
| 911 | } else if (modrm_is_reg_reg && RegStorage::RegNum(raw_reg_b) >= 4) { |
| 912 | rex |= 0x40; // REX.0000 |
| 913 | } |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 914 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 915 | if (w) { |
| 916 | rex |= 0x48; // REX.W000 |
| 917 | } |
| 918 | if (r) { |
| 919 | rex |= 0x44; // REX.0R00 |
| 920 | } |
| 921 | if (x) { |
| 922 | rex |= 0x42; // REX.00X0 |
| 923 | } |
| 924 | if (b) { |
| 925 | rex |= 0x41; // REX.000B |
| 926 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 927 | if (entry->skeleton.prefix1 != 0) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 928 | if (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 929 | // 64 bit addresses by GS, not FS. |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 930 | code_buffer_.push_back(THREAD_PREFIX_GS); |
| 931 | } else { |
Serguei Katkov | 94f3eb0 | 2014-06-24 13:23:17 +0700 | [diff] [blame] | 932 | if (entry->skeleton.prefix1 == REX_W || entry->skeleton.prefix1 == REX) { |
| 933 | DCHECK(cu_->target64); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 934 | rex |= entry->skeleton.prefix1; |
| 935 | code_buffer_.push_back(rex); |
| 936 | rex = 0; |
| 937 | } else { |
| 938 | code_buffer_.push_back(entry->skeleton.prefix1); |
| 939 | } |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 940 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 941 | if (entry->skeleton.prefix2 != 0) { |
Serguei Katkov | 94f3eb0 | 2014-06-24 13:23:17 +0700 | [diff] [blame] | 942 | if (entry->skeleton.prefix2 == REX_W || entry->skeleton.prefix1 == REX) { |
| 943 | DCHECK(cu_->target64); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 944 | rex |= entry->skeleton.prefix2; |
| 945 | code_buffer_.push_back(rex); |
| 946 | rex = 0; |
| 947 | } else { |
| 948 | code_buffer_.push_back(entry->skeleton.prefix2); |
| 949 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 950 | } |
| 951 | } else { |
| 952 | DCHECK_EQ(0, entry->skeleton.prefix2); |
| 953 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 954 | if (rex != 0) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 955 | DCHECK(cu_->target64); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 956 | code_buffer_.push_back(rex); |
| 957 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 958 | } |
| 959 | |
| 960 | void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { |
| 961 | code_buffer_.push_back(entry->skeleton.opcode); |
| 962 | if (entry->skeleton.opcode == 0x0F) { |
| 963 | code_buffer_.push_back(entry->skeleton.extra_opcode1); |
| 964 | if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { |
| 965 | code_buffer_.push_back(entry->skeleton.extra_opcode2); |
| 966 | } else { |
| 967 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
| 968 | } |
| 969 | } else { |
| 970 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 971 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
| 972 | } |
| 973 | } |
| 974 | |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 975 | void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 976 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) { |
| 977 | EmitPrefix(entry, raw_reg_r, raw_reg_x, raw_reg_b); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 978 | EmitOpcode(entry); |
| 979 | } |
| 980 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 981 | void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 982 | // BP requires an explicit disp, so do not omit it in the 0 case |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 983 | if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 984 | return; |
| 985 | } else if (IS_SIMM8(disp)) { |
| 986 | code_buffer_.push_back(disp & 0xFF); |
| 987 | } else { |
| 988 | code_buffer_.push_back(disp & 0xFF); |
| 989 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 990 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 991 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 992 | } |
| 993 | } |
| 994 | |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 995 | void X86Mir2Lir::EmitModrmThread(uint8_t reg_or_opcode) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 996 | if (cu_->target64) { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 997 | // Absolute adressing for GS access. |
| 998 | uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rX86_SP.GetRegNum(); |
| 999 | code_buffer_.push_back(modrm); |
| 1000 | uint8_t sib = (0/*TIMES_1*/ << 6) | (rs_rX86_SP.GetRegNum() << 3) | rs_rBP.GetRegNum(); |
| 1001 | code_buffer_.push_back(sib); |
| 1002 | } else { |
| 1003 | uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rBP.GetRegNum(); |
| 1004 | code_buffer_.push_back(modrm); |
| 1005 | } |
| 1006 | } |
| 1007 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1008 | void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) { |
| 1009 | DCHECK_LT(reg_or_opcode, 8); |
| 1010 | DCHECK_LT(base, 8); |
| 1011 | uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1012 | code_buffer_.push_back(modrm); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1013 | if (base == rs_rX86_SP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1014 | // Special SIB for SP base |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1015 | code_buffer_.push_back(0 << 6 | rs_rX86_SP.GetRegNum() << 3 | rs_rX86_SP.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1016 | } |
| 1017 | EmitDisp(base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1018 | } |
| 1019 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1020 | void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1021 | int scale, int32_t disp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1022 | DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8); |
| 1023 | uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 | |
| 1024 | rs_rX86_SP.GetRegNum(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1025 | code_buffer_.push_back(modrm); |
| 1026 | DCHECK_LT(scale, 4); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1027 | DCHECK_LT(RegStorage::RegNum(index), 8); |
| 1028 | DCHECK_LT(RegStorage::RegNum(base), 8); |
| 1029 | uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1030 | code_buffer_.push_back(sib); |
| 1031 | EmitDisp(base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1032 | } |
| 1033 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1034 | void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1035 | switch (entry->skeleton.immediate_bytes) { |
| 1036 | case 1: |
| 1037 | DCHECK(IS_SIMM8(imm)); |
| 1038 | code_buffer_.push_back(imm & 0xFF); |
| 1039 | break; |
| 1040 | case 2: |
| 1041 | DCHECK(IS_SIMM16(imm)); |
| 1042 | code_buffer_.push_back(imm & 0xFF); |
| 1043 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1044 | break; |
| 1045 | case 4: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1046 | DCHECK(IS_SIMM32(imm)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1047 | code_buffer_.push_back(imm & 0xFF); |
| 1048 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1049 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 1050 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 1051 | break; |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1052 | case 8: |
| 1053 | code_buffer_.push_back(imm & 0xFF); |
| 1054 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1055 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 1056 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 1057 | code_buffer_.push_back((imm >> 32) & 0xFF); |
| 1058 | code_buffer_.push_back((imm >> 40) & 0xFF); |
| 1059 | code_buffer_.push_back((imm >> 48) & 0xFF); |
| 1060 | code_buffer_.push_back((imm >> 56) & 0xFF); |
| 1061 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1062 | default: |
| 1063 | LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes |
| 1064 | << ") for instruction: " << entry->name; |
| 1065 | break; |
| 1066 | } |
| 1067 | } |
| 1068 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1069 | void X86Mir2Lir::EmitNullary(const X86EncodingMap* entry) { |
| 1070 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1071 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1072 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1073 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1074 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1075 | } |
| 1076 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1077 | void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg) { |
| 1078 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1079 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1080 | // There's no 3-byte instruction with +rd |
| 1081 | DCHECK(entry->skeleton.opcode != 0x0F || |
| 1082 | (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A)); |
| 1083 | DCHECK(!RegStorage::IsFloat(raw_reg)); |
| 1084 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1085 | code_buffer_.back() += low_reg; |
| 1086 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1087 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1088 | } |
| 1089 | |
| 1090 | void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg) { |
| 1091 | CheckValidByteRegister(entry, raw_reg); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1092 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1093 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1094 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1095 | code_buffer_.push_back(modrm); |
| 1096 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1097 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1098 | } |
| 1099 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1100 | void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { |
| 1101 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1102 | EmitPrefix(entry, NO_REG, NO_REG, raw_base); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1103 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1104 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1105 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1106 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1107 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1108 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1109 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1110 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1111 | } |
| 1112 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1113 | void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, |
| 1114 | int scale, int32_t disp) { |
| 1115 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1116 | EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1117 | uint8_t low_index = LowRegisterBits(raw_index); |
| 1118 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1119 | EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1120 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1121 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1122 | } |
| 1123 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1124 | void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, |
| 1125 | int32_t raw_reg) { |
| 1126 | CheckValidByteRegister(entry, raw_reg); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1127 | EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1128 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1129 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1130 | EmitModrmDisp(low_reg, low_base, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1131 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1132 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1133 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1134 | } |
| 1135 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1136 | void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 1137 | int32_t disp) { |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1138 | // Opcode will flip operands. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1139 | EmitMemReg(entry, raw_base, disp, raw_reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1140 | } |
| 1141 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1142 | void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 1143 | int32_t raw_index, int scale, int32_t disp) { |
| 1144 | CheckValidByteRegister(entry, raw_reg); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1145 | EmitPrefixAndOpcode(entry, raw_reg, raw_index, raw_base); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1146 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1147 | uint8_t low_index = LowRegisterBits(raw_index); |
| 1148 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1149 | EmitModrmSibDisp(low_reg, low_base, low_index, scale, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1150 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1151 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1152 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1153 | } |
| 1154 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1155 | void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, |
| 1156 | int scale, int32_t disp, int32_t raw_reg) { |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1157 | // Opcode will flip operands. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1158 | EmitRegArray(entry, raw_reg, raw_base, raw_index, scale, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1159 | } |
| 1160 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1161 | void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, |
| 1162 | int32_t imm) { |
| 1163 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1164 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1165 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1166 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1167 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
Mark Mendell | 9ed4277 | 2014-05-07 17:26:12 -0400 | [diff] [blame] | 1168 | EmitImm(entry, imm); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1169 | } |
| 1170 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1171 | void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry, |
| 1172 | int32_t raw_base, int32_t raw_index, int scale, int32_t disp, |
| 1173 | int32_t imm) { |
| 1174 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1175 | EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1176 | uint8_t low_index = LowRegisterBits(raw_index); |
| 1177 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1178 | EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); |
| 1179 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1180 | EmitImm(entry, imm); |
| 1181 | } |
| 1182 | |
| 1183 | void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) { |
| 1184 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1185 | DCHECK_NE(entry->skeleton.prefix1, 0); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1186 | EmitPrefixAndOpcode(entry, raw_reg, NO_REG, NO_REG); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1187 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1188 | EmitModrmThread(low_reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1189 | code_buffer_.push_back(disp & 0xFF); |
| 1190 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1191 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1192 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1193 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1194 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1195 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1196 | } |
| 1197 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1198 | void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2) { |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1199 | if (!IsByteSecondOperand(entry)) { |
| 1200 | CheckValidByteRegister(entry, raw_reg1); |
| 1201 | } |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1202 | CheckValidByteRegister(entry, raw_reg2); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1203 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1204 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1205 | uint8_t low_reg2 = LowRegisterBits(raw_reg2); |
| 1206 | uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1207 | code_buffer_.push_back(modrm); |
| 1208 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1209 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1210 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1211 | } |
| 1212 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1213 | void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, |
| 1214 | int32_t imm) { |
| 1215 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1216 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1217 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1218 | uint8_t low_reg2 = LowRegisterBits(raw_reg2); |
| 1219 | uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1220 | code_buffer_.push_back(modrm); |
| 1221 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1222 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1223 | EmitImm(entry, imm); |
| 1224 | } |
| 1225 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1226 | void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1227 | int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) { |
| 1228 | DCHECK(!RegStorage::IsFloat(raw_reg)); |
| 1229 | CheckValidByteRegister(entry, raw_reg); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1230 | EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1231 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1232 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1233 | EmitModrmDisp(low_reg, low_base, disp); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1234 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1235 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1236 | EmitImm(entry, imm); |
| 1237 | } |
| 1238 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1239 | void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1240 | int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) { |
| 1241 | // Opcode will flip operands. |
| 1242 | EmitRegMemImm(entry, raw_reg, raw_base, disp, imm); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1243 | } |
| 1244 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1245 | void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { |
| 1246 | CheckValidByteRegister(entry, raw_reg); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1247 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1248 | if (RegStorage::RegNum(raw_reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1249 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1250 | } else { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1251 | uint8_t low_reg = LowRegisterBits(raw_reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1252 | EmitOpcode(entry); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1253 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1254 | code_buffer_.push_back(modrm); |
| 1255 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1256 | EmitImm(entry, imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1257 | } |
| 1258 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1259 | void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) { |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1260 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1261 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 1262 | EmitModrmThread(entry->skeleton.modrm_opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1263 | code_buffer_.push_back(disp & 0xFF); |
| 1264 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1265 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1266 | code_buffer_.push_back((disp >> 24) & 0xFF); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1267 | EmitImm(entry, imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1268 | DCHECK_EQ(entry->skeleton.ax_opcode, 0); |
| 1269 | } |
| 1270 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1271 | void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) { |
| 1272 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1273 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1274 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1275 | code_buffer_.push_back(0xB8 + low_reg); |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1276 | switch (entry->skeleton.immediate_bytes) { |
| 1277 | case 4: |
| 1278 | code_buffer_.push_back(imm & 0xFF); |
| 1279 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1280 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 1281 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 1282 | break; |
| 1283 | case 8: |
| 1284 | code_buffer_.push_back(imm & 0xFF); |
| 1285 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1286 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 1287 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 1288 | code_buffer_.push_back((imm >> 32) & 0xFF); |
| 1289 | code_buffer_.push_back((imm >> 40) & 0xFF); |
| 1290 | code_buffer_.push_back((imm >> 48) & 0xFF); |
| 1291 | code_buffer_.push_back((imm >> 56) & 0xFF); |
| 1292 | break; |
| 1293 | default: |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1294 | LOG(FATAL) << "Unsupported immediate size for EmitMovRegImm: " |
| 1295 | << static_cast<uint32_t>(entry->skeleton.immediate_bytes); |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1296 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1297 | } |
| 1298 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1299 | void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { |
| 1300 | CheckValidByteRegister(entry, raw_reg); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1301 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1302 | if (imm != 1) { |
| 1303 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1304 | } else { |
| 1305 | // Shorter encoding for 1 bit shift |
| 1306 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1307 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1308 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1309 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1310 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1311 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1312 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1313 | code_buffer_.push_back(modrm); |
| 1314 | if (imm != 1) { |
| 1315 | DCHECK_EQ(entry->skeleton.immediate_bytes, 1); |
| 1316 | DCHECK(IS_SIMM8(imm)); |
| 1317 | code_buffer_.push_back(imm & 0xFF); |
| 1318 | } |
| 1319 | } |
| 1320 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1321 | void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl) { |
| 1322 | CheckValidByteRegister(entry, raw_reg); |
| 1323 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1324 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1325 | code_buffer_.push_back(entry->skeleton.opcode); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1326 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1327 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1328 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1329 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1330 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1331 | code_buffer_.push_back(modrm); |
| 1332 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1333 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1334 | } |
| 1335 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1336 | void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, |
| 1337 | int32_t displacement, int32_t raw_cl) { |
| 1338 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1339 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1340 | EmitPrefix(entry, NO_REG, NO_REG, raw_base); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1341 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1342 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1343 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1344 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1345 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1346 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, displacement); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1347 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1348 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1349 | } |
| 1350 | |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 1351 | void X86Mir2Lir::EmitShiftRegRegCl(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t raw_cl) { |
| 1352 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1353 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); |
| 1354 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); |
| 1355 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1356 | uint8_t low_reg2 = LowRegisterBits(raw_reg2); |
| 1357 | uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; |
| 1358 | code_buffer_.push_back(modrm); |
| 1359 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1360 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1361 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1362 | } |
| 1363 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1364 | void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, |
| 1365 | int32_t imm) { |
| 1366 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1367 | EmitPrefix(entry, NO_REG, NO_REG, raw_base); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1368 | if (imm != 1) { |
| 1369 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1370 | } else { |
| 1371 | // Shorter encoding for 1 bit shift |
| 1372 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1373 | } |
| 1374 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1375 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1376 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1377 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1378 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1379 | if (imm != 1) { |
| 1380 | DCHECK_EQ(entry->skeleton.immediate_bytes, 1); |
| 1381 | DCHECK(IS_SIMM8(imm)); |
| 1382 | code_buffer_.push_back(imm & 0xFF); |
| 1383 | } |
| 1384 | } |
| 1385 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1386 | void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc) { |
| 1387 | CheckValidByteRegister(entry, raw_reg); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1388 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1389 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1390 | DCHECK_EQ(0x0F, entry->skeleton.opcode); |
| 1391 | code_buffer_.push_back(0x0F); |
| 1392 | DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1393 | DCHECK_GE(cc, 0); |
| 1394 | DCHECK_LT(cc, 16); |
| 1395 | code_buffer_.push_back(0x90 | cc); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1396 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1397 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1398 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1399 | code_buffer_.push_back(modrm); |
| 1400 | DCHECK_EQ(entry->skeleton.immediate_bytes, 0); |
| 1401 | } |
| 1402 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1403 | void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, |
| 1404 | int32_t cc) { |
| 1405 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1406 | if (entry->skeleton.prefix1 != 0) { |
| 1407 | code_buffer_.push_back(entry->skeleton.prefix1); |
| 1408 | if (entry->skeleton.prefix2 != 0) { |
| 1409 | code_buffer_.push_back(entry->skeleton.prefix2); |
| 1410 | } |
| 1411 | } else { |
| 1412 | DCHECK_EQ(0, entry->skeleton.prefix2); |
| 1413 | } |
| 1414 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1415 | DCHECK_EQ(0x0F, entry->skeleton.opcode); |
| 1416 | code_buffer_.push_back(0x0F); |
| 1417 | DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1418 | DCHECK_GE(cc, 0); |
| 1419 | DCHECK_LT(cc, 16); |
| 1420 | code_buffer_.push_back(0x90 | cc); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1421 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1422 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1423 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1424 | DCHECK_EQ(entry->skeleton.immediate_bytes, 0); |
| 1425 | } |
| 1426 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1427 | void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, |
| 1428 | int32_t cc) { |
| 1429 | // Generate prefix and opcode without the condition. |
| 1430 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1431 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1432 | |
| 1433 | // Now add the condition. The last byte of opcode is the one that receives it. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1434 | DCHECK_GE(cc, 0); |
| 1435 | DCHECK_LT(cc, 16); |
| 1436 | code_buffer_.back() += cc; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1437 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1438 | // Not expecting to have to encode immediate or do anything special for ModR/M since there are |
| 1439 | // two registers. |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1440 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1441 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1442 | |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1443 | // For register to register encoding, the mod is 3. |
| 1444 | const uint8_t mod = (3 << 6); |
| 1445 | |
| 1446 | // Encode the ModR/M byte now. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1447 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1448 | uint8_t low_reg2 = LowRegisterBits(raw_reg2); |
| 1449 | const uint8_t modrm = mod | (low_reg1 << 3) | low_reg2; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1450 | code_buffer_.push_back(modrm); |
| 1451 | } |
| 1452 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1453 | void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, |
| 1454 | int32_t disp, int32_t cc) { |
| 1455 | // Generate prefix and opcode without the condition. |
| 1456 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1457 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_base); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1458 | |
| 1459 | // Now add the condition. The last byte of opcode is the one that receives it. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1460 | DCHECK_GE(cc, 0); |
| 1461 | DCHECK_LT(cc, 16); |
| 1462 | code_buffer_.back() += cc; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1463 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1464 | // Not expecting to have to encode immediate or do anything special for ModR/M since there are |
| 1465 | // two registers. |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1466 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1467 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1468 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1469 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1470 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1471 | EmitModrmDisp(low_reg1, low_base, disp); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1472 | } |
| 1473 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1474 | void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int32_t rel) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1475 | if (entry->opcode == kX86Jmp8) { |
| 1476 | DCHECK(IS_SIMM8(rel)); |
| 1477 | code_buffer_.push_back(0xEB); |
| 1478 | code_buffer_.push_back(rel & 0xFF); |
| 1479 | } else if (entry->opcode == kX86Jmp32) { |
| 1480 | code_buffer_.push_back(0xE9); |
| 1481 | code_buffer_.push_back(rel & 0xFF); |
| 1482 | code_buffer_.push_back((rel >> 8) & 0xFF); |
| 1483 | code_buffer_.push_back((rel >> 16) & 0xFF); |
| 1484 | code_buffer_.push_back((rel >> 24) & 0xFF); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1485 | } else if (entry->opcode == kX86Jecxz8) { |
| 1486 | DCHECK(IS_SIMM8(rel)); |
| 1487 | code_buffer_.push_back(0xE3); |
| 1488 | code_buffer_.push_back(rel & 0xFF); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1489 | } else { |
| 1490 | DCHECK(entry->opcode == kX86JmpR); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1491 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1492 | EmitPrefix(entry, NO_REG, NO_REG, rel); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1493 | code_buffer_.push_back(entry->skeleton.opcode); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1494 | uint8_t low_reg = LowRegisterBits(rel); |
| 1495 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1496 | code_buffer_.push_back(modrm); |
| 1497 | } |
| 1498 | } |
| 1499 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1500 | void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc) { |
| 1501 | DCHECK_GE(cc, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1502 | DCHECK_LT(cc, 16); |
| 1503 | if (entry->opcode == kX86Jcc8) { |
| 1504 | DCHECK(IS_SIMM8(rel)); |
| 1505 | code_buffer_.push_back(0x70 | cc); |
| 1506 | code_buffer_.push_back(rel & 0xFF); |
| 1507 | } else { |
| 1508 | DCHECK(entry->opcode == kX86Jcc32); |
| 1509 | code_buffer_.push_back(0x0F); |
| 1510 | code_buffer_.push_back(0x80 | cc); |
| 1511 | code_buffer_.push_back(rel & 0xFF); |
| 1512 | code_buffer_.push_back((rel >> 8) & 0xFF); |
| 1513 | code_buffer_.push_back((rel >> 16) & 0xFF); |
| 1514 | code_buffer_.push_back((rel >> 24) & 0xFF); |
| 1515 | } |
| 1516 | } |
| 1517 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1518 | void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { |
| 1519 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1520 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1521 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1522 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1523 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1524 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1525 | } |
| 1526 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1527 | void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) { |
| 1528 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1529 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1530 | DCHECK_EQ(4, entry->skeleton.immediate_bytes); |
| 1531 | code_buffer_.push_back(disp & 0xFF); |
| 1532 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1533 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1534 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1535 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1536 | } |
| 1537 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1538 | void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int32_t disp) { |
| 1539 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1540 | DCHECK_NE(entry->skeleton.prefix1, 0); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1541 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 1542 | EmitModrmThread(entry->skeleton.modrm_opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1543 | code_buffer_.push_back(disp & 0xFF); |
| 1544 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1545 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1546 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1547 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1548 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1549 | } |
| 1550 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1551 | void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, |
| 1552 | int32_t raw_index, int scale, int32_t table_or_disp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1553 | int disp; |
| 1554 | if (entry->opcode == kX86PcRelLoadRA) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1555 | Mir2Lir::EmbeddedData *tab_rec = |
| 1556 | reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1557 | disp = tab_rec->offset; |
| 1558 | } else { |
| 1559 | DCHECK(entry->opcode == kX86PcRelAdr); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1560 | Mir2Lir::EmbeddedData *tab_rec = |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1561 | reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(raw_base_or_table)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1562 | disp = tab_rec->offset; |
| 1563 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1564 | if (entry->opcode == kX86PcRelLoadRA) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1565 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1566 | EmitPrefix(entry, raw_reg, raw_index, raw_base_or_table); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1567 | code_buffer_.push_back(entry->skeleton.opcode); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1568 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1569 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1570 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1571 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1572 | uint8_t modrm = (2 << 6) | (low_reg << 3) | rs_rX86_SP.GetRegNum(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1573 | code_buffer_.push_back(modrm); |
| 1574 | DCHECK_LT(scale, 4); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1575 | uint8_t low_base_or_table = LowRegisterBits(raw_base_or_table); |
| 1576 | uint8_t low_index = LowRegisterBits(raw_index); |
| 1577 | uint8_t sib = (scale << 6) | (low_index << 3) | low_base_or_table; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1578 | code_buffer_.push_back(sib); |
| 1579 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1580 | } else { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1581 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1582 | code_buffer_.push_back(entry->skeleton.opcode + low_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1583 | } |
| 1584 | code_buffer_.push_back(disp & 0xFF); |
| 1585 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1586 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1587 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1588 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1589 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1590 | } |
| 1591 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1592 | void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset) { |
| 1593 | DCHECK_EQ(entry->opcode, kX86StartOfMethod) << entry->name; |
| 1594 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1595 | EmitPrefix(entry, raw_reg, NO_REG, NO_REG); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1596 | code_buffer_.push_back(0xE8); // call +0 |
| 1597 | code_buffer_.push_back(0); |
| 1598 | code_buffer_.push_back(0); |
| 1599 | code_buffer_.push_back(0); |
| 1600 | code_buffer_.push_back(0); |
| 1601 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1602 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1603 | code_buffer_.push_back(0x58 + low_reg); // pop reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1604 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1605 | EmitRegImm(&X86Mir2Lir::EncodingMap[cu_->target64 ? kX86Sub64RI : kX86Sub32RI], |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1606 | raw_reg, offset + 5 /* size of call +0 */); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1607 | } |
| 1608 | |
| 1609 | void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { |
| 1610 | UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " |
| 1611 | << BuildInsnString(entry->fmt, lir, 0); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1612 | for (size_t i = 0; i < GetInsnSize(lir); ++i) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1613 | code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 |
| 1614 | } |
| 1615 | } |
| 1616 | |
| 1617 | /* |
| 1618 | * Assemble the LIR into binary instruction format. Note that we may |
| 1619 | * discover that pc-relative displacements may not fit the selected |
| 1620 | * instruction. In those cases we will try to substitute a new code |
| 1621 | * sequence or request that the trace be shortened and retried. |
| 1622 | */ |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1623 | AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1624 | LIR *lir; |
| 1625 | AssemblerStatus res = kSuccess; // Assume success |
| 1626 | |
| 1627 | const bool kVerbosePcFixup = false; |
| 1628 | for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 1629 | if (IsPseudoLirOp(lir->opcode)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1630 | continue; |
| 1631 | } |
| 1632 | |
| 1633 | if (lir->flags.is_nop) { |
| 1634 | continue; |
| 1635 | } |
| 1636 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1637 | if (lir->flags.fixup != kFixupNone) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1638 | switch (lir->opcode) { |
| 1639 | case kX86Jcc8: { |
| 1640 | LIR *target_lir = lir->target; |
| 1641 | DCHECK(target_lir != NULL); |
| 1642 | int delta = 0; |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1643 | CodeOffset pc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1644 | if (IS_SIMM8(lir->operands[0])) { |
| 1645 | pc = lir->offset + 2 /* opcode + rel8 */; |
| 1646 | } else { |
| 1647 | pc = lir->offset + 6 /* 2 byte opcode + rel32 */; |
| 1648 | } |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1649 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1650 | delta = target - pc; |
| 1651 | if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { |
| 1652 | if (kVerbosePcFixup) { |
| 1653 | LOG(INFO) << "Retry for JCC growth at " << lir->offset |
| 1654 | << " delta: " << delta << " old delta: " << lir->operands[0]; |
| 1655 | } |
| 1656 | lir->opcode = kX86Jcc32; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1657 | lir->flags.size = GetInsnSize(lir); |
| 1658 | DCHECK(lir->u.m.def_mask->Equals(kEncodeAll)); |
| 1659 | DCHECK(lir->u.m.use_mask->Equals(kEncodeAll)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1660 | res = kRetryAll; |
| 1661 | } |
| 1662 | if (kVerbosePcFixup) { |
| 1663 | LOG(INFO) << "Source:"; |
| 1664 | DumpLIRInsn(lir, 0); |
| 1665 | LOG(INFO) << "Target:"; |
| 1666 | DumpLIRInsn(target_lir, 0); |
| 1667 | LOG(INFO) << "Delta " << delta; |
| 1668 | } |
| 1669 | lir->operands[0] = delta; |
| 1670 | break; |
| 1671 | } |
| 1672 | case kX86Jcc32: { |
| 1673 | LIR *target_lir = lir->target; |
| 1674 | DCHECK(target_lir != NULL); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1675 | CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; |
| 1676 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1677 | int delta = target - pc; |
| 1678 | if (kVerbosePcFixup) { |
| 1679 | LOG(INFO) << "Source:"; |
| 1680 | DumpLIRInsn(lir, 0); |
| 1681 | LOG(INFO) << "Target:"; |
| 1682 | DumpLIRInsn(target_lir, 0); |
| 1683 | LOG(INFO) << "Delta " << delta; |
| 1684 | } |
| 1685 | lir->operands[0] = delta; |
| 1686 | break; |
| 1687 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1688 | case kX86Jecxz8: { |
| 1689 | LIR *target_lir = lir->target; |
| 1690 | DCHECK(target_lir != NULL); |
| 1691 | CodeOffset pc; |
| 1692 | pc = lir->offset + 2; // opcode + rel8 |
| 1693 | CodeOffset target = target_lir->offset; |
| 1694 | int delta = target - pc; |
| 1695 | lir->operands[0] = delta; |
| 1696 | DCHECK(IS_SIMM8(delta)); |
| 1697 | break; |
| 1698 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1699 | case kX86Jmp8: { |
| 1700 | LIR *target_lir = lir->target; |
| 1701 | DCHECK(target_lir != NULL); |
| 1702 | int delta = 0; |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1703 | CodeOffset pc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1704 | if (IS_SIMM8(lir->operands[0])) { |
| 1705 | pc = lir->offset + 2 /* opcode + rel8 */; |
| 1706 | } else { |
| 1707 | pc = lir->offset + 5 /* opcode + rel32 */; |
| 1708 | } |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1709 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1710 | delta = target - pc; |
| 1711 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { |
| 1712 | // Useless branch |
buzbee | 252254b | 2013-09-08 16:20:53 -0700 | [diff] [blame] | 1713 | NopLIR(lir); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1714 | if (kVerbosePcFixup) { |
| 1715 | LOG(INFO) << "Retry for useless branch at " << lir->offset; |
| 1716 | } |
| 1717 | res = kRetryAll; |
| 1718 | } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { |
| 1719 | if (kVerbosePcFixup) { |
| 1720 | LOG(INFO) << "Retry for JMP growth at " << lir->offset; |
| 1721 | } |
| 1722 | lir->opcode = kX86Jmp32; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1723 | lir->flags.size = GetInsnSize(lir); |
| 1724 | DCHECK(lir->u.m.def_mask->Equals(kEncodeAll)); |
| 1725 | DCHECK(lir->u.m.use_mask->Equals(kEncodeAll)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1726 | res = kRetryAll; |
| 1727 | } |
| 1728 | lir->operands[0] = delta; |
| 1729 | break; |
| 1730 | } |
| 1731 | case kX86Jmp32: { |
| 1732 | LIR *target_lir = lir->target; |
| 1733 | DCHECK(target_lir != NULL); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1734 | CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; |
| 1735 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1736 | int delta = target - pc; |
| 1737 | lir->operands[0] = delta; |
| 1738 | break; |
| 1739 | } |
| 1740 | default: |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 1741 | if (lir->flags.fixup == kFixupLoad) { |
| 1742 | LIR *target_lir = lir->target; |
| 1743 | DCHECK(target_lir != NULL); |
| 1744 | CodeOffset target = target_lir->offset; |
| 1745 | lir->operands[2] = target; |
| 1746 | int newSize = GetInsnSize(lir); |
| 1747 | if (newSize != lir->flags.size) { |
| 1748 | lir->flags.size = newSize; |
| 1749 | res = kRetryAll; |
| 1750 | } |
| 1751 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1752 | break; |
| 1753 | } |
| 1754 | } |
| 1755 | |
| 1756 | /* |
| 1757 | * If one of the pc-relative instructions expanded we'll have |
| 1758 | * to make another pass. Don't bother to fully assemble the |
| 1759 | * instruction. |
| 1760 | */ |
| 1761 | if (res != kSuccess) { |
| 1762 | continue; |
| 1763 | } |
| 1764 | CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); |
| 1765 | const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; |
| 1766 | size_t starting_cbuf_size = code_buffer_.size(); |
| 1767 | switch (entry->kind) { |
| 1768 | case kData: // 4 bytes of data |
| 1769 | code_buffer_.push_back(lir->operands[0]); |
| 1770 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1771 | case kNullary: // 1 byte of opcode and possible prefixes. |
| 1772 | EmitNullary(entry); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1773 | break; |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 1774 | case kRegOpcode: // lir operands - 0: reg |
| 1775 | EmitOpRegOpcode(entry, lir->operands[0]); |
| 1776 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1777 | case kReg: // lir operands - 0: reg |
| 1778 | EmitOpReg(entry, lir->operands[0]); |
| 1779 | break; |
| 1780 | case kMem: // lir operands - 0: base, 1: disp |
| 1781 | EmitOpMem(entry, lir->operands[0], lir->operands[1]); |
| 1782 | break; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1783 | case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
| 1784 | EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]); |
| 1785 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1786 | case kMemReg: // lir operands - 0: base, 1: disp, 2: reg |
| 1787 | EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1788 | break; |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1789 | case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
| 1790 | EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1791 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1792 | case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate |
| 1793 | EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1794 | lir->operands[3], lir->operands[4]); |
| 1795 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1796 | case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg |
| 1797 | EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1798 | lir->operands[3], lir->operands[4]); |
| 1799 | break; |
| 1800 | case kRegMem: // lir operands - 0: reg, 1: base, 2: disp |
| 1801 | EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1802 | break; |
| 1803 | case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp |
| 1804 | EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1805 | lir->operands[3], lir->operands[4]); |
| 1806 | break; |
| 1807 | case kRegThread: // lir operands - 0: reg, 1: disp |
| 1808 | EmitRegThread(entry, lir->operands[0], lir->operands[1]); |
| 1809 | break; |
| 1810 | case kRegReg: // lir operands - 0: reg1, 1: reg2 |
| 1811 | EmitRegReg(entry, lir->operands[0], lir->operands[1]); |
| 1812 | break; |
| 1813 | case kRegRegStore: // lir operands - 0: reg2, 1: reg1 |
| 1814 | EmitRegReg(entry, lir->operands[1], lir->operands[0]); |
| 1815 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1816 | case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1817 | EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1818 | lir->operands[3]); |
| 1819 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1820 | case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1821 | EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1822 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1823 | case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm |
| 1824 | EmitRegRegImm(entry, lir->operands[1], lir->operands[0], lir->operands[2]); |
| 1825 | break; |
| 1826 | case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1827 | EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1828 | lir->operands[3]); |
| 1829 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1830 | case kRegImm: // lir operands - 0: reg, 1: immediate |
| 1831 | EmitRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1832 | break; |
| 1833 | case kThreadImm: // lir operands - 0: disp, 1: immediate |
| 1834 | EmitThreadImm(entry, lir->operands[0], lir->operands[1]); |
| 1835 | break; |
| 1836 | case kMovRegImm: // lir operands - 0: reg, 1: immediate |
| 1837 | EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1838 | break; |
Yixin Shou | 5192cbb | 2014-07-01 13:48:17 -0400 | [diff] [blame] | 1839 | case kMovRegQuadImm: { |
| 1840 | int64_t value = static_cast<int64_t>(static_cast<int64_t>(lir->operands[1]) << 32 | |
| 1841 | static_cast<uint32_t>(lir->operands[2])); |
| 1842 | EmitMovRegImm(entry, lir->operands[0], value); |
| 1843 | } |
| 1844 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1845 | case kShiftRegImm: // lir operands - 0: reg, 1: immediate |
| 1846 | EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1847 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1848 | case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate |
| 1849 | EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1850 | break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1851 | case kShiftRegCl: // lir operands - 0: reg, 1: cl |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1852 | EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); |
| 1853 | break; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1854 | case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl |
| 1855 | EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1856 | break; |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 1857 | case kShiftRegRegCl: // lir operands - 0: reg1, 1: reg2, 2: cl |
| 1858 | EmitShiftRegRegCl(entry, lir->operands[1], lir->operands[0], lir->operands[2]); |
| 1859 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1860 | case kRegCond: // lir operands - 0: reg, 1: condition |
| 1861 | EmitRegCond(entry, lir->operands[0], lir->operands[1]); |
| 1862 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1863 | case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition |
| 1864 | EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1865 | break; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1866 | case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition |
| 1867 | EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1868 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1869 | case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1870 | EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1871 | lir->operands[3]); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1872 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1873 | case kJmp: // lir operands - 0: rel |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 1874 | if (entry->opcode == kX86JmpT) { |
| 1875 | // This works since the instruction format for jmp and call is basically the same and |
| 1876 | // EmitCallThread loads opcode info. |
| 1877 | EmitCallThread(entry, lir->operands[0]); |
| 1878 | } else { |
| 1879 | EmitJmp(entry, lir->operands[0]); |
| 1880 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1881 | break; |
| 1882 | case kJcc: // lir operands - 0: rel, 1: CC, target assigned |
| 1883 | EmitJcc(entry, lir->operands[0], lir->operands[1]); |
| 1884 | break; |
| 1885 | case kCall: |
| 1886 | switch (entry->opcode) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1887 | case kX86CallI: // lir operands - 0: disp |
| 1888 | EmitCallImmediate(entry, lir->operands[0]); |
| 1889 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1890 | case kX86CallM: // lir operands - 0: base, 1: disp |
| 1891 | EmitCallMem(entry, lir->operands[0], lir->operands[1]); |
| 1892 | break; |
| 1893 | case kX86CallT: // lir operands - 0: disp |
| 1894 | EmitCallThread(entry, lir->operands[0]); |
| 1895 | break; |
| 1896 | default: |
| 1897 | EmitUnimplemented(entry, lir); |
| 1898 | break; |
| 1899 | } |
| 1900 | break; |
| 1901 | case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table |
| 1902 | EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1903 | lir->operands[3], lir->operands[4]); |
| 1904 | break; |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1905 | case kMacro: // lir operands - 0: reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1906 | EmitMacro(entry, lir->operands[0], lir->offset); |
| 1907 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1908 | case kNop: // TODO: these instruction kinds are missing implementations. |
| 1909 | case kThreadReg: |
| 1910 | case kRegArrayImm: |
| 1911 | case kShiftArrayImm: |
| 1912 | case kShiftArrayCl: |
| 1913 | case kArrayCond: |
| 1914 | case kUnimplemented: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1915 | EmitUnimplemented(entry, lir); |
| 1916 | break; |
| 1917 | } |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 1918 | DCHECK_EQ(lir->flags.size, GetInsnSize(lir)); |
| 1919 | CHECK_EQ(lir->flags.size, code_buffer_.size() - starting_cbuf_size) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1920 | << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; |
| 1921 | } |
| 1922 | return res; |
| 1923 | } |
| 1924 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1925 | // LIR offset assignment. |
| 1926 | // TODO: consolidate w/ Arm assembly mechanism. |
| 1927 | int X86Mir2Lir::AssignInsnOffsets() { |
| 1928 | LIR* lir; |
| 1929 | int offset = 0; |
| 1930 | |
| 1931 | for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { |
| 1932 | lir->offset = offset; |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 1933 | if (LIKELY(!IsPseudoLirOp(lir->opcode))) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1934 | if (!lir->flags.is_nop) { |
| 1935 | offset += lir->flags.size; |
| 1936 | } |
| 1937 | } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { |
| 1938 | if (offset & 0x2) { |
| 1939 | offset += 2; |
| 1940 | lir->operands[0] = 1; |
| 1941 | } else { |
| 1942 | lir->operands[0] = 0; |
| 1943 | } |
| 1944 | } |
| 1945 | /* Pseudo opcodes don't consume space */ |
| 1946 | } |
| 1947 | return offset; |
| 1948 | } |
| 1949 | |
| 1950 | /* |
| 1951 | * Walk the compilation unit and assign offsets to instructions |
| 1952 | * and literals and compute the total size of the compiled unit. |
| 1953 | * TODO: consolidate w/ Arm assembly mechanism. |
| 1954 | */ |
| 1955 | void X86Mir2Lir::AssignOffsets() { |
| 1956 | int offset = AssignInsnOffsets(); |
| 1957 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1958 | if (const_vectors_ != nullptr) { |
| 1959 | /* assign offsets to vector literals */ |
| 1960 | |
| 1961 | // First, get offset to 12 mod 16 to align to 16 byte boundary. |
| 1962 | // This will ensure that the vector is 16 byte aligned, as the procedure is |
| 1963 | // always aligned at at 4 mod 16. |
| 1964 | int align_size = (16-4) - (offset & 0xF); |
| 1965 | if (align_size < 0) { |
| 1966 | align_size += 16; |
| 1967 | } |
| 1968 | |
| 1969 | offset += align_size; |
| 1970 | |
| 1971 | // Now assign each literal the right offset. |
| 1972 | for (LIR *p = const_vectors_; p != nullptr; p = p->next) { |
| 1973 | p->offset = offset; |
| 1974 | offset += 16; |
| 1975 | } |
| 1976 | } |
| 1977 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1978 | /* Const values have to be word aligned */ |
Andreas Gampe | 6601882 | 2014-05-05 20:47:19 -0700 | [diff] [blame] | 1979 | offset = RoundUp(offset, 4); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1980 | |
| 1981 | /* Set up offsets for literals */ |
| 1982 | data_offset_ = offset; |
| 1983 | |
| 1984 | offset = AssignLiteralOffset(offset); |
| 1985 | |
| 1986 | offset = AssignSwitchTablesOffset(offset); |
| 1987 | |
| 1988 | offset = AssignFillArrayDataOffset(offset); |
| 1989 | |
| 1990 | total_size_ = offset; |
| 1991 | } |
| 1992 | |
| 1993 | /* |
| 1994 | * Go over each instruction in the list and calculate the offset from the top |
| 1995 | * before sending them off to the assembler. If out-of-range branch distance is |
| 1996 | * seen rearrange the instructions a bit to correct it. |
| 1997 | * TODO: consolidate w/ Arm assembly mechanism. |
| 1998 | */ |
| 1999 | void X86Mir2Lir::AssembleLIR() { |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 2000 | cu_->NewTimingSplit("Assemble"); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 2001 | |
| 2002 | // We will remove the method address if we never ended up using it |
| 2003 | if (store_method_addr_ && !store_method_addr_used_) { |
| 2004 | setup_method_address_[0]->flags.is_nop = true; |
| 2005 | setup_method_address_[1]->flags.is_nop = true; |
| 2006 | } |
| 2007 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 2008 | AssignOffsets(); |
| 2009 | int assembler_retries = 0; |
| 2010 | /* |
| 2011 | * Assemble here. Note that we generate code with optimistic assumptions |
| 2012 | * and if found now to work, we'll have to redo the sequence and retry. |
| 2013 | */ |
| 2014 | |
| 2015 | while (true) { |
| 2016 | AssemblerStatus res = AssembleInstructions(0); |
| 2017 | if (res == kSuccess) { |
| 2018 | break; |
| 2019 | } else { |
| 2020 | assembler_retries++; |
| 2021 | if (assembler_retries > MAX_ASSEMBLER_RETRIES) { |
| 2022 | CodegenDump(); |
| 2023 | LOG(FATAL) << "Assembler error - too many retries"; |
| 2024 | } |
| 2025 | // Redo offsets and try again |
| 2026 | AssignOffsets(); |
| 2027 | code_buffer_.clear(); |
| 2028 | } |
| 2029 | } |
| 2030 | |
| 2031 | // Install literals |
| 2032 | InstallLiteralPools(); |
| 2033 | |
| 2034 | // Install switch tables |
| 2035 | InstallSwitchTables(); |
| 2036 | |
| 2037 | // Install fill array data |
| 2038 | InstallFillArrayData(); |
| 2039 | |
| 2040 | // Create the mapping table and native offset to reference map. |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 2041 | cu_->NewTimingSplit("PcMappingTable"); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 2042 | CreateMappingTables(); |
| 2043 | |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 2044 | cu_->NewTimingSplit("GcMap"); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 2045 | CreateNativeGcMap(); |
| 2046 | } |
| 2047 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2048 | } // namespace art |