Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 34 | #include <runtime_svc.h> |
| 35 | #include <debug.h> |
Dan Handley | 35e98e5 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 36 | #include "psci_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | |
| 38 | /******************************************************************************* |
| 39 | * PSCI frontend api for servicing SMCs. Described in the PSCI spec. |
| 40 | ******************************************************************************/ |
| 41 | int psci_cpu_on(unsigned long target_cpu, |
| 42 | unsigned long entrypoint, |
| 43 | unsigned long context_id) |
| 44 | |
| 45 | { |
| 46 | int rc; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 47 | unsigned int start_afflvl, end_afflvl; |
Soby Mathew | 78879b9 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 48 | entry_point_info_t ep; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 49 | |
| 50 | /* Determine if the cpu exists of not */ |
| 51 | rc = psci_validate_mpidr(target_cpu, MPIDR_AFFLVL0); |
| 52 | if (rc != PSCI_E_SUCCESS) { |
Soby Mathew | 539dced | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 53 | return PSCI_E_INVALID_PARAMS; |
| 54 | } |
| 55 | |
| 56 | /* Validate the entrypoint using platform pm_ops */ |
| 57 | if (psci_plat_pm_ops->validate_ns_entrypoint) { |
| 58 | rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); |
| 59 | if (rc != PSCI_E_SUCCESS) { |
| 60 | assert(rc == PSCI_E_INVALID_PARAMS); |
| 61 | return PSCI_E_INVALID_PARAMS; |
| 62 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 63 | } |
| 64 | |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 65 | /* |
Soby Mathew | 78879b9 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 66 | * Verify and derive the re-entry information for |
| 67 | * the non-secure world from the non-secure state from |
| 68 | * where this call originated. |
| 69 | */ |
| 70 | rc = psci_get_ns_ep_info(&ep, entrypoint, context_id); |
| 71 | if (rc != PSCI_E_SUCCESS) |
| 72 | return rc; |
| 73 | |
| 74 | |
| 75 | /* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 76 | * To turn this cpu on, specify which affinity |
| 77 | * levels need to be turned on |
| 78 | */ |
| 79 | start_afflvl = MPIDR_AFFLVL0; |
| 80 | end_afflvl = get_max_afflvl(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | rc = psci_afflvl_on(target_cpu, |
Soby Mathew | 78879b9 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 82 | &ep, |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | start_afflvl, |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 84 | end_afflvl); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 85 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 86 | return rc; |
| 87 | } |
| 88 | |
| 89 | unsigned int psci_version(void) |
| 90 | { |
| 91 | return PSCI_MAJOR_VER | PSCI_MINOR_VER; |
| 92 | } |
| 93 | |
| 94 | int psci_cpu_suspend(unsigned int power_state, |
| 95 | unsigned long entrypoint, |
| 96 | unsigned long context_id) |
| 97 | { |
| 98 | int rc; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 99 | unsigned int target_afflvl, pstate_type; |
Soby Mathew | 78879b9 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 100 | entry_point_info_t ep; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 101 | |
Vikram Kanigiri | 759ec93 | 2014-04-01 19:26:26 +0100 | [diff] [blame] | 102 | /* Check SBZ bits in power state are zero */ |
| 103 | if (psci_validate_power_state(power_state)) |
| 104 | return PSCI_E_INVALID_PARAMS; |
| 105 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 106 | /* Sanity check the requested state */ |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 107 | target_afflvl = psci_get_pstate_afflvl(power_state); |
Soby Mathew | 264999f | 2014-10-02 17:24:19 +0100 | [diff] [blame] | 108 | if (target_afflvl > get_max_afflvl()) |
Vikram Kanigiri | d118f9f | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 109 | return PSCI_E_INVALID_PARAMS; |
| 110 | |
Soby Mathew | 539dced | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 111 | /* Validate the power_state using platform pm_ops */ |
| 112 | if (psci_plat_pm_ops->validate_power_state) { |
| 113 | rc = psci_plat_pm_ops->validate_power_state(power_state); |
| 114 | if (rc != PSCI_E_SUCCESS) { |
| 115 | assert(rc == PSCI_E_INVALID_PARAMS); |
| 116 | return PSCI_E_INVALID_PARAMS; |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | /* Validate the entrypoint using platform pm_ops */ |
| 121 | if (psci_plat_pm_ops->validate_ns_entrypoint) { |
| 122 | rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); |
| 123 | if (rc != PSCI_E_SUCCESS) { |
| 124 | assert(rc == PSCI_E_INVALID_PARAMS); |
| 125 | return PSCI_E_INVALID_PARAMS; |
| 126 | } |
| 127 | } |
| 128 | |
Achin Gupta | 317ba09 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 129 | /* Determine the 'state type' in the 'power_state' parameter */ |
Vikram Kanigiri | d118f9f | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 130 | pstate_type = psci_get_pstate_type(power_state); |
Achin Gupta | 317ba09 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 131 | |
| 132 | /* |
| 133 | * Ensure that we have a platform specific handler for entering |
| 134 | * a standby state. |
| 135 | */ |
Vikram Kanigiri | d118f9f | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 136 | if (pstate_type == PSTATE_TYPE_STANDBY) { |
Achin Gupta | 317ba09 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 137 | if (!psci_plat_pm_ops->affinst_standby) |
Vikram Kanigiri | d118f9f | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 138 | return PSCI_E_INVALID_PARAMS; |
Achin Gupta | 317ba09 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 139 | |
Soby Mathew | 539dced | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 140 | psci_plat_pm_ops->affinst_standby(power_state); |
| 141 | return PSCI_E_SUCCESS; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 142 | } |
| 143 | |
Achin Gupta | 317ba09 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 144 | /* |
Soby Mathew | 78879b9 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 145 | * Verify and derive the re-entry information for |
| 146 | * the non-secure world from the non-secure state from |
| 147 | * where this call originated. |
| 148 | */ |
| 149 | rc = psci_get_ns_ep_info(&ep, entrypoint, context_id); |
| 150 | if (rc != PSCI_E_SUCCESS) |
| 151 | return rc; |
| 152 | |
Soby Mathew | 31244d7 | 2014-09-30 11:19:51 +0100 | [diff] [blame] | 153 | /* Save PSCI power state parameter for the core in suspend context */ |
| 154 | psci_set_suspend_power_state(power_state); |
| 155 | |
Soby Mathew | 78879b9 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 156 | /* |
Achin Gupta | 317ba09 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 157 | * Do what is needed to enter the power down state. Upon success, |
Soby Mathew | 539dced | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 158 | * enter the final wfi which will power down this CPU. |
Achin Gupta | 317ba09 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 159 | */ |
Soby Mathew | 539dced | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 160 | psci_afflvl_suspend(&ep, |
| 161 | MPIDR_AFFLVL0, |
| 162 | target_afflvl); |
| 163 | |
Soby Mathew | 31244d7 | 2014-09-30 11:19:51 +0100 | [diff] [blame] | 164 | /* Reset PSCI power state parameter for the core. */ |
| 165 | psci_set_suspend_power_state(PSCI_INVALID_DATA); |
Soby Mathew | 539dced | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 166 | return PSCI_E_SUCCESS; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | int psci_cpu_off(void) |
| 170 | { |
| 171 | int rc; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 172 | int target_afflvl = get_max_afflvl(); |
| 173 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 174 | /* |
| 175 | * Traverse from the highest to the lowest affinity level. When the |
| 176 | * lowest affinity level is hit, all the locks are acquired. State |
| 177 | * management is done immediately followed by cpu, cluster ... |
| 178 | * ..target_afflvl specific actions as this function unwinds back. |
| 179 | */ |
Andrew Thoelke | 56378aa | 2014-06-09 12:44:21 +0100 | [diff] [blame] | 180 | rc = psci_afflvl_off(MPIDR_AFFLVL0, target_afflvl); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 181 | |
Achin Gupta | 3140a9e | 2013-12-02 16:23:12 +0000 | [diff] [blame] | 182 | /* |
| 183 | * The only error cpu_off can return is E_DENIED. So check if that's |
| 184 | * indeed the case. |
| 185 | */ |
Achin Gupta | 317ba09 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 186 | assert (rc == PSCI_E_DENIED); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 187 | |
| 188 | return rc; |
| 189 | } |
| 190 | |
| 191 | int psci_affinity_info(unsigned long target_affinity, |
| 192 | unsigned int lowest_affinity_level) |
| 193 | { |
| 194 | int rc = PSCI_E_INVALID_PARAMS; |
| 195 | unsigned int aff_state; |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 196 | aff_map_node_t *node; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 197 | |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 198 | if (lowest_affinity_level > get_max_afflvl()) |
| 199 | return rc; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 200 | |
| 201 | node = psci_get_aff_map_node(target_affinity, lowest_affinity_level); |
| 202 | if (node && (node->state & PSCI_AFF_PRESENT)) { |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 203 | |
| 204 | /* |
| 205 | * TODO: For affinity levels higher than 0 i.e. cpu, the |
| 206 | * state will always be either ON or OFF. Need to investigate |
| 207 | * how critical is it to support ON_PENDING here. |
| 208 | */ |
| 209 | aff_state = psci_get_state(node); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 210 | |
| 211 | /* A suspended cpu is available & on for the OS */ |
| 212 | if (aff_state == PSCI_STATE_SUSPEND) { |
| 213 | aff_state = PSCI_STATE_ON; |
| 214 | } |
| 215 | |
| 216 | rc = aff_state; |
| 217 | } |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 218 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 219 | return rc; |
| 220 | } |
| 221 | |
Soby Mathew | 8991eed | 2014-10-23 10:35:34 +0100 | [diff] [blame^] | 222 | int psci_migrate(unsigned long target_cpu) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 223 | { |
Soby Mathew | 8991eed | 2014-10-23 10:35:34 +0100 | [diff] [blame^] | 224 | int rc; |
| 225 | unsigned long resident_cpu_mpidr; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 226 | |
Soby Mathew | 8991eed | 2014-10-23 10:35:34 +0100 | [diff] [blame^] | 227 | rc = psci_spd_migrate_info(&resident_cpu_mpidr); |
| 228 | if (rc != PSCI_TOS_UP_MIG_CAP) |
| 229 | return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? |
| 230 | PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 231 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 232 | /* |
Soby Mathew | 8991eed | 2014-10-23 10:35:34 +0100 | [diff] [blame^] | 233 | * Migrate should only be invoked on the CPU where |
| 234 | * the Secure OS is resident. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 235 | */ |
Soby Mathew | 8991eed | 2014-10-23 10:35:34 +0100 | [diff] [blame^] | 236 | if (resident_cpu_mpidr != read_mpidr_el1()) |
| 237 | return PSCI_E_NOT_PRESENT; |
| 238 | |
| 239 | /* Check the validity of the specified target cpu */ |
| 240 | rc = psci_validate_mpidr(target_cpu, MPIDR_AFFLVL0); |
| 241 | if (rc != PSCI_E_SUCCESS) |
| 242 | return PSCI_E_INVALID_PARAMS; |
| 243 | |
| 244 | assert(psci_spd_pm && psci_spd_pm->svc_migrate); |
| 245 | |
| 246 | rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); |
| 247 | assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); |
| 248 | |
| 249 | return rc; |
| 250 | } |
| 251 | |
| 252 | int psci_migrate_info_type(void) |
| 253 | { |
| 254 | unsigned long resident_cpu_mpidr; |
| 255 | |
| 256 | return psci_spd_migrate_info(&resident_cpu_mpidr); |
| 257 | } |
| 258 | |
| 259 | long psci_migrate_info_up_cpu(void) |
| 260 | { |
| 261 | unsigned long resident_cpu_mpidr; |
| 262 | int rc; |
| 263 | |
| 264 | /* |
| 265 | * Return value of this depends upon what |
| 266 | * psci_spd_migrate_info() returns. |
| 267 | */ |
| 268 | rc = psci_spd_migrate_info(&resident_cpu_mpidr); |
| 269 | if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP) |
| 270 | return PSCI_E_INVALID_PARAMS; |
| 271 | |
| 272 | return resident_cpu_mpidr; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 273 | } |
| 274 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 275 | /******************************************************************************* |
| 276 | * PSCI top level handler for servicing SMCs. |
| 277 | ******************************************************************************/ |
| 278 | uint64_t psci_smc_handler(uint32_t smc_fid, |
| 279 | uint64_t x1, |
| 280 | uint64_t x2, |
| 281 | uint64_t x3, |
| 282 | uint64_t x4, |
| 283 | void *cookie, |
| 284 | void *handle, |
| 285 | uint64_t flags) |
| 286 | { |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 287 | if (is_caller_secure(flags)) |
| 288 | SMC_RET1(handle, SMC_UNK); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 289 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 290 | if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { |
| 291 | /* 32-bit PSCI function, clear top parameter bits */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 292 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 293 | x1 = (uint32_t)x1; |
| 294 | x2 = (uint32_t)x2; |
| 295 | x3 = (uint32_t)x3; |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 296 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 297 | switch (smc_fid) { |
| 298 | case PSCI_VERSION: |
| 299 | SMC_RET1(handle, psci_version()); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 300 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 301 | case PSCI_CPU_OFF: |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 302 | SMC_RET1(handle, psci_cpu_off()); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 303 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 304 | case PSCI_CPU_SUSPEND_AARCH32: |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 305 | SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3)); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 306 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 307 | case PSCI_CPU_ON_AARCH32: |
| 308 | SMC_RET1(handle, psci_cpu_on(x1, x2, x3)); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 309 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 310 | case PSCI_AFFINITY_INFO_AARCH32: |
| 311 | SMC_RET1(handle, psci_affinity_info(x1, x2)); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 312 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 313 | case PSCI_MIG_AARCH32: |
| 314 | SMC_RET1(handle, psci_migrate(x1)); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 315 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 316 | case PSCI_MIG_INFO_TYPE: |
| 317 | SMC_RET1(handle, psci_migrate_info_type()); |
| 318 | |
| 319 | case PSCI_MIG_INFO_UP_CPU_AARCH32: |
| 320 | SMC_RET1(handle, psci_migrate_info_up_cpu()); |
| 321 | |
Juan Castillo | d5f1309 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 322 | case PSCI_SYSTEM_OFF: |
| 323 | psci_system_off(); |
| 324 | /* We should never return from psci_system_off() */ |
| 325 | |
| 326 | case PSCI_SYSTEM_RESET: |
| 327 | psci_system_reset(); |
| 328 | /* We should never return from psci_system_reset() */ |
| 329 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 330 | default: |
| 331 | break; |
| 332 | } |
| 333 | } else { |
| 334 | /* 64-bit PSCI function */ |
| 335 | |
| 336 | switch (smc_fid) { |
| 337 | case PSCI_CPU_SUSPEND_AARCH64: |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 338 | SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3)); |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 339 | |
| 340 | case PSCI_CPU_ON_AARCH64: |
| 341 | SMC_RET1(handle, psci_cpu_on(x1, x2, x3)); |
| 342 | |
| 343 | case PSCI_AFFINITY_INFO_AARCH64: |
| 344 | SMC_RET1(handle, psci_affinity_info(x1, x2)); |
| 345 | |
| 346 | case PSCI_MIG_AARCH64: |
| 347 | SMC_RET1(handle, psci_migrate(x1)); |
| 348 | |
| 349 | case PSCI_MIG_INFO_UP_CPU_AARCH64: |
| 350 | SMC_RET1(handle, psci_migrate_info_up_cpu()); |
| 351 | |
| 352 | default: |
| 353 | break; |
| 354 | } |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 355 | } |
| 356 | |
Andrew Thoelke | 5003eca | 2014-06-10 16:37:37 +0100 | [diff] [blame] | 357 | WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); |
| 358 | SMC_RET1(handle, SMC_UNK); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 359 | } |