Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 1 | /* Capstone Disassembly Engine */ |
Nguyen Anh Quynh | bfcaba5 | 2015-03-04 17:45:23 +0800 | [diff] [blame] | 2 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 3 | |
| 4 | #ifdef CAPSTONE_HAS_ARM64 |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 5 | |
| 6 | #include <stdio.h> // debug |
| 7 | #include <string.h> |
| 8 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 9 | #include "../../utils.h" |
| 10 | |
Nguyen Anh Quynh | 3732725 | 2014-01-20 09:47:21 +0800 | [diff] [blame] | 11 | #include "AArch64Mapping.h" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 12 | |
| 13 | #define GET_INSTRINFO_ENUM |
| 14 | #include "AArch64GenInstrInfo.inc" |
| 15 | |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 16 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 17 | static name_map reg_name_maps[] = { |
| 18 | { ARM64_REG_INVALID, NULL }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 19 | |
| 20 | { ARM64_REG_X29, "x29"}, |
| 21 | { ARM64_REG_X30, "x30"}, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 22 | { ARM64_REG_NZCV, "nzcv"}, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 23 | { ARM64_REG_SP, "sp"}, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 24 | { ARM64_REG_WSP, "wsp"}, |
Nguyen Anh Quynh | 1922b2f | 2014-05-18 10:30:09 +0800 | [diff] [blame] | 25 | { ARM64_REG_WZR, "wzr"}, |
Nguyen Anh Quynh | 1922b2f | 2014-05-18 10:30:09 +0800 | [diff] [blame] | 26 | { ARM64_REG_XZR, "xzr"}, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 27 | { ARM64_REG_B0, "b0"}, |
| 28 | { ARM64_REG_B1, "b1"}, |
| 29 | { ARM64_REG_B2, "b2"}, |
| 30 | { ARM64_REG_B3, "b3"}, |
| 31 | { ARM64_REG_B4, "b4"}, |
| 32 | { ARM64_REG_B5, "b5"}, |
| 33 | { ARM64_REG_B6, "b6"}, |
| 34 | { ARM64_REG_B7, "b7"}, |
| 35 | { ARM64_REG_B8, "b8"}, |
| 36 | { ARM64_REG_B9, "b9"}, |
| 37 | { ARM64_REG_B10, "b10"}, |
| 38 | { ARM64_REG_B11, "b11"}, |
| 39 | { ARM64_REG_B12, "b12"}, |
| 40 | { ARM64_REG_B13, "b13"}, |
| 41 | { ARM64_REG_B14, "b14"}, |
| 42 | { ARM64_REG_B15, "b15"}, |
| 43 | { ARM64_REG_B16, "b16"}, |
| 44 | { ARM64_REG_B17, "b17"}, |
| 45 | { ARM64_REG_B18, "b18"}, |
| 46 | { ARM64_REG_B19, "b19"}, |
| 47 | { ARM64_REG_B20, "b20"}, |
| 48 | { ARM64_REG_B21, "b21"}, |
| 49 | { ARM64_REG_B22, "b22"}, |
| 50 | { ARM64_REG_B23, "b23"}, |
| 51 | { ARM64_REG_B24, "b24"}, |
| 52 | { ARM64_REG_B25, "b25"}, |
| 53 | { ARM64_REG_B26, "b26"}, |
| 54 | { ARM64_REG_B27, "b27"}, |
| 55 | { ARM64_REG_B28, "b28"}, |
| 56 | { ARM64_REG_B29, "b29"}, |
| 57 | { ARM64_REG_B30, "b30"}, |
| 58 | { ARM64_REG_B31, "b31"}, |
| 59 | { ARM64_REG_D0, "d0"}, |
| 60 | { ARM64_REG_D1, "d1"}, |
| 61 | { ARM64_REG_D2, "d2"}, |
| 62 | { ARM64_REG_D3, "d3"}, |
| 63 | { ARM64_REG_D4, "d4"}, |
| 64 | { ARM64_REG_D5, "d5"}, |
| 65 | { ARM64_REG_D6, "d6"}, |
| 66 | { ARM64_REG_D7, "d7"}, |
| 67 | { ARM64_REG_D8, "d8"}, |
| 68 | { ARM64_REG_D9, "d9"}, |
| 69 | { ARM64_REG_D10, "d10"}, |
| 70 | { ARM64_REG_D11, "d11"}, |
| 71 | { ARM64_REG_D12, "d12"}, |
| 72 | { ARM64_REG_D13, "d13"}, |
| 73 | { ARM64_REG_D14, "d14"}, |
| 74 | { ARM64_REG_D15, "d15"}, |
| 75 | { ARM64_REG_D16, "d16"}, |
| 76 | { ARM64_REG_D17, "d17"}, |
| 77 | { ARM64_REG_D18, "d18"}, |
| 78 | { ARM64_REG_D19, "d19"}, |
| 79 | { ARM64_REG_D20, "d20"}, |
| 80 | { ARM64_REG_D21, "d21"}, |
| 81 | { ARM64_REG_D22, "d22"}, |
| 82 | { ARM64_REG_D23, "d23"}, |
| 83 | { ARM64_REG_D24, "d24"}, |
| 84 | { ARM64_REG_D25, "d25"}, |
| 85 | { ARM64_REG_D26, "d26"}, |
| 86 | { ARM64_REG_D27, "d27"}, |
| 87 | { ARM64_REG_D28, "d28"}, |
| 88 | { ARM64_REG_D29, "d29"}, |
| 89 | { ARM64_REG_D30, "d30"}, |
| 90 | { ARM64_REG_D31, "d31"}, |
| 91 | { ARM64_REG_H0, "h0"}, |
| 92 | { ARM64_REG_H1, "h1"}, |
| 93 | { ARM64_REG_H2, "h2"}, |
| 94 | { ARM64_REG_H3, "h3"}, |
| 95 | { ARM64_REG_H4, "h4"}, |
| 96 | { ARM64_REG_H5, "h5"}, |
| 97 | { ARM64_REG_H6, "h6"}, |
| 98 | { ARM64_REG_H7, "h7"}, |
| 99 | { ARM64_REG_H8, "h8"}, |
| 100 | { ARM64_REG_H9, "h9"}, |
| 101 | { ARM64_REG_H10, "h10"}, |
| 102 | { ARM64_REG_H11, "h11"}, |
| 103 | { ARM64_REG_H12, "h12"}, |
| 104 | { ARM64_REG_H13, "h13"}, |
| 105 | { ARM64_REG_H14, "h14"}, |
| 106 | { ARM64_REG_H15, "h15"}, |
| 107 | { ARM64_REG_H16, "h16"}, |
| 108 | { ARM64_REG_H17, "h17"}, |
| 109 | { ARM64_REG_H18, "h18"}, |
| 110 | { ARM64_REG_H19, "h19"}, |
| 111 | { ARM64_REG_H20, "h20"}, |
| 112 | { ARM64_REG_H21, "h21"}, |
| 113 | { ARM64_REG_H22, "h22"}, |
| 114 | { ARM64_REG_H23, "h23"}, |
| 115 | { ARM64_REG_H24, "h24"}, |
| 116 | { ARM64_REG_H25, "h25"}, |
| 117 | { ARM64_REG_H26, "h26"}, |
| 118 | { ARM64_REG_H27, "h27"}, |
| 119 | { ARM64_REG_H28, "h28"}, |
| 120 | { ARM64_REG_H29, "h29"}, |
| 121 | { ARM64_REG_H30, "h30"}, |
| 122 | { ARM64_REG_H31, "h31"}, |
| 123 | { ARM64_REG_Q0, "q0"}, |
| 124 | { ARM64_REG_Q1, "q1"}, |
| 125 | { ARM64_REG_Q2, "q2"}, |
| 126 | { ARM64_REG_Q3, "q3"}, |
| 127 | { ARM64_REG_Q4, "q4"}, |
| 128 | { ARM64_REG_Q5, "q5"}, |
| 129 | { ARM64_REG_Q6, "q6"}, |
| 130 | { ARM64_REG_Q7, "q7"}, |
| 131 | { ARM64_REG_Q8, "q8"}, |
| 132 | { ARM64_REG_Q9, "q9"}, |
| 133 | { ARM64_REG_Q10, "q10"}, |
| 134 | { ARM64_REG_Q11, "q11"}, |
| 135 | { ARM64_REG_Q12, "q12"}, |
| 136 | { ARM64_REG_Q13, "q13"}, |
| 137 | { ARM64_REG_Q14, "q14"}, |
| 138 | { ARM64_REG_Q15, "q15"}, |
| 139 | { ARM64_REG_Q16, "q16"}, |
| 140 | { ARM64_REG_Q17, "q17"}, |
| 141 | { ARM64_REG_Q18, "q18"}, |
| 142 | { ARM64_REG_Q19, "q19"}, |
| 143 | { ARM64_REG_Q20, "q20"}, |
| 144 | { ARM64_REG_Q21, "q21"}, |
| 145 | { ARM64_REG_Q22, "q22"}, |
| 146 | { ARM64_REG_Q23, "q23"}, |
| 147 | { ARM64_REG_Q24, "q24"}, |
| 148 | { ARM64_REG_Q25, "q25"}, |
| 149 | { ARM64_REG_Q26, "q26"}, |
| 150 | { ARM64_REG_Q27, "q27"}, |
| 151 | { ARM64_REG_Q28, "q28"}, |
| 152 | { ARM64_REG_Q29, "q29"}, |
| 153 | { ARM64_REG_Q30, "q30"}, |
| 154 | { ARM64_REG_Q31, "q31"}, |
| 155 | { ARM64_REG_S0, "s0"}, |
| 156 | { ARM64_REG_S1, "s1"}, |
| 157 | { ARM64_REG_S2, "s2"}, |
| 158 | { ARM64_REG_S3, "s3"}, |
| 159 | { ARM64_REG_S4, "s4"}, |
| 160 | { ARM64_REG_S5, "s5"}, |
| 161 | { ARM64_REG_S6, "s6"}, |
| 162 | { ARM64_REG_S7, "s7"}, |
| 163 | { ARM64_REG_S8, "s8"}, |
| 164 | { ARM64_REG_S9, "s9"}, |
| 165 | { ARM64_REG_S10, "s10"}, |
| 166 | { ARM64_REG_S11, "s11"}, |
| 167 | { ARM64_REG_S12, "s12"}, |
| 168 | { ARM64_REG_S13, "s13"}, |
| 169 | { ARM64_REG_S14, "s14"}, |
| 170 | { ARM64_REG_S15, "s15"}, |
| 171 | { ARM64_REG_S16, "s16"}, |
| 172 | { ARM64_REG_S17, "s17"}, |
| 173 | { ARM64_REG_S18, "s18"}, |
| 174 | { ARM64_REG_S19, "s19"}, |
| 175 | { ARM64_REG_S20, "s20"}, |
| 176 | { ARM64_REG_S21, "s21"}, |
| 177 | { ARM64_REG_S22, "s22"}, |
| 178 | { ARM64_REG_S23, "s23"}, |
| 179 | { ARM64_REG_S24, "s24"}, |
| 180 | { ARM64_REG_S25, "s25"}, |
| 181 | { ARM64_REG_S26, "s26"}, |
| 182 | { ARM64_REG_S27, "s27"}, |
| 183 | { ARM64_REG_S28, "s28"}, |
| 184 | { ARM64_REG_S29, "s29"}, |
| 185 | { ARM64_REG_S30, "s30"}, |
| 186 | { ARM64_REG_S31, "s31"}, |
| 187 | { ARM64_REG_W0, "w0"}, |
| 188 | { ARM64_REG_W1, "w1"}, |
| 189 | { ARM64_REG_W2, "w2"}, |
| 190 | { ARM64_REG_W3, "w3"}, |
| 191 | { ARM64_REG_W4, "w4"}, |
| 192 | { ARM64_REG_W5, "w5"}, |
| 193 | { ARM64_REG_W6, "w6"}, |
| 194 | { ARM64_REG_W7, "w7"}, |
| 195 | { ARM64_REG_W8, "w8"}, |
| 196 | { ARM64_REG_W9, "w9"}, |
| 197 | { ARM64_REG_W10, "w10"}, |
| 198 | { ARM64_REG_W11, "w11"}, |
| 199 | { ARM64_REG_W12, "w12"}, |
| 200 | { ARM64_REG_W13, "w13"}, |
| 201 | { ARM64_REG_W14, "w14"}, |
| 202 | { ARM64_REG_W15, "w15"}, |
| 203 | { ARM64_REG_W16, "w16"}, |
| 204 | { ARM64_REG_W17, "w17"}, |
| 205 | { ARM64_REG_W18, "w18"}, |
| 206 | { ARM64_REG_W19, "w19"}, |
| 207 | { ARM64_REG_W20, "w20"}, |
| 208 | { ARM64_REG_W21, "w21"}, |
| 209 | { ARM64_REG_W22, "w22"}, |
| 210 | { ARM64_REG_W23, "w23"}, |
| 211 | { ARM64_REG_W24, "w24"}, |
| 212 | { ARM64_REG_W25, "w25"}, |
| 213 | { ARM64_REG_W26, "w26"}, |
| 214 | { ARM64_REG_W27, "w27"}, |
| 215 | { ARM64_REG_W28, "w28"}, |
| 216 | { ARM64_REG_W29, "w29"}, |
| 217 | { ARM64_REG_W30, "w30"}, |
| 218 | { ARM64_REG_X0, "x0"}, |
| 219 | { ARM64_REG_X1, "x1"}, |
| 220 | { ARM64_REG_X2, "x2"}, |
| 221 | { ARM64_REG_X3, "x3"}, |
| 222 | { ARM64_REG_X4, "x4"}, |
| 223 | { ARM64_REG_X5, "x5"}, |
| 224 | { ARM64_REG_X6, "x6"}, |
| 225 | { ARM64_REG_X7, "x7"}, |
| 226 | { ARM64_REG_X8, "x8"}, |
| 227 | { ARM64_REG_X9, "x9"}, |
| 228 | { ARM64_REG_X10, "x10"}, |
| 229 | { ARM64_REG_X11, "x11"}, |
| 230 | { ARM64_REG_X12, "x12"}, |
| 231 | { ARM64_REG_X13, "x13"}, |
| 232 | { ARM64_REG_X14, "x14"}, |
| 233 | { ARM64_REG_X15, "x15"}, |
| 234 | { ARM64_REG_X16, "x16"}, |
| 235 | { ARM64_REG_X17, "x17"}, |
| 236 | { ARM64_REG_X18, "x18"}, |
| 237 | { ARM64_REG_X19, "x19"}, |
| 238 | { ARM64_REG_X20, "x20"}, |
| 239 | { ARM64_REG_X21, "x21"}, |
| 240 | { ARM64_REG_X22, "x22"}, |
| 241 | { ARM64_REG_X23, "x23"}, |
| 242 | { ARM64_REG_X24, "x24"}, |
| 243 | { ARM64_REG_X25, "x25"}, |
| 244 | { ARM64_REG_X26, "x26"}, |
| 245 | { ARM64_REG_X27, "x27"}, |
| 246 | { ARM64_REG_X28, "x28"}, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 247 | |
| 248 | { ARM64_REG_V0, "v0"}, |
| 249 | { ARM64_REG_V1, "v1"}, |
| 250 | { ARM64_REG_V2, "v2"}, |
| 251 | { ARM64_REG_V3, "v3"}, |
| 252 | { ARM64_REG_V4, "v4"}, |
| 253 | { ARM64_REG_V5, "v5"}, |
| 254 | { ARM64_REG_V6, "v6"}, |
| 255 | { ARM64_REG_V7, "v7"}, |
| 256 | { ARM64_REG_V8, "v8"}, |
| 257 | { ARM64_REG_V9, "v9"}, |
| 258 | { ARM64_REG_V10, "v10"}, |
| 259 | { ARM64_REG_V11, "v11"}, |
| 260 | { ARM64_REG_V12, "v12"}, |
| 261 | { ARM64_REG_V13, "v13"}, |
| 262 | { ARM64_REG_V14, "v14"}, |
| 263 | { ARM64_REG_V15, "v15"}, |
| 264 | { ARM64_REG_V16, "v16"}, |
| 265 | { ARM64_REG_V17, "v17"}, |
| 266 | { ARM64_REG_V18, "v18"}, |
| 267 | { ARM64_REG_V19, "v19"}, |
| 268 | { ARM64_REG_V20, "v20"}, |
| 269 | { ARM64_REG_V21, "v21"}, |
| 270 | { ARM64_REG_V22, "v22"}, |
| 271 | { ARM64_REG_V23, "v23"}, |
| 272 | { ARM64_REG_V24, "v24"}, |
| 273 | { ARM64_REG_V25, "v25"}, |
| 274 | { ARM64_REG_V26, "v26"}, |
| 275 | { ARM64_REG_V27, "v27"}, |
| 276 | { ARM64_REG_V28, "v28"}, |
| 277 | { ARM64_REG_V29, "v29"}, |
| 278 | { ARM64_REG_V30, "v30"}, |
| 279 | { ARM64_REG_V31, "v31"}, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 280 | }; |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 281 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 282 | |
pancake | f0e4eed | 2013-12-11 22:14:42 +0100 | [diff] [blame] | 283 | const char *AArch64_reg_name(csh handle, unsigned int reg) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 284 | { |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 285 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 286 | if (reg >= ARM64_REG_ENDING) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 287 | return NULL; |
| 288 | |
| 289 | return reg_name_maps[reg].name; |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 290 | #else |
| 291 | return NULL; |
| 292 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 293 | } |
| 294 | |
| 295 | static insn_map insns[] = { |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 296 | // dummy item |
| 297 | { |
| 298 | 0, 0, |
| 299 | #ifndef CAPSTONE_DIET |
| 300 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 301 | #endif |
| 302 | }, |
Nguyen Anh Quynh | b265406 | 2014-01-03 17:08:58 +0800 | [diff] [blame] | 303 | |
Nguyen Anh Quynh | bb5dcce | 2015-03-08 10:54:32 +0800 | [diff] [blame] | 304 | #include "AArch64MappingInsn.inc" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 305 | }; |
| 306 | |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 307 | // some alias instruction only need to be defined locally to satisfy |
| 308 | // some lookup functions |
| 309 | // just make sure these IDs never reuse any other IDs ARM_INS_* |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 310 | #define ARM64_INS_NEGS (unsigned short)-1 |
| 311 | #define ARM64_INS_NGCS (unsigned short)-2 |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 312 | |
Nguyen Anh Quynh | b265406 | 2014-01-03 17:08:58 +0800 | [diff] [blame] | 313 | // given internal insn id, return public instruction info |
Nguyen Anh Quynh | 1acfd0b | 2014-01-06 10:56:59 +0800 | [diff] [blame] | 314 | void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 315 | { |
Nguyen Anh Quynh | 1acfd0b | 2014-01-06 10:56:59 +0800 | [diff] [blame] | 316 | int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); |
Nguyen Anh Quynh | b265406 | 2014-01-03 17:08:58 +0800 | [diff] [blame] | 317 | if (i != 0) { |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 318 | insn->id = insns[i].mapid; |
Nguyen Anh Quynh | f35e2ad | 2013-12-03 11:10:26 +0800 | [diff] [blame] | 319 | |
Nguyen Anh Quynh | 1acfd0b | 2014-01-06 10:56:59 +0800 | [diff] [blame] | 320 | if (h->detail) { |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 321 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 322 | cs_struct handle; |
Nguyen Anh Quynh | 1acfd0b | 2014-01-06 10:56:59 +0800 | [diff] [blame] | 323 | handle.detail = h->detail; |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 324 | |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 325 | memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 326 | insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); |
Nguyen Anh Quynh | f35e2ad | 2013-12-03 11:10:26 +0800 | [diff] [blame] | 327 | |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 328 | memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 329 | insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); |
Nguyen Anh Quynh | f35e2ad | 2013-12-03 11:10:26 +0800 | [diff] [blame] | 330 | |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 331 | memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); |
Nguyen Anh Quynh | efffe78 | 2015-03-25 15:02:13 +0800 | [diff] [blame] | 332 | insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); |
Nguyen Anh Quynh | f35e2ad | 2013-12-03 11:10:26 +0800 | [diff] [blame] | 333 | |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 334 | insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV); |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 335 | #endif |
Nguyen Anh Quynh | ec0ed8e | 2013-12-02 13:55:38 +0800 | [diff] [blame] | 336 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 337 | } |
| 338 | } |
| 339 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 340 | static name_map insn_name_maps[] = { |
| 341 | { ARM64_INS_INVALID, NULL }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 342 | |
| 343 | { ARM64_INS_ABS, "abs" }, |
| 344 | { ARM64_INS_ADC, "adc" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 345 | { ARM64_INS_ADDHN, "addhn" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 346 | { ARM64_INS_ADDHN2, "addhn2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 347 | { ARM64_INS_ADDP, "addp" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 348 | { ARM64_INS_ADD, "add" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 349 | { ARM64_INS_ADDV, "addv" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 350 | { ARM64_INS_ADR, "adr" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 351 | { ARM64_INS_ADRP, "adrp" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 352 | { ARM64_INS_AESD, "aesd" }, |
| 353 | { ARM64_INS_AESE, "aese" }, |
| 354 | { ARM64_INS_AESIMC, "aesimc" }, |
| 355 | { ARM64_INS_AESMC, "aesmc" }, |
| 356 | { ARM64_INS_AND, "and" }, |
| 357 | { ARM64_INS_ASR, "asr" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 358 | { ARM64_INS_B, "b" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 359 | { ARM64_INS_BFM, "bfm" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 360 | { ARM64_INS_BIC, "bic" }, |
| 361 | { ARM64_INS_BIF, "bif" }, |
| 362 | { ARM64_INS_BIT, "bit" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 363 | { ARM64_INS_BL, "bl" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 364 | { ARM64_INS_BLR, "blr" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 365 | { ARM64_INS_BR, "br" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 366 | { ARM64_INS_BRK, "brk" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 367 | { ARM64_INS_BSL, "bsl" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 368 | { ARM64_INS_CBNZ, "cbnz" }, |
| 369 | { ARM64_INS_CBZ, "cbz" }, |
| 370 | { ARM64_INS_CCMN, "ccmn" }, |
| 371 | { ARM64_INS_CCMP, "ccmp" }, |
| 372 | { ARM64_INS_CLREX, "clrex" }, |
| 373 | { ARM64_INS_CLS, "cls" }, |
| 374 | { ARM64_INS_CLZ, "clz" }, |
| 375 | { ARM64_INS_CMEQ, "cmeq" }, |
| 376 | { ARM64_INS_CMGE, "cmge" }, |
| 377 | { ARM64_INS_CMGT, "cmgt" }, |
| 378 | { ARM64_INS_CMHI, "cmhi" }, |
| 379 | { ARM64_INS_CMHS, "cmhs" }, |
| 380 | { ARM64_INS_CMLE, "cmle" }, |
| 381 | { ARM64_INS_CMLT, "cmlt" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 382 | { ARM64_INS_CMTST, "cmtst" }, |
| 383 | { ARM64_INS_CNT, "cnt" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 384 | { ARM64_INS_MOV, "mov" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 385 | { ARM64_INS_CRC32B, "crc32b" }, |
| 386 | { ARM64_INS_CRC32CB, "crc32cb" }, |
| 387 | { ARM64_INS_CRC32CH, "crc32ch" }, |
| 388 | { ARM64_INS_CRC32CW, "crc32cw" }, |
| 389 | { ARM64_INS_CRC32CX, "crc32cx" }, |
| 390 | { ARM64_INS_CRC32H, "crc32h" }, |
| 391 | { ARM64_INS_CRC32W, "crc32w" }, |
| 392 | { ARM64_INS_CRC32X, "crc32x" }, |
| 393 | { ARM64_INS_CSEL, "csel" }, |
| 394 | { ARM64_INS_CSINC, "csinc" }, |
| 395 | { ARM64_INS_CSINV, "csinv" }, |
| 396 | { ARM64_INS_CSNEG, "csneg" }, |
| 397 | { ARM64_INS_DCPS1, "dcps1" }, |
| 398 | { ARM64_INS_DCPS2, "dcps2" }, |
| 399 | { ARM64_INS_DCPS3, "dcps3" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 400 | { ARM64_INS_DMB, "dmb" }, |
| 401 | { ARM64_INS_DRPS, "drps" }, |
| 402 | { ARM64_INS_DSB, "dsb" }, |
| 403 | { ARM64_INS_DUP, "dup" }, |
| 404 | { ARM64_INS_EON, "eon" }, |
| 405 | { ARM64_INS_EOR, "eor" }, |
| 406 | { ARM64_INS_ERET, "eret" }, |
| 407 | { ARM64_INS_EXTR, "extr" }, |
| 408 | { ARM64_INS_EXT, "ext" }, |
| 409 | { ARM64_INS_FABD, "fabd" }, |
| 410 | { ARM64_INS_FABS, "fabs" }, |
| 411 | { ARM64_INS_FACGE, "facge" }, |
| 412 | { ARM64_INS_FACGT, "facgt" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 413 | { ARM64_INS_FADD, "fadd" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 414 | { ARM64_INS_FADDP, "faddp" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 415 | { ARM64_INS_FCCMP, "fccmp" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 416 | { ARM64_INS_FCCMPE, "fccmpe" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 417 | { ARM64_INS_FCMEQ, "fcmeq" }, |
| 418 | { ARM64_INS_FCMGE, "fcmge" }, |
| 419 | { ARM64_INS_FCMGT, "fcmgt" }, |
| 420 | { ARM64_INS_FCMLE, "fcmle" }, |
| 421 | { ARM64_INS_FCMLT, "fcmlt" }, |
| 422 | { ARM64_INS_FCMP, "fcmp" }, |
| 423 | { ARM64_INS_FCMPE, "fcmpe" }, |
| 424 | { ARM64_INS_FCSEL, "fcsel" }, |
| 425 | { ARM64_INS_FCVTAS, "fcvtas" }, |
| 426 | { ARM64_INS_FCVTAU, "fcvtau" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 427 | { ARM64_INS_FCVT, "fcvt" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 428 | { ARM64_INS_FCVTL, "fcvtl" }, |
| 429 | { ARM64_INS_FCVTL2, "fcvtl2" }, |
| 430 | { ARM64_INS_FCVTMS, "fcvtms" }, |
| 431 | { ARM64_INS_FCVTMU, "fcvtmu" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 432 | { ARM64_INS_FCVTNS, "fcvtns" }, |
| 433 | { ARM64_INS_FCVTNU, "fcvtnu" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 434 | { ARM64_INS_FCVTN, "fcvtn" }, |
| 435 | { ARM64_INS_FCVTN2, "fcvtn2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 436 | { ARM64_INS_FCVTPS, "fcvtps" }, |
| 437 | { ARM64_INS_FCVTPU, "fcvtpu" }, |
| 438 | { ARM64_INS_FCVTXN, "fcvtxn" }, |
| 439 | { ARM64_INS_FCVTXN2, "fcvtxn2" }, |
| 440 | { ARM64_INS_FCVTZS, "fcvtzs" }, |
| 441 | { ARM64_INS_FCVTZU, "fcvtzu" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 442 | { ARM64_INS_FDIV, "fdiv" }, |
| 443 | { ARM64_INS_FMADD, "fmadd" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 444 | { ARM64_INS_FMAX, "fmax" }, |
| 445 | { ARM64_INS_FMAXNM, "fmaxnm" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 446 | { ARM64_INS_FMAXNMP, "fmaxnmp" }, |
| 447 | { ARM64_INS_FMAXNMV, "fmaxnmv" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 448 | { ARM64_INS_FMAXP, "fmaxp" }, |
| 449 | { ARM64_INS_FMAXV, "fmaxv" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 450 | { ARM64_INS_FMIN, "fmin" }, |
| 451 | { ARM64_INS_FMINNM, "fminnm" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 452 | { ARM64_INS_FMINNMP, "fminnmp" }, |
| 453 | { ARM64_INS_FMINNMV, "fminnmv" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 454 | { ARM64_INS_FMINP, "fminp" }, |
| 455 | { ARM64_INS_FMINV, "fminv" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 456 | { ARM64_INS_FMLA, "fmla" }, |
| 457 | { ARM64_INS_FMLS, "fmls" }, |
| 458 | { ARM64_INS_FMOV, "fmov" }, |
| 459 | { ARM64_INS_FMSUB, "fmsub" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 460 | { ARM64_INS_FMUL, "fmul" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 461 | { ARM64_INS_FMULX, "fmulx" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 462 | { ARM64_INS_FNEG, "fneg" }, |
| 463 | { ARM64_INS_FNMADD, "fnmadd" }, |
| 464 | { ARM64_INS_FNMSUB, "fnmsub" }, |
| 465 | { ARM64_INS_FNMUL, "fnmul" }, |
| 466 | { ARM64_INS_FRECPE, "frecpe" }, |
| 467 | { ARM64_INS_FRECPS, "frecps" }, |
| 468 | { ARM64_INS_FRECPX, "frecpx" }, |
| 469 | { ARM64_INS_FRINTA, "frinta" }, |
| 470 | { ARM64_INS_FRINTI, "frinti" }, |
| 471 | { ARM64_INS_FRINTM, "frintm" }, |
| 472 | { ARM64_INS_FRINTN, "frintn" }, |
| 473 | { ARM64_INS_FRINTP, "frintp" }, |
| 474 | { ARM64_INS_FRINTX, "frintx" }, |
| 475 | { ARM64_INS_FRINTZ, "frintz" }, |
| 476 | { ARM64_INS_FRSQRTE, "frsqrte" }, |
| 477 | { ARM64_INS_FRSQRTS, "frsqrts" }, |
| 478 | { ARM64_INS_FSQRT, "fsqrt" }, |
| 479 | { ARM64_INS_FSUB, "fsub" }, |
| 480 | { ARM64_INS_HINT, "hint" }, |
| 481 | { ARM64_INS_HLT, "hlt" }, |
| 482 | { ARM64_INS_HVC, "hvc" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 483 | { ARM64_INS_INS, "ins" }, |
| 484 | { ARM64_INS_ISB, "isb" }, |
| 485 | { ARM64_INS_LD1, "ld1" }, |
| 486 | { ARM64_INS_LD1R, "ld1r" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 487 | { ARM64_INS_LD2R, "ld2r" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 488 | { ARM64_INS_LD2, "ld2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 489 | { ARM64_INS_LD3R, "ld3r" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 490 | { ARM64_INS_LD3, "ld3" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 491 | { ARM64_INS_LD4, "ld4" }, |
| 492 | { ARM64_INS_LD4R, "ld4r" }, |
| 493 | { ARM64_INS_LDARB, "ldarb" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 494 | { ARM64_INS_LDARH, "ldarh" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 495 | { ARM64_INS_LDAR, "ldar" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 496 | { ARM64_INS_LDAXP, "ldaxp" }, |
| 497 | { ARM64_INS_LDAXRB, "ldaxrb" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 498 | { ARM64_INS_LDAXRH, "ldaxrh" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 499 | { ARM64_INS_LDAXR, "ldaxr" }, |
| 500 | { ARM64_INS_LDNP, "ldnp" }, |
| 501 | { ARM64_INS_LDP, "ldp" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 502 | { ARM64_INS_LDPSW, "ldpsw" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 503 | { ARM64_INS_LDRB, "ldrb" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 504 | { ARM64_INS_LDR, "ldr" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 505 | { ARM64_INS_LDRH, "ldrh" }, |
| 506 | { ARM64_INS_LDRSB, "ldrsb" }, |
| 507 | { ARM64_INS_LDRSH, "ldrsh" }, |
| 508 | { ARM64_INS_LDRSW, "ldrsw" }, |
| 509 | { ARM64_INS_LDTRB, "ldtrb" }, |
| 510 | { ARM64_INS_LDTRH, "ldtrh" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 511 | { ARM64_INS_LDTRSB, "ldtrsb" }, |
| 512 | { ARM64_INS_LDTRSH, "ldtrsh" }, |
| 513 | { ARM64_INS_LDTRSW, "ldtrsw" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 514 | { ARM64_INS_LDTR, "ldtr" }, |
| 515 | { ARM64_INS_LDURB, "ldurb" }, |
| 516 | { ARM64_INS_LDUR, "ldur" }, |
| 517 | { ARM64_INS_LDURH, "ldurh" }, |
| 518 | { ARM64_INS_LDURSB, "ldursb" }, |
| 519 | { ARM64_INS_LDURSH, "ldursh" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 520 | { ARM64_INS_LDURSW, "ldursw" }, |
| 521 | { ARM64_INS_LDXP, "ldxp" }, |
| 522 | { ARM64_INS_LDXRB, "ldxrb" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 523 | { ARM64_INS_LDXRH, "ldxrh" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 524 | { ARM64_INS_LDXR, "ldxr" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 525 | { ARM64_INS_LSL, "lsl" }, |
| 526 | { ARM64_INS_LSR, "lsr" }, |
| 527 | { ARM64_INS_MADD, "madd" }, |
| 528 | { ARM64_INS_MLA, "mla" }, |
| 529 | { ARM64_INS_MLS, "mls" }, |
| 530 | { ARM64_INS_MOVI, "movi" }, |
| 531 | { ARM64_INS_MOVK, "movk" }, |
| 532 | { ARM64_INS_MOVN, "movn" }, |
| 533 | { ARM64_INS_MOVZ, "movz" }, |
| 534 | { ARM64_INS_MRS, "mrs" }, |
| 535 | { ARM64_INS_MSR, "msr" }, |
| 536 | { ARM64_INS_MSUB, "msub" }, |
| 537 | { ARM64_INS_MUL, "mul" }, |
| 538 | { ARM64_INS_MVNI, "mvni" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 539 | { ARM64_INS_NEG, "neg" }, |
| 540 | { ARM64_INS_NOT, "not" }, |
| 541 | { ARM64_INS_ORN, "orn" }, |
| 542 | { ARM64_INS_ORR, "orr" }, |
| 543 | { ARM64_INS_PMULL2, "pmull2" }, |
| 544 | { ARM64_INS_PMULL, "pmull" }, |
| 545 | { ARM64_INS_PMUL, "pmul" }, |
| 546 | { ARM64_INS_PRFM, "prfm" }, |
| 547 | { ARM64_INS_PRFUM, "prfum" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 548 | { ARM64_INS_RADDHN, "raddhn" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 549 | { ARM64_INS_RADDHN2, "raddhn2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 550 | { ARM64_INS_RBIT, "rbit" }, |
| 551 | { ARM64_INS_RET, "ret" }, |
| 552 | { ARM64_INS_REV16, "rev16" }, |
| 553 | { ARM64_INS_REV32, "rev32" }, |
| 554 | { ARM64_INS_REV64, "rev64" }, |
| 555 | { ARM64_INS_REV, "rev" }, |
| 556 | { ARM64_INS_ROR, "ror" }, |
| 557 | { ARM64_INS_RSHRN2, "rshrn2" }, |
| 558 | { ARM64_INS_RSHRN, "rshrn" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 559 | { ARM64_INS_RSUBHN, "rsubhn" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 560 | { ARM64_INS_RSUBHN2, "rsubhn2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 561 | { ARM64_INS_SABAL2, "sabal2" }, |
| 562 | { ARM64_INS_SABAL, "sabal" }, |
| 563 | { ARM64_INS_SABA, "saba" }, |
| 564 | { ARM64_INS_SABDL2, "sabdl2" }, |
| 565 | { ARM64_INS_SABDL, "sabdl" }, |
| 566 | { ARM64_INS_SABD, "sabd" }, |
| 567 | { ARM64_INS_SADALP, "sadalp" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 568 | { ARM64_INS_SADDLP, "saddlp" }, |
| 569 | { ARM64_INS_SADDLV, "saddlv" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 570 | { ARM64_INS_SADDL2, "saddl2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 571 | { ARM64_INS_SADDL, "saddl" }, |
| 572 | { ARM64_INS_SADDW2, "saddw2" }, |
| 573 | { ARM64_INS_SADDW, "saddw" }, |
| 574 | { ARM64_INS_SBC, "sbc" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 575 | { ARM64_INS_SBFM, "sbfm" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 576 | { ARM64_INS_SCVTF, "scvtf" }, |
| 577 | { ARM64_INS_SDIV, "sdiv" }, |
| 578 | { ARM64_INS_SHA1C, "sha1c" }, |
| 579 | { ARM64_INS_SHA1H, "sha1h" }, |
| 580 | { ARM64_INS_SHA1M, "sha1m" }, |
| 581 | { ARM64_INS_SHA1P, "sha1p" }, |
| 582 | { ARM64_INS_SHA1SU0, "sha1su0" }, |
| 583 | { ARM64_INS_SHA1SU1, "sha1su1" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 584 | { ARM64_INS_SHA256H2, "sha256h2" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 585 | { ARM64_INS_SHA256H, "sha256h" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 586 | { ARM64_INS_SHA256SU0, "sha256su0" }, |
| 587 | { ARM64_INS_SHA256SU1, "sha256su1" }, |
| 588 | { ARM64_INS_SHADD, "shadd" }, |
| 589 | { ARM64_INS_SHLL2, "shll2" }, |
| 590 | { ARM64_INS_SHLL, "shll" }, |
| 591 | { ARM64_INS_SHL, "shl" }, |
| 592 | { ARM64_INS_SHRN2, "shrn2" }, |
| 593 | { ARM64_INS_SHRN, "shrn" }, |
| 594 | { ARM64_INS_SHSUB, "shsub" }, |
| 595 | { ARM64_INS_SLI, "sli" }, |
| 596 | { ARM64_INS_SMADDL, "smaddl" }, |
| 597 | { ARM64_INS_SMAXP, "smaxp" }, |
| 598 | { ARM64_INS_SMAXV, "smaxv" }, |
| 599 | { ARM64_INS_SMAX, "smax" }, |
| 600 | { ARM64_INS_SMC, "smc" }, |
| 601 | { ARM64_INS_SMINP, "sminp" }, |
| 602 | { ARM64_INS_SMINV, "sminv" }, |
| 603 | { ARM64_INS_SMIN, "smin" }, |
| 604 | { ARM64_INS_SMLAL2, "smlal2" }, |
| 605 | { ARM64_INS_SMLAL, "smlal" }, |
| 606 | { ARM64_INS_SMLSL2, "smlsl2" }, |
| 607 | { ARM64_INS_SMLSL, "smlsl" }, |
| 608 | { ARM64_INS_SMOV, "smov" }, |
| 609 | { ARM64_INS_SMSUBL, "smsubl" }, |
| 610 | { ARM64_INS_SMULH, "smulh" }, |
| 611 | { ARM64_INS_SMULL2, "smull2" }, |
| 612 | { ARM64_INS_SMULL, "smull" }, |
| 613 | { ARM64_INS_SQABS, "sqabs" }, |
| 614 | { ARM64_INS_SQADD, "sqadd" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 615 | { ARM64_INS_SQDMLAL, "sqdmlal" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 616 | { ARM64_INS_SQDMLAL2, "sqdmlal2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 617 | { ARM64_INS_SQDMLSL, "sqdmlsl" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 618 | { ARM64_INS_SQDMLSL2, "sqdmlsl2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 619 | { ARM64_INS_SQDMULH, "sqdmulh" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 620 | { ARM64_INS_SQDMULL, "sqdmull" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 621 | { ARM64_INS_SQDMULL2, "sqdmull2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 622 | { ARM64_INS_SQNEG, "sqneg" }, |
| 623 | { ARM64_INS_SQRDMULH, "sqrdmulh" }, |
| 624 | { ARM64_INS_SQRSHL, "sqrshl" }, |
| 625 | { ARM64_INS_SQRSHRN, "sqrshrn" }, |
| 626 | { ARM64_INS_SQRSHRN2, "sqrshrn2" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 627 | { ARM64_INS_SQRSHRUN, "sqrshrun" }, |
| 628 | { ARM64_INS_SQRSHRUN2, "sqrshrun2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 629 | { ARM64_INS_SQSHLU, "sqshlu" }, |
| 630 | { ARM64_INS_SQSHL, "sqshl" }, |
| 631 | { ARM64_INS_SQSHRN, "sqshrn" }, |
| 632 | { ARM64_INS_SQSHRN2, "sqshrn2" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 633 | { ARM64_INS_SQSHRUN, "sqshrun" }, |
| 634 | { ARM64_INS_SQSHRUN2, "sqshrun2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 635 | { ARM64_INS_SQSUB, "sqsub" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 636 | { ARM64_INS_SQXTN2, "sqxtn2" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 637 | { ARM64_INS_SQXTN, "sqxtn" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 638 | { ARM64_INS_SQXTUN2, "sqxtun2" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 639 | { ARM64_INS_SQXTUN, "sqxtun" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 640 | { ARM64_INS_SRHADD, "srhadd" }, |
| 641 | { ARM64_INS_SRI, "sri" }, |
| 642 | { ARM64_INS_SRSHL, "srshl" }, |
| 643 | { ARM64_INS_SRSHR, "srshr" }, |
| 644 | { ARM64_INS_SRSRA, "srsra" }, |
| 645 | { ARM64_INS_SSHLL2, "sshll2" }, |
| 646 | { ARM64_INS_SSHLL, "sshll" }, |
| 647 | { ARM64_INS_SSHL, "sshl" }, |
| 648 | { ARM64_INS_SSHR, "sshr" }, |
| 649 | { ARM64_INS_SSRA, "ssra" }, |
| 650 | { ARM64_INS_SSUBL2, "ssubl2" }, |
| 651 | { ARM64_INS_SSUBL, "ssubl" }, |
| 652 | { ARM64_INS_SSUBW2, "ssubw2" }, |
| 653 | { ARM64_INS_SSUBW, "ssubw" }, |
| 654 | { ARM64_INS_ST1, "st1" }, |
| 655 | { ARM64_INS_ST2, "st2" }, |
| 656 | { ARM64_INS_ST3, "st3" }, |
| 657 | { ARM64_INS_ST4, "st4" }, |
| 658 | { ARM64_INS_STLRB, "stlrb" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 659 | { ARM64_INS_STLRH, "stlrh" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 660 | { ARM64_INS_STLR, "stlr" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 661 | { ARM64_INS_STLXP, "stlxp" }, |
| 662 | { ARM64_INS_STLXRB, "stlxrb" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 663 | { ARM64_INS_STLXRH, "stlxrh" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 664 | { ARM64_INS_STLXR, "stlxr" }, |
| 665 | { ARM64_INS_STNP, "stnp" }, |
| 666 | { ARM64_INS_STP, "stp" }, |
| 667 | { ARM64_INS_STRB, "strb" }, |
| 668 | { ARM64_INS_STR, "str" }, |
| 669 | { ARM64_INS_STRH, "strh" }, |
| 670 | { ARM64_INS_STTRB, "sttrb" }, |
| 671 | { ARM64_INS_STTRH, "sttrh" }, |
| 672 | { ARM64_INS_STTR, "sttr" }, |
| 673 | { ARM64_INS_STURB, "sturb" }, |
| 674 | { ARM64_INS_STUR, "stur" }, |
| 675 | { ARM64_INS_STURH, "sturh" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 676 | { ARM64_INS_STXP, "stxp" }, |
| 677 | { ARM64_INS_STXRB, "stxrb" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 678 | { ARM64_INS_STXRH, "stxrh" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 679 | { ARM64_INS_STXR, "stxr" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 680 | { ARM64_INS_SUBHN, "subhn" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 681 | { ARM64_INS_SUBHN2, "subhn2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 682 | { ARM64_INS_SUB, "sub" }, |
| 683 | { ARM64_INS_SUQADD, "suqadd" }, |
| 684 | { ARM64_INS_SVC, "svc" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 685 | { ARM64_INS_SYSL, "sysl" }, |
| 686 | { ARM64_INS_SYS, "sys" }, |
| 687 | { ARM64_INS_TBL, "tbl" }, |
| 688 | { ARM64_INS_TBNZ, "tbnz" }, |
| 689 | { ARM64_INS_TBX, "tbx" }, |
| 690 | { ARM64_INS_TBZ, "tbz" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 691 | { ARM64_INS_TRN1, "trn1" }, |
| 692 | { ARM64_INS_TRN2, "trn2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 693 | { ARM64_INS_UABAL2, "uabal2" }, |
| 694 | { ARM64_INS_UABAL, "uabal" }, |
| 695 | { ARM64_INS_UABA, "uaba" }, |
| 696 | { ARM64_INS_UABDL2, "uabdl2" }, |
| 697 | { ARM64_INS_UABDL, "uabdl" }, |
| 698 | { ARM64_INS_UABD, "uabd" }, |
| 699 | { ARM64_INS_UADALP, "uadalp" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 700 | { ARM64_INS_UADDLP, "uaddlp" }, |
| 701 | { ARM64_INS_UADDLV, "uaddlv" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 702 | { ARM64_INS_UADDL2, "uaddl2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 703 | { ARM64_INS_UADDL, "uaddl" }, |
| 704 | { ARM64_INS_UADDW2, "uaddw2" }, |
| 705 | { ARM64_INS_UADDW, "uaddw" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 706 | { ARM64_INS_UBFM, "ubfm" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 707 | { ARM64_INS_UCVTF, "ucvtf" }, |
| 708 | { ARM64_INS_UDIV, "udiv" }, |
| 709 | { ARM64_INS_UHADD, "uhadd" }, |
| 710 | { ARM64_INS_UHSUB, "uhsub" }, |
| 711 | { ARM64_INS_UMADDL, "umaddl" }, |
| 712 | { ARM64_INS_UMAXP, "umaxp" }, |
| 713 | { ARM64_INS_UMAXV, "umaxv" }, |
| 714 | { ARM64_INS_UMAX, "umax" }, |
| 715 | { ARM64_INS_UMINP, "uminp" }, |
| 716 | { ARM64_INS_UMINV, "uminv" }, |
| 717 | { ARM64_INS_UMIN, "umin" }, |
| 718 | { ARM64_INS_UMLAL2, "umlal2" }, |
| 719 | { ARM64_INS_UMLAL, "umlal" }, |
| 720 | { ARM64_INS_UMLSL2, "umlsl2" }, |
| 721 | { ARM64_INS_UMLSL, "umlsl" }, |
| 722 | { ARM64_INS_UMOV, "umov" }, |
| 723 | { ARM64_INS_UMSUBL, "umsubl" }, |
| 724 | { ARM64_INS_UMULH, "umulh" }, |
| 725 | { ARM64_INS_UMULL2, "umull2" }, |
| 726 | { ARM64_INS_UMULL, "umull" }, |
| 727 | { ARM64_INS_UQADD, "uqadd" }, |
| 728 | { ARM64_INS_UQRSHL, "uqrshl" }, |
| 729 | { ARM64_INS_UQRSHRN, "uqrshrn" }, |
| 730 | { ARM64_INS_UQRSHRN2, "uqrshrn2" }, |
| 731 | { ARM64_INS_UQSHL, "uqshl" }, |
| 732 | { ARM64_INS_UQSHRN, "uqshrn" }, |
| 733 | { ARM64_INS_UQSHRN2, "uqshrn2" }, |
| 734 | { ARM64_INS_UQSUB, "uqsub" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 735 | { ARM64_INS_UQXTN2, "uqxtn2" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 736 | { ARM64_INS_UQXTN, "uqxtn" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 737 | { ARM64_INS_URECPE, "urecpe" }, |
| 738 | { ARM64_INS_URHADD, "urhadd" }, |
| 739 | { ARM64_INS_URSHL, "urshl" }, |
| 740 | { ARM64_INS_URSHR, "urshr" }, |
| 741 | { ARM64_INS_URSQRTE, "ursqrte" }, |
| 742 | { ARM64_INS_URSRA, "ursra" }, |
| 743 | { ARM64_INS_USHLL2, "ushll2" }, |
| 744 | { ARM64_INS_USHLL, "ushll" }, |
| 745 | { ARM64_INS_USHL, "ushl" }, |
| 746 | { ARM64_INS_USHR, "ushr" }, |
| 747 | { ARM64_INS_USQADD, "usqadd" }, |
| 748 | { ARM64_INS_USRA, "usra" }, |
| 749 | { ARM64_INS_USUBL2, "usubl2" }, |
| 750 | { ARM64_INS_USUBL, "usubl" }, |
| 751 | { ARM64_INS_USUBW2, "usubw2" }, |
| 752 | { ARM64_INS_USUBW, "usubw" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 753 | { ARM64_INS_UZP1, "uzp1" }, |
| 754 | { ARM64_INS_UZP2, "uzp2" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 755 | { ARM64_INS_XTN2, "xtn2" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 756 | { ARM64_INS_XTN, "xtn" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 757 | { ARM64_INS_ZIP1, "zip1" }, |
| 758 | { ARM64_INS_ZIP2, "zip2" }, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 759 | }; |
| 760 | |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 761 | // map *S & alias instructions back to original id |
| 762 | static name_map alias_insn_name_maps[] = { |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 763 | { ARM64_INS_ADC, "adcs" }, |
| 764 | { ARM64_INS_AND, "ands" }, |
| 765 | { ARM64_INS_ADD, "adds" }, |
| 766 | { ARM64_INS_BIC, "bics" }, |
| 767 | { ARM64_INS_SBC, "sbcs" }, |
| 768 | { ARM64_INS_SUB, "subs" }, |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 769 | |
| 770 | // alias insn |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 771 | { ARM64_INS_MNEG, "mneg" }, |
| 772 | { ARM64_INS_UMNEGL, "umnegl" }, |
| 773 | { ARM64_INS_SMNEGL, "smnegl" }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 774 | { ARM64_INS_NOP, "nop" }, |
| 775 | { ARM64_INS_YIELD, "yield" }, |
| 776 | { ARM64_INS_WFE, "wfe" }, |
| 777 | { ARM64_INS_WFI, "wfi" }, |
| 778 | { ARM64_INS_SEV, "sev" }, |
| 779 | { ARM64_INS_SEVL, "sevl" }, |
| 780 | { ARM64_INS_NGC, "ngc" }, |
| 781 | { ARM64_INS_NGCS, "ngcs" }, |
| 782 | { ARM64_INS_NEGS, "negs" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 783 | |
| 784 | { ARM64_INS_SBFIZ, "sbfiz" }, |
| 785 | { ARM64_INS_UBFIZ, "ubfiz" }, |
| 786 | { ARM64_INS_SBFX, "sbfx" }, |
| 787 | { ARM64_INS_UBFX, "ubfx" }, |
| 788 | { ARM64_INS_BFI, "bfi" }, |
| 789 | { ARM64_INS_BFXIL, "bfxil" }, |
| 790 | { ARM64_INS_CMN, "cmn" }, |
| 791 | { ARM64_INS_MVN, "mvn" }, |
| 792 | { ARM64_INS_TST, "tst" }, |
| 793 | { ARM64_INS_CSET, "cset" }, |
| 794 | { ARM64_INS_CINC, "cinc" }, |
| 795 | { ARM64_INS_CSETM, "csetm" }, |
| 796 | { ARM64_INS_CINV, "cinv" }, |
| 797 | { ARM64_INS_CNEG, "cneg" }, |
| 798 | { ARM64_INS_SXTB, "sxtb" }, |
| 799 | { ARM64_INS_SXTH, "sxth" }, |
| 800 | { ARM64_INS_SXTW, "sxtw" }, |
| 801 | { ARM64_INS_CMP, "cmp" }, |
| 802 | { ARM64_INS_UXTB, "uxtb" }, |
| 803 | { ARM64_INS_UXTH, "uxth" }, |
| 804 | { ARM64_INS_UXTW, "uxtw" }, |
| 805 | |
| 806 | { ARM64_INS_IC, "ic" }, |
| 807 | { ARM64_INS_DC, "dc" }, |
| 808 | { ARM64_INS_AT, "at" }, |
| 809 | { ARM64_INS_TLBI, "tlbi" }, |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 810 | }; |
| 811 | |
pancake | f0e4eed | 2013-12-11 22:14:42 +0100 | [diff] [blame] | 812 | const char *AArch64_insn_name(csh handle, unsigned int id) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 813 | { |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 814 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | f6c7cbc | 2014-03-12 12:50:54 +0800 | [diff] [blame] | 815 | unsigned int i; |
| 816 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 817 | if (id >= ARM64_INS_ENDING) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 818 | return NULL; |
| 819 | |
Nguyen Anh Quynh | dcbe0f8 | 2014-01-12 10:11:36 +0800 | [diff] [blame] | 820 | if (id < ARR_SIZE(insn_name_maps)) |
| 821 | return insn_name_maps[id].name; |
| 822 | |
| 823 | // then find alias insn |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 824 | for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { |
| 825 | if (alias_insn_name_maps[i].id == id) |
| 826 | return alias_insn_name_maps[i].name; |
| 827 | } |
| 828 | |
Nguyen Anh Quynh | dcbe0f8 | 2014-01-12 10:11:36 +0800 | [diff] [blame] | 829 | // not found |
| 830 | return NULL; |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 831 | #else |
| 832 | return NULL; |
| 833 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 834 | } |
| 835 | |
Nguyen Anh Quynh | 650f96c | 2014-07-08 08:59:27 +0800 | [diff] [blame] | 836 | #ifndef CAPSTONE_DIET |
| 837 | static name_map group_name_maps[] = { |
Nguyen Anh Quynh | c2ea812 | 2014-10-31 15:36:19 +0800 | [diff] [blame] | 838 | // generic groups |
Nguyen Anh Quynh | 650f96c | 2014-07-08 08:59:27 +0800 | [diff] [blame] | 839 | { ARM64_GRP_INVALID, NULL }, |
Nguyen Anh Quynh | c2ea812 | 2014-10-31 15:36:19 +0800 | [diff] [blame] | 840 | { ARM64_GRP_JUMP, "jump" }, |
David Callahan | 9092e52 | 2015-03-15 18:01:48 -0700 | [diff] [blame] | 841 | { ARM64_GRP_CALL, "call" }, |
| 842 | { ARM64_GRP_RET, "return" }, |
Nguyen Anh Quynh | 1182d25 | 2015-04-27 12:13:34 +0800 | [diff] [blame] | 843 | { ARM64_GRP_PRIVILEGE, "privilege" }, |
Zach Riggle | 1e882cf | 2015-07-27 12:41:57 -0400 | [diff] [blame] | 844 | { ARM64_GRP_INT, "int" }, |
Nguyen Anh Quynh | c2ea812 | 2014-10-31 15:36:19 +0800 | [diff] [blame] | 845 | |
| 846 | // architecture-specific groups |
Nguyen Anh Quynh | 650f96c | 2014-07-08 08:59:27 +0800 | [diff] [blame] | 847 | { ARM64_GRP_CRYPTO, "crypto" }, |
| 848 | { ARM64_GRP_FPARMV8, "fparmv8" }, |
| 849 | { ARM64_GRP_NEON, "neon" }, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 850 | { ARM64_GRP_CRC, "crc" }, |
Nguyen Anh Quynh | 650f96c | 2014-07-08 08:59:27 +0800 | [diff] [blame] | 851 | }; |
| 852 | #endif |
| 853 | |
| 854 | const char *AArch64_group_name(csh handle, unsigned int id) |
| 855 | { |
| 856 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | 1182d25 | 2015-04-27 12:13:34 +0800 | [diff] [blame] | 857 | return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); |
Nguyen Anh Quynh | 650f96c | 2014-07-08 08:59:27 +0800 | [diff] [blame] | 858 | #else |
| 859 | return NULL; |
| 860 | #endif |
| 861 | } |
| 862 | |
Nguyen Anh Quynh | 6b7abe3 | 2013-11-30 00:54:24 +0800 | [diff] [blame] | 863 | // map instruction name to public instruction ID |
pancake | f0e4eed | 2013-12-11 22:14:42 +0100 | [diff] [blame] | 864 | arm64_reg AArch64_map_insn(const char *name) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 865 | { |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 866 | // NOTE: skip first NULL name in insn_name_maps |
| 867 | int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); |
| 868 | |
| 869 | if (i == -1) |
| 870 | // try again with 'special' insn that is not available in insn_name_maps |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 871 | i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 872 | |
| 873 | return (i != -1)? i : ARM64_REG_INVALID; |
| 874 | } |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 875 | |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 876 | // map internal raw vregister to 'public' register |
| 877 | arm64_reg AArch64_map_vregister(unsigned int r) |
| 878 | { |
| 879 | // for some reasons different Arm64 can map different register number to |
| 880 | // the same register. this function handles the issue for exposing Mips |
| 881 | // operands by mapping internal registers to 'public' register. |
| 882 | unsigned int map[] = { 0, |
| 883 | 0, 0, 0, 0, 0, |
| 884 | 0, 0, 0, 0, 0, |
| 885 | 0, 0, 0, 0, 0, |
| 886 | 0, 0, 0, 0, 0, |
| 887 | 0, 0, 0, 0, 0, |
| 888 | 0, 0, 0, 0, 0, |
| 889 | 0, 0, 0, 0, 0, |
| 890 | 0, 0, 0, 0, ARM64_REG_V0, |
| 891 | ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, |
| 892 | ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, |
| 893 | ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, |
| 894 | ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, |
| 895 | ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, |
| 896 | ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, |
| 897 | ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 898 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 899 | 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1, |
| 900 | ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, |
| 901 | ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, |
| 902 | ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, |
| 903 | ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, |
| 904 | ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, |
| 905 | ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, |
| 906 | 0, 0, 0, 0, 0, |
| 907 | 0, 0, 0, 0, 0, |
| 908 | 0, 0, 0, 0, 0, |
| 909 | 0, 0, 0, 0, 0, |
| 910 | 0, 0, 0, 0, 0, |
| 911 | 0, 0, 0, 0, 0, |
| 912 | 0, 0, 0, 0, 0, |
| 913 | 0, 0, 0, 0, 0, |
| 914 | 0, 0, 0, 0, 0, |
| 915 | 0, 0, 0, 0, 0, |
| 916 | 0, 0, 0, 0, 0, |
| 917 | 0, 0, 0, 0, 0, |
| 918 | 0, 0, 0, 0, 0, |
| 919 | 0, 0, 0, 0, 0, |
| 920 | 0, 0, 0, 0, 0, |
| 921 | 0, 0, 0, 0, 0, |
| 922 | 0, 0, 0, 0, 0, |
| 923 | 0, 0, 0, 0, 0, |
| 924 | 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, |
| 925 | ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, |
| 926 | ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, |
| 927 | ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, |
| 928 | ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, |
| 929 | ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, |
| 930 | ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, |
| 931 | ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, |
| 932 | ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, |
| 933 | ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, |
| 934 | ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, |
| 935 | ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, |
| 936 | ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, |
| 937 | ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, |
| 938 | ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, |
| 939 | ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, |
| 940 | ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, |
| 941 | ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, |
| 942 | ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, |
| 943 | ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, |
| 944 | ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, |
| 945 | ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, |
| 946 | ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, |
| 947 | ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, |
| 948 | ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, |
| 949 | ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, |
| 950 | ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, |
| 951 | ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, |
| 952 | ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, |
| 953 | ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, |
| 954 | ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, |
| 955 | ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, |
| 956 | ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, |
| 957 | ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, |
| 958 | ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, |
| 959 | ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, |
| 960 | ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, |
| 961 | ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, |
| 962 | ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, }; |
| 963 | |
| 964 | if (r < ARR_SIZE(map)) |
| 965 | return map[r]; |
| 966 | |
| 967 | // cannot find this register |
| 968 | return 0; |
| 969 | } |
| 970 | |
| 971 | void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp) |
| 972 | { |
| 973 | if (MI->csh->detail) { |
| 974 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp; |
| 975 | } |
| 976 | } |
| 977 | |
| 978 | void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp) |
| 979 | { |
| 980 | if (MI->csh->detail) { |
| 981 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vess = sp; |
| 982 | } |
| 983 | } |
| 984 | |
| 985 | void arm64_op_addFP(MCInst *MI, float fp) |
| 986 | { |
| 987 | if (MI->csh->detail) { |
| 988 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; |
| 989 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp; |
| 990 | MI->flat_insn->detail->arm64.op_count++; |
| 991 | } |
| 992 | } |
| 993 | |
| 994 | void arm64_op_addImm(MCInst *MI, int64_t imm) |
| 995 | { |
| 996 | if (MI->csh->detail) { |
| 997 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
Nguyen Anh Quynh | 4b6b15f | 2014-08-26 15:57:04 +0800 | [diff] [blame] | 998 | MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm; |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 999 | MI->flat_insn->detail->arm64.op_count++; |
| 1000 | } |
| 1001 | } |
| 1002 | |
Pranith Kumar | 653827b | 2016-01-06 15:52:12 -0400 | [diff] [blame] | 1003 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | e8eb536 | 2015-02-23 11:35:35 +0800 | [diff] [blame] | 1004 | |
Nguyen Anh Quynh | e8eb536 | 2015-02-23 11:35:35 +0800 | [diff] [blame] | 1005 | // map instruction to its characteristics |
| 1006 | typedef struct insn_op { |
| 1007 | unsigned int eflags_update; // how this instruction update status flags |
Nguyen Anh Quynh | aab7f63 | 2016-01-22 22:25:49 +0800 | [diff] [blame] | 1008 | uint8_t access[5]; |
Nguyen Anh Quynh | e8eb536 | 2015-02-23 11:35:35 +0800 | [diff] [blame] | 1009 | } insn_op; |
| 1010 | |
Nguyen Anh Quynh | ed6d75a | 2015-02-24 22:03:28 +0800 | [diff] [blame] | 1011 | static insn_op insn_ops[] = { |
Pranith Kumar | 653827b | 2016-01-06 15:52:12 -0400 | [diff] [blame] | 1012 | { |
| 1013 | /* NULL item */ |
| 1014 | 0, { 0 } |
| 1015 | }, |
| 1016 | |
| 1017 | #include "AArch64MappingInsnOp.inc" |
Nguyen Anh Quynh | ed6d75a | 2015-02-24 22:03:28 +0800 | [diff] [blame] | 1018 | }; |
Pranith Kumar | 653827b | 2016-01-06 15:52:12 -0400 | [diff] [blame] | 1019 | |
| 1020 | // given internal insn id, return operand access info |
Nguyen Anh Quynh | aab7f63 | 2016-01-22 22:25:49 +0800 | [diff] [blame] | 1021 | uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id) |
Pranith Kumar | 653827b | 2016-01-06 15:52:12 -0400 | [diff] [blame] | 1022 | { |
| 1023 | int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); |
| 1024 | if (i != 0) { |
Nguyen Anh Quynh | aab7f63 | 2016-01-22 22:25:49 +0800 | [diff] [blame] | 1025 | return insn_ops[i].access; |
Pranith Kumar | 653827b | 2016-01-06 15:52:12 -0400 | [diff] [blame] | 1026 | } |
| 1027 | |
| 1028 | return NULL; |
| 1029 | } |
| 1030 | |
| 1031 | void AArch64_reg_access(const cs_insn *insn, |
| 1032 | cs_regs regs_read, uint8_t *regs_read_count, |
| 1033 | cs_regs regs_write, uint8_t *regs_write_count) |
| 1034 | { |
| 1035 | uint8_t i; |
| 1036 | uint8_t read_count, write_count; |
| 1037 | cs_arm64 *arm64 = &(insn->detail->arm64); |
| 1038 | |
| 1039 | read_count = insn->detail->regs_read_count; |
| 1040 | write_count = insn->detail->regs_write_count; |
| 1041 | |
| 1042 | // implicit registers |
| 1043 | memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); |
| 1044 | memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); |
| 1045 | |
| 1046 | // explicit registers |
| 1047 | for (i = 0; i < arm64->op_count; i++) { |
| 1048 | cs_arm64_op *op = &(arm64->operands[i]); |
| 1049 | switch((int)op->type) { |
| 1050 | case ARM64_OP_REG: |
| 1051 | if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { |
| 1052 | regs_read[read_count] = op->reg; |
| 1053 | read_count++; |
| 1054 | } |
| 1055 | if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { |
| 1056 | regs_write[write_count] = op->reg; |
| 1057 | write_count++; |
| 1058 | } |
| 1059 | break; |
| 1060 | case ARM_OP_MEM: |
| 1061 | // registers appeared in memory references always being read |
| 1062 | if ((op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { |
| 1063 | regs_read[read_count] = op->mem.base; |
| 1064 | read_count++; |
| 1065 | } |
| 1066 | if ((op->mem.index != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { |
| 1067 | regs_read[read_count] = op->mem.index; |
| 1068 | read_count++; |
| 1069 | } |
| 1070 | if ((arm64->writeback) && (op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) { |
| 1071 | regs_write[write_count] = op->mem.base; |
| 1072 | write_count++; |
| 1073 | } |
| 1074 | default: |
| 1075 | break; |
| 1076 | } |
| 1077 | } |
| 1078 | |
| 1079 | *regs_read_count = read_count; |
| 1080 | *regs_write_count = write_count; |
| 1081 | } |
Nguyen Anh Quynh | e8eb536 | 2015-02-23 11:35:35 +0800 | [diff] [blame] | 1082 | #endif |
Nguyen Anh Quynh | ed6d75a | 2015-02-24 22:03:28 +0800 | [diff] [blame] | 1083 | |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 1084 | #endif |