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gerrit-public.fairphone.software / platform / external / capstone / bb5dccedfad5ca9f9a40db98f656f31505bdf8e1 / . / arch / AArch64 / AArch64Mapping.c
blob: b5eed138cf02c6c18a27b1cd4009e4814079bc9f [file] [log] [blame]
Nguyen Anh Quynh8598a212014-05-14 11:26:41 +0800[diff] [blame]1/* Capstone Disassembly Engine */
Nguyen Anh Quynhbfcaba52015-03-04 17:45:23 +0800[diff] [blame]2/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
Nguyen Anh Quynh8598a212014-05-14 11:26:41 +0800[diff] [blame]3
4#ifdef CAPSTONE_HAS_ARM64
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]5
6#include <stdio.h> // debug
7#include <string.h>
8
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]9#include "../../utils.h"
10
Nguyen Anh Quynh37327252014-01-20 09:47:21 +0800[diff] [blame]11#include "AArch64Mapping.h"
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]12
13#define GET_INSTRINFO_ENUM
14#include "AArch64GenInstrInfo.inc"
15
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]16#ifndef CAPSTONE_DIET
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]17static name_map reg_name_maps[] = {
18 { ARM64_REG_INVALID, NULL },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]19
20 { ARM64_REG_X29, "x29"},
21 { ARM64_REG_X30, "x30"},
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]22 { ARM64_REG_NZCV, "nzcv"},
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]23 { ARM64_REG_SP, "sp"},
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]24 { ARM64_REG_WSP, "wsp"},
Nguyen Anh Quynh1922b2f2014-05-18 10:30:09 +0800[diff] [blame]25 { ARM64_REG_WZR, "wzr"},
Nguyen Anh Quynh1922b2f2014-05-18 10:30:09 +0800[diff] [blame]26 { ARM64_REG_XZR, "xzr"},
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]27 { ARM64_REG_B0, "b0"},
28 { ARM64_REG_B1, "b1"},
29 { ARM64_REG_B2, "b2"},
30 { ARM64_REG_B3, "b3"},
31 { ARM64_REG_B4, "b4"},
32 { ARM64_REG_B5, "b5"},
33 { ARM64_REG_B6, "b6"},
34 { ARM64_REG_B7, "b7"},
35 { ARM64_REG_B8, "b8"},
36 { ARM64_REG_B9, "b9"},
37 { ARM64_REG_B10, "b10"},
38 { ARM64_REG_B11, "b11"},
39 { ARM64_REG_B12, "b12"},
40 { ARM64_REG_B13, "b13"},
41 { ARM64_REG_B14, "b14"},
42 { ARM64_REG_B15, "b15"},
43 { ARM64_REG_B16, "b16"},
44 { ARM64_REG_B17, "b17"},
45 { ARM64_REG_B18, "b18"},
46 { ARM64_REG_B19, "b19"},
47 { ARM64_REG_B20, "b20"},
48 { ARM64_REG_B21, "b21"},
49 { ARM64_REG_B22, "b22"},
50 { ARM64_REG_B23, "b23"},
51 { ARM64_REG_B24, "b24"},
52 { ARM64_REG_B25, "b25"},
53 { ARM64_REG_B26, "b26"},
54 { ARM64_REG_B27, "b27"},
55 { ARM64_REG_B28, "b28"},
56 { ARM64_REG_B29, "b29"},
57 { ARM64_REG_B30, "b30"},
58 { ARM64_REG_B31, "b31"},
59 { ARM64_REG_D0, "d0"},
60 { ARM64_REG_D1, "d1"},
61 { ARM64_REG_D2, "d2"},
62 { ARM64_REG_D3, "d3"},
63 { ARM64_REG_D4, "d4"},
64 { ARM64_REG_D5, "d5"},
65 { ARM64_REG_D6, "d6"},
66 { ARM64_REG_D7, "d7"},
67 { ARM64_REG_D8, "d8"},
68 { ARM64_REG_D9, "d9"},
69 { ARM64_REG_D10, "d10"},
70 { ARM64_REG_D11, "d11"},
71 { ARM64_REG_D12, "d12"},
72 { ARM64_REG_D13, "d13"},
73 { ARM64_REG_D14, "d14"},
74 { ARM64_REG_D15, "d15"},
75 { ARM64_REG_D16, "d16"},
76 { ARM64_REG_D17, "d17"},
77 { ARM64_REG_D18, "d18"},
78 { ARM64_REG_D19, "d19"},
79 { ARM64_REG_D20, "d20"},
80 { ARM64_REG_D21, "d21"},
81 { ARM64_REG_D22, "d22"},
82 { ARM64_REG_D23, "d23"},
83 { ARM64_REG_D24, "d24"},
84 { ARM64_REG_D25, "d25"},
85 { ARM64_REG_D26, "d26"},
86 { ARM64_REG_D27, "d27"},
87 { ARM64_REG_D28, "d28"},
88 { ARM64_REG_D29, "d29"},
89 { ARM64_REG_D30, "d30"},
90 { ARM64_REG_D31, "d31"},
91 { ARM64_REG_H0, "h0"},
92 { ARM64_REG_H1, "h1"},
93 { ARM64_REG_H2, "h2"},
94 { ARM64_REG_H3, "h3"},
95 { ARM64_REG_H4, "h4"},
96 { ARM64_REG_H5, "h5"},
97 { ARM64_REG_H6, "h6"},
98 { ARM64_REG_H7, "h7"},
99 { ARM64_REG_H8, "h8"},
100 { ARM64_REG_H9, "h9"},
101 { ARM64_REG_H10, "h10"},
102 { ARM64_REG_H11, "h11"},
103 { ARM64_REG_H12, "h12"},
104 { ARM64_REG_H13, "h13"},
105 { ARM64_REG_H14, "h14"},
106 { ARM64_REG_H15, "h15"},
107 { ARM64_REG_H16, "h16"},
108 { ARM64_REG_H17, "h17"},
109 { ARM64_REG_H18, "h18"},
110 { ARM64_REG_H19, "h19"},
111 { ARM64_REG_H20, "h20"},
112 { ARM64_REG_H21, "h21"},
113 { ARM64_REG_H22, "h22"},
114 { ARM64_REG_H23, "h23"},
115 { ARM64_REG_H24, "h24"},
116 { ARM64_REG_H25, "h25"},
117 { ARM64_REG_H26, "h26"},
118 { ARM64_REG_H27, "h27"},
119 { ARM64_REG_H28, "h28"},
120 { ARM64_REG_H29, "h29"},
121 { ARM64_REG_H30, "h30"},
122 { ARM64_REG_H31, "h31"},
123 { ARM64_REG_Q0, "q0"},
124 { ARM64_REG_Q1, "q1"},
125 { ARM64_REG_Q2, "q2"},
126 { ARM64_REG_Q3, "q3"},
127 { ARM64_REG_Q4, "q4"},
128 { ARM64_REG_Q5, "q5"},
129 { ARM64_REG_Q6, "q6"},
130 { ARM64_REG_Q7, "q7"},
131 { ARM64_REG_Q8, "q8"},
132 { ARM64_REG_Q9, "q9"},
133 { ARM64_REG_Q10, "q10"},
134 { ARM64_REG_Q11, "q11"},
135 { ARM64_REG_Q12, "q12"},
136 { ARM64_REG_Q13, "q13"},
137 { ARM64_REG_Q14, "q14"},
138 { ARM64_REG_Q15, "q15"},
139 { ARM64_REG_Q16, "q16"},
140 { ARM64_REG_Q17, "q17"},
141 { ARM64_REG_Q18, "q18"},
142 { ARM64_REG_Q19, "q19"},
143 { ARM64_REG_Q20, "q20"},
144 { ARM64_REG_Q21, "q21"},
145 { ARM64_REG_Q22, "q22"},
146 { ARM64_REG_Q23, "q23"},
147 { ARM64_REG_Q24, "q24"},
148 { ARM64_REG_Q25, "q25"},
149 { ARM64_REG_Q26, "q26"},
150 { ARM64_REG_Q27, "q27"},
151 { ARM64_REG_Q28, "q28"},
152 { ARM64_REG_Q29, "q29"},
153 { ARM64_REG_Q30, "q30"},
154 { ARM64_REG_Q31, "q31"},
155 { ARM64_REG_S0, "s0"},
156 { ARM64_REG_S1, "s1"},
157 { ARM64_REG_S2, "s2"},
158 { ARM64_REG_S3, "s3"},
159 { ARM64_REG_S4, "s4"},
160 { ARM64_REG_S5, "s5"},
161 { ARM64_REG_S6, "s6"},
162 { ARM64_REG_S7, "s7"},
163 { ARM64_REG_S8, "s8"},
164 { ARM64_REG_S9, "s9"},
165 { ARM64_REG_S10, "s10"},
166 { ARM64_REG_S11, "s11"},
167 { ARM64_REG_S12, "s12"},
168 { ARM64_REG_S13, "s13"},
169 { ARM64_REG_S14, "s14"},
170 { ARM64_REG_S15, "s15"},
171 { ARM64_REG_S16, "s16"},
172 { ARM64_REG_S17, "s17"},
173 { ARM64_REG_S18, "s18"},
174 { ARM64_REG_S19, "s19"},
175 { ARM64_REG_S20, "s20"},
176 { ARM64_REG_S21, "s21"},
177 { ARM64_REG_S22, "s22"},
178 { ARM64_REG_S23, "s23"},
179 { ARM64_REG_S24, "s24"},
180 { ARM64_REG_S25, "s25"},
181 { ARM64_REG_S26, "s26"},
182 { ARM64_REG_S27, "s27"},
183 { ARM64_REG_S28, "s28"},
184 { ARM64_REG_S29, "s29"},
185 { ARM64_REG_S30, "s30"},
186 { ARM64_REG_S31, "s31"},
187 { ARM64_REG_W0, "w0"},
188 { ARM64_REG_W1, "w1"},
189 { ARM64_REG_W2, "w2"},
190 { ARM64_REG_W3, "w3"},
191 { ARM64_REG_W4, "w4"},
192 { ARM64_REG_W5, "w5"},
193 { ARM64_REG_W6, "w6"},
194 { ARM64_REG_W7, "w7"},
195 { ARM64_REG_W8, "w8"},
196 { ARM64_REG_W9, "w9"},
197 { ARM64_REG_W10, "w10"},
198 { ARM64_REG_W11, "w11"},
199 { ARM64_REG_W12, "w12"},
200 { ARM64_REG_W13, "w13"},
201 { ARM64_REG_W14, "w14"},
202 { ARM64_REG_W15, "w15"},
203 { ARM64_REG_W16, "w16"},
204 { ARM64_REG_W17, "w17"},
205 { ARM64_REG_W18, "w18"},
206 { ARM64_REG_W19, "w19"},
207 { ARM64_REG_W20, "w20"},
208 { ARM64_REG_W21, "w21"},
209 { ARM64_REG_W22, "w22"},
210 { ARM64_REG_W23, "w23"},
211 { ARM64_REG_W24, "w24"},
212 { ARM64_REG_W25, "w25"},
213 { ARM64_REG_W26, "w26"},
214 { ARM64_REG_W27, "w27"},
215 { ARM64_REG_W28, "w28"},
216 { ARM64_REG_W29, "w29"},
217 { ARM64_REG_W30, "w30"},
218 { ARM64_REG_X0, "x0"},
219 { ARM64_REG_X1, "x1"},
220 { ARM64_REG_X2, "x2"},
221 { ARM64_REG_X3, "x3"},
222 { ARM64_REG_X4, "x4"},
223 { ARM64_REG_X5, "x5"},
224 { ARM64_REG_X6, "x6"},
225 { ARM64_REG_X7, "x7"},
226 { ARM64_REG_X8, "x8"},
227 { ARM64_REG_X9, "x9"},
228 { ARM64_REG_X10, "x10"},
229 { ARM64_REG_X11, "x11"},
230 { ARM64_REG_X12, "x12"},
231 { ARM64_REG_X13, "x13"},
232 { ARM64_REG_X14, "x14"},
233 { ARM64_REG_X15, "x15"},
234 { ARM64_REG_X16, "x16"},
235 { ARM64_REG_X17, "x17"},
236 { ARM64_REG_X18, "x18"},
237 { ARM64_REG_X19, "x19"},
238 { ARM64_REG_X20, "x20"},
239 { ARM64_REG_X21, "x21"},
240 { ARM64_REG_X22, "x22"},
241 { ARM64_REG_X23, "x23"},
242 { ARM64_REG_X24, "x24"},
243 { ARM64_REG_X25, "x25"},
244 { ARM64_REG_X26, "x26"},
245 { ARM64_REG_X27, "x27"},
246 { ARM64_REG_X28, "x28"},
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]247
248 { ARM64_REG_V0, "v0"},
249 { ARM64_REG_V1, "v1"},
250 { ARM64_REG_V2, "v2"},
251 { ARM64_REG_V3, "v3"},
252 { ARM64_REG_V4, "v4"},
253 { ARM64_REG_V5, "v5"},
254 { ARM64_REG_V6, "v6"},
255 { ARM64_REG_V7, "v7"},
256 { ARM64_REG_V8, "v8"},
257 { ARM64_REG_V9, "v9"},
258 { ARM64_REG_V10, "v10"},
259 { ARM64_REG_V11, "v11"},
260 { ARM64_REG_V12, "v12"},
261 { ARM64_REG_V13, "v13"},
262 { ARM64_REG_V14, "v14"},
263 { ARM64_REG_V15, "v15"},
264 { ARM64_REG_V16, "v16"},
265 { ARM64_REG_V17, "v17"},
266 { ARM64_REG_V18, "v18"},
267 { ARM64_REG_V19, "v19"},
268 { ARM64_REG_V20, "v20"},
269 { ARM64_REG_V21, "v21"},
270 { ARM64_REG_V22, "v22"},
271 { ARM64_REG_V23, "v23"},
272 { ARM64_REG_V24, "v24"},
273 { ARM64_REG_V25, "v25"},
274 { ARM64_REG_V26, "v26"},
275 { ARM64_REG_V27, "v27"},
276 { ARM64_REG_V28, "v28"},
277 { ARM64_REG_V29, "v29"},
278 { ARM64_REG_V30, "v30"},
279 { ARM64_REG_V31, "v31"},
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]280};
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]281#endif
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]282
pancakef0e4eed2013-12-11 22:14:42 +0100[diff] [blame]283const char *AArch64_reg_name(csh handle, unsigned int reg)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]284{
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]285#ifndef CAPSTONE_DIET
Nguyen Anh Quynhd7e42b72014-09-29 17:15:25 +0800[diff] [blame]286 if (reg >= ARM64_REG_ENDING)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]287 return NULL;
288
289 return reg_name_maps[reg].name;
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]290#else
291 return NULL;
292#endif
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]293}
294
295static insn_map insns[] = {
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]296 // dummy item
297 {
298 0, 0,
299#ifndef CAPSTONE_DIET
300 { 0 }, { 0 }, { 0 }, 0, 0
301#endif
302 },
Nguyen Anh Quynhb2654062014-01-03 17:08:58 +0800[diff] [blame]303
Nguyen Anh Quynhbb5dcce2015-03-08 10:54:32 +0800[diff] [blame^]304#include "AArch64MappingInsn.inc"
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]305};
306
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]307// some alias instruction only need to be defined locally to satisfy
308// some lookup functions
309// just make sure these IDs never reuse any other IDs ARM_INS_*
Alex Ionescu46018db2014-01-22 09:45:00 -0800[diff] [blame]310#define ARM64_INS_NEGS (unsigned short)-1
311#define ARM64_INS_NGCS (unsigned short)-2
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]312
Nguyen Anh Quynhb2654062014-01-03 17:08:58 +0800[diff] [blame]313// given internal insn id, return public instruction info
Nguyen Anh Quynh1acfd0b2014-01-06 10:56:59 +0800[diff] [blame]314void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]315{
Nguyen Anh Quynh1acfd0b2014-01-06 10:56:59 +0800[diff] [blame]316 int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
Nguyen Anh Quynhb2654062014-01-03 17:08:58 +0800[diff] [blame]317 if (i != 0) {
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]318 insn->id = insns[i].mapid;
Nguyen Anh Quynhf35e2ad2013-12-03 11:10:26 +0800[diff] [blame]319
Nguyen Anh Quynh1acfd0b2014-01-06 10:56:59 +0800[diff] [blame]320 if (h->detail) {
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]321#ifndef CAPSTONE_DIET
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame]322 cs_struct handle;
Nguyen Anh Quynh1acfd0b2014-01-06 10:56:59 +0800[diff] [blame]323 handle.detail = h->detail;
Nguyen Anh Quynh42c6b1a2013-12-30 00:15:25 +0800[diff] [blame]324
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame]325 memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
Alex Ionescu46018db2014-01-22 09:45:00 -0800[diff] [blame]326 insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
Nguyen Anh Quynhf35e2ad2013-12-03 11:10:26 +0800[diff] [blame]327
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame]328 memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
Alex Ionescu46018db2014-01-22 09:45:00 -0800[diff] [blame]329 insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
Nguyen Anh Quynhf35e2ad2013-12-03 11:10:26 +0800[diff] [blame]330
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame]331 memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
Alex Ionescu46018db2014-01-22 09:45:00 -0800[diff] [blame]332 insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
Nguyen Anh Quynhf35e2ad2013-12-03 11:10:26 +0800[diff] [blame]333
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame]334 insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV);
Nguyen Anh Quynhec0ed8e2013-12-02 13:55:38 +0800[diff] [blame]335
Nguyen Anh Quynh4d3e8522013-12-14 10:45:09 +0800[diff] [blame]336 if (insns[i].branch || insns[i].indirect_branch) {
337 // this insn also belongs to JUMP group. add JUMP group
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame]338 insn->detail->groups[insn->detail->groups_count] = ARM64_GRP_JUMP;
339 insn->detail->groups_count++;
Nguyen Anh Quynh4d3e8522013-12-14 10:45:09 +0800[diff] [blame]340 }
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]341#endif
Nguyen Anh Quynhec0ed8e2013-12-02 13:55:38 +0800[diff] [blame]342 }
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]343 }
344}
345
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]346static name_map insn_name_maps[] = {
347 { ARM64_INS_INVALID, NULL },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]348
349 { ARM64_INS_ABS, "abs" },
350 { ARM64_INS_ADC, "adc" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]351 { ARM64_INS_ADDHN, "addhn" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]352 { ARM64_INS_ADDHN2, "addhn2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]353 { ARM64_INS_ADDP, "addp" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]354 { ARM64_INS_ADD, "add" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]355 { ARM64_INS_ADDV, "addv" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]356 { ARM64_INS_ADR, "adr" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]357 { ARM64_INS_ADRP, "adrp" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]358 { ARM64_INS_AESD, "aesd" },
359 { ARM64_INS_AESE, "aese" },
360 { ARM64_INS_AESIMC, "aesimc" },
361 { ARM64_INS_AESMC, "aesmc" },
362 { ARM64_INS_AND, "and" },
363 { ARM64_INS_ASR, "asr" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]364 { ARM64_INS_B, "b" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]365 { ARM64_INS_BFM, "bfm" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]366 { ARM64_INS_BIC, "bic" },
367 { ARM64_INS_BIF, "bif" },
368 { ARM64_INS_BIT, "bit" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]369 { ARM64_INS_BL, "bl" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]370 { ARM64_INS_BLR, "blr" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]371 { ARM64_INS_BR, "br" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]372 { ARM64_INS_BRK, "brk" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]373 { ARM64_INS_BSL, "bsl" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]374 { ARM64_INS_CBNZ, "cbnz" },
375 { ARM64_INS_CBZ, "cbz" },
376 { ARM64_INS_CCMN, "ccmn" },
377 { ARM64_INS_CCMP, "ccmp" },
378 { ARM64_INS_CLREX, "clrex" },
379 { ARM64_INS_CLS, "cls" },
380 { ARM64_INS_CLZ, "clz" },
381 { ARM64_INS_CMEQ, "cmeq" },
382 { ARM64_INS_CMGE, "cmge" },
383 { ARM64_INS_CMGT, "cmgt" },
384 { ARM64_INS_CMHI, "cmhi" },
385 { ARM64_INS_CMHS, "cmhs" },
386 { ARM64_INS_CMLE, "cmle" },
387 { ARM64_INS_CMLT, "cmlt" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]388 { ARM64_INS_CMTST, "cmtst" },
389 { ARM64_INS_CNT, "cnt" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]390 { ARM64_INS_MOV, "mov" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]391 { ARM64_INS_CRC32B, "crc32b" },
392 { ARM64_INS_CRC32CB, "crc32cb" },
393 { ARM64_INS_CRC32CH, "crc32ch" },
394 { ARM64_INS_CRC32CW, "crc32cw" },
395 { ARM64_INS_CRC32CX, "crc32cx" },
396 { ARM64_INS_CRC32H, "crc32h" },
397 { ARM64_INS_CRC32W, "crc32w" },
398 { ARM64_INS_CRC32X, "crc32x" },
399 { ARM64_INS_CSEL, "csel" },
400 { ARM64_INS_CSINC, "csinc" },
401 { ARM64_INS_CSINV, "csinv" },
402 { ARM64_INS_CSNEG, "csneg" },
403 { ARM64_INS_DCPS1, "dcps1" },
404 { ARM64_INS_DCPS2, "dcps2" },
405 { ARM64_INS_DCPS3, "dcps3" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]406 { ARM64_INS_DMB, "dmb" },
407 { ARM64_INS_DRPS, "drps" },
408 { ARM64_INS_DSB, "dsb" },
409 { ARM64_INS_DUP, "dup" },
410 { ARM64_INS_EON, "eon" },
411 { ARM64_INS_EOR, "eor" },
412 { ARM64_INS_ERET, "eret" },
413 { ARM64_INS_EXTR, "extr" },
414 { ARM64_INS_EXT, "ext" },
415 { ARM64_INS_FABD, "fabd" },
416 { ARM64_INS_FABS, "fabs" },
417 { ARM64_INS_FACGE, "facge" },
418 { ARM64_INS_FACGT, "facgt" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]419 { ARM64_INS_FADD, "fadd" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]420 { ARM64_INS_FADDP, "faddp" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]421 { ARM64_INS_FCCMP, "fccmp" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]422 { ARM64_INS_FCCMPE, "fccmpe" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]423 { ARM64_INS_FCMEQ, "fcmeq" },
424 { ARM64_INS_FCMGE, "fcmge" },
425 { ARM64_INS_FCMGT, "fcmgt" },
426 { ARM64_INS_FCMLE, "fcmle" },
427 { ARM64_INS_FCMLT, "fcmlt" },
428 { ARM64_INS_FCMP, "fcmp" },
429 { ARM64_INS_FCMPE, "fcmpe" },
430 { ARM64_INS_FCSEL, "fcsel" },
431 { ARM64_INS_FCVTAS, "fcvtas" },
432 { ARM64_INS_FCVTAU, "fcvtau" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]433 { ARM64_INS_FCVT, "fcvt" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]434 { ARM64_INS_FCVTL, "fcvtl" },
435 { ARM64_INS_FCVTL2, "fcvtl2" },
436 { ARM64_INS_FCVTMS, "fcvtms" },
437 { ARM64_INS_FCVTMU, "fcvtmu" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]438 { ARM64_INS_FCVTNS, "fcvtns" },
439 { ARM64_INS_FCVTNU, "fcvtnu" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]440 { ARM64_INS_FCVTN, "fcvtn" },
441 { ARM64_INS_FCVTN2, "fcvtn2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]442 { ARM64_INS_FCVTPS, "fcvtps" },
443 { ARM64_INS_FCVTPU, "fcvtpu" },
444 { ARM64_INS_FCVTXN, "fcvtxn" },
445 { ARM64_INS_FCVTXN2, "fcvtxn2" },
446 { ARM64_INS_FCVTZS, "fcvtzs" },
447 { ARM64_INS_FCVTZU, "fcvtzu" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]448 { ARM64_INS_FDIV, "fdiv" },
449 { ARM64_INS_FMADD, "fmadd" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]450 { ARM64_INS_FMAX, "fmax" },
451 { ARM64_INS_FMAXNM, "fmaxnm" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]452 { ARM64_INS_FMAXNMP, "fmaxnmp" },
453 { ARM64_INS_FMAXNMV, "fmaxnmv" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]454 { ARM64_INS_FMAXP, "fmaxp" },
455 { ARM64_INS_FMAXV, "fmaxv" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]456 { ARM64_INS_FMIN, "fmin" },
457 { ARM64_INS_FMINNM, "fminnm" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]458 { ARM64_INS_FMINNMP, "fminnmp" },
459 { ARM64_INS_FMINNMV, "fminnmv" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]460 { ARM64_INS_FMINP, "fminp" },
461 { ARM64_INS_FMINV, "fminv" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]462 { ARM64_INS_FMLA, "fmla" },
463 { ARM64_INS_FMLS, "fmls" },
464 { ARM64_INS_FMOV, "fmov" },
465 { ARM64_INS_FMSUB, "fmsub" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]466 { ARM64_INS_FMUL, "fmul" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]467 { ARM64_INS_FMULX, "fmulx" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]468 { ARM64_INS_FNEG, "fneg" },
469 { ARM64_INS_FNMADD, "fnmadd" },
470 { ARM64_INS_FNMSUB, "fnmsub" },
471 { ARM64_INS_FNMUL, "fnmul" },
472 { ARM64_INS_FRECPE, "frecpe" },
473 { ARM64_INS_FRECPS, "frecps" },
474 { ARM64_INS_FRECPX, "frecpx" },
475 { ARM64_INS_FRINTA, "frinta" },
476 { ARM64_INS_FRINTI, "frinti" },
477 { ARM64_INS_FRINTM, "frintm" },
478 { ARM64_INS_FRINTN, "frintn" },
479 { ARM64_INS_FRINTP, "frintp" },
480 { ARM64_INS_FRINTX, "frintx" },
481 { ARM64_INS_FRINTZ, "frintz" },
482 { ARM64_INS_FRSQRTE, "frsqrte" },
483 { ARM64_INS_FRSQRTS, "frsqrts" },
484 { ARM64_INS_FSQRT, "fsqrt" },
485 { ARM64_INS_FSUB, "fsub" },
486 { ARM64_INS_HINT, "hint" },
487 { ARM64_INS_HLT, "hlt" },
488 { ARM64_INS_HVC, "hvc" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]489 { ARM64_INS_INS, "ins" },
490 { ARM64_INS_ISB, "isb" },
491 { ARM64_INS_LD1, "ld1" },
492 { ARM64_INS_LD1R, "ld1r" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]493 { ARM64_INS_LD2R, "ld2r" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]494 { ARM64_INS_LD2, "ld2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]495 { ARM64_INS_LD3R, "ld3r" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]496 { ARM64_INS_LD3, "ld3" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]497 { ARM64_INS_LD4, "ld4" },
498 { ARM64_INS_LD4R, "ld4r" },
499 { ARM64_INS_LDARB, "ldarb" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]500 { ARM64_INS_LDARH, "ldarh" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]501 { ARM64_INS_LDAR, "ldar" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]502 { ARM64_INS_LDAXP, "ldaxp" },
503 { ARM64_INS_LDAXRB, "ldaxrb" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]504 { ARM64_INS_LDAXRH, "ldaxrh" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]505 { ARM64_INS_LDAXR, "ldaxr" },
506 { ARM64_INS_LDNP, "ldnp" },
507 { ARM64_INS_LDP, "ldp" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]508 { ARM64_INS_LDPSW, "ldpsw" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]509 { ARM64_INS_LDRB, "ldrb" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]510 { ARM64_INS_LDR, "ldr" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]511 { ARM64_INS_LDRH, "ldrh" },
512 { ARM64_INS_LDRSB, "ldrsb" },
513 { ARM64_INS_LDRSH, "ldrsh" },
514 { ARM64_INS_LDRSW, "ldrsw" },
515 { ARM64_INS_LDTRB, "ldtrb" },
516 { ARM64_INS_LDTRH, "ldtrh" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]517 { ARM64_INS_LDTRSB, "ldtrsb" },
518 { ARM64_INS_LDTRSH, "ldtrsh" },
519 { ARM64_INS_LDTRSW, "ldtrsw" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]520 { ARM64_INS_LDTR, "ldtr" },
521 { ARM64_INS_LDURB, "ldurb" },
522 { ARM64_INS_LDUR, "ldur" },
523 { ARM64_INS_LDURH, "ldurh" },
524 { ARM64_INS_LDURSB, "ldursb" },
525 { ARM64_INS_LDURSH, "ldursh" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]526 { ARM64_INS_LDURSW, "ldursw" },
527 { ARM64_INS_LDXP, "ldxp" },
528 { ARM64_INS_LDXRB, "ldxrb" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]529 { ARM64_INS_LDXRH, "ldxrh" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]530 { ARM64_INS_LDXR, "ldxr" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]531 { ARM64_INS_LSL, "lsl" },
532 { ARM64_INS_LSR, "lsr" },
533 { ARM64_INS_MADD, "madd" },
534 { ARM64_INS_MLA, "mla" },
535 { ARM64_INS_MLS, "mls" },
536 { ARM64_INS_MOVI, "movi" },
537 { ARM64_INS_MOVK, "movk" },
538 { ARM64_INS_MOVN, "movn" },
539 { ARM64_INS_MOVZ, "movz" },
540 { ARM64_INS_MRS, "mrs" },
541 { ARM64_INS_MSR, "msr" },
542 { ARM64_INS_MSUB, "msub" },
543 { ARM64_INS_MUL, "mul" },
544 { ARM64_INS_MVNI, "mvni" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]545 { ARM64_INS_NEG, "neg" },
546 { ARM64_INS_NOT, "not" },
547 { ARM64_INS_ORN, "orn" },
548 { ARM64_INS_ORR, "orr" },
549 { ARM64_INS_PMULL2, "pmull2" },
550 { ARM64_INS_PMULL, "pmull" },
551 { ARM64_INS_PMUL, "pmul" },
552 { ARM64_INS_PRFM, "prfm" },
553 { ARM64_INS_PRFUM, "prfum" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]554 { ARM64_INS_RADDHN, "raddhn" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]555 { ARM64_INS_RADDHN2, "raddhn2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]556 { ARM64_INS_RBIT, "rbit" },
557 { ARM64_INS_RET, "ret" },
558 { ARM64_INS_REV16, "rev16" },
559 { ARM64_INS_REV32, "rev32" },
560 { ARM64_INS_REV64, "rev64" },
561 { ARM64_INS_REV, "rev" },
562 { ARM64_INS_ROR, "ror" },
563 { ARM64_INS_RSHRN2, "rshrn2" },
564 { ARM64_INS_RSHRN, "rshrn" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]565 { ARM64_INS_RSUBHN, "rsubhn" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]566 { ARM64_INS_RSUBHN2, "rsubhn2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]567 { ARM64_INS_SABAL2, "sabal2" },
568 { ARM64_INS_SABAL, "sabal" },
569 { ARM64_INS_SABA, "saba" },
570 { ARM64_INS_SABDL2, "sabdl2" },
571 { ARM64_INS_SABDL, "sabdl" },
572 { ARM64_INS_SABD, "sabd" },
573 { ARM64_INS_SADALP, "sadalp" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]574 { ARM64_INS_SADDLP, "saddlp" },
575 { ARM64_INS_SADDLV, "saddlv" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]576 { ARM64_INS_SADDL2, "saddl2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]577 { ARM64_INS_SADDL, "saddl" },
578 { ARM64_INS_SADDW2, "saddw2" },
579 { ARM64_INS_SADDW, "saddw" },
580 { ARM64_INS_SBC, "sbc" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]581 { ARM64_INS_SBFM, "sbfm" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]582 { ARM64_INS_SCVTF, "scvtf" },
583 { ARM64_INS_SDIV, "sdiv" },
584 { ARM64_INS_SHA1C, "sha1c" },
585 { ARM64_INS_SHA1H, "sha1h" },
586 { ARM64_INS_SHA1M, "sha1m" },
587 { ARM64_INS_SHA1P, "sha1p" },
588 { ARM64_INS_SHA1SU0, "sha1su0" },
589 { ARM64_INS_SHA1SU1, "sha1su1" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]590 { ARM64_INS_SHA256H2, "sha256h2" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]591 { ARM64_INS_SHA256H, "sha256h" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]592 { ARM64_INS_SHA256SU0, "sha256su0" },
593 { ARM64_INS_SHA256SU1, "sha256su1" },
594 { ARM64_INS_SHADD, "shadd" },
595 { ARM64_INS_SHLL2, "shll2" },
596 { ARM64_INS_SHLL, "shll" },
597 { ARM64_INS_SHL, "shl" },
598 { ARM64_INS_SHRN2, "shrn2" },
599 { ARM64_INS_SHRN, "shrn" },
600 { ARM64_INS_SHSUB, "shsub" },
601 { ARM64_INS_SLI, "sli" },
602 { ARM64_INS_SMADDL, "smaddl" },
603 { ARM64_INS_SMAXP, "smaxp" },
604 { ARM64_INS_SMAXV, "smaxv" },
605 { ARM64_INS_SMAX, "smax" },
606 { ARM64_INS_SMC, "smc" },
607 { ARM64_INS_SMINP, "sminp" },
608 { ARM64_INS_SMINV, "sminv" },
609 { ARM64_INS_SMIN, "smin" },
610 { ARM64_INS_SMLAL2, "smlal2" },
611 { ARM64_INS_SMLAL, "smlal" },
612 { ARM64_INS_SMLSL2, "smlsl2" },
613 { ARM64_INS_SMLSL, "smlsl" },
614 { ARM64_INS_SMOV, "smov" },
615 { ARM64_INS_SMSUBL, "smsubl" },
616 { ARM64_INS_SMULH, "smulh" },
617 { ARM64_INS_SMULL2, "smull2" },
618 { ARM64_INS_SMULL, "smull" },
619 { ARM64_INS_SQABS, "sqabs" },
620 { ARM64_INS_SQADD, "sqadd" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]621 { ARM64_INS_SQDMLAL, "sqdmlal" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]622 { ARM64_INS_SQDMLAL2, "sqdmlal2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]623 { ARM64_INS_SQDMLSL, "sqdmlsl" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]624 { ARM64_INS_SQDMLSL2, "sqdmlsl2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]625 { ARM64_INS_SQDMULH, "sqdmulh" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]626 { ARM64_INS_SQDMULL, "sqdmull" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]627 { ARM64_INS_SQDMULL2, "sqdmull2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]628 { ARM64_INS_SQNEG, "sqneg" },
629 { ARM64_INS_SQRDMULH, "sqrdmulh" },
630 { ARM64_INS_SQRSHL, "sqrshl" },
631 { ARM64_INS_SQRSHRN, "sqrshrn" },
632 { ARM64_INS_SQRSHRN2, "sqrshrn2" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]633 { ARM64_INS_SQRSHRUN, "sqrshrun" },
634 { ARM64_INS_SQRSHRUN2, "sqrshrun2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]635 { ARM64_INS_SQSHLU, "sqshlu" },
636 { ARM64_INS_SQSHL, "sqshl" },
637 { ARM64_INS_SQSHRN, "sqshrn" },
638 { ARM64_INS_SQSHRN2, "sqshrn2" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]639 { ARM64_INS_SQSHRUN, "sqshrun" },
640 { ARM64_INS_SQSHRUN2, "sqshrun2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]641 { ARM64_INS_SQSUB, "sqsub" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]642 { ARM64_INS_SQXTN2, "sqxtn2" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]643 { ARM64_INS_SQXTN, "sqxtn" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]644 { ARM64_INS_SQXTUN2, "sqxtun2" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]645 { ARM64_INS_SQXTUN, "sqxtun" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]646 { ARM64_INS_SRHADD, "srhadd" },
647 { ARM64_INS_SRI, "sri" },
648 { ARM64_INS_SRSHL, "srshl" },
649 { ARM64_INS_SRSHR, "srshr" },
650 { ARM64_INS_SRSRA, "srsra" },
651 { ARM64_INS_SSHLL2, "sshll2" },
652 { ARM64_INS_SSHLL, "sshll" },
653 { ARM64_INS_SSHL, "sshl" },
654 { ARM64_INS_SSHR, "sshr" },
655 { ARM64_INS_SSRA, "ssra" },
656 { ARM64_INS_SSUBL2, "ssubl2" },
657 { ARM64_INS_SSUBL, "ssubl" },
658 { ARM64_INS_SSUBW2, "ssubw2" },
659 { ARM64_INS_SSUBW, "ssubw" },
660 { ARM64_INS_ST1, "st1" },
661 { ARM64_INS_ST2, "st2" },
662 { ARM64_INS_ST3, "st3" },
663 { ARM64_INS_ST4, "st4" },
664 { ARM64_INS_STLRB, "stlrb" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]665 { ARM64_INS_STLRH, "stlrh" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]666 { ARM64_INS_STLR, "stlr" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]667 { ARM64_INS_STLXP, "stlxp" },
668 { ARM64_INS_STLXRB, "stlxrb" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]669 { ARM64_INS_STLXRH, "stlxrh" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]670 { ARM64_INS_STLXR, "stlxr" },
671 { ARM64_INS_STNP, "stnp" },
672 { ARM64_INS_STP, "stp" },
673 { ARM64_INS_STRB, "strb" },
674 { ARM64_INS_STR, "str" },
675 { ARM64_INS_STRH, "strh" },
676 { ARM64_INS_STTRB, "sttrb" },
677 { ARM64_INS_STTRH, "sttrh" },
678 { ARM64_INS_STTR, "sttr" },
679 { ARM64_INS_STURB, "sturb" },
680 { ARM64_INS_STUR, "stur" },
681 { ARM64_INS_STURH, "sturh" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]682 { ARM64_INS_STXP, "stxp" },
683 { ARM64_INS_STXRB, "stxrb" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]684 { ARM64_INS_STXRH, "stxrh" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]685 { ARM64_INS_STXR, "stxr" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]686 { ARM64_INS_SUBHN, "subhn" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]687 { ARM64_INS_SUBHN2, "subhn2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]688 { ARM64_INS_SUB, "sub" },
689 { ARM64_INS_SUQADD, "suqadd" },
690 { ARM64_INS_SVC, "svc" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]691 { ARM64_INS_SYSL, "sysl" },
692 { ARM64_INS_SYS, "sys" },
693 { ARM64_INS_TBL, "tbl" },
694 { ARM64_INS_TBNZ, "tbnz" },
695 { ARM64_INS_TBX, "tbx" },
696 { ARM64_INS_TBZ, "tbz" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]697 { ARM64_INS_TRN1, "trn1" },
698 { ARM64_INS_TRN2, "trn2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]699 { ARM64_INS_UABAL2, "uabal2" },
700 { ARM64_INS_UABAL, "uabal" },
701 { ARM64_INS_UABA, "uaba" },
702 { ARM64_INS_UABDL2, "uabdl2" },
703 { ARM64_INS_UABDL, "uabdl" },
704 { ARM64_INS_UABD, "uabd" },
705 { ARM64_INS_UADALP, "uadalp" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]706 { ARM64_INS_UADDLP, "uaddlp" },
707 { ARM64_INS_UADDLV, "uaddlv" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]708 { ARM64_INS_UADDL2, "uaddl2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]709 { ARM64_INS_UADDL, "uaddl" },
710 { ARM64_INS_UADDW2, "uaddw2" },
711 { ARM64_INS_UADDW, "uaddw" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]712 { ARM64_INS_UBFM, "ubfm" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]713 { ARM64_INS_UCVTF, "ucvtf" },
714 { ARM64_INS_UDIV, "udiv" },
715 { ARM64_INS_UHADD, "uhadd" },
716 { ARM64_INS_UHSUB, "uhsub" },
717 { ARM64_INS_UMADDL, "umaddl" },
718 { ARM64_INS_UMAXP, "umaxp" },
719 { ARM64_INS_UMAXV, "umaxv" },
720 { ARM64_INS_UMAX, "umax" },
721 { ARM64_INS_UMINP, "uminp" },
722 { ARM64_INS_UMINV, "uminv" },
723 { ARM64_INS_UMIN, "umin" },
724 { ARM64_INS_UMLAL2, "umlal2" },
725 { ARM64_INS_UMLAL, "umlal" },
726 { ARM64_INS_UMLSL2, "umlsl2" },
727 { ARM64_INS_UMLSL, "umlsl" },
728 { ARM64_INS_UMOV, "umov" },
729 { ARM64_INS_UMSUBL, "umsubl" },
730 { ARM64_INS_UMULH, "umulh" },
731 { ARM64_INS_UMULL2, "umull2" },
732 { ARM64_INS_UMULL, "umull" },
733 { ARM64_INS_UQADD, "uqadd" },
734 { ARM64_INS_UQRSHL, "uqrshl" },
735 { ARM64_INS_UQRSHRN, "uqrshrn" },
736 { ARM64_INS_UQRSHRN2, "uqrshrn2" },
737 { ARM64_INS_UQSHL, "uqshl" },
738 { ARM64_INS_UQSHRN, "uqshrn" },
739 { ARM64_INS_UQSHRN2, "uqshrn2" },
740 { ARM64_INS_UQSUB, "uqsub" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]741 { ARM64_INS_UQXTN2, "uqxtn2" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]742 { ARM64_INS_UQXTN, "uqxtn" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]743 { ARM64_INS_URECPE, "urecpe" },
744 { ARM64_INS_URHADD, "urhadd" },
745 { ARM64_INS_URSHL, "urshl" },
746 { ARM64_INS_URSHR, "urshr" },
747 { ARM64_INS_URSQRTE, "ursqrte" },
748 { ARM64_INS_URSRA, "ursra" },
749 { ARM64_INS_USHLL2, "ushll2" },
750 { ARM64_INS_USHLL, "ushll" },
751 { ARM64_INS_USHL, "ushl" },
752 { ARM64_INS_USHR, "ushr" },
753 { ARM64_INS_USQADD, "usqadd" },
754 { ARM64_INS_USRA, "usra" },
755 { ARM64_INS_USUBL2, "usubl2" },
756 { ARM64_INS_USUBL, "usubl" },
757 { ARM64_INS_USUBW2, "usubw2" },
758 { ARM64_INS_USUBW, "usubw" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]759 { ARM64_INS_UZP1, "uzp1" },
760 { ARM64_INS_UZP2, "uzp2" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]761 { ARM64_INS_XTN2, "xtn2" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]762 { ARM64_INS_XTN, "xtn" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]763 { ARM64_INS_ZIP1, "zip1" },
764 { ARM64_INS_ZIP2, "zip2" },
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]765};
766
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]767// map *S & alias instructions back to original id
768static name_map alias_insn_name_maps[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]769 { ARM64_INS_ADC, "adcs" },
770 { ARM64_INS_AND, "ands" },
771 { ARM64_INS_ADD, "adds" },
772 { ARM64_INS_BIC, "bics" },
773 { ARM64_INS_SBC, "sbcs" },
774 { ARM64_INS_SUB, "subs" },
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]775
776 // alias insn
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]777 { ARM64_INS_MNEG, "mneg" },
778 { ARM64_INS_UMNEGL, "umnegl" },
779 { ARM64_INS_SMNEGL, "smnegl" },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]780 { ARM64_INS_NOP, "nop" },
781 { ARM64_INS_YIELD, "yield" },
782 { ARM64_INS_WFE, "wfe" },
783 { ARM64_INS_WFI, "wfi" },
784 { ARM64_INS_SEV, "sev" },
785 { ARM64_INS_SEVL, "sevl" },
786 { ARM64_INS_NGC, "ngc" },
787 { ARM64_INS_NGCS, "ngcs" },
788 { ARM64_INS_NEGS, "negs" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]789
790 { ARM64_INS_SBFIZ, "sbfiz" },
791 { ARM64_INS_UBFIZ, "ubfiz" },
792 { ARM64_INS_SBFX, "sbfx" },
793 { ARM64_INS_UBFX, "ubfx" },
794 { ARM64_INS_BFI, "bfi" },
795 { ARM64_INS_BFXIL, "bfxil" },
796 { ARM64_INS_CMN, "cmn" },
797 { ARM64_INS_MVN, "mvn" },
798 { ARM64_INS_TST, "tst" },
799 { ARM64_INS_CSET, "cset" },
800 { ARM64_INS_CINC, "cinc" },
801 { ARM64_INS_CSETM, "csetm" },
802 { ARM64_INS_CINV, "cinv" },
803 { ARM64_INS_CNEG, "cneg" },
804 { ARM64_INS_SXTB, "sxtb" },
805 { ARM64_INS_SXTH, "sxth" },
806 { ARM64_INS_SXTW, "sxtw" },
807 { ARM64_INS_CMP, "cmp" },
808 { ARM64_INS_UXTB, "uxtb" },
809 { ARM64_INS_UXTH, "uxth" },
810 { ARM64_INS_UXTW, "uxtw" },
811
812 { ARM64_INS_IC, "ic" },
813 { ARM64_INS_DC, "dc" },
814 { ARM64_INS_AT, "at" },
815 { ARM64_INS_TLBI, "tlbi" },
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]816};
817
pancakef0e4eed2013-12-11 22:14:42 +0100[diff] [blame]818const char *AArch64_insn_name(csh handle, unsigned int id)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]819{
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]820#ifndef CAPSTONE_DIET
Nguyen Anh Quynhf6c7cbc2014-03-12 12:50:54 +0800[diff] [blame]821 unsigned int i;
822
Nguyen Anh Quynhd7e42b72014-09-29 17:15:25 +0800[diff] [blame]823 if (id >= ARM64_INS_ENDING)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]824 return NULL;
825
Nguyen Anh Quynhdcbe0f82014-01-12 10:11:36 +0800[diff] [blame]826 if (id < ARR_SIZE(insn_name_maps))
827 return insn_name_maps[id].name;
828
829 // then find alias insn
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]830 for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) {
831 if (alias_insn_name_maps[i].id == id)
832 return alias_insn_name_maps[i].name;
833 }
834
Nguyen Anh Quynhdcbe0f82014-01-12 10:11:36 +0800[diff] [blame]835 // not found
836 return NULL;
Nguyen Anh Quynhfc83a432014-02-22 23:26:27 +0800[diff] [blame]837#else
838 return NULL;
839#endif
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]840}
841
Nguyen Anh Quynh650f96c2014-07-08 08:59:27 +0800[diff] [blame]842#ifndef CAPSTONE_DIET
843static name_map group_name_maps[] = {
Nguyen Anh Quynhc2ea8122014-10-31 15:36:19 +0800[diff] [blame]844 // generic groups
Nguyen Anh Quynh650f96c2014-07-08 08:59:27 +0800[diff] [blame]845 { ARM64_GRP_INVALID, NULL },
Nguyen Anh Quynhc2ea8122014-10-31 15:36:19 +0800[diff] [blame]846 { ARM64_GRP_JUMP, "jump" },
847
848 // architecture-specific groups
Nguyen Anh Quynh650f96c2014-07-08 08:59:27 +0800[diff] [blame]849 { ARM64_GRP_CRYPTO, "crypto" },
850 { ARM64_GRP_FPARMV8, "fparmv8" },
851 { ARM64_GRP_NEON, "neon" },
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]852 { ARM64_GRP_CRC, "crc" },
Nguyen Anh Quynh650f96c2014-07-08 08:59:27 +0800[diff] [blame]853
Nguyen Anh Quynh650f96c2014-07-08 08:59:27 +0800[diff] [blame]854};
855#endif
856
857const char *AArch64_group_name(csh handle, unsigned int id)
858{
859#ifndef CAPSTONE_DIET
Nguyen Anh Quynhc2ea8122014-10-31 15:36:19 +0800[diff] [blame]860 // verify group id
861 if (id >= ARM64_GRP_ENDING || (id > ARM64_GRP_JUMP && id < ARM64_GRP_CRYPTO))
Nguyen Anh Quynh650f96c2014-07-08 08:59:27 +0800[diff] [blame]862 return NULL;
863
Nguyen Anh Quynhc2ea8122014-10-31 15:36:19 +0800[diff] [blame]864 // NOTE: when new generic groups are added, 2 must be changed accordingly
865 if (id >= 128)
866 return group_name_maps[id - 128 + 2].name;
867 else
868 return group_name_maps[id].name;
Nguyen Anh Quynh650f96c2014-07-08 08:59:27 +0800[diff] [blame]869#else
870 return NULL;
871#endif
872}
873
Nguyen Anh Quynh6b7abe32013-11-30 00:54:24 +0800[diff] [blame]874// map instruction name to public instruction ID
pancakef0e4eed2013-12-11 22:14:42 +0100[diff] [blame]875arm64_reg AArch64_map_insn(const char *name)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]876{
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]877 // NOTE: skip first NULL name in insn_name_maps
878 int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
879
880 if (i == -1)
881 // try again with 'special' insn that is not available in insn_name_maps
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]882 i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name);
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]883
884 return (i != -1)? i : ARM64_REG_INVALID;
885}
Nguyen Anh Quynh8598a212014-05-14 11:26:41 +0800[diff] [blame]886
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]887// map internal raw vregister to 'public' register
888arm64_reg AArch64_map_vregister(unsigned int r)
889{
890 // for some reasons different Arm64 can map different register number to
891 // the same register. this function handles the issue for exposing Mips
892 // operands by mapping internal registers to 'public' register.
893 unsigned int map[] = { 0,
894 0, 0, 0, 0, 0,
895 0, 0, 0, 0, 0,
896 0, 0, 0, 0, 0,
897 0, 0, 0, 0, 0,
898 0, 0, 0, 0, 0,
899 0, 0, 0, 0, 0,
900 0, 0, 0, 0, 0,
901 0, 0, 0, 0, ARM64_REG_V0,
902 ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5,
903 ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10,
904 ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15,
905 ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20,
906 ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25,
907 ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30,
908 ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
909 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
910 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1,
911 ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6,
912 ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11,
913 ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16,
914 ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21,
915 ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26,
916 ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31,
917 0, 0, 0, 0, 0,
918 0, 0, 0, 0, 0,
919 0, 0, 0, 0, 0,
920 0, 0, 0, 0, 0,
921 0, 0, 0, 0, 0,
922 0, 0, 0, 0, 0,
923 0, 0, 0, 0, 0,
924 0, 0, 0, 0, 0,
925 0, 0, 0, 0, 0,
926 0, 0, 0, 0, 0,
927 0, 0, 0, 0, 0,
928 0, 0, 0, 0, 0,
929 0, 0, 0, 0, 0,
930 0, 0, 0, 0, 0,
931 0, 0, 0, 0, 0,
932 0, 0, 0, 0, 0,
933 0, 0, 0, 0, 0,
934 0, 0, 0, 0, 0,
935 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2,
936 ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7,
937 ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12,
938 ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17,
939 ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22,
940 ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27,
941 ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0,
942 ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5,
943 ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10,
944 ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15,
945 ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20,
946 ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25,
947 ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30,
948 ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3,
949 ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8,
950 ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13,
951 ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18,
952 ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23,
953 ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28,
954 ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1,
955 ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6,
956 ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11,
957 ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16,
958 ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21,
959 ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26,
960 ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31,
961 ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4,
962 ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9,
963 ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14,
964 ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19,
965 ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24,
966 ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29,
967 ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2,
968 ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7,
969 ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12,
970 ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17,
971 ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22,
972 ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27,
973 ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, };
974
975 if (r < ARR_SIZE(map))
976 return map[r];
977
978 // cannot find this register
979 return 0;
980}
981
982void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp)
983{
984 if (MI->csh->detail) {
985 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp;
986 }
987}
988
989void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp)
990{
991 if (MI->csh->detail) {
992 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vess = sp;
993 }
994}
995
996void arm64_op_addFP(MCInst *MI, float fp)
997{
998 if (MI->csh->detail) {
999 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
1000 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp;
1001 MI->flat_insn->detail->arm64.op_count++;
1002 }
1003}
1004
1005void arm64_op_addImm(MCInst *MI, int64_t imm)
1006{
1007 if (MI->csh->detail) {
1008 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
Nguyen Anh Quynh4b6b15f2014-08-26 15:57:04 +0800[diff] [blame]1009 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm;
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1010 MI->flat_insn->detail->arm64.op_count++;
1011 }
1012}
1013
Nguyen Anh Quynhe8eb5362015-02-23 11:35:35 +0800[diff] [blame]1014#if 0
1015
1016// Runtime option for the disassembled engine
1017typedef enum cs_op_type {
1018 CS_OP_READ = 1, // this operand reads register
1019 CS_OP_WRITE, // this operand writes register
1020} cs_op_type;
1021
1022// map instruction to its characteristics
1023typedef struct insn_op {
1024 unsigned int eflags_update; // how this instruction update status flags
1025 cs_op_type operands[4];
1026} insn_op;
1027
Nguyen Anh Quynhed6d75a2015-02-24 22:03:28 +0800[diff] [blame]1028static insn_op insn_ops[] = {
1029 { /* AArch64_ABSv16i8, ARM64_INS_ABS: abs.16b $rd, $rn */
BuiDinhCuong51ff8492015-02-24 20:22:08 +0700[diff] [blame]1030 0,
1031 { CS_OP_WRITE, CS_OP_READ, 0 }
1032 },
1033 { /* AArch64_ABSv1i64, ARM64_INS_ABS: abs $rd, $rn */
1034 0,
1035 { CS_OP_WRITE, CS_OP_READ, 0 }
1036 },
1037 { /* AArch64_ABSv2i32, ARM64_INS_ABS: abs.2s $rd, $rn */
1038 0,
1039 { CS_OP_WRITE, CS_OP_READ, 0 }
1040 },
1041 { /* AArch64_ABSv2i64, ARM64_INS_ABS: abs.2d $rd, $rn */
1042 0,
1043 { CS_OP_WRITE, CS_OP_READ, 0 }
1044 },
1045 { /* AArch64_ABSv4i16, ARM64_INS_ABS: abs.4h $rd, $rn */
1046 0,
1047 { CS_OP_WRITE, CS_OP_READ, 0 }
1048 },
1049 { /* AArch64_ABSv4i32, ARM64_INS_ABS: abs.4s $rd, $rn */
1050 0,
1051 { CS_OP_WRITE, CS_OP_READ, 0 }
1052 },
1053 { /* AArch64_ABSv8i16, ARM64_INS_ABS: abs.8h $rd, $rn */
1054 0,
1055 { CS_OP_WRITE, CS_OP_READ, 0 }
1056 },
1057 { /* AArch64_ABSv8i8, ARM64_INS_ABS: abs.8b $rd, $rn */
1058 0,
1059 { CS_OP_WRITE, CS_OP_READ, 0 }
1060 },
1061 { /* AArch64_ADCSWr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */
1062 0,
1063 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1064 },
1065 { /* AArch64_ADCSXr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */
1066 0,
1067 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1068 },
1069 { /* AArch64_ADCWr, ARM64_INS_ADC: adc $rd, $rn, $rm */
1070 0,
1071 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1072 },
1073 { /* AArch64_ADCXr, ARM64_INS_ADC: adc $rd, $rn, $rm */
1074 0,
1075 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1076 },
1077 { /* AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN: addhn.2s $rd, $rn, $rm */
1078 0,
1079 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1080 },
1081 { /* AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2: addhn2.4s $rd, $rn, $rm */
1082 0,
1083 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1084 },
1085 { /* AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN: addhn.4h $rd, $rn, $rm */
1086 0,
1087 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1088 },
1089 { /* AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2: addhn2.8h $rd, $rn, $rm */
1090 0,
1091 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1092 },
1093 { /* AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2: addhn2.16b $rd, $rn, $rm */
1094 0,
1095 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1096 },
1097 { /* AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN: addhn.8b $rd, $rn, $rm */
1098 0,
1099 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1100 },
1101 { /* AArch64_ADDPv16i8, ARM64_INS_ADDP: addp.16b $rd, $rn, $rm| */
1102 0,
1103 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1104 },
1105 { /* AArch64_ADDPv2i32, ARM64_INS_ADDP: addp.2s $rd, $rn, $rm| */
1106 0,
1107 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1108 },
1109 { /* AArch64_ADDPv2i64, ARM64_INS_ADDP: addp.2d $rd, $rn, $rm| */
1110 0,
1111 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1112 },
1113 { /* AArch64_ADDPv2i64p, ARM64_INS_ADDP: addp.2d $rd, $rn */
1114 0,
1115 { CS_OP_WRITE, CS_OP_READ, 0 }
1116 },
1117 { /* AArch64_ADDPv4i16, ARM64_INS_ADDP: addp.4h $rd, $rn, $rm| */
1118 0,
1119 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1120 },
1121 { /* AArch64_ADDPv4i32, ARM64_INS_ADDP: addp.4s $rd, $rn, $rm| */
1122 0,
1123 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1124 },
1125 { /* AArch64_ADDPv8i16, ARM64_INS_ADDP: addp.8h $rd, $rn, $rm| */
1126 0,
1127 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1128 },
1129 { /* AArch64_ADDPv8i8, ARM64_INS_ADDP: addp.8b $rd, $rn, $rm| */
1130 0,
1131 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1132 },
1133 { /* AArch64_ADDSWri, ARM64_INS_ADDS: adds $rd, $rn, $imm */
1134 0,
1135 { CS_OP_READ, CS_OP_READ, CS_OP_READ,0 }
1136 },
1137 { /* AArch64_ADDSWrs, ARM64_INS_ADDS: adds $rd, $rn, $rm */
1138 0,
1139 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1140 },
1141 { /* AArch64_ADDSWrx, ARM64_INS_ADDS: adds $r1, $r2, $r3 */
1142 0,
1143 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1144 },
1145 { /* AArch64_ADDSXri, ARM64_INS_ADDS: adds $rd, $rn, $imm */
1146 0,
1147 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1148 },
1149 { /* AArch64_ADDSXrs, ARM64_INS_ADDS: adds $rd, $rn, $rm */
1150 0,
1151 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1152 },
1153 { /* AArch64_ADDSXrx, ARM64_INS_ADDS: adds $r1, $r2, $r3 */
1154 0,
1155 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1156 },
1157 { /* AArch64_ADDSXrx64, ARM64_INS_ADDS: adds $rd, $rn, $rm$ext */
1158 0,
1159 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1160 },
1161 { /* AArch64_ADDVv16i8v, ARM64_INS_ADDV: addv.16b $rd, $rn */
1162 0,
1163 { CS_OP_WRITE, CS_OP_READ, 0 }
1164 },
1165 { /* AArch64_ADDVv4i16v, ARM64_INS_ADDV: addv.4h $rd, $rn */
1166 0,
1167 { CS_OP_WRITE, CS_OP_READ, 0 }
1168 },
1169 { /* AArch64_ADDVv4i32v, ARM64_INS_ADDV: addv.4s $rd, $rn */
1170 0,
1171 { CS_OP_WRITE, CS_OP_READ, 0 }
1172 },
1173 { /* AArch64_ADDVv8i16v, ARM64_INS_ADDV: addv.8h $rd, $rn */
1174 0,
1175 { CS_OP_WRITE, CS_OP_READ, 0 }
1176 },
1177 { /* AArch64_ADDVv8i8v, ARM64_INS_ADDV: addv.8b $rd, $rn */
1178 0,
1179 { CS_OP_WRITE, CS_OP_READ, 0 }
1180 },
1181 { /* AArch64_ADDWri, ARM64_INS_ADD: add $rd, $rn, $imm */
1182 0,
1183 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1184 },
1185 { /* AArch64_ADDWrs, ARM64_INS_ADD: add $rd, $rn, $rm */
1186 0,
1187 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1188 },
1189 { /* AArch64_ADDWrx, ARM64_INS_ADD: add $r1, $r2, $r3 */
1190 0,
1191 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1192 },
1193 { /* AArch64_ADDXri, ARM64_INS_ADD: add $rd, $rn, $imm */
1194 0,
1195 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1196 },
1197 { /* AArch64_ADDXrs, ARM64_INS_ADD: add $rd, $rn, $rm */
1198 0,
1199 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1200 },
1201 { /* AArch64_ADDXrx, ARM64_INS_ADD: add $r1, $r2, $r3 */
1202 0,
1203 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1204 },
1205 { /* AArch64_ADDXrx64, ARM64_INS_ADD: add $rd, $rn, $rm$ext */
1206 0,
1207 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1208 },
1209 { /* AArch64_ADDv16i8, ARM64_INS_ADD: add.16b $rd, $rn, $rm| */
1210 0,
1211 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1212 },
1213 { /* AArch64_ADDv1i64, ARM64_INS_ADD: add $rd, $rn, $rm */
1214 0,
1215 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1216 },
1217 { /* AArch64_ADDv2i32, ARM64_INS_ADD: add.2s $rd, $rn, $rm| */
1218 0,
1219 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1220 },
1221 { /* AArch64_ADDv2i64, ARM64_INS_ADD: add.2d $rd, $rn, $rm| */
1222 0,
1223 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1224 },
1225 { /* AArch64_ADDv4i16, ARM64_INS_ADD: add.4h $rd, $rn, $rm| */
1226 0,
1227 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1228 },
1229 { /* AArch64_ADDv4i32, ARM64_INS_ADD: add.4s $rd, $rn, $rm| */
1230 0,
1231 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1232 },
1233 { /* AArch64_ADDv8i16, ARM64_INS_ADD: add.8h $rd, $rn, $rm| */
1234 0,
1235 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1236 },
1237 { /* AArch64_ADDv8i8, ARM64_INS_ADD: add.8b $rd, $rn, $rm| */
1238 0,
1239 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1240 },
1241 { /* AArch64_ADR, ARM64_INS_ADR: adr $xd, $label */
1242 0,
1243 { CS_OP_WRITE, CS_OP_READ, 0 }
1244 },
1245 { /* AArch64_ADRP, ARM64_INS_ADRP: adrp $xd, $label */
1246 0,
1247 { CS_OP_WRITE, CS_OP_READ, 0 }
1248 },
1249 { /* AArch64_AESDrr, ARM64_INS_AESD: aesd.16b $rd, $rn */
1250 0,
1251 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, 0 }
1252 },
1253 { /* AArch64_AESErr, ARM64_INS_AESE: aese.16b $rd, $rn */
1254 0,
1255 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, 0 }
1256 },
1257 { /* AArch64_AESIMCrr, ARM64_INS_AESIMC: aesimc.16b $rd, $rn */
1258 0,
1259 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, 0 }
1260 },
1261 { /* AArch64_AESMCrr, ARM64_INS_AESMC: aesmc.16b $rd, $rn */
1262 0,
1263 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, 0 }
1264 },
1265 { /* AArch64_ANDSWri, ARM64_INS_ANDS: ands $rd, $rn, $imm */
1266 0,
1267 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1268 },
1269 { /* AArch64_ANDSWrs, ARM64_INS_ANDS: ands $rd, $rn, $rm */
1270 0,
1271 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1272 },
1273 { /* AArch64_ANDSXri, ARM64_INS_ANDS: ands $rd, $rn, $imm */
1274 0,
1275 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1276 },
1277 { /* AArch64_ANDSXrs, ARM64_INS_ANDS: ands $rd, $rn, $rm */
1278 0,
1279 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1280 },
1281 { /* AArch64_ANDWri, ARM64_INS_AND: and $rd, $rn, $imm */
1282 0,
1283 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1284 },
1285 { /* AArch64_ANDWrs, ARM64_INS_AND: and $rd, $rn, $rm */
1286 0,
1287 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1288 },
1289 { /* AArch64_ANDXri, ARM64_INS_AND: and $rd, $rn, $imm */
1290 0,
1291 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1292 },
1293 { /* AArch64_ANDXrs, ARM64_INS_AND: and $rd, $rn, $rm */
1294 0,
1295 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1296 },
1297 { /* AArch64_ANDv16i8, ARM64_INS_AND: and.16b $rd, $rn, $rm| */
1298 0,
1299 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1300 },
1301 { /* AArch64_ANDv8i8, ARM64_INS_AND: and.8b $rd, $rn, $rm| */
1302 0,
1303 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1304 },
1305 { /* AArch64_ASRVWr, ARM64_INS_ASR: asr $rd, $rn, $rm */
1306 0,
1307 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1308 },
1309 { /* AArch64_ASRVXr, ARM64_INS_ASR: asr $rd, $rn, $rm */
1310 0,
1311 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1312 },
1313 { /* AArch64_B, ARM64_INS_B: b $addr */
1314 0,
1315 { CS_OP_READ, 0 }
1316 },
1317 { /* AArch64_BFMWri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */
1318 0,
1319 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1320 },
1321 { /* AArch64_BFMXri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */
1322 0,
1323 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1324 },
1325 { /* AArch64_BICSWrs, ARM64_INS_BICS: bics $rd, $rn, $rm */
1326 0,
1327 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1328 },
1329 { /* AArch64_BICSXrs, ARM64_INS_BICS: bics $rd, $rn, $rm */
1330 0,
1331 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1332 },
1333 { /* AArch64_BICWrs, ARM64_INS_BIC: bic $rd, $rn, $rm */
1334 0,
1335 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1336 },
1337 { /* AArch64_BICXrs, ARM64_INS_BIC: bic $rd, $rn, $rm */
1338 0,
1339 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1340 },
1341 { /* AArch64_BICv16i8, ARM64_INS_BIC: bic.16b $rd, $rn, $rm| */
1342 0,
1343 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1344 },
1345 { /* AArch64_BICv2i32, ARM64_INS_BIC: bic.2s $rd, $imm8$shift */
1346 0,
1347 { CS_OP_WRITE, CS_OP_READ, 0 }
1348 },
1349 { /* AArch64_BICv4i16, ARM64_INS_BIC: bic.4h $rd, $imm8$shift */
1350 0,
1351 { CS_OP_WRITE, CS_OP_READ, 0 }
1352 },
1353 { /* AArch64_BICv4i32, ARM64_INS_BIC: bic.4s $rd, $imm8$shift */
1354 0,
1355 { CS_OP_WRITE, CS_OP_READ, 0 }
1356 },
1357 { /* AArch64_BICv8i16, ARM64_INS_BIC: bic.8h $rd, $imm8$shift */
1358 0,
1359 { CS_OP_WRITE, CS_OP_READ, 0 }
1360 },
1361 { /* AArch64_BICv8i8, ARM64_INS_BIC: bic.8b $rd, $rn, $rm| */
1362 0,
1363 { CS_OP_WRITE, CS_OP_READ, 0 }
1364 },
1365 { /* AArch64_BIFv16i8, ARM64_INS_BIF: bif.16b $rd, $rn, $rm| */
1366 0,
1367 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1368 },
1369 { /* AArch64_BIFv8i8, ARM64_INS_BIF: bif.8b $rd, $rn, $rm| */
1370 0,
1371 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1372 },
1373 { /* AArch64_BITv16i8, ARM64_INS_BIT: bit.16b $rd, $rn, $rm */
1374 0,
1375 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1376 },
1377 { /* AArch64_BITv8i8, ARM64_INS_BIT: bit.8b $rd, $rn, $rm */
1378 0,
1379 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1380 },
1381 { /* AArch64_BL, ARM64_INS_BL: bl $addr */
1382 0,
1383 { CS_OP_READ, 0 }
1384 },
1385 { /* AArch64_BLR, ARM64_INS_BLR: blr $rn */
1386 0,
1387 { CS_OP_READ, 0 }
1388 },
1389 { /* AArch64_BR, ARM64_INS_BR: br $rn */
1390 0,
1391 { CS_OP_READ, 0 }
1392 },
1393 { /* AArch64_BRK, ARM64_INS_BRK: brk $imm */
1394 0,
1395 { CS_OP_READ, 0 }
1396 },
1397 { /* AArch64_BSLv16i8, ARM64_INS_BSL: bsl.16b $rd, $rn, $rm */
1398 0,
1399 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1400 },
1401 { /* AArch64_BSLv8i8, ARM64_INS_BSL: bsl.8b $rd, $rn, $rm */
1402 0,
1403 { CS_OP_READ | CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1404 },
1405 { /* AArch64_Bcc, ARM64_INS_B: b.$cond $target */
1406 0,
1407 { CS_OP_READ, 0 }
1408 },
1409 { /* AArch64_CBNZW, ARM64_INS_CBNZ: cbnz $rt, $target */
1410 0,
1411 { CS_OP_READ, CS_OP_READ, 0 }
1412 },
1413 { /* AArch64_CBNZX, ARM64_INS_CBNZ: cbnz $rt, $target */
1414 0,
1415 { CS_OP_READ, CS_OP_READ, 0 }
1416 },
1417 { /* AArch64_CBZW, ARM64_INS_CBZ: cbz $rt, $target */
1418 0,
1419 { CS_OP_READ, CS_OP_READ, 0 }
1420 },
1421 { /* AArch64_CBZX, ARM64_INS_CBZ: cbz $rt, $target */
1422 0,
1423 { CS_OP_READ, CS_OP_READ, 0 }
1424 },
1425 { /* AArch64_CCMNWi, ARM64_INS_CCMN: ccmn $rn, $imm, $nzcv, $cond */
1426 0,
1427 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1428 },
1429 { /* AArch64_CCMNWr, ARM64_INS_CCMN: ccmn $rn, $rm, $nzcv, $cond */
1430 0,
1431 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1432 },
1433 { /* AArch64_CCMNXi, ARM64_INS_CCMN: ccmn $rn, $imm, $nzcv, $cond */
1434 0,
1435 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1436 },
1437 { /* AArch64_CCMNXr, ARM64_INS_CCMN: ccmn $rn, $rm, $nzcv, $cond */
1438 0,
1439 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1440 },
1441 { /* AArch64_CCMPWi, ARM64_INS_CCMP: ccmp $rn, $imm, $nzcv, $cond */
1442 0,
1443 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1444 },
1445 { /* AArch64_CCMPWr, ARM64_INS_CCMP: ccmp $rn, $rm, $nzcv, $cond */
1446 0,
1447 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1448 },
1449 { /* AArch64_CCMPXi, ARM64_INS_CCMP: ccmp $rn, $imm, $nzcv, $cond */
1450 0,
1451 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1452 },
1453 { /* AArch64_CCMPXr, ARM64_INS_CCMP: ccmp $rn, $rm, $nzcv, $cond */
1454 0,
1455 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1456 },
1457 { /* AArch64_CLREX, ARM64_INS_CLREX: clrex $crm */
1458 0,
1459 { CS_OP_READ, 0 }
1460 },
1461 { /* AArch64_CLSWr, ARM64_INS_CLS: cls $rd, $rn */
1462 0,
1463 { CS_OP_WRITE, CS_OP_READ, 0 }
1464 },
1465 { /* AArch64_CLSXr, ARM64_INS_CLS: cls $rd, $rn */
1466 0,
1467 { CS_OP_WRITE, CS_OP_READ, 0 }
1468 },
1469 { /* AArch64_CLSv16i8, ARM64_INS_CLS: cls.16b $rd, $rn */
1470 0,
1471 { CS_OP_WRITE, CS_OP_READ, 0 }
1472 },
1473 { /* AArch64_CLSv2i32, ARM64_INS_CLS: cls.2s $rd, $rn */
1474 0,
1475 { CS_OP_WRITE, CS_OP_READ, 0 }
1476 },
1477 { /* AArch64_CLSv4i16, ARM64_INS_CLS: cls.4h $rd, $rn */
1478 0,
1479 { CS_OP_WRITE, CS_OP_READ, 0 }
1480 },
1481 { /* AArch64_CLSv4i32, ARM64_INS_CLS: cls.4s $rd, $rn */
1482 0,
1483 { CS_OP_WRITE, CS_OP_READ, 0 }
1484 },
1485 { /* AArch64_CLSv8i16, ARM64_INS_CLS: cls.8h $rd, $rn */
1486 0,
1487 { CS_OP_WRITE, CS_OP_READ, 0 }
1488 },
1489 { /* AArch64_CLSv8i8, ARM64_INS_CLS: cls.8b $rd, $rn */
1490 0,
1491 { CS_OP_WRITE, CS_OP_READ, 0 }
1492 },
1493 { /* AArch64_CLZWr, ARM64_INS_CLZ: clz $rd, $rn */
1494 0,
1495 { CS_OP_WRITE, CS_OP_READ, 0 }
1496 },
1497 { /* AArch64_CLZXr, ARM64_INS_CLZ: clz $rd, $rn */
1498 0,
1499 { CS_OP_WRITE, CS_OP_READ, 0 }
1500 },
1501 { /* AArch64_CLZv16i8, ARM64_INS_CLZ: clz.16b $rd, $rn */
1502 0,
1503 { CS_OP_WRITE, CS_OP_READ, 0 }
1504 },
1505 { /* AArch64_CLZv2i32, ARM64_INS_CLZ: clz.2s $rd, $rn */
1506 0,
1507 { CS_OP_WRITE, CS_OP_READ, 0 }
1508 },
1509 { /* AArch64_CLZv4i16, ARM64_INS_CLZ: clz.4h $rd, $rn */
1510 0,
1511 { CS_OP_WRITE, CS_OP_READ, 0 }
1512 },
1513 { /* AArch64_CLZv4i32, ARM64_INS_CLZ: clz.4s $rd, $rn */
1514 0,
1515 { CS_OP_WRITE, CS_OP_READ, 0 }
1516 },
1517 { /* AArch64_CLZv8i16, ARM64_INS_CLZ: clz.8h $rd, $rn */
1518 0,
1519 { CS_OP_WRITE, CS_OP_READ, 0 }
1520 },
1521 { /* AArch64_CLZv8i8, ARM64_INS_CLZ: clz.8b $rd, $rn */
1522 0,
1523 { CS_OP_WRITE, CS_OP_READ, 0 }
1524 },
1525 { /* AArch64_CMEQv16i8, ARM64_INS_CMEQ: cmeq.16b $rd, $rn, $rm| */
1526 0,
1527 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1528 },
1529 { /* AArch64_CMEQv16i8rz, ARM64_INS_CMEQ: cmeq.16b $rd, $rn, #0 */
1530 0,
1531 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1532 },
1533 { /* AArch64_CMEQv1i64, ARM64_INS_CMEQ: cmeq $rd, $rn, $rm */
1534 0,
1535 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1536 },
1537 { /* AArch64_CMEQv1i64rz, ARM64_INS_CMEQ: cmeq $rd, $rn, #0 */
1538 0,
1539 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1540 },
1541 { /* AArch64_CMEQv2i32, ARM64_INS_CMEQ: cmeq.2s $rd, $rn, $rm| */
1542 0,
1543 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1544 },
1545 { /* AArch64_CMEQv2i32rz, ARM64_INS_CMEQ: cmeq.2s $rd, $rn, #0 */
1546 0,
1547 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1548 },
1549 { /* AArch64_CMEQv2i64, ARM64_INS_CMEQ: cmeq.2d $rd, $rn, $rm| */
1550 0,
1551 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1552 },
1553 { /* AArch64_CMEQv2i64rz, ARM64_INS_CMEQ: cmeq.2d $rd, $rn, #0 */
1554 0,
1555 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1556 },
1557 { /* AArch64_CMEQv4i16, ARM64_INS_CMEQ: cmeq.4h $rd, $rn, $rm| */
1558 0,
1559 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1560 },
1561 { /* AArch64_CMEQv4i16rz, ARM64_INS_CMEQ: cmeq.4h $rd, $rn, #0 */
1562 0,
1563 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1564 },
1565 { /* AArch64_CMEQv4i32, ARM64_INS_CMEQ: cmeq.4s $rd, $rn, $rm| */
1566 0,
1567 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1568 },
1569 { /* AArch64_CMEQv4i32rz, ARM64_INS_CMEQ: cmeq.4s $rd, $rn, #0 */
1570 0,
1571 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1572 },
1573 { /* AArch64_CMEQv8i16, ARM64_INS_CMEQ: cmeq.8h $rd, $rn, $rm| */
1574 0,
1575 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1576 },
1577 { /* AArch64_CMEQv8i16rz, ARM64_INS_CMEQ: cmeq.8h $rd, $rn, #0 */
1578 0,
1579 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1580 },
1581 { /* AArch64_CMEQv8i8, ARM64_INS_CMEQ: cmeq.8b $rd, $rn, $rm| */
1582 0,
1583 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1584 },
1585 { /* AArch64_CMEQv8i8rz, ARM64_INS_CMEQ: cmeq.8b $rd, $rn, #0 */
1586 0,
1587 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1588 },
1589 { /* AArch64_CMGEv16i8, ARM64_INS_CMGE: cmge.16b $rd, $rn, $rm| */
1590 0,
1591 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1592 },
1593 { /* AArch64_CMGEv16i8rz, ARM64_INS_CMGE: cmge.16b $rd, $rn, #0 */
1594 0,
1595 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1596 },
1597 { /* AArch64_CMGEv1i64, ARM64_INS_CMGE: cmge $rd, $rn, $rm */
1598 0,
1599 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1600 },
1601 { /* AArch64_CMGEv1i64rz, ARM64_INS_CMGE: cmge $rd, $rn, #0 */
1602 0,
1603 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1604 },
1605 { /* AArch64_CMGEv2i32, ARM64_INS_CMGE: cmge.2s $rd, $rn, $rm| */
1606 0,
1607 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1608 },
1609 { /* AArch64_CMGEv2i32rz, ARM64_INS_CMGE: cmge.2s $rd, $rn, #0 */
1610 0,
1611 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1612 },
1613 { /* AArch64_CMGEv2i64, ARM64_INS_CMGE: cmge.2d $rd, $rn, $rm| */
1614 0,
1615 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1616 },
1617 { /* AArch64_CMGEv2i64rz, ARM64_INS_CMGE: cmge.2d $rd, $rn, #0 */
1618 0,
1619 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1620 },
1621 { /* AArch64_CMGEv4i16, ARM64_INS_CMGE: cmge.4h $rd, $rn, $rm| */
1622 0,
1623 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1624 },
1625 { /* AArch64_CMGEv4i16rz, ARM64_INS_CMGE: cmge.4h $rd, $rn, #0 */
1626 0,
1627 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1628 },
1629 { /* AArch64_CMGEv4i32, ARM64_INS_CMGE: cmge.4s $rd, $rn, $rm| */
1630 0,
1631 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1632 },
1633 { /* AArch64_CMGEv4i32rz, ARM64_INS_CMGE: cmge.4s $rd, $rn, #0 */
1634 0,
1635 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1636 },
1637 { /* AArch64_CMGEv8i16, ARM64_INS_CMGE: cmge.8h $rd, $rn, $rm| */
1638 0,
1639 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1640 },
1641 { /* AArch64_CMGEv8i16rz, ARM64_INS_CMGE: cmge.8h $rd, $rn, #0 */
1642 0,
1643 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1644 },
1645 { /* AArch64_CMGEv8i8, ARM64_INS_CMGE: cmge.8b $rd, $rn, $rm| */
1646 0,
1647 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1648 },
1649 { /* AArch64_CMGEv8i8rz, ARM64_INS_CMGE: cmge.8b $rd, $rn, #0 */
1650 0,
1651 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1652 },
1653 { /* AArch64_CMGTv16i8, ARM64_INS_CMGT: cmgt.16b $rd, $rn, $rm| */
1654 0,
1655 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1656 },
1657 { /* AArch64_CMGTv16i8rz, ARM64_INS_CMGT: cmgt.16b $rd, $rn, #0 */
1658 0,
1659 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1660 },
1661 { /* AArch64_CMGTv1i64, ARM64_INS_CMGT: cmgt $rd, $rn, $rm */
1662 0,
1663 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1664 },
1665 { /* AArch64_CMGTv1i64rz, ARM64_INS_CMGT: cmgt $rd, $rn, #0 */
1666 0,
1667 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1668 },
1669 { /* AArch64_CMGTv2i32, ARM64_INS_CMGT: cmgt.2s $rd, $rn, $rm| */
1670 0,
1671 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1672 },
1673 { /* AArch64_CMGTv2i32rz, ARM64_INS_CMGT: cmgt.2s $rd, $rn, #0 */
1674 0,
1675 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1676 },
1677 { /* AArch64_CMGTv2i64, ARM64_INS_CMGT: cmgt.2d $rd, $rn, $rm| */
1678 0,
1679 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1680 },
1681 { /* AArch64_CMGTv2i64rz, ARM64_INS_CMGT: cmgt.2d $rd, $rn, #0 */
1682 0,
1683 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1684 },
1685 { /* AArch64_CMGTv4i16, ARM64_INS_CMGT: cmgt.4h $rd, $rn, $rm| */
1686 0,
1687 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1688 },
1689 { /* AArch64_CMGTv4i16rz, ARM64_INS_CMGT: cmgt.4h $rd, $rn, #0 */
1690 0,
1691 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1692 },
1693 { /* AArch64_CMGTv4i32, ARM64_INS_CMGT: cmgt.4s $rd, $rn, $rm| */
1694 0,
1695 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1696 },
1697 { /* AArch64_CMGTv4i32rz, ARM64_INS_CMGT: cmgt.4s $rd, $rn, #0 */
1698 0,
1699 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1700 },
1701 { /* AArch64_CMGTv8i16, ARM64_INS_CMGT: cmgt.8h $rd, $rn, $rm| */
1702 0,
1703 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1704 },
1705 { /* AArch64_CMGTv8i16rz, ARM64_INS_CMGT: cmgt.8h $rd, $rn, #0 */
1706 0,
1707 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1708 },
1709 { /* AArch64_CMGTv8i8, ARM64_INS_CMGT: cmgt.8b $rd, $rn, $rm| */
1710 0,
1711 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1712 },
1713 { /* AArch64_CMGTv8i8rz, ARM64_INS_CMGT: cmgt.8b $rd, $rn, #0 */
1714 0,
1715 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1716 },
1717 { /* AArch64_CMHIv16i8, ARM64_INS_CMHI: cmhi.16b $rd, $rn, $rm| */
1718 0,
1719 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1720 },
1721 { /* AArch64_CMHIv1i64, ARM64_INS_CMHI: cmhi $rd, $rn, $rm */
1722 0,
1723 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1724 },
1725 { /* AArch64_CMHIv2i32, ARM64_INS_CMHI: cmhi.2s $rd, $rn, $rm| */
1726 0,
1727 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1728 },
1729 { /* AArch64_CMHIv2i64, ARM64_INS_CMHI: cmhi.2d $rd, $rn, $rm| */
1730 0,
1731 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1732 },
1733 { /* AArch64_CMHIv4i16, ARM64_INS_CMHI: cmhi.4h $rd, $rn, $rm| */
1734 0,
1735 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1736 },
1737 { /* AArch64_CMHIv4i32, ARM64_INS_CMHI: cmhi.4s $rd, $rn, $rm| */
1738 0,
1739 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1740 },
1741 { /* AArch64_CMHIv8i16, ARM64_INS_CMHI: cmhi.8h $rd, $rn, $rm| */
1742 0,
1743 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1744 },
1745 { /* AArch64_CMHIv8i8, ARM64_INS_CMHI: cmhi.8b $rd, $rn, $rm| */
1746 0,
1747 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1748 },
1749 { /* AArch64_CMHSv16i8, ARM64_INS_CMHS: cmhs.16b $rd, $rn, $rm| */
1750 0,
1751 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1752 },
1753 { /* AArch64_CMHSv1i64, ARM64_INS_CMHS: cmhs $rd, $rn, $rm */
1754 0,
1755 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1756 },
1757 { /* AArch64_CMHSv2i32, ARM64_INS_CMHS: cmhs.2s $rd, $rn, $rm| */
1758 0,
1759 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1760 },
1761 { /* AArch64_CMHSv2i64, ARM64_INS_CMHS: cmhs.2d $rd, $rn, $rm| */
1762 0,
1763 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1764 },
1765 { /* AArch64_CMHSv4i16, ARM64_INS_CMHS: cmhs.4h $rd, $rn, $rm| */
1766 0,
1767 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1768 },
1769 { /* AArch64_CMHSv4i32, ARM64_INS_CMHS: cmhs.4s $rd, $rn, $rm| */
1770 0,
1771 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1772 },
1773 { /* AArch64_CMHSv8i16, ARM64_INS_CMHS: cmhs.8h $rd, $rn, $rm| */
1774 0,
1775 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1776 },
1777 { /* AArch64_CMHSv8i8, ARM64_INS_CMHS: cmhs.8b $rd, $rn, $rm| */
1778 0,
1779 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1780 },
1781 { /* AArch64_CMLEv16i8rz, ARM64_INS_CMLE: cmle.16b $rd, $rn, #0 */
1782 0,
1783 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1784 },
1785 { /* AArch64_CMLEv1i64rz, ARM64_INS_CMLE: cmle $rd, $rn, #0 */
1786 0,
1787 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1788 },
1789 { /* AArch64_CMLEv2i32rz, ARM64_INS_CMLE: cmle.2s $rd, $rn, #0 */
1790 0,
1791 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1792 },
1793 { /* AArch64_CMLEv2i64rz, ARM64_INS_CMLE: cmle.2d $rd, $rn, #0 */
1794 0,
1795 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1796 },
1797 { /* AArch64_CMLEv4i16rz, ARM64_INS_CMLE: cmle.4h $rd, $rn, #0 */
1798 0,
1799 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1800 },
1801 { /* AArch64_CMLEv4i32rz, ARM64_INS_CMLE: cmle.4s $rd, $rn, #0 */
1802 0,
1803 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1804 },
1805 { /* AArch64_CMLEv8i16rz, ARM64_INS_CMLE: cmle.8h $rd, $rn, #0 */
1806 0,
1807 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1808 },
1809 { /* AArch64_CMLEv8i8rz, ARM64_INS_CMLE: cmle.8b $rd, $rn, #0 */
1810 0,
1811 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1812 },
1813 { /* AArch64_CMLTv16i8rz, ARM64_INS_CMLT: cmlt.16b $rd, $rn, #0 */
1814 0,
1815 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1816 },
1817 { /* AArch64_CMLTv1i64rz, ARM64_INS_CMLT: cmlt $rd, $rn, #0 */
1818 0,
1819 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1820 },
1821 { /* AArch64_CMLTv2i32rz, ARM64_INS_CMLT: cmlt.2s $rd, $rn, #0 */
1822 0,
1823 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1824 },
1825 { /* AArch64_CMLTv2i64rz, ARM64_INS_CMLT: cmlt.2d $rd, $rn, #0 */
1826 0,
1827 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1828 },
1829 { /* AArch64_CMLTv4i16rz, ARM64_INS_CMLT: cmlt.4h $rd, $rn, #0 */
1830 0,
1831 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1832 },
1833 { /* AArch64_CMLTv4i32rz, ARM64_INS_CMLT: cmlt.4s $rd, $rn, #0 */
1834 0,
1835 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1836 },
1837 { /* AArch64_CMLTv8i16rz, ARM64_INS_CMLT: cmlt.8h $rd, $rn, #0 */
1838 0,
1839 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1840 },
1841 { /* AArch64_CMLTv8i8rz, ARM64_INS_CMLT: cmlt.8b $rd, $rn, #0 */
1842 0,
1843 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1844 },
1845 { /* AArch64_CMTSTv16i8, ARM64_INS_CMTST: cmtst.16b $rd, $rn, $rm| */
1846 0,
1847 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1848 },
1849 { /* AArch64_CMTSTv1i64, ARM64_INS_CMTST: cmtst $rd, $rn, $rm */
1850 0,
1851 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1852 },
1853 { /* AArch64_CMTSTv2i32, ARM64_INS_CMTST: cmtst.2s $rd, $rn, $rm| */
1854 0,
1855 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1856 },
1857 { /* AArch64_CMTSTv2i64, ARM64_INS_CMTST: cmtst.2d $rd, $rn, $rm| */
1858 0,
1859 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1860 },
1861 { /* AArch64_CMTSTv4i16, ARM64_INS_CMTST: cmtst.4h $rd, $rn, $rm| */
1862 0,
1863 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1864 },
1865 { /* AArch64_CMTSTv4i32, ARM64_INS_CMTST: cmtst.4s $rd, $rn, $rm| */
1866 0,
1867 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1868 },
1869 { /* AArch64_CMTSTv8i16, ARM64_INS_CMTST: cmtst.8h $rd, $rn, $rm| */
1870 0,
1871 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1872 },
1873 { /* AArch64_CMTSTv8i8, ARM64_INS_CMTST: cmtst.8b $rd, $rn, $rm| */
1874 0,
1875 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1876 },
1877 { /* AArch64_CNTv16i8, ARM64_INS_CNT: cnt.16b $rd, $rn */
1878 0,
1879 { CS_OP_WRITE, CS_OP_READ, 0 }
1880 },
1881 { /* AArch64_CNTv8i8, ARM64_INS_CNT: cnt.8b $rd, $rn */
1882 0,
1883 { CS_OP_WRITE, CS_OP_READ, 0 }
1884 },
1885 { /* AArch64_CPYi16, ARM64_INS_MOV: mov $dst, $src$idx */
1886 0,
1887 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1888 },
1889 { /* AArch64_CPYi32, ARM64_INS_MOV: mov $dst, $src$idx */
1890 0,
1891 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1892 },
1893 { /* AArch64_CPYi64, ARM64_INS_MOV: mov $dst, $src$idx */
1894 0,
1895 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1896 },
1897 { /* AArch64_CPYi8, ARM64_INS_MOV: mov $dst, $src$idx */
1898 0,
1899 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1900 },
1901 { /* AArch64_CRC32Brr, ARM64_INS_CRC32B: crc32b $rd, $rn, $rm */
1902 0,
1903 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1904 },
1905 { /* AArch64_CRC32CBrr, ARM64_INS_CRC32CB: crc32cb $rd, $rn, $rm */
1906 0,
1907 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1908 },
1909 { /* AArch64_CRC32CHrr, ARM64_INS_CRC32CH: crc32ch $rd, $rn, $rm */
1910 0,
1911 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1912 },
1913 { /* AArch64_CRC32CWrr, ARM64_INS_CRC32CW: crc32cw $rd, $rn, $rm */
1914 0,
1915 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1916 },
1917 { /* AArch64_CRC32CXrr, ARM64_INS_CRC32CX: crc32cx $rd, $rn, $rm */
1918 0,
1919 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1920 },
1921 { /* AArch64_CRC32Hrr, ARM64_INS_CRC32H: crc32h $rd, $rn, $rm */
1922 0,
1923 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1924 },
1925 { /* AArch64_CRC32Wrr, ARM64_INS_CRC32W: crc32w $rd, $rn, $rm */
1926 0,
1927 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1928 },
1929 { /* AArch64_CRC32Xrr, ARM64_INS_CRC32X: crc32x $rd, $rn, $rm */
1930 0,
1931 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1932 },
1933 { /* AArch64_CSELWr, ARM64_INS_CSEL: csel $rd, $rn, $rm, $cond */
1934 0,
1935 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1936 },
1937 { /* AArch64_CSELXr, ARM64_INS_CSEL: csel $rd, $rn, $rm, $cond */
1938 0,
1939 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1940 },
1941 { /* AArch64_CSINCWr, ARM64_INS_CSINC: csinc $rd, $rn, $rm, $cond */
1942 0,
1943 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1944 },
1945 { /* AArch64_CSINCXr, ARM64_INS_CSINC: csinc $rd, $rn, $rm, $cond */
1946 0,
1947 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1948 },
1949 { /* AArch64_CSINVWr, ARM64_INS_CSINV: csinv $rd, $rn, $rm, $cond */
1950 0,
1951 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1952 },
1953 { /* AArch64_CSINVXr, ARM64_INS_CSINV: csinv $rd, $rn, $rm, $cond */
1954 0,
1955 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1956 },
1957 { /* AArch64_CSNEGWr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */
1958 0,
1959 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1960 },
1961 { /* AArch64_CSNEGXr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */
1962 0,
1963 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
1964 },
1965 { /* AArch64_DCPS1, ARM64_INS_DCPS1: dcps1 $imm */
1966 0,
1967 { CS_OP_READ, 0 }
1968 },
1969 { /* AArch64_DCPS2, ARM64_INS_DCPS2: dcps2 $imm */
1970 0,
1971 { CS_OP_READ, 0 }
1972 },
1973 { /* AArch64_DCPS3, ARM64_INS_DCPS3: dcps3 $imm */
1974 0,
1975 { CS_OP_READ, 0 }
1976 },
1977 { /* AArch64_DMB, ARM64_INS_DMB: dmb $crm */
1978 0,
1979 { CS_OP_READ, 0 }
1980 },
1981 { /* AArch64_DRPS, ARM64_INS_DRPS: drps */
1982 0,
1983 { 0 }
1984 },
1985 { /* AArch64_DSB, ARM64_INS_DSB: dsb $crm */
1986 0,
1987 { CS_OP_READ, 0 }
1988 },
1989 { /* AArch64_DUPv16i8gpr, ARM64_INS_DUP: dup.16b $rd, $rn */
1990 0,
1991 { CS_OP_WRITE, CS_OP_READ, 0 }
1992 },
1993 { /* AArch64_DUPv16i8lane, ARM64_INS_DUP: dup.16b $rd, $rn$idx */
1994 0,
1995 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
1996 },
1997 { /* AArch64_DUPv2i32gpr, ARM64_INS_DUP: dup.2s $rd, $rn */
1998 0,
1999 { CS_OP_WRITE, CS_OP_READ, 0 }
2000 },
2001 { /* AArch64_DUPv2i32lane, ARM64_INS_DUP: dup.2s $rd, $rn$idx */
2002 0,
2003 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2004 },
2005 { /* AArch64_DUPv2i64gpr, ARM64_INS_DUP: dup.2d $rd, $rn */
2006 0,
2007 { CS_OP_WRITE, CS_OP_READ, 0 }
2008 },
2009 { /* AArch64_DUPv2i64lane, ARM64_INS_DUP: dup.2d $rd, $rn$idx */
2010 0,
2011 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2012 },
2013 { /* AArch64_DUPv4i16gpr, ARM64_INS_DUP: dup.4h $rd, $rn */
2014 0,
2015 { CS_OP_WRITE, CS_OP_READ, 0 }
2016 },
2017 { /* AArch64_DUPv4i16lane, ARM64_INS_DUP: dup.4h $rd, $rn$idx */
2018 0,
2019 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2020 },
2021 { /* AArch64_DUPv4i32gpr, ARM64_INS_DUP: dup.4s $rd, $rn */
2022 0,
2023 { CS_OP_WRITE, CS_OP_READ, 0 }
2024 },
2025 { /* AArch64_DUPv4i32lane, ARM64_INS_DUP: dup.4s $rd, $rn$idx */
2026 0,
2027 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2028 },
2029 { /* AArch64_DUPv8i16gpr, ARM64_INS_DUP: dup.8h $rd, $rn */
2030 0,
2031 { CS_OP_WRITE, CS_OP_READ, 0 }
2032 },
2033 { /* AArch64_DUPv8i16lane, ARM64_INS_DUP: dup.8h $rd, $rn$idx */
2034 0,
2035 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2036 },
2037 { /* AArch64_DUPv8i8gpr, ARM64_INS_DUP: dup.8b $rd, $rn */
2038 0,
2039 { CS_OP_WRITE, CS_OP_READ, 0 }
2040 },
2041 { /* AArch64_DUPv8i8lane, ARM64_INS_DUP: dup.8b $rd, $rn$idx */
2042 0,
2043 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2044 },
2045 { /* AArch64_EONWrs, ARM64_INS_EON: eon $rd, $rn, $rm */
2046 0,
2047 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2048 },
2049 { /* AArch64_EONXrs, ARM64_INS_EON: eon $rd, $rn, $rm */
2050 0,
2051 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2052 },
2053 { /* AArch64_EORWri, ARM64_INS_EOR: eor $rd, $rn, $imm */
2054 0,
2055 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2056 },
2057 { /* AArch64_EORWrs, ARM64_INS_EOR: eor $rd, $rn, $rm */
2058 0,
2059 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2060 },
2061 { /* AArch64_EORXri, ARM64_INS_EOR: eor $rd, $rn, $imm */
2062 0,
2063 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2064 },
2065 { /* AArch64_EORXrs, ARM64_INS_EOR: eor $rd, $rn, $rm */
2066 0,
2067 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2068 },
2069 { /* AArch64_EORv16i8, ARM64_INS_EOR: eor.16b $rd, $rn, $rm| */
2070 0,
2071 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2072 },
2073 { /* AArch64_EORv8i8, ARM64_INS_EOR: eor.8b $rd, $rn, $rm| */
2074 0,
2075 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2076 },
2077 { /* AArch64_ERET, ARM64_INS_ERET: eret */
2078 0,
2079 { 0 }
2080 },
2081 { /* AArch64_EXTRWrri, ARM64_INS_EXTR: extr $rd, $rn, $rm, $imm */
2082 0,
2083 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
2084 },
2085 { /* AArch64_EXTRXrri, ARM64_INS_EXTR: extr $rd, $rn, $rm, $imm */
2086 0,
2087 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
2088 },
2089 { /* AArch64_EXTv16i8, ARM64_INS_EXT: ext.16b $rd, $rn, $rm, $imm */
2090 0,
2091 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
2092 },
2093 { /* AArch64_EXTv8i8, ARM64_INS_EXT: ext.8b $rd, $rn, $rm, $imm */
2094 0,
2095 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
2096 },
2097 { /* AArch64_FABD32, ARM64_INS_FABD: fabd $rd, $rn, $rm */
2098 0,
2099 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2100 },
2101 { /* AArch64_FABD64, ARM64_INS_FABD: fabd $rd, $rn, $rm */
2102 0,
2103 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2104 },
2105 { /* AArch64_FABDv2f32, ARM64_INS_FABD: fabd.2s $rd, $rn, $rm| */
2106 0,
2107 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2108 },
2109 { /* AArch64_FABDv2f64, ARM64_INS_FABD: fabd.2d $rd, $rn, $rm| */
2110 0,
2111 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2112 },
2113 { /* AArch64_FABDv4f32, ARM64_INS_FABD: fabd.4s $rd, $rn, $rm| */
2114 0,
2115 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2116 },
2117 { /* AArch64_FABSDr, ARM64_INS_FABS: fabs $rd, $rn */
2118 0,
2119 { CS_OP_WRITE, CS_OP_READ, 0 }
2120 },
2121 { /* AArch64_FABSSr, ARM64_INS_FABS: fabs $rd, $rn */
2122 0,
2123 { CS_OP_WRITE, CS_OP_READ, 0 }
2124 },
2125 { /* AArch64_FABSv2f32, ARM64_INS_FABS: fabs.2s $rd, $rn */
2126 0,
2127 { CS_OP_WRITE, CS_OP_READ, 0 }
2128 },
2129 { /* AArch64_FABSv2f64, ARM64_INS_FABS: fabs.2d $rd, $rn */
2130 0,
2131 { CS_OP_WRITE, CS_OP_READ, 0 }
2132 },
2133 { /* AArch64_FABSv4f32, ARM64_INS_FABS: fabs.4s $rd, $rn */
2134 0,
2135 { CS_OP_WRITE, CS_OP_READ, 0 }
2136 },
2137 { /* AArch64_FACGE32, ARM64_INS_FACGE: facge $rd, $rn, $rm */
2138 0,
2139 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2140 },
2141 { /* AArch64_FACGE64, ARM64_INS_FACGE: facge $rd, $rn, $rm */
2142 0,
2143 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2144 },
2145 { /* AArch64_FACGEv2f32, ARM64_INS_FACGE: facge.2s $rd, $rn, $rm| */
2146 0,
2147 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2148 },
2149 { /* AArch64_FACGEv2f64, ARM64_INS_FACGE: facge.2d $rd, $rn, $rm| */
2150 0,
2151 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2152 },
2153 { /* AArch64_FACGEv4f32, ARM64_INS_FACGE: facge.4s $rd, $rn, $rm| */
2154 0,
2155 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2156 },
2157 { /* AArch64_FACGT32, ARM64_INS_FACGT: facgt $rd, $rn, $rm */
2158 0,
2159 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2160 },
2161 { /* AArch64_FACGT64, ARM64_INS_FACGT: facgt $rd, $rn, $rm */
2162 0,
2163 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2164 },
2165 { /* AArch64_FACGTv2f32, ARM64_INS_FACGT: facgt.2s $rd, $rn, $rm| */
2166 0,
2167 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2168 },
2169 { /* AArch64_FACGTv2f64, ARM64_INS_FACGT: facgt.2d $rd, $rn, $rm| */
2170 0,
2171 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2172 },
2173 { /* AArch64_FACGTv4f32, ARM64_INS_FACGT: facgt.4s $rd, $rn, $rm| */
2174 0,
2175 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2176 },
2177 { /* AArch64_FADDDrr, ARM64_INS_FADD: fadd $rd, $rn, $rm */
2178 0,
2179 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2180 },
2181 { /* AArch64_FADDPv2f32, ARM64_INS_FADDP: faddp.2s $rd, $rn, $rm| */
2182 0,
2183 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2184 },
2185 { /* AArch64_FADDPv2f64, ARM64_INS_FADDP: faddp.2d $rd, $rn, $rm| */
2186 0,
2187 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2188 },
2189 { /* AArch64_FADDPv2i32p, ARM64_INS_FADDP: faddp.2s $rd, $rn */
2190 0,
2191 { CS_OP_WRITE, CS_OP_READ, 0 }
2192 },
2193 { /* AArch64_FADDPv2i64p, ARM64_INS_FADDP: faddp.2d $rd, $rn */
2194 0,
2195 { CS_OP_WRITE, CS_OP_READ, 0 }
2196 },
2197 { /* AArch64_FADDPv4f32, ARM64_INS_FADDP: faddp.4s $rd, $rn, $rm| */
2198 0,
2199 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2200 },
2201 { /* AArch64_FADDSrr, ARM64_INS_FADD: fadd $rd, $rn, $rm */
2202 0,
2203 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2204 },
2205 { /* AArch64_FADDv2f32, ARM64_INS_FADD: fadd.2s $rd, $rn, $rm| */
2206 0,
2207 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2208 },
2209 { /* AArch64_FADDv2f64, ARM64_INS_FADD: fadd.2d $rd, $rn, $rm| */
2210 0,
2211 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2212 },
2213 { /* AArch64_FADDv4f32, ARM64_INS_FADD: fadd.4s $rd, $rn, $rm| */
2214 0,
2215 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2216 },
2217 { /* AArch64_FCCMPDrr, ARM64_INS_FCCMP: fccmp $rn, $rm, $nzcv, $cond */
2218 0,
2219 { CS_OP_READ, CS_OP_READ, CS_OP_WRITE, CS_OP_READ, 0 }
2220 },
2221 { /* AArch64_FCCMPEDrr, ARM64_INS_FCCMPE: fccmpe $rn, $rm, $nzcv, $cond */
2222 0,
2223 { CS_OP_READ, CS_OP_READ, CS_OP_WRITE, CS_OP_READ, 0 }
2224 },
2225 { /* AArch64_FCCMPESrr, ARM64_INS_FCCMPE: fccmpe $rn, $rm, $nzcv, $cond */
2226 0,
2227 { CS_OP_READ, CS_OP_READ, CS_OP_WRITE, CS_OP_READ, 0 }
2228 },
2229 { /* AArch64_FCCMPSrr, ARM64_INS_FCCMP: fccmp $rn, $rm, $nzcv, $cond */
2230 0,
2231 { CS_OP_READ, CS_OP_READ, CS_OP_WRITE, CS_OP_READ, 0 }
2232 },
2233 { /* AArch64_FCMEQ32, ARM64_INS_FCMEQ: fcmeq $rd, $rn, $rm */
2234 0,
2235 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2236 },
2237 { /* AArch64_FCMEQ64, ARM64_INS_FCMEQ: fcmeq $rd, $rn, $rm */
2238 0,
2239 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2240 },
2241 { /* AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ: fcmeq $rd, $rn, #0.0 */
2242 0,
2243 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2244 },
2245 { /* AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ: fcmeq $rd, $rn, #0.0 */
2246 0,
2247 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2248 },
2249 { /* AArch64_FCMEQv2f32, ARM64_INS_FCMEQ: fcmeq.2s $rd, $rn, $rm| */
2250 0,
2251 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2252 },
2253 { /* AArch64_FCMEQv2f64, ARM64_INS_FCMEQ: fcmeq.2d $rd, $rn, $rm| */
2254 0,
2255 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2256 },
2257 { /* AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ: fcmeq.2s $rd, $rn, #0.0 */
2258 0,
2259 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2260 },
2261 { /* AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ: fcmeq.2d $rd, $rn, #0.0 */
2262 0,
2263 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2264 },
2265 { /* AArch64_FCMEQv4f32, ARM64_INS_FCMEQ: fcmeq.4s $rd, $rn, $rm| */
2266 0,
2267 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2268 },
2269 { /* AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ: fcmeq.4s $rd, $rn, #0.0 */
2270 0,
2271 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2272 },
2273 { /* AArch64_FCMGE32, ARM64_INS_FCMGE: fcmge $rd, $rn, $rm */
2274 0,
2275 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2276 },
2277 { /* AArch64_FCMGE64, ARM64_INS_FCMGE: fcmge $rd, $rn, $rm */
2278 0,
2279 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2280 },
2281 { /* AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE: fcmge $rd, $rn, #0.0 */
2282 0,
2283 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2284 },
2285 { /* AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE: fcmge $rd, $rn, #0.0 */
2286 0,
2287 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2288 },
2289 { /* AArch64_FCMGEv2f32, ARM64_INS_FCMGE: fcmge.2s $rd, $rn, $rm| */
2290 0,
2291 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2292 },
2293 { /* AArch64_FCMGEv2f64, ARM64_INS_FCMGE: fcmge.2d $rd, $rn, $rm| */
2294 0,
2295 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2296 },
2297 { /* AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE: fcmge.2s $rd, $rn, #0.0 */
2298 0,
2299 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2300 },
2301 { /* AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE: fcmge.2d $rd, $rn, #0.0 */
2302 0,
2303 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2304 },
2305 { /* AArch64_FCMGEv4f32, ARM64_INS_FCMGE: fcmge.4s $rd, $rn, $rm| */
2306 0,
2307 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2308 },
2309 { /* AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE: fcmge.4s $rd, $rn, #0.0 */
2310 0,
2311 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2312 },
2313 { /* AArch64_FCMGT32, ARM64_INS_FCMGT: fcmgt $rd, $rn, $rm */
2314 0,
2315 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2316 },
2317 { /* AArch64_FCMGT64, ARM64_INS_FCMGT: fcmgt $rd, $rn, $rm */
2318 0,
2319 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2320 },
2321 { /* AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT: fcmgt $rd, $rn, #0.0 */
2322 0,
2323 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2324 },
2325 { /* AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT: fcmgt $rd, $rn, #0.0 */
2326 0,
2327 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2328 },
2329 { /* AArch64_FCMGTv2f32, ARM64_INS_FCMGT: fcmgt.2s $rd, $rn, $rm| */
2330 0,
2331 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2332 },
2333 { /* AArch64_FCMGTv2f64, ARM64_INS_FCMGT: fcmgt.2d $rd, $rn, $rm| */
2334 0,
2335 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2336 },
2337 { /* AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT: fcmgt.2s $rd, $rn, #0.0 */
2338 0,
2339 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2340 },
2341 { /* AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT: fcmgt.2d $rd, $rn, #0.0 */
2342 0,
2343 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2344 },
2345 { /* AArch64_FCMGTv4f32, ARM64_INS_FCMGT: fcmgt.4s $rd, $rn, $rm| */
2346 0,
2347 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2348 },
2349 { /* AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT: fcmgt.4s $rd, $rn, #0.0 */
2350 0,
2351 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2352 },
2353 { /* AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE: fcmle $rd, $rn, #0.0 */
2354 0,
2355 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2356 },
2357 { /* AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE: fcmle $rd, $rn, #0.0 */
2358 0,
2359 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2360 },
2361 { /* AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE: fcmle.2s $rd, $rn, #0.0 */
2362 0,
2363 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2364 },
2365 { /* AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE: fcmle.2d $rd, $rn, #0.0 */
2366 0,
2367 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2368 },
2369 { /* AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE: fcmle.4s $rd, $rn, #0.0 */
2370 0,
2371 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2372 },
2373 { /* AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT: fcmlt $rd, $rn, #0.0 */
2374 0,
2375 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2376 },
2377 { /* AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT: fcmlt $rd, $rn, #0.0 */
2378 0,
2379 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2380 },
2381 { /* AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT: fcmlt.2s $rd, $rn, #0.0 */
2382 0,
2383 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2384 },
2385 { /* AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT: fcmlt.2d $rd, $rn, #0.0 */
2386 0,
2387 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2388 },
2389 { /* AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT: fcmlt.4s $rd, $rn, #0.0 */
2390 0,
2391 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2392 },
2393 { /* AArch64_FCMPDri, ARM64_INS_FCMP: fcmp $rn, #0.0 */
2394 0,
2395 { CS_OP_READ, CS_OP_READ, 0 }
2396 },
2397 { /* AArch64_FCMPDrr, ARM64_INS_FCMP: fcmp $rn, $rm */
2398 0,
2399 { CS_OP_READ, CS_OP_READ, 0 }
2400 },
2401 { /* AArch64_FCMPEDri, ARM64_INS_FCMPE: fcmpe $rn, #0.0 */
2402 0,
2403 { CS_OP_READ, CS_OP_READ, 0 }
2404 },
2405 { /* AArch64_FCMPEDrr, ARM64_INS_FCMPE: fcmpe $rn, $rm */
2406 0,
2407 { CS_OP_READ, CS_OP_READ, 0 }
2408 },
2409 { /* AArch64_FCMPESri, ARM64_INS_FCMPE: fcmpe $rn, #0.0 */
2410 0,
2411 { CS_OP_READ, CS_OP_READ, 0 }
2412 },
2413 { /* AArch64_FCMPESrr, ARM64_INS_FCMPE: fcmpe $rn, $rm */
2414 0,
2415 { CS_OP_READ, CS_OP_READ, 0 }
2416 },
2417 { /* AArch64_FCMPSri, ARM64_INS_FCMP: fcmp $rn, #0.0 */
2418 0,
2419 { CS_OP_READ, CS_OP_READ, 0 }
2420 },
2421 { /* AArch64_FCMPSrr, ARM64_INS_FCMP: fcmp $rn, $rm */
2422 0,
2423 { CS_OP_READ, CS_OP_READ, 0 }
2424 },
2425 { /* AArch64_FCSELDrrr, ARM64_INS_FCSEL: fcsel $rd, $rn, $rm, $cond */
2426 0,
2427 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
2428 },
2429 { /* AArch64_FCSELSrrr, ARM64_INS_FCSEL: fcsel $rd, $rn, $rm, $cond */
2430 0,
2431 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
2432 },
2433 { /* AArch64_FCVTASUWDr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */
2434 0,
2435 { CS_OP_WRITE, CS_OP_READ, 0 }
2436 },
2437 { /* AArch64_FCVTASUWSr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */
2438 0,
2439 { CS_OP_WRITE, CS_OP_READ, 0 }
2440 },
2441 { /* AArch64_FCVTASUXDr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */
2442 0,
2443 { CS_OP_WRITE, CS_OP_READ, 0 }
2444 },
2445 { /* AArch64_FCVTASUXSr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */
2446 0,
2447 { CS_OP_WRITE, CS_OP_READ, 0 }
2448 },
2449 { /* AArch64_FCVTASv1i32, ARM64_INS_FCVTAS: fcvtas $rd, $rn */
2450 0,
2451 { CS_OP_WRITE, CS_OP_READ, 0 }
2452 },
2453 { /* AArch64_FCVTASv1i64, ARM64_INS_FCVTAS: fcvtas $rd, $rn */
2454 0,
2455 { CS_OP_WRITE, CS_OP_READ, 0 }
2456 },
2457 { /* AArch64_FCVTASv2f32, ARM64_INS_FCVTAS: fcvtas.2s $rd, $rn */
2458 0,
2459 { CS_OP_WRITE, CS_OP_READ, 0 }
2460 },
2461 { /* AArch64_FCVTASv2f64, ARM64_INS_FCVTAS: fcvtas.2d $rd, $rn */
2462 0,
2463 { CS_OP_WRITE, CS_OP_READ, 0 }
2464 },
2465 { /* AArch64_FCVTASv4f32, ARM64_INS_FCVTAS: fcvtas.4s $rd, $rn */
2466 0,
2467 { CS_OP_WRITE, CS_OP_READ, 0 }
2468 },
2469 { /* AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */
2470 0,
2471 { CS_OP_WRITE, CS_OP_READ, 0 }
2472 },
2473 { /* AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */
2474 0,
2475 { CS_OP_WRITE, CS_OP_READ, 0 }
2476 },
2477 { /* AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */
2478 0,
2479 { CS_OP_WRITE, CS_OP_READ, 0 }
2480 },
2481 { /* AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */
2482 0,
2483 { CS_OP_WRITE, CS_OP_READ, 0 }
2484 },
2485 { /* AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU: fcvtau $rd, $rn */
2486 0,
2487 { CS_OP_WRITE, CS_OP_READ, 0 }
2488 },
2489 { /* AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU: fcvtau $rd, $rn */
2490 0,
2491 { CS_OP_WRITE, CS_OP_READ, 0 }
2492 },
2493 { /* AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU: fcvtau.2s $rd, $rn */
2494 0,
2495 { CS_OP_WRITE, CS_OP_READ, 0 }
2496 },
2497 { /* AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU: fcvtau.2d $rd, $rn */
2498 0,
2499 { CS_OP_WRITE, CS_OP_READ, 0 }
2500 },
2501 { /* AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU: fcvtau.4s $rd, $rn */
2502 0,
2503 { CS_OP_WRITE, CS_OP_READ, 0 }
2504 },
2505 { /* AArch64_FCVTDHr, ARM64_INS_FCVT: fcvt $rd, $rn */
2506 0,
2507 { CS_OP_WRITE, CS_OP_READ, 0 }
2508 },
2509 { /* AArch64_FCVTDSr, ARM64_INS_FCVT: fcvt $rd, $rn */
2510 0,
2511 { CS_OP_WRITE, CS_OP_READ, 0 }
2512 },
2513 { /* AArch64_FCVTHDr, ARM64_INS_FCVT: fcvt $rd, $rn */
2514 0,
2515 { CS_OP_WRITE, CS_OP_READ, 0 }
2516 },
2517 { /* AArch64_FCVTHSr, ARM64_INS_FCVT: fcvt $rd, $rn */
2518 0,
2519 { CS_OP_WRITE, CS_OP_READ, 0 }
2520 },
2521 { /* AArch64_FCVTLv2i32, ARM64_INS_FCVTL: fcvtl $rd.2d, $rn.2s */
2522 0,
2523 { CS_OP_WRITE, CS_OP_READ, 0 }
2524 },
2525 { /* AArch64_FCVTLv4i16, ARM64_INS_FCVTL: fcvtl $rd.4s, $rn.4h */
2526 0,
2527 { CS_OP_WRITE, CS_OP_READ, 0 }
2528 },
2529 { /* AArch64_FCVTLv4i32, ARM64_INS_FCVTL2: fcvtl2 $rd.2d, $rn.4s */
2530 0,
2531 { CS_OP_WRITE, CS_OP_READ, 0 }
2532 },
2533 { /* AArch64_FCVTLv8i16, ARM64_INS_FCVTL2: fcvtl2 $rd.4s, $rn.8h */
2534 0,
2535 { CS_OP_WRITE, CS_OP_READ, 0 }
2536 },
2537 { /* AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */
2538 0,
2539 { CS_OP_WRITE, CS_OP_READ, 0 }
2540 },
2541 { /* AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */
2542 0,
2543 { CS_OP_WRITE, CS_OP_READ, 0 }
2544 },
2545 { /* AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */
2546 0,
2547 { CS_OP_WRITE, CS_OP_READ, 0 }
2548 },
2549 { /* AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */
2550 0,
2551 { CS_OP_WRITE, CS_OP_READ, 0 }
2552 },
2553 { /* AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS: fcvtms $rd, $rn */
2554 0,
2555 { CS_OP_WRITE, CS_OP_READ, 0 }
2556 },
2557 { /* AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS: fcvtms $rd, $rn */
2558 0,
2559 { CS_OP_WRITE, CS_OP_READ, 0 }
2560 },
2561 { /* AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS: fcvtms.2s $rd, $rn */
2562 0,
2563 { CS_OP_WRITE, CS_OP_READ, 0 }
2564 },
2565 { /* AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS: fcvtms.2d $rd, $rn */
2566 0,
2567 { CS_OP_WRITE, CS_OP_READ, 0 }
2568 },
2569 { /* AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS: fcvtms.4s $rd, $rn */
2570 0,
2571 { CS_OP_WRITE, CS_OP_READ, 0 }
2572 },
2573 { /* AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */
2574 0,
2575 { CS_OP_WRITE, CS_OP_READ, 0 }
2576 },
2577 { /* AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */
2578 0,
2579 { CS_OP_WRITE, CS_OP_READ, 0 }
2580 },
2581 { /* AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */
2582 0,
2583 { CS_OP_WRITE, CS_OP_READ, 0 }
2584 },
2585 { /* AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */
2586 0,
2587 { CS_OP_WRITE, CS_OP_READ, 0 }
2588 },
2589 { /* AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */
2590 0,
2591 { CS_OP_WRITE, CS_OP_READ, 0 }
2592 },
2593 { /* AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */
2594 0,
2595 { CS_OP_WRITE, CS_OP_READ, 0 }
2596 },
2597 { /* AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU: fcvtmu.2s $rd, $rn */
2598 0,
2599 { CS_OP_WRITE, CS_OP_READ, 0 }
2600 },
2601 { /* AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU: fcvtmu.2d $rd, $rn */
2602 0,
2603 { CS_OP_WRITE, CS_OP_READ, 0 }
2604 },
2605 { /* AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU: fcvtmu.4s $rd, $rn */
2606 0,
2607 { CS_OP_WRITE, CS_OP_READ, 0 }
2608 },
2609 { /* AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */
2610 0,
2611 { CS_OP_WRITE, CS_OP_READ, 0 }
2612 },
2613 { /* AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */
2614 0,
2615 { CS_OP_WRITE, CS_OP_READ, 0 }
2616 },
2617 { /* AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */
2618 0,
2619 { CS_OP_WRITE, CS_OP_READ, 0 }
2620 },
2621 { /* AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */
2622 0,
2623 { CS_OP_WRITE, CS_OP_READ, 0 }
2624 },
2625 { /* AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS: fcvtns $rd, $rn */
2626 0,
2627 { CS_OP_WRITE, CS_OP_READ, 0 }
2628 },
2629 { /* AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS: fcvtns $rd, $rn */
2630 0,
2631 { CS_OP_WRITE, CS_OP_READ, 0 }
2632 },
2633 { /* AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS: fcvtns.2s $rd, $rn */
2634 0,
2635 { CS_OP_WRITE, CS_OP_READ, 0 }
2636 },
2637 { /* AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS: fcvtns.2d $rd, $rn */
2638 0,
2639 { CS_OP_WRITE, CS_OP_READ, 0 }
2640 },
2641 { /* AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS: fcvtns.4s $rd, $rn */
2642 0,
2643 { CS_OP_WRITE, CS_OP_READ, 0 }
2644 },
2645 { /* AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */
2646 0,
2647 { CS_OP_WRITE, CS_OP_READ, 0 }
2648 },
2649 { /* AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */
2650 0,
2651 { CS_OP_WRITE, CS_OP_READ, 0 }
2652 },
2653 { /* AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */
2654 0,
2655 { CS_OP_WRITE, CS_OP_READ, 0 }
2656 },
2657 { /* AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */
2658 0,
2659 { CS_OP_WRITE, CS_OP_READ, 0 }
2660 },
2661 { /* AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */
2662 0,
2663 { CS_OP_WRITE, CS_OP_READ, 0 }
2664 },
2665 { /* AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */
2666 0,
2667 { CS_OP_WRITE, CS_OP_READ, 0 }
2668 },
2669 { /* AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU: fcvtnu.2s $rd, $rn */
2670 0,
2671 { CS_OP_WRITE, CS_OP_READ, 0 }
2672 },
2673 { /* AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU: fcvtnu.2d $rd, $rn */
2674 0,
2675 { CS_OP_WRITE, CS_OP_READ, 0 }
2676 },
2677 { /* AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU: fcvtnu.4s $rd, $rn */
2678 0,
2679 { CS_OP_WRITE, CS_OP_READ, 0 }
2680 },
2681 { /* AArch64_FCVTNv2i32, ARM64_INS_FCVTN: fcvtn $rd.2s, $rn.2d */
2682 0,
2683 { CS_OP_WRITE, CS_OP_READ, 0 }
2684 },
2685 { /* AArch64_FCVTNv4i16, ARM64_INS_FCVTN: fcvtn $rd.4h, $rn.4s */
2686 0,
2687 { CS_OP_WRITE, CS_OP_READ, 0 }
2688 },
2689 { /* AArch64_FCVTNv4i32, ARM64_INS_FCVTN2: fcvtn2 $rd.4s, $rn.2d */
2690 0,
2691 { CS_OP_WRITE, CS_OP_READ, 0 }
2692 },
2693 { /* AArch64_FCVTNv8i16, ARM64_INS_FCVTN2: fcvtn2 $rd.8h, $rn.4s */
2694 0,
2695 { CS_OP_WRITE, CS_OP_READ, 0 }
2696 },
2697 { /* AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */
2698 0,
2699 { CS_OP_WRITE, CS_OP_READ, 0 }
2700 },
2701 { /* AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */
2702 0,
2703 { CS_OP_WRITE, CS_OP_READ, 0 }
2704 },
2705 { /* AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */
2706 0,
2707 { CS_OP_WRITE, CS_OP_READ, 0 }
2708 },
2709 { /* AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */
2710 0,
2711 { CS_OP_WRITE, CS_OP_READ, 0 }
2712 },
2713 { /* AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS: fcvtps $rd, $rn */
2714 0,
2715 { CS_OP_WRITE, CS_OP_READ, 0 }
2716 },
2717 { /* AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS: fcvtps $rd, $rn */
2718 0,
2719 { CS_OP_WRITE, CS_OP_READ, 0 }
2720 },
2721 { /* AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS: fcvtps.2s $rd, $rn */
2722 0,
2723 { CS_OP_WRITE, CS_OP_READ, 0 }
2724 },
2725 { /* AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS: fcvtps.2d $rd, $rn */
2726 0,
2727 { CS_OP_WRITE, CS_OP_READ, 0 }
2728 },
2729 { /* AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS: fcvtps.4s $rd, $rn */
2730 0,
2731 { CS_OP_WRITE, CS_OP_READ, 0 }
2732 },
2733 { /* AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */
2734 0,
2735 { CS_OP_WRITE, CS_OP_READ, 0 }
2736 },
2737 { /* AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */
2738 0,
2739 { CS_OP_WRITE, CS_OP_READ, 0 }
2740 },
2741 { /* AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */
2742 0,
2743 { CS_OP_WRITE, CS_OP_READ, 0 }
2744 },
2745 { /* AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */
2746 0,
2747 { CS_OP_WRITE, CS_OP_READ, 0 }
2748 },
2749 { /* AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */
2750 0,
2751 { CS_OP_WRITE, CS_OP_READ, 0 }
2752 },
2753 { /* AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */
2754 0,
2755 { CS_OP_WRITE, CS_OP_READ, 0 }
2756 },
2757 { /* AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU: fcvtpu.2s $rd, $rn */
2758 0,
2759 { CS_OP_WRITE, CS_OP_READ, 0 }
2760 },
2761 { /* AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU: fcvtpu.2d $rd, $rn */
2762 0,
2763 { CS_OP_WRITE, CS_OP_READ, 0 }
2764 },
2765 { /* AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU: fcvtpu.4s $rd, $rn */
2766 0,
2767 { CS_OP_WRITE, CS_OP_READ, 0 }
2768 },
2769 { /* AArch64_FCVTSDr, ARM64_INS_FCVT: fcvt $rd, $rn */
2770 0,
2771 { CS_OP_WRITE, CS_OP_READ, 0 }
2772 },
2773 { /* AArch64_FCVTSHr, ARM64_INS_FCVT: fcvt $rd, $rn */
2774 0,
2775 { CS_OP_WRITE, CS_OP_READ, 0 }
2776 },
2777 { /* AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN: fcvtxn $rd, $rn */
2778 0,
2779 { CS_OP_WRITE, CS_OP_READ, 0 }
2780 },
2781 { /* AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN: fcvtxn $rd.2s, $rn.2d */
2782 0,
2783 { CS_OP_WRITE, CS_OP_READ, 0 }
2784 },
2785 { /* AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2: fcvtxn2 $rd.4s, $rn.2d */
2786 0,
2787 { CS_OP_WRITE, CS_OP_READ, 0 }
2788 },
2789 { /* AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */
2790 0,
2791 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2792 },
2793 { /* AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */
2794 0,
2795 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2796 },
2797 { /* AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */
2798 0,
2799 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2800 },
2801 { /* AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */
2802 0,
2803 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2804 },
2805 { /* AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2806 0,
2807 { CS_OP_WRITE, CS_OP_READ, 0 }
2808 },
2809 { /* AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2810 0,
2811 { CS_OP_WRITE, CS_OP_READ, 0 }
2812 },
2813 { /* AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2814 0,
2815 { CS_OP_WRITE, CS_OP_READ, 0 }
2816 },
2817 { /* AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2818 0,
2819 { CS_OP_WRITE, CS_OP_READ, 0 }
2820 },
2821 { /* AArch64_FCVTZS_IntSWDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */
2822 0,
2823 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2824 },
2825 { /* AArch64_FCVTZS_IntSWSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */
2826 0,
2827 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2828 },
2829 { /* AArch64_FCVTZS_IntSXDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */
2830 0,
2831 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2832 },
2833 { /* AArch64_FCVTZS_IntSXSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */
2834 0,
2835 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2836 },
2837 { /* AArch64_FCVTZS_IntUWDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2838 0,
2839 { CS_OP_WRITE, CS_OP_READ, 0 }
2840 },
2841 { /* AArch64_FCVTZS_IntUWSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2842 0,
2843 { CS_OP_WRITE, CS_OP_READ, 0 }
2844 },
2845 { /* AArch64_FCVTZS_IntUXDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2846 0,
2847 { CS_OP_WRITE, CS_OP_READ, 0 }
2848 },
2849 { /* AArch64_FCVTZS_IntUXSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2850 0,
2851 { CS_OP_WRITE, CS_OP_READ, 0 }
2852 },
2853 { /* AArch64_FCVTZS_Intv2f32, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn */
2854 0,
2855 { CS_OP_WRITE, CS_OP_READ, 0 }
2856 },
2857 { /* AArch64_FCVTZS_Intv2f64, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn */
2858 0,
2859 { CS_OP_WRITE, CS_OP_READ, 0 }
2860 },
2861 { /* AArch64_FCVTZS_Intv4f32, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn */
2862 0,
2863 { CS_OP_WRITE, CS_OP_READ, 0 }
2864 },
2865 { /* AArch64_FCVTZSd, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $imm */
2866 0,
2867 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2868 },
2869 { /* AArch64_FCVTZSs, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $imm */
2870 0,
2871 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2872 },
2873 { /* AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2874 0,
2875 { CS_OP_WRITE, CS_OP_READ, 0 }
2876 },
2877 { /* AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */
2878 0,
2879 { CS_OP_WRITE, CS_OP_READ, 0 }
2880 },
2881 { /* AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn */
2882 0,
2883 { CS_OP_WRITE, CS_OP_READ, 0 }
2884 },
2885 { /* AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn */
2886 0,
2887 { CS_OP_WRITE, CS_OP_READ, 0 }
2888 },
2889 { /* AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn, $imm */
2890 0,
2891 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2892 },
2893 { /* AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn, $imm */
2894 0,
2895 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2896 },
2897 { /* AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn */
2898 0,
2899 { CS_OP_WRITE, CS_OP_READ, 0 }
2900 },
2901 { /* AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn, $imm */
2902 0,
2903 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2904 },
2905 { /* AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */
2906 0,
2907 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2908 },
2909 { /* AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */
2910 0,
2911 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2912 },
2913 { /* AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */
2914 0,
2915 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2916 },
2917 { /* AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */
2918 0,
2919 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2920 },
2921 { /* AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2922 0,
2923 { CS_OP_WRITE, CS_OP_READ, 0 }
2924 },
2925 { /* AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2926 0,
2927 { CS_OP_WRITE, CS_OP_READ, 0 }
2928 },
2929 { /* AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2930 0,
2931 { CS_OP_WRITE, CS_OP_READ, 0 }
2932 },
2933 { /* AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2934 0,
2935 { CS_OP_WRITE, CS_OP_READ, 0 }
2936 },
2937 { /* AArch64_FCVTZU_IntSWDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */
2938 0,
2939 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2940 },
2941 { /* AArch64_FCVTZU_IntSWSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */
2942 0,
2943 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2944 },
2945 { /* AArch64_FCVTZU_IntSXDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */
2946 0,
2947 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2948 },
2949 { /* AArch64_FCVTZU_IntSXSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */
2950 0,
2951 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2952 },
2953 { /* AArch64_FCVTZU_IntUWDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2954 0,
2955 { CS_OP_WRITE, CS_OP_READ, 0 }
2956 },
2957 { /* AArch64_FCVTZU_IntUWSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2958 0,
2959 { CS_OP_WRITE, CS_OP_READ, 0 }
2960 },
2961 { /* AArch64_FCVTZU_IntUXDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2962 0,
2963 { CS_OP_WRITE, CS_OP_READ, 0 }
2964 },
2965 { /* AArch64_FCVTZU_IntUXSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2966 0,
2967 { CS_OP_WRITE, CS_OP_READ, 0 }
2968 },
2969 { /* AArch64_FCVTZU_Intv2f32, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn */
2970 0,
2971 { CS_OP_WRITE, CS_OP_READ, 0 }
2972 },
2973 { /* AArch64_FCVTZU_Intv2f64, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn */
2974 0,
2975 { CS_OP_WRITE, CS_OP_READ, 0 }
2976 },
2977 { /* AArch64_FCVTZU_Intv4f32, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn */
2978 0,
2979 { CS_OP_WRITE, CS_OP_READ, 0 }
2980 },
2981 { /* AArch64_FCVTZUd, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $imm */
2982 0,
2983 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2984 },
2985 { /* AArch64_FCVTZUs, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $imm */
2986 0,
2987 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
2988 },
2989 { /* AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2990 0,
2991 { CS_OP_WRITE, CS_OP_READ, 0 }
2992 },
2993 { /* AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */
2994 0,
2995 { CS_OP_WRITE, CS_OP_READ, 0 }
2996 },
2997 { /* AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn */
2998 0,
2999 { CS_OP_WRITE, CS_OP_READ, 0 }
3000 },
3001 { /* AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn */
3002 0,
3003 { CS_OP_WRITE, CS_OP_READ, 0 }
3004 },
3005 { /* AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn, $imm */
3006 0,
3007 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3008 },
3009 { /* AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn, $imm */
3010 0,
3011 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3012 },
3013 { /* AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn */
3014 0,
3015 { CS_OP_WRITE, CS_OP_READ, 0 }
3016 },
3017 { /* AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn, $imm */
3018 0,
3019 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3020 },
3021 { /* AArch64_FDIVDrr, ARM64_INS_FDIV: fdiv $rd, $rn, $rm */
3022 0,
3023 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3024 },
3025 { /* AArch64_FDIVSrr, ARM64_INS_FDIV: fdiv $rd, $rn, $rm */
3026 0,
3027 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3028 },
3029 { /* AArch64_FDIVv2f32, ARM64_INS_FDIV: fdiv.2s $rd, $rn, $rm| */
3030 0,
3031 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3032 },
3033 { /* AArch64_FDIVv2f64, ARM64_INS_FDIV: fdiv.2d $rd, $rn, $rm| */
3034 0,
3035 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3036 },
3037 { /* AArch64_FDIVv4f32, ARM64_INS_FDIV: fdiv.4s $rd, $rn, $rm| */
3038 0,
3039 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3040 },
3041 { /* AArch64_FMADDDrrr, ARM64_INS_FMADD: fmadd $rd, $rn, $rm, $ra */
3042 0,
3043 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3044 },
3045 { /* AArch64_FMADDSrrr, ARM64_INS_FMADD: fmadd $rd, $rn, $rm, $ra */
3046 0,
3047 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3048 },
3049 { /* AArch64_FMAXDrr, ARM64_INS_FMAX: fmax $rd, $rn, $rm */
3050 0,
3051 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3052 },
3053 { /* AArch64_FMAXNMDrr, ARM64_INS_FMAXNM: fmaxnm $rd, $rn, $rm */
3054 0,
3055 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3056 },
3057 { /* AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP: fmaxnmp.2s $rd, $rn, $rm| */
3058 0,
3059 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3060 },
3061 { /* AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP: fmaxnmp.2d $rd, $rn, $rm| */
3062 0,
3063 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3064 },
3065 { /* AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP: fmaxnmp.2s $rd, $rn */
3066 0,
3067 { CS_OP_WRITE, CS_OP_READ, 0 }
3068 },
3069 { /* AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP: fmaxnmp.2d $rd, $rn */
3070 0,
3071 { CS_OP_WRITE, CS_OP_READ, 0 }
3072 },
3073 { /* AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP: fmaxnmp.4s $rd, $rn, $rm| */
3074 0,
3075 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3076 },
3077 { /* AArch64_FMAXNMSrr, ARM64_INS_FMAXNM: fmaxnm $rd, $rn, $rm */
3078 0,
3079 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3080 },
3081 { /* AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV: fmaxnmv.4s $rd, $rn */
3082 0,
3083 { CS_OP_WRITE, CS_OP_READ, 0 }
3084 },
3085 { /* AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM: fmaxnm.2s $rd, $rn, $rm| */
3086 0,
3087 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3088 },
3089 { /* AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM: fmaxnm.2d $rd, $rn, $rm| */
3090 0,
3091 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3092 },
3093 { /* AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM: fmaxnm.4s $rd, $rn, $rm| */
3094 0,
3095 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3096 },
3097 { /* AArch64_FMAXPv2f32, ARM64_INS_FMAXP: fmaxp.2s $rd, $rn, $rm| */
3098 0,
3099 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3100 },
3101 { /* AArch64_FMAXPv2f64, ARM64_INS_FMAXP: fmaxp.2d $rd, $rn, $rm| */
3102 0,
3103 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3104 },
3105 { /* AArch64_FMAXPv2i32p, ARM64_INS_FMAXP: fmaxp.2s $rd, $rn */
3106 0,
3107 { CS_OP_WRITE, CS_OP_READ, 0 }
3108 },
3109 { /* AArch64_FMAXPv2i64p, ARM64_INS_FMAXP: fmaxp.2d $rd, $rn */
3110 0,
3111 { CS_OP_WRITE, CS_OP_READ, 0 }
3112 },
3113 { /* AArch64_FMAXPv4f32, ARM64_INS_FMAXP: fmaxp.4s $rd, $rn, $rm| */
3114 0,
3115 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3116 },
3117 { /* AArch64_FMAXSrr, ARM64_INS_FMAX: fmax $rd, $rn, $rm */
3118 0,
3119 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3120 },
3121 { /* AArch64_FMAXVv4i32v, ARM64_INS_FMAXV: fmaxv.4s $rd, $rn */
3122 0,
3123 { CS_OP_WRITE, CS_OP_READ, 0 }
3124 },
3125 { /* AArch64_FMAXv2f32, ARM64_INS_FMAX: fmax.2s $rd, $rn, $rm| */
3126 0,
3127 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3128 },
3129 { /* AArch64_FMAXv2f64, ARM64_INS_FMAX: fmax.2d $rd, $rn, $rm| */
3130 0,
3131 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3132 },
3133 { /* AArch64_FMAXv4f32, ARM64_INS_FMAX: fmax.4s $rd, $rn, $rm| */
3134 0,
3135 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3136 },
3137 { /* AArch64_FMINDrr, ARM64_INS_FMIN: fmin $rd, $rn, $rm */
3138 0,
3139 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3140 },
3141 { /* AArch64_FMINNMDrr, ARM64_INS_FMINNM: fminnm $rd, $rn, $rm */
3142 0,
3143 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3144 },
3145 { /* AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP: fminnmp.2s $rd, $rn, $rm| */
3146 0,
3147 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3148 },
3149 { /* AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP: fminnmp.2d $rd, $rn, $rm| */
3150 0,
3151 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3152 },
3153 { /* AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP: fminnmp.2s $rd, $rn */
3154 0,
3155 { CS_OP_WRITE, CS_OP_READ, 0 }
3156 },
3157 { /* AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP: fminnmp.2d $rd, $rn */
3158 0,
3159 { CS_OP_WRITE, CS_OP_READ, 0 }
3160 },
3161 { /* AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP: fminnmp.4s $rd, $rn, $rm| */
3162 0,
3163 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3164 },
3165 { /* AArch64_FMINNMSrr, ARM64_INS_FMINNM: fminnm $rd, $rn, $rm */
3166 0,
3167 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3168 },
3169 { /* AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV: fminnmv.4s $rd, $rn */
3170 0,
3171 { CS_OP_WRITE, CS_OP_READ, 0 }
3172 },
3173 { /* AArch64_FMINNMv2f32, ARM64_INS_FMINNM: fminnm.2s $rd, $rn, $rm| */
3174 0,
3175 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3176 },
3177 { /* AArch64_FMINNMv2f64, ARM64_INS_FMINNM: fminnm.2d $rd, $rn, $rm| */
3178 0,
3179 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3180 },
3181 { /* AArch64_FMINNMv4f32, ARM64_INS_FMINNM: fminnm.4s $rd, $rn, $rm| */
3182 0,
3183 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3184 },
3185 { /* AArch64_FMINPv2f32, ARM64_INS_FMINP: fminp.2s $rd, $rn, $rm| */
3186 0,
3187 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3188 },
3189 { /* AArch64_FMINPv2f64, ARM64_INS_FMINP: fminp.2d $rd, $rn, $rm| */
3190 0,
3191 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3192 },
3193 { /* AArch64_FMINPv2i32p, ARM64_INS_FMINP: fminp.2s $rd, $rn */
3194 0,
3195 { CS_OP_WRITE, CS_OP_READ, 0 }
3196 },
3197 { /* AArch64_FMINPv2i64p, ARM64_INS_FMINP: fminp.2d $rd, $rn */
3198 0,
3199 { CS_OP_WRITE, CS_OP_READ, 0 }
3200 },
3201 { /* AArch64_FMINPv4f32, ARM64_INS_FMINP: fminp.4s $rd, $rn, $rm| */
3202 0,
3203 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3204 },
3205 { /* AArch64_FMINSrr, ARM64_INS_FMIN: fmin $rd, $rn, $rm */
3206 0,
3207 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3208 },
3209 { /* AArch64_FMINVv4i32v, ARM64_INS_FMINV: fminv.4s $rd, $rn */
3210 0,
3211 { CS_OP_WRITE, CS_OP_READ, 0 }
3212 },
3213 { /* AArch64_FMINv2f32, ARM64_INS_FMIN: fmin.2s $rd, $rn, $rm| */
3214 0,
3215 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3216 },
3217 { /* AArch64_FMINv2f64, ARM64_INS_FMIN: fmin.2d $rd, $rn, $rm| */
3218 0,
3219 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3220 },
3221 { /* AArch64_FMINv4f32, ARM64_INS_FMIN: fmin.4s $rd, $rn, $rm| */
3222 0,
3223 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3224 },
3225 { /* AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA: fmla.s $rd, $rn, $rm$idx */
3226 0,
3227 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3228 },
3229 { /* AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA: fmla.d $rd, $rn, $rm$idx */
3230 0,
3231 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3232 },
3233 { /* AArch64_FMLAv2f32, ARM64_INS_FMLA: fmla.2s $rd, $rn, $rm */
3234 0,
3235 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3236 },
3237 { /* AArch64_FMLAv2f64, ARM64_INS_FMLA: fmla.2d $rd, $rn, $rm */
3238 0,
3239 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3240 },
3241 { /* AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA: fmla.2s $rd, $rn, $rm$idx */
3242 0,
3243 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3244 },
3245 { /* AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA: fmla.2d $rd, $rn, $rm$idx */
3246 0,
3247 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3248 },
3249 { /* AArch64_FMLAv4f32, ARM64_INS_FMLA: fmla.4s $rd, $rn, $rm */
3250 0,
3251 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3252 },
3253 { /* AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA: fmla.4s $rd, $rn, $rm$idx */
3254 0,
3255 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3256 },
3257 { /* AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS: fmls.s $rd, $rn, $rm$idx */
3258 0,
3259 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3260 },
3261 { /* AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS: fmls.d $rd, $rn, $rm$idx */
3262 0,
3263 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3264 },
3265 { /* AArch64_FMLSv2f32, ARM64_INS_FMLS: fmls.2s $rd, $rn, $rm */
3266 0,
3267 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3268 },
3269 { /* AArch64_FMLSv2f64, ARM64_INS_FMLS: fmls.2d $rd, $rn, $rm */
3270 0,
3271 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3272 },
3273 { /* AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS: fmls.2s $rd, $rn, $rm$idx */
3274 0,
3275 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3276 },
3277 { /* AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS: fmls.2d $rd, $rn, $rm$idx */
3278 0,
3279 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3280 },
3281 { /* AArch64_FMLSv4f32, ARM64_INS_FMLS: fmls.4s $rd, $rn, $rm */
3282 0,
3283 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3284 },
3285 { /* AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS: fmls.4s $rd, $rn, $rm$idx */
3286 0,
3287 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3288 },
3289 { /* AArch64_FMOVDXHighr, ARM64_INS_FMOV: fmov.d $rd, $rn$idx */
3290 0,
3291 { CS_OP_WRITE, CS_OP_READ, 0 }
3292 },
3293 { /* AArch64_FMOVDXr, ARM64_INS_FMOV: fmov $rd, $rn */
3294 0,
3295 { CS_OP_WRITE, CS_OP_READ, 0 }
3296 },
3297 { /* AArch64_FMOVDi, ARM64_INS_FMOV: fmov $rd, $imm */
3298 0,
3299 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3300 },
3301 { /* AArch64_FMOVDr, ARM64_INS_FMOV: fmov $rd, $rn */
3302 0,
3303 { CS_OP_WRITE, CS_OP_READ, 0 }
3304 },
3305 { /* AArch64_FMOVSWr, ARM64_INS_FMOV: fmov $rd, $rn */
3306 0,
3307 { CS_OP_WRITE, CS_OP_READ, 0 }
3308 },
3309 { /* AArch64_FMOVSi, ARM64_INS_FMOV: fmov $rd, $imm */
3310 0,
3311 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3312 },
3313 { /* AArch64_FMOVSr, ARM64_INS_FMOV: fmov $rd, $rn */
3314 0,
3315 { CS_OP_WRITE, CS_OP_READ, 0 }
3316 },
3317 { /* AArch64_FMOVWSr, ARM64_INS_FMOV: fmov $rd, $rn */
3318 0,
3319 { CS_OP_WRITE, CS_OP_READ, 0 }
3320 },
3321 { /* AArch64_FMOVXDHighr, ARM64_INS_FMOV: fmov.d $rd$idx, $rn */
3322 0,
3323 { CS_OP_WRITE, CS_OP_READ, 0 }
3324 },
3325 { /* AArch64_FMOVXDr, ARM64_INS_FMOV: fmov $rd, $rn */
3326 0,
3327 { CS_OP_WRITE, CS_OP_READ, 0 }
3328 },
3329 { /* AArch64_FMOVv2f32_ns, ARM64_INS_FMOV: fmov.2s $rd, $imm8 */
3330 0,
3331 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ,0 }
3332 },
3333 { /* AArch64_FMOVv2f64_ns, ARM64_INS_FMOV: fmov.2d $rd, $imm8 */
3334 0,
3335 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ,0 }
3336 },
3337 { /* AArch64_FMOVv4f32_ns, ARM64_INS_FMOV: fmov.4s $rd, $imm8 */
3338 0,
3339 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ,0 }
3340 },
3341 { /* AArch64_FMSUBDrrr, ARM64_INS_FMSUB: fmsub $rd, $rn, $rm, $ra */
3342 0,
3343 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3344 },
3345 { /* AArch64_FMSUBSrrr, ARM64_INS_FMSUB: fmsub $rd, $rn, $rm, $ra */
3346 0,
3347 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3348 },
3349 { /* AArch64_FMULDrr, ARM64_INS_FMUL: fmul $rd, $rn, $rm */
3350 0,
3351 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3352 },
3353 { /* AArch64_FMULSrr, ARM64_INS_FMUL: fmul $rd, $rn, $rm */
3354 0,
3355 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3356 },
3357 { /* AArch64_FMULX32, ARM64_INS_FMULX: fmulx $rd, $rn, $rm */
3358 0,
3359 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3360 },
3361 { /* AArch64_FMULX64, ARM64_INS_FMULX: fmulx $rd, $rn, $rm */
3362 0,
3363 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3364 },
3365 { /* AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX: fmulx.s $rd, $rn, $rm$idx */
3366 0,
3367 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3368 },
3369 { /* AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX: fmulx.d $rd, $rn, $rm$idx */
3370 0,
3371 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3372 },
3373 { /* AArch64_FMULXv2f32, ARM64_INS_FMULX: fmulx.2s $rd, $rn, $rm| */
3374 0,
3375 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3376 },
3377 { /* AArch64_FMULXv2f64, ARM64_INS_FMULX: fmulx.2d $rd, $rn, $rm| */
3378 0,
3379 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3380 },
3381 { /* AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX: fmulx.2s $rd, $rn, $rm$idx */
3382 0,
3383 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3384 },
3385 { /* AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX: fmulx.2d $rd, $rn, $rm$idx */
3386 0,
3387 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3388 },
3389 { /* AArch64_FMULXv4f32, ARM64_INS_FMULX: fmulx.4s $rd, $rn, $rm| */
3390 0,
3391 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3392 },
3393 { /* AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX: fmulx.4s $rd, $rn, $rm$idx */
3394 0,
3395 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3396 },
3397 { /* AArch64_FMULv1i32_indexed, ARM64_INS_FMUL: fmul.s $rd, $rn, $rm$idx */
3398 0,
3399 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3400 },
3401 { /* AArch64_FMULv1i64_indexed, ARM64_INS_FMUL: fmul.d $rd, $rn, $rm$idx */
3402 0,
3403 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3404 },
3405 { /* AArch64_FMULv2f32, ARM64_INS_FMUL: fmul.2s $rd, $rn, $rm| */
3406 0,
3407 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3408 },
3409 { /* AArch64_FMULv2f64, ARM64_INS_FMUL: fmul.2d $rd, $rn, $rm| */
3410 0,
3411 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3412 },
3413 { /* AArch64_FMULv2i32_indexed, ARM64_INS_FMUL: fmul.2s $rd, $rn, $rm$idx */
3414 0,
3415 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3416 },
3417 { /* AArch64_FMULv2i64_indexed, ARM64_INS_FMUL: fmul.2d $rd, $rn, $rm$idx */
3418 0,
3419 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3420 },
3421 { /* AArch64_FMULv4f32, ARM64_INS_FMUL: fmul.4s $rd, $rn, $rm| */
3422 0,
3423 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3424 },
3425 { /* AArch64_FMULv4i32_indexed, ARM64_INS_FMUL: fmul.4s $rd, $rn, $rm$idx */
3426 0,
3427 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3428 },
3429 { /* AArch64_FNEGDr, ARM64_INS_FNEG: fneg $rd, $rn */
3430 0,
3431 { CS_OP_WRITE, CS_OP_READ, 0 }
3432 },
3433 { /* AArch64_FNEGSr, ARM64_INS_FNEG: fneg $rd, $rn */
3434 0,
3435 { CS_OP_WRITE, CS_OP_READ, 0 }
3436 },
3437 { /* AArch64_FNEGv2f32, ARM64_INS_FNEG: fneg.2s $rd, $rn */
3438 0,
3439 { CS_OP_WRITE, CS_OP_READ, 0 }
3440 },
3441 { /* AArch64_FNEGv2f64, ARM64_INS_FNEG: fneg.2d $rd, $rn */
3442 0,
3443 { CS_OP_WRITE, CS_OP_READ, 0 }
3444 },
3445 { /* AArch64_FNEGv4f32, ARM64_INS_FNEG: fneg.4s $rd, $rn */
3446 0,
3447 { CS_OP_WRITE, CS_OP_READ, 0 }
3448 },
3449 { /* AArch64_FNMADDDrrr, ARM64_INS_FNMADD: fnmadd $rd, $rn, $rm, $ra */
3450 0,
3451 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3452 },
3453 { /* AArch64_FNMADDSrrr, ARM64_INS_FNMADD: fnmadd $rd, $rn, $rm, $ra */
3454 0,
3455 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3456 },
3457 { /* AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB: fnmsub $rd, $rn, $rm, $ra */
3458 0,
3459 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3460 },
3461 { /* AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB: fnmsub $rd, $rn, $rm, $ra */
3462 0,
3463 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3464 },
3465 { /* AArch64_FNMULDrr, ARM64_INS_FNMUL: fnmul $rd, $rn, $rm */
3466 0,
3467 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3468 },
3469 { /* AArch64_FNMULSrr, ARM64_INS_FNMUL: fnmul $rd, $rn, $rm */
3470 0,
3471 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3472 },
3473 { /* AArch64_FRECPEv1i32, ARM64_INS_FRECPE: frecpe $rd, $rn */
3474 0,
3475 { CS_OP_WRITE, CS_OP_READ, 0 }
3476 },
3477 { /* AArch64_FRECPEv1i64, ARM64_INS_FRECPE: frecpe $rd, $rn */
3478 0,
3479 { CS_OP_WRITE, CS_OP_READ, 0 }
3480 },
3481 { /* AArch64_FRECPEv2f32, ARM64_INS_FRECPE: frecpe.2s $rd, $rn */
3482 0,
3483 { CS_OP_WRITE, CS_OP_READ, 0 }
3484 },
3485 { /* AArch64_FRECPEv2f64, ARM64_INS_FRECPE: frecpe.2d $rd, $rn */
3486 0,
3487 { CS_OP_WRITE, CS_OP_READ, 0 }
3488 },
3489 { /* AArch64_FRECPEv4f32, ARM64_INS_FRECPE: frecpe.4s $rd, $rn */
3490 0,
3491 { CS_OP_WRITE, CS_OP_READ, 0 }
3492 },
3493 { /* AArch64_FRECPS32, ARM64_INS_FRECPS: frecps $rd, $rn, $rm */
3494 0,
3495 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3496 },
3497 { /* AArch64_FRECPS64, ARM64_INS_FRECPS: frecps $rd, $rn, $rm */
3498 0,
3499 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3500 },
3501 { /* AArch64_FRECPSv2f32, ARM64_INS_FRECPS: frecps.2s $rd, $rn, $rm| */
3502 0,
3503 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3504 },
3505 { /* AArch64_FRECPSv2f64, ARM64_INS_FRECPS: frecps.2d $rd, $rn, $rm| */
3506 0,
3507 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3508 },
3509 { /* AArch64_FRECPSv4f32, ARM64_INS_FRECPS: frecps.4s $rd, $rn, $rm| */
3510 0,
3511 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3512 },
3513 { /* AArch64_FRECPXv1i32, ARM64_INS_FRECPX: frecpx $rd, $rn */
3514 0,
3515 { CS_OP_WRITE, CS_OP_READ, 0 }
3516 },
3517 { /* AArch64_FRECPXv1i64, ARM64_INS_FRECPX: frecpx $rd, $rn */
3518 0,
3519 { CS_OP_WRITE, CS_OP_READ, 0 }
3520 },
3521 { /* AArch64_FRINTADr, ARM64_INS_FRINTA: frinta $rd, $rn */
3522 0,
3523 { CS_OP_WRITE, CS_OP_READ, 0 }
3524 },
3525 { /* AArch64_FRINTASr, ARM64_INS_FRINTA: frinta $rd, $rn */
3526 0,
3527 { CS_OP_WRITE, CS_OP_READ, 0 }
3528 },
3529 { /* AArch64_FRINTAv2f32, ARM64_INS_FRINTA: frinta.2s $rd, $rn */
3530 0,
3531 { CS_OP_WRITE, CS_OP_READ, 0 }
3532 },
3533 { /* AArch64_FRINTAv2f64, ARM64_INS_FRINTA: frinta.2d $rd, $rn */
3534 0,
3535 { CS_OP_WRITE, CS_OP_READ, 0 }
3536 },
3537 { /* AArch64_FRINTAv4f32, ARM64_INS_FRINTA: frinta.4s $rd, $rn */
3538 0,
3539 { CS_OP_WRITE, CS_OP_READ, 0 }
3540 },
3541 { /* AArch64_FRINTIDr, ARM64_INS_FRINTI: frinti $rd, $rn */
3542 0,
3543 { CS_OP_WRITE, CS_OP_READ, 0 }
3544 },
3545 { /* AArch64_FRINTISr, ARM64_INS_FRINTI: frinti $rd, $rn */
3546 0,
3547 { CS_OP_WRITE, CS_OP_READ, 0 }
3548 },
3549 { /* AArch64_FRINTIv2f32, ARM64_INS_FRINTI: frinti.2s $rd, $rn */
3550 0,
3551 { CS_OP_WRITE, CS_OP_READ, 0 }
3552 },
3553 { /* AArch64_FRINTIv2f64, ARM64_INS_FRINTI: frinti.2d $rd, $rn */
3554 0,
3555 { CS_OP_WRITE, CS_OP_READ, 0 }
3556 },
3557 { /* AArch64_FRINTIv4f32, ARM64_INS_FRINTI: frinti.4s $rd, $rn */
3558 0,
3559 { CS_OP_WRITE, CS_OP_READ, 0 }
3560 },
3561 { /* AArch64_FRINTMDr, ARM64_INS_FRINTM: frintm $rd, $rn */
3562 0,
3563 { CS_OP_WRITE, CS_OP_READ, 0 }
3564 },
3565 { /* AArch64_FRINTMSr, ARM64_INS_FRINTM: frintm $rd, $rn */
3566 0,
3567 { CS_OP_WRITE, CS_OP_READ, 0 }
3568 },
3569 { /* AArch64_FRINTMv2f32, ARM64_INS_FRINTM: frintm.2s $rd, $rn */
3570 0,
3571 { CS_OP_WRITE, CS_OP_READ, 0 }
3572 },
3573 { /* AArch64_FRINTMv2f64, ARM64_INS_FRINTM: frintm.2d $rd, $rn */
3574 0,
3575 { CS_OP_WRITE, CS_OP_READ, 0 }
3576 },
3577 { /* AArch64_FRINTMv4f32, ARM64_INS_FRINTM: frintm.4s $rd, $rn */
3578 0,
3579 { CS_OP_WRITE, CS_OP_READ, 0 }
3580 },
3581 { /* AArch64_FRINTNDr, ARM64_INS_FRINTN: frintn $rd, $rn */
3582 0,
3583 { CS_OP_WRITE, CS_OP_READ, 0 }
3584 },
3585 { /* AArch64_FRINTNSr, ARM64_INS_FRINTN: frintn $rd, $rn */
3586 0,
3587 { CS_OP_WRITE, CS_OP_READ, 0 }
3588 },
3589 { /* AArch64_FRINTNv2f32, ARM64_INS_FRINTN: frintn.2s $rd, $rn */
3590 0,
3591 { CS_OP_WRITE, CS_OP_READ, 0 }
3592 },
3593 { /* AArch64_FRINTNv2f64, ARM64_INS_FRINTN: frintn.2d $rd, $rn */
3594 0,
3595 { CS_OP_WRITE, CS_OP_READ, 0 }
3596 },
3597 { /* AArch64_FRINTNv4f32, ARM64_INS_FRINTN: frintn.4s $rd, $rn */
3598 0,
3599 { CS_OP_WRITE, CS_OP_READ, 0 }
3600 },
3601 { /* AArch64_FRINTPDr, ARM64_INS_FRINTP: frintp $rd, $rn */
3602 0,
3603 { CS_OP_WRITE, CS_OP_READ, 0 }
3604 },
3605 { /* AArch64_FRINTPSr, ARM64_INS_FRINTP: frintp $rd, $rn */
3606 0,
3607 { CS_OP_WRITE, CS_OP_READ, 0 }
3608 },
3609 { /* AArch64_FRINTPv2f32, ARM64_INS_FRINTP: frintp.2s $rd, $rn */
3610 0,
3611 { CS_OP_WRITE, CS_OP_READ, 0 }
3612 },
3613 { /* AArch64_FRINTPv2f64, ARM64_INS_FRINTP: frintp.2d $rd, $rn */
3614 0,
3615 { CS_OP_WRITE, CS_OP_READ, 0 }
3616 },
3617 { /* AArch64_FRINTPv4f32, ARM64_INS_FRINTP: frintp.4s $rd, $rn */
3618 0,
3619 { CS_OP_WRITE, CS_OP_READ, 0 }
3620 },
3621 { /* AArch64_FRINTXDr, ARM64_INS_FRINTX: frintx $rd, $rn */
3622 0,
3623 { CS_OP_WRITE, CS_OP_READ, 0 }
3624 },
3625 { /* AArch64_FRINTXSr, ARM64_INS_FRINTX: frintx $rd, $rn */
3626 0,
3627 { CS_OP_WRITE, CS_OP_READ, 0 }
3628 },
3629 { /* AArch64_FRINTXv2f32, ARM64_INS_FRINTX: frintx.2s $rd, $rn */
3630 0,
3631 { CS_OP_WRITE, CS_OP_READ, 0 }
3632 },
3633 { /* AArch64_FRINTXv2f64, ARM64_INS_FRINTX: frintx.2d $rd, $rn */
3634 0,
3635 { CS_OP_WRITE, CS_OP_READ, 0 }
3636 },
3637 { /* AArch64_FRINTXv4f32, ARM64_INS_FRINTX: frintx.4s $rd, $rn */
3638 0,
3639 { CS_OP_WRITE, CS_OP_READ, 0 }
3640 },
3641 { /* AArch64_FRINTZDr, ARM64_INS_FRINTZ: frintz $rd, $rn */
3642 0,
3643 { CS_OP_WRITE, CS_OP_READ, 0 }
3644 },
3645 { /* AArch64_FRINTZSr, ARM64_INS_FRINTZ: frintz $rd, $rn */
3646 0,
3647 { CS_OP_WRITE, CS_OP_READ, 0 }
3648 },
3649 { /* AArch64_FRINTZv2f32, ARM64_INS_FRINTZ: frintz.2s $rd, $rn */
3650 0,
3651 { CS_OP_WRITE, CS_OP_READ, 0 }
3652 },
3653 { /* AArch64_FRINTZv2f64, ARM64_INS_FRINTZ: frintz.2d $rd, $rn */
3654 0,
3655 { CS_OP_WRITE, CS_OP_READ, 0 }
3656 },
3657 { /* AArch64_FRINTZv4f32, ARM64_INS_FRINTZ: frintz.4s $rd, $rn */
3658 0,
3659 { CS_OP_WRITE, CS_OP_READ, 0 }
3660 },
3661 { /* AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE: frsqrte $rd, $rn */
3662 0,
3663 { CS_OP_WRITE, CS_OP_READ, 0 }
3664 },
3665 { /* AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE: frsqrte $rd, $rn */
3666 0,
3667 { CS_OP_WRITE, CS_OP_READ, 0 }
3668 },
3669 { /* AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE: frsqrte.2s $rd, $rn */
3670 0,
3671 { CS_OP_WRITE, CS_OP_READ, 0 }
3672 },
3673 { /* AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE: frsqrte.2d $rd, $rn */
3674 0,
3675 { CS_OP_WRITE, CS_OP_READ, 0 }
3676 },
3677 { /* AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE: frsqrte.4s $rd, $rn */
3678 0,
3679 { CS_OP_WRITE, CS_OP_READ, 0 }
3680 },
3681 { /* AArch64_FRSQRTS32, ARM64_INS_FRSQRTS: frsqrts $rd, $rn, $rm */
3682 0,
3683 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3684 },
3685 { /* AArch64_FRSQRTS64, ARM64_INS_FRSQRTS: frsqrts $rd, $rn, $rm */
3686 0,
3687 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3688 },
3689 { /* AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS: frsqrts.2s $rd, $rn, $rm| */
3690 0,
3691 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3692 },
3693 { /* AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS: frsqrts.2d $rd, $rn, $rm| */
3694 0,
3695 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3696 },
3697 { /* AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS: frsqrts.4s $rd, $rn, $rm| */
3698 0,
3699 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3700 },
3701 { /* AArch64_FSQRTDr, ARM64_INS_FSQRT: fsqrt $rd, $rn */
3702 0,
3703 { CS_OP_WRITE, CS_OP_READ, 0 }
3704 },
3705 { /* AArch64_FSQRTSr, ARM64_INS_FSQRT: fsqrt $rd, $rn */
3706 0,
3707 { CS_OP_WRITE, CS_OP_READ, 0 }
3708 },
3709 { /* AArch64_FSQRTv2f32, ARM64_INS_FSQRT: fsqrt.2s $rd, $rn */
3710 0,
3711 { CS_OP_WRITE, CS_OP_READ, 0 }
3712 },
3713 { /* AArch64_FSQRTv2f64, ARM64_INS_FSQRT: fsqrt.2d $rd, $rn */
3714 0,
3715 { CS_OP_WRITE, CS_OP_READ, 0 }
3716 },
3717 { /* AArch64_FSQRTv4f32, ARM64_INS_FSQRT: fsqrt.4s $rd, $rn */
3718 0,
3719 { CS_OP_WRITE, CS_OP_READ, 0 }
3720 },
3721 { /* AArch64_FSUBDrr, ARM64_INS_FSUB: fsub $rd, $rn, $rm */
3722 0,
3723 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3724 },
3725 { /* AArch64_FSUBSrr, ARM64_INS_FSUB: fsub $rd, $rn, $rm */
3726 0,
3727 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3728 },
3729 { /* AArch64_FSUBv2f32, ARM64_INS_FSUB: fsub.2s $rd, $rn, $rm| */
3730 0,
3731 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3732 },
3733 { /* AArch64_FSUBv2f64, ARM64_INS_FSUB: fsub.2d $rd, $rn, $rm| */
3734 0,
3735 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3736 },
3737 { /* AArch64_FSUBv4f32, ARM64_INS_FSUB: fsub.4s $rd, $rn, $rm| */
3738 0,
3739 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
3740 },
3741 { /* AArch64_HINT, ARM64_INS_HINT: hint $imm */
3742 0,
3743 { CS_OP_READ, 0 }
3744 },
3745 { /* AArch64_HLT, ARM64_INS_HLT: hlt $imm */
3746 0,
3747 { CS_OP_READ, 0 }
3748 },
3749 { /* AArch64_HVC, ARM64_INS_HVC: hvc $imm */
3750 0,
3751 { CS_OP_READ, 0 }
3752 },
3753 { /* AArch64_INSvi16gpr, ARM64_INS_INS: ins.h $rd$idx, $rn */
3754 0,
3755 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3756 },
3757 { /* AArch64_INSvi16lane, ARM64_INS_INS: ins.h $rd$idx, $rn$idx2 */
3758 0,
3759 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3760 },
3761 { /* AArch64_INSvi32gpr, ARM64_INS_INS: ins.s $rd$idx, $rn */
3762 0,
3763 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3764 },
3765 { /* AArch64_INSvi32lane, ARM64_INS_INS: ins.s $rd$idx, $rn$idx2 */
3766 0,
3767 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3768 },
3769 { /* AArch64_INSvi64gpr, ARM64_INS_INS: ins.d $rd$idx, $rn */
3770 0,
3771 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3772 },
3773 { /* AArch64_INSvi64lane, ARM64_INS_INS: ins.d $rd$idx, $rn$idx2 */
3774 0,
3775 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3776 },
3777 { /* AArch64_INSvi8gpr, ARM64_INS_INS: ins.b $rd$idx, $rn */
3778 0,
3779 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3780 },
3781 { /* AArch64_INSvi8lane, ARM64_INS_INS: ins.b $rd$idx, $rn$idx2 */
3782 0,
3783 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
3784 },
3785 { /* AArch64_ISB, ARM64_INS_ISB: isb $crm */
3786 0,
3787 { 0 }
3788 },
3789 { /* AArch64_LD1Fourv16b, ARM64_INS_LD1: ld1 $vt, [$rn] */
3790 0,
3791 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3792 },
3793 { /* AArch64_LD1Fourv16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3794 0,
3795 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3796 },
3797 { /* AArch64_LD1Fourv1d, ARM64_INS_LD1: ld1 $vt, [$rn] */
3798 0,
3799 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3800 },
3801 { /* AArch64_LD1Fourv1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3802 0,
3803 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3804 },
3805 { /* AArch64_LD1Fourv2d, ARM64_INS_LD1: ld1 $vt, [$rn] */
3806 0,
3807 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3808 },
3809 { /* AArch64_LD1Fourv2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3810 0,
3811 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3812 },
3813 { /* AArch64_LD1Fourv2s, ARM64_INS_LD1: ld1 $vt, [$rn] */
3814 0,
3815 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3816 },
3817 { /* AArch64_LD1Fourv2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3818 0,
3819 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3820 },
3821 { /* AArch64_LD1Fourv4h, ARM64_INS_LD1: ld1 $vt, [$rn] */
3822 0,
3823 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3824 },
3825 { /* AArch64_LD1Fourv4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3826 0,
3827 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3828 },
3829 { /* AArch64_LD1Fourv4s, ARM64_INS_LD1: ld1 $vt, [$rn] */
3830 0,
3831 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3832 },
3833 { /* AArch64_LD1Fourv4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3834 0,
3835 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3836 },
3837 { /* AArch64_LD1Fourv8b, ARM64_INS_LD1: ld1 $vt, [$rn] */
3838 0,
3839 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3840 },
3841 { /* AArch64_LD1Fourv8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3842 0,
3843 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3844 },
3845 { /* AArch64_LD1Fourv8h, ARM64_INS_LD1: ld1 $vt, [$rn] */
3846 0,
3847 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3848 },
3849 { /* AArch64_LD1Fourv8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3850 0,
3851 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3852 },
3853 { /* AArch64_LD1Onev16b, ARM64_INS_LD1: ld1 $vt, [$rn] */
3854 0,
3855 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3856 },
3857 { /* AArch64_LD1Onev16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3858 0,
3859 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3860 },
3861 { /* AArch64_LD1Onev1d, ARM64_INS_LD1: ld1 $vt, [$rn] */
3862 0,
3863 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3864 },
3865 { /* AArch64_LD1Onev1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3866 0,
3867 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3868 },
3869 { /* AArch64_LD1Onev2d, ARM64_INS_LD1: ld1 $vt, [$rn] */
3870 0,
3871 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3872 },
3873 { /* AArch64_LD1Onev2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3874 0,
3875 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ0 }
3876 },
3877 { /* AArch64_LD1Onev2s, ARM64_INS_LD1: ld1 $vt, [$rn] */
3878 0,
3879 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3880 },
3881 { /* AArch64_LD1Onev2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3882 0,
3883 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3884 },
3885 { /* AArch64_LD1Onev4h, ARM64_INS_LD1: ld1 $vt, [$rn] */
3886 0,
3887 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3888 },
3889 { /* AArch64_LD1Onev4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3890 0,
3891 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3892 },
3893 { /* AArch64_LD1Onev4s, ARM64_INS_LD1: ld1 $vt, [$rn] */
3894 0,
3895 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3896 },
3897 { /* AArch64_LD1Onev4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3898 0,
3899 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3900 },
3901 { /* AArch64_LD1Onev8b, ARM64_INS_LD1: ld1 $vt, [$rn] */
3902 0,
3903 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3904 },
3905 { /* AArch64_LD1Onev8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3906 0,
3907 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3908 },
3909 { /* AArch64_LD1Onev8h, ARM64_INS_LD1: ld1 $vt, [$rn] */
3910 0,
3911 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3912 },
3913 { /* AArch64_LD1Onev8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3914 0,
3915 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3916 },
3917 { /* AArch64_LD1Rv16b, ARM64_INS_LD1R: ld1r $vt, [$rn] */
3918 0,
3919 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3920 },
3921 { /* AArch64_LD1Rv16b_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */
3922 0,
3923 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3924 },
3925 { /* AArch64_LD1Rv1d, ARM64_INS_LD1R: ld1r $vt, [$rn] */
3926 0,
3927 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3928 },
3929 { /* AArch64_LD1Rv1d_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */
3930 0,
3931 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3932 },
3933 { /* AArch64_LD1Rv2d, ARM64_INS_LD1R: ld1r $vt, [$rn] */
3934 0,
3935 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3936 },
3937 { /* AArch64_LD1Rv2d_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */
3938 0,
3939 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3940 },
3941 { /* AArch64_LD1Rv2s, ARM64_INS_LD1R: ld1r $vt, [$rn] */
3942 0,
3943 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3944 },
3945 { /* AArch64_LD1Rv2s_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */
3946 0,
3947 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3948 },
3949 { /* AArch64_LD1Rv4h, ARM64_INS_LD1R: ld1r $vt, [$rn] */
3950 0,
3951 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3952 },
3953 { /* AArch64_LD1Rv4h_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */
3954 0,
3955 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3956 },
3957 { /* AArch64_LD1Rv4s, ARM64_INS_LD1R: ld1r $vt, [$rn] */
3958 0,
3959 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3960 },
3961 { /* AArch64_LD1Rv4s_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */
3962 0,
3963 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3964 },
3965 { /* AArch64_LD1Rv8b, ARM64_INS_LD1R: ld1r $vt, [$rn] */
3966 0,
3967 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3968 },
3969 { /* AArch64_LD1Rv8b_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */
3970 0,
3971 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3972 },
3973 { /* AArch64_LD1Rv8h, ARM64_INS_LD1R: ld1r $vt, [$rn] */
3974 0,
3975 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3976 },
3977 { /* AArch64_LD1Rv8h_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */
3978 0,
3979 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3980 },
3981 { /* AArch64_LD1Threev16b, ARM64_INS_LD1: ld1 $vt, [$rn] */
3982 0,
3983 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3984 },
3985 { /* AArch64_LD1Threev16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3986 0,
3987 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3988 },
3989 { /* AArch64_LD1Threev1d, ARM64_INS_LD1: ld1 $vt, [$rn] */
3990 0,
3991 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
3992 },
3993 { /* AArch64_LD1Threev1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
3994 0,
3995 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
3996 },
3997 { /* AArch64_LD1Threev2d, ARM64_INS_LD1: ld1 $vt, [$rn] */
3998 0,
3999 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4000 },
4001 { /* AArch64_LD1Threev2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4002 0,
4003 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4004 },
4005 { /* AArch64_LD1Threev2s, ARM64_INS_LD1: ld1 $vt, [$rn] */
4006 0,
4007 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4008 },
4009 { /* AArch64_LD1Threev2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4010 0,
4011 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4012 },
4013 { /* AArch64_LD1Threev4h, ARM64_INS_LD1: ld1 $vt, [$rn] */
4014 0,
4015 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4016 },
4017 { /* AArch64_LD1Threev4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4018 0,
4019 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4020 },
4021 { /* AArch64_LD1Threev4s, ARM64_INS_LD1: ld1 $vt, [$rn] */
4022 0,
4023 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4024 },
4025 { /* AArch64_LD1Threev4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4026 0,
4027 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4028 },
4029 { /* AArch64_LD1Threev8b, ARM64_INS_LD1: ld1 $vt, [$rn] */
4030 0,
4031 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4032 },
4033 { /* AArch64_LD1Threev8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4034 0,
4035 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4036 },
4037 { /* AArch64_LD1Threev8h, ARM64_INS_LD1: ld1 $vt, [$rn] */
4038 0,
4039 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4040 },
4041 { /* AArch64_LD1Threev8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4042 0,
4043 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4044 },
4045 { /* AArch64_LD1Twov16b, ARM64_INS_LD1: ld1 $vt, [$rn] */
4046 0,
4047 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4048 },
4049 { /* AArch64_LD1Twov16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4050 0,
4051 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4052 },
4053 { /* AArch64_LD1Twov1d, ARM64_INS_LD1: ld1 $vt, [$rn] */
4054 0,
4055 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4056 },
4057 { /* AArch64_LD1Twov1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4058 0,
4059 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4060 },
4061 { /* AArch64_LD1Twov2d, ARM64_INS_LD1: ld1 $vt, [$rn] */
4062 0,
4063 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4064 },
4065 { /* AArch64_LD1Twov2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4066 0,
4067 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4068 },
4069 { /* AArch64_LD1Twov2s, ARM64_INS_LD1: ld1 $vt, [$rn] */
4070 0,
4071 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4072 },
4073 { /* AArch64_LD1Twov2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4074 0,
4075 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4076 },
4077 { /* AArch64_LD1Twov4h, ARM64_INS_LD1: ld1 $vt, [$rn] */
4078 0,
4079 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4080 },
4081 { /* AArch64_LD1Twov4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4082 0,
4083 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4084 },
4085 { /* AArch64_LD1Twov4s, ARM64_INS_LD1: ld1 $vt, [$rn] */
4086 0,
4087 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4088 },
4089 { /* AArch64_LD1Twov4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4090 0,
4091 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4092 },
4093 { /* AArch64_LD1Twov8b, ARM64_INS_LD1: ld1 $vt, [$rn] */
4094 0,
4095 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4096 },
4097 { /* AArch64_LD1Twov8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4098 0,
4099 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4100 },
4101 { /* AArch64_LD1Twov8h, ARM64_INS_LD1: ld1 $vt, [$rn] */
4102 0,
4103 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4104 },
4105 { /* AArch64_LD1Twov8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */
4106 0,
4107 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4108 },
4109 { /* AArch64_LD1i16, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */
4110 0,
4111 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4112 },
4113 { /* AArch64_LD1i16_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */
4114 0,
4115 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4116 },
4117 { /* AArch64_LD1i32, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */
4118 0,
4119 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4120 },
4121 { /* AArch64_LD1i32_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */
4122 0,
4123 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4124 },
4125 { /* AArch64_LD1i64, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */
4126 0,
4127 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4128 },
4129 { /* AArch64_LD1i64_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */
4130 0,
4131 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4132 },
4133 { /* AArch64_LD1i8, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */
4134 0,
4135 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4136 },
4137 { /* AArch64_LD1i8_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */
4138 0,
4139 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4140 },
4141 { /* AArch64_LD2Rv16b, ARM64_INS_LD2R: ld2r $vt, [$rn] */
4142 0,
4143 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4144 },
4145 { /* AArch64_LD2Rv16b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */
4146 0,
4147 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4148 },
4149 { /* AArch64_LD2Rv1d, ARM64_INS_LD2R: ld2r $vt, [$rn] */
4150 0,
4151 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4152 },
4153 { /* AArch64_LD2Rv1d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */
4154 0,
4155 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4156 },
4157 { /* AArch64_LD2Rv2d, ARM64_INS_LD2R: ld2r $vt, [$rn] */
4158 0,
4159 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4160 },
4161 { /* AArch64_LD2Rv2d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */
4162 0,
4163 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4164 },
4165 { /* AArch64_LD2Rv2s, ARM64_INS_LD2R: ld2r $vt, [$rn] */
4166 0,
4167 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4168 },
4169 { /* AArch64_LD2Rv2s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */
4170 0,
4171 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4172 },
4173 { /* AArch64_LD2Rv4h, ARM64_INS_LD2R: ld2r $vt, [$rn] */
4174 0,
4175 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4176 },
4177 { /* AArch64_LD2Rv4h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */
4178 0,
4179 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4180 },
4181 { /* AArch64_LD2Rv4s, ARM64_INS_LD2R: ld2r $vt, [$rn] */
4182 0,
4183 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4184 },
4185 { /* AArch64_LD2Rv4s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */
4186 0,
4187 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4188 },
4189 { /* AArch64_LD2Rv8b, ARM64_INS_LD2R: ld2r $vt, [$rn] */
4190 0,
4191 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4192 },
4193 { /* AArch64_LD2Rv8b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */
4194 0,
4195 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4196 },
4197 { /* AArch64_LD2Rv8h, ARM64_INS_LD2R: ld2r $vt, [$rn] */
4198 0,
4199 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4200 },
4201 { /* AArch64_LD2Rv8h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */
4202 0,
4203 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4204 },
4205 { /* AArch64_LD2Twov16b, ARM64_INS_LD2: ld2 $vt, [$rn] */
4206 0,
4207 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4208 },
4209 { /* AArch64_LD2Twov16b_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */
4210 0,
4211 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4212 },
4213 { /* AArch64_LD2Twov2d, ARM64_INS_LD2: ld2 $vt, [$rn] */
4214 0,
4215 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4216 },
4217 { /* AArch64_LD2Twov2d_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */
4218 0,
4219 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4220 },
4221 { /* AArch64_LD2Twov2s, ARM64_INS_LD2: ld2 $vt, [$rn] */
4222 0,
4223 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4224 },
4225 { /* AArch64_LD2Twov2s_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */
4226 0,
4227 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4228 },
4229 { /* AArch64_LD2Twov4h, ARM64_INS_LD2: ld2 $vt, [$rn] */
4230 0,
4231 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4232 },
4233 { /* AArch64_LD2Twov4h_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */
4234 0,
4235 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4236 },
4237 { /* AArch64_LD2Twov4s, ARM64_INS_LD2: ld2 $vt, [$rn] */
4238 0,
4239 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4240 },
4241 { /* AArch64_LD2Twov4s_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */
4242 0,
4243 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4244 },
4245 { /* AArch64_LD2Twov8b, ARM64_INS_LD2: ld2 $vt, [$rn] */
4246 0,
4247 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4248 },
4249 { /* AArch64_LD2Twov8b_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */
4250 0,
4251 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4252 },
4253 { /* AArch64_LD2Twov8h, ARM64_INS_LD2: ld2 $vt, [$rn] */
4254 0,
4255 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4256 },
4257 { /* AArch64_LD2Twov8h_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */
4258 0,
4259 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4260 },
4261 { /* AArch64_LD2i16, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */
4262 0,
4263 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4264 },
4265 { /* AArch64_LD2i16_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */
4266 0,
4267 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4268 },
4269 { /* AArch64_LD2i32, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */
4270 0,
4271 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4272 },
4273 { /* AArch64_LD2i32_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */
4274 0,
4275 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4276 },
4277 { /* AArch64_LD2i64, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */
4278 0,
4279 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4280 },
4281 { /* AArch64_LD2i64_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */
4282 0,
4283 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4284 },
4285 { /* AArch64_LD2i8, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */
4286 0,
4287 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0}
4288 },
4289 { /* AArch64_LD2i8_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */
4290 0,
4291 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
4292 },
4293 { /* AArch64_LD3Rv16b, ARM64_INS_LD3R: ld3r $vt, [$rn] */
4294 0,
4295 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4296 },
4297 { /* AArch64_LD3Rv16b_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */
4298 0,
4299 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4300 },
4301 { /* AArch64_LD3Rv1d, ARM64_INS_LD3R: ld3r $vt, [$rn] */
4302 0,
4303 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4304 },
4305 { /* AArch64_LD3Rv1d_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */
4306 0,
4307 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4308 },
4309 { /* AArch64_LD3Rv2d, ARM64_INS_LD3R: ld3r $vt, [$rn] */
4310 0,
4311 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4312 },
4313 { /* AArch64_LD3Rv2d_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */
4314 0,
4315 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4316 },
4317 { /* AArch64_LD3Rv2s, ARM64_INS_LD3R: ld3r $vt, [$rn] */
4318 0,
4319 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4320 },
4321 { /* AArch64_LD3Rv2s_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */
4322 0,
4323 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4324 },
4325 { /* AArch64_LD3Rv4h, ARM64_INS_LD3R: ld3r $vt, [$rn] */
4326 0,
4327 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4328 },
4329 { /* AArch64_LD3Rv4h_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */
4330 0,
4331 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4332 },
4333 { /* AArch64_LD3Rv4s, ARM64_INS_LD3R: ld3r $vt, [$rn] */
4334 0,
4335 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4336 },
4337 { /* AArch64_LD3Rv4s_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */
4338 0,
4339 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4340 },
4341 { /* AArch64_LD3Rv8b, ARM64_INS_LD3R: ld3r $vt, [$rn] */
4342 0,
4343 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4344 },
4345 { /* AArch64_LD3Rv8b_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */
4346 0,
4347 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4348 },
4349 { /* AArch64_LD3Rv8h, ARM64_INS_LD3R: ld3r $vt, [$rn] */
4350 0,
4351 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4352 },
4353 { /* AArch64_LD3Rv8h_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */
4354 0,
4355 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4356 },
4357 { /* AArch64_LD3Threev16b, ARM64_INS_LD3: ld3 $vt, [$rn] */
4358 0,
4359 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4360 },
4361 { /* AArch64_LD3Threev16b_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */
4362 0,
4363 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4364 },
4365 { /* AArch64_LD3Threev2d, ARM64_INS_LD3: ld3 $vt, [$rn] */
4366 0,
4367 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4368 },
4369 { /* AArch64_LD3Threev2d_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */
4370 0,
4371 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4372 },
4373 { /* AArch64_LD3Threev2s, ARM64_INS_LD3: ld3 $vt, [$rn] */
4374 0,
4375 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4376 },
4377 { /* AArch64_LD3Threev2s_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */
4378 0,
4379 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4380 },
4381 { /* AArch64_LD3Threev4h, ARM64_INS_LD3: ld3 $vt, [$rn] */
4382 0,
4383 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4384 },
4385 { /* AArch64_LD3Threev4h_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */
4386 0,
4387 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4388 },
4389 { /* AArch64_LD3Threev4s, ARM64_INS_LD3: ld3 $vt, [$rn] */
4390 0,
4391 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4392 },
4393 { /* AArch64_LD3Threev4s_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */
4394 0,
4395 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4396 },
4397 { /* AArch64_LD3Threev8b, ARM64_INS_LD3: ld3 $vt, [$rn] */
4398 0,
4399 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4400 },
4401 { /* AArch64_LD3Threev8b_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */
4402 0,
4403 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4404 },
4405 { /* AArch64_LD3Threev8h, ARM64_INS_LD3: ld3 $vt, [$rn] */
4406 0,
4407 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4408 },
4409 { /* AArch64_LD3Threev8h_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */
4410 0,
4411 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4412 },
4413 { /* AArch64_LD3i16, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */
4414 0,
4415 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4416 },
4417 { /* AArch64_LD3i16_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */
4418 0,
4419 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4420 },
4421 { /* AArch64_LD3i32, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */
4422 0,
4423 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4424 },
4425 { /* AArch64_LD3i32_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */
4426 0,
4427 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4428 },
4429 { /* AArch64_LD3i64, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */
4430 0,
4431 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4432 },
4433 { /* AArch64_LD3i64_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */
4434 0,
4435 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4436 },
4437 { /* AArch64_LD3i8, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */
4438 0,
4439 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4440 },
4441 { /* AArch64_LD3i8_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */
4442 0,
4443 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4444 },
4445 { /* AArch64_LD4Fourv16b, ARM64_INS_LD4: ld4 $vt, [$rn] */
4446 0,
4447 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4448 },
4449 { /* AArch64_LD4Fourv16b_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */
4450 0,
4451 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4452 },
4453 { /* AArch64_LD4Fourv2d, ARM64_INS_LD4: ld4 $vt, [$rn] */
4454 0,
4455 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4456 },
4457 { /* AArch64_LD4Fourv2d_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */
4458 0,
4459 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4460 },
4461 { /* AArch64_LD4Fourv2s, ARM64_INS_LD4: ld4 $vt, [$rn] */
4462 0,
4463 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4464 },
4465 { /* AArch64_LD4Fourv2s_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */
4466 0,
4467 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4468 },
4469 { /* AArch64_LD4Fourv4h, ARM64_INS_LD4: ld4 $vt, [$rn] */
4470 0,
4471 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4472 },
4473 { /* AArch64_LD4Fourv4h_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */
4474 0,
4475 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4476 },
4477 { /* AArch64_LD4Fourv4s, ARM64_INS_LD4: ld4 $vt, [$rn] */
4478 0,
4479 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4480 },
4481 { /* AArch64_LD4Fourv4s_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */
4482 0,
4483 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4484 },
4485 { /* AArch64_LD4Fourv8b, ARM64_INS_LD4: ld4 $vt, [$rn] */
4486 0,
4487 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4488 },
4489 { /* AArch64_LD4Fourv8b_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */
4490 0,
4491 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4492 },
4493 { /* AArch64_LD4Fourv8h, ARM64_INS_LD4: ld4 $vt, [$rn] */
4494 0,
4495 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4496 },
4497 { /* AArch64_LD4Fourv8h_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */
4498 0,
4499 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4500 },
4501 { /* AArch64_LD4Rv16b, ARM64_INS_LD4R: ld4r $vt, [$rn] */
4502 0,
4503 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4504 },
4505 { /* AArch64_LD4Rv16b_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */
4506 0,
4507 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4508 },
4509 { /* AArch64_LD4Rv1d, ARM64_INS_LD4R: ld4r $vt, [$rn] */
4510 0,
4511 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4512 },
4513 { /* AArch64_LD4Rv1d_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */
4514 0,
4515 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4516 },
4517 { /* AArch64_LD4Rv2d, ARM64_INS_LD4R: ld4r $vt, [$rn] */
4518 0,
4519 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4520 },
4521 { /* AArch64_LD4Rv2d_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */
4522 0,
4523 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4524 },
4525 { /* AArch64_LD4Rv2s, ARM64_INS_LD4R: ld4r $vt, [$rn] */
4526 0,
4527 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4528 },
4529 { /* AArch64_LD4Rv2s_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */
4530 0,
4531 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4532 },
4533 { /* AArch64_LD4Rv4h, ARM64_INS_LD4R: ld4r $vt, [$rn] */
4534 0,
4535 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4536 },
4537 { /* AArch64_LD4Rv4h_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */
4538 0,
4539 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4540 },
4541 { /* AArch64_LD4Rv4s, ARM64_INS_LD4R: ld4r $vt, [$rn] */
4542 0,
4543 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4544 },
4545 { /* AArch64_LD4Rv4s_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */
4546 0,
4547 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4548 },
4549 { /* AArch64_LD4Rv8b, ARM64_INS_LD4R: ld4r $vt, [$rn] */
4550 0,
4551 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4552 },
4553 { /* AArch64_LD4Rv8b_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */
4554 0,
4555 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4556 },
4557 { /* AArch64_LD4Rv8h, ARM64_INS_LD4R: ld4r $vt, [$rn] */
4558 0,
4559 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4560 },
4561 { /* AArch64_LD4Rv8h_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */
4562 0,
4563 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4564 },
4565 { /* AArch64_LD4i16, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */
4566 0,
4567 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4568 },
4569 { /* AArch64_LD4i16_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */
4570 0,
4571 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4572 },
4573 { /* AArch64_LD4i32, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */
4574 0,
4575 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4576 },
4577 { /* AArch64_LD4i32_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */
4578 0,
4579 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4580 },
4581 { /* AArch64_LD4i64, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */
4582 0,
4583 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4584 },
4585 { /* AArch64_LD4i64_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */
4586 0,
4587 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4588 },
4589 { /* AArch64_LD4i8, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */
4590 0,
4591 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
4592 },
4593 { /* AArch64_LD4i8_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */
4594 0,
4595 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4596 },
4597 { /* AArch64_LDARB, ARM64_INS_LDARB: ldarb $rt, [$rn] */
4598 0,
4599 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4600 },
4601 { /* AArch64_LDARH, ARM64_INS_LDARH: ldarh $rt, [$rn] */
4602 0,
4603 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4604 },
4605 { /* AArch64_LDARW, ARM64_INS_LDAR: ldar $rt, [$rn] */
4606 0,
4607 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4608 },
4609 { /* AArch64_LDARX, ARM64_INS_LDAR: ldar $rt, [$rn] */
4610 0,
4611 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4612 },
4613 { /* AArch64_LDAXPW, ARM64_INS_LDAXP: ldaxp $rt, $rt2, [$rn] */
4614 0,
4615 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4616 },
4617 { /* AArch64_LDAXPX, ARM64_INS_LDAXP: ldaxp $rt, $rt2, [$rn] */
4618 0,
4619 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4620 },
4621 { /* AArch64_LDAXRB, ARM64_INS_LDAXRB: ldaxrb $rt, [$rn] */
4622 0,
4623 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4624 },
4625 { /* AArch64_LDAXRH, ARM64_INS_LDAXRH: ldaxrh $rt, [$rn] */
4626 0,
4627 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4628 },
4629 { /* AArch64_LDAXRW, ARM64_INS_LDAXR: ldaxr $rt, [$rn] */
4630 0,
4631 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4632 },
4633 { /* AArch64_LDAXRX, ARM64_INS_LDAXR: ldaxr $rt, [$rn] */
4634 0,
4635 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4636 },
4637 { /* AArch64_LDNPDi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */
4638 0,
4639 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4640 },
4641 { /* AArch64_LDNPQi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */
4642 0,
4643 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4644 },
4645 { /* AArch64_LDNPSi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */
4646 0,
4647 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4648 },
4649 { /* AArch64_LDNPWi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */
4650 0,
4651 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4652 },
4653 { /* AArch64_LDNPXi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */
4654 0,
4655 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4656 },
4657 { /* AArch64_LDPDi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */
4658 0,
4659 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4660 },
4661 { /* AArch64_LDPDpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */
4662 0,
4663 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4664 },
4665 { /* AArch64_LDPDpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */
4666 0,
4667 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4668 },
4669 { /* AArch64_LDPQi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */
4670 0,
4671 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4672 },
4673 { /* AArch64_LDPQpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */
4674 0,
4675 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4676 },
4677 { /* AArch64_LDPQpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */
4678 0,
4679 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4680 },
4681 { /* AArch64_LDPSWi, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn, $offset] */
4682 0,
4683 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4684 },
4685 { /* AArch64_LDPSWpost, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn], $offset */
4686 0,
4687 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4688 },
4689 { /* AArch64_LDPSWpre, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn, $offset]! */
4690 0,
4691 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4692 },
4693 { /* AArch64_LDPSi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */
4694 0,
4695 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4696 },
4697 { /* AArch64_LDPSpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */
4698 0,
4699 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4700 },
4701 { /* AArch64_LDPSpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */
4702 0,
4703 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4704 },
4705 { /* AArch64_LDPWi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */
4706 0,
4707 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4708 },
4709 { /* AArch64_LDPWpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */
4710 0,
4711 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4712 },
4713 { /* AArch64_LDPWpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */
4714 0,
4715 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4716 },
4717 { /* AArch64_LDPXi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */
4718 0,
4719 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4720 },
4721 { /* AArch64_LDPXpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */
4722 0,
4723 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4724 },
4725 { /* AArch64_LDPXpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */
4726 0,
4727 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4728 },
4729 { /* AArch64_LDRBBpost, ARM64_INS_LDRB: ldrb $rt, [$rn], $offset */
4730 0,
4731 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4732 },
4733 { /* AArch64_LDRBBpre, ARM64_INS_LDRB: ldrb $rt, [$rn, $offset]! */
4734 0,
4735 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4736 },
4737 { /* AArch64_LDRBBroW, ARM64_INS_LDRB: ldrb $rt, [$rn, $rm, $extend] */
4738 0,
4739 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4740 },
4741 { /* AArch64_LDRBBroX, ARM64_INS_LDRB: ldrb $rt, [$rn, $rm, $extend] */
4742 0,
4743 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4744 },
4745 { /* AArch64_LDRBBui, ARM64_INS_LDRB: ldrb $rt, [$rn, $offset] */
4746 0,
4747 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4748 },
4749 { /* AArch64_LDRBpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */
4750 0,
4751 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4752 },
4753 { /* AArch64_LDRBpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */
4754 0,
4755 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4756 },
4757 { /* AArch64_LDRBroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4758 0,
4759 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4760 },
4761 { /* AArch64_LDRBroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4762 0,
4763 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4764 },
4765 { /* AArch64_LDRBui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */
4766 0,
4767 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4768 },
4769 { /* AArch64_LDRDl, ARM64_INS_LDR: ldr $rt, $label */
4770 0,
4771 { CS_OP_WRITE, CS_OP_READ, 0 }
4772 },
4773 { /* AArch64_LDRDpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */
4774 0,
4775 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4776 },
4777 { /* AArch64_LDRDpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */
4778 0,
4779 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4780 },
4781 { /* AArch64_LDRDroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4782 0,
4783 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4784 },
4785 { /* AArch64_LDRDroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4786 0,
4787 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4788 },
4789 { /* AArch64_LDRDui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */
4790 0,
4791 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4792 },
4793 { /* AArch64_LDRHHpost, ARM64_INS_LDRH: ldrh $rt, [$rn], $offset */
4794 0,
4795 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4796 },
4797 { /* AArch64_LDRHHpre, ARM64_INS_LDRH: ldrh $rt, [$rn, $offset]! */
4798 0,
4799 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4800 },
4801 { /* AArch64_LDRHHroW, ARM64_INS_LDRH: ldrh $rt, [$rn, $rm, $extend] */
4802 0,
4803 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4804 },
4805 { /* AArch64_LDRHHroX, ARM64_INS_LDRH: ldrh $rt, [$rn, $rm, $extend] */
4806 0,
4807 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4808 },
4809 { /* AArch64_LDRHHui, ARM64_INS_LDRH: ldrh $rt, [$rn, $offset] */
4810 0,
4811 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4812 },
4813 { /* AArch64_LDRHpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */
4814 0,
4815 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4816 },
4817 { /* AArch64_LDRHpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */
4818 0,
4819 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4820 },
4821 { /* AArch64_LDRHroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4822 0,
4823 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4824 },
4825 { /* AArch64_LDRHroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4826 0,
4827 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4828 },
4829 { /* AArch64_LDRHui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */
4830 0,
4831 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4832 },
4833 { /* AArch64_LDRQl, ARM64_INS_LDR: ldr $rt, $label */
4834 0,
4835 { CS_OP_WRITE, CS_OP_READ, 0 }
4836 },
4837 { /* AArch64_LDRQpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */
4838 0,
4839 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4840 },
4841 { /* AArch64_LDRQpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */
4842 0,
4843 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4844 },
4845 { /* AArch64_LDRQroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4846 0,
4847 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4848 },
4849 { /* AArch64_LDRQroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4850 0,
4851 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4852 },
4853 { /* AArch64_LDRQui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */
4854 0,
4855 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4856 },
4857 { /* AArch64_LDRSBWpost, ARM64_INS_LDRSB: ldrsb $rt, [$rn], $offset */
4858 0,
4859 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4860 },
4861 { /* AArch64_LDRSBWpre, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset]! */
4862 0,
4863 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4864 },
4865 { /* AArch64_LDRSBWroW, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */
4866 0,
4867 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4868 },
4869 { /* AArch64_LDRSBWroX, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */
4870 0,
4871 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4872 },
4873 { /* AArch64_LDRSBWui, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset] */
4874 0,
4875 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4876 },
4877 { /* AArch64_LDRSBXpost, ARM64_INS_LDRSB: ldrsb $rt, [$rn], $offset */
4878 0,
4879 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4880 },
4881 { /* AArch64_LDRSBXpre, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset]! */
4882 0,
4883 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4884 },
4885 { /* AArch64_LDRSBXroW, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */
4886 0,
4887 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4888 },
4889 { /* AArch64_LDRSBXroX, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */
4890 0,
4891 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4892 },
4893 { /* AArch64_LDRSBXui, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset] */
4894 0,
4895 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4896 },
4897 { /* AArch64_LDRSHWpost, ARM64_INS_LDRSH: ldrsh $rt, [$rn], $offset */
4898 0,
4899 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4900 },
4901 { /* AArch64_LDRSHWpre, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset]! */
4902 0,
4903 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4904 },
4905 { /* AArch64_LDRSHWroW, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */
4906 0,
4907 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4908 },
4909 { /* AArch64_LDRSHWroX, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */
4910 0,
4911 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4912 },
4913 { /* AArch64_LDRSHWui, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset] */
4914 0,
4915 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4916 },
4917 { /* AArch64_LDRSHXpost, ARM64_INS_LDRSH: ldrsh $rt, [$rn], $offset */
4918 0,
4919 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4920 },
4921 { /* AArch64_LDRSHXpre, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset]! */
4922 0,
4923 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4924 },
4925 { /* AArch64_LDRSHXroW, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */
4926 0,
4927 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4928 },
4929 { /* AArch64_LDRSHXroX, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */
4930 0,
4931 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4932 },
4933 { /* AArch64_LDRSHXui, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset] */
4934 0,
4935 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4936 },
4937 { /* AArch64_LDRSWl, ARM64_INS_LDRSW: ldrsw $rt, $label */
4938 0,
4939 { CS_OP_WRITE, CS_OP_READ, 0 }
4940 },
4941 { /* AArch64_LDRSWpost, ARM64_INS_LDRSW: ldrsw $rt, [$rn], $offset */
4942 0,
4943 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4944 },
4945 { /* AArch64_LDRSWpre, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $offset]! */
4946 0,
4947 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4948 },
4949 { /* AArch64_LDRSWroW, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $rm, $extend] */
4950 0,
4951 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4952 },
4953 { /* AArch64_LDRSWroX, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $rm, $extend] */
4954 0,
4955 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4956 },
4957 { /* AArch64_LDRSWui, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $offset] */
4958 0,
4959 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4960 },
4961 { /* AArch64_LDRSl, ARM64_INS_LDR: ldr $rt, $label */
4962 0,
4963 { CS_OP_WRITE, CS_OP_READ, 0 }
4964 },
4965 { /* AArch64_LDRSpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */
4966 0,
4967 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4968 },
4969 { /* AArch64_LDRSpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */
4970 0,
4971 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4972 },
4973 { /* AArch64_LDRSroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4974 0,
4975 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4976 },
4977 { /* AArch64_LDRSroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4978 0,
4979 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
4980 },
4981 { /* AArch64_LDRSui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */
4982 0,
4983 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4984 },
4985 { /* AArch64_LDRWl, ARM64_INS_LDR: ldr $rt, $label */
4986 0,
4987 { CS_OP_WRITE, CS_OP_READ, 0 }
4988 },
4989 { /* AArch64_LDRWpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */
4990 0,
4991 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4992 },
4993 { /* AArch64_LDRWpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */
4994 0,
4995 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
4996 },
4997 { /* AArch64_LDRWroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
4998 0,
4999 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5000 },
5001 { /* AArch64_LDRWroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
5002 0,
5003 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5004 },
5005 { /* AArch64_LDRWui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */
5006 0,
5007 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5008 },
5009 { /* AArch64_LDRXl, ARM64_INS_LDR: ldr $rt, $label */
5010 0,
5011 { CS_OP_WRITE, CS_OP_READ, 0 }
5012 },
5013 { /* AArch64_LDRXpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */
5014 0,
5015 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5016 },
5017 { /* AArch64_LDRXpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */
5018 0,
5019 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5020 },
5021 { /* AArch64_LDRXroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
5022 0,
5023 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5024 },
5025 { /* AArch64_LDRXroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */
5026 0,
5027 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5028 },
5029 { /* AArch64_LDRXui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */
5030 0,
5031 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5032 },
5033 { /* AArch64_LDTRBi, ARM64_INS_LDTRB: ldtrb $rt, [$rn, $offset] */
5034 0,
5035 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5036 },
5037 { /* AArch64_LDTRHi, ARM64_INS_LDTRH: ldtrh $rt, [$rn, $offset] */
5038 0,
5039 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5040 },
5041 { /* AArch64_LDTRSBWi, ARM64_INS_LDTRSB: ldtrsb $rt, [$rn, $offset] */
5042 0,
5043 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5044 },
5045 { /* AArch64_LDTRSBXi, ARM64_INS_LDTRSB: ldtrsb $rt, [$rn, $offset] */
5046 0,
5047 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5048 },
5049 { /* AArch64_LDTRSHWi, ARM64_INS_LDTRSH: ldtrsh $rt, [$rn, $offset] */
5050 0,
5051 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5052 },
5053 { /* AArch64_LDTRSHXi, ARM64_INS_LDTRSH: ldtrsh $rt, [$rn, $offset] */
5054 0,
5055 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5056 },
5057 { /* AArch64_LDTRSWi, ARM64_INS_LDTRSW: ldtrsw $rt, [$rn, $offset] */
5058 0,
5059 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5060 },
5061 { /* AArch64_LDTRWi, ARM64_INS_LDTR: ldtr $rt, [$rn, $offset] */
5062 0,
5063 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5064 },
5065 { /* AArch64_LDTRXi, ARM64_INS_LDTR: ldtr $rt, [$rn, $offset] */
5066 0,
5067 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5068 },
5069 { /* AArch64_LDURBBi, ARM64_INS_LDURB: ldurb $rt, [$rn, $offset] */
5070 0,
5071 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5072 },
5073 { /* AArch64_LDURBi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */
5074 0,
5075 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5076 },
5077 { /* AArch64_LDURDi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */
5078 0,
5079 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5080 },
5081 { /* AArch64_LDURHHi, ARM64_INS_LDURH: ldurh $rt, [$rn, $offset] */
5082 0,
5083 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5084 },
5085 { /* AArch64_LDURHi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */
5086 0,
5087 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5088 },
5089 { /* AArch64_LDURQi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */
5090 0,
5091 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5092 },
5093 { /* AArch64_LDURSBWi, ARM64_INS_LDURSB: ldursb $rt, [$rn, $offset] */
5094 0,
5095 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5096 },
5097 { /* AArch64_LDURSBXi, ARM64_INS_LDURSB: ldursb $rt, [$rn, $offset] */
5098 0,
5099 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5100 },
5101 { /* AArch64_LDURSHWi, ARM64_INS_LDURSH: ldursh $rt, [$rn, $offset] */
5102 0,
5103 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5104 },
5105 { /* AArch64_LDURSHXi, ARM64_INS_LDURSH: ldursh $rt, [$rn, $offset] */
5106 0,
5107 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5108 },
5109 { /* AArch64_LDURSWi, ARM64_INS_LDURSW: ldursw $rt, [$rn, $offset] */
5110 0,
5111 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5112 },
5113 { /* AArch64_LDURSi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */
5114 0,
5115 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5116 },
5117 { /* AArch64_LDURWi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */
5118 0,
5119 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5120 },
5121 { /* AArch64_LDURXi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */
5122 0,
5123 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5124 },
5125 { /* AArch64_LDXPW, ARM64_INS_LDXP: ldxp $rt, $rt2, [$rn] */
5126 0,
5127 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5128 },
5129 { /* AArch64_LDXPX, ARM64_INS_LDXP: ldxp $rt, $rt2, [$rn] */
5130 0,
5131 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5132 },
5133 { /* AArch64_LDXRB, ARM64_INS_LDXRB: ldxrb $rt, [$rn] */
5134 0,
5135 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5136 },
5137 { /* AArch64_LDXRH, ARM64_INS_LDXRH: ldxrh $rt, [$rn] */
5138 0,
5139 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5140 },
5141 { /* AArch64_LDXRW, ARM64_INS_LDXR: ldxr $rt, [$rn] */
5142 0,
5143 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5144 },
5145 { /* AArch64_LDXRX, ARM64_INS_LDXR: ldxr $rt, [$rn] */
5146 0,
5147 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5148 },
5149 { /* AArch64_LSLVWr, ARM64_INS_LSL: lsl $rd, $rn, $rm */
5150 0,
5151 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5152 },
5153 { /* AArch64_LSLVXr, ARM64_INS_LSL: lsl $rd, $rn, $rm */
5154 0,
5155 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5156 },
5157 { /* AArch64_LSRVWr, ARM64_INS_LSR: lsr $rd, $rn, $rm */
5158 0,
5159 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5160 },
5161 { /* AArch64_LSRVXr, ARM64_INS_LSR: lsr $rd, $rn, $rm */
5162 0,
5163 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5164 },
5165 { /* AArch64_MADDWrrr, ARM64_INS_MADD: madd $rd, $rn, $rm, $ra */
5166 0,
5167 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5168 },
5169 { /* AArch64_MADDXrrr, ARM64_INS_MADD: madd $rd, $rn, $rm, $ra */
5170 0,
5171 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5172 },
5173 { /* AArch64_MLAv16i8, ARM64_INS_MLA: mla.16b $rd, $rn, $rm */
5174 0,
5175 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5176 },
5177 { /* AArch64_MLAv2i32, ARM64_INS_MLA: mla.2s $rd, $rn, $rm */
5178 0,
5179 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5180 },
5181 { /* AArch64_MLAv2i32_indexed, ARM64_INS_MLA: mla.2s $rd, $rn, $rm$idx */
5182 0,
5183 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5184 },
5185 { /* AArch64_MLAv4i16, ARM64_INS_MLA: mla.4h $rd, $rn, $rm */
5186 0,
5187 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5188 },
5189 { /* AArch64_MLAv4i16_indexed, ARM64_INS_MLA: mla.4h $rd, $rn, $rm$idx */
5190 0,
5191 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5192 },
5193 { /* AArch64_MLAv4i32, ARM64_INS_MLA: mla.4s $rd, $rn, $rm */
5194 0,
5195 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5196 },
5197 { /* AArch64_MLAv4i32_indexed, ARM64_INS_MLA: mla.4s $rd, $rn, $rm$idx */
5198 0,
5199 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5200 },
5201 { /* AArch64_MLAv8i16, ARM64_INS_MLA: mla.8h $rd, $rn, $rm */
5202 0,
5203 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5204 },
5205 { /* AArch64_MLAv8i16_indexed, ARM64_INS_MLA: mla.8h $rd, $rn, $rm$idx */
5206 0,
5207 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5208 },
5209 { /* AArch64_MLAv8i8, ARM64_INS_MLA: mla.8b $rd, $rn, $rm */
5210 0,
5211 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5212 },
5213 { /* AArch64_MLSv16i8, ARM64_INS_MLS: mls.16b $rd, $rn, $rm */
5214 0,
5215 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5216 },
5217 { /* AArch64_MLSv2i32, ARM64_INS_MLS: mls.2s $rd, $rn, $rm */
5218 0,
5219 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5220 },
5221 { /* AArch64_MLSv2i32_indexed, ARM64_INS_MLS: mls.2s $rd, $rn, $rm$idx */
5222 0,
5223 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5224 },
5225 { /* AArch64_MLSv4i16, ARM64_INS_MLS: mls.4h $rd, $rn, $rm */
5226 0,
5227 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5228 },
5229 { /* AArch64_MLSv4i16_indexed, ARM64_INS_MLS: mls.4h $rd, $rn, $rm$idx */
5230 0,
5231 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5232 },
5233 { /* AArch64_MLSv4i32, ARM64_INS_MLS: mls.4s $rd, $rn, $rm */
5234 0,
5235 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5236 },
5237 { /* AArch64_MLSv4i32_indexed, ARM64_INS_MLS: mls.4s $rd, $rn, $rm$idx */
5238 0,
5239 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5240 },
5241 { /* AArch64_MLSv8i16, ARM64_INS_MLS: mls.8h $rd, $rn, $rm */
5242 0,
5243 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5244 },
5245 { /* AArch64_MLSv8i16_indexed, ARM64_INS_MLS: mls.8h $rd, $rn, $rm$idx */
5246 0,
5247 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5248 },
5249 { /* AArch64_MLSv8i8, ARM64_INS_MLS: mls.8b $rd, $rn, $rm */
5250 0,
5251 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5252 },
5253 { /* AArch64_MOVID, ARM64_INS_MOVI: movi $rd, $imm8 */
5254 0,
5255 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5256 },
5257 { /* AArch64_MOVIv16b_ns, ARM64_INS_MOVI: movi.16b $rd, $imm8 */
5258 0,
5259 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5260 },
5261 { /* AArch64_MOVIv2d_ns, ARM64_INS_MOVI: movi.2d $rd, $imm8 */
5262 0,
5263 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5264 },
5265 { /* AArch64_MOVIv2i32, ARM64_INS_MOVI: movi.2s $rd, $imm8$shift */
5266 0,
5267 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5268 },
5269 { /* AArch64_MOVIv2s_msl, ARM64_INS_MOVI: movi.2s $rd, $imm8$shift */
5270 0,
5271 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5272 },
5273 { /* AArch64_MOVIv4i16, ARM64_INS_MOVI: movi.4h $rd, $imm8$shift */
5274 0,
5275 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5276 },
5277 { /* AArch64_MOVIv4i32, ARM64_INS_MOVI: movi.4s $rd, $imm8$shift */
5278 0,
5279 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5280 },
5281 { /* AArch64_MOVIv4s_msl, ARM64_INS_MOVI: movi.4s $rd, $imm8$shift */
5282 0,
5283 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5284 },
5285 { /* AArch64_MOVIv8b_ns, ARM64_INS_MOVI: movi.8b $rd, $imm8 */
5286 0,
5287 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5288 },
5289 { /* AArch64_MOVIv8i16, ARM64_INS_MOVI: movi.8h $rd, $imm8$shift */
5290 0,
5291 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5292 },
5293 { /* AArch64_MOVKWi, ARM64_INS_MOVK: movk $rd, $imm$shift */
5294 0,
5295 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5296 },
5297 { /* AArch64_MOVKXi, ARM64_INS_MOVK: movk $rd, $imm$shift */
5298 0,
5299 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5300 },
5301 { /* AArch64_MOVNWi, ARM64_INS_MOVN: movn $rd, $imm$shift */
5302 0,
5303 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5304 },
5305 { /* AArch64_MOVNXi, ARM64_INS_MOVN: movn $rd, $imm$shift */
5306 0,
5307 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5308 },
5309 { /* AArch64_MOVZWi, ARM64_INS_MOVZ: movz $rd, $imm$shift */
5310 0,
5311 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5312 },
5313 { /* AArch64_MOVZXi, ARM64_INS_MOVZ: movz $rd, $imm$shift */
5314 0,
5315 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5316 },
5317 { /* AArch64_MRS, ARM64_INS_MRS: mrs $rt, $systemreg */
5318 0,
5319 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
5320 },
5321 { /* AArch64_MSR, ARM64_INS_MSR: msr $systemreg, $rt */
5322 0,
5323 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
5324 },
5325 { /* AArch64_MSRpstate, ARM64_INS_MSR: msr $pstate_field, $imm */
5326 0,
5327 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5328 },
5329 { /* AArch64_MSUBWrrr, ARM64_INS_MSUB: msub $rd, $rn, $rm, $ra */
5330 0,
5331 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5332 },
5333 { /* AArch64_MSUBXrrr, ARM64_INS_MSUB: msub $rd, $rn, $rm, $ra */
5334 0,
5335 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5336 },
5337 { /* AArch64_MULv16i8, ARM64_INS_MUL: mul.16b $rd, $rn, $rm| */
5338 0,
5339 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5340 },
5341 { /* AArch64_MULv2i32, ARM64_INS_MUL: mul.2s $rd, $rn, $rm| */
5342 0,
5343 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5344 },
5345 { /* AArch64_MULv2i32_indexed, ARM64_INS_MUL: mul.2s $rd, $rn, $rm$idx */
5346 0,
5347 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5348 },
5349 { /* AArch64_MULv4i16, ARM64_INS_MUL: mul.4h $rd, $rn, $rm| */
5350 0,
5351 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5352 },
5353 { /* AArch64_MULv4i16_indexed, ARM64_INS_MUL: mul.4h $rd, $rn, $rm$idx */
5354 0,
5355 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5356 },
5357 { /* AArch64_MULv4i32, ARM64_INS_MUL: mul.4s $rd, $rn, $rm| */
5358 0,
5359 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5360 },
5361 { /* AArch64_MULv4i32_indexed, ARM64_INS_MUL: mul.4s $rd, $rn, $rm$idx */
5362 0,
5363 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5364 },
5365 { /* AArch64_MULv8i16, ARM64_INS_MUL: mul.8h $rd, $rn, $rm| */
5366 0,
5367 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5368 },
5369 { /* AArch64_MULv8i16_indexed, ARM64_INS_MUL: mul.8h $rd, $rn, $rm$idx */
5370 0,
5371 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5372 },
5373 { /* AArch64_MULv8i8, ARM64_INS_MUL: mul.8b $rd, $rn, $rm| */
5374 0,
5375 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5376 },
5377 { /* AArch64_MVNIv2i32, ARM64_INS_MVNI: mvni.2s $rd, $imm8$shift */
5378 0,
5379 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5380 },
5381 { /* AArch64_MVNIv2s_msl, ARM64_INS_MVNI: mvni.2s $rd, $imm8$shift */
5382 0,
5383 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5384 },
5385 { /* AArch64_MVNIv4i16, ARM64_INS_MVNI: mvni.4h $rd, $imm8$shift */
5386 0,
5387 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5388 },
5389 { /* AArch64_MVNIv4i32, ARM64_INS_MVNI: mvni.4s $rd, $imm8$shift */
5390 0,
5391 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5392 },
5393 { /* AArch64_MVNIv4s_msl, ARM64_INS_MVNI: mvni.4s $rd, $imm8$shift */
5394 0,
5395 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5396 },
5397 { /* AArch64_MVNIv8i16, ARM64_INS_MVNI: mvni.8h $rd, $imm8$shift */
5398 0,
5399 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5400 },
5401 { /* AArch64_NEGv16i8, ARM64_INS_NEG: neg.16b $rd, $rn */
5402 0,
5403 { CS_OP_WRITE, CS_OP_READ, 0 }
5404 },
5405 { /* AArch64_NEGv1i64, ARM64_INS_NEG: neg $rd, $rn */
5406 0,
5407 { CS_OP_WRITE, CS_OP_READ, 0 }
5408 },
5409 { /* AArch64_NEGv2i32, ARM64_INS_NEG: neg.2s $rd, $rn */
5410 0,
5411 { CS_OP_WRITE, CS_OP_READ, 0 }
5412 },
5413 { /* AArch64_NEGv2i64, ARM64_INS_NEG: neg.2d $rd, $rn */
5414 0,
5415 { CS_OP_WRITE, CS_OP_READ, 0 }
5416 },
5417 { /* AArch64_NEGv4i16, ARM64_INS_NEG: neg.4h $rd, $rn */
5418 0,
5419 { CS_OP_WRITE, CS_OP_READ, 0 }
5420 },
5421 { /* AArch64_NEGv4i32, ARM64_INS_NEG: neg.4s $rd, $rn */
5422 0,
5423 { CS_OP_WRITE, CS_OP_READ, 0 }
5424 },
5425 { /* AArch64_NEGv8i16, ARM64_INS_NEG: neg.8h $rd, $rn */
5426 0,
5427 { CS_OP_WRITE, CS_OP_READ, 0 }
5428 },
5429 { /* AArch64_NEGv8i8, ARM64_INS_NEG: neg.8b $rd, $rn */
5430 0,
5431 { CS_OP_WRITE, CS_OP_READ, 0 }
5432 },
5433 { /* AArch64_NOTv16i8, ARM64_INS_NOT: not.16b $rd, $rn */
5434 0,
5435 { CS_OP_WRITE, CS_OP_READ, 0 }
5436 },
5437 { /* AArch64_NOTv8i8, ARM64_INS_NOT: not.8b $rd, $rn */
5438 0,
5439 { CS_OP_WRITE, CS_OP_READ, 0 }
5440 },
5441 { /* AArch64_ORNWrs, ARM64_INS_ORN: orn $rd, $rn, $rm */
5442 0,
5443 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5444 },
5445 { /* AArch64_ORNXrs, ARM64_INS_ORN: orn $rd, $rn, $rm */
5446 0,
5447 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5448 },
5449 { /* AArch64_ORNv16i8, ARM64_INS_ORN: orn.16b $rd, $rn, $rm| */
5450 0,
5451 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5452 },
5453 { /* AArch64_ORNv8i8, ARM64_INS_ORN: orn.8b $rd, $rn, $rm| */
5454 0,
5455 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5456 },
5457 { /* AArch64_ORRWri, ARM64_INS_ORR: orr $rd, $rn, $imm */
5458 0,
5459 { CS_OP_WRITE | CS_OP_READ, , CS_OP_READ, 0 }
5460 },
5461 { /* AArch64_ORRWrs, ARM64_INS_ORR: orr $rd, $rn, $rm */
5462 0,
5463 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5464 },
5465 { /* AArch64_ORRXri, ARM64_INS_ORR: orr $rd, $rn, $imm */
5466 0,
5467 { CS_OP_WRITE | CS_OP_READ, , CS_OP_READ, 0 }
5468 },
5469 { /* AArch64_ORRXrs, ARM64_INS_ORR: orr $rd, $rn, $rm */
5470 0,
5471 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5472 },
5473 { /* AArch64_ORRv16i8, ARM64_INS_ORR: orr.16b $rd, $rn, $rm| */
5474 0,
5475 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5476 },
5477 { /* AArch64_ORRv2i32, ARM64_INS_ORR: orr.2s $rd, $imm8$shift */
5478 0,
5479 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5480 },
5481 { /* AArch64_ORRv4i16, ARM64_INS_ORR: orr.4h $rd, $imm8$shift */
5482 0,
5483 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5484 },
5485 { /* AArch64_ORRv4i32, ARM64_INS_ORR: orr.4s $rd, $imm8$shift */
5486 0,
5487 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5488 },
5489 { /* AArch64_ORRv8i16, ARM64_INS_ORR: orr.8h $rd, $imm8$shift */
5490 0,
5491 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5492 },
5493 { /* AArch64_ORRv8i8, ARM64_INS_ORR: orr.8b $rd, $rn, $rm| */
5494 0,
5495 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
5496 },
5497 { /* AArch64_PMULLv16i8, ARM64_INS_PMULL2: pmull2.8h $rd, $rn, $rm */
5498 0,
5499 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5500 },
5501 { /* AArch64_PMULLv1i64, ARM64_INS_PMULL: pmull.1q $rd, $rn, $rm */
5502 0,
5503 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5504 },
5505 { /* AArch64_PMULLv2i64, ARM64_INS_PMULL2: pmull2.1q $rd, $rn, $rm */
5506 0,
5507 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5508 },
5509 { /* AArch64_PMULLv8i8, ARM64_INS_PMULL: pmull.8h $rd, $rn, $rm */
5510 0,
5511 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5512 },
5513 { /* AArch64_PMULv16i8, ARM64_INS_PMUL: pmul.16b $rd, $rn, $rm| */
5514 0,
5515 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5516 },
5517 { /* AArch64_PMULv8i8, ARM64_INS_PMUL: pmul.8b $rd, $rn, $rm| */
5518 0,
5519 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5520 },
5521 { /* AArch64_PRFMl, ARM64_INS_PRFM: prfm $rt, $label */
5522 0,
5523 { CS_OP_WRITE, CS_OP_READ, 0 }
5524 },
5525 { /* AArch64_PRFMroW, ARM64_INS_PRFM: prfm $rt, [$rn, $rm, $extend] */
5526 0,
5527 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5528 },
5529 { /* AArch64_PRFMroX, ARM64_INS_PRFM: prfm $rt, [$rn, $rm, $extend] */
5530 0,
5531 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5532 },
5533 { /* AArch64_PRFMui, ARM64_INS_PRFM: prfm $rt, [$rn, $offset] */
5534 0,
5535 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5536 },
5537 { /* AArch64_PRFUMi, ARM64_INS_PRFUM: prfum $rt, [$rn, $offset] */
5538 0,
5539 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
5540 },
5541 { /* AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN: raddhn.2s $rd, $rn, $rm */
5542 0,
5543 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5544 },
5545 { /* AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2: raddhn2.4s $rd, $rn, $rm */
5546 0,
5547 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5548 },
5549 { /* AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN: raddhn.4h $rd, $rn, $rm */
5550 0,
5551 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5552 },
5553 { /* AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2: raddhn2.8h $rd, $rn, $rm */
5554 0,
5555 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5556 },
5557 { /* AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2: raddhn2.16b $rd, $rn, $rm */
5558 0,
5559 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5560 },
5561 { /* AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN: raddhn.8b $rd, $rn, $rm */
5562 0,
5563 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5564 },
5565 { /* AArch64_RBITWr, ARM64_INS_RBIT: rbit $rd, $rn */
5566 0,
5567 { CS_OP_WRITE, CS_OP_READ, 0}
5568 },
5569 { /* AArch64_RBITXr, ARM64_INS_RBIT: rbit $rd, $rn */
5570 0,
5571 { CS_OP_WRITE, CS_OP_READ, 0}
5572 },
5573 { /* AArch64_RBITv16i8, ARM64_INS_RBIT: rbit.16b $rd, $rn */
5574 0,
5575 { CS_OP_WRITE, CS_OP_READ, 0}
5576 },
5577 { /* AArch64_RBITv8i8, ARM64_INS_RBIT: rbit.8b $rd, $rn */
5578 0,
5579 { CS_OP_WRITE, CS_OP_READ, 0}
5580 },
5581 { /* AArch64_RET, ARM64_INS_RET: ret $rn */
5582 0,
5583 { CS_OP_READ, 0 }
5584 },
5585 { /* AArch64_REV16Wr, ARM64_INS_REV16: rev16 $rd, $rn */
5586 0,
5587 { CS_OP_WRITE, CS_OP_READ, 0}
5588 },
5589 { /* AArch64_REV16Xr, ARM64_INS_REV16: rev16 $rd, $rn */
5590 0,
5591 { CS_OP_WRITE, CS_OP_READ, 0}
5592 },
5593 { /* AArch64_REV16v16i8, ARM64_INS_REV16: rev16.16b $rd, $rn */
5594 0,
5595 { CS_OP_WRITE, CS_OP_READ, 0}
5596 },
5597 { /* AArch64_REV16v8i8, ARM64_INS_REV16: rev16.8b $rd, $rn */
5598 0,
5599 { CS_OP_WRITE, CS_OP_READ, 0}
5600 },
5601 { /* AArch64_REV32Xr, ARM64_INS_REV32: rev32 $rd, $rn */
5602 0,
5603 { CS_OP_WRITE, CS_OP_READ, 0}
5604 },
5605 { /* AArch64_REV32v16i8, ARM64_INS_REV32: rev32.16b $rd, $rn */
5606 0,
5607 { CS_OP_WRITE, CS_OP_READ, 0}
5608 },
5609 { /* AArch64_REV32v4i16, ARM64_INS_REV32: rev32.4h $rd, $rn */
5610 0,
5611 { CS_OP_WRITE, CS_OP_READ, 0}
5612 },
5613 { /* AArch64_REV32v8i16, ARM64_INS_REV32: rev32.8h $rd, $rn */
5614 0,
5615 { CS_OP_WRITE, CS_OP_READ, 0}
5616 },
5617 { /* AArch64_REV32v8i8, ARM64_INS_REV32: rev32.8b $rd, $rn */
5618 0,
5619 { CS_OP_WRITE, CS_OP_READ, 0}
5620 },
5621 { /* AArch64_REV64v16i8, ARM64_INS_REV64: rev64.16b $rd, $rn */
5622 0,
5623 { CS_OP_WRITE, CS_OP_READ, 0}
5624 },
5625 { /* AArch64_REV64v2i32, ARM64_INS_REV64: rev64.2s $rd, $rn */
5626 0,
5627 { CS_OP_WRITE, CS_OP_READ, 0}
5628 },
5629 { /* AArch64_REV64v4i16, ARM64_INS_REV64: rev64.4h $rd, $rn */
5630 0,
5631 { CS_OP_WRITE, CS_OP_READ, 0}
5632 },
5633 { /* AArch64_REV64v4i32, ARM64_INS_REV64: rev64.4s $rd, $rn */
5634 0,
5635 { CS_OP_WRITE, CS_OP_READ, 0}
5636 },
5637 { /* AArch64_REV64v8i16, ARM64_INS_REV64: rev64.8h $rd, $rn */
5638 0,
5639 { CS_OP_WRITE, CS_OP_READ, 0}
5640 },
5641 { /* AArch64_REV64v8i8, ARM64_INS_REV64: rev64.8b $rd, $rn */
5642 0,
5643 { CS_OP_WRITE, CS_OP_READ, 0}
5644 },
5645 { /* AArch64_REVWr, ARM64_INS_REV: rev $rd, $rn */
5646 0,
5647 { CS_OP_WRITE, CS_OP_READ, 0}
5648 },
5649 { /* AArch64_REVXr, ARM64_INS_REV: rev $rd, $rn */
5650 0,
5651 { CS_OP_WRITE, CS_OP_READ, 0}
5652 },
5653 { /* AArch64_RORVWr, ARM64_INS_ROR: ror $rd, $rn, $rm */
5654 0,
5655 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5656 },
5657 { /* AArch64_RORVXr, ARM64_INS_ROR: ror $rd, $rn, $rm */
5658 0,
5659 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5660 },
5661 { /* AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2: rshrn2.16b $rd, $rn, $imm */
5662 0,
5663 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5664 },
5665 { /* AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN: rshrn.2s $rd, $rn, $imm */
5666 0,
5667 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5668 },
5669 { /* AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN: rshrn.4h $rd, $rn, $imm */
5670 0,
5671 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5672 },
5673 { /* AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2: rshrn2.4s $rd, $rn, $imm */
5674 0,
5675 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5676 },
5677 { /* AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2: rshrn2.8h $rd, $rn, $imm */
5678 0,
5679 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5680 },
5681 { /* AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN: rshrn.8b $rd, $rn, $imm */
5682 0,
5683 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5684 },
5685 { /* AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN: rsubhn.2s $rd, $rn, $rm */
5686 0,
5687 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5688 },
5689 { /* AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2: rsubhn2.4s $rd, $rn, $rm */
5690 0,
5691 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5692 },
5693 { /* AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN: rsubhn.4h $rd, $rn, $rm */
5694 0,
5695 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5696 },
5697 { /* AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2: rsubhn2.8h $rd, $rn, $rm */
5698 0,
5699 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5700 },
5701 { /* AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2: rsubhn2.16b $rd, $rn, $rm */
5702 0,
5703 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5704 },
5705 { /* AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN: rsubhn.8b $rd, $rn, $rm */
5706 0,
5707 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5708 },
5709 { /* AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2: sabal2.8h $rd, $rn, $rm */
5710 0,
5711 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5712 },
5713 { /* AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL: sabal.2d $rd, $rn, $rm */
5714 0,
5715 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5716 },
5717 { /* AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL: sabal.4s $rd, $rn, $rm */
5718 0,
5719 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5720 },
5721 { /* AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2: sabal2.2d $rd, $rn, $rm */
5722 0,
5723 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5724 },
5725 { /* AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2: sabal2.4s $rd, $rn, $rm */
5726 0,
5727 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5728 },
5729 { /* AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL: sabal.8h $rd, $rn, $rm */
5730 0,
5731 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5732 },
5733 { /* AArch64_SABAv16i8, ARM64_INS_SABA: saba.16b $rd, $rn, $rm */
5734 0,
5735 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5736 },
5737 { /* AArch64_SABAv2i32, ARM64_INS_SABA: saba.2s $rd, $rn, $rm */
5738 0,
5739 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5740 },
5741 { /* AArch64_SABAv4i16, ARM64_INS_SABA: saba.4h $rd, $rn, $rm */
5742 0,
5743 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5744 },
5745 { /* AArch64_SABAv4i32, ARM64_INS_SABA: saba.4s $rd, $rn, $rm */
5746 0,
5747 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5748 },
5749 { /* AArch64_SABAv8i16, ARM64_INS_SABA: saba.8h $rd, $rn, $rm */
5750 0,
5751 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5752 },
5753 { /* AArch64_SABAv8i8, ARM64_INS_SABA: saba.8b $rd, $rn, $rm */
5754 0,
5755 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5756 },
5757 { /* AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2: sabdl2.8h $rd, $rn, $rm */
5758 0,
5759 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5760 },
5761 { /* AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL: sabdl.2d $rd, $rn, $rm */
5762 0,
5763 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5764 },
5765 { /* AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL: sabdl.4s $rd, $rn, $rm */
5766 0,
5767 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5768 },
5769 { /* AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2: sabdl2.2d $rd, $rn, $rm */
5770 0,
5771 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5772 },
5773 { /* AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2: sabdl2.4s $rd, $rn, $rm */
5774 0,
5775 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5776 },
5777 { /* AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL: sabdl.8h $rd, $rn, $rm */
5778 0,
5779 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5780 },
5781 { /* AArch64_SABDv16i8, ARM64_INS_SABD: sabd.16b $rd, $rn, $rm| */
5782 0,
5783 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5784 },
5785 { /* AArch64_SABDv2i32, ARM64_INS_SABD: sabd.2s $rd, $rn, $rm| */
5786 0,
5787 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5788 },
5789 { /* AArch64_SABDv4i16, ARM64_INS_SABD: sabd.4h $rd, $rn, $rm| */
5790 0,
5791 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5792 },
5793 { /* AArch64_SABDv4i32, ARM64_INS_SABD: sabd.4s $rd, $rn, $rm| */
5794 0,
5795 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5796 },
5797 { /* AArch64_SABDv8i16, ARM64_INS_SABD: sabd.8h $rd, $rn, $rm| */
5798 0,
5799 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5800 },
5801 { /* AArch64_SABDv8i8, ARM64_INS_SABD: sabd.8b $rd, $rn, $rm| */
5802 0,
5803 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
5804 },
5805 { /* AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP: sadalp.8h $rd, $rn */
5806 0,
5807 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5808 },
5809 { /* AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP: sadalp.1d $rd, $rn */
5810 0,
5811 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5812 },
5813 { /* AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP: sadalp.2s $rd, $rn */
5814 0,
5815 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5816 },
5817 { /* AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP: sadalp.2d $rd, $rn */
5818 0,
5819 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5820 },
5821 { /* AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP: sadalp.4s $rd, $rn */
5822 0,
5823 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5824 },
5825 { /* AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP: sadalp.4h $rd, $rn */
5826 0,
5827 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5828 },
5829 { /* AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP: saddlp.8h $rd, $rn */
5830 0,
5831 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5832 },
5833 { /* AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP: saddlp.1d $rd, $rn */
5834 0,
5835 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5836 },
5837 { /* AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP: saddlp.2s $rd, $rn */
5838 0,
5839 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5840 },
5841 { /* AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP: saddlp.2d $rd, $rn */
5842 0,
5843 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5844 },
5845 { /* AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP: saddlp.4s $rd, $rn */
5846 0,
5847 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5848 },
5849 { /* AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP: saddlp.4h $rd, $rn */
5850 0,
5851 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0}
5852 },
5853 { /* AArch64_SADDLVv16i8v, ARM64_INS_SADDLV: saddlv.16b $rd, $rn */
5854 0,
5855 { CS_OP_WRITE, CS_OP_READ, 0}
5856 },
5857 { /* AArch64_SADDLVv4i16v, ARM64_INS_SADDLV: saddlv.4h $rd, $rn */
5858 0,
5859 { CS_OP_WRITE, CS_OP_READ, 0}
5860 },
5861 { /* AArch64_SADDLVv4i32v, ARM64_INS_SADDLV: saddlv.4s $rd, $rn */
5862 0,
5863 { CS_OP_WRITE, CS_OP_READ, 0}
5864 },
5865 { /* AArch64_SADDLVv8i16v, ARM64_INS_SADDLV: saddlv.8h $rd, $rn */
5866 0,
5867 { CS_OP_WRITE, CS_OP_READ, 0}
5868 },
5869 { /* AArch64_SADDLVv8i8v, ARM64_INS_SADDLV: saddlv.8b $rd, $rn */
5870 0,
5871 { CS_OP_WRITE, CS_OP_READ, 0}
5872 },
5873 { /* AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2: saddl2.8h $rd, $rn, $rm */
5874 0,
5875 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5876 },
5877 { /* AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL: saddl.2d $rd, $rn, $rm */
5878 0,
5879 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5880 },
5881 { /* AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL: saddl.4s $rd, $rn, $rm */
5882 0,
5883 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5884 },
5885 { /* AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2: saddl2.2d $rd, $rn, $rm */
5886 0,
5887 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5888 },
5889 { /* AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2: saddl2.4s $rd, $rn, $rm */
5890 0,
5891 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5892 },
5893 { /* AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL: saddl.8h $rd, $rn, $rm */
5894 0,
5895 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5896 },
5897 { /* AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2: saddw2.8h $rd, $rn, $rm */
5898 0,
5899 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5900 },
5901 { /* AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW: saddw.2d $rd, $rn, $rm */
5902 0,
5903 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5904 },
5905 { /* AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW: saddw.4s $rd, $rn, $rm */
5906 0,
5907 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5908 },
5909 { /* AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2: saddw2.2d $rd, $rn, $rm */
5910 0,
5911 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5912 },
5913 { /* AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2: saddw2.4s $rd, $rn, $rm */
5914 0,
5915 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5916 },
5917 { /* AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW: saddw.8h $rd, $rn, $rm */
5918 0,
5919 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5920 },
5921 { /* AArch64_SBCSWr, ARM64_INS_SBCS: sbcs $rd, $rn, $rm */
5922 0,
5923 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5924 },
5925 { /* AArch64_SBCSXr, ARM64_INS_SBCS: sbcs $rd, $rn, $rm */
5926 0,
5927 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5928 },
5929 { /* AArch64_SBCWr, ARM64_INS_SBC: sbc $rd, $rn, $rm */
5930 0,
5931 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5932 },
5933 { /* AArch64_SBCXr, ARM64_INS_SBC: sbc $rd, $rn, $rm */
5934 0,
5935 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5936 },
5937 { /* AArch64_SBFMWri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */
5938 0,
5939 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5940 },
5941 { /* AArch64_SBFMXri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */
5942 0,
5943 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
5944 },
5945 { /* AArch64_SCVTFSWDri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */
5946 0,
5947 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5948 },
5949 { /* AArch64_SCVTFSWSri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */
5950 0,
5951 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5952 },
5953 { /* AArch64_SCVTFSXDri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */
5954 0,
5955 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5956 },
5957 { /* AArch64_SCVTFSXSri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */
5958 0,
5959 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5960 },
5961 { /* AArch64_SCVTFUWDri, ARM64_INS_SCVTF: scvtf $rd, $rn */
5962 0,
5963 { CS_OP_WRITE, CS_OP_READ, 0}
5964 },
5965 { /* AArch64_SCVTFUWSri, ARM64_INS_SCVTF: scvtf $rd, $rn */
5966 0,
5967 { CS_OP_WRITE, CS_OP_READ, 0}
5968 },
5969 { /* AArch64_SCVTFUXDri, ARM64_INS_SCVTF: scvtf $rd, $rn */
5970 0,
5971 { CS_OP_WRITE, CS_OP_READ, 0}
5972 },
5973 { /* AArch64_SCVTFUXSri, ARM64_INS_SCVTF: scvtf $rd, $rn */
5974 0,
5975 { CS_OP_WRITE, CS_OP_READ, 0}
5976 },
5977 { /* AArch64_SCVTFd, ARM64_INS_SCVTF: scvtf $rd, $rn, $imm */
5978 0,
5979 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5980 },
5981 { /* AArch64_SCVTFs, ARM64_INS_SCVTF: scvtf $rd, $rn, $imm */
5982 0,
5983 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
5984 },
5985 { /* AArch64_SCVTFv1i32, ARM64_INS_SCVTF: scvtf $rd, $rn */
5986 0,
5987 { CS_OP_WRITE, CS_OP_READ, 0}
5988 },
5989 { /* AArch64_SCVTFv1i64, ARM64_INS_SCVTF: scvtf $rd, $rn */
5990 0,
5991 { CS_OP_WRITE, CS_OP_READ, 0}
5992 },
5993 { /* AArch64_SCVTFv2f32, ARM64_INS_SCVTF: scvtf.2s $rd, $rn */
5994 0,
5995 { CS_OP_WRITE, CS_OP_READ, 0}
5996 },
5997 { /* AArch64_SCVTFv2f64, ARM64_INS_SCVTF: scvtf.2d $rd, $rn */
5998 0,
5999 { CS_OP_WRITE, CS_OP_READ, 0}
6000 },
6001 { /* AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF: scvtf.2s $rd, $rn, $imm */
6002 0,
6003 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6004 },
6005 { /* AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF: scvtf.2d $rd, $rn, $imm */
6006 0,
6007 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6008 },
6009 { /* AArch64_SCVTFv4f32, ARM64_INS_SCVTF: scvtf.4s $rd, $rn */
6010 0,
6011 { CS_OP_WRITE, CS_OP_READ, 0}
6012 },
6013 { /* AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF: scvtf.4s $rd, $rn, $imm */
6014 0,
6015 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6016 },
6017 { /* AArch64_SDIVWr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */
6018 0,
6019 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6020 },
6021 { /* AArch64_SDIVXr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */
6022 0,
6023 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6024 },
6025 { /* AArch64_SDIV_IntWr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */
6026 0,
6027 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6028 },
6029 { /* AArch64_SDIV_IntXr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */
6030 0,
6031 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6032 },
6033 { /* AArch64_SHA1Crrr, ARM64_INS_SHA1C: sha1c.4s $rd, $rn, $rm */
6034 0,
6035 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6036 },
6037 { /* AArch64_SHA1Hrr, ARM64_INS_SHA1H: sha1h $rd, $rn */
6038 0,
6039 { CS_OP_WRITE, CS_OP_READ, 0 }
6040 },
6041 { /* AArch64_SHA1Mrrr, ARM64_INS_SHA1M: sha1m.4s $rd, $rn, $rm */
6042 0,
6043 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6044 },
6045 { /* AArch64_SHA1Prrr, ARM64_INS_SHA1P: sha1p.4s $rd, $rn, $rm */
6046 0,
6047 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6048 },
6049 { /* AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0: sha1su0.4s $rd, $rn, $rm */
6050 0,
6051 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6052 },
6053 { /* AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1: sha1su1.4s $rd, $rn */
6054 0,
6055 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
6056 },
6057 { /* AArch64_SHA256H2rrr, ARM64_INS_SHA256H2: sha256h2.4s $rd, $rn, $rm */
6058 0,
6059 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6060 },
6061 { /* AArch64_SHA256Hrrr, ARM64_INS_SHA256H: sha256h.4s $rd, $rn, $rm */
6062 0,
6063 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6064 },
6065 { /* AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0: sha256su0.4s $rd, $rn */
6066 0,
6067 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
6068 },
6069 { /* AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1: sha256su1.4s $rd, $rn, $rm */
6070 0,
6071 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6072 },
6073 { /* AArch64_SHADDv16i8, ARM64_INS_SHADD: shadd.16b $rd, $rn, $rm| */
6074 0,
6075 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6076 },
6077 { /* AArch64_SHADDv2i32, ARM64_INS_SHADD: shadd.2s $rd, $rn, $rm| */
6078 0,
6079 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6080 },
6081 { /* AArch64_SHADDv4i16, ARM64_INS_SHADD: shadd.4h $rd, $rn, $rm| */
6082 0,
6083 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6084 },
6085 { /* AArch64_SHADDv4i32, ARM64_INS_SHADD: shadd.4s $rd, $rn, $rm| */
6086 0,
6087 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6088 },
6089 { /* AArch64_SHADDv8i16, ARM64_INS_SHADD: shadd.8h $rd, $rn, $rm| */
6090 0,
6091 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6092 },
6093 { /* AArch64_SHADDv8i8, ARM64_INS_SHADD: shadd.8b $rd, $rn, $rm| */
6094 0,
6095 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6096 },
6097 { /* AArch64_SHLLv16i8, ARM64_INS_SHLL2: shll2.8h $rd, $rn, #8 */
6098 0,
6099 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6100 },
6101 { /* AArch64_SHLLv2i32, ARM64_INS_SHLL: shll.2d $rd, $rn, #32 */
6102 0,
6103 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6104 },
6105 { /* AArch64_SHLLv4i16, ARM64_INS_SHLL: shll.4s $rd, $rn, #16 */
6106 0,
6107 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6108 },
6109 { /* AArch64_SHLLv4i32, ARM64_INS_SHLL2: shll2.2d $rd, $rn, #32 */
6110 0,
6111 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6112 },
6113 { /* AArch64_SHLLv8i16, ARM64_INS_SHLL2: shll2.4s $rd, $rn, #16 */
6114 0,
6115 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6116 },
6117 { /* AArch64_SHLLv8i8, ARM64_INS_SHLL: shll.8h $rd, $rn, #8 */
6118 0,
6119 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6120 },
6121 { /* AArch64_SHLd, ARM64_INS_SHL: shl $rd, $rn, $imm */
6122 0,
6123 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6124 },
6125 { /* AArch64_SHLv16i8_shift, ARM64_INS_SHL: shl.16b $rd, $rn, $imm */
6126 0,
6127 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6128 },
6129 { /* AArch64_SHLv2i32_shift, ARM64_INS_SHL: shl.2s $rd, $rn, $imm */
6130 0,
6131 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6132 },
6133 { /* AArch64_SHLv2i64_shift, ARM64_INS_SHL: shl.2d $rd, $rn, $imm */
6134 0,
6135 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6136 },
6137 { /* AArch64_SHLv4i16_shift, ARM64_INS_SHL: shl.4h $rd, $rn, $imm */
6138 0,
6139 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6140 },
6141 { /* AArch64_SHLv4i32_shift, ARM64_INS_SHL: shl.4s $rd, $rn, $imm */
6142 0,
6143 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6144 },
6145 { /* AArch64_SHLv8i16_shift, ARM64_INS_SHL: shl.8h $rd, $rn, $imm */
6146 0,
6147 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6148 },
6149 { /* AArch64_SHLv8i8_shift, ARM64_INS_SHL: shl.8b $rd, $rn, $imm */
6150 0,
6151 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6152 },
6153 { /* AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2: shrn2.16b $rd, $rn, $imm */
6154 0,
6155 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6156 },
6157 { /* AArch64_SHRNv2i32_shift, ARM64_INS_SHRN: shrn.2s $rd, $rn, $imm */
6158 0,
6159 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6160 },
6161 { /* AArch64_SHRNv4i16_shift, ARM64_INS_SHRN: shrn.4h $rd, $rn, $imm */
6162 0,
6163 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6164 },
6165 { /* AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2: shrn2.4s $rd, $rn, $imm */
6166 0,
6167 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6168 },
6169 { /* AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2: shrn2.8h $rd, $rn, $imm */
6170 0,
6171 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6172 },
6173 { /* AArch64_SHRNv8i8_shift, ARM64_INS_SHRN: shrn.8b $rd, $rn, $imm */
6174 0,
6175 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6176 },
6177 { /* AArch64_SHSUBv16i8, ARM64_INS_SHSUB: shsub.16b $rd, $rn, $rm| */
6178 0,
6179 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6180 },
6181 { /* AArch64_SHSUBv2i32, ARM64_INS_SHSUB: shsub.2s $rd, $rn, $rm| */
6182 0,
6183 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6184 },
6185 { /* AArch64_SHSUBv4i16, ARM64_INS_SHSUB: shsub.4h $rd, $rn, $rm| */
6186 0,
6187 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6188 },
6189 { /* AArch64_SHSUBv4i32, ARM64_INS_SHSUB: shsub.4s $rd, $rn, $rm| */
6190 0,
6191 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6192 },
6193 { /* AArch64_SHSUBv8i16, ARM64_INS_SHSUB: shsub.8h $rd, $rn, $rm| */
6194 0,
6195 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6196 },
6197 { /* AArch64_SHSUBv8i8, ARM64_INS_SHSUB: shsub.8b $rd, $rn, $rm| */
6198 0,
6199 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0}
6200 },
6201 { /* AArch64_SLId, ARM64_INS_SLI: sli $rd, $rn, $imm */
6202 0,
6203 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
6204 },
6205 { /* AArch64_SLIv16i8_shift, ARM64_INS_SLI: sli.16b $rd, $rn, $imm */
6206 0,
6207 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
6208 },
6209 { /* AArch64_SLIv2i32_shift, ARM64_INS_SLI: sli.2s $rd, $rn, $imm */
6210 0,
6211 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
6212 },
6213 { /* AArch64_SLIv2i64_shift, ARM64_INS_SLI: sli.2d $rd, $rn, $imm */
6214 0,
6215 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
6216 },
6217 { /* AArch64_SLIv4i16_shift, ARM64_INS_SLI: sli.4h $rd, $rn, $imm */
6218 0,
6219 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
6220 },
6221 { /* AArch64_SLIv4i32_shift, ARM64_INS_SLI: sli.4s $rd, $rn, $imm */
6222 0,
6223 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
6224 },
6225 { /* AArch64_SLIv8i16_shift, ARM64_INS_SLI: sli.8h $rd, $rn, $imm */
6226 0,
6227 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
6228 },
6229 { /* AArch64_SLIv8i8_shift, ARM64_INS_SLI: sli.8b $rd, $rn, $imm */
6230 0,
6231 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0}
6232 },
6233 { /* AArch64_SMADDLrrr, ARM64_INS_SMADDL: smaddl $rd, $rn, $rm, $ra */
6234 0,
6235 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6236 },
6237 { /* AArch64_SMAXPv16i8, ARM64_INS_SMAXP: smaxp.16b $rd, $rn, $rm| */
6238 0,
6239 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6240 },
6241 { /* AArch64_SMAXPv2i32, ARM64_INS_SMAXP: smaxp.2s $rd, $rn, $rm| */
6242 0,
6243 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6244 },
6245 { /* AArch64_SMAXPv4i16, ARM64_INS_SMAXP: smaxp.4h $rd, $rn, $rm| */
6246 0,
6247 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6248 },
6249 { /* AArch64_SMAXPv4i32, ARM64_INS_SMAXP: smaxp.4s $rd, $rn, $rm| */
6250 0,
6251 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6252 },
6253 { /* AArch64_SMAXPv8i16, ARM64_INS_SMAXP: smaxp.8h $rd, $rn, $rm| */
6254 0,
6255 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6256 },
6257 { /* AArch64_SMAXPv8i8, ARM64_INS_SMAXP: smaxp.8b $rd, $rn, $rm| */
6258 0,
6259 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6260 },
6261 { /* AArch64_SMAXVv16i8v, ARM64_INS_SMAXV: smaxv.16b $rd, $rn */
6262 0,
6263 { CS_OP_WRITE, CS_OP_READ, 0 }
6264 },
6265 { /* AArch64_SMAXVv4i16v, ARM64_INS_SMAXV: smaxv.4h $rd, $rn */
6266 0,
6267 { CS_OP_WRITE, CS_OP_READ, 0 }
6268 },
6269 { /* AArch64_SMAXVv4i32v, ARM64_INS_SMAXV: smaxv.4s $rd, $rn */
6270 0,
6271 { CS_OP_WRITE, CS_OP_READ, 0 }
6272 },
6273 { /* AArch64_SMAXVv8i16v, ARM64_INS_SMAXV: smaxv.8h $rd, $rn */
6274 0,
6275 { CS_OP_WRITE, CS_OP_READ, 0 }
6276 },
6277 { /* AArch64_SMAXVv8i8v, ARM64_INS_SMAXV: smaxv.8b $rd, $rn */
6278 0,
6279 { CS_OP_WRITE, CS_OP_READ, 0 }
6280 },
6281 { /* AArch64_SMAXv16i8, ARM64_INS_SMAX: smax.16b $rd, $rn, $rm| */
6282 0,
6283 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6284 },
6285 { /* AArch64_SMAXv2i32, ARM64_INS_SMAX: smax.2s $rd, $rn, $rm| */
6286 0,
6287 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6288 },
6289 { /* AArch64_SMAXv4i16, ARM64_INS_SMAX: smax.4h $rd, $rn, $rm| */
6290 0,
6291 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6292 },
6293 { /* AArch64_SMAXv4i32, ARM64_INS_SMAX: smax.4s $rd, $rn, $rm| */
6294 0,
6295 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6296 },
6297 { /* AArch64_SMAXv8i16, ARM64_INS_SMAX: smax.8h $rd, $rn, $rm| */
6298 0,
6299 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6300 },
6301 { /* AArch64_SMAXv8i8, ARM64_INS_SMAX: smax.8b $rd, $rn, $rm| */
6302 0,
6303 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6304 },
6305 { /* AArch64_SMC, ARM64_INS_SMC: smc $imm */
6306 0,
6307 { CS_OP_READ, 0 }
6308 },
6309 { /* AArch64_SMINPv16i8, ARM64_INS_SMINP: sminp.16b $rd, $rn, $rm| */
6310 0,
6311 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6312 },
6313 { /* AArch64_SMINPv2i32, ARM64_INS_SMINP: sminp.2s $rd, $rn, $rm| */
6314 0,
6315 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6316 },
6317 { /* AArch64_SMINPv4i16, ARM64_INS_SMINP: sminp.4h $rd, $rn, $rm| */
6318 0,
6319 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6320 },
6321 { /* AArch64_SMINPv4i32, ARM64_INS_SMINP: sminp.4s $rd, $rn, $rm| */
6322 0,
6323 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6324 },
6325 { /* AArch64_SMINPv8i16, ARM64_INS_SMINP: sminp.8h $rd, $rn, $rm| */
6326 0,
6327 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6328 },
6329 { /* AArch64_SMINPv8i8, ARM64_INS_SMINP: sminp.8b $rd, $rn, $rm| */
6330 0,
6331 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6332 },
6333 { /* AArch64_SMINVv16i8v, ARM64_INS_SMINV: sminv.16b $rd, $rn */
6334 0,
6335 { CS_OP_WRITE, CS_OP_READ, 0 }
6336 },
6337 { /* AArch64_SMINVv4i16v, ARM64_INS_SMINV: sminv.4h $rd, $rn */
6338 0,
6339 { CS_OP_WRITE, CS_OP_READ, 0 }
6340 },
6341 { /* AArch64_SMINVv4i32v, ARM64_INS_SMINV: sminv.4s $rd, $rn */
6342 0,
6343 { CS_OP_WRITE, CS_OP_READ, 0 }
6344 },
6345 { /* AArch64_SMINVv8i16v, ARM64_INS_SMINV: sminv.8h $rd, $rn */
6346 0,
6347 { CS_OP_WRITE, CS_OP_READ, 0 }
6348 },
6349 { /* AArch64_SMINVv8i8v, ARM64_INS_SMINV: sminv.8b $rd, $rn */
6350 0,
6351 { CS_OP_WRITE, CS_OP_READ, 0 }
6352 },
6353 { /* AArch64_SMINv16i8, ARM64_INS_SMIN: smin.16b $rd, $rn, $rm| */
6354 0,
6355 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6356 },
6357 { /* AArch64_SMINv2i32, ARM64_INS_SMIN: smin.2s $rd, $rn, $rm| */
6358 0,
6359 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6360 },
6361 { /* AArch64_SMINv4i16, ARM64_INS_SMIN: smin.4h $rd, $rn, $rm| */
6362 0,
6363 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6364 },
6365 { /* AArch64_SMINv4i32, ARM64_INS_SMIN: smin.4s $rd, $rn, $rm| */
6366 0,
6367 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6368 },
6369 { /* AArch64_SMINv8i16, ARM64_INS_SMIN: smin.8h $rd, $rn, $rm| */
6370 0,
6371 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6372 },
6373 { /* AArch64_SMINv8i8, ARM64_INS_SMIN: smin.8b $rd, $rn, $rm| */
6374 0,
6375 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6376 },
6377 { /* AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2: smlal2.8h $rd, $rn, $rm */
6378 0,
6379 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6380 },
6381 { /* AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL: smlal.2d $rd, $rn, $rm$idx */
6382 0,
6383 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6384 },
6385 { /* AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL: smlal.2d $rd, $rn, $rm */
6386 0,
6387 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6388 },
6389 { /* AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL: smlal.4s $rd, $rn, $rm$idx */
6390 0,
6391 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6392 },
6393 { /* AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL: smlal.4s $rd, $rn, $rm */
6394 0,
6395 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6396 },
6397 { /* AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2: smlal2.2d $rd, $rn, $rm$idx */
6398 0,
6399 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6400 },
6401 { /* AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2: smlal2.2d $rd, $rn, $rm */
6402 0,
6403 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6404 },
6405 { /* AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2: smlal2.4s $rd, $rn, $rm$idx */
6406 0,
6407 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6408 },
6409 { /* AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2: smlal2.4s $rd, $rn, $rm */
6410 0,
6411 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6412 },
6413 { /* AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL: smlal.8h $rd, $rn, $rm */
6414 0,
6415 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6416 },
6417 { /* AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2: smlsl2.8h $rd, $rn, $rm */
6418 0,
6419 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6420 },
6421 { /* AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL: smlsl.2d $rd, $rn, $rm$idx */
6422 0,
6423 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6424 },
6425 { /* AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL: smlsl.2d $rd, $rn, $rm */
6426 0,
6427 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6428 },
6429 { /* AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL: smlsl.4s $rd, $rn, $rm$idx */
6430 0,
6431 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6432 },
6433 { /* AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL: smlsl.4s $rd, $rn, $rm */
6434 0,
6435 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6436 },
6437 { /* AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2: smlsl2.2d $rd, $rn, $rm$idx */
6438 0,
6439 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6440 },
6441 { /* AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2: smlsl2.2d $rd, $rn, $rm */
6442 0,
6443 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6444 },
6445 { /* AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2: smlsl2.4s $rd, $rn, $rm$idx */
6446 0,
6447 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6448 },
6449 { /* AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2: smlsl2.4s $rd, $rn, $rm */
6450 0,
6451 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6452 },
6453 { /* AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL: smlsl.8h $rd, $rn, $rm */
6454 0,
6455 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6456 },
6457 { /* AArch64_SMOVvi16to32, ARM64_INS_SMOV: smov.h $rd, $rn$idx */
6458 0,
6459 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6460 },
6461 { /* AArch64_SMOVvi16to64, ARM64_INS_SMOV: smov.h $rd, $rn$idx */
6462 0,
6463 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6464 },
6465 { /* AArch64_SMOVvi32to64, ARM64_INS_SMOV: smov.s $rd, $rn$idx */
6466 0,
6467 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6468 },
6469 { /* AArch64_SMOVvi8to32, ARM64_INS_SMOV: smov.b $rd, $rn$idx */
6470 0,
6471 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6472 },
6473 { /* AArch64_SMOVvi8to64, ARM64_INS_SMOV: smov.b $rd, $rn$idx */
6474 0,
6475 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6476 },
6477 { /* AArch64_SMSUBLrrr, ARM64_INS_SMSUBL: smsubl $rd, $rn, $rm, $ra */
6478 0,
6479 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6480 },
6481 { /* AArch64_SMULHrr, ARM64_INS_SMULH: smulh $rd, $rn, $rm */
6482 0,
6483 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6484 },
6485 { /* AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2: smull2.8h $rd, $rn, $rm */
6486 0,
6487 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6488 },
6489 { /* AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL: smull.2d $rd, $rn, $rm$idx */
6490 0,
6491 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6492 },
6493 { /* AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL: smull.2d $rd, $rn, $rm */
6494 0,
6495 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6496 },
6497 { /* AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL: smull.4s $rd, $rn, $rm$idx */
6498 0,
6499 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6500 },
6501 { /* AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL: smull.4s $rd, $rn, $rm */
6502 0,
6503 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6504 },
6505 { /* AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2: smull2.2d $rd, $rn, $rm$idx */
6506 0,
6507 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6508 },
6509 { /* AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2: smull2.2d $rd, $rn, $rm */
6510 0,
6511 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6512 },
6513 { /* AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2: smull2.4s $rd, $rn, $rm$idx */
6514 0,
6515 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6516 },
6517 { /* AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2: smull2.4s $rd, $rn, $rm */
6518 0,
6519 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6520 },
6521 { /* AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL: smull.8h $rd, $rn, $rm */
6522 0,
6523 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6524 },
6525 { /* AArch64_SQABSv16i8, ARM64_INS_SQABS: sqabs.16b $rd, $rn */
6526 0,
6527 { CS_OP_WRITE, CS_OP_READ, 0 }
6528 },
6529 { /* AArch64_SQABSv1i16, ARM64_INS_SQABS: sqabs $rd, $rn */
6530 0,
6531 { CS_OP_WRITE, CS_OP_READ, 0 }
6532 },
6533 { /* AArch64_SQABSv1i32, ARM64_INS_SQABS: sqabs $rd, $rn */
6534 0,
6535 { CS_OP_WRITE, CS_OP_READ, 0 }
6536 },
6537 { /* AArch64_SQABSv1i64, ARM64_INS_SQABS: sqabs $rd, $rn */
6538 0,
6539 { CS_OP_WRITE, CS_OP_READ, 0 }
6540 },
6541 { /* AArch64_SQABSv1i8, ARM64_INS_SQABS: sqabs $rd, $rn */
6542 0,
6543 { CS_OP_WRITE, CS_OP_READ, 0 }
6544 },
6545 { /* AArch64_SQABSv2i32, ARM64_INS_SQABS: sqabs.2s $rd, $rn */
6546 0,
6547 { CS_OP_WRITE, CS_OP_READ, 0 }
6548 },
6549 { /* AArch64_SQABSv2i64, ARM64_INS_SQABS: sqabs.2d $rd, $rn */
6550 0,
6551 { CS_OP_WRITE, CS_OP_READ, 0 }
6552 },
6553 { /* AArch64_SQABSv4i16, ARM64_INS_SQABS: sqabs.4h $rd, $rn */
6554 0,
6555 { CS_OP_WRITE, CS_OP_READ, 0 }
6556 },
6557 { /* AArch64_SQABSv4i32, ARM64_INS_SQABS: sqabs.4s $rd, $rn */
6558 0,
6559 { CS_OP_WRITE, CS_OP_READ, 0 }
6560 },
6561 { /* AArch64_SQABSv8i16, ARM64_INS_SQABS: sqabs.8h $rd, $rn */
6562 0,
6563 { CS_OP_WRITE, CS_OP_READ, 0 }
6564 },
6565 { /* AArch64_SQABSv8i8, ARM64_INS_SQABS: sqabs.8b $rd, $rn */
6566 0,
6567 { CS_OP_WRITE, CS_OP_READ, 0 }
6568 },
6569 { /* AArch64_SQADDv16i8, ARM64_INS_SQADD: sqadd.16b $rd, $rn, $rm| */
6570 0,
6571 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6572 },
6573 { /* AArch64_SQADDv1i16, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */
6574 0,
6575 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6576 },
6577 { /* AArch64_SQADDv1i32, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */
6578 0,
6579 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6580 },
6581 { /* AArch64_SQADDv1i64, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */
6582 0,
6583 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6584 },
6585 { /* AArch64_SQADDv1i8, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */
6586 0,
6587 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6588 },
6589 { /* AArch64_SQADDv2i32, ARM64_INS_SQADD: sqadd.2s $rd, $rn, $rm| */
6590 0,
6591 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6592 },
6593 { /* AArch64_SQADDv2i64, ARM64_INS_SQADD: sqadd.2d $rd, $rn, $rm| */
6594 0,
6595 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6596 },
6597 { /* AArch64_SQADDv4i16, ARM64_INS_SQADD: sqadd.4h $rd, $rn, $rm| */
6598 0,
6599 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6600 },
6601 { /* AArch64_SQADDv4i32, ARM64_INS_SQADD: sqadd.4s $rd, $rn, $rm| */
6602 0,
6603 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6604 },
6605 { /* AArch64_SQADDv8i16, ARM64_INS_SQADD: sqadd.8h $rd, $rn, $rm| */
6606 0,
6607 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6608 },
6609 { /* AArch64_SQADDv8i8, ARM64_INS_SQADD: sqadd.8b $rd, $rn, $rm| */
6610 0,
6611 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6612 },
6613 { /* AArch64_SQDMLALi16, ARM64_INS_SQDMLAL: sqdmlal $rd, $rn, $rm */
6614 0,
6615 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6616 },
6617 { /* AArch64_SQDMLALi32, ARM64_INS_SQDMLAL: sqdmlal $rd, $rn, $rm */
6618 0,
6619 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6620 },
6621 { /* AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL: sqdmlal.h $rd, $rn, $rm$idx */
6622 0,
6623 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6624 },
6625 { /* AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL: sqdmlal.s $rd, $rn, $rm$idx */
6626 0,
6627 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6628 },
6629 { /* AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL: sqdmlal.2d $rd, $rn, $rm$idx */
6630 0,
6631 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6632 },
6633 { /* AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL: sqdmlal.2d $rd, $rn, $rm */
6634 0,
6635 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6636 },
6637 { /* AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL: sqdmlal.4s $rd, $rn, $rm$idx */
6638 0,
6639 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6640 },
6641 { /* AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL: sqdmlal.4s $rd, $rn, $rm */
6642 0,
6643 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6644 },
6645 { /* AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2: sqdmlal2.2d $rd, $rn, $rm$idx */
6646 0,
6647 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6648 },
6649 { /* AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2: sqdmlal2.2d $rd, $rn, $rm */
6650 0,
6651 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6652 },
6653 { /* AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2: sqdmlal2.4s $rd, $rn, $rm$idx */
6654 0,
6655 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6656 },
6657 { /* AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2: sqdmlal2.4s $rd, $rn, $rm */
6658 0,
6659 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6660 },
6661 { /* AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL: sqdmlsl $rd, $rn, $rm */
6662 0,
6663 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6664 },
6665 { /* AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL: sqdmlsl $rd, $rn, $rm */
6666 0,
6667 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6668 },
6669 { /* AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL: sqdmlsl.h $rd, $rn, $rm$idx */
6670 0,
6671 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6672 },
6673 { /* AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL: sqdmlsl.s $rd, $rn, $rm$idx */
6674 0,
6675 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6676 },
6677 { /* AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL: sqdmlsl.2d $rd, $rn, $rm$idx */
6678 0,
6679 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6680 },
6681 { /* AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL: sqdmlsl.2d $rd, $rn, $rm */
6682 0,
6683 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6684 },
6685 { /* AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL: sqdmlsl.4s $rd, $rn, $rm$idx */
6686 0,
6687 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6688 },
6689 { /* AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL: sqdmlsl.4s $rd, $rn, $rm */
6690 0,
6691 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6692 },
6693 { /* AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2: sqdmlsl2.2d $rd, $rn, $rm$idx */
6694 0,
6695 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6696 },
6697 { /* AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2: sqdmlsl2.2d $rd, $rn, $rm */
6698 0,
6699 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6700 },
6701 { /* AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2: sqdmlsl2.4s $rd, $rn, $rm$idx */
6702 0,
6703 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6704 },
6705 { /* AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2: sqdmlsl2.4s $rd, $rn, $rm */
6706 0,
6707 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6708 },
6709 { /* AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH: sqdmulh $rd, $rn, $rm */
6710 0,
6711 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6712 },
6713 { /* AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH: sqdmulh.h $rd, $rn, $rm$idx */
6714 0,
6715 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6716 },
6717 { /* AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH: sqdmulh $rd, $rn, $rm */
6718 0,
6719 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6720 },
6721 { /* AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH: sqdmulh.s $rd, $rn, $rm$idx */
6722 0,
6723 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6724 },
6725 { /* AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH: sqdmulh.2s $rd, $rn, $rm| */
6726 0,
6727 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6728 },
6729 { /* AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH: sqdmulh.2s $rd, $rn, $rm$idx */
6730 0,
6731 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6732 },
6733 { /* AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH: sqdmulh.4h $rd, $rn, $rm| */
6734 0,
6735 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6736 },
6737 { /* AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH: sqdmulh.4h $rd, $rn, $rm$idx */
6738 0,
6739 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6740 },
6741 { /* AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH: sqdmulh.4s $rd, $rn, $rm| */
6742 0,
6743 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6744 },
6745 { /* AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH: sqdmulh.4s $rd, $rn, $rm$idx */
6746 0,
6747 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6748 },
6749 { /* AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH: sqdmulh.8h $rd, $rn, $rm| */
6750 0,
6751 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6752 },
6753 { /* AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH: sqdmulh.8h $rd, $rn, $rm$idx */
6754 0,
6755 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6756 },
6757 { /* AArch64_SQDMULLi16, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */
6758 0,
6759 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6760 },
6761 { /* AArch64_SQDMULLi32, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */
6762 0,
6763 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6764 },
6765 { /* AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL: sqdmull.h $rd, $rn, $rm$idx */
6766 0,
6767 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6768 },
6769 { /* AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL: sqdmull.s $rd, $rn, $rm$idx */
6770 0,
6771 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6772 },
6773 { /* AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm$idx */
6774 0,
6775 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6776 },
6777 { /* AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm */
6778 0,
6779 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6780 },
6781 { /* AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm$idx */
6782 0,
6783 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6784 },
6785 { /* AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm */
6786 0,
6787 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6788 },
6789 { /* AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2: sqdmull2.2d $rd, $rn, $rm$idx */
6790 0,
6791 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6792 },
6793 { /* AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2: sqdmull2.2d $rd, $rn, $rm */
6794 0,
6795 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6796 },
6797 { /* AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2: sqdmull2.4s $rd, $rn, $rm$idx */
6798 0,
6799 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6800 },
6801 { /* AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2: sqdmull2.4s $rd, $rn, $rm */
6802 0,
6803 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6804 },
6805 { /* AArch64_SQNEGv16i8, ARM64_INS_SQNEG: sqneg.16b $rd, $rn */
6806 0,
6807 { CS_OP_WRITE, CS_OP_READ, 0 }
6808 },
6809 { /* AArch64_SQNEGv1i16, ARM64_INS_SQNEG: sqneg $rd, $rn */
6810 0,
6811 { CS_OP_WRITE, CS_OP_READ, 0 }
6812 },
6813 { /* AArch64_SQNEGv1i32, ARM64_INS_SQNEG: sqneg $rd, $rn */
6814 0,
6815 { CS_OP_WRITE, CS_OP_READ, 0 }
6816 },
6817 { /* AArch64_SQNEGv1i64, ARM64_INS_SQNEG: sqneg $rd, $rn */
6818 0,
6819 { CS_OP_WRITE, CS_OP_READ, 0 }
6820 },
6821 { /* AArch64_SQNEGv1i8, ARM64_INS_SQNEG: sqneg $rd, $rn */
6822 0,
6823 { CS_OP_WRITE, CS_OP_READ, 0 }
6824 },
6825 { /* AArch64_SQNEGv2i32, ARM64_INS_SQNEG: sqneg.2s $rd, $rn */
6826 0,
6827 { CS_OP_WRITE, CS_OP_READ, 0 }
6828 },
6829 { /* AArch64_SQNEGv2i64, ARM64_INS_SQNEG: sqneg.2d $rd, $rn */
6830 0,
6831 { CS_OP_WRITE, CS_OP_READ, 0 }
6832 },
6833 { /* AArch64_SQNEGv4i16, ARM64_INS_SQNEG: sqneg.4h $rd, $rn */
6834 0,
6835 { CS_OP_WRITE, CS_OP_READ, 0 }
6836 },
6837 { /* AArch64_SQNEGv4i32, ARM64_INS_SQNEG: sqneg.4s $rd, $rn */
6838 0,
6839 { CS_OP_WRITE, CS_OP_READ, 0 }
6840 },
6841 { /* AArch64_SQNEGv8i16, ARM64_INS_SQNEG: sqneg.8h $rd, $rn */
6842 0,
6843 { CS_OP_WRITE, CS_OP_READ, 0 }
6844 },
6845 { /* AArch64_SQNEGv8i8, ARM64_INS_SQNEG: sqneg.8b $rd, $rn */
6846 0,
6847 { CS_OP_WRITE, CS_OP_READ, 0 }
6848 },
6849 { /* AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH: sqrdmulh $rd, $rn, $rm */
6850 0,
6851 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6852 },
6853 { /* AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.h $rd, $rn, $rm$idx */
6854 0,
6855 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6856 },
6857 { /* AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH: sqrdmulh $rd, $rn, $rm */
6858 0,
6859 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6860 },
6861 { /* AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.s $rd, $rn, $rm$idx */
6862 0,
6863 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6864 },
6865 { /* AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH: sqrdmulh.2s $rd, $rn, $rm| */
6866 0,
6867 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6868 },
6869 { /* AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.2s $rd, $rn, $rm$idx */
6870 0,
6871 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6872 },
6873 { /* AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH: sqrdmulh.4h $rd, $rn, $rm| */
6874 0,
6875 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6876 },
6877 { /* AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.4h $rd, $rn, $rm$idx */
6878 0,
6879 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6880 },
6881 { /* AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH: sqrdmulh.4s $rd, $rn, $rm| */
6882 0,
6883 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6884 },
6885 { /* AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.4s $rd, $rn, $rm$idx */
6886 0,
6887 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6888 },
6889 { /* AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH: sqrdmulh.8h $rd, $rn, $rm| */
6890 0,
6891 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6892 },
6893 { /* AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.8h $rd, $rn, $rm$idx */
6894 0,
6895 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
6896 },
6897 { /* AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL: sqrshl.16b $rd, $rn, $rm| */
6898 0,
6899 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6900 },
6901 { /* AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */
6902 0,
6903 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6904 },
6905 { /* AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */
6906 0,
6907 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6908 },
6909 { /* AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */
6910 0,
6911 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6912 },
6913 { /* AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */
6914 0,
6915 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6916 },
6917 { /* AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL: sqrshl.2s $rd, $rn, $rm| */
6918 0,
6919 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6920 },
6921 { /* AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL: sqrshl.2d $rd, $rn, $rm| */
6922 0,
6923 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6924 },
6925 { /* AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL: sqrshl.4h $rd, $rn, $rm| */
6926 0,
6927 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6928 },
6929 { /* AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL: sqrshl.4s $rd, $rn, $rm| */
6930 0,
6931 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6932 },
6933 { /* AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL: sqrshl.8h $rd, $rn, $rm| */
6934 0,
6935 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6936 },
6937 { /* AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL: sqrshl.8b $rd, $rn, $rm| */
6938 0,
6939 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6940 },
6941 { /* AArch64_SQRSHRNb, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */
6942 0,
6943 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6944 },
6945 { /* AArch64_SQRSHRNh, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */
6946 0,
6947 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6948 },
6949 { /* AArch64_SQRSHRNs, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */
6950 0,
6951 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6952 },
6953 { /* AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2: sqrshrn2.16b $rd, $rn, $imm */
6954 0,
6955 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6956 },
6957 { /* AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN: sqrshrn.2s $rd, $rn, $imm */
6958 0,
6959 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6960 },
6961 { /* AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN: sqrshrn.4h $rd, $rn, $imm */
6962 0,
6963 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6964 },
6965 { /* AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2: sqrshrn2.4s $rd, $rn, $imm */
6966 0,
6967 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6968 },
6969 { /* AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2: sqrshrn2.8h $rd, $rn, $imm */
6970 0,
6971 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6972 },
6973 { /* AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN: sqrshrn.8b $rd, $rn, $imm */
6974 0,
6975 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6976 },
6977 { /* AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */
6978 0,
6979 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6980 },
6981 { /* AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */
6982 0,
6983 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6984 },
6985 { /* AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */
6986 0,
6987 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6988 },
6989 { /* AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.16b $rd, $rn, $imm */
6990 0,
6991 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6992 },
6993 { /* AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN: sqrshrun.2s $rd, $rn, $imm */
6994 0,
6995 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
6996 },
6997 { /* AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN: sqrshrun.4h $rd, $rn, $imm */
6998 0,
6999 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7000 },
7001 { /* AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.4s $rd, $rn, $imm */
7002 0,
7003 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7004 },
7005 { /* AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.8h $rd, $rn, $imm */
7006 0,
7007 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7008 },
7009 { /* AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN: sqrshrun.8b $rd, $rn, $imm */
7010 0,
7011 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7012 },
7013 { /* AArch64_SQSHLUb, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */
7014 0,
7015 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7016 },
7017 { /* AArch64_SQSHLUd, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */
7018 0,
7019 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7020 },
7021 { /* AArch64_SQSHLUh, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */
7022 0,
7023 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7024 },
7025 { /* AArch64_SQSHLUs, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */
7026 0,
7027 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7028 },
7029 { /* AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU: sqshlu.16b $rd, $rn, $imm */
7030 0,
7031 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7032 },
7033 { /* AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU: sqshlu.2s $rd, $rn, $imm */
7034 0,
7035 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7036 },
7037 { /* AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU: sqshlu.2d $rd, $rn, $imm */
7038 0,
7039 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7040 },
7041 { /* AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU: sqshlu.4h $rd, $rn, $imm */
7042 0,
7043 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7044 },
7045 { /* AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU: sqshlu.4s $rd, $rn, $imm */
7046 0,
7047 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7048 },
7049 { /* AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU: sqshlu.8h $rd, $rn, $imm */
7050 0,
7051 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7052 },
7053 { /* AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU: sqshlu.8b $rd, $rn, $imm */
7054 0,
7055 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7056 },
7057 { /* AArch64_SQSHLb, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */
7058 0,
7059 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7060 },
7061 { /* AArch64_SQSHLd, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */
7062 0,
7063 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7064 },
7065 { /* AArch64_SQSHLh, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */
7066 0,
7067 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7068 },
7069 { /* AArch64_SQSHLs, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */
7070 0,
7071 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7072 },
7073 { /* AArch64_SQSHLv16i8, ARM64_INS_SQSHL: sqshl.16b $rd, $rn, $rm| */
7074 0,
7075 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7076 },
7077 { /* AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL: sqshl.16b $rd, $rn, $imm */
7078 0,
7079 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7080 },
7081 { /* AArch64_SQSHLv1i16, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */
7082 0,
7083 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7084 },
7085 { /* AArch64_SQSHLv1i32, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */
7086 0,
7087 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7088 },
7089 { /* AArch64_SQSHLv1i64, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */
7090 0,
7091 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7092 },
7093 { /* AArch64_SQSHLv1i8, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */
7094 0,
7095 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7096 },
7097 { /* AArch64_SQSHLv2i32, ARM64_INS_SQSHL: sqshl.2s $rd, $rn, $rm| */
7098 0,
7099 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7100 },
7101 { /* AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL: sqshl.2s $rd, $rn, $imm */
7102 0,
7103 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7104 },
7105 { /* AArch64_SQSHLv2i64, ARM64_INS_SQSHL: sqshl.2d $rd, $rn, $rm| */
7106 0,
7107 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7108 },
7109 { /* AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL: sqshl.2d $rd, $rn, $imm */
7110 0,
7111 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7112 },
7113 { /* AArch64_SQSHLv4i16, ARM64_INS_SQSHL: sqshl.4h $rd, $rn, $rm| */
7114 0,
7115 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7116 },
7117 { /* AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL: sqshl.4h $rd, $rn, $imm */
7118 0,
7119 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7120 },
7121 { /* AArch64_SQSHLv4i32, ARM64_INS_SQSHL: sqshl.4s $rd, $rn, $rm| */
7122 0,
7123 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7124 },
7125 { /* AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL: sqshl.4s $rd, $rn, $imm */
7126 0,
7127 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7128 },
7129 { /* AArch64_SQSHLv8i16, ARM64_INS_SQSHL: sqshl.8h $rd, $rn, $rm| */
7130 0,
7131 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7132 },
7133 { /* AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL: sqshl.8h $rd, $rn, $imm */
7134 0,
7135 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7136 },
7137 { /* AArch64_SQSHLv8i8, ARM64_INS_SQSHL: sqshl.8b $rd, $rn, $rm| */
7138 0,
7139 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7140 },
7141 { /* AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL: sqshl.8b $rd, $rn, $imm */
7142 0,
7143 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7144 },
7145 { /* AArch64_SQSHRNb, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */
7146 0,
7147 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7148 },
7149 { /* AArch64_SQSHRNh, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */
7150 0,
7151 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7152 },
7153 { /* AArch64_SQSHRNs, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */
7154 0,
7155 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7156 },
7157 { /* AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2: sqshrn2.16b $rd, $rn, $imm */
7158 0,
7159 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7160 },
7161 { /* AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN: sqshrn.2s $rd, $rn, $imm */
7162 0,
7163 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7164 },
7165 { /* AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN: sqshrn.4h $rd, $rn, $imm */
7166 0,
7167 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7168 },
7169 { /* AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2: sqshrn2.4s $rd, $rn, $imm */
7170 0,
7171 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7172 },
7173 { /* AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2: sqshrn2.8h $rd, $rn, $imm */
7174 0,
7175 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7176 },
7177 { /* AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN: sqshrn.8b $rd, $rn, $imm */
7178 0,
7179 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7180 },
7181 { /* AArch64_SQSHRUNb, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */
7182 0,
7183 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7184 },
7185 { /* AArch64_SQSHRUNh, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */
7186 0,
7187 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7188 },
7189 { /* AArch64_SQSHRUNs, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */
7190 0,
7191 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7192 },
7193 { /* AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2: sqshrun2.16b $rd, $rn, $imm */
7194 0,
7195 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7196 },
7197 { /* AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN: sqshrun.2s $rd, $rn, $imm */
7198 0,
7199 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7200 },
7201 { /* AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN: sqshrun.4h $rd, $rn, $imm */
7202 0,
7203 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7204 },
7205 { /* AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2: sqshrun2.4s $rd, $rn, $imm */
7206 0,
7207 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7208 },
7209 { /* AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2: sqshrun2.8h $rd, $rn, $imm */
7210 0,
7211 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7212 },
7213 { /* AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN: sqshrun.8b $rd, $rn, $imm */
7214 0,
7215 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7216 },
7217 { /* AArch64_SQSUBv16i8, ARM64_INS_SQSUB: sqsub.16b $rd, $rn, $rm| */
7218 0,
7219 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7220 },
7221 { /* AArch64_SQSUBv1i16, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */
7222 0,
7223 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7224 },
7225 { /* AArch64_SQSUBv1i32, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */
7226 0,
7227 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7228 },
7229 { /* AArch64_SQSUBv1i64, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */
7230 0,
7231 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7232 },
7233 { /* AArch64_SQSUBv1i8, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */
7234 0,
7235 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7236 },
7237 { /* AArch64_SQSUBv2i32, ARM64_INS_SQSUB: sqsub.2s $rd, $rn, $rm| */
7238 0,
7239 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7240 },
7241 { /* AArch64_SQSUBv2i64, ARM64_INS_SQSUB: sqsub.2d $rd, $rn, $rm| */
7242 0,
7243 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7244 },
7245 { /* AArch64_SQSUBv4i16, ARM64_INS_SQSUB: sqsub.4h $rd, $rn, $rm| */
7246 0,
7247 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7248 },
7249 { /* AArch64_SQSUBv4i32, ARM64_INS_SQSUB: sqsub.4s $rd, $rn, $rm| */
7250 0,
7251 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7252 },
7253 { /* AArch64_SQSUBv8i16, ARM64_INS_SQSUB: sqsub.8h $rd, $rn, $rm| */
7254 0,
7255 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7256 },
7257 { /* AArch64_SQSUBv8i8, ARM64_INS_SQSUB: sqsub.8b $rd, $rn, $rm| */
7258 0,
7259 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7260 },
7261 { /* AArch64_SQXTNv16i8, ARM64_INS_SQXTN2: sqxtn2.16b $rd, $rn */
7262 0,
7263 { CS_OP_WRITE, CS_OP_READ, 0 }
7264 },
7265 { /* AArch64_SQXTNv1i16, ARM64_INS_SQXTN: sqxtn $rd, $rn */
7266 0,
7267 { CS_OP_WRITE, CS_OP_READ, 0 }
7268 },
7269 { /* AArch64_SQXTNv1i32, ARM64_INS_SQXTN: sqxtn $rd, $rn */
7270 0,
7271 { CS_OP_WRITE, CS_OP_READ, 0 }
7272 },
7273 { /* AArch64_SQXTNv1i8, ARM64_INS_SQXTN: sqxtn $rd, $rn */
7274 0,
7275 { CS_OP_WRITE, CS_OP_READ, 0 }
7276 },
7277 { /* AArch64_SQXTNv2i32, ARM64_INS_SQXTN: sqxtn.2s $rd, $rn */
7278 0,
7279 { CS_OP_WRITE, CS_OP_READ, 0 }
7280 },
7281 { /* AArch64_SQXTNv4i16, ARM64_INS_SQXTN: sqxtn.4h $rd, $rn */
7282 0,
7283 { CS_OP_WRITE, CS_OP_READ, 0 }
7284 },
7285 { /* AArch64_SQXTNv4i32, ARM64_INS_SQXTN2: sqxtn2.4s $rd, $rn */
7286 0,
7287 { CS_OP_WRITE, CS_OP_READ, 0 }
7288 },
7289 { /* AArch64_SQXTNv8i16, ARM64_INS_SQXTN2: sqxtn2.8h $rd, $rn */
7290 0,
7291 { CS_OP_WRITE, CS_OP_READ, 0 }
7292 },
7293 { /* AArch64_SQXTNv8i8, ARM64_INS_SQXTN: sqxtn.8b $rd, $rn */
7294 0,
7295 { CS_OP_WRITE, CS_OP_READ, 0 }
7296 },
7297 { /* AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2: sqxtun2.16b $rd, $rn */
7298 0,
7299 { CS_OP_WRITE, CS_OP_READ, 0 }
7300 },
7301 { /* AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN: sqxtun $rd, $rn */
7302 0,
7303 { CS_OP_WRITE, CS_OP_READ, 0 }
7304 },
7305 { /* AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN: sqxtun $rd, $rn */
7306 0,
7307 { CS_OP_WRITE, CS_OP_READ, 0 }
7308 },
7309 { /* AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN: sqxtun $rd, $rn */
7310 0,
7311 { CS_OP_WRITE, CS_OP_READ, 0 }
7312 },
7313 { /* AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN: sqxtun.2s $rd, $rn */
7314 0,
7315 { CS_OP_WRITE, CS_OP_READ, 0 }
7316 },
7317 { /* AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN: sqxtun.4h $rd, $rn */
7318 0,
7319 { CS_OP_WRITE, CS_OP_READ, 0 }
7320 },
7321 { /* AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2: sqxtun2.4s $rd, $rn */
7322 0,
7323 { CS_OP_WRITE, CS_OP_READ, 0 }
7324 },
7325 { /* AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2: sqxtun2.8h $rd, $rn */
7326 0,
7327 { CS_OP_WRITE, CS_OP_READ, 0 }
7328 },
7329 { /* AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN: sqxtun.8b $rd, $rn */
7330 0,
7331 { CS_OP_WRITE, CS_OP_READ, 0 }
7332 },
7333 { /* AArch64_SRHADDv16i8, ARM64_INS_SRHADD: srhadd.16b $rd, $rn, $rm| */
7334 0,
7335 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7336 },
7337 { /* AArch64_SRHADDv2i32, ARM64_INS_SRHADD: srhadd.2s $rd, $rn, $rm| */
7338 0,
7339 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7340 },
7341 { /* AArch64_SRHADDv4i16, ARM64_INS_SRHADD: srhadd.4h $rd, $rn, $rm| */
7342 0,
7343 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7344 },
7345 { /* AArch64_SRHADDv4i32, ARM64_INS_SRHADD: srhadd.4s $rd, $rn, $rm| */
7346 0,
7347 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7348 },
7349 { /* AArch64_SRHADDv8i16, ARM64_INS_SRHADD: srhadd.8h $rd, $rn, $rm| */
7350 0,
7351 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7352 },
7353 { /* AArch64_SRHADDv8i8, ARM64_INS_SRHADD: srhadd.8b $rd, $rn, $rm| */
7354 0,
7355 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7356 },
7357 { /* AArch64_SRId, ARM64_INS_SRI: sri $rd, $rn, $imm */
7358 0,
7359 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7360 },
7361 { /* AArch64_SRIv16i8_shift, ARM64_INS_SRI: sri.16b $rd, $rn, $imm */
7362 0,
7363 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7364 },
7365 { /* AArch64_SRIv2i32_shift, ARM64_INS_SRI: sri.2s $rd, $rn, $imm */
7366 0,
7367 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7368 },
7369 { /* AArch64_SRIv2i64_shift, ARM64_INS_SRI: sri.2d $rd, $rn, $imm */
7370 0,
7371 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7372 },
7373 { /* AArch64_SRIv4i16_shift, ARM64_INS_SRI: sri.4h $rd, $rn, $imm */
7374 0,
7375 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7376 },
7377 { /* AArch64_SRIv4i32_shift, ARM64_INS_SRI: sri.4s $rd, $rn, $imm */
7378 0,
7379 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7380 },
7381 { /* AArch64_SRIv8i16_shift, ARM64_INS_SRI: sri.8h $rd, $rn, $imm */
7382 0,
7383 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7384 },
7385 { /* AArch64_SRIv8i8_shift, ARM64_INS_SRI: sri.8b $rd, $rn, $imm */
7386 0,
7387 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7388 },
7389 { /* AArch64_SRSHLv16i8, ARM64_INS_SRSHL: srshl.16b $rd, $rn, $rm| */
7390 0,
7391 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7392 },
7393 { /* AArch64_SRSHLv1i64, ARM64_INS_SRSHL: srshl $rd, $rn, $rm */
7394 0,
7395 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7396 },
7397 { /* AArch64_SRSHLv2i32, ARM64_INS_SRSHL: srshl.2s $rd, $rn, $rm| */
7398 0,
7399 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7400 },
7401 { /* AArch64_SRSHLv2i64, ARM64_INS_SRSHL: srshl.2d $rd, $rn, $rm| */
7402 0,
7403 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7404 },
7405 { /* AArch64_SRSHLv4i16, ARM64_INS_SRSHL: srshl.4h $rd, $rn, $rm| */
7406 0,
7407 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7408 },
7409 { /* AArch64_SRSHLv4i32, ARM64_INS_SRSHL: srshl.4s $rd, $rn, $rm| */
7410 0,
7411 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7412 },
7413 { /* AArch64_SRSHLv8i16, ARM64_INS_SRSHL: srshl.8h $rd, $rn, $rm| */
7414 0,
7415 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7416 },
7417 { /* AArch64_SRSHLv8i8, ARM64_INS_SRSHL: srshl.8b $rd, $rn, $rm| */
7418 0,
7419 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7420 },
7421 { /* AArch64_SRSHRd, ARM64_INS_SRSHR: srshr $rd, $rn, $imm */
7422 0,
7423 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7424 },
7425 { /* AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR: srshr.16b $rd, $rn, $imm */
7426 0,
7427 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7428 },
7429 { /* AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR: srshr.2s $rd, $rn, $imm */
7430 0,
7431 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7432 },
7433 { /* AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR: srshr.2d $rd, $rn, $imm */
7434 0,
7435 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7436 },
7437 { /* AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR: srshr.4h $rd, $rn, $imm */
7438 0,
7439 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7440 },
7441 { /* AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR: srshr.4s $rd, $rn, $imm */
7442 0,
7443 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7444 },
7445 { /* AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR: srshr.8h $rd, $rn, $imm */
7446 0,
7447 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7448 },
7449 { /* AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR: srshr.8b $rd, $rn, $imm */
7450 0,
7451 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7452 },
7453 { /* AArch64_SRSRAd, ARM64_INS_SRSRA: srsra $rd, $rn, $imm */
7454 0,
7455 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7456 },
7457 { /* AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA: srsra.16b $rd, $rn, $imm */
7458 0,
7459 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7460 },
7461 { /* AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA: srsra.2s $rd, $rn, $imm */
7462 0,
7463 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7464 },
7465 { /* AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA: srsra.2d $rd, $rn, $imm */
7466 0,
7467 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7468 },
7469 { /* AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA: srsra.4h $rd, $rn, $imm */
7470 0,
7471 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7472 },
7473 { /* AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA: srsra.4s $rd, $rn, $imm */
7474 0,
7475 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7476 },
7477 { /* AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA: srsra.8h $rd, $rn, $imm */
7478 0,
7479 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7480 },
7481 { /* AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA: srsra.8b $rd, $rn, $imm */
7482 0,
7483 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7484 },
7485 { /* AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2: sshll2.8h $rd, $rn, $imm */
7486 0,
7487 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7488 },
7489 { /* AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL: sshll.2d $rd, $rn, $imm */
7490 0,
7491 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7492 },
7493 { /* AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL: sshll.4s $rd, $rn, $imm */
7494 0,
7495 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7496 },
7497 { /* AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2: sshll2.2d $rd, $rn, $imm */
7498 0,
7499 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7500 },
7501 { /* AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2: sshll2.4s $rd, $rn, $imm */
7502 0,
7503 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7504 },
7505 { /* AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL: sshll.8h $rd, $rn, $imm */
7506 0,
7507 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7508 },
7509 { /* AArch64_SSHLv16i8, ARM64_INS_SSHL: sshl.16b $rd, $rn, $rm| */
7510 0,
7511 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7512 },
7513 { /* AArch64_SSHLv1i64, ARM64_INS_SSHL: sshl $rd, $rn, $rm */
7514 0,
7515 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7516 },
7517 { /* AArch64_SSHLv2i32, ARM64_INS_SSHL: sshl.2s $rd, $rn, $rm| */
7518 0,
7519 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7520 },
7521 { /* AArch64_SSHLv2i64, ARM64_INS_SSHL: sshl.2d $rd, $rn, $rm| */
7522 0,
7523 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7524 },
7525 { /* AArch64_SSHLv4i16, ARM64_INS_SSHL: sshl.4h $rd, $rn, $rm| */
7526 0,
7527 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7528 },
7529 { /* AArch64_SSHLv4i32, ARM64_INS_SSHL: sshl.4s $rd, $rn, $rm| */
7530 0,
7531 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7532 },
7533 { /* AArch64_SSHLv8i16, ARM64_INS_SSHL: sshl.8h $rd, $rn, $rm| */
7534 0,
7535 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7536 },
7537 { /* AArch64_SSHLv8i8, ARM64_INS_SSHL: sshl.8b $rd, $rn, $rm| */
7538 0,
7539 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7540 },
7541 { /* AArch64_SSHRd, ARM64_INS_SSHR: sshr $rd, $rn, $imm */
7542 0,
7543 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7544 },
7545 { /* AArch64_SSHRv16i8_shift, ARM64_INS_SSHR: sshr.16b $rd, $rn, $imm */
7546 0,
7547 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7548 },
7549 { /* AArch64_SSHRv2i32_shift, ARM64_INS_SSHR: sshr.2s $rd, $rn, $imm */
7550 0,
7551 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7552 },
7553 { /* AArch64_SSHRv2i64_shift, ARM64_INS_SSHR: sshr.2d $rd, $rn, $imm */
7554 0,
7555 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7556 },
7557 { /* AArch64_SSHRv4i16_shift, ARM64_INS_SSHR: sshr.4h $rd, $rn, $imm */
7558 0,
7559 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7560 },
7561 { /* AArch64_SSHRv4i32_shift, ARM64_INS_SSHR: sshr.4s $rd, $rn, $imm */
7562 0,
7563 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7564 },
7565 { /* AArch64_SSHRv8i16_shift, ARM64_INS_SSHR: sshr.8h $rd, $rn, $imm */
7566 0,
7567 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7568 },
7569 { /* AArch64_SSHRv8i8_shift, ARM64_INS_SSHR: sshr.8b $rd, $rn, $imm */
7570 0,
7571 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7572 },
7573 { /* AArch64_SSRAd, ARM64_INS_SSRA: ssra $rd, $rn, $imm */
7574 0,
7575 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7576 },
7577 { /* AArch64_SSRAv16i8_shift, ARM64_INS_SSRA: ssra.16b $rd, $rn, $imm */
7578 0,
7579 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7580 },
7581 { /* AArch64_SSRAv2i32_shift, ARM64_INS_SSRA: ssra.2s $rd, $rn, $imm */
7582 0,
7583 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7584 },
7585 { /* AArch64_SSRAv2i64_shift, ARM64_INS_SSRA: ssra.2d $rd, $rn, $imm */
7586 0,
7587 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7588 },
7589 { /* AArch64_SSRAv4i16_shift, ARM64_INS_SSRA: ssra.4h $rd, $rn, $imm */
7590 0,
7591 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7592 },
7593 { /* AArch64_SSRAv4i32_shift, ARM64_INS_SSRA: ssra.4s $rd, $rn, $imm */
7594 0,
7595 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7596 },
7597 { /* AArch64_SSRAv8i16_shift, ARM64_INS_SSRA: ssra.8h $rd, $rn, $imm */
7598 0,
7599 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7600 },
7601 { /* AArch64_SSRAv8i8_shift, ARM64_INS_SSRA: ssra.8b $rd, $rn, $imm */
7602 0,
7603 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
7604 },
7605 { /* AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2: ssubl2.8h $rd, $rn, $rm */
7606 0,
7607 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7608 },
7609 { /* AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL: ssubl.2d $rd, $rn, $rm */
7610 0,
7611 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7612 },
7613 { /* AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL: ssubl.4s $rd, $rn, $rm */
7614 0,
7615 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7616 },
7617 { /* AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2: ssubl2.2d $rd, $rn, $rm */
7618 0,
7619 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7620 },
7621 { /* AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2: ssubl2.4s $rd, $rn, $rm */
7622 0,
7623 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7624 },
7625 { /* AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL: ssubl.8h $rd, $rn, $rm */
7626 0,
7627 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7628 },
7629 { /* AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2: ssubw2.8h $rd, $rn, $rm */
7630 0,
7631 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7632 },
7633 { /* AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW: ssubw.2d $rd, $rn, $rm */
7634 0,
7635 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7636 },
7637 { /* AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW: ssubw.4s $rd, $rn, $rm */
7638 0,
7639 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7640 },
7641 { /* AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2: ssubw2.2d $rd, $rn, $rm */
7642 0,
7643 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7644 },
7645 { /* AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2: ssubw2.4s $rd, $rn, $rm */
7646 0,
7647 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7648 },
7649 { /* AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW: ssubw.8h $rd, $rn, $rm */
7650 0,
7651 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
7652 },
7653 { /* AArch64_ST1Fourv16b, ARM64_INS_ST1: st1 $vt, [$rn] */
7654 0,
7655 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7656 },
7657 { /* AArch64_ST1Fourv16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7658 0,
7659 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7660 },
7661 { /* AArch64_ST1Fourv1d, ARM64_INS_ST1: st1 $vt, [$rn] */
7662 0,
7663 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7664 },
7665 { /* AArch64_ST1Fourv1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7666 0,
7667 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7668 },
7669 { /* AArch64_ST1Fourv2d, ARM64_INS_ST1: st1 $vt, [$rn] */
7670 0,
7671 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7672 },
7673 { /* AArch64_ST1Fourv2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7674 0,
7675 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7676 },
7677 { /* AArch64_ST1Fourv2s, ARM64_INS_ST1: st1 $vt, [$rn] */
7678 0,
7679 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7680 },
7681 { /* AArch64_ST1Fourv2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7682 0,
7683 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7684 },
7685 { /* AArch64_ST1Fourv4h, ARM64_INS_ST1: st1 $vt, [$rn] */
7686 0,
7687 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7688 },
7689 { /* AArch64_ST1Fourv4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7690 0,
7691 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7692 },
7693 { /* AArch64_ST1Fourv4s, ARM64_INS_ST1: st1 $vt, [$rn] */
7694 0,
7695 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7696 },
7697 { /* AArch64_ST1Fourv4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7698 0,
7699 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7700 },
7701 { /* AArch64_ST1Fourv8b, ARM64_INS_ST1: st1 $vt, [$rn] */
7702 0,
7703 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7704 },
7705 { /* AArch64_ST1Fourv8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7706 0,
7707 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7708 },
7709 { /* AArch64_ST1Fourv8h, ARM64_INS_ST1: st1 $vt, [$rn] */
7710 0,
7711 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7712 },
7713 { /* AArch64_ST1Fourv8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7714 0,
7715 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7716 },
7717 { /* AArch64_ST1Onev16b, ARM64_INS_ST1: st1 $vt, [$rn] */
7718 0,
7719 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7720 },
7721 { /* AArch64_ST1Onev16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7722 0,
7723 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7724 },
7725 { /* AArch64_ST1Onev1d, ARM64_INS_ST1: st1 $vt, [$rn] */
7726 0,
7727 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7728 },
7729 { /* AArch64_ST1Onev1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7730 0,
7731 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7732 },
7733 { /* AArch64_ST1Onev2d, ARM64_INS_ST1: st1 $vt, [$rn] */
7734 0,
7735 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7736 },
7737 { /* AArch64_ST1Onev2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7738 0,
7739 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7740 },
7741 { /* AArch64_ST1Onev2s, ARM64_INS_ST1: st1 $vt, [$rn] */
7742 0,
7743 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7744 },
7745 { /* AArch64_ST1Onev2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7746 0,
7747 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7748 },
7749 { /* AArch64_ST1Onev4h, ARM64_INS_ST1: st1 $vt, [$rn] */
7750 0,
7751 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7752 },
7753 { /* AArch64_ST1Onev4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7754 0,
7755 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7756 },
7757 { /* AArch64_ST1Onev4s, ARM64_INS_ST1: st1 $vt, [$rn] */
7758 0,
7759 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7760 },
7761 { /* AArch64_ST1Onev4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7762 0,
7763 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7764 },
7765 { /* AArch64_ST1Onev8b, ARM64_INS_ST1: st1 $vt, [$rn] */
7766 0,
7767 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7768 },
7769 { /* AArch64_ST1Onev8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7770 0,
7771 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7772 },
7773 { /* AArch64_ST1Onev8h, ARM64_INS_ST1: st1 $vt, [$rn] */
7774 0,
7775 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7776 },
7777 { /* AArch64_ST1Onev8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7778 0,
7779 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7780 },
7781 { /* AArch64_ST1Threev16b, ARM64_INS_ST1: st1 $vt, [$rn] */
7782 0,
7783 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7784 },
7785 { /* AArch64_ST1Threev16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7786 0,
7787 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7788 },
7789 { /* AArch64_ST1Threev1d, ARM64_INS_ST1: st1 $vt, [$rn] */
7790 0,
7791 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7792 },
7793 { /* AArch64_ST1Threev1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7794 0,
7795 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7796 },
7797 { /* AArch64_ST1Threev2d, ARM64_INS_ST1: st1 $vt, [$rn] */
7798 0,
7799 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7800 },
7801 { /* AArch64_ST1Threev2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7802 0,
7803 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7804 },
7805 { /* AArch64_ST1Threev2s, ARM64_INS_ST1: st1 $vt, [$rn] */
7806 0,
7807 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7808 },
7809 { /* AArch64_ST1Threev2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7810 0,
7811 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7812 },
7813 { /* AArch64_ST1Threev4h, ARM64_INS_ST1: st1 $vt, [$rn] */
7814 0,
7815 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7816 },
7817 { /* AArch64_ST1Threev4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7818 0,
7819 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7820 },
7821 { /* AArch64_ST1Threev4s, ARM64_INS_ST1: st1 $vt, [$rn] */
7822 0,
7823 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7824 },
7825 { /* AArch64_ST1Threev4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7826 0,
7827 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7828 },
7829 { /* AArch64_ST1Threev8b, ARM64_INS_ST1: st1 $vt, [$rn] */
7830 0,
7831 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7832 },
7833 { /* AArch64_ST1Threev8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7834 0,
7835 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7836 },
7837 { /* AArch64_ST1Threev8h, ARM64_INS_ST1: st1 $vt, [$rn] */
7838 0,
7839 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7840 },
7841 { /* AArch64_ST1Threev8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7842 0,
7843 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7844 },
7845 { /* AArch64_ST1Twov16b, ARM64_INS_ST1: st1 $vt, [$rn] */
7846 0,
7847 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7848 },
7849 { /* AArch64_ST1Twov16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7850 0,
7851 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7852 },
7853 { /* AArch64_ST1Twov1d, ARM64_INS_ST1: st1 $vt, [$rn] */
7854 0,
7855 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7856 },
7857 { /* AArch64_ST1Twov1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7858 0,
7859 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7860 },
7861 { /* AArch64_ST1Twov2d, ARM64_INS_ST1: st1 $vt, [$rn] */
7862 0,
7863 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7864 },
7865 { /* AArch64_ST1Twov2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7866 0,
7867 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7868 },
7869 { /* AArch64_ST1Twov2s, ARM64_INS_ST1: st1 $vt, [$rn] */
7870 0,
7871 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7872 },
7873 { /* AArch64_ST1Twov2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7874 0,
7875 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7876 },
7877 { /* AArch64_ST1Twov4h, ARM64_INS_ST1: st1 $vt, [$rn] */
7878 0,
7879 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7880 },
7881 { /* AArch64_ST1Twov4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7882 0,
7883 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7884 },
7885 { /* AArch64_ST1Twov4s, ARM64_INS_ST1: st1 $vt, [$rn] */
7886 0,
7887 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7888 },
7889 { /* AArch64_ST1Twov4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7890 0,
7891 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7892 },
7893 { /* AArch64_ST1Twov8b, ARM64_INS_ST1: st1 $vt, [$rn] */
7894 0,
7895 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7896 },
7897 { /* AArch64_ST1Twov8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7898 0,
7899 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7900 },
7901 { /* AArch64_ST1Twov8h, ARM64_INS_ST1: st1 $vt, [$rn] */
7902 0,
7903 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7904 },
7905 { /* AArch64_ST1Twov8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */
7906 0,
7907 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7908 },
7909 { /* AArch64_ST1i16, ARM64_INS_ST1: st1 $vt$idx, [$rn] */
7910 0,
7911 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7912 },
7913 { /* AArch64_ST1i16_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */
7914 0,
7915 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7916 },
7917 { /* AArch64_ST1i32, ARM64_INS_ST1: st1 $vt$idx, [$rn] */
7918 0,
7919 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7920 },
7921 { /* AArch64_ST1i32_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */
7922 0,
7923 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7924 },
7925 { /* AArch64_ST1i64, ARM64_INS_ST1: st1 $vt$idx, [$rn] */
7926 0,
7927 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7928 },
7929 { /* AArch64_ST1i64_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */
7930 0,
7931 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7932 },
7933 { /* AArch64_ST1i8, ARM64_INS_ST1: st1 $vt$idx, [$rn] */
7934 0,
7935 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7936 },
7937 { /* AArch64_ST1i8_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */
7938 0,
7939 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7940 },
7941 { /* AArch64_ST2Twov16b, ARM64_INS_ST2: st2 $vt, [$rn] */
7942 0,
7943 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7944 },
7945 { /* AArch64_ST2Twov16b_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */
7946 0,
7947 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7948 },
7949 { /* AArch64_ST2Twov2d, ARM64_INS_ST2: st2 $vt, [$rn] */
7950 0,
7951 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7952 },
7953 { /* AArch64_ST2Twov2d_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */
7954 0,
7955 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7956 },
7957 { /* AArch64_ST2Twov2s, ARM64_INS_ST2: st2 $vt, [$rn] */
7958 0,
7959 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7960 },
7961 { /* AArch64_ST2Twov2s_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */
7962 0,
7963 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7964 },
7965 { /* AArch64_ST2Twov4h, ARM64_INS_ST2: st2 $vt, [$rn] */
7966 0,
7967 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7968 },
7969 { /* AArch64_ST2Twov4h_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */
7970 0,
7971 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7972 },
7973 { /* AArch64_ST2Twov4s, ARM64_INS_ST2: st2 $vt, [$rn] */
7974 0,
7975 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7976 },
7977 { /* AArch64_ST2Twov4s_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */
7978 0,
7979 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7980 },
7981 { /* AArch64_ST2Twov8b, ARM64_INS_ST2: st2 $vt, [$rn] */
7982 0,
7983 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7984 },
7985 { /* AArch64_ST2Twov8b_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */
7986 0,
7987 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7988 },
7989 { /* AArch64_ST2Twov8h, ARM64_INS_ST2: st2 $vt, [$rn] */
7990 0,
7991 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
7992 },
7993 { /* AArch64_ST2Twov8h_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */
7994 0,
7995 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
7996 },
7997 { /* AArch64_ST2i16, ARM64_INS_ST2: st2 $vt$idx, [$rn] */
7998 0,
7999 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8000 },
8001 { /* AArch64_ST2i16_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */
8002 0,
8003 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8004 },
8005 { /* AArch64_ST2i32, ARM64_INS_ST2: st2 $vt$idx, [$rn] */
8006 0,
8007 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8008 },
8009 { /* AArch64_ST2i32_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */
8010 0,
8011 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8012 },
8013 { /* AArch64_ST2i64, ARM64_INS_ST2: st2 $vt$idx, [$rn] */
8014 0,
8015 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8016 },
8017 { /* AArch64_ST2i64_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */
8018 0,
8019 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8020 },
8021 { /* AArch64_ST2i8, ARM64_INS_ST2: st2 $vt$idx, [$rn] */
8022 0,
8023 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8024 },
8025 { /* AArch64_ST2i8_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */
8026 0,
8027 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8028 },
8029 { /* AArch64_ST3Threev16b, ARM64_INS_ST3: st3 $vt, [$rn] */
8030 0,
8031 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8032 },
8033 { /* AArch64_ST3Threev16b_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */
8034 0,
8035 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8036 },
8037 { /* AArch64_ST3Threev2d, ARM64_INS_ST3: st3 $vt, [$rn] */
8038 0,
8039 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8040 },
8041 { /* AArch64_ST3Threev2d_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */
8042 0,
8043 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8044 },
8045 { /* AArch64_ST3Threev2s, ARM64_INS_ST3: st3 $vt, [$rn] */
8046 0,
8047 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8048 },
8049 { /* AArch64_ST3Threev2s_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */
8050 0,
8051 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8052 },
8053 { /* AArch64_ST3Threev4h, ARM64_INS_ST3: st3 $vt, [$rn] */
8054 0,
8055 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8056 },
8057 { /* AArch64_ST3Threev4h_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */
8058 0,
8059 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8060 },
8061 { /* AArch64_ST3Threev4s, ARM64_INS_ST3: st3 $vt, [$rn] */
8062 0,
8063 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8064 },
8065 { /* AArch64_ST3Threev4s_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */
8066 0,
8067 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8068 },
8069 { /* AArch64_ST3Threev8b, ARM64_INS_ST3: st3 $vt, [$rn] */
8070 0,
8071 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8072 },
8073 { /* AArch64_ST3Threev8b_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */
8074 0,
8075 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8076 },
8077 { /* AArch64_ST3Threev8h, ARM64_INS_ST3: st3 $vt, [$rn] */
8078 0,
8079 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8080 },
8081 { /* AArch64_ST3Threev8h_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */
8082 0,
8083 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8084 },
8085 { /* AArch64_ST3i16, ARM64_INS_ST3: st3 $vt$idx, [$rn] */
8086 0,
8087 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8088 },
8089 { /* AArch64_ST3i16_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */
8090 0,
8091 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8092 },
8093 { /* AArch64_ST3i32, ARM64_INS_ST3: st3 $vt$idx, [$rn] */
8094 0,
8095 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8096 },
8097 { /* AArch64_ST3i32_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */
8098 0,
8099 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8100 },
8101 { /* AArch64_ST3i64, ARM64_INS_ST3: st3 $vt$idx, [$rn] */
8102 0,
8103 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8104 },
8105 { /* AArch64_ST3i64_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */
8106 0,
8107 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8108 },
8109 { /* AArch64_ST3i8, ARM64_INS_ST3: st3 $vt$idx, [$rn] */
8110 0,
8111 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8112 },
8113 { /* AArch64_ST3i8_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */
8114 0,
8115 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8116 },
8117 { /* AArch64_ST4Fourv16b, ARM64_INS_ST4: st4 $vt, [$rn] */
8118 0,
8119 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8120 },
8121 { /* AArch64_ST4Fourv16b_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */
8122 0,
8123 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8124 },
8125 { /* AArch64_ST4Fourv2d, ARM64_INS_ST4: st4 $vt, [$rn] */
8126 0,
8127 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8128 },
8129 { /* AArch64_ST4Fourv2d_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */
8130 0,
8131 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8132 },
8133 { /* AArch64_ST4Fourv2s, ARM64_INS_ST4: st4 $vt, [$rn] */
8134 0,
8135 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8136 },
8137 { /* AArch64_ST4Fourv2s_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */
8138 0,
8139 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8140 },
8141 { /* AArch64_ST4Fourv4h, ARM64_INS_ST4: st4 $vt, [$rn] */
8142 0,
8143 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8144 },
8145 { /* AArch64_ST4Fourv4h_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */
8146 0,
8147 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8148 },
8149 { /* AArch64_ST4Fourv4s, ARM64_INS_ST4: st4 $vt, [$rn] */
8150 0,
8151 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8152 },
8153 { /* AArch64_ST4Fourv4s_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */
8154 0,
8155 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8156 },
8157 { /* AArch64_ST4Fourv8b, ARM64_INS_ST4: st4 $vt, [$rn] */
8158 0,
8159 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8160 },
8161 { /* AArch64_ST4Fourv8b_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */
8162 0,
8163 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8164 },
8165 { /* AArch64_ST4Fourv8h, ARM64_INS_ST4: st4 $vt, [$rn] */
8166 0,
8167 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8168 },
8169 { /* AArch64_ST4Fourv8h_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */
8170 0,
8171 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8172 },
8173 { /* AArch64_ST4i16, ARM64_INS_ST4: st4 $vt$idx, [$rn] */
8174 0,
8175 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8176 },
8177 { /* AArch64_ST4i16_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */
8178 0,
8179 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8180 },
8181 { /* AArch64_ST4i32, ARM64_INS_ST4: st4 $vt$idx, [$rn] */
8182 0,
8183 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8184 },
8185 { /* AArch64_ST4i32_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */
8186 0,
8187 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8188 },
8189 { /* AArch64_ST4i64, ARM64_INS_ST4: st4 $vt$idx, [$rn] */
8190 0,
8191 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8192 },
8193 { /* AArch64_ST4i64_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */
8194 0,
8195 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8196 },
8197 { /* AArch64_ST4i8, ARM64_INS_ST4: st4 $vt$idx, [$rn] */
8198 0,
8199 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8200 },
8201 { /* AArch64_ST4i8_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */
8202 0,
8203 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8204 },
8205 { /* AArch64_STLRB, ARM64_INS_STLRB: stlrb $rt, [$rn] */
8206 0,
8207 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8208 },
8209 { /* AArch64_STLRH, ARM64_INS_STLRH: stlrh $rt, [$rn] */
8210 0,
8211 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8212 },
8213 { /* AArch64_STLRW, ARM64_INS_STLR: stlr $rt, [$rn] */
8214 0,
8215 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8216 },
8217 { /* AArch64_STLRX, ARM64_INS_STLR: stlr $rt, [$rn] */
8218 0,
8219 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8220 },
8221 { /* AArch64_STLXPW, ARM64_INS_STLXP: stlxp $ws, $rt, $rt2, [$rn] */
8222 0,
8223 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8224 },
8225 { /* AArch64_STLXPX, ARM64_INS_STLXP: stlxp $ws, $rt, $rt2, [$rn] */
8226 0,
8227 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8228 },
8229 { /* AArch64_STLXRB, ARM64_INS_STLXRB: stlxrb $ws, $rt, [$rn] */
8230 0,
8231 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8232 },
8233 { /* AArch64_STLXRH, ARM64_INS_STLXRH: stlxrh $ws, $rt, [$rn] */
8234 0,
8235 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8236 },
8237 { /* AArch64_STLXRW, ARM64_INS_STLXR: stlxr $ws, $rt, [$rn] */
8238 0,
8239 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8240 },
8241 { /* AArch64_STLXRX, ARM64_INS_STLXR: stlxr $ws, $rt, [$rn] */
8242 0,
8243 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8244 },
8245 { /* AArch64_STNPDi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */
8246 0,
8247 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8248 },
8249 { /* AArch64_STNPQi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */
8250 0,
8251 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8252 },
8253 { /* AArch64_STNPSi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */
8254 0,
8255 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8256 },
8257 { /* AArch64_STNPWi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */
8258 0,
8259 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8260 },
8261 { /* AArch64_STNPXi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */
8262 0,
8263 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8264 },
8265 { /* AArch64_STPDi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */
8266 0,
8267 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8268 },
8269 { /* AArch64_STPDpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */
8270 0,
8271 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8272 },
8273 { /* AArch64_STPDpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */
8274 0,
8275 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8276 },
8277 { /* AArch64_STPQi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */
8278 0,
8279 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8280 },
8281 { /* AArch64_STPQpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */
8282 0,
8283 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8284 },
8285 { /* AArch64_STPQpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */
8286 0,
8287 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8288 },
8289 { /* AArch64_STPSi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */
8290 0,
8291 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8292 },
8293 { /* AArch64_STPSpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */
8294 0,
8295 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8296 },
8297 { /* AArch64_STPSpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */
8298 0,
8299 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8300 },
8301 { /* AArch64_STPWi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */
8302 0,
8303 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8304 },
8305 { /* AArch64_STPWpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */
8306 0,
8307 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8308 },
8309 { /* AArch64_STPWpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */
8310 0,
8311 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8312 },
8313 { /* AArch64_STPXi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */
8314 0,
8315 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8316 },
8317 { /* AArch64_STPXpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */
8318 0,
8319 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8320 },
8321 { /* AArch64_STPXpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */
8322 0,
8323 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8324 },
8325 { /* AArch64_STRBBpost, ARM64_INS_STRB: strb $rt, [$rn], $offset */
8326 0,
8327 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8328 },
8329 { /* AArch64_STRBBpre, ARM64_INS_STRB: strb $rt, [$rn, $offset]! */
8330 0,
8331 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8332 },
8333 { /* AArch64_STRBBroW, ARM64_INS_STRB: strb $rt, [$rn, $rm, $extend] */
8334 0,
8335 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8336 },
8337 { /* AArch64_STRBBroX, ARM64_INS_STRB: strb $rt, [$rn, $rm, $extend] */
8338 0,
8339 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8340 },
8341 { /* AArch64_STRBBui, ARM64_INS_STRB: strb $rt, [$rn, $offset] */
8342 0,
8343 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8344 },
8345 { /* AArch64_STRBpost, ARM64_INS_STR: str $rt, [$rn], $offset */
8346 0,
8347 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8348 },
8349 { /* AArch64_STRBpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */
8350 0,
8351 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8352 },
8353 { /* AArch64_STRBroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8354 0,
8355 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8356 },
8357 { /* AArch64_STRBroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8358 0,
8359 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8360 },
8361 { /* AArch64_STRBui, ARM64_INS_STR: str $rt, [$rn, $offset] */
8362 0,
8363 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8364 },
8365 { /* AArch64_STRDpost, ARM64_INS_STR: str $rt, [$rn], $offset */
8366 0,
8367 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8368 },
8369 { /* AArch64_STRDpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */
8370 0,
8371 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8372 },
8373 { /* AArch64_STRDroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8374 0,
8375 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8376 },
8377 { /* AArch64_STRDroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8378 0,
8379 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8380 },
8381 { /* AArch64_STRDui, ARM64_INS_STR: str $rt, [$rn, $offset] */
8382 0,
8383 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8384 },
8385 { /* AArch64_STRHHpost, ARM64_INS_STRH: strh $rt, [$rn], $offset */
8386 0,
8387 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8388 },
8389 { /* AArch64_STRHHpre, ARM64_INS_STRH: strh $rt, [$rn, $offset]! */
8390 0,
8391 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8392 },
8393 { /* AArch64_STRHHroW, ARM64_INS_STRH: strh $rt, [$rn, $rm, $extend] */
8394 0,
8395 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8396 },
8397 { /* AArch64_STRHHroX, ARM64_INS_STRH: strh $rt, [$rn, $rm, $extend] */
8398 0,
8399 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8400 },
8401 { /* AArch64_STRHHui, ARM64_INS_STRH: strh $rt, [$rn, $offset] */
8402 0,
8403 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8404 },
8405 { /* AArch64_STRHpost, ARM64_INS_STR: str $rt, [$rn], $offset */
8406 0,
8407 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8408 },
8409 { /* AArch64_STRHpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */
8410 0,
8411 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8412 },
8413 { /* AArch64_STRHroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8414 0,
8415 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8416 },
8417 { /* AArch64_STRHroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8418 0,
8419 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8420 },
8421 { /* AArch64_STRHui, ARM64_INS_STR: str $rt, [$rn, $offset] */
8422 0,
8423 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8424 },
8425 { /* AArch64_STRQpost, ARM64_INS_STR: str $rt, [$rn], $offset */
8426 0,
8427 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8428 },
8429 { /* AArch64_STRQpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */
8430 0,
8431 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8432 },
8433 { /* AArch64_STRQroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8434 0,
8435 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8436 },
8437 { /* AArch64_STRQroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8438 0,
8439 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8440 },
8441 { /* AArch64_STRQui, ARM64_INS_STR: str $rt, [$rn, $offset] */
8442 0,
8443 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8444 },
8445 { /* AArch64_STRSpost, ARM64_INS_STR: str $rt, [$rn], $offset */
8446 0,
8447 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8448 },
8449 { /* AArch64_STRSpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */
8450 0,
8451 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8452 },
8453 { /* AArch64_STRSroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8454 0,
8455 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8456 },
8457 { /* AArch64_STRSroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8458 0,
8459 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8460 },
8461 { /* AArch64_STRSui, ARM64_INS_STR: str $rt, [$rn, $offset] */
8462 0,
8463 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8464 },
8465 { /* AArch64_STRWpost, ARM64_INS_STR: str $rt, [$rn], $offset */
8466 0,
8467 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8468 },
8469 { /* AArch64_STRWpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */
8470 0,
8471 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8472 },
8473 { /* AArch64_STRWroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8474 0,
8475 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8476 },
8477 { /* AArch64_STRWroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8478 0,
8479 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8480 },
8481 { /* AArch64_STRWui, ARM64_INS_STR: str $rt, [$rn, $offset] */
8482 0,
8483 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8484 },
8485 { /* AArch64_STRXpost, ARM64_INS_STR: str $rt, [$rn], $offset */
8486 0,
8487 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8488 },
8489 { /* AArch64_STRXpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */
8490 0,
8491 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8492 },
8493 { /* AArch64_STRXroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8494 0,
8495 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8496 },
8497 { /* AArch64_STRXroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */
8498 0,
8499 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8500 },
8501 { /* AArch64_STRXui, ARM64_INS_STR: str $rt, [$rn, $offset] */
8502 0,
8503 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8504 },
8505 { /* AArch64_STTRBi, ARM64_INS_STTRB: sttrb $rt, [$rn, $offset] */
8506 0,
8507 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8508 },
8509 { /* AArch64_STTRHi, ARM64_INS_STTRH: sttrh $rt, [$rn, $offset] */
8510 0,
8511 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8512 },
8513 { /* AArch64_STTRWi, ARM64_INS_STTR: sttr $rt, [$rn, $offset] */
8514 0,
8515 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8516 },
8517 { /* AArch64_STTRXi, ARM64_INS_STTR: sttr $rt, [$rn, $offset] */
8518 0,
8519 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8520 },
8521 { /* AArch64_STURBBi, ARM64_INS_STURB: sturb $rt, [$rn, $offset] */
8522 0,
8523 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8524 },
8525 { /* AArch64_STURBi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */
8526 0,
8527 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8528 },
8529 { /* AArch64_STURDi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */
8530 0,
8531 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8532 },
8533 { /* AArch64_STURHHi, ARM64_INS_STURH: sturh $rt, [$rn, $offset] */
8534 0,
8535 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8536 },
8537 { /* AArch64_STURHi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */
8538 0,
8539 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8540 },
8541 { /* AArch64_STURQi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */
8542 0,
8543 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8544 },
8545 { /* AArch64_STURSi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */
8546 0,
8547 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8548 },
8549 { /* AArch64_STURWi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */
8550 0,
8551 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8552 },
8553 { /* AArch64_STURXi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */
8554 0,
8555 { CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8556 },
8557 { /* AArch64_STXPW, ARM64_INS_STXP: stxp $ws, $rt, $rt2, [$rn] */
8558 0,
8559 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8560 },
8561 { /* AArch64_STXPX, ARM64_INS_STXP: stxp $ws, $rt, $rt2, [$rn] */
8562 0,
8563 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8564 },
8565 { /* AArch64_STXRB, ARM64_INS_STXRB: stxrb $ws, $rt, [$rn] */
8566 0,
8567 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8568 },
8569 { /* AArch64_STXRH, ARM64_INS_STXRH: stxrh $ws, $rt, [$rn] */
8570 0,
8571 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8572 },
8573 { /* AArch64_STXRW, ARM64_INS_STXR: stxr $ws, $rt, [$rn] */
8574 0,
8575 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8576 },
8577 { /* AArch64_STXRX, ARM64_INS_STXR: stxr $ws, $rt, [$rn] */
8578 0,
8579 { CS_OP_WRITE, CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8580 },
8581 { /* AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN: subhn.2s $rd, $rn, $rm */
8582 0,
8583 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8584 },
8585 { /* AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2: subhn2.4s $rd, $rn, $rm */
8586 0,
8587 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8588 },
8589 { /* AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN: subhn.4h $rd, $rn, $rm */
8590 0,
8591 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8592 },
8593 { /* AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2: subhn2.8h $rd, $rn, $rm */
8594 0,
8595 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8596 },
8597 { /* AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2: subhn2.16b $rd, $rn, $rm */
8598 0,
8599 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8600 },
8601 { /* AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN: subhn.8b $rd, $rn, $rm */
8602 0,
8603 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8604 },
8605 { /* AArch64_SUBSWri, ARM64_INS_SUBS: subs $rd, $rn, $imm */
8606 0,
8607 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8608 },
8609 { /* AArch64_SUBSWrs, ARM64_INS_SUBS: subs $rd, $rn, $rm */
8610 0,
8611 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8612 },
8613 { /* AArch64_SUBSWrx, ARM64_INS_SUBS: subs $r1, $r2, $r3 */
8614 0,
8615 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8616 },
8617 { /* AArch64_SUBSXri, ARM64_INS_SUBS: subs $rd, $rn, $imm */
8618 0,
8619 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8620 },
8621 { /* AArch64_SUBSXrs, ARM64_INS_SUBS: subs $rd, $rn, $rm */
8622 0,
8623 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8624 },
8625 { /* AArch64_SUBSXrx, ARM64_INS_SUBS: subs $r1, $r2, $r3 */
8626 0,
8627 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8628 },
8629 { /* AArch64_SUBSXrx64, ARM64_INS_SUBS: subs $rd, $rn, $rm$ext */
8630 0,
8631 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8632 },
8633 { /* AArch64_SUBWri, ARM64_INS_SUB: sub $rd, $rn, $imm */
8634 0,
8635 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8636 },
8637 { /* AArch64_SUBWrs, ARM64_INS_SUB: sub $rd, $rn, $rm */
8638 0,
8639 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8640 },
8641 { /* AArch64_SUBWrx, ARM64_INS_SUB: sub $r1, $r2, $r3 */
8642 0,
8643 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8644 },
8645 { /* AArch64_SUBXri, ARM64_INS_SUB: sub $rd, $rn, $imm */
8646 0,
8647 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8648 },
8649 { /* AArch64_SUBXrs, ARM64_INS_SUB: sub $rd, $rn, $rm */
8650 0,
8651 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8652 },
8653 { /* AArch64_SUBXrx, ARM64_INS_SUB: sub $r1, $r2, $r3 */
8654 0,
8655 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8656 },
8657 { /* AArch64_SUBXrx64, ARM64_INS_SUB: sub $rd, $rn, $rm$ext */
8658 0,
8659 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8660 },
8661 { /* AArch64_SUBv16i8, ARM64_INS_SUB: sub.16b $rd, $rn, $rm| */
8662 0,
8663 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8664 },
8665 { /* AArch64_SUBv1i64, ARM64_INS_SUB: sub $rd, $rn, $rm */
8666 0,
8667 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8668 },
8669 { /* AArch64_SUBv2i32, ARM64_INS_SUB: sub.2s $rd, $rn, $rm| */
8670 0,
8671 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8672 },
8673 { /* AArch64_SUBv2i64, ARM64_INS_SUB: sub.2d $rd, $rn, $rm| */
8674 0,
8675 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8676 },
8677 { /* AArch64_SUBv4i16, ARM64_INS_SUB: sub.4h $rd, $rn, $rm| */
8678 0,
8679 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8680 },
8681 { /* AArch64_SUBv4i32, ARM64_INS_SUB: sub.4s $rd, $rn, $rm| */
8682 0,
8683 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8684 },
8685 { /* AArch64_SUBv8i16, ARM64_INS_SUB: sub.8h $rd, $rn, $rm| */
8686 0,
8687 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8688 },
8689 { /* AArch64_SUBv8i8, ARM64_INS_SUB: sub.8b $rd, $rn, $rm| */
8690 0,
8691 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8692 },
8693 { /* AArch64_SUQADDv16i8, ARM64_INS_SUQADD: suqadd.16b $rd, $rn */
8694 0,
8695 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8696 },
8697 { /* AArch64_SUQADDv1i16, ARM64_INS_SUQADD: suqadd $rd, $rn */
8698 0,
8699 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8700 },
8701 { /* AArch64_SUQADDv1i32, ARM64_INS_SUQADD: suqadd $rd, $rn */
8702 0,
8703 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8704 },
8705 { /* AArch64_SUQADDv1i64, ARM64_INS_SUQADD: suqadd $rd, $rn */
8706 0,
8707 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8708 },
8709 { /* AArch64_SUQADDv1i8, ARM64_INS_SUQADD: suqadd $rd, $rn */
8710 0,
8711 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8712 },
8713 { /* AArch64_SUQADDv2i32, ARM64_INS_SUQADD: suqadd.2s $rd, $rn */
8714 0,
8715 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8716 },
8717 { /* AArch64_SUQADDv2i64, ARM64_INS_SUQADD: suqadd.2d $rd, $rn */
8718 0,
8719 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8720 },
8721 { /* AArch64_SUQADDv4i16, ARM64_INS_SUQADD: suqadd.4h $rd, $rn */
8722 0,
8723 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8724 },
8725 { /* AArch64_SUQADDv4i32, ARM64_INS_SUQADD: suqadd.4s $rd, $rn */
8726 0,
8727 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8728 },
8729 { /* AArch64_SUQADDv8i16, ARM64_INS_SUQADD: suqadd.8h $rd, $rn */
8730 0,
8731 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8732 },
8733 { /* AArch64_SUQADDv8i8, ARM64_INS_SUQADD: suqadd.8b $rd, $rn */
8734 0,
8735 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8736 },
8737 { /* AArch64_SVC, ARM64_INS_SVC: svc $imm */
8738 0,
8739 { CS_OP_READ, 0 }
8740 },
8741 { /* AArch64_SYSLxt, ARM64_INS_SYSL: sysl $rt, $op1, $cn, $cm, $op2 */
8742 0,
8743 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8744 },
8745 { /* AArch64_SYSxt, ARM64_INS_SYS: sys $op1, $cn, $cm, $op2, $rt */
8746 0,
8747 { CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_WRITE | CS_OP_READ, 0 }
8748 },
8749 { /* AArch64_TBLv16i8Four, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */
8750 0,
8751 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8752 },
8753 { /* AArch64_TBLv16i8One, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */
8754 0,
8755 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8756 },
8757 { /* AArch64_TBLv16i8Three, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */
8758 0,
8759 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8760 },
8761 { /* AArch64_TBLv16i8Two, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */
8762 0,
8763 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8764 },
8765 { /* AArch64_TBLv8i8Four, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */
8766 0,
8767 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8768 },
8769 { /* AArch64_TBLv8i8One, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */
8770 0,
8771 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8772 },
8773 { /* AArch64_TBLv8i8Three, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */
8774 0,
8775 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8776 },
8777 { /* AArch64_TBLv8i8Two, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */
8778 0,
8779 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8780 },
8781 { /* AArch64_TBNZW, ARM64_INS_TBNZ: tbnz $rt, $bit_off, $target */
8782 0,
8783 { CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8784 },
8785 { /* AArch64_TBNZX, ARM64_INS_TBNZ: tbnz $rt, $bit_off, $target */
8786 0,
8787 { CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8788 },
8789 { /* AArch64_TBXv16i8Four, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */
8790 0,
8791 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8792 },
8793 { /* AArch64_TBXv16i8One, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */
8794 0,
8795 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8796 },
8797 { /* AArch64_TBXv16i8Three, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */
8798 0,
8799 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8800 },
8801 { /* AArch64_TBXv16i8Two, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */
8802 0,
8803 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8804 },
8805 { /* AArch64_TBXv8i8Four, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */
8806 0,
8807 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8808 },
8809 { /* AArch64_TBXv8i8One, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */
8810 0,
8811 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8812 },
8813 { /* AArch64_TBXv8i8Three, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */
8814 0,
8815 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8816 },
8817 { /* AArch64_TBXv8i8Two, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */
8818 0,
8819 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8820 },
8821 { /* AArch64_TBZW, ARM64_INS_TBZ: tbz $rt, $bit_off, $target */
8822 0,
8823 { CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8824 },
8825 { /* AArch64_TBZX, ARM64_INS_TBZ: tbz $rt, $bit_off, $target */
8826 0,
8827 { CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8828 },
8829 { /* AArch64_TRN1v16i8, ARM64_INS_TRN1: trn1.16b $rd, $rn, $rm */
8830 0,
8831 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8832 },
8833 { /* AArch64_TRN1v2i32, ARM64_INS_TRN1: trn1.2s $rd, $rn, $rm */
8834 0,
8835 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8836 },
8837 { /* AArch64_TRN1v2i64, ARM64_INS_TRN1: trn1.2d $rd, $rn, $rm */
8838 0,
8839 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8840 },
8841 { /* AArch64_TRN1v4i16, ARM64_INS_TRN1: trn1.4h $rd, $rn, $rm */
8842 0,
8843 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8844 },
8845 { /* AArch64_TRN1v4i32, ARM64_INS_TRN1: trn1.4s $rd, $rn, $rm */
8846 0,
8847 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8848 },
8849 { /* AArch64_TRN1v8i16, ARM64_INS_TRN1: trn1.8h $rd, $rn, $rm */
8850 0,
8851 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8852 },
8853 { /* AArch64_TRN1v8i8, ARM64_INS_TRN1: trn1.8b $rd, $rn, $rm */
8854 0,
8855 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8856 },
8857 { /* AArch64_TRN2v16i8, ARM64_INS_TRN2: trn2.16b $rd, $rn, $rm */
8858 0,
8859 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8860 },
8861 { /* AArch64_TRN2v2i32, ARM64_INS_TRN2: trn2.2s $rd, $rn, $rm */
8862 0,
8863 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8864 },
8865 { /* AArch64_TRN2v2i64, ARM64_INS_TRN2: trn2.2d $rd, $rn, $rm */
8866 0,
8867 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8868 },
8869 { /* AArch64_TRN2v4i16, ARM64_INS_TRN2: trn2.4h $rd, $rn, $rm */
8870 0,
8871 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8872 },
8873 { /* AArch64_TRN2v4i32, ARM64_INS_TRN2: trn2.4s $rd, $rn, $rm */
8874 0,
8875 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8876 },
8877 { /* AArch64_TRN2v8i16, ARM64_INS_TRN2: trn2.8h $rd, $rn, $rm */
8878 0,
8879 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8880 },
8881 { /* AArch64_TRN2v8i8, ARM64_INS_TRN2: trn2.8b $rd, $rn, $rm */
8882 0,
8883 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
8884 },
8885 { /* AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2: uabal2.8h $rd, $rn, $rm */
8886 0,
8887 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8888 },
8889 { /* AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL: uabal.2d $rd, $rn, $rm */
8890 0,
8891 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8892 },
8893 { /* AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL: uabal.4s $rd, $rn, $rm */
8894 0,
8895 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8896 },
8897 { /* AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2: uabal2.2d $rd, $rn, $rm */
8898 0,
8899 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8900 },
8901 { /* AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2: uabal2.4s $rd, $rn, $rm */
8902 0,
8903 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8904 },
8905 { /* AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL: uabal.8h $rd, $rn, $rm */
8906 0,
8907 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8908 },
8909 { /* AArch64_UABAv16i8, ARM64_INS_UABA: uaba.16b $rd, $rn, $rm */
8910 0,
8911 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8912 },
8913 { /* AArch64_UABAv2i32, ARM64_INS_UABA: uaba.2s $rd, $rn, $rm */
8914 0,
8915 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8916 },
8917 { /* AArch64_UABAv4i16, ARM64_INS_UABA: uaba.4h $rd, $rn, $rm */
8918 0,
8919 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8920 },
8921 { /* AArch64_UABAv4i32, ARM64_INS_UABA: uaba.4s $rd, $rn, $rm */
8922 0,
8923 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8924 },
8925 { /* AArch64_UABAv8i16, ARM64_INS_UABA: uaba.8h $rd, $rn, $rm */
8926 0,
8927 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8928 },
8929 { /* AArch64_UABAv8i8, ARM64_INS_UABA: uaba.8b $rd, $rn, $rm */
8930 0,
8931 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8932 },
8933 { /* AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2: uabdl2.8h $rd, $rn, $rm */
8934 0,
8935 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8936 },
8937 { /* AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL: uabdl.2d $rd, $rn, $rm */
8938 0,
8939 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8940 },
8941 { /* AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL: uabdl.4s $rd, $rn, $rm */
8942 0,
8943 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8944 },
8945 { /* AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2: uabdl2.2d $rd, $rn, $rm */
8946 0,
8947 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8948 },
8949 { /* AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2: uabdl2.4s $rd, $rn, $rm */
8950 0,
8951 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8952 },
8953 { /* AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL: uabdl.8h $rd, $rn, $rm */
8954 0,
8955 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8956 },
8957 { /* AArch64_UABDv16i8, ARM64_INS_UABD: uabd.16b $rd, $rn, $rm| */
8958 0,
8959 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8960 },
8961 { /* AArch64_UABDv2i32, ARM64_INS_UABD: uabd.2s $rd, $rn, $rm| */
8962 0,
8963 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8964 },
8965 { /* AArch64_UABDv4i16, ARM64_INS_UABD: uabd.4h $rd, $rn, $rm| */
8966 0,
8967 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8968 },
8969 { /* AArch64_UABDv4i32, ARM64_INS_UABD: uabd.4s $rd, $rn, $rm| */
8970 0,
8971 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8972 },
8973 { /* AArch64_UABDv8i16, ARM64_INS_UABD: uabd.8h $rd, $rn, $rm| */
8974 0,
8975 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8976 },
8977 { /* AArch64_UABDv8i8, ARM64_INS_UABD: uabd.8b $rd, $rn, $rm| */
8978 0,
8979 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
8980 },
8981 { /* AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP: uadalp.8h $rd, $rn */
8982 0,
8983 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8984 },
8985 { /* AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP: uadalp.1d $rd, $rn */
8986 0,
8987 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8988 },
8989 { /* AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP: uadalp.2s $rd, $rn */
8990 0,
8991 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8992 },
8993 { /* AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP: uadalp.2d $rd, $rn */
8994 0,
8995 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
8996 },
8997 { /* AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP: uadalp.4s $rd, $rn */
8998 0,
8999 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
9000 },
9001 { /* AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP: uadalp.4h $rd, $rn */
9002 0,
9003 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
9004 },
9005 { /* AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP: uaddlp.8h $rd, $rn */
9006 0,
9007 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
9008 },
9009 { /* AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP: uaddlp.1d $rd, $rn */
9010 0,
9011 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
9012 },
9013 { /* AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP: uaddlp.2s $rd, $rn */
9014 0,
9015 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
9016 },
9017 { /* AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP: uaddlp.2d $rd, $rn */
9018 0,
9019 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
9020 },
9021 { /* AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP: uaddlp.4s $rd, $rn */
9022 0,
9023 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
9024 },
9025 { /* AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP: uaddlp.4h $rd, $rn */
9026 0,
9027 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
9028 },
9029 { /* AArch64_UADDLVv16i8v, ARM64_INS_UADDLV: uaddlv.16b $rd, $rn */
9030 0,
9031 { CS_OP_WRITE, CS_OP_READ, 0 }
9032 },
9033 { /* AArch64_UADDLVv4i16v, ARM64_INS_UADDLV: uaddlv.4h $rd, $rn */
9034 0,
9035 { CS_OP_WRITE, CS_OP_READ, 0 }
9036 },
9037 { /* AArch64_UADDLVv4i32v, ARM64_INS_UADDLV: uaddlv.4s $rd, $rn */
9038 0,
9039 { CS_OP_WRITE, CS_OP_READ, 0 }
9040 },
9041 { /* AArch64_UADDLVv8i16v, ARM64_INS_UADDLV: uaddlv.8h $rd, $rn */
9042 0,
9043 { CS_OP_WRITE, CS_OP_READ, 0 }
9044 },
9045 { /* AArch64_UADDLVv8i8v, ARM64_INS_UADDLV: uaddlv.8b $rd, $rn */
9046 0,
9047 { CS_OP_WRITE, CS_OP_READ, 0 }
9048 },
9049 { /* AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2: uaddl2.8h $rd, $rn, $rm */
9050 0,
9051 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9052 },
9053 { /* AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL: uaddl.2d $rd, $rn, $rm */
9054 0,
9055 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9056 },
9057 { /* AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL: uaddl.4s $rd, $rn, $rm */
9058 0,
9059 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9060 },
9061 { /* AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2: uaddl2.2d $rd, $rn, $rm */
9062 0,
9063 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9064 },
9065 { /* AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2: uaddl2.4s $rd, $rn, $rm */
9066 0,
9067 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9068 },
9069 { /* AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL: uaddl.8h $rd, $rn, $rm */
9070 0,
9071 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9072 },
9073 { /* AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2: uaddw2.8h $rd, $rn, $rm */
9074 0,
9075 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9076 },
9077 { /* AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW: uaddw.2d $rd, $rn, $rm */
9078 0,
9079 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9080 },
9081 { /* AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW: uaddw.4s $rd, $rn, $rm */
9082 0,
9083 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9084 },
9085 { /* AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2: uaddw2.2d $rd, $rn, $rm */
9086 0,
9087 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9088 },
9089 { /* AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2: uaddw2.4s $rd, $rn, $rm */
9090 0,
9091 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9092 },
9093 { /* AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW: uaddw.8h $rd, $rn, $rm */
9094 0,
9095 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9096 },
9097 { /* AArch64_UBFMWri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */
9098 0,
9099 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9100 },
9101 { /* AArch64_UBFMXri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */
9102 0,
9103 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9104 },
9105 { /* AArch64_UCVTFSWDri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */
9106 0,
9107 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9108 },
9109 { /* AArch64_UCVTFSWSri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */
9110 0,
9111 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9112 },
9113 { /* AArch64_UCVTFSXDri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */
9114 0,
9115 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9116 },
9117 { /* AArch64_UCVTFSXSri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */
9118 0,
9119 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9120 },
9121 { /* AArch64_UCVTFUWDri, ARM64_INS_UCVTF: ucvtf $rd, $rn */
9122 0,
9123 { CS_OP_WRITE, CS_OP_READ, 0 }
9124 },
9125 { /* AArch64_UCVTFUWSri, ARM64_INS_UCVTF: ucvtf $rd, $rn */
9126 0,
9127 { CS_OP_WRITE, CS_OP_READ, 0 }
9128 },
9129 { /* AArch64_UCVTFUXDri, ARM64_INS_UCVTF: ucvtf $rd, $rn */
9130 0,
9131 { CS_OP_WRITE, CS_OP_READ, 0 }
9132 },
9133 { /* AArch64_UCVTFUXSri, ARM64_INS_UCVTF: ucvtf $rd, $rn */
9134 0,
9135 { CS_OP_WRITE, CS_OP_READ, 0 }
9136 },
9137 { /* AArch64_UCVTFd, ARM64_INS_UCVTF: ucvtf $rd, $rn, $imm */
9138 0,
9139 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9140 },
9141 { /* AArch64_UCVTFs, ARM64_INS_UCVTF: ucvtf $rd, $rn, $imm */
9142 0,
9143 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9144 },
9145 { /* AArch64_UCVTFv1i32, ARM64_INS_UCVTF: ucvtf $rd, $rn */
9146 0,
9147 { CS_OP_WRITE, CS_OP_READ, 0 }
9148 },
9149 { /* AArch64_UCVTFv1i64, ARM64_INS_UCVTF: ucvtf $rd, $rn */
9150 0,
9151 { CS_OP_WRITE, CS_OP_READ, 0 }
9152 },
9153 { /* AArch64_UCVTFv2f32, ARM64_INS_UCVTF: ucvtf.2s $rd, $rn */
9154 0,
9155 { CS_OP_WRITE, CS_OP_READ, 0 }
9156 },
9157 { /* AArch64_UCVTFv2f64, ARM64_INS_UCVTF: ucvtf.2d $rd, $rn */
9158 0,
9159 { CS_OP_WRITE, CS_OP_READ, 0 }
9160 },
9161 { /* AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF: ucvtf.2s $rd, $rn, $imm */
9162 0,
9163 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9164 },
9165 { /* AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF: ucvtf.2d $rd, $rn, $imm */
9166 0,
9167 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9168 },
9169 { /* AArch64_UCVTFv4f32, ARM64_INS_UCVTF: ucvtf.4s $rd, $rn */
9170 0,
9171 { CS_OP_WRITE, CS_OP_READ, 0 }
9172 },
9173 { /* AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF: ucvtf.4s $rd, $rn, $imm */
9174 0,
9175 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9176 },
9177 { /* AArch64_UDIVWr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */
9178 0,
9179 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9180 },
9181 { /* AArch64_UDIVXr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */
9182 0,
9183 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9184 },
9185 { /* AArch64_UDIV_IntWr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */
9186 0,
9187 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9188 },
9189 { /* AArch64_UDIV_IntXr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */
9190 0,
9191 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9192 },
9193 { /* AArch64_UHADDv16i8, ARM64_INS_UHADD: uhadd.16b $rd, $rn, $rm| */
9194 0,
9195 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9196 },
9197 { /* AArch64_UHADDv2i32, ARM64_INS_UHADD: uhadd.2s $rd, $rn, $rm| */
9198 0,
9199 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9200 },
9201 { /* AArch64_UHADDv4i16, ARM64_INS_UHADD: uhadd.4h $rd, $rn, $rm| */
9202 0,
9203 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9204 },
9205 { /* AArch64_UHADDv4i32, ARM64_INS_UHADD: uhadd.4s $rd, $rn, $rm| */
9206 0,
9207 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9208 },
9209 { /* AArch64_UHADDv8i16, ARM64_INS_UHADD: uhadd.8h $rd, $rn, $rm| */
9210 0,
9211 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9212 },
9213 { /* AArch64_UHADDv8i8, ARM64_INS_UHADD: uhadd.8b $rd, $rn, $rm| */
9214 0,
9215 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9216 },
9217 { /* AArch64_UHSUBv16i8, ARM64_INS_UHSUB: uhsub.16b $rd, $rn, $rm| */
9218 0,
9219 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9220 },
9221 { /* AArch64_UHSUBv2i32, ARM64_INS_UHSUB: uhsub.2s $rd, $rn, $rm| */
9222 0,
9223 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9224 },
9225 { /* AArch64_UHSUBv4i16, ARM64_INS_UHSUB: uhsub.4h $rd, $rn, $rm| */
9226 0,
9227 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9228 },
9229 { /* AArch64_UHSUBv4i32, ARM64_INS_UHSUB: uhsub.4s $rd, $rn, $rm| */
9230 0,
9231 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9232 },
9233 { /* AArch64_UHSUBv8i16, ARM64_INS_UHSUB: uhsub.8h $rd, $rn, $rm| */
9234 0,
9235 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9236 },
9237 { /* AArch64_UHSUBv8i8, ARM64_INS_UHSUB: uhsub.8b $rd, $rn, $rm| */
9238 0,
9239 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9240 },
9241 { /* AArch64_UMADDLrrr, ARM64_INS_UMADDL: umaddl $rd, $rn, $rm, $ra */
9242 0,
9243 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9244 },
9245 { /* AArch64_UMAXPv16i8, ARM64_INS_UMAXP: umaxp.16b $rd, $rn, $rm| */
9246 0,
9247 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9248 },
9249 { /* AArch64_UMAXPv2i32, ARM64_INS_UMAXP: umaxp.2s $rd, $rn, $rm| */
9250 0,
9251 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9252 },
9253 { /* AArch64_UMAXPv4i16, ARM64_INS_UMAXP: umaxp.4h $rd, $rn, $rm| */
9254 0,
9255 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9256 },
9257 { /* AArch64_UMAXPv4i32, ARM64_INS_UMAXP: umaxp.4s $rd, $rn, $rm| */
9258 0,
9259 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9260 },
9261 { /* AArch64_UMAXPv8i16, ARM64_INS_UMAXP: umaxp.8h $rd, $rn, $rm| */
9262 0,
9263 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9264 },
9265 { /* AArch64_UMAXPv8i8, ARM64_INS_UMAXP: umaxp.8b $rd, $rn, $rm| */
9266 0,
9267 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9268 },
9269 { /* AArch64_UMAXVv16i8v, ARM64_INS_UMAXV: umaxv.16b $rd, $rn */
9270 0,
9271 { CS_OP_WRITE, CS_OP_READ, 0 }
9272 },
9273 { /* AArch64_UMAXVv4i16v, ARM64_INS_UMAXV: umaxv.4h $rd, $rn */
9274 0,
9275 { CS_OP_WRITE, CS_OP_READ, 0 }
9276 },
9277 { /* AArch64_UMAXVv4i32v, ARM64_INS_UMAXV: umaxv.4s $rd, $rn */
9278 0,
9279 { CS_OP_WRITE, CS_OP_READ, 0 }
9280 },
9281 { /* AArch64_UMAXVv8i16v, ARM64_INS_UMAXV: umaxv.8h $rd, $rn */
9282 0,
9283 { CS_OP_WRITE, CS_OP_READ, 0 }
9284 },
9285 { /* AArch64_UMAXVv8i8v, ARM64_INS_UMAXV: umaxv.8b $rd, $rn */
9286 0,
9287 { CS_OP_WRITE, CS_OP_READ, 0 }
9288 },
9289 { /* AArch64_UMAXv16i8, ARM64_INS_UMAX: umax.16b $rd, $rn, $rm| */
9290 0,
9291 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9292 },
9293 { /* AArch64_UMAXv2i32, ARM64_INS_UMAX: umax.2s $rd, $rn, $rm| */
9294 0,
9295 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9296 },
9297 { /* AArch64_UMAXv4i16, ARM64_INS_UMAX: umax.4h $rd, $rn, $rm| */
9298 0,
9299 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9300 },
9301 { /* AArch64_UMAXv4i32, ARM64_INS_UMAX: umax.4s $rd, $rn, $rm| */
9302 0,
9303 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9304 },
9305 { /* AArch64_UMAXv8i16, ARM64_INS_UMAX: umax.8h $rd, $rn, $rm| */
9306 0,
9307 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9308 },
9309 { /* AArch64_UMAXv8i8, ARM64_INS_UMAX: umax.8b $rd, $rn, $rm| */
9310 0,
9311 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9312 },
9313 { /* AArch64_UMINPv16i8, ARM64_INS_UMINP: uminp.16b $rd, $rn, $rm| */
9314 0,
9315 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9316 },
9317 { /* AArch64_UMINPv2i32, ARM64_INS_UMINP: uminp.2s $rd, $rn, $rm| */
9318 0,
9319 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9320 },
9321 { /* AArch64_UMINPv4i16, ARM64_INS_UMINP: uminp.4h $rd, $rn, $rm| */
9322 0,
9323 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9324 },
9325 { /* AArch64_UMINPv4i32, ARM64_INS_UMINP: uminp.4s $rd, $rn, $rm| */
9326 0,
9327 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9328 },
9329 { /* AArch64_UMINPv8i16, ARM64_INS_UMINP: uminp.8h $rd, $rn, $rm| */
9330 0,
9331 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9332 },
9333 { /* AArch64_UMINPv8i8, ARM64_INS_UMINP: uminp.8b $rd, $rn, $rm| */
9334 0,
9335 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9336 },
9337 { /* AArch64_UMINVv16i8v, ARM64_INS_UMINV: uminv.16b $rd, $rn */
9338 0,
9339 { CS_OP_WRITE, CS_OP_READ, 0 }
9340 },
9341 { /* AArch64_UMINVv4i16v, ARM64_INS_UMINV: uminv.4h $rd, $rn */
9342 0,
9343 { CS_OP_WRITE, CS_OP_READ, 0 }
9344 },
9345 { /* AArch64_UMINVv4i32v, ARM64_INS_UMINV: uminv.4s $rd, $rn */
9346 0,
9347 { CS_OP_WRITE, CS_OP_READ, 0 }
9348 },
9349 { /* AArch64_UMINVv8i16v, ARM64_INS_UMINV: uminv.8h $rd, $rn */
9350 0,
9351 { CS_OP_WRITE, CS_OP_READ, 0 }
9352 },
9353 { /* AArch64_UMINVv8i8v, ARM64_INS_UMINV: uminv.8b $rd, $rn */
9354 0,
9355 { CS_OP_WRITE, CS_OP_READ, 0 }
9356 },
9357 { /* AArch64_UMINv16i8, ARM64_INS_UMIN: umin.16b $rd, $rn, $rm| */
9358 0,
9359 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9360 },
9361 { /* AArch64_UMINv2i32, ARM64_INS_UMIN: umin.2s $rd, $rn, $rm| */
9362 0,
9363 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9364 },
9365 { /* AArch64_UMINv4i16, ARM64_INS_UMIN: umin.4h $rd, $rn, $rm| */
9366 0,
9367 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9368 },
9369 { /* AArch64_UMINv4i32, ARM64_INS_UMIN: umin.4s $rd, $rn, $rm| */
9370 0,
9371 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9372 },
9373 { /* AArch64_UMINv8i16, ARM64_INS_UMIN: umin.8h $rd, $rn, $rm| */
9374 0,
9375 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9376 },
9377 { /* AArch64_UMINv8i8, ARM64_INS_UMIN: umin.8b $rd, $rn, $rm| */
9378 0,
9379 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9380 },
9381 { /* AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2: umlal2.8h $rd, $rn, $rm */
9382 0,
9383 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9384 },
9385 { /* AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL: umlal.2d $rd, $rn, $rm$idx */
9386 0,
9387 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9388 },
9389 { /* AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL: umlal.2d $rd, $rn, $rm */
9390 0,
9391 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9392 },
9393 { /* AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL: umlal.4s $rd, $rn, $rm$idx */
9394 0,
9395 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9396 },
9397 { /* AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL: umlal.4s $rd, $rn, $rm */
9398 0,
9399 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9400 },
9401 { /* AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2: umlal2.2d $rd, $rn, $rm$idx */
9402 0,
9403 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9404 },
9405 { /* AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2: umlal2.2d $rd, $rn, $rm */
9406 0,
9407 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9408 },
9409 { /* AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2: umlal2.4s $rd, $rn, $rm$idx */
9410 0,
9411 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9412 },
9413 { /* AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2: umlal2.4s $rd, $rn, $rm */
9414 0,
9415 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9416 },
9417 { /* AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL: umlal.8h $rd, $rn, $rm */
9418 0,
9419 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9420 },
9421 { /* AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2: umlsl2.8h $rd, $rn, $rm */
9422 0,
9423 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9424 },
9425 { /* AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL: umlsl.2d $rd, $rn, $rm$idx */
9426 0,
9427 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9428 },
9429 { /* AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL: umlsl.2d $rd, $rn, $rm */
9430 0,
9431 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9432 },
9433 { /* AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL: umlsl.4s $rd, $rn, $rm$idx */
9434 0,
9435 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9436 },
9437 { /* AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL: umlsl.4s $rd, $rn, $rm */
9438 0,
9439 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9440 },
9441 { /* AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2: umlsl2.2d $rd, $rn, $rm$idx */
9442 0,
9443 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9444 },
9445 { /* AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2: umlsl2.2d $rd, $rn, $rm */
9446 0,
9447 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9448 },
9449 { /* AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2: umlsl2.4s $rd, $rn, $rm$idx */
9450 0,
9451 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9452 },
9453 { /* AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2: umlsl2.4s $rd, $rn, $rm */
9454 0,
9455 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9456 },
9457 { /* AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL: umlsl.8h $rd, $rn, $rm */
9458 0,
9459 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9460 },
9461 { /* AArch64_UMOVvi16, ARM64_INS_UMOV: umov.h $rd, $rn$idx */
9462 0,
9463 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9464 },
9465 { /* AArch64_UMOVvi32, ARM64_INS_UMOV: umov.s $rd, $rn$idx */
9466 0,
9467 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9468 },
9469 { /* AArch64_UMOVvi64, ARM64_INS_UMOV: umov.d $rd, $rn$idx */
9470 0,
9471 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9472 },
9473 { /* AArch64_UMOVvi8, ARM64_INS_UMOV: umov.b $rd, $rn$idx */
9474 0,
9475 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9476 },
9477 { /* AArch64_UMSUBLrrr, ARM64_INS_UMSUBL: umsubl $rd, $rn, $rm, $ra */
9478 0,
9479 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9480 },
9481 { /* AArch64_UMULHrr, ARM64_INS_UMULH: umulh $rd, $rn, $rm */
9482 0,
9483 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9484 },
9485 { /* AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2: umull2.8h $rd, $rn, $rm */
9486 0,
9487 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9488 },
9489 { /* AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL: umull.2d $rd, $rn, $rm$idx */
9490 0,
9491 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9492 },
9493 { /* AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL: umull.2d $rd, $rn, $rm */
9494 0,
9495 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9496 },
9497 { /* AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL: umull.4s $rd, $rn, $rm$idx */
9498 0,
9499 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9500 },
9501 { /* AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL: umull.4s $rd, $rn, $rm */
9502 0,
9503 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9504 },
9505 { /* AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2: umull2.2d $rd, $rn, $rm$idx */
9506 0,
9507 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9508 },
9509 { /* AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2: umull2.2d $rd, $rn, $rm */
9510 0,
9511 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9512 },
9513 { /* AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2: umull2.4s $rd, $rn, $rm$idx */
9514 0,
9515 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9516 },
9517 { /* AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2: umull2.4s $rd, $rn, $rm */
9518 0,
9519 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9520 },
9521 { /* AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL: umull.8h $rd, $rn, $rm */
9522 0,
9523 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9524 },
9525 { /* AArch64_UQADDv16i8, ARM64_INS_UQADD: uqadd.16b $rd, $rn, $rm| */
9526 0,
9527 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9528 },
9529 { /* AArch64_UQADDv1i16, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */
9530 0,
9531 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9532 },
9533 { /* AArch64_UQADDv1i32, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */
9534 0,
9535 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9536 },
9537 { /* AArch64_UQADDv1i64, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */
9538 0,
9539 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9540 },
9541 { /* AArch64_UQADDv1i8, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */
9542 0,
9543 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9544 },
9545 { /* AArch64_UQADDv2i32, ARM64_INS_UQADD: uqadd.2s $rd, $rn, $rm| */
9546 0,
9547 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9548 },
9549 { /* AArch64_UQADDv2i64, ARM64_INS_UQADD: uqadd.2d $rd, $rn, $rm| */
9550 0,
9551 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9552 },
9553 { /* AArch64_UQADDv4i16, ARM64_INS_UQADD: uqadd.4h $rd, $rn, $rm| */
9554 0,
9555 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9556 },
9557 { /* AArch64_UQADDv4i32, ARM64_INS_UQADD: uqadd.4s $rd, $rn, $rm| */
9558 0,
9559 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9560 },
9561 { /* AArch64_UQADDv8i16, ARM64_INS_UQADD: uqadd.8h $rd, $rn, $rm| */
9562 0,
9563 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9564 },
9565 { /* AArch64_UQADDv8i8, ARM64_INS_UQADD: uqadd.8b $rd, $rn, $rm| */
9566 0,
9567 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9568 },
9569 { /* AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL: uqrshl.16b $rd, $rn, $rm| */
9570 0,
9571 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9572 },
9573 { /* AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */
9574 0,
9575 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9576 },
9577 { /* AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */
9578 0,
9579 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9580 },
9581 { /* AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */
9582 0,
9583 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9584 },
9585 { /* AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */
9586 0,
9587 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9588 },
9589 { /* AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL: uqrshl.2s $rd, $rn, $rm| */
9590 0,
9591 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9592 },
9593 { /* AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL: uqrshl.2d $rd, $rn, $rm| */
9594 0,
9595 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9596 },
9597 { /* AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL: uqrshl.4h $rd, $rn, $rm| */
9598 0,
9599 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9600 },
9601 { /* AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL: uqrshl.4s $rd, $rn, $rm| */
9602 0,
9603 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9604 },
9605 { /* AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL: uqrshl.8h $rd, $rn, $rm| */
9606 0,
9607 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9608 },
9609 { /* AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL: uqrshl.8b $rd, $rn, $rm| */
9610 0,
9611 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9612 },
9613 { /* AArch64_UQRSHRNb, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */
9614 0,
9615 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9616 },
9617 { /* AArch64_UQRSHRNh, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */
9618 0,
9619 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9620 },
9621 { /* AArch64_UQRSHRNs, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */
9622 0,
9623 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9624 },
9625 { /* AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2: uqrshrn2.16b $rd, $rn, $imm */
9626 0,
9627 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9628 },
9629 { /* AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN: uqrshrn.2s $rd, $rn, $imm */
9630 0,
9631 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9632 },
9633 { /* AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN: uqrshrn.4h $rd, $rn, $imm */
9634 0,
9635 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9636 },
9637 { /* AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2: uqrshrn2.4s $rd, $rn, $imm */
9638 0,
9639 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9640 },
9641 { /* AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2: uqrshrn2.8h $rd, $rn, $imm */
9642 0,
9643 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9644 },
9645 { /* AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN: uqrshrn.8b $rd, $rn, $imm */
9646 0,
9647 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9648 },
9649 { /* AArch64_UQSHLb, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */
9650 0,
9651 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9652 },
9653 { /* AArch64_UQSHLd, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */
9654 0,
9655 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9656 },
9657 { /* AArch64_UQSHLh, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */
9658 0,
9659 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9660 },
9661 { /* AArch64_UQSHLs, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */
9662 0,
9663 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9664 },
9665 { /* AArch64_UQSHLv16i8, ARM64_INS_UQSHL: uqshl.16b $rd, $rn, $rm| */
9666 0,
9667 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9668 },
9669 { /* AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL: uqshl.16b $rd, $rn, $imm */
9670 0,
9671 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9672 },
9673 { /* AArch64_UQSHLv1i16, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */
9674 0,
9675 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9676 },
9677 { /* AArch64_UQSHLv1i32, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */
9678 0,
9679 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9680 },
9681 { /* AArch64_UQSHLv1i64, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */
9682 0,
9683 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9684 },
9685 { /* AArch64_UQSHLv1i8, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */
9686 0,
9687 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9688 },
9689 { /* AArch64_UQSHLv2i32, ARM64_INS_UQSHL: uqshl.2s $rd, $rn, $rm| */
9690 0,
9691 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9692 },
9693 { /* AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL: uqshl.2s $rd, $rn, $imm */
9694 0,
9695 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9696 },
9697 { /* AArch64_UQSHLv2i64, ARM64_INS_UQSHL: uqshl.2d $rd, $rn, $rm| */
9698 0,
9699 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9700 },
9701 { /* AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL: uqshl.2d $rd, $rn, $imm */
9702 0,
9703 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9704 },
9705 { /* AArch64_UQSHLv4i16, ARM64_INS_UQSHL: uqshl.4h $rd, $rn, $rm| */
9706 0,
9707 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9708 },
9709 { /* AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL: uqshl.4h $rd, $rn, $imm */
9710 0,
9711 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9712 },
9713 { /* AArch64_UQSHLv4i32, ARM64_INS_UQSHL: uqshl.4s $rd, $rn, $rm| */
9714 0,
9715 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9716 },
9717 { /* AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL: uqshl.4s $rd, $rn, $imm */
9718 0,
9719 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9720 },
9721 { /* AArch64_UQSHLv8i16, ARM64_INS_UQSHL: uqshl.8h $rd, $rn, $rm| */
9722 0,
9723 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9724 },
9725 { /* AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL: uqshl.8h $rd, $rn, $imm */
9726 0,
9727 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9728 },
9729 { /* AArch64_UQSHLv8i8, ARM64_INS_UQSHL: uqshl.8b $rd, $rn, $rm| */
9730 0,
9731 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9732 },
9733 { /* AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL: uqshl.8b $rd, $rn, $imm */
9734 0,
9735 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9736 },
9737 { /* AArch64_UQSHRNb, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */
9738 0,
9739 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9740 },
9741 { /* AArch64_UQSHRNh, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */
9742 0,
9743 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9744 },
9745 { /* AArch64_UQSHRNs, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */
9746 0,
9747 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9748 },
9749 { /* AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2: uqshrn2.16b $rd, $rn, $imm */
9750 0,
9751 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9752 },
9753 { /* AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN: uqshrn.2s $rd, $rn, $imm */
9754 0,
9755 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9756 },
9757 { /* AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN: uqshrn.4h $rd, $rn, $imm */
9758 0,
9759 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9760 },
9761 { /* AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2: uqshrn2.4s $rd, $rn, $imm */
9762 0,
9763 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9764 },
9765 { /* AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2: uqshrn2.8h $rd, $rn, $imm */
9766 0,
9767 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9768 },
9769 { /* AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN: uqshrn.8b $rd, $rn, $imm */
9770 0,
9771 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9772 },
9773 { /* AArch64_UQSUBv16i8, ARM64_INS_UQSUB: uqsub.16b $rd, $rn, $rm| */
9774 0,
9775 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9776 },
9777 { /* AArch64_UQSUBv1i16, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */
9778 0,
9779 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9780 },
9781 { /* AArch64_UQSUBv1i32, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */
9782 0,
9783 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9784 },
9785 { /* AArch64_UQSUBv1i64, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */
9786 0,
9787 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9788 },
9789 { /* AArch64_UQSUBv1i8, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */
9790 0,
9791 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9792 },
9793 { /* AArch64_UQSUBv2i32, ARM64_INS_UQSUB: uqsub.2s $rd, $rn, $rm| */
9794 0,
9795 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9796 },
9797 { /* AArch64_UQSUBv2i64, ARM64_INS_UQSUB: uqsub.2d $rd, $rn, $rm| */
9798 0,
9799 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9800 },
9801 { /* AArch64_UQSUBv4i16, ARM64_INS_UQSUB: uqsub.4h $rd, $rn, $rm| */
9802 0,
9803 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9804 },
9805 { /* AArch64_UQSUBv4i32, ARM64_INS_UQSUB: uqsub.4s $rd, $rn, $rm| */
9806 0,
9807 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9808 },
9809 { /* AArch64_UQSUBv8i16, ARM64_INS_UQSUB: uqsub.8h $rd, $rn, $rm| */
9810 0,
9811 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9812 },
9813 { /* AArch64_UQSUBv8i8, ARM64_INS_UQSUB: uqsub.8b $rd, $rn, $rm| */
9814 0,
9815 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9816 },
9817 { /* AArch64_UQXTNv16i8, ARM64_INS_UQXTN2: uqxtn2.16b $rd, $rn */
9818 0,
9819 { CS_OP_WRITE, CS_OP_READ, 0 }
9820 },
9821 { /* AArch64_UQXTNv1i16, ARM64_INS_UQXTN: uqxtn $rd, $rn */
9822 0,
9823 { CS_OP_WRITE, CS_OP_READ, 0 }
9824 },
9825 { /* AArch64_UQXTNv1i32, ARM64_INS_UQXTN: uqxtn $rd, $rn */
9826 0,
9827 { CS_OP_WRITE, CS_OP_READ, 0 }
9828 },
9829 { /* AArch64_UQXTNv1i8, ARM64_INS_UQXTN: uqxtn $rd, $rn */
9830 0,
9831 { CS_OP_WRITE, CS_OP_READ, 0 }
9832 },
9833 { /* AArch64_UQXTNv2i32, ARM64_INS_UQXTN: uqxtn.2s $rd, $rn */
9834 0,
9835 { CS_OP_WRITE, CS_OP_READ, 0 }
9836 },
9837 { /* AArch64_UQXTNv4i16, ARM64_INS_UQXTN: uqxtn.4h $rd, $rn */
9838 0,
9839 { CS_OP_WRITE, CS_OP_READ, 0 }
9840 },
9841 { /* AArch64_UQXTNv4i32, ARM64_INS_UQXTN2: uqxtn2.4s $rd, $rn */
9842 0,
9843 { CS_OP_WRITE, CS_OP_READ, 0 }
9844 },
9845 { /* AArch64_UQXTNv8i16, ARM64_INS_UQXTN2: uqxtn2.8h $rd, $rn */
9846 0,
9847 { CS_OP_WRITE, CS_OP_READ, 0 }
9848 },
9849 { /* AArch64_UQXTNv8i8, ARM64_INS_UQXTN: uqxtn.8b $rd, $rn */
9850 0,
9851 { CS_OP_WRITE, CS_OP_READ, 0 }
9852 },
9853 { /* AArch64_URECPEv2i32, ARM64_INS_URECPE: urecpe.2s $rd, $rn */
9854 0,
9855 { CS_OP_WRITE, CS_OP_READ, 0 }
9856 },
9857 { /* AArch64_URECPEv4i32, ARM64_INS_URECPE: urecpe.4s $rd, $rn */
9858 0,
9859 { CS_OP_WRITE, CS_OP_READ, 0 }
9860 },
9861 { /* AArch64_URHADDv16i8, ARM64_INS_URHADD: urhadd.16b $rd, $rn, $rm| */
9862 0,
9863 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9864 },
9865 { /* AArch64_URHADDv2i32, ARM64_INS_URHADD: urhadd.2s $rd, $rn, $rm| */
9866 0,
9867 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9868 },
9869 { /* AArch64_URHADDv4i16, ARM64_INS_URHADD: urhadd.4h $rd, $rn, $rm| */
9870 0,
9871 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9872 },
9873 { /* AArch64_URHADDv4i32, ARM64_INS_URHADD: urhadd.4s $rd, $rn, $rm| */
9874 0,
9875 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9876 },
9877 { /* AArch64_URHADDv8i16, ARM64_INS_URHADD: urhadd.8h $rd, $rn, $rm| */
9878 0,
9879 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9880 },
9881 { /* AArch64_URHADDv8i8, ARM64_INS_URHADD: urhadd.8b $rd, $rn, $rm| */
9882 0,
9883 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9884 },
9885 { /* AArch64_URSHLv16i8, ARM64_INS_URSHL: urshl.16b $rd, $rn, $rm| */
9886 0,
9887 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9888 },
9889 { /* AArch64_URSHLv1i64, ARM64_INS_URSHL: urshl $rd, $rn, $rm */
9890 0,
9891 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9892 },
9893 { /* AArch64_URSHLv2i32, ARM64_INS_URSHL: urshl.2s $rd, $rn, $rm| */
9894 0,
9895 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9896 },
9897 { /* AArch64_URSHLv2i64, ARM64_INS_URSHL: urshl.2d $rd, $rn, $rm| */
9898 0,
9899 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9900 },
9901 { /* AArch64_URSHLv4i16, ARM64_INS_URSHL: urshl.4h $rd, $rn, $rm| */
9902 0,
9903 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9904 },
9905 { /* AArch64_URSHLv4i32, ARM64_INS_URSHL: urshl.4s $rd, $rn, $rm| */
9906 0,
9907 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9908 },
9909 { /* AArch64_URSHLv8i16, ARM64_INS_URSHL: urshl.8h $rd, $rn, $rm| */
9910 0,
9911 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9912 },
9913 { /* AArch64_URSHLv8i8, ARM64_INS_URSHL: urshl.8b $rd, $rn, $rm| */
9914 0,
9915 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9916 },
9917 { /* AArch64_URSHRd, ARM64_INS_URSHR: urshr $rd, $rn, $imm */
9918 0,
9919 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9920 },
9921 { /* AArch64_URSHRv16i8_shift, ARM64_INS_URSHR: urshr.16b $rd, $rn, $imm */
9922 0,
9923 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9924 },
9925 { /* AArch64_URSHRv2i32_shift, ARM64_INS_URSHR: urshr.2s $rd, $rn, $imm */
9926 0,
9927 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9928 },
9929 { /* AArch64_URSHRv2i64_shift, ARM64_INS_URSHR: urshr.2d $rd, $rn, $imm */
9930 0,
9931 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9932 },
9933 { /* AArch64_URSHRv4i16_shift, ARM64_INS_URSHR: urshr.4h $rd, $rn, $imm */
9934 0,
9935 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9936 },
9937 { /* AArch64_URSHRv4i32_shift, ARM64_INS_URSHR: urshr.4s $rd, $rn, $imm */
9938 0,
9939 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9940 },
9941 { /* AArch64_URSHRv8i16_shift, ARM64_INS_URSHR: urshr.8h $rd, $rn, $imm */
9942 0,
9943 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9944 },
9945 { /* AArch64_URSHRv8i8_shift, ARM64_INS_URSHR: urshr.8b $rd, $rn, $imm */
9946 0,
9947 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9948 },
9949 { /* AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE: ursqrte.2s $rd, $rn */
9950 0,
9951 { CS_OP_WRITE, CS_OP_READ, 0 }
9952 },
9953 { /* AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE: ursqrte.4s $rd, $rn */
9954 0,
9955 { CS_OP_WRITE, CS_OP_READ, 0 }
9956 },
9957 { /* AArch64_URSRAd, ARM64_INS_URSRA: ursra $rd, $rn, $imm */
9958 0,
9959 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9960 },
9961 { /* AArch64_URSRAv16i8_shift, ARM64_INS_URSRA: ursra.16b $rd, $rn, $imm */
9962 0,
9963 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9964 },
9965 { /* AArch64_URSRAv2i32_shift, ARM64_INS_URSRA: ursra.2s $rd, $rn, $imm */
9966 0,
9967 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9968 },
9969 { /* AArch64_URSRAv2i64_shift, ARM64_INS_URSRA: ursra.2d $rd, $rn, $imm */
9970 0,
9971 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9972 },
9973 { /* AArch64_URSRAv4i16_shift, ARM64_INS_URSRA: ursra.4h $rd, $rn, $imm */
9974 0,
9975 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9976 },
9977 { /* AArch64_URSRAv4i32_shift, ARM64_INS_URSRA: ursra.4s $rd, $rn, $imm */
9978 0,
9979 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9980 },
9981 { /* AArch64_URSRAv8i16_shift, ARM64_INS_URSRA: ursra.8h $rd, $rn, $imm */
9982 0,
9983 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9984 },
9985 { /* AArch64_URSRAv8i8_shift, ARM64_INS_URSRA: ursra.8b $rd, $rn, $imm */
9986 0,
9987 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
9988 },
9989 { /* AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2: ushll2.8h $rd, $rn, $imm */
9990 0,
9991 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9992 },
9993 { /* AArch64_USHLLv2i32_shift, ARM64_INS_USHLL: ushll.2d $rd, $rn, $imm */
9994 0,
9995 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
9996 },
9997 { /* AArch64_USHLLv4i16_shift, ARM64_INS_USHLL: ushll.4s $rd, $rn, $imm */
9998 0,
9999 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10000 },
10001 { /* AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2: ushll2.2d $rd, $rn, $imm */
10002 0,
10003 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10004 },
10005 { /* AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2: ushll2.4s $rd, $rn, $imm */
10006 0,
10007 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10008 },
10009 { /* AArch64_USHLLv8i8_shift, ARM64_INS_USHLL: ushll.8h $rd, $rn, $imm */
10010 0,
10011 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10012 },
10013 { /* AArch64_USHLv16i8, ARM64_INS_USHL: ushl.16b $rd, $rn, $rm| */
10014 0,
10015 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10016 },
10017 { /* AArch64_USHLv1i64, ARM64_INS_USHL: ushl $rd, $rn, $rm */
10018 0,
10019 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10020 },
10021 { /* AArch64_USHLv2i32, ARM64_INS_USHL: ushl.2s $rd, $rn, $rm| */
10022 0,
10023 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10024 },
10025 { /* AArch64_USHLv2i64, ARM64_INS_USHL: ushl.2d $rd, $rn, $rm| */
10026 0,
10027 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10028 },
10029 { /* AArch64_USHLv4i16, ARM64_INS_USHL: ushl.4h $rd, $rn, $rm| */
10030 0,
10031 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10032 },
10033 { /* AArch64_USHLv4i32, ARM64_INS_USHL: ushl.4s $rd, $rn, $rm| */
10034 0,
10035 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10036 },
10037 { /* AArch64_USHLv8i16, ARM64_INS_USHL: ushl.8h $rd, $rn, $rm| */
10038 0,
10039 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10040 },
10041 { /* AArch64_USHLv8i8, ARM64_INS_USHL: ushl.8b $rd, $rn, $rm| */
10042 0,
10043 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10044 },
10045 { /* AArch64_USHRd, ARM64_INS_USHR: ushr $rd, $rn, $imm */
10046 0,
10047 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10048 },
10049 { /* AArch64_USHRv16i8_shift, ARM64_INS_USHR: ushr.16b $rd, $rn, $imm */
10050 0,
10051 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10052 },
10053 { /* AArch64_USHRv2i32_shift, ARM64_INS_USHR: ushr.2s $rd, $rn, $imm */
10054 0,
10055 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10056 },
10057 { /* AArch64_USHRv2i64_shift, ARM64_INS_USHR: ushr.2d $rd, $rn, $imm */
10058 0,
10059 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10060 },
10061 { /* AArch64_USHRv4i16_shift, ARM64_INS_USHR: ushr.4h $rd, $rn, $imm */
10062 0,
10063 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10064 },
10065 { /* AArch64_USHRv4i32_shift, ARM64_INS_USHR: ushr.4s $rd, $rn, $imm */
10066 0,
10067 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10068 },
10069 { /* AArch64_USHRv8i16_shift, ARM64_INS_USHR: ushr.8h $rd, $rn, $imm */
10070 0,
10071 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10072 },
10073 { /* AArch64_USHRv8i8_shift, ARM64_INS_USHR: ushr.8b $rd, $rn, $imm */
10074 0,
10075 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10076 },
10077 { /* AArch64_USQADDv16i8, ARM64_INS_USQADD: usqadd.16b $rd, $rn */
10078 0,
10079 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10080 },
10081 { /* AArch64_USQADDv1i16, ARM64_INS_USQADD: usqadd $rd, $rn */
10082 0,
10083 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10084 },
10085 { /* AArch64_USQADDv1i32, ARM64_INS_USQADD: usqadd $rd, $rn */
10086 0,
10087 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10088 },
10089 { /* AArch64_USQADDv1i64, ARM64_INS_USQADD: usqadd $rd, $rn */
10090 0,
10091 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10092 },
10093 { /* AArch64_USQADDv1i8, ARM64_INS_USQADD: usqadd $rd, $rn */
10094 0,
10095 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10096 },
10097 { /* AArch64_USQADDv2i32, ARM64_INS_USQADD: usqadd.2s $rd, $rn */
10098 0,
10099 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10100 },
10101 { /* AArch64_USQADDv2i64, ARM64_INS_USQADD: usqadd.2d $rd, $rn */
10102 0,
10103 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10104 },
10105 { /* AArch64_USQADDv4i16, ARM64_INS_USQADD: usqadd.4h $rd, $rn */
10106 0,
10107 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10108 },
10109 { /* AArch64_USQADDv4i32, ARM64_INS_USQADD: usqadd.4s $rd, $rn */
10110 0,
10111 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10112 },
10113 { /* AArch64_USQADDv8i16, ARM64_INS_USQADD: usqadd.8h $rd, $rn */
10114 0,
10115 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10116 },
10117 { /* AArch64_USQADDv8i8, ARM64_INS_USQADD: usqadd.8b $rd, $rn */
10118 0,
10119 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, 0 }
10120 },
10121 { /* AArch64_USRAd, ARM64_INS_USRA: usra $rd, $rn, $imm */
10122 0,
10123 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10124 },
10125 { /* AArch64_USRAv16i8_shift, ARM64_INS_USRA: usra.16b $rd, $rn, $imm */
10126 0,
10127 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10128 },
10129 { /* AArch64_USRAv2i32_shift, ARM64_INS_USRA: usra.2s $rd, $rn, $imm */
10130 0,
10131 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10132 },
10133 { /* AArch64_USRAv2i64_shift, ARM64_INS_USRA: usra.2d $rd, $rn, $imm */
10134 0,
10135 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10136 },
10137 { /* AArch64_USRAv4i16_shift, ARM64_INS_USRA: usra.4h $rd, $rn, $imm */
10138 0,
10139 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10140 },
10141 { /* AArch64_USRAv4i32_shift, ARM64_INS_USRA: usra.4s $rd, $rn, $imm */
10142 0,
10143 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10144 },
10145 { /* AArch64_USRAv8i16_shift, ARM64_INS_USRA: usra.8h $rd, $rn, $imm */
10146 0,
10147 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10148 },
10149 { /* AArch64_USRAv8i8_shift, ARM64_INS_USRA: usra.8b $rd, $rn, $imm */
10150 0,
10151 { CS_OP_WRITE | CS_OP_READ, CS_OP_READ, CS_OP_READ, 0 }
10152 },
10153 { /* AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2: usubl2.8h $rd, $rn, $rm */
10154 0,
10155 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10156 },
10157 { /* AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL: usubl.2d $rd, $rn, $rm */
10158 0,
10159 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10160 },
10161 { /* AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL: usubl.4s $rd, $rn, $rm */
10162 0,
10163 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10164 },
10165 { /* AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2: usubl2.2d $rd, $rn, $rm */
10166 0,
10167 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10168 },
10169 { /* AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2: usubl2.4s $rd, $rn, $rm */
10170 0,
10171 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10172 },
10173 { /* AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL: usubl.8h $rd, $rn, $rm */
10174 0,
10175 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10176 },
10177 { /* AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2: usubw2.8h $rd, $rn, $rm */
10178 0,
10179 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10180 },
10181 { /* AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW: usubw.2d $rd, $rn, $rm */
10182 0,
10183 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10184 },
10185 { /* AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW: usubw.4s $rd, $rn, $rm */
10186 0,
10187 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10188 },
10189 { /* AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2: usubw2.2d $rd, $rn, $rm */
10190 0,
10191 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10192 },
10193 { /* AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2: usubw2.4s $rd, $rn, $rm */
10194 0,
10195 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10196 },
10197 { /* AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW: usubw.8h $rd, $rn, $rm */
10198 0,
10199 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10200 },
10201 { /* AArch64_UZP1v16i8, ARM64_INS_UZP1: uzp1.16b $rd, $rn, $rm */
10202 0,
10203 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10204 },
10205 { /* AArch64_UZP1v2i32, ARM64_INS_UZP1: uzp1.2s $rd, $rn, $rm */
10206 0,
10207 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10208 },
10209 { /* AArch64_UZP1v2i64, ARM64_INS_UZP1: uzp1.2d $rd, $rn, $rm */
10210 0,
10211 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10212 },
10213 { /* AArch64_UZP1v4i16, ARM64_INS_UZP1: uzp1.4h $rd, $rn, $rm */
10214 0,
10215 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10216 },
10217 { /* AArch64_UZP1v4i32, ARM64_INS_UZP1: uzp1.4s $rd, $rn, $rm */
10218 0,
10219 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10220 },
10221 { /* AArch64_UZP1v8i16, ARM64_INS_UZP1: uzp1.8h $rd, $rn, $rm */
10222 0,
10223 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10224 },
10225 { /* AArch64_UZP1v8i8, ARM64_INS_UZP1: uzp1.8b $rd, $rn, $rm */
10226 0,
10227 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10228 },
10229 { /* AArch64_UZP2v16i8, ARM64_INS_UZP2: uzp2.16b $rd, $rn, $rm */
10230 0,
10231 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10232 },
10233 { /* AArch64_UZP2v2i32, ARM64_INS_UZP2: uzp2.2s $rd, $rn, $rm */
10234 0,
10235 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10236 },
10237 { /* AArch64_UZP2v2i64, ARM64_INS_UZP2: uzp2.2d $rd, $rn, $rm */
10238 0,
10239 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10240 },
10241 { /* AArch64_UZP2v4i16, ARM64_INS_UZP2: uzp2.4h $rd, $rn, $rm */
10242 0,
10243 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10244 },
10245 { /* AArch64_UZP2v4i32, ARM64_INS_UZP2: uzp2.4s $rd, $rn, $rm */
10246 0,
10247 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10248 },
10249 { /* AArch64_UZP2v8i16, ARM64_INS_UZP2: uzp2.8h $rd, $rn, $rm */
10250 0,
10251 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10252 },
10253 { /* AArch64_UZP2v8i8, ARM64_INS_UZP2: uzp2.8b $rd, $rn, $rm */
10254 0,
10255 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10256 },
10257 { /* AArch64_XTNv16i8, ARM64_INS_XTN2: xtn2.16b $rd, $rn */
10258 0,
10259 { CS_OP_WRITE, CS_OP_READ, 0 }
10260 },
10261 { /* AArch64_XTNv2i32, ARM64_INS_XTN: xtn.2s $rd, $rn */
10262 0,
10263 { CS_OP_WRITE, CS_OP_READ, 0 }
10264 },
10265 { /* AArch64_XTNv4i16, ARM64_INS_XTN: xtn.4h $rd, $rn */
10266 0,
10267 { CS_OP_WRITE, CS_OP_READ, 0 }
10268 },
10269 { /* AArch64_XTNv4i32, ARM64_INS_XTN2: xtn2.4s $rd, $rn */
10270 0,
10271 { CS_OP_WRITE, CS_OP_READ, 0 }
10272 },
10273 { /* AArch64_XTNv8i16, ARM64_INS_XTN2: xtn2.8h $rd, $rn */
10274 0,
10275 { CS_OP_WRITE, CS_OP_READ, 0 }
10276 },
10277 { /* AArch64_XTNv8i8, ARM64_INS_XTN: xtn.8b $rd, $rn */
10278 0,
10279 { CS_OP_WRITE, CS_OP_READ, 0 }
10280 },
10281 { /* AArch64_ZIP1v16i8, ARM64_INS_ZIP1: zip1.16b $rd, $rn, $rm */
10282 0,
10283 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10284 },
10285 { /* AArch64_ZIP1v2i32, ARM64_INS_ZIP1: zip1.2s $rd, $rn, $rm */
10286 0,
10287 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10288 },
10289 { /* AArch64_ZIP1v2i64, ARM64_INS_ZIP1: zip1.2d $rd, $rn, $rm */
10290 0,
10291 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10292 },
10293 { /* AArch64_ZIP1v4i16, ARM64_INS_ZIP1: zip1.4h $rd, $rn, $rm */
10294 0,
10295 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10296 },
10297 { /* AArch64_ZIP1v4i32, ARM64_INS_ZIP1: zip1.4s $rd, $rn, $rm */
10298 0,
10299 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10300 },
10301 { /* AArch64_ZIP1v8i16, ARM64_INS_ZIP1: zip1.8h $rd, $rn, $rm */
10302 0,
10303 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10304 },
10305 { /* AArch64_ZIP1v8i8, ARM64_INS_ZIP1: zip1.8b $rd, $rn, $rm */
10306 0,
10307 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10308 },
10309 { /* AArch64_ZIP2v16i8, ARM64_INS_ZIP2: zip2.16b $rd, $rn, $rm */
10310 0,
10311 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10312 },
10313 { /* AArch64_ZIP2v2i32, ARM64_INS_ZIP2: zip2.2s $rd, $rn, $rm */
10314 0,
10315 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10316 },
10317 { /* AArch64_ZIP2v2i64, ARM64_INS_ZIP2: zip2.2d $rd, $rn, $rm */
10318 0,
10319 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10320 },
10321 { /* AArch64_ZIP2v4i16, ARM64_INS_ZIP2: zip2.4h $rd, $rn, $rm */
10322 0,
10323 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10324 },
10325 { /* AArch64_ZIP2v4i32, ARM64_INS_ZIP2: zip2.4s $rd, $rn, $rm */
10326 0,
10327 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10328 },
10329 { /* AArch64_ZIP2v8i16, ARM64_INS_ZIP2: zip2.8h $rd, $rn, $rm */
10330 0,
10331 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
10332 },
10333 { /* AArch64_ZIP2v8i8, ARM64_INS_ZIP2: zip2.8b $rd, $rn, $rm */
10334 0,
10335 { CS_OP_WRITE, CS_OP_READ, CS_OP_READ, 0 }
Nguyen Anh Quynhed6d75a2015-02-24 22:03:28 +0800[diff] [blame]10336 }
10337};
Nguyen Anh Quynhe8eb5362015-02-23 11:35:35 +0800[diff] [blame]10338#endif
Nguyen Anh Quynhed6d75a2015-02-24 22:03:28 +0800[diff] [blame]10339
Nguyen Anh Quynh8598a212014-05-14 11:26:41 +0800[diff] [blame]10340#endif