blob: 2efb6191c7dd7cb5874435aebec80bbd2cb2482e [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
Wu Fengguang020abdb2010-04-19 13:13:06 +080029#define _GNU_SOURCE
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080030#include <unistd.h>
Wu Fengguang020abdb2010-04-19 13:13:06 +080031#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <err.h>
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080035#include <arpa/inet.h>
36#include "intel_gpu_tools.h"
37
Wu Fengguang020abdb2010-04-19 13:13:06 +080038static uint32_t devid;
39
40
41#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
42#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
43#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
44#define BIT(reg, n) BITS(reg, n, n)
45
46#define min_t(type, x, y) ({ \
47 type __min1 = (x); \
48 type __min2 = (y); \
49 __min1 < __min2 ? __min1: __min2; })
50
51#define OPNAME(names, index) \
52 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
53
54#define dump_reg(reg, desc) \
55 do { \
56 dword = INREG(reg); \
57 printf("%-21s 0x%08x %s\n", # reg, dword, desc); \
58 } while (0)
59
60
61static char *pixel_clock[] = {
62 [0] = "25.2 / 1.001 MHz",
63 [1] = "25.2 MHz",
64 [2] = "27 MHz",
65 [3] = "27 * 1.001 MHz",
66 [4] = "54 MHz",
67 [5] = "54 * 1.001 MHz",
68 [6] = "74.25 / 1.001 MHz",
69 [7] = "74.25 MHz",
70 [8] = "148.5 / 1.001 MHz",
71 [9] = "148.5 MHz",
72 [10] = "Reserved",
73};
74
75static char *power_state[] = {
76 [0] = "D0",
77 [1] = "D1",
78 [2] = "D2",
79 [3] = "D3",
80};
81
82static char *stream_type[] = {
83 [0] = "default samples",
84 [1] = "one bit stream",
85 [2] = "DST stream",
86 [3] = "MLP stream",
87 [4] = "Reserved",
88};
89
90static char *dip_port[] = {
91 [0] = "Reserved",
92 [1] = "Digital Port B",
93 [2] = "Digital Port C",
94 [3] = "Digital Port D",
95};
96
97static char *dip_index[] = {
98 [0] = "Audio DIP",
99 [1] = "ACP DIP",
100 [2] = "ISRC1 DIP",
101 [3] = "ISRC2 DIP",
102 [4] = "Reserved",
103};
104
105static char *dip_trans[] = {
106 [0] = "disabled",
107 [1] = "reserved",
108 [2] = "send once",
109 [3] = "best effort",
110};
111
112static char *video_dip_index[] = {
113 [0] = "AVI DIP",
114 [1] = "Vendor-specific DIP",
115 [2] = "Reserved",
116 [3] = "Source Product Description DIP",
117};
118
119static char *video_dip_trans[] = {
120 [0] = "send once",
121 [1] = "send every vsync",
122 [2] = "send at least every other vsync",
123 [3] = "reserved",
124};
125
126static char *trans_to_port_sel[] = {
127 [0] = "no port",
128 [1] = "Digital Port B",
129 [2] = "Digital Port B",
130 [3] = "Digital Port B",
131 [4] = "Digital Port B",
132 [5 ... 7] = "reserved",
133};
134
135static char *transcoder_select[] = {
136 [0] = "Transcoder A",
137 [1] = "Transcoder B",
138 [2] = "Transcoder C",
139 [3] = "reserved",
140};
141
142static char *dp_port_width[] = {
143 [0] = "x1 mode",
144 [1] = "x2 mode",
Wu Fengguangcf4c12f2011-11-12 11:12:46 +0800145 [2] = "reserved",
146 [3] = "x4 mode",
147 [4 ... 7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800148};
149
Wu Fengguang12861a92011-11-12 11:12:47 +0800150static char *bits_per_sample[] = {
151 [0] = "reserved",
152 [1] = "16 bits",
153 [2] = "24 bits",
154 [3] = "32 bits",
155 [4] = "20 bits",
156 [5] = "reserved",
157};
158
159
Wu Fengguang020abdb2010-04-19 13:13:06 +0800160static void do_self_tests(void)
161{
162 if (BIT(1, 0) != 1)
163 exit(1);
164 if (BIT(0x80000000, 31) != 1)
165 exit(2);
166 if (BITS(0xc0000000, 31, 30) != 3)
167 exit(3);
168}
169
170/*
171 * EagleLake registers
172 */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800173#define AUD_CONFIG 0x62000
174#define AUD_DEBUG 0x62010
175#define AUD_VID_DID 0x62020
176#define AUD_RID 0x62024
177#define AUD_SUBN_CNT 0x62028
178#define AUD_FUNC_GRP 0x62040
179#define AUD_SUBN_CNT2 0x62044
180#define AUD_GRP_CAP 0x62048
181#define AUD_PWRST 0x6204c
182#define AUD_SUPPWR 0x62050
183#define AUD_SID 0x62054
184#define AUD_OUT_CWCAP 0x62070
185#define AUD_OUT_PCMSIZE 0x62074
186#define AUD_OUT_STR 0x62078
187#define AUD_OUT_DIG_CNVT 0x6207c
188#define AUD_OUT_CH_STR 0x62080
189#define AUD_OUT_STR_DESC 0x62084
190#define AUD_PINW_CAP 0x620a0
191#define AUD_PIN_CAP 0x620a4
192#define AUD_PINW_CONNLNG 0x620a8
193#define AUD_PINW_CONNLST 0x620ac
194#define AUD_PINW_CNTR 0x620b0
195#define AUD_PINW_UNSOLRESP 0x620b8
196#define AUD_CNTL_ST 0x620b4
197#define AUD_PINW_CONFIG 0x620bc
198#define AUD_HDMIW_STATUS 0x620d4
199#define AUD_HDMIW_HDMIEDID 0x6210c
200#define AUD_HDMIW_INFOFR 0x62118
201#define AUD_CONV_CHCNT 0x62120
202#define AUD_CTS_ENABLE 0x62128
203
204#define VIDEO_DIP_CTL 0x61170
205#define VIDEO_DIP_ENABLE (1<<31)
206#define VIDEO_DIP_ENABLE_AVI (1<<21)
207#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
208#define VIDEO_DIP_ENABLE_SPD (1<<24)
209#define VIDEO_DIP_BUF_AVI (0<<19)
210#define VIDEO_DIP_BUF_VENDOR (1<<19)
211#define VIDEO_DIP_BUF_SPD (3<<19)
212#define VIDEO_DIP_TRANS_ONCE (0<<16)
213#define VIDEO_DIP_TRANS_1 (1<<16)
214#define VIDEO_DIP_TRANS_2 (2<<16)
215
216#define AUDIO_HOTPLUG_EN (1<<24)
217
218
Wu Fengguang020abdb2010-04-19 13:13:06 +0800219static void dump_eaglelake(void)
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800220{
221 uint32_t dword;
222 int i;
223
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800224 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
225
226 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
227 dump_reg(SDVOB, "Digital Display Port B Control Register");
228 dump_reg(SDVOC, "Digital Display Port C Control Register");
229 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
230
231 dump_reg(AUD_CONFIG, "Audio Configuration");
232 dump_reg(AUD_DEBUG, "Audio Debug");
233 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
234 dump_reg(AUD_RID, "Audio Revision ID");
235 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
236 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
237 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
238 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
239 dump_reg(AUD_PWRST, "Audio Power State");
240 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
241 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
242 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
243 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
244 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
245 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
246 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
247 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
248 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
249 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
250 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
251 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
252 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
253 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
254 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
255 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
256 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
257 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
258 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
259 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
260 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
261
262 printf("\nDetails:\n\n");
263
264 dword = INREG(AUD_VID_DID);
265 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
266 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
267
268 dword = INREG(AUD_RID);
269 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
270 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
271 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
272 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
273
274 dword = INREG(SDVOB);
275 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
276 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
277 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
278 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
279 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
280
281 dword = INREG(SDVOC);
282 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
283 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
284 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
285 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
286 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
287
288 dword = INREG(PORT_HOTPLUG_EN);
289 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
290 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
291 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
292 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
293 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
294 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
295 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
296 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
297
298 dword = INREG(VIDEO_DIP_CTL);
299 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
300 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
301 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
302 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
303 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
304 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
305 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
306 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
307 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
308 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
309 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
310 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
311 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
312
313 dword = INREG(AUD_CONFIG);
314 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
315 OPNAME(pixel_clock, BITS(dword, 19, 16)));
316 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
317 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
318 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
319
320 dword = INREG(AUD_DEBUG);
321 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
322
323 dword = INREG(AUD_SUBN_CNT);
324 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
325 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
326
327 dword = INREG(AUD_SUBN_CNT2);
328 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
329 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
330
331 dword = INREG(AUD_FUNC_GRP);
332 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
333 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
334
335 dword = INREG(AUD_GRP_CAP);
336 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
337 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
338 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
339
340 dword = INREG(AUD_PWRST);
341 printf("AUD_PWRST device power state\t\t%s\n",
342 power_state[BITS(dword, 5, 4)]);
343 printf("AUD_PWRST device power state setting\t%s\n",
344 power_state[BITS(dword, 1, 0)]);
345
346 dword = INREG(AUD_SUPPWR);
347 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
348 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
349 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
350 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
351
352 dword = INREG(AUD_OUT_CWCAP);
353 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
354 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
355 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
356 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
357 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
358 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
359 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
360 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
361 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
362 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
363 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
364 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
365 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
366 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
367
368 dword = INREG(AUD_OUT_DIG_CNVT);
369 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
370 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
371 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
372 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
373 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
374 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
375 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
376 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
377 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
378
379 dword = INREG(AUD_OUT_CH_STR);
380 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
Wu Fengguang5032f682011-11-12 11:12:41 +0800381 printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800382
383 dword = INREG(AUD_OUT_STR_DESC);
Wu Fengguang5032f682011-11-12 11:12:41 +0800384 printf("AUD_OUT_STR_DESC stream channels\t%lu\n", BITS(dword, 3, 0) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800385 printf("AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n",
386 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800387
388 dword = INREG(AUD_PINW_CAP);
389 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
390 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
Wu Fengguang5032f682011-11-12 11:12:41 +0800391 printf("AUD_PINW_CAP channel count\t\t%lu\n",
392 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800393 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
394 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
395 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
396 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
397 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
398 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
399 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
400 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
401 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
402 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
403 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
404
405
406 dword = INREG(AUD_PIN_CAP);
407 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
408 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
409 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
410 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
411
412 dword = INREG(AUD_PINW_CNTR);
413 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
414 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
415 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
416 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
417 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
418 BITS(dword, 2, 0),
419 OPNAME(stream_type, BITS(dword, 2, 0)));
420
421 dword = INREG(AUD_PINW_UNSOLRESP);
422 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
423
424 dword = INREG(AUD_CNTL_ST);
425 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
426 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
427 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
428 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
429 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
430 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
431 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
432 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
433 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
434 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
435 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
436 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
437 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
438 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
439 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
440
441 dword = INREG(AUD_HDMIW_STATUS);
442 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
443 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
444 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
445 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
446
447 dword = INREG(AUD_CONV_CHCNT);
448 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
449 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
450
451 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
452 for (i = 0; i < 8; i++) {
453 OUTREG(AUD_CONV_CHCNT, i);
454 dword = INREG(AUD_CONV_CHCNT);
455 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
456 }
457
458 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
459 dword = INREG(AUD_CNTL_ST);
460 dword &= ~BITMASK(20, 18);
461 dword &= ~BITMASK(3, 0);
462 OUTREG(AUD_CNTL_ST, dword);
463 for (i = 0; i < 8; i++)
464 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
465 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800466}
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800467
Wu Fengguang020abdb2010-04-19 13:13:06 +0800468#undef AUD_RID
469#undef AUD_VID_DID
470#undef AUD_PWRST
471#undef AUD_OUT_CH_STR
472#undef AUD_HDMIW_STATUS
473
474/*
475 * IronLake registers
476 */
477#define AUD_CONFIG_A 0xE2000
478#define AUD_CONFIG_B 0xE2100
479#define AUD_CTS_ENABLE_A 0xE2028
480#define AUD_CTS_ENABLE_B 0xE2128
481#define AUD_MISC_CTRL_A 0xE2010
482#define AUD_MISC_CTRL_B 0xE2110
483#define AUD_VID_DID 0xE2020
484#define AUD_RID 0xE2024
485#define AUD_PWRST 0xE204C
486#define AUD_PORT_EN_HD_CFG 0xE207C
487#define AUD_OUT_DIG_CNVT_A 0xE2080
488#define AUD_OUT_DIG_CNVT_B 0xE2180
489#define AUD_OUT_CH_STR 0xE2088
490#define AUD_OUT_STR_DESC_A 0xE2084
491#define AUD_OUT_STR_DESC_B 0xE2184
492#define AUD_PINW_CONNLNG_LIST 0xE20A8
493#define AUD_PINW_CONNLNG_SEL 0xE20AC
494#define AUD_CNTL_ST_A 0xE20B4
495#define AUD_CNTL_ST_B 0xE21B4
496#define AUD_CNTL_ST2 0xE20C0
497#define AUD_HDMIW_STATUS 0xE20D4
498#define AUD_HDMIW_HDMIEDID_A 0xE2050
499#define AUD_HDMIW_HDMIEDID_B 0xE2150
500#define AUD_HDMIW_INFOFR_A 0xE2054
501#define AUD_HDMIW_INFOFR_B 0xE2154
502
503static void dump_ironlake(void)
504{
505 uint32_t dword;
506 int i;
507
508 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
509 dump_reg(HDMIC, "HDMI Port C Control");
510 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800511 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
512 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
513 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
514 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800515 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
516 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
517 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
518 dump_reg(AUD_RID, "Audio Revision ID");
519 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
520 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800521 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
522 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800523 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800524 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
525 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800526 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
527 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800528 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
529 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800530 dump_reg(AUD_CNTL_ST2, "Audio Control State 2");
531 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800532 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
533 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
534 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
535 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800536
537 printf("\nDetails:\n\n");
538
539 dword = INREG(AUD_VID_DID);
540 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
541 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
542
543 dword = INREG(AUD_RID);
544 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
545 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
546 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
547 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
548
549 dword = INREG(HDMIB);
550 printf("HDMIB HDMIB_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
551 printf("HDMIB Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
552 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800553 printf("HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800554 printf("HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
555 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
556
557 dword = INREG(HDMIC);
558 printf("HDMIC HDMIC_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
559 printf("HDMIC Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
560 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800561 printf("HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800562 printf("HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
563 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
564
565 dword = INREG(HDMID);
566 printf("HDMID HDMID_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
567 printf("HDMID Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
568 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
569 printf("HDMID Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
570 printf("HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
571 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
572
573 dword = INREG(AUD_CONFIG_A);
574 printf("AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
575 OPNAME(pixel_clock, BITS(dword, 19, 16)));
576 dword = INREG(AUD_CONFIG_B);
577 printf("AUD_CONFIG_B Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
578 OPNAME(pixel_clock, BITS(dword, 19, 16)));
579
580 dword = INREG(AUD_CTS_ENABLE_A);
581 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
582 printf("AUD_CTS_ENABLE_A CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
583 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
584 dword = INREG(AUD_CTS_ENABLE_B);
585 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
586 printf("AUD_CTS_ENABLE_B CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
587 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
588
589 dword = INREG(AUD_MISC_CTRL_A);
590 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
591 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
592 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
593 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
594 dword = INREG(AUD_MISC_CTRL_B);
595 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
596 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
597 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
598 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
599
600 dword = INREG(AUD_PWRST);
601 printf("AUD_PWRST Function_Group_Device_Power_State_Current\t%s\n", power_state[BITS(dword, 23, 22)]);
602 printf("AUD_PWRST Function_Group_Device_Power_State_Set \t%s\n", power_state[BITS(dword, 21, 20)]);
603 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
604 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
605 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
606 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
607 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
608 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
609 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
610 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
611 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
612 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
613
614 dword = INREG(AUD_PORT_EN_HD_CFG);
615 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
616 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
617 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
618 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
619 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12));
620 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13));
621 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14));
622 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16));
623 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17));
624 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18));
625
626 dword = INREG(AUD_OUT_DIG_CNVT_A);
627 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
628 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
629 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
630 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800631 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800632 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
633 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
634 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
635 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800636 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800637
638 dword = INREG(AUD_OUT_DIG_CNVT_B);
639 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
640 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
641 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
642 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800643 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800644 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
645 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
646 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
647 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800648 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800649
650 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
651 for (i = 0; i < 8; i++) {
652 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
653 dword = INREG(AUD_OUT_CH_STR);
654 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
655 1 + BITS(dword, 3, 0),
656 1 + BITS(dword, 7, 4),
657 1 + BITS(dword, 15, 12),
658 1 + BITS(dword, 23, 20));
659 }
660
661 dword = INREG(AUD_OUT_STR_DESC_A);
662 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800663 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800664 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
665 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800666 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
667
668 dword = INREG(AUD_OUT_STR_DESC_B);
669 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800670 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800671 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
672 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800673 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
674
675 dword = INREG(AUD_PINW_CONNLNG_SEL);
676 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
677 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
678 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
679
680 dword = INREG(AUD_CNTL_ST_A);
681 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
682 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
683 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800684 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800685 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
686 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
687 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
688 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
689 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
690
691 dword = INREG(AUD_CNTL_ST_B);
692 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
693 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
694 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800695 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800696 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
697 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
698 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
699 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
700 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
701
702 dword = INREG(AUD_CNTL_ST2);
703 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1));
704 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
705 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5));
706 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
707 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9));
708 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
709
710 dword = INREG(AUD_HDMIW_STATUS);
711 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
712 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
713 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
714 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
715 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
716 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 29));
717
718 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
719 dword = INREG(AUD_CNTL_ST_A);
720 dword &= ~BITMASK(9, 5);
721 OUTREG(AUD_CNTL_ST_A, dword);
722 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
723 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
724 printf("\n");
725
726 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
727 dword = INREG(AUD_CNTL_ST_B);
728 dword &= ~BITMASK(9, 5);
729 OUTREG(AUD_CNTL_ST_B, dword);
730 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
731 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
732 printf("\n");
733
734 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
735 dword = INREG(AUD_CNTL_ST_A);
736 dword &= ~BITMASK(20, 18);
737 dword &= ~BITMASK(3, 0);
738 OUTREG(AUD_CNTL_ST_A, dword);
739 for (i = 0; i < 8; i++)
740 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
741 printf("\n");
742
743 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
744 dword = INREG(AUD_CNTL_ST_B);
745 dword &= ~BITMASK(20, 18);
746 dword &= ~BITMASK(3, 0);
747 OUTREG(AUD_CNTL_ST_B, dword);
748 for (i = 0; i < 8; i++)
749 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
750 printf("\n");
751
752}
753
754
755#undef AUD_CONFIG_A
756#undef AUD_MISC_CTRL_A
757#undef AUD_VID_DID
758#undef AUD_RID
759#undef AUD_CTS_ENABLE_A
760#undef AUD_PWRST
761#undef AUD_HDMIW_HDMIEDID_A
762#undef AUD_HDMIW_INFOFR_A
763#undef AUD_PORT_EN_HD_CFG
764#undef AUD_OUT_DIG_CNVT_A
765#undef AUD_OUT_STR_DESC_A
766#undef AUD_OUT_CH_STR
767#undef AUD_PINW_CONNLNG_LIST
768#undef AUD_CNTL_ST_A
769#undef AUD_HDMIW_STATUS
770#undef AUD_CONFIG_B
771#undef AUD_MISC_CTRL_B
772#undef AUD_CTS_ENABLE_B
773#undef AUD_HDMIW_HDMIEDID_B
774#undef AUD_HDMIW_INFOFR_B
775#undef AUD_OUT_DIG_CNVT_B
776#undef AUD_OUT_STR_DESC_B
777#undef AUD_CNTL_ST_B
778
779/*
780 * CougarPoint registers
781 */
Wu Fengguang97d20312011-11-12 11:12:45 +0800782#define DP_CTL_B 0xE4100
Wu Fengguang020abdb2010-04-19 13:13:06 +0800783#define DP_CTL_C 0xE4200
784#define DP_AUX_CTL_C 0xE4210
785#define DP_AUX_TST_C 0xE4228
786#define SPORT_DDI_CRC_C 0xE4250
787#define SPORT_DDI_CRC_R 0xE4264
788#define DP_CTL_D 0xE4300
789#define DP_AUX_CTL_D 0xE4310
790#define DP_AUX_TST_D 0xE4328
791#define SPORT_DDI_CRC_CTL_D 0xE4350
792#define AUD_CONFIG_A 0xE5000
793#define AUD_MISC_CTRL_A 0xE5010
794#define AUD_VID_DID 0xE5020
795#define AUD_RID 0xE5024
796#define AUD_CTS_ENABLE_A 0xE5028
797#define AUD_PWRST 0xE504C
798#define AUD_HDMIW_HDMIEDID_A 0xE5050
799#define AUD_HDMIW_INFOFR_A 0xE5054
800#define AUD_PORT_EN_HD_CFG 0xE507C
801#define AUD_OUT_DIG_CNVT_A 0xE5080
802#define AUD_OUT_STR_DESC_A 0xE5084
803#define AUD_OUT_CH_STR 0xE5088
804#define AUD_PINW_CONNLNG_LIST 0xE50A8
805#define AUD_PINW_CONNLNG_SELA 0xE50AC
806#define AUD_CNTL_ST_A 0xE50B4
807#define AUD_CNTRL_ST2 0xE50C0
808#define AUD_CNTRL_ST3 0xE50C4
809#define AUD_HDMIW_STATUS 0xE50D4
810#define AUD_CONFIG_B 0xE5100
811#define AUD_MISC_CTRL_B 0xE5110
812#define AUD_CTS_ENABLE_B 0xE5128
813#define AUD_HDMIW_HDMIEDID_B 0xE5150
814#define AUD_HDMIW_INFOFR_B 0xE5154
815#define AUD_OUT_DIG_CNVT_B 0xE5180
816#define AUD_OUT_STR_DESC_B 0xE5184
817#define AUD_CNTL_ST_B 0xE51B4
818#define AUD_CONFIG_C 0xE5200
819#define AUD_MISC_CTRL_C 0xE5210
820#define AUD_CTS_ENABLE_C 0xE5228
821#define AUD_HDMIW_HDMIEDID_C 0xE5250
822#define AUD_HDMIW_INFOFR_C 0xE5254
823#define AUD_OUT_DIG_CNVT_C 0xE5280
824#define AUD_OUT_STR_DESC_C 0xE5284
825#define AUD_CNTL_ST_C 0xE52B4
826#define AUD_CONFIG_D 0xE5300
827#define AUD_MISC_CTRL_D 0xE5310
828#define AUD_CTS_ENABLE_D 0xE5328
829#define AUD_HDMIW_HDMIEDID_D 0xE5350
830#define AUD_HDMIW_INFOFR_D 0xE5354
831#define AUD_OUT_DIG_CNVT_D 0xE5380
832#define AUD_OUT_STR_DESC_D 0xE5384
833#define AUD_CNTL_ST_D 0xE53B4
834
835
836static void dump_cpt(void)
837{
838 uint32_t dword;
839 int i;
840
841 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
842 dump_reg(HDMIC, "HDMI Port C Control");
843 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguang97d20312011-11-12 11:12:45 +0800844 dump_reg(DP_CTL_B, "DisplayPort B Control");
845 dump_reg(DP_CTL_C, "DisplayPort C Control");
846 dump_reg(DP_CTL_D, "DisplayPort D Control");
847 dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control");
848 dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control");
849 dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800850 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
851 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
852 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
853 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
854 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
855 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800856 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
857 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
858 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
859 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
860 dump_reg(AUD_RID, "Audio Revision ID");
861 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
862 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800863 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
864 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
865 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800866 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800867 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
868 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
869 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800870 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
871 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800872 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
873 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
874 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800875 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
876 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
877 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800878 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
879 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
880 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
881 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
882 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
883 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800884
885 printf("\nDetails:\n\n");
886
887 dword = INREG(AUD_VID_DID);
888 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
889 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
890
891 dword = INREG(AUD_RID);
892 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
893 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
894 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
895 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
896
897 dword = INREG(HDMIB);
898 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
899 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
900 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
901 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
902 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
903 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
904 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
905 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
906
907 dword = INREG(HDMIC);
908 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
909 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
910 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
911 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
912 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
913 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
914 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
915 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
916
917 dword = INREG(HDMID);
918 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
919 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
920 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
921 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
922 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
923 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
924 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
925 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
926
Wu Fengguang97d20312011-11-12 11:12:45 +0800927 dword = INREG(DP_CTL_B);
928 printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
929 printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800930 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800931 printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
932 printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
933 printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800934
Wu Fengguang97d20312011-11-12 11:12:45 +0800935 dword = INREG(DP_CTL_C);
936 printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
937 printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800938 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800939 printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
940 printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
941 printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800942
Wu Fengguang97d20312011-11-12 11:12:45 +0800943 dword = INREG(DP_CTL_D);
944 printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
945 printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800946 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800947 printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
948 printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
949 printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800950
951 dword = INREG(AUD_CONFIG_A);
952 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
953 OPNAME(pixel_clock, BITS(dword, 19, 16)));
954 dword = INREG(AUD_CONFIG_B);
955 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
956 OPNAME(pixel_clock, BITS(dword, 19, 16)));
957 dword = INREG(AUD_CONFIG_C);
958 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
959 OPNAME(pixel_clock, BITS(dword, 19, 16)));
960
961 dword = INREG(AUD_CTS_ENABLE_A);
962 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
963 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
964 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
965 dword = INREG(AUD_CTS_ENABLE_B);
966 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
967 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
968 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
969 dword = INREG(AUD_CTS_ENABLE_C);
970 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
971 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
972 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
973
974 dword = INREG(AUD_MISC_CTRL_A);
975 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
976 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
977 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
978 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
979 dword = INREG(AUD_MISC_CTRL_B);
980 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
981 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
982 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
983 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
984 dword = INREG(AUD_MISC_CTRL_C);
985 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
986 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
987 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
988 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
989
990 dword = INREG(AUD_PWRST);
991 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
992 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
993 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
994 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
995 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
996 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
997 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
998 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
999 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
1000 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
1001 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
1002 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
1003 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
1004 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
1005
1006 dword = INREG(AUD_PORT_EN_HD_CFG);
1007 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
1008 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
1009 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
1010 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
1011 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
1012 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
1013 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
1014 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
1015 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
1016 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
1017 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
1018 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
1019
1020 dword = INREG(AUD_OUT_DIG_CNVT_A);
1021 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1022 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1023 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1024 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001025 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001026 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1027 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1028 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1029 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1030 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1031
1032 dword = INREG(AUD_OUT_DIG_CNVT_B);
1033 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1034 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1035 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1036 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001037 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001038 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1039 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1040 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1041 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1042 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1043
1044 dword = INREG(AUD_OUT_DIG_CNVT_C);
1045 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1046 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1047 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1048 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001049 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001050 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1051 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1052 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1053 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1054 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1055
1056 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1057 for (i = 0; i < 8; i++) {
1058 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1059 dword = INREG(AUD_OUT_CH_STR);
1060 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1061 1 + BITS(dword, 3, 0),
1062 1 + BITS(dword, 7, 4),
1063 1 + BITS(dword, 15, 12),
1064 1 + BITS(dword, 23, 20));
1065 }
1066
1067 dword = INREG(AUD_OUT_STR_DESC_A);
1068 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001069 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001070 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
1071 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001072 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1073
1074 dword = INREG(AUD_OUT_STR_DESC_B);
1075 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001076 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001077 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
1078 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001079 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1080
1081 dword = INREG(AUD_OUT_STR_DESC_C);
1082 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001083 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001084 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
1085 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001086 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1087
1088 dword = INREG(AUD_PINW_CONNLNG_SEL);
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001089 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
1090 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
1091 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001092
1093 dword = INREG(AUD_CNTL_ST_A);
1094 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1095 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001096 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1097 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001098 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1099 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1100 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1101 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1102 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1103
1104 dword = INREG(AUD_CNTL_ST_B);
1105 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1106 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001107 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1108 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001109 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1110 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1111 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1112 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1113 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1114
1115 dword = INREG(AUD_CNTL_ST_C);
1116 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1117 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001118 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1119 printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001120 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1121 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1122 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1123 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1124 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1125
1126 dword = INREG(AUD_CNTRL_ST2);
1127 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1128 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1129 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1130 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1131 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1132 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
1133
1134 dword = INREG(AUD_CNTRL_ST3);
1135 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3));
1136 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1137 BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]);
1138 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7));
1139 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1140 BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]);
1141 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11));
1142 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1143 BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]);
1144
1145 dword = INREG(AUD_HDMIW_STATUS);
1146 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1147 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1148 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1149 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1150 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1151 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1152 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1153 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
1154
1155 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1156 dword = INREG(AUD_CNTL_ST_A);
1157 dword &= ~BITMASK(9, 5);
1158 OUTREG(AUD_CNTL_ST_A, dword);
1159 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1160 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1161 printf("\n");
1162
1163 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1164 dword = INREG(AUD_CNTL_ST_B);
1165 dword &= ~BITMASK(9, 5);
1166 OUTREG(AUD_CNTL_ST_B, dword);
1167 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1168 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1169 printf("\n");
1170
1171 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1172 dword = INREG(AUD_CNTL_ST_C);
1173 dword &= ~BITMASK(9, 5);
1174 OUTREG(AUD_CNTL_ST_C, dword);
1175 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1176 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1177 printf("\n");
1178
1179 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1180 dword = INREG(AUD_CNTL_ST_A);
1181 dword &= ~BITMASK(20, 18);
1182 dword &= ~BITMASK(3, 0);
1183 OUTREG(AUD_CNTL_ST_A, dword);
1184 for (i = 0; i < 8; i++)
1185 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1186 printf("\n");
1187
1188 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1189 dword = INREG(AUD_CNTL_ST_B);
1190 dword &= ~BITMASK(20, 18);
1191 dword &= ~BITMASK(3, 0);
1192 OUTREG(AUD_CNTL_ST_B, dword);
1193 for (i = 0; i < 8; i++)
1194 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1195 printf("\n");
1196
1197 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1198 dword = INREG(AUD_CNTL_ST_C);
1199 dword &= ~BITMASK(20, 18);
1200 dword &= ~BITMASK(3, 0);
1201 OUTREG(AUD_CNTL_ST_C, dword);
1202 for (i = 0; i < 8; i++)
1203 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1204 printf("\n");
1205
1206}
1207
1208int main(int argc, char **argv)
1209{
1210 struct pci_device *pci_dev;
1211
1212 pci_dev = intel_get_pci_device();
1213 devid = pci_dev->device_id; /* XXX not true when mapping! */
1214
1215 do_self_tests();
1216
1217 if (argc == 2)
1218 intel_map_file(argv[1]);
1219 else
1220 intel_get_mmio(pci_dev);
1221
Wu Fengguang63e3c372011-11-12 11:12:44 +08001222 if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
Wu Fengguang020abdb2010-04-19 13:13:06 +08001223 intel_check_pch();
1224 dump_cpt();
Chris Wilson3c5c8ba2011-02-01 13:35:36 +00001225 } else if (IS_GEN5(devid))
Wu Fengguang020abdb2010-04-19 13:13:06 +08001226 dump_ironlake();
1227 else
1228 dump_eaglelake();
1229
1230 return 0;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001231}