Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 3, |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 28 | SDTCisVT<3, i8>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 30 | def SDTX86BrCond : SDTypeProfile<0, 2, |
| 31 | [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 32 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 33 | def SDTX86SetCC : SDTypeProfile<1, 1, |
| 34 | [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 35 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 36 | def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 37 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 38 | def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; |
| 39 | def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>, |
| 40 | SDTCisVT<1, i32> ]>; |
| 41 | |
| 42 | def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; |
| 43 | |
| 44 | def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>; |
| 45 | def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>; |
| 46 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 47 | def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 48 | SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 49 | def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, |
| 50 | SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 51 | def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>, |
| 52 | SDTCisVT<2, OtherVT>]>; |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 53 | def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 54 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 55 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 56 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 57 | def SDTX86RdTsc : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 58 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 59 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 60 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 61 | |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 62 | def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, |
| 63 | [SDNPCommutative, SDNPAssociative]>; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 64 | def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, |
| 65 | [SDNPCommutative, SDNPAssociative]>; |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 66 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 67 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, |
| 68 | [SDNPOutFlag]>; |
| 69 | def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, |
| 70 | [SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 71 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 72 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 73 | [SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 74 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 75 | [SDNPHasChain, SDNPInFlag]>; |
Evan Cheng | 5ee4ccc | 2006-01-12 08:27:59 +0000 | [diff] [blame] | 76 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 77 | [SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 78 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 79 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
| 80 | [SDNPHasChain, SDNPOptInFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 81 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 82 | def X86callseq_start : |
| 83 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
| 84 | [SDNPHasChain]>; |
| 85 | def X86callseq_end : |
| 86 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Chris Lattner | af63bb0 | 2006-01-24 05:17:12 +0000 | [diff] [blame] | 87 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 88 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 89 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
| 90 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 91 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 92 | def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet, |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 93 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 94 | def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet, |
| 95 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 96 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 97 | def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, |
| 98 | [SDNPHasChain]>; |
| 99 | def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 100 | [SDNPHasChain, SDNPInFlag]>; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 101 | def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, |
Evan Cheng | e3de85b | 2006-02-04 02:20:30 +0000 | [diff] [blame] | 102 | [SDNPHasChain]>; |
| 103 | def X86fildflag: SDNode<"X86ISD::FILD_FLAG",SDTX86Fild, |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 104 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 105 | def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, |
| 106 | [SDNPHasChain]>; |
| 107 | def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, |
| 108 | [SDNPHasChain]>; |
| 109 | def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, |
| 110 | [SDNPHasChain]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 111 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 112 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
| 113 | [SDNPHasChain, SDNPInFlag]>; |
| 114 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
| 115 | [SDNPHasChain, SDNPInFlag]>; |
| 116 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 117 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc, |
| 118 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 119 | |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 120 | def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, |
| 121 | [SDNPHasChain]>; |
| 122 | |
Evan Cheng | a0ea053 | 2006-02-23 02:43:52 +0000 | [diff] [blame] | 123 | def X86TGAWrapper : SDNode<"X86ISD::TGAWrapper", SDTIntUnaryOp>; |
| 124 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 125 | //===----------------------------------------------------------------------===// |
| 126 | // X86 Operand Definitions. |
| 127 | // |
| 128 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 129 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 130 | // |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 131 | class X86MemOperand<string printMethod> : Operand<i32> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 132 | let PrintMethod = printMethod; |
Chris Lattner | 6adaf79 | 2005-11-19 07:01:30 +0000 | [diff] [blame] | 133 | let NumMIOperands = 4; |
| 134 | let MIOperandInfo = (ops R32, i8imm, R32, i32imm); |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 135 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 136 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 137 | def i8mem : X86MemOperand<"printi8mem">; |
| 138 | def i16mem : X86MemOperand<"printi16mem">; |
| 139 | def i32mem : X86MemOperand<"printi32mem">; |
| 140 | def i64mem : X86MemOperand<"printi64mem">; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 141 | def i128mem : X86MemOperand<"printi128mem">; |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 142 | def f32mem : X86MemOperand<"printf32mem">; |
| 143 | def f64mem : X86MemOperand<"printf64mem">; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 144 | def f128mem : X86MemOperand<"printf128mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 145 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 146 | def SSECC : Operand<i8> { |
| 147 | let PrintMethod = "printSSECC"; |
| 148 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 149 | |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 150 | def piclabel: Operand<i32> { |
| 151 | let PrintMethod = "printPICLabel"; |
| 152 | } |
| 153 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 154 | // A couple of more descriptive operand definitions. |
| 155 | // 16-bits but only 8 bits are significant. |
| 156 | def i16i8imm : Operand<i16>; |
| 157 | // 32-bits but only 8 bits are significant. |
| 158 | def i32i8imm : Operand<i32>; |
| 159 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 160 | // Branch targets have OtherVT type. |
| 161 | def brtarget : Operand<OtherVT>; |
| 162 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 163 | //===----------------------------------------------------------------------===// |
| 164 | // X86 Complex Pattern Definitions. |
| 165 | // |
| 166 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 167 | // Define X86 specific addressing mode. |
Evan Cheng | 670fd8f | 2005-12-08 02:15:07 +0000 | [diff] [blame] | 168 | def addr : ComplexPattern<i32, 4, "SelectAddr", []>; |
Evan Cheng | 502c5bb | 2005-12-15 08:31:04 +0000 | [diff] [blame] | 169 | def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr", |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 170 | [add, frameindex, constpool]>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 171 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 172 | //===----------------------------------------------------------------------===// |
| 173 | // X86 Instruction Format Definitions. |
| 174 | // |
| 175 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 176 | // Format specifies the encoding used by the instruction. This is part of the |
| 177 | // ad-hoc solution used to emit machine instruction encodings by our machine |
| 178 | // code emitter. |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 179 | class Format<bits<6> val> { |
| 180 | bits<6> Value = val; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | def Pseudo : Format<0>; def RawFrm : Format<1>; |
| 184 | def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; |
| 185 | def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; |
| 186 | def MRMSrcMem : Format<6>; |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 187 | def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; |
| 188 | def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; |
| 189 | def MRM6r : Format<22>; def MRM7r : Format<23>; |
| 190 | def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; |
| 191 | def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; |
| 192 | def MRM6m : Format<30>; def MRM7m : Format<31>; |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 193 | def MRMInitReg : Format<32>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 194 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 195 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 196 | // X86 Instruction Predicate Definitions. |
Evan Cheng | ffcb95b | 2006-02-21 19:13:53 +0000 | [diff] [blame] | 197 | def HasMMX : Predicate<"Subtarget->hasMMX()">; |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 198 | def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; |
Evan Cheng | 559806f | 2006-01-27 08:10:46 +0000 | [diff] [blame] | 199 | def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; |
| 200 | def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; |
| 201 | def FPStack : Predicate<"!Subtarget->hasSSE2()">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 202 | |
| 203 | //===----------------------------------------------------------------------===// |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 204 | // X86 specific pattern fragments. |
| 205 | // |
| 206 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 207 | // ImmType - This specifies the immediate type used by an instruction. This is |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 208 | // part of the ad-hoc solution used to emit machine instruction encodings by our |
| 209 | // machine code emitter. |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 210 | class ImmType<bits<2> val> { |
| 211 | bits<2> Value = val; |
| 212 | } |
| 213 | def NoImm : ImmType<0>; |
| 214 | def Imm8 : ImmType<1>; |
| 215 | def Imm16 : ImmType<2>; |
| 216 | def Imm32 : ImmType<3>; |
| 217 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 218 | // FPFormat - This specifies what form this FP instruction has. This is used by |
| 219 | // the Floating-Point stackifier pass. |
| 220 | class FPFormat<bits<3> val> { |
| 221 | bits<3> Value = val; |
| 222 | } |
| 223 | def NotFP : FPFormat<0>; |
| 224 | def ZeroArgFP : FPFormat<1>; |
| 225 | def OneArgFP : FPFormat<2>; |
| 226 | def OneArgFPRW : FPFormat<3>; |
| 227 | def TwoArgFP : FPFormat<4>; |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 228 | def CompareFP : FPFormat<5>; |
| 229 | def CondMovFP : FPFormat<6>; |
| 230 | def SpecialFP : FPFormat<7>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 231 | |
| 232 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 233 | class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> |
| 234 | : Instruction { |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 235 | let Namespace = "X86"; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 236 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 237 | bits<8> Opcode = opcod; |
| 238 | Format Form = f; |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 239 | bits<6> FormBits = Form.Value; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 240 | ImmType ImmT = i; |
| 241 | bits<2> ImmTypeBits = ImmT.Value; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 242 | |
Chris Lattner | c96bb81 | 2004-08-11 07:12:04 +0000 | [diff] [blame] | 243 | dag OperandList = ops; |
| 244 | string AsmString = AsmStr; |
| 245 | |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 246 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 247 | // Attributes specific to X86 instructions... |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 248 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 249 | bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 250 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 251 | bits<4> Prefix = 0; // Which prefix byte does this inst have? |
| 252 | FPFormat FPForm; // What flavor of FP instruction is this? |
| 253 | bits<3> FPFormBits = 0; |
| 254 | } |
| 255 | |
| 256 | class Imp<list<Register> uses, list<Register> defs> { |
| 257 | list<Register> Uses = uses; |
| 258 | list<Register> Defs = defs; |
| 259 | } |
| 260 | |
| 261 | |
| 262 | // Prefix byte classes which are used to indicate to the ad-hoc machine code |
| 263 | // emitter that various prefix bytes are required. |
| 264 | class OpSize { bit hasOpSizePrefix = 1; } |
| 265 | class TB { bits<4> Prefix = 1; } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 266 | class REP { bits<4> Prefix = 2; } |
| 267 | class D8 { bits<4> Prefix = 3; } |
| 268 | class D9 { bits<4> Prefix = 4; } |
| 269 | class DA { bits<4> Prefix = 5; } |
| 270 | class DB { bits<4> Prefix = 6; } |
| 271 | class DC { bits<4> Prefix = 7; } |
| 272 | class DD { bits<4> Prefix = 8; } |
| 273 | class DE { bits<4> Prefix = 9; } |
| 274 | class DF { bits<4> Prefix = 10; } |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 275 | class XD { bits<4> Prefix = 11; } |
| 276 | class XS { bits<4> Prefix = 12; } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 277 | |
| 278 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 279 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 280 | // Pattern fragments... |
| 281 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 282 | |
| 283 | // X86 specific condition code. These correspond to CondCode in |
| 284 | // X86ISelLowering.h. They must be kept in synch. |
| 285 | def X86_COND_A : PatLeaf<(i8 0)>; |
| 286 | def X86_COND_AE : PatLeaf<(i8 1)>; |
| 287 | def X86_COND_B : PatLeaf<(i8 2)>; |
| 288 | def X86_COND_BE : PatLeaf<(i8 3)>; |
| 289 | def X86_COND_E : PatLeaf<(i8 4)>; |
| 290 | def X86_COND_G : PatLeaf<(i8 5)>; |
| 291 | def X86_COND_GE : PatLeaf<(i8 6)>; |
| 292 | def X86_COND_L : PatLeaf<(i8 7)>; |
| 293 | def X86_COND_LE : PatLeaf<(i8 8)>; |
| 294 | def X86_COND_NE : PatLeaf<(i8 9)>; |
| 295 | def X86_COND_NO : PatLeaf<(i8 10)>; |
| 296 | def X86_COND_NP : PatLeaf<(i8 11)>; |
| 297 | def X86_COND_NS : PatLeaf<(i8 12)>; |
| 298 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 299 | def X86_COND_P : PatLeaf<(i8 14)>; |
| 300 | def X86_COND_S : PatLeaf<(i8 15)>; |
| 301 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 302 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 303 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 304 | // sign extended field. |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 305 | return (int)N->getValue() == (signed char)N->getValue(); |
| 306 | }]>; |
| 307 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 308 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 309 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 310 | // sign extended field. |
| 311 | return (int)N->getValue() == (signed char)N->getValue(); |
| 312 | }]>; |
| 313 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 314 | def i16immZExt8 : PatLeaf<(i16 imm), [{ |
| 315 | // i16immZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 316 | // extended field. |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 317 | return (unsigned)N->getValue() == (unsigned char)N->getValue(); |
| 318 | }]>; |
| 319 | |
Evan Cheng | 650d688 | 2006-01-05 02:08:37 +0000 | [diff] [blame] | 320 | def fp32imm0 : PatLeaf<(f32 fpimm), [{ |
| 321 | return N->isExactlyValue(+0.0); |
| 322 | }]>; |
| 323 | |
| 324 | def fp64imm0 : PatLeaf<(f64 fpimm), [{ |
| 325 | return N->isExactlyValue(+0.0); |
| 326 | }]>; |
| 327 | |
| 328 | def fp64immneg0 : PatLeaf<(f64 fpimm), [{ |
| 329 | return N->isExactlyValue(-0.0); |
| 330 | }]>; |
| 331 | |
| 332 | def fp64imm1 : PatLeaf<(f64 fpimm), [{ |
| 333 | return N->isExactlyValue(+1.0); |
| 334 | }]>; |
| 335 | |
| 336 | def fp64immneg1 : PatLeaf<(f64 fpimm), [{ |
| 337 | return N->isExactlyValue(-1.0); |
| 338 | }]>; |
| 339 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 340 | // Helper fragments for loads. |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 341 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
| 342 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>; |
| 343 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 344 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; |
| 345 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 346 | |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 347 | def X86loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; |
| 348 | def X86loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; |
| 349 | |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 350 | def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>; |
| 351 | def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>; |
| 352 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>; |
| 353 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>; |
| 354 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>; |
| 355 | |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 356 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextload node:$ptr, i1))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 357 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>; |
| 358 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>; |
| 359 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>; |
| 360 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>; |
| 361 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>; |
| 362 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 363 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>; |
| 364 | def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>; |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 365 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 366 | def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>; |
| 367 | def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>; |
| 368 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 369 | //===----------------------------------------------------------------------===// |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 370 | // Instruction templates... |
| 371 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 372 | class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 373 | : X86Inst<o, f, NoImm, ops, asm> { |
| 374 | let Pattern = pattern; |
| 375 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 376 | class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 377 | : X86Inst<o, f, Imm8 , ops, asm> { |
| 378 | let Pattern = pattern; |
| 379 | } |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 380 | class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 381 | : X86Inst<o, f, Imm16, ops, asm> { |
| 382 | let Pattern = pattern; |
| 383 | } |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 384 | class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 385 | : X86Inst<o, f, Imm32, ops, asm> { |
| 386 | let Pattern = pattern; |
| 387 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 388 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 389 | //===----------------------------------------------------------------------===// |
| 390 | // Instruction list... |
| 391 | // |
| 392 | |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 393 | def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 394 | [(X86callseq_start imm:$amt)]>; |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 395 | def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2), |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 396 | "#ADJCALLSTACKUP", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 397 | [(X86callseq_end imm:$amt1, imm:$amt2)]>; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 398 | def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>; |
| 399 | def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 400 | def IMPLICIT_DEF_R8 : I<0, Pseudo, (ops R8:$dst), |
| 401 | "#IMPLICIT_DEF $dst", |
| 402 | [(set R8:$dst, (undef))]>; |
| 403 | def IMPLICIT_DEF_R16 : I<0, Pseudo, (ops R16:$dst), |
| 404 | "#IMPLICIT_DEF $dst", |
| 405 | [(set R16:$dst, (undef))]>; |
| 406 | def IMPLICIT_DEF_R32 : I<0, Pseudo, (ops R32:$dst), |
| 407 | "#IMPLICIT_DEF $dst", |
| 408 | [(set R32:$dst, (undef))]>; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 409 | |
| 410 | // Nop |
| 411 | def NOOP : I<0x90, RawFrm, (ops), "nop", []>; |
| 412 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 413 | //===----------------------------------------------------------------------===// |
| 414 | // Control Flow Instructions... |
| 415 | // |
| 416 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 417 | // Return instructions. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 418 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
| 419 | hasCtrlDep = 1, noResults = 1 in { |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 420 | def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>; |
| 421 | def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", |
| 422 | [(X86retflag imm:$amt)]>; |
Evan Cheng | 171049d | 2005-12-23 22:14:32 +0000 | [diff] [blame] | 423 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 424 | |
| 425 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 426 | let isBranch = 1, isTerminator = 1, noResults = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 427 | class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> : |
| 428 | I<opcode, RawFrm, ops, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 429 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 430 | // Conditional branches |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 431 | let isBarrier = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 432 | def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 433 | |
| 434 | def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 435 | [(X86brcond bb:$dst, X86_COND_E)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 436 | def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 437 | [(X86brcond bb:$dst, X86_COND_NE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 438 | def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 439 | [(X86brcond bb:$dst, X86_COND_L)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 440 | def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 441 | [(X86brcond bb:$dst, X86_COND_LE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 442 | def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 443 | [(X86brcond bb:$dst, X86_COND_G)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 444 | def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 445 | [(X86brcond bb:$dst, X86_COND_GE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 446 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 447 | def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 448 | [(X86brcond bb:$dst, X86_COND_B)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 449 | def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 450 | [(X86brcond bb:$dst, X86_COND_BE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 451 | def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 452 | [(X86brcond bb:$dst, X86_COND_A)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 453 | def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 454 | [(X86brcond bb:$dst, X86_COND_AE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 455 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 456 | def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 457 | [(X86brcond bb:$dst, X86_COND_S)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 458 | def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 459 | [(X86brcond bb:$dst, X86_COND_NS)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 460 | def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 461 | [(X86brcond bb:$dst, X86_COND_P)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 462 | def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 463 | [(X86brcond bb:$dst, X86_COND_NP)]>, TB; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 464 | def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 465 | [(X86brcond bb:$dst, X86_COND_O)]>, TB; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 466 | def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 467 | [(X86brcond bb:$dst, X86_COND_NO)]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 468 | |
| 469 | //===----------------------------------------------------------------------===// |
| 470 | // Call Instructions... |
| 471 | // |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 472 | let isCall = 1, noResults = 1 in |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 473 | // All calls clobber the non-callee saved registers... |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 474 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 475 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { |
Chris Lattner | a3b8c57 | 2006-02-06 23:41:19 +0000 | [diff] [blame] | 476 | def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst), "call ${dst:call}", |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 477 | []>; |
| 478 | def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 479 | [(X86call R32:$dst)]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 480 | def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 481 | [(X86call (loadi32 addr:$dst))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 482 | } |
| 483 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 484 | // Tail call stuff. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 485 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Chris Lattner | a3b8c57 | 2006-02-06 23:41:19 +0000 | [diff] [blame] | 486 | def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL", []>; |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 487 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 488 | def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>; |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 489 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 490 | def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), |
| 491 | "jmp {*}$dst # TAIL CALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 492 | |
| 493 | // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every |
| 494 | // way, except that it is marked as being a terminator. This causes the epilog |
| 495 | // inserter to insert reloads of callee saved registers BEFORE this. We need |
| 496 | // this until we have a more accurate way of tracking where the stack pointer is |
| 497 | // within a function. |
| 498 | let isTerminator = 1, isTwoAddress = 1 in |
| 499 | def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 500 | "add{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 501 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 502 | //===----------------------------------------------------------------------===// |
| 503 | // Miscellaneous Instructions... |
| 504 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 505 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 506 | (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 507 | def POP32r : I<0x58, AddRegFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 508 | (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 509 | |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 510 | def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label), |
| 511 | "call $label", []>; |
| 512 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 513 | let isTwoAddress = 1 in // R32 = bswap R32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 514 | def BSWAP32r : I<0xC8, AddRegFrm, |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 515 | (ops R32:$dst, R32:$src), |
| 516 | "bswap{l} $dst", |
| 517 | [(set R32:$dst, (bswap R32:$src))]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 518 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 519 | def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 520 | (ops R8:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 521 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 522 | def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 523 | (ops R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 524 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 525 | def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 526 | (ops R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 527 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 528 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 529 | def XCHG8mr : I<0x86, MRMDestMem, |
| 530 | (ops i8mem:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 531 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 532 | def XCHG16mr : I<0x87, MRMDestMem, |
| 533 | (ops i16mem:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 534 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 535 | def XCHG32mr : I<0x87, MRMDestMem, |
| 536 | (ops i32mem:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 537 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 538 | def XCHG8rm : I<0x86, MRMSrcMem, |
| 539 | (ops R8:$src1, i8mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 540 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 541 | def XCHG16rm : I<0x87, MRMSrcMem, |
| 542 | (ops R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 543 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 544 | def XCHG32rm : I<0x87, MRMSrcMem, |
| 545 | (ops R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 546 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 547 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 548 | def LEA16r : I<0x8D, MRMSrcMem, |
| 549 | (ops R16:$dst, i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 550 | "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 551 | def LEA32r : I<0x8D, MRMSrcMem, |
| 552 | (ops R32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 553 | "lea{l} {$src|$dst}, {$dst|$src}", |
| 554 | [(set R32:$dst, leaaddr:$src)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 555 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 556 | def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", |
| 557 | [(X86rep_movs i8)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 558 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 559 | def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", |
| 560 | [(X86rep_movs i16)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 561 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 562 | def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", |
| 563 | [(X86rep_movs i32)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 564 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 565 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 566 | def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", |
| 567 | [(X86rep_stos i8)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 568 | Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 569 | def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", |
| 570 | [(X86rep_stos i16)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 571 | Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 572 | def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", |
| 573 | [(X86rep_stos i32)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 574 | Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; |
| 575 | |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 576 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 577 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 578 | // Input/Output Instructions... |
| 579 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 580 | def IN8rr : I<0xEC, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 581 | "in{b} {%dx, %al|%AL, %DX}", |
| 582 | [(set AL, (readport DX))]>, Imp<[DX], [AL]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 583 | def IN16rr : I<0xED, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 584 | "in{w} {%dx, %ax|%AX, %DX}", |
| 585 | [(set AX, (readport DX))]>, Imp<[DX], [AX]>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 586 | def IN32rr : I<0xED, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 587 | "in{l} {%dx, %eax|%EAX, %DX}", |
| 588 | [(set EAX, (readport DX))]>, Imp<[DX],[EAX]>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 589 | |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 590 | def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port), |
| 591 | "in{b} {$port, %al|%AL, $port}", |
| 592 | [(set AL, (readport i16immZExt8:$port))]>, |
| 593 | Imp<[], [AL]>; |
| 594 | def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), |
| 595 | "in{w} {$port, %ax|%AX, $port}", |
| 596 | [(set AX, (readport i16immZExt8:$port))]>, |
| 597 | Imp<[], [AX]>, OpSize; |
| 598 | def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), |
| 599 | "in{l} {$port, %eax|%EAX, $port}", |
| 600 | [(set EAX, (readport i16immZExt8:$port))]>, |
| 601 | Imp<[],[EAX]>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 602 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 603 | def OUT8rr : I<0xEE, RawFrm, (ops), |
| 604 | "out{b} {%al, %dx|%DX, %AL}", |
| 605 | [(writeport AL, DX)]>, Imp<[DX, AL], []>; |
| 606 | def OUT16rr : I<0xEF, RawFrm, (ops), |
| 607 | "out{w} {%ax, %dx|%DX, %AX}", |
| 608 | [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize; |
| 609 | def OUT32rr : I<0xEF, RawFrm, (ops), |
| 610 | "out{l} {%eax, %dx|%DX, %EAX}", |
| 611 | [(writeport EAX, DX)]>, Imp<[DX, EAX], []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 612 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 613 | def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port), |
| 614 | "out{b} {%al, $port|$port, %AL}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 615 | [(writeport AL, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 616 | Imp<[AL], []>; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 617 | def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 618 | "out{w} {%ax, $port|$port, %AX}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 619 | [(writeport AX, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 620 | Imp<[AX], []>, OpSize; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 621 | def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 622 | "out{l} {%eax, $port|$port, %EAX}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 623 | [(writeport EAX, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 624 | Imp<[EAX], []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 625 | |
| 626 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 627 | // Move Instructions... |
| 628 | // |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 629 | def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 630 | "mov{b} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 631 | def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 632 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 633 | def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 634 | "mov{l} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 635 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 636 | "mov{b} {$src, $dst|$dst, $src}", |
| 637 | [(set R8:$dst, imm:$src)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 638 | def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 639 | "mov{w} {$src, $dst|$dst, $src}", |
| 640 | [(set R16:$dst, imm:$src)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 641 | def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 642 | "mov{l} {$src, $dst|$dst, $src}", |
| 643 | [(set R32:$dst, imm:$src)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 644 | def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 645 | "mov{b} {$src, $dst|$dst, $src}", |
| 646 | [(store (i8 imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 647 | def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 648 | "mov{w} {$src, $dst|$dst, $src}", |
| 649 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 650 | def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 651 | "mov{l} {$src, $dst|$dst, $src}", |
| 652 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 653 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 654 | def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 655 | "mov{b} {$src, $dst|$dst, $src}", |
| 656 | [(set R8:$dst, (load addr:$src))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 657 | def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 658 | "mov{w} {$src, $dst|$dst, $src}", |
| 659 | [(set R16:$dst, (load addr:$src))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 660 | def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 661 | "mov{l} {$src, $dst|$dst, $src}", |
| 662 | [(set R32:$dst, (load addr:$src))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 663 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 664 | def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 665 | "mov{b} {$src, $dst|$dst, $src}", |
| 666 | [(store R8:$src, addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 667 | def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 668 | "mov{w} {$src, $dst|$dst, $src}", |
| 669 | [(store R16:$src, addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 670 | def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 671 | "mov{l} {$src, $dst|$dst, $src}", |
| 672 | [(store R32:$src, addr:$dst)]>; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 673 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 674 | //===----------------------------------------------------------------------===// |
| 675 | // Fixed-Register Multiplication and Division Instructions... |
| 676 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 677 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 678 | // Extra precision multiplication |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 679 | def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", |
| 680 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 681 | // This probably ought to be moved to a def : Pat<> if the |
| 682 | // syntax can be accepted. |
| 683 | [(set AL, (mul AL, R8:$src))]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 684 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 685 | def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 686 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 687 | def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 688 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 689 | def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 690 | "mul{b} $src", |
| 691 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 692 | // This probably ought to be moved to a def : Pat<> if the |
| 693 | // syntax can be accepted. |
| 694 | [(set AL, (mul AL, (loadi8 addr:$src)))]>, |
| 695 | Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 696 | def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 697 | "mul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 698 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 699 | def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 700 | "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 701 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 702 | def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 703 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 704 | def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 705 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 706 | def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 707 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
| 708 | def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 709 | "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 710 | def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 711 | "imul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 712 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 713 | def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 714 | "imul{l} $src", []>, |
| 715 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 716 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 717 | // unsigned division/remainder |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 718 | def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 719 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 720 | def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 721 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 722 | def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 723 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 724 | def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 725 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 726 | def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 727 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 728 | def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 729 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 730 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 731 | // Signed division/remainder. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 732 | def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 733 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 734 | def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 735 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 736 | def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 737 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 738 | def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 739 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 740 | def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 741 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 742 | def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 743 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 744 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 745 | // Sign-extenders for division. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 746 | def CBW : I<0x98, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 747 | "{cbtw|cbw}", []>, Imp<[AL],[AH]>; // AX = signext(AL) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 748 | def CWD : I<0x99, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 749 | "{cwtd|cwd}", []>, Imp<[AX],[DX]>; // DX:AX = signext(AX) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 750 | def CDQ : I<0x99, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 751 | "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 752 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 753 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 754 | //===----------------------------------------------------------------------===// |
| 755 | // Two address Instructions... |
| 756 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 757 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 758 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 759 | // Conditional moves |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 760 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16 |
| 761 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 762 | "cmovb {$src2, $dst|$dst, $src2}", |
| 763 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 764 | X86_COND_B))]>, |
| 765 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 766 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16] |
| 767 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 768 | "cmovb {$src2, $dst|$dst, $src2}", |
| 769 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 770 | X86_COND_B))]>, |
| 771 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 772 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32 |
| 773 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 774 | "cmovb {$src2, $dst|$dst, $src2}", |
| 775 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 776 | X86_COND_B))]>, |
| 777 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 778 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32] |
| 779 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 780 | "cmovb {$src2, $dst|$dst, $src2}", |
| 781 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 782 | X86_COND_B))]>, |
| 783 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 784 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 785 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 |
| 786 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 787 | "cmovae {$src2, $dst|$dst, $src2}", |
| 788 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 789 | X86_COND_AE))]>, |
| 790 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 791 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] |
| 792 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 793 | "cmovae {$src2, $dst|$dst, $src2}", |
| 794 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 795 | X86_COND_AE))]>, |
| 796 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 797 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 |
| 798 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 799 | "cmovae {$src2, $dst|$dst, $src2}", |
| 800 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 801 | X86_COND_AE))]>, |
| 802 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 803 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] |
| 804 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 805 | "cmovae {$src2, $dst|$dst, $src2}", |
| 806 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 807 | X86_COND_AE))]>, |
| 808 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 809 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 810 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 |
| 811 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 812 | "cmove {$src2, $dst|$dst, $src2}", |
| 813 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 814 | X86_COND_E))]>, |
| 815 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 816 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] |
| 817 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 818 | "cmove {$src2, $dst|$dst, $src2}", |
| 819 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 820 | X86_COND_E))]>, |
| 821 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 822 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 |
| 823 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 824 | "cmove {$src2, $dst|$dst, $src2}", |
| 825 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 826 | X86_COND_E))]>, |
| 827 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 828 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] |
| 829 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 830 | "cmove {$src2, $dst|$dst, $src2}", |
| 831 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 832 | X86_COND_E))]>, |
| 833 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 834 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 835 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 |
| 836 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 837 | "cmovne {$src2, $dst|$dst, $src2}", |
| 838 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 839 | X86_COND_NE))]>, |
| 840 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 841 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] |
| 842 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 843 | "cmovne {$src2, $dst|$dst, $src2}", |
| 844 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 845 | X86_COND_NE))]>, |
| 846 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 847 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 |
| 848 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 849 | "cmovne {$src2, $dst|$dst, $src2}", |
| 850 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 851 | X86_COND_NE))]>, |
| 852 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 853 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] |
| 854 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 855 | "cmovne {$src2, $dst|$dst, $src2}", |
| 856 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 857 | X86_COND_NE))]>, |
| 858 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 859 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 860 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 |
| 861 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 862 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 863 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 864 | X86_COND_BE))]>, |
| 865 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 866 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] |
| 867 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 868 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 869 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 870 | X86_COND_BE))]>, |
| 871 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 872 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 |
| 873 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 874 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 875 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 876 | X86_COND_BE))]>, |
| 877 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 878 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] |
| 879 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 880 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 881 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 882 | X86_COND_BE))]>, |
| 883 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 884 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 885 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 |
| 886 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 887 | "cmova {$src2, $dst|$dst, $src2}", |
| 888 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 889 | X86_COND_A))]>, |
| 890 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 891 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] |
| 892 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 893 | "cmova {$src2, $dst|$dst, $src2}", |
| 894 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 895 | X86_COND_A))]>, |
| 896 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 897 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 |
| 898 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 899 | "cmova {$src2, $dst|$dst, $src2}", |
| 900 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 901 | X86_COND_A))]>, |
| 902 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 903 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] |
| 904 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 905 | "cmova {$src2, $dst|$dst, $src2}", |
| 906 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 907 | X86_COND_A))]>, |
| 908 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 909 | |
| 910 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16 |
| 911 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 912 | "cmovl {$src2, $dst|$dst, $src2}", |
| 913 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 914 | X86_COND_L))]>, |
| 915 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 916 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16] |
| 917 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 918 | "cmovl {$src2, $dst|$dst, $src2}", |
| 919 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 920 | X86_COND_L))]>, |
| 921 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 922 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32 |
| 923 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 924 | "cmovl {$src2, $dst|$dst, $src2}", |
| 925 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 926 | X86_COND_L))]>, |
| 927 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 928 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32] |
| 929 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 930 | "cmovl {$src2, $dst|$dst, $src2}", |
| 931 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 932 | X86_COND_L))]>, |
| 933 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 934 | |
| 935 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 |
| 936 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 937 | "cmovge {$src2, $dst|$dst, $src2}", |
| 938 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 939 | X86_COND_GE))]>, |
| 940 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 941 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] |
| 942 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 943 | "cmovge {$src2, $dst|$dst, $src2}", |
| 944 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 945 | X86_COND_GE))]>, |
| 946 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 947 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 |
| 948 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 949 | "cmovge {$src2, $dst|$dst, $src2}", |
| 950 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 951 | X86_COND_GE))]>, |
| 952 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 953 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] |
| 954 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 955 | "cmovge {$src2, $dst|$dst, $src2}", |
| 956 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 957 | X86_COND_GE))]>, |
| 958 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 959 | |
| 960 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 |
| 961 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 962 | "cmovle {$src2, $dst|$dst, $src2}", |
| 963 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 964 | X86_COND_LE))]>, |
| 965 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 966 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] |
| 967 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 968 | "cmovle {$src2, $dst|$dst, $src2}", |
| 969 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 970 | X86_COND_LE))]>, |
| 971 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 972 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 |
| 973 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 974 | "cmovle {$src2, $dst|$dst, $src2}", |
| 975 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 976 | X86_COND_LE))]>, |
| 977 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 978 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] |
| 979 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 980 | "cmovle {$src2, $dst|$dst, $src2}", |
| 981 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 982 | X86_COND_LE))]>, |
| 983 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 984 | |
| 985 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 |
| 986 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 987 | "cmovg {$src2, $dst|$dst, $src2}", |
| 988 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 989 | X86_COND_G))]>, |
| 990 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 991 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] |
| 992 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 993 | "cmovg {$src2, $dst|$dst, $src2}", |
| 994 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 995 | X86_COND_G))]>, |
| 996 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 997 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 |
| 998 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 999 | "cmovg {$src2, $dst|$dst, $src2}", |
| 1000 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1001 | X86_COND_G))]>, |
| 1002 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1003 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] |
| 1004 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 1005 | "cmovg {$src2, $dst|$dst, $src2}", |
| 1006 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1007 | X86_COND_G))]>, |
| 1008 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 1009 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1010 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 |
| 1011 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1012 | "cmovs {$src2, $dst|$dst, $src2}", |
| 1013 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1014 | X86_COND_S))]>, |
| 1015 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1016 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] |
| 1017 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1018 | "cmovs {$src2, $dst|$dst, $src2}", |
| 1019 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1020 | X86_COND_S))]>, |
| 1021 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1022 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 |
| 1023 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1024 | "cmovs {$src2, $dst|$dst, $src2}", |
| 1025 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1026 | X86_COND_S))]>, |
| 1027 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1028 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] |
| 1029 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1030 | "cmovs {$src2, $dst|$dst, $src2}", |
| 1031 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1032 | X86_COND_S))]>, |
| 1033 | TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1034 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1035 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 |
| 1036 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1037 | "cmovns {$src2, $dst|$dst, $src2}", |
| 1038 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1039 | X86_COND_NS))]>, |
| 1040 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1041 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] |
| 1042 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1043 | "cmovns {$src2, $dst|$dst, $src2}", |
| 1044 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1045 | X86_COND_NS))]>, |
| 1046 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1047 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 |
| 1048 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1049 | "cmovns {$src2, $dst|$dst, $src2}", |
| 1050 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1051 | X86_COND_NS))]>, |
| 1052 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1053 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] |
| 1054 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1055 | "cmovns {$src2, $dst|$dst, $src2}", |
| 1056 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1057 | X86_COND_NS))]>, |
| 1058 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 1059 | |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1060 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16 |
| 1061 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1062 | "cmovp {$src2, $dst|$dst, $src2}", |
| 1063 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1064 | X86_COND_P))]>, |
| 1065 | TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1066 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16] |
| 1067 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1068 | "cmovp {$src2, $dst|$dst, $src2}", |
| 1069 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1070 | X86_COND_P))]>, |
| 1071 | TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1072 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32 |
| 1073 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1074 | "cmovp {$src2, $dst|$dst, $src2}", |
| 1075 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1076 | X86_COND_P))]>, |
| 1077 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1078 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32] |
| 1079 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1080 | "cmovp {$src2, $dst|$dst, $src2}", |
| 1081 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1082 | X86_COND_P))]>, |
| 1083 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1084 | |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1085 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16 |
| 1086 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1087 | "cmovnp {$src2, $dst|$dst, $src2}", |
| 1088 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1089 | X86_COND_NP))]>, |
| 1090 | TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1091 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16] |
| 1092 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1093 | "cmovnp {$src2, $dst|$dst, $src2}", |
| 1094 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1095 | X86_COND_NP))]>, |
| 1096 | TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1097 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32 |
| 1098 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1099 | "cmovnp {$src2, $dst|$dst, $src2}", |
| 1100 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1101 | X86_COND_NP))]>, |
| 1102 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1103 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32] |
| 1104 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1105 | "cmovnp {$src2, $dst|$dst, $src2}", |
| 1106 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1107 | X86_COND_NP))]>, |
| 1108 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1109 | |
| 1110 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1111 | // unary instructions |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1112 | def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst", |
| 1113 | [(set R8:$dst, (ineg R8:$src))]>; |
| 1114 | def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst", |
| 1115 | [(set R16:$dst, (ineg R16:$src))]>, OpSize; |
| 1116 | def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst", |
| 1117 | [(set R32:$dst, (ineg R32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1118 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1119 | def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1120 | [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1121 | def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1122 | [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1123 | def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1124 | [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>; |
| 1125 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1126 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1127 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1128 | def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst", |
| 1129 | [(set R8:$dst, (not R8:$src))]>; |
| 1130 | def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst", |
| 1131 | [(set R16:$dst, (not R16:$src))]>, OpSize; |
| 1132 | def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst", |
| 1133 | [(set R32:$dst, (not R32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1134 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1135 | def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1136 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1137 | def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1138 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1139 | def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1140 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1141 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1142 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1143 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1144 | def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst", |
| 1145 | [(set R8:$dst, (add R8:$src, 1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1146 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1147 | def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst", |
| 1148 | [(set R16:$dst, (add R16:$src, 1))]>, OpSize; |
| 1149 | def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst", |
| 1150 | [(set R32:$dst, (add R32:$src, 1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1151 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1152 | let isTwoAddress = 0 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1153 | def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1154 | [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1155 | def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1156 | [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1157 | def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1158 | [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1159 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1160 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1161 | def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", |
| 1162 | [(set R8:$dst, (add R8:$src, -1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1163 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1164 | def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", |
| 1165 | [(set R16:$dst, (add R16:$src, -1))]>, OpSize; |
| 1166 | def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", |
| 1167 | [(set R32:$dst, (add R32:$src, -1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1168 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1169 | |
| 1170 | let isTwoAddress = 0 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1171 | def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1172 | [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1173 | def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1174 | [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1175 | def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1176 | [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1177 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1178 | |
| 1179 | // Logical operators... |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1180 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1181 | def AND8rr : I<0x20, MRMDestReg, |
| 1182 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1183 | "and{b} {$src2, $dst|$dst, $src2}", |
| 1184 | [(set R8:$dst, (and R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1185 | def AND16rr : I<0x21, MRMDestReg, |
| 1186 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1187 | "and{w} {$src2, $dst|$dst, $src2}", |
| 1188 | [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1189 | def AND32rr : I<0x21, MRMDestReg, |
| 1190 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1191 | "and{l} {$src2, $dst|$dst, $src2}", |
| 1192 | [(set R32:$dst, (and R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1193 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1194 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1195 | def AND8rm : I<0x22, MRMSrcMem, |
| 1196 | (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1197 | "and{b} {$src2, $dst|$dst, $src2}", |
| 1198 | [(set R8:$dst, (and R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1199 | def AND16rm : I<0x23, MRMSrcMem, |
| 1200 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1201 | "and{w} {$src2, $dst|$dst, $src2}", |
| 1202 | [(set R16:$dst, (and R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1203 | def AND32rm : I<0x23, MRMSrcMem, |
| 1204 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1205 | "and{l} {$src2, $dst|$dst, $src2}", |
| 1206 | [(set R32:$dst, (and R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1207 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1208 | def AND8ri : Ii8<0x80, MRM4r, |
| 1209 | (ops R8 :$dst, R8 :$src1, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1210 | "and{b} {$src2, $dst|$dst, $src2}", |
| 1211 | [(set R8:$dst, (and R8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1212 | def AND16ri : Ii16<0x81, MRM4r, |
| 1213 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1214 | "and{w} {$src2, $dst|$dst, $src2}", |
| 1215 | [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1216 | def AND32ri : Ii32<0x81, MRM4r, |
| 1217 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1218 | "and{l} {$src2, $dst|$dst, $src2}", |
| 1219 | [(set R32:$dst, (and R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1220 | def AND16ri8 : Ii8<0x83, MRM4r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1221 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1222 | "and{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1223 | [(set R16:$dst, (and R16:$src1, i16immSExt8:$src2))]>, |
| 1224 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1225 | def AND32ri8 : Ii8<0x83, MRM4r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1226 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1227 | "and{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1228 | [(set R32:$dst, (and R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1229 | |
| 1230 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1231 | def AND8mr : I<0x20, MRMDestMem, |
| 1232 | (ops i8mem :$dst, R8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1233 | "and{b} {$src, $dst|$dst, $src}", |
| 1234 | [(store (and (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1235 | def AND16mr : I<0x21, MRMDestMem, |
| 1236 | (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1237 | "and{w} {$src, $dst|$dst, $src}", |
| 1238 | [(store (and (load addr:$dst), R16:$src), addr:$dst)]>, |
| 1239 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1240 | def AND32mr : I<0x21, MRMDestMem, |
| 1241 | (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1242 | "and{l} {$src, $dst|$dst, $src}", |
| 1243 | [(store (and (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1244 | def AND8mi : Ii8<0x80, MRM4m, |
| 1245 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1246 | "and{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1247 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1248 | def AND16mi : Ii16<0x81, MRM4m, |
| 1249 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1250 | "and{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1251 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1252 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1253 | def AND32mi : Ii32<0x81, MRM4m, |
| 1254 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1255 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1256 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1257 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1258 | (ops i16mem:$dst, i16i8imm :$src), |
| 1259 | "and{w} {$src, $dst|$dst, $src}", |
| 1260 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1261 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1262 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1263 | (ops i32mem:$dst, i32i8imm :$src), |
| 1264 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | e3703d4 | 2006-01-14 01:18:49 +0000 | [diff] [blame] | 1265 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1266 | } |
| 1267 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1268 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1269 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1270 | def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1271 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1272 | [(set R8:$dst, (or R8:$src1, R8:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1273 | def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1274 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1275 | [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1276 | def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1277 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1278 | [(set R32:$dst, (or R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1279 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1280 | def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1281 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1282 | [(set R8:$dst, (or R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1283 | def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1284 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1285 | [(set R16:$dst, (or R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1286 | def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1287 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1288 | [(set R32:$dst, (or R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1289 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1290 | def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1291 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1292 | [(set R8:$dst, (or R8:$src1, imm:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1293 | def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1294 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1295 | [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1296 | def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1297 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1298 | [(set R32:$dst, (or R32:$src1, imm:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1299 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1300 | def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1301 | "or{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1302 | [(set R16:$dst, (or R16:$src1, i16immSExt8:$src2))]>, OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1303 | def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1304 | "or{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1305 | [(set R32:$dst, (or R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1306 | let isTwoAddress = 0 in { |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1307 | def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1308 | "or{b} {$src, $dst|$dst, $src}", |
| 1309 | [(store (or (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1310 | def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1311 | "or{w} {$src, $dst|$dst, $src}", |
| 1312 | [(store (or (load addr:$dst), R16:$src), addr:$dst)]>, OpSize; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1313 | def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1314 | "or{l} {$src, $dst|$dst, $src}", |
| 1315 | [(store (or (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1316 | def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1317 | "or{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1318 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1319 | def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1320 | "or{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1321 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1322 | OpSize; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1323 | def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1324 | "or{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1325 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1326 | def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src), |
| 1327 | "or{w} {$src, $dst|$dst, $src}", |
| 1328 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1329 | OpSize; |
| 1330 | def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src), |
| 1331 | "or{l} {$src, $dst|$dst, $src}", |
| 1332 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1333 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1334 | |
| 1335 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1336 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1337 | def XOR8rr : I<0x30, MRMDestReg, |
| 1338 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1339 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1340 | [(set R8:$dst, (xor R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1341 | def XOR16rr : I<0x31, MRMDestReg, |
| 1342 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1343 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1344 | [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1345 | def XOR32rr : I<0x31, MRMDestReg, |
| 1346 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1347 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1348 | [(set R32:$dst, (xor R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1349 | } |
| 1350 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1351 | def XOR8rm : I<0x32, MRMSrcMem , |
| 1352 | (ops R8 :$dst, R8:$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1353 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1354 | [(set R8:$dst, (xor R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1355 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1356 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 1357 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1358 | [(set R16:$dst, (xor R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1359 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1360 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 1361 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1362 | [(set R32:$dst, (xor R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1363 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1364 | def XOR8ri : Ii8<0x80, MRM6r, |
| 1365 | (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1366 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1367 | [(set R8:$dst, (xor R8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1368 | def XOR16ri : Ii16<0x81, MRM6r, |
| 1369 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1370 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1371 | [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1372 | def XOR32ri : Ii32<0x81, MRM6r, |
| 1373 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1374 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1375 | [(set R32:$dst, (xor R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1376 | def XOR16ri8 : Ii8<0x83, MRM6r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1377 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1378 | "xor{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1379 | [(set R16:$dst, (xor R16:$src1, i16immSExt8:$src2))]>, |
| 1380 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1381 | def XOR32ri8 : Ii8<0x83, MRM6r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1382 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1383 | "xor{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1384 | [(set R32:$dst, (xor R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1385 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1386 | def XOR8mr : I<0x30, MRMDestMem, |
| 1387 | (ops i8mem :$dst, R8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1388 | "xor{b} {$src, $dst|$dst, $src}", |
| 1389 | [(store (xor (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1390 | def XOR16mr : I<0x31, MRMDestMem, |
| 1391 | (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1392 | "xor{w} {$src, $dst|$dst, $src}", |
| 1393 | [(store (xor (load addr:$dst), R16:$src), addr:$dst)]>, |
| 1394 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1395 | def XOR32mr : I<0x31, MRMDestMem, |
| 1396 | (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1397 | "xor{l} {$src, $dst|$dst, $src}", |
| 1398 | [(store (xor (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1399 | def XOR8mi : Ii8<0x80, MRM6m, |
| 1400 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1401 | "xor{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1402 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1403 | def XOR16mi : Ii16<0x81, MRM6m, |
| 1404 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1405 | "xor{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1406 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1407 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1408 | def XOR32mi : Ii32<0x81, MRM6m, |
| 1409 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1410 | "xor{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1411 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1412 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1413 | (ops i16mem:$dst, i16i8imm :$src), |
| 1414 | "xor{w} {$src, $dst|$dst, $src}", |
| 1415 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1416 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1417 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1418 | (ops i32mem:$dst, i32i8imm :$src), |
| 1419 | "xor{l} {$src, $dst|$dst, $src}", |
| 1420 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1421 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1422 | |
| 1423 | // Shift instructions |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1424 | def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1425 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1426 | [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1427 | def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1428 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1429 | [(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1430 | def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1431 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1432 | [(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1433 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1434 | def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1435 | "shl{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1436 | [(set R8:$dst, (shl R8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1437 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1438 | def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1439 | "shl{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1440 | [(set R16:$dst, (shl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1441 | def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1442 | "shl{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1443 | [(set R32:$dst, (shl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1444 | } |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1445 | |
| 1446 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1447 | def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1448 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1449 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1450 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1451 | def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1452 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1453 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1454 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1455 | def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1456 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1457 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1458 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1459 | def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1460 | "shl{b} {$src, $dst|$dst, $src}", |
| 1461 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1462 | def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1463 | "shl{w} {$src, $dst|$dst, $src}", |
| 1464 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1465 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1466 | def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1467 | "shl{l} {$src, $dst|$dst, $src}", |
| 1468 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1469 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1470 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1471 | def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1472 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1473 | [(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1474 | def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1475 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1476 | [(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1477 | def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1478 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1479 | [(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1480 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1481 | def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1482 | "shr{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1483 | [(set R8:$dst, (srl R8:$src1, (i8 imm:$src2)))]>; |
| 1484 | def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1485 | "shr{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1486 | [(set R16:$dst, (srl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1487 | def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1488 | "shr{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1489 | [(set R32:$dst, (srl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1490 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1491 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1492 | def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1493 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1494 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1495 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1496 | def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1497 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1498 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1499 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1500 | def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1501 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1502 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1503 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1504 | def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1505 | "shr{b} {$src, $dst|$dst, $src}", |
| 1506 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1507 | def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1508 | "shr{w} {$src, $dst|$dst, $src}", |
| 1509 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1510 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1511 | def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1512 | "shr{l} {$src, $dst|$dst, $src}", |
| 1513 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1514 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1515 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1516 | def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1517 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1518 | [(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1519 | def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1520 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1521 | [(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1522 | def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1523 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1524 | [(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1525 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1526 | def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1527 | "sar{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1528 | [(set R8:$dst, (sra R8:$src1, (i8 imm:$src2)))]>; |
| 1529 | def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1530 | "sar{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1531 | [(set R16:$dst, (sra R16:$src1, (i8 imm:$src2)))]>, |
| 1532 | OpSize; |
| 1533 | def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1534 | "sar{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1535 | [(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1536 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1537 | def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1538 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1539 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1540 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1541 | def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1542 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1543 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1544 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1545 | def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1546 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1547 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1548 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1549 | def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1550 | "sar{b} {$src, $dst|$dst, $src}", |
| 1551 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1552 | def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1553 | "sar{w} {$src, $dst|$dst, $src}", |
| 1554 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1555 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1556 | def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1557 | "sar{l} {$src, $dst|$dst, $src}", |
| 1558 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1559 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1560 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1561 | // Rotate instructions |
| 1562 | // FIXME: provide shorter instructions when imm8 == 1 |
| 1563 | def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1564 | "rol{b} {%cl, $dst|$dst, %CL}", |
| 1565 | [(set R8:$dst, (rotl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1566 | def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1567 | "rol{w} {%cl, $dst|$dst, %CL}", |
| 1568 | [(set R16:$dst, (rotl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1569 | def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1570 | "rol{l} {%cl, $dst|$dst, %CL}", |
| 1571 | [(set R32:$dst, (rotl R32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1572 | |
| 1573 | def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1574 | "rol{b} {$src2, $dst|$dst, $src2}", |
| 1575 | [(set R8:$dst, (rotl R8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1576 | def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1577 | "rol{w} {$src2, $dst|$dst, $src2}", |
| 1578 | [(set R16:$dst, (rotl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1579 | def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1580 | "rol{l} {$src2, $dst|$dst, $src2}", |
| 1581 | [(set R32:$dst, (rotl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1582 | |
| 1583 | let isTwoAddress = 0 in { |
| 1584 | def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1585 | "rol{b} {%cl, $dst|$dst, %CL}", |
| 1586 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1587 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1588 | def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1589 | "rol{w} {%cl, $dst|$dst, %CL}", |
| 1590 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1591 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1592 | def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1593 | "rol{l} {%cl, $dst|$dst, %CL}", |
| 1594 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1595 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1596 | def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1597 | "rol{b} {$src, $dst|$dst, $src}", |
| 1598 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1599 | def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1600 | "rol{w} {$src, $dst|$dst, $src}", |
| 1601 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1602 | OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1603 | def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1604 | "rol{l} {$src, $dst|$dst, $src}", |
| 1605 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1606 | } |
| 1607 | |
| 1608 | def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1609 | "ror{b} {%cl, $dst|$dst, %CL}", |
| 1610 | [(set R8:$dst, (rotr R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1611 | def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1612 | "ror{w} {%cl, $dst|$dst, %CL}", |
| 1613 | [(set R16:$dst, (rotr R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1614 | def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1615 | "ror{l} {%cl, $dst|$dst, %CL}", |
| 1616 | [(set R32:$dst, (rotr R32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1617 | |
| 1618 | def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1619 | "ror{b} {$src2, $dst|$dst, $src2}", |
| 1620 | [(set R8:$dst, (rotr R8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1621 | def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1622 | "ror{w} {$src2, $dst|$dst, $src2}", |
| 1623 | [(set R16:$dst, (rotr R16:$src1, (i8 imm:$src2)))]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1624 | def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1625 | "ror{l} {$src2, $dst|$dst, $src2}", |
| 1626 | [(set R32:$dst, (rotr R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1627 | let isTwoAddress = 0 in { |
| 1628 | def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1629 | "ror{b} {%cl, $dst|$dst, %CL}", |
| 1630 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1631 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1632 | def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1633 | "ror{w} {%cl, $dst|$dst, %CL}", |
| 1634 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1635 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1636 | def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1637 | "ror{l} {%cl, $dst|$dst, %CL}", |
| 1638 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1639 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1640 | def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1641 | "ror{b} {$src, $dst|$dst, $src}", |
| 1642 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1643 | def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1644 | "ror{w} {$src, $dst|$dst, $src}", |
| 1645 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1646 | OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1647 | def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1648 | "ror{l} {$src, $dst|$dst, $src}", |
| 1649 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1650 | } |
| 1651 | |
| 1652 | |
| 1653 | |
| 1654 | // Double shift instructions (generalizations of rotate) |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1655 | def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1656 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1657 | [(set R32:$dst, (X86shld R32:$src1, R32:$src2, CL))]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1658 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1659 | def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1660 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1661 | [(set R32:$dst, (X86shrd R32:$src1, R32:$src2, CL))]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1662 | Imp<[CL],[]>, TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1663 | def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1664 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1665 | [(set R16:$dst, (X86shld R16:$src1, R16:$src2, CL))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1666 | Imp<[CL],[]>, TB, OpSize; |
| 1667 | def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1668 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1669 | [(set R16:$dst, (X86shrd R16:$src1, R16:$src2, CL))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1670 | Imp<[CL],[]>, TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1671 | |
| 1672 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1673 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
| 1674 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1675 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1676 | [(set R32:$dst, (X86shld R32:$src1, R32:$src2, |
| 1677 | (i8 imm:$src3)))]>, |
| 1678 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1679 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
| 1680 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1681 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1682 | [(set R32:$dst, (X86shrd R32:$src1, R32:$src2, |
| 1683 | (i8 imm:$src3)))]>, |
| 1684 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1685 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
| 1686 | (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1687 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1688 | [(set R16:$dst, (X86shld R16:$src1, R16:$src2, |
| 1689 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1690 | TB, OpSize; |
| 1691 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
| 1692 | (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1693 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1694 | [(set R16:$dst, (X86shrd R16:$src1, R16:$src2, |
| 1695 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1696 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1697 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1698 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1699 | let isTwoAddress = 0 in { |
| 1700 | def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1701 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1702 | [(store (X86shld (loadi32 addr:$dst), R32:$src2, CL), |
| 1703 | addr:$dst)]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1704 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1705 | def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1706 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1707 | [(store (X86shrd (loadi32 addr:$dst), R32:$src2, CL), |
| 1708 | addr:$dst)]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1709 | Imp<[CL],[]>, TB; |
| 1710 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
| 1711 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1712 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1713 | [(store (X86shld (loadi32 addr:$dst), R32:$src2, |
| 1714 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1715 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1716 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
| 1717 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1718 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1719 | [(store (X86shrd (loadi32 addr:$dst), R32:$src2, |
| 1720 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1721 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1722 | |
| 1723 | def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1724 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1725 | [(store (X86shld (loadi16 addr:$dst), R16:$src2, CL), |
| 1726 | addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1727 | Imp<[CL],[]>, TB, OpSize; |
| 1728 | def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1729 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1730 | [(store (X86shrd (loadi16 addr:$dst), R16:$src2, CL), |
| 1731 | addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1732 | Imp<[CL],[]>, TB, OpSize; |
| 1733 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
| 1734 | (ops i16mem:$dst, R16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1735 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1736 | [(store (X86shld (loadi16 addr:$dst), R16:$src2, |
| 1737 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1738 | TB, OpSize; |
| 1739 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
| 1740 | (ops i16mem:$dst, R16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1741 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1742 | [(store (X86shrd (loadi16 addr:$dst), R16:$src2, |
| 1743 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1744 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1745 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1746 | |
| 1747 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1748 | // Arithmetic. |
| 1749 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1750 | def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1751 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1752 | [(set R8:$dst, (add R8:$src1, R8:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1753 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1754 | def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1755 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1756 | [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1757 | def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1758 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1759 | [(set R32:$dst, (add R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1760 | } // end isConvertibleToThreeAddress |
| 1761 | } // end isCommutable |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1762 | def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1763 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1764 | [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1765 | def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1766 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1767 | [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1768 | def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1769 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1770 | [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1771 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1772 | def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1773 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1774 | [(set R8:$dst, (add R8:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1775 | |
| 1776 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1777 | def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1778 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1779 | [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1780 | def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1781 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1782 | [(set R32:$dst, (add R32:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1783 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1784 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1785 | // FIXME: move ADD16ri8 above ADD16ri to optimize for space. |
| 1786 | def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1787 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1788 | [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>, |
| 1789 | OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1790 | def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1791 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1792 | [(set R32:$dst, (add R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1793 | |
| 1794 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1795 | def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1796 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1797 | [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1798 | def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1799 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1800 | [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>, |
| 1801 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1802 | def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1803 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1804 | [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1805 | def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1806 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1807 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1808 | def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1809 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1810 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1811 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1812 | def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1813 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1814 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1815 | def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1816 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1817 | [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1818 | OpSize; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1819 | def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1820 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1821 | [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1822 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1823 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1824 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1825 | def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1826 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1827 | [(set R32:$dst, (adde R32:$src1, R32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1828 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1829 | def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1830 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1831 | [(set R32:$dst, (adde R32:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1832 | def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1833 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1834 | [(set R32:$dst, (adde R32:$src1, imm:$src2))]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1835 | def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1836 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1837 | [(set R32:$dst, (adde R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1838 | |
| 1839 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1840 | def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1841 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1842 | [(store (adde (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1843 | def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1844 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1845 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1846 | def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1847 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1848 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1849 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1850 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1851 | def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1852 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1853 | [(set R8:$dst, (sub R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1854 | def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1855 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1856 | [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1857 | def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1858 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1859 | [(set R32:$dst, (sub R32:$src1, R32:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1860 | def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1861 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1862 | [(set R8:$dst, (sub R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1863 | def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1864 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1865 | [(set R16:$dst, (sub R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1866 | def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1867 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1868 | [(set R32:$dst, (sub R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1869 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1870 | def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1871 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1872 | [(set R8:$dst, (sub R8:$src1, imm:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1873 | def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1874 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1875 | [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1876 | def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1877 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1878 | [(set R32:$dst, (sub R32:$src1, imm:$src2))]>; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1879 | def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1880 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1881 | [(set R16:$dst, (sub R16:$src1, i16immSExt8:$src2))]>, |
| 1882 | OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1883 | def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1884 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1885 | [(set R32:$dst, (sub R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1886 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1887 | def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1888 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1889 | [(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1890 | def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1891 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1892 | [(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>, |
| 1893 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1894 | def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1895 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1896 | [(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1897 | def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1898 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1899 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1900 | def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1901 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1902 | [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1903 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1904 | def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1905 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1906 | [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1907 | def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1908 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1909 | [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1910 | OpSize; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1911 | def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1912 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1913 | [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1914 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1915 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1916 | def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1917 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1918 | [(set R32:$dst, (sube R32:$src1, R32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1919 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1920 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1921 | def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1922 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1923 | [(store (sube (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1924 | def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1925 | "sbb{b} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1926 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1927 | def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1928 | "sbb{w} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1929 | [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1930 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1931 | def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1932 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1933 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1934 | def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1935 | "sbb{w} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1936 | [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1937 | OpSize; |
| 1938 | def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1939 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1940 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1941 | } |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1942 | def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1943 | "sbb{b} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1944 | [(set R8:$dst, (sube R8:$src1, imm:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1945 | def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1946 | "sbb{w} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1947 | [(set R16:$dst, (sube R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1948 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1949 | def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1950 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1951 | [(set R32:$dst, (sube R32:$src1, (load addr:$src2)))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1952 | def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1953 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1954 | [(set R32:$dst, (sube R32:$src1, imm:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1955 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1956 | def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1957 | "sbb{w} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1958 | [(set R16:$dst, (sube R16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1959 | OpSize; |
| 1960 | def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1961 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1962 | [(set R32:$dst, (sube R32:$src1, i32immSExt8:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1963 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1964 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1965 | def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1966 | "imul{w} {$src2, $dst|$dst, $src2}", |
| 1967 | [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1968 | def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1969 | "imul{l} {$src2, $dst|$dst, $src2}", |
| 1970 | [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1971 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1972 | def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1973 | "imul{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1974 | [(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>, |
| 1975 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1976 | def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1977 | "imul{l} {$src2, $dst|$dst, $src2}", |
| 1978 | [(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1979 | |
| 1980 | } // end Two Address instructions |
| 1981 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1982 | // Suprisingly enough, these are not two address instructions! |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1983 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16 |
| 1984 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1985 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1986 | [(set R16:$dst, (mul R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1987 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32 |
| 1988 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1989 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 1990 | [(set R32:$dst, (mul R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1991 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8 |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1992 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1993 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1994 | [(set R16:$dst, (mul R16:$src1, i16immSExt8:$src2))]>, |
| 1995 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1996 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1997 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1998 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1999 | [(set R32:$dst, (mul R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2000 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2001 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2002 | (ops R16:$dst, i16mem:$src1, i16imm:$src2), |
| 2003 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 2004 | [(set R16:$dst, (mul (load addr:$src1), imm:$src2))]>, |
| 2005 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2006 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32 |
| 2007 | (ops R32:$dst, i32mem:$src1, i32imm:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2008 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 2009 | [(set R32:$dst, (mul (load addr:$src1), imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2010 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2011 | (ops R16:$dst, i16mem:$src1, i16i8imm :$src2), |
| 2012 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2013 | [(set R16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, |
| 2014 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2015 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2016 | (ops R32:$dst, i32mem:$src1, i32i8imm: $src2), |
| 2017 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2018 | [(set R32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2019 | |
| 2020 | //===----------------------------------------------------------------------===// |
| 2021 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2022 | // |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2023 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 2024 | def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2025 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2026 | [(X86test R8:$src1, R8:$src2)]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 2027 | def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2028 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2029 | [(X86test R16:$src1, R16:$src2)]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 2030 | def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2031 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2032 | [(X86test R32:$src1, R32:$src2)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2033 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2034 | def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2035 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2036 | [(X86test (loadi8 addr:$src1), R8:$src2)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2037 | def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2038 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2039 | [(X86test (loadi16 addr:$src1), R16:$src2)]>, |
| 2040 | OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2041 | def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2042 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2043 | [(X86test (loadi32 addr:$src1), R32:$src2)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2044 | def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2045 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2046 | [(X86test R8:$src1, (loadi8 addr:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2047 | def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2048 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2049 | [(X86test R16:$src1, (loadi16 addr:$src2))]>, |
| 2050 | OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2051 | def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2052 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2053 | [(X86test R32:$src1, (loadi32 addr:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2054 | |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2055 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 |
| 2056 | (ops R8:$src1, i8imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2057 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2058 | [(X86test R8:$src1, imm:$src2)]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2059 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16 |
| 2060 | (ops R16:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2061 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2062 | [(X86test R16:$src1, imm:$src2)]>, OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2063 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32 |
| 2064 | (ops R32:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2065 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2066 | [(X86test R32:$src1, imm:$src2)]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2067 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2068 | (ops i8mem:$src1, i8imm:$src2), |
| 2069 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2070 | [(X86test (loadi8 addr:$src1), imm:$src2)]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2071 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
| 2072 | (ops i16mem:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2073 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2074 | [(X86test (loadi16 addr:$src1), imm:$src2)]>, |
| 2075 | OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2076 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
| 2077 | (ops i32mem:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2078 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2079 | [(X86test (loadi32 addr:$src1), imm:$src2)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2080 | |
| 2081 | |
| 2082 | // Condition code ops, incl. set if equal/not equal/... |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2083 | def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH |
| 2084 | def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2085 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2086 | def SETEr : I<0x94, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2087 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2088 | "sete $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2089 | [(set R8:$dst, (X86setcc X86_COND_E))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2090 | TB; // R8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2091 | def SETEm : I<0x94, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2092 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2093 | "sete $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2094 | [(store (X86setcc X86_COND_E), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2095 | TB; // [mem8] = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2096 | def SETNEr : I<0x95, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2097 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2098 | "setne $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2099 | [(set R8:$dst, (X86setcc X86_COND_NE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2100 | TB; // R8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2101 | def SETNEm : I<0x95, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2102 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2103 | "setne $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2104 | [(store (X86setcc X86_COND_NE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2105 | TB; // [mem8] = != |
| 2106 | def SETLr : I<0x9C, MRM0r, |
| 2107 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2108 | "setl $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2109 | [(set R8:$dst, (X86setcc X86_COND_L))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2110 | TB; // R8 = < signed |
| 2111 | def SETLm : I<0x9C, MRM0m, |
| 2112 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2113 | "setl $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2114 | [(store (X86setcc X86_COND_L), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2115 | TB; // [mem8] = < signed |
| 2116 | def SETGEr : I<0x9D, MRM0r, |
| 2117 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2118 | "setge $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2119 | [(set R8:$dst, (X86setcc X86_COND_GE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2120 | TB; // R8 = >= signed |
| 2121 | def SETGEm : I<0x9D, MRM0m, |
| 2122 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2123 | "setge $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2124 | [(store (X86setcc X86_COND_GE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2125 | TB; // [mem8] = >= signed |
| 2126 | def SETLEr : I<0x9E, MRM0r, |
| 2127 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2128 | "setle $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2129 | [(set R8:$dst, (X86setcc X86_COND_LE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2130 | TB; // R8 = <= signed |
| 2131 | def SETLEm : I<0x9E, MRM0m, |
| 2132 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2133 | "setle $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2134 | [(store (X86setcc X86_COND_LE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2135 | TB; // [mem8] = <= signed |
| 2136 | def SETGr : I<0x9F, MRM0r, |
| 2137 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2138 | "setg $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2139 | [(set R8:$dst, (X86setcc X86_COND_G))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2140 | TB; // R8 = > signed |
| 2141 | def SETGm : I<0x9F, MRM0m, |
| 2142 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2143 | "setg $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2144 | [(store (X86setcc X86_COND_G), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2145 | TB; // [mem8] = > signed |
| 2146 | |
| 2147 | def SETBr : I<0x92, MRM0r, |
| 2148 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2149 | "setb $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2150 | [(set R8:$dst, (X86setcc X86_COND_B))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2151 | TB; // R8 = < unsign |
| 2152 | def SETBm : I<0x92, MRM0m, |
| 2153 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2154 | "setb $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2155 | [(store (X86setcc X86_COND_B), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2156 | TB; // [mem8] = < unsign |
| 2157 | def SETAEr : I<0x93, MRM0r, |
| 2158 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2159 | "setae $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2160 | [(set R8:$dst, (X86setcc X86_COND_AE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2161 | TB; // R8 = >= unsign |
| 2162 | def SETAEm : I<0x93, MRM0m, |
| 2163 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2164 | "setae $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2165 | [(store (X86setcc X86_COND_AE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2166 | TB; // [mem8] = >= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2167 | def SETBEr : I<0x96, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2168 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2169 | "setbe $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2170 | [(set R8:$dst, (X86setcc X86_COND_BE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2171 | TB; // R8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2172 | def SETBEm : I<0x96, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2173 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2174 | "setbe $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2175 | [(store (X86setcc X86_COND_BE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2176 | TB; // [mem8] = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2177 | def SETAr : I<0x97, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2178 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2179 | "seta $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2180 | [(set R8:$dst, (X86setcc X86_COND_A))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2181 | TB; // R8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2182 | def SETAm : I<0x97, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2183 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2184 | "seta $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2185 | [(store (X86setcc X86_COND_A), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2186 | TB; // [mem8] = > signed |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2187 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2188 | def SETSr : I<0x98, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2189 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2190 | "sets $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2191 | [(set R8:$dst, (X86setcc X86_COND_S))]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2192 | TB; // R8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2193 | def SETSm : I<0x98, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2194 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2195 | "sets $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2196 | [(store (X86setcc X86_COND_S), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2197 | TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2198 | def SETNSr : I<0x99, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2199 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2200 | "setns $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2201 | [(set R8:$dst, (X86setcc X86_COND_NS))]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2202 | TB; // R8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2203 | def SETNSm : I<0x99, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2204 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2205 | "setns $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2206 | [(store (X86setcc X86_COND_NS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2207 | TB; // [mem8] = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2208 | def SETPr : I<0x9A, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2209 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2210 | "setp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2211 | [(set R8:$dst, (X86setcc X86_COND_P))]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2212 | TB; // R8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2213 | def SETPm : I<0x9A, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2214 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2215 | "setp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2216 | [(store (X86setcc X86_COND_P), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2217 | TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2218 | def SETNPr : I<0x9B, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2219 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2220 | "setnp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2221 | [(set R8:$dst, (X86setcc X86_COND_NP))]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2222 | TB; // R8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2223 | def SETNPm : I<0x9B, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2224 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2225 | "setnp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2226 | [(store (X86setcc X86_COND_NP), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2227 | TB; // [mem8] = not parity |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2228 | |
| 2229 | // Integer comparisons |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2230 | def CMP8rr : I<0x38, MRMDestReg, |
| 2231 | (ops R8 :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2232 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2233 | [(X86cmp R8:$src1, R8:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2234 | def CMP16rr : I<0x39, MRMDestReg, |
| 2235 | (ops R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2236 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2237 | [(X86cmp R16:$src1, R16:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2238 | def CMP32rr : I<0x39, MRMDestReg, |
| 2239 | (ops R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2240 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2241 | [(X86cmp R32:$src1, R32:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2242 | def CMP8mr : I<0x38, MRMDestMem, |
| 2243 | (ops i8mem :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2244 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2245 | [(X86cmp (loadi8 addr:$src1), R8:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2246 | def CMP16mr : I<0x39, MRMDestMem, |
| 2247 | (ops i16mem:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2248 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2249 | [(X86cmp (loadi16 addr:$src1), R16:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2250 | def CMP32mr : I<0x39, MRMDestMem, |
| 2251 | (ops i32mem:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2252 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2253 | [(X86cmp (loadi32 addr:$src1), R32:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2254 | def CMP8rm : I<0x3A, MRMSrcMem, |
| 2255 | (ops R8 :$src1, i8mem :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2256 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2257 | [(X86cmp R8:$src1, (loadi8 addr:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2258 | def CMP16rm : I<0x3B, MRMSrcMem, |
| 2259 | (ops R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2260 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2261 | [(X86cmp R16:$src1, (loadi16 addr:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2262 | def CMP32rm : I<0x3B, MRMSrcMem, |
| 2263 | (ops R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2264 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2265 | [(X86cmp R32:$src1, (loadi32 addr:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2266 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2267 | (ops R8:$src1, i8imm:$src2), |
| 2268 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2269 | [(X86cmp R8:$src1, imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2270 | def CMP16ri : Ii16<0x81, MRM7r, |
| 2271 | (ops R16:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2272 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2273 | [(X86cmp R16:$src1, imm:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2274 | def CMP32ri : Ii32<0x81, MRM7r, |
| 2275 | (ops R32:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2276 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2277 | [(X86cmp R32:$src1, imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2278 | def CMP8mi : Ii8 <0x80, MRM7m, |
| 2279 | (ops i8mem :$src1, i8imm :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2280 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2281 | [(X86cmp (loadi8 addr:$src1), imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2282 | def CMP16mi : Ii16<0x81, MRM7m, |
| 2283 | (ops i16mem:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2284 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2285 | [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2286 | def CMP32mi : Ii32<0x81, MRM7m, |
| 2287 | (ops i32mem:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2288 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2289 | [(X86cmp (loadi32 addr:$src1), imm:$src2)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2290 | |
| 2291 | // Sign/Zero extenders |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2292 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2293 | "movs{bw|x} {$src, $dst|$dst, $src}", |
| 2294 | [(set R16:$dst, (sext R8:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2295 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2296 | "movs{bw|x} {$src, $dst|$dst, $src}", |
| 2297 | [(set R16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2298 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2299 | "movs{bl|x} {$src, $dst|$dst, $src}", |
| 2300 | [(set R32:$dst, (sext R8:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2301 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2302 | "movs{bl|x} {$src, $dst|$dst, $src}", |
| 2303 | [(set R32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2304 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2305 | "movs{wl|x} {$src, $dst|$dst, $src}", |
| 2306 | [(set R32:$dst, (sext R16:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2307 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2308 | "movs{wl|x} {$src, $dst|$dst, $src}", |
| 2309 | [(set R32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 2310 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2311 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2312 | "movz{bw|x} {$src, $dst|$dst, $src}", |
| 2313 | [(set R16:$dst, (zext R8:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2314 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2315 | "movz{bw|x} {$src, $dst|$dst, $src}", |
| 2316 | [(set R16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2317 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2318 | "movz{bl|x} {$src, $dst|$dst, $src}", |
| 2319 | [(set R32:$dst, (zext R8:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2320 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2321 | "movz{bl|x} {$src, $dst|$dst, $src}", |
| 2322 | [(set R32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2323 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2324 | "movz{wl|x} {$src, $dst|$dst, $src}", |
| 2325 | [(set R32:$dst, (zext R16:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2326 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2327 | "movz{wl|x} {$src, $dst|$dst, $src}", |
| 2328 | [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
| 2329 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2330 | //===----------------------------------------------------------------------===// |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2331 | // Miscellaneous Instructions |
| 2332 | //===----------------------------------------------------------------------===// |
| 2333 | |
| 2334 | def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>, |
| 2335 | TB, Imp<[],[EAX,EDX]>; |
| 2336 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2337 | //===----------------------------------------------------------------------===// |
| 2338 | // Alias Instructions |
| 2339 | //===----------------------------------------------------------------------===// |
| 2340 | |
| 2341 | // Alias instructions that map movr0 to xor. |
| 2342 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
| 2343 | def MOV8r0 : I<0x30, MRMInitReg, (ops R8 :$dst), |
| 2344 | "xor{b} $dst, $dst", |
| 2345 | [(set R8:$dst, 0)]>; |
| 2346 | def MOV16r0 : I<0x31, MRMInitReg, (ops R16:$dst), |
| 2347 | "xor{w} $dst, $dst", |
| 2348 | [(set R16:$dst, 0)]>, OpSize; |
| 2349 | def MOV32r0 : I<0x31, MRMInitReg, (ops R32:$dst), |
| 2350 | "xor{l} $dst, $dst", |
| 2351 | [(set R32:$dst, 0)]>; |
| 2352 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2353 | //===----------------------------------------------------------------------===// |
| 2354 | // Non-Instruction Patterns |
| 2355 | //===----------------------------------------------------------------------===// |
| 2356 | |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 2357 | // GlobalAddress and ExternalSymbol |
Evan Cheng | 77e9043 | 2006-01-12 19:36:31 +0000 | [diff] [blame] | 2358 | def : Pat<(i32 globaladdr:$dst), (MOV32ri tglobaladdr:$dst)>; |
| 2359 | def : Pat<(i32 externalsym:$dst), (MOV32ri texternalsym:$dst)>; |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 2360 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2361 | // Calls |
| 2362 | def : Pat<(X86call tglobaladdr:$dst), |
| 2363 | (CALLpcrel32 tglobaladdr:$dst)>; |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 2364 | def : Pat<(X86call texternalsym:$dst), |
| 2365 | (CALLpcrel32 texternalsym:$dst)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2366 | |
| 2367 | // X86 specific add which produces a flag. |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2368 | def : Pat<(addc R32:$src1, R32:$src2), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2369 | (ADD32rr R32:$src1, R32:$src2)>; |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2370 | def : Pat<(addc R32:$src1, (load addr:$src2)), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2371 | (ADD32rm R32:$src1, addr:$src2)>; |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2372 | def : Pat<(addc R32:$src1, imm:$src2), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2373 | (ADD32ri R32:$src1, imm:$src2)>; |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2374 | def : Pat<(addc R32:$src1, i32immSExt8:$src2), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2375 | (ADD32ri8 R32:$src1, i32immSExt8:$src2)>; |
| 2376 | |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2377 | def : Pat<(subc R32:$src1, R32:$src2), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2378 | (SUB32rr R32:$src1, R32:$src2)>; |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2379 | def : Pat<(subc R32:$src1, (load addr:$src2)), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2380 | (SUB32rm R32:$src1, addr:$src2)>; |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2381 | def : Pat<(subc R32:$src1, imm:$src2), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2382 | (SUB32ri R32:$src1, imm:$src2)>; |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2383 | def : Pat<(subc R32:$src1, i32immSExt8:$src2), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2384 | (SUB32ri8 R32:$src1, i32immSExt8:$src2)>; |
| 2385 | |
Evan Cheng | b841433 | 2006-01-13 21:45:19 +0000 | [diff] [blame] | 2386 | def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1), |
| 2387 | (MOV8mi addr:$dst, imm:$src)>; |
| 2388 | def : Pat<(truncstore R8:$src, addr:$dst, i1), |
| 2389 | (MOV8mr addr:$dst, R8:$src)>; |
| 2390 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2391 | // {s|z}extload bool -> {s|z}extload byte |
| 2392 | def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>; |
| 2393 | def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>; |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 2394 | def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2395 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 2396 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 2397 | |
| 2398 | // extload bool -> extload byte |
| 2399 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
| 2400 | |
| 2401 | // anyext -> zext |
| 2402 | def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src)>; |
| 2403 | def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8 R8 :$src)>; |
| 2404 | def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>; |
| 2405 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 2406 | //===----------------------------------------------------------------------===// |
| 2407 | // Some peepholes |
| 2408 | //===----------------------------------------------------------------------===// |
| 2409 | |
| 2410 | // (shl x, 1) ==> (add x, x) |
| 2411 | def : Pat<(shl R8 :$src1, (i8 1)), (ADD8rr R8 :$src1, R8 :$src1)>; |
| 2412 | def : Pat<(shl R16:$src1, (i8 1)), (ADD16rr R16:$src1, R16:$src1)>; |
| 2413 | def : Pat<(shl R32:$src1, (i8 1)), (ADD32rr R32:$src1, R32:$src1)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 2414 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2415 | // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c) |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 2416 | def : Pat<(or (srl R32:$src1, CL:$amt), |
| 2417 | (shl R32:$src2, (sub 32, CL:$amt))), |
| 2418 | (SHRD32rrCL R32:$src1, R32:$src2)>; |
| 2419 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2420 | def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), |
| 2421 | (shl R32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 2422 | (SHRD32mrCL addr:$dst, R32:$src2)>; |
| 2423 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2424 | // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 2425 | def : Pat<(or (shl R32:$src1, CL:$amt), |
| 2426 | (srl R32:$src2, (sub 32, CL:$amt))), |
| 2427 | (SHLD32rrCL R32:$src1, R32:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2428 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2429 | def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), |
| 2430 | (srl R32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 2431 | (SHLD32mrCL addr:$dst, R32:$src2)>; |
| 2432 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2433 | // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) |
| 2434 | def : Pat<(or (srl R16:$src1, CL:$amt), |
| 2435 | (shl R16:$src2, (sub 16, CL:$amt))), |
| 2436 | (SHRD16rrCL R16:$src1, R16:$src2)>; |
| 2437 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2438 | def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), |
| 2439 | (shl R16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 2440 | (SHRD16mrCL addr:$dst, R16:$src2)>; |
| 2441 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2442 | // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) |
| 2443 | def : Pat<(or (shl R16:$src1, CL:$amt), |
| 2444 | (srl R16:$src2, (sub 16, CL:$amt))), |
| 2445 | (SHLD16rrCL R16:$src1, R16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2446 | |
| 2447 | def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), |
| 2448 | (srl R16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 2449 | (SHLD16mrCL addr:$dst, R16:$src2)>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 2450 | |
| 2451 | |
| 2452 | //===----------------------------------------------------------------------===// |
| 2453 | // Floating Point Stack Support |
| 2454 | //===----------------------------------------------------------------------===// |
| 2455 | |
| 2456 | include "X86InstrFPStack.td" |
| 2457 | |
| 2458 | //===----------------------------------------------------------------------===// |
| 2459 | // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) |
| 2460 | //===----------------------------------------------------------------------===// |
| 2461 | |
| 2462 | include "X86InstrMMX.td" |
| 2463 | |
| 2464 | //===----------------------------------------------------------------------===// |
| 2465 | // XMM Floating point support (requires SSE / SSE2) |
| 2466 | //===----------------------------------------------------------------------===// |
| 2467 | |
| 2468 | include "X86InstrSSE.td" |