Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 16 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 17 | // |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 18 | |
| 19 | class X86MemOperand<ValueType Ty> : Operand<Ty> { |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 20 | let NumMIOperands = 4; |
| 21 | let PrintMethod = "printMemoryOperand"; |
| 22 | } |
| 23 | |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 24 | def i8mem : X86MemOperand<i8>; |
| 25 | def i16mem : X86MemOperand<i16>; |
| 26 | def i32mem : X86MemOperand<i32>; |
| 27 | def i64mem : X86MemOperand<i64>; |
| 28 | def f32mem : X86MemOperand<f32>; |
| 29 | def f64mem : X86MemOperand<f64>; |
| 30 | def f80mem : X86MemOperand<f80>; |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 31 | |
Chris Lattner | e4ead0c | 2004-08-11 06:59:12 +0000 | [diff] [blame] | 32 | // PCRelative calls need special operand formatting. |
| 33 | let PrintMethod = "printCallOperand" in |
| 34 | def calltarget : Operand<i32>; |
| 35 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 36 | // Format specifies the encoding used by the instruction. This is part of the |
| 37 | // ad-hoc solution used to emit machine instruction encodings by our machine |
| 38 | // code emitter. |
| 39 | class Format<bits<5> val> { |
| 40 | bits<5> Value = val; |
| 41 | } |
| 42 | |
| 43 | def Pseudo : Format<0>; def RawFrm : Format<1>; |
| 44 | def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; |
| 45 | def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; |
| 46 | def MRMSrcMem : Format<6>; |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 47 | def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; |
| 48 | def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; |
| 49 | def MRM6r : Format<22>; def MRM7r : Format<23>; |
| 50 | def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; |
| 51 | def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; |
| 52 | def MRM6m : Format<30>; def MRM7m : Format<31>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 53 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 54 | // ImmType - This specifies the immediate type used by an instruction. This is |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 55 | // part of the ad-hoc solution used to emit machine instruction encodings by our |
| 56 | // machine code emitter. |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 57 | class ImmType<bits<2> val> { |
| 58 | bits<2> Value = val; |
| 59 | } |
| 60 | def NoImm : ImmType<0>; |
| 61 | def Imm8 : ImmType<1>; |
| 62 | def Imm16 : ImmType<2>; |
| 63 | def Imm32 : ImmType<3>; |
| 64 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 65 | // FPFormat - This specifies what form this FP instruction has. This is used by |
| 66 | // the Floating-Point stackifier pass. |
| 67 | class FPFormat<bits<3> val> { |
| 68 | bits<3> Value = val; |
| 69 | } |
| 70 | def NotFP : FPFormat<0>; |
| 71 | def ZeroArgFP : FPFormat<1>; |
| 72 | def OneArgFP : FPFormat<2>; |
| 73 | def OneArgFPRW : FPFormat<3>; |
| 74 | def TwoArgFP : FPFormat<4>; |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 75 | def CompareFP : FPFormat<5>; |
| 76 | def CondMovFP : FPFormat<6>; |
| 77 | def SpecialFP : FPFormat<7>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 78 | |
| 79 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 80 | class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> |
| 81 | : Instruction { |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 82 | let Namespace = "X86"; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 83 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 84 | bits<8> Opcode = opcod; |
| 85 | Format Form = f; |
| 86 | bits<5> FormBits = Form.Value; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 87 | ImmType ImmT = i; |
| 88 | bits<2> ImmTypeBits = ImmT.Value; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 89 | |
Chris Lattner | c96bb81 | 2004-08-11 07:12:04 +0000 | [diff] [blame] | 90 | dag OperandList = ops; |
| 91 | string AsmString = AsmStr; |
| 92 | |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 93 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 94 | // Attributes specific to X86 instructions... |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 95 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 96 | bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 97 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 98 | bits<4> Prefix = 0; // Which prefix byte does this inst have? |
| 99 | FPFormat FPForm; // What flavor of FP instruction is this? |
| 100 | bits<3> FPFormBits = 0; |
| 101 | } |
| 102 | |
| 103 | class Imp<list<Register> uses, list<Register> defs> { |
| 104 | list<Register> Uses = uses; |
| 105 | list<Register> Defs = defs; |
| 106 | } |
| 107 | |
| 108 | |
| 109 | // Prefix byte classes which are used to indicate to the ad-hoc machine code |
| 110 | // emitter that various prefix bytes are required. |
| 111 | class OpSize { bit hasOpSizePrefix = 1; } |
| 112 | class TB { bits<4> Prefix = 1; } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 113 | class REP { bits<4> Prefix = 2; } |
| 114 | class D8 { bits<4> Prefix = 3; } |
| 115 | class D9 { bits<4> Prefix = 4; } |
| 116 | class DA { bits<4> Prefix = 5; } |
| 117 | class DB { bits<4> Prefix = 6; } |
| 118 | class DC { bits<4> Prefix = 7; } |
| 119 | class DD { bits<4> Prefix = 8; } |
| 120 | class DE { bits<4> Prefix = 9; } |
| 121 | class DF { bits<4> Prefix = 10; } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 122 | |
| 123 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 124 | //===----------------------------------------------------------------------===// |
| 125 | // Instruction templates... |
| 126 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 127 | class I<bits<8> o, Format f, dag ops, string asm> |
| 128 | : X86Inst<o, f, NoImm, ops, asm>; |
| 129 | class Ii8 <bits<8> o, Format f, dag ops, string asm> |
| 130 | : X86Inst<o, f, Imm8 , ops, asm>; |
| 131 | class Ii16<bits<8> o, Format f, dag ops, string asm> |
| 132 | : X86Inst<o, f, Imm16, ops, asm>; |
| 133 | class Ii32<bits<8> o, Format f, dag ops, string asm> |
| 134 | : X86Inst<o, f, Imm32, ops, asm>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 135 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 136 | //===----------------------------------------------------------------------===// |
| 137 | // Instruction list... |
| 138 | // |
| 139 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 140 | def PHI : I<0, Pseudo, (ops), "PHINODE">; // PHI node. |
| 141 | def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 142 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 143 | def ADJCALLSTACKDOWN : I<0, Pseudo, (ops), "#ADJCALLSTACKDOWN">; |
| 144 | def ADJCALLSTACKUP : I<0, Pseudo, (ops), "#ADJCALLSTACKUP">; |
| 145 | def IMPLICIT_USE : I<0, Pseudo, (ops), "#IMPLICIT_USE">; |
| 146 | def IMPLICIT_DEF : I<0, Pseudo, (ops), "#IMPLICIT_DEF">; |
Alkis Evlogimenos | e0bb3e7 | 2003-12-20 16:22:59 +0000 | [diff] [blame] | 147 | let isTerminator = 1 in |
| 148 | let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 149 | def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">; |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 150 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 151 | //===----------------------------------------------------------------------===// |
| 152 | // Control Flow Instructions... |
| 153 | // |
| 154 | |
| 155 | // Return instruction... |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 156 | let isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 157 | def RET : I<0xC3, RawFrm, (ops), "ret">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 158 | |
| 159 | // All branches are RawFrm, Void, Branch, and Terminators |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 160 | let isBranch = 1, isTerminator = 1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 161 | class IBr<bits<8> opcode, dag ops, string asm> : I<opcode, RawFrm, ops, asm>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 162 | |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 163 | let isBarrier = 1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 164 | def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">; |
| 165 | def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB; |
| 166 | def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB; |
| 167 | def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB; |
| 168 | def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB; |
| 169 | def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB; |
| 170 | def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB; |
| 171 | def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB; |
| 172 | def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 173 | def JP : IBr<0x8A, (ops i32imm:$dst), "jp $dst">, TB; |
| 174 | def JNP : IBr<0x8B, (ops i32imm:$dst), "jnp $dst">, TB; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 175 | def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB; |
| 176 | def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB; |
| 177 | def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB; |
| 178 | def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 179 | |
| 180 | |
| 181 | //===----------------------------------------------------------------------===// |
| 182 | // Call Instructions... |
| 183 | // |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 184 | let isCall = 1 in |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 185 | // All calls clobber the non-callee saved registers... |
Alkis Evlogimenos | 978f629 | 2004-09-08 16:54:54 +0000 | [diff] [blame] | 186 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0] in { |
Chris Lattner | e4ead0c | 2004-08-11 06:59:12 +0000 | [diff] [blame] | 187 | def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">; |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 188 | def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst">; |
| 189 | def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | |
| 193 | //===----------------------------------------------------------------------===// |
| 194 | // Miscellaneous Instructions... |
| 195 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 196 | def LEAVE : I<0xC9, RawFrm, |
| 197 | (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>; |
| 198 | def POP32r : I<0x58, AddRegFrm, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 199 | (ops R32:$reg), "pop{l} $reg">, Imp<[ESP],[ESP]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 200 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 201 | let isTwoAddress = 1 in // R32 = bswap R32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 202 | def BSWAP32r : I<0xC8, AddRegFrm, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 203 | (ops R32:$dst, R32:$src), "bswap{l} $dst">, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 204 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 205 | def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 206 | (ops R8:$src1, R8:$src2), |
| 207 | "xchg{b} {$src2|$src1}, {$src1|$src2}">; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 208 | def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 209 | (ops R16:$src1, R16:$src2), |
| 210 | "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 211 | def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 212 | (ops R32:$src1, R32:$src2), |
| 213 | "xchg{l} {$src2|$src1}, {$src1|$src2}">; |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 214 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 215 | def XCHG8mr : I<0x86, MRMDestMem, |
| 216 | (ops i8mem:$src1, R8:$src2), |
| 217 | "xchg{b} {$src2|$src1}, {$src1|$src2}">; |
| 218 | def XCHG16mr : I<0x87, MRMDestMem, |
| 219 | (ops i16mem:$src1, R16:$src2), |
| 220 | "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; |
| 221 | def XCHG32mr : I<0x87, MRMDestMem, |
| 222 | (ops i32mem:$src1, R32:$src2), |
| 223 | "xchg{l} {$src2|$src1}, {$src1|$src2}">; |
| 224 | def XCHG8rm : I<0x86, MRMSrcMem, |
| 225 | (ops R8:$src1, i8mem:$src2), |
| 226 | "xchg{b} {$src2|$src1}, {$src1|$src2}">; |
| 227 | def XCHG16rm : I<0x87, MRMSrcMem, |
| 228 | (ops R16:$src1, i16mem:$src2), |
| 229 | "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; |
| 230 | def XCHG32rm : I<0x87, MRMSrcMem, |
| 231 | (ops R32:$src1, i32mem:$src2), |
| 232 | "xchg{l} {$src2|$src1}, {$src1|$src2}">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 233 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 234 | def LEA16r : I<0x8D, MRMSrcMem, |
| 235 | (ops R16:$dst, i32mem:$src), |
| 236 | "lea{w} {$src|$dst}, {$dst|$src}">, OpSize; |
| 237 | def LEA32r : I<0x8D, MRMSrcMem, |
| 238 | (ops R32:$dst, i32mem:$src), |
| 239 | "lea{l} {$src|$dst}, {$dst|$src}">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 240 | |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 241 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 242 | def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 243 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 244 | def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 245 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 246 | def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 247 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 248 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 249 | def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 250 | Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 251 | def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 252 | Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; |
John Criswell | 546faca | 2004-11-10 04:48:15 +0000 | [diff] [blame] | 253 | def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 254 | Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; |
| 255 | |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 256 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 257 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 258 | // Input/Output Instructions... |
| 259 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 260 | def IN8rr : I<0xEC, RawFrm, (ops), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 261 | "in{b} {%DX, %AL|AL, DX}">, Imp<[DX], [AL]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 262 | def IN16rr : I<0xED, RawFrm, (ops), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 263 | "in{w} {%DX, %AX|AX, DX}">, Imp<[DX], [AX]>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 264 | def IN32rr : I<0xED, RawFrm, (ops), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 265 | "in{l} {%DX, %EAX|EAX, DX}">, Imp<[DX],[EAX]>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 266 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 267 | def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 268 | "in{b} {$port, %AL|AL, $port}">, Imp<[], [AL]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 269 | def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 270 | "in{w} {$port, %AX|AX, $port}">, Imp<[], [AX]>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 271 | def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 272 | "in{l} {$port, %EAX|EAX, $port}">, Imp<[],[EAX]>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 273 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 274 | def OUT8rr : I<0xEE, RawFrm, (ops), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 275 | "out{b} {%AL, %DX|DX, AL}">, Imp<[DX, AL], []>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 276 | def OUT16rr : I<0xEF, RawFrm, (ops), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 277 | "out{w} {%AX, %DX|DX, AX}">, Imp<[DX, AX], []>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 278 | def OUT32rr : I<0xEF, RawFrm, (ops), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 279 | "out{l} {%EAX, %DX|DX, EAX}">, Imp<[DX, EAX], []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 280 | |
Chris Lattner | 7d620d5 | 2004-08-10 16:22:02 +0000 | [diff] [blame] | 281 | def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 282 | "out{b} {%AL, $port|$port, AL}">, Imp<[AL], []>; |
Chris Lattner | 7d620d5 | 2004-08-10 16:22:02 +0000 | [diff] [blame] | 283 | def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 284 | "out{w} {%AX, $port|$port, AX}">, Imp<[AX], []>, OpSize; |
Chris Lattner | 7d620d5 | 2004-08-10 16:22:02 +0000 | [diff] [blame] | 285 | def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 286 | "out{l} {%EAX, $port|$port, %EAX}">, Imp<[EAX], []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 287 | |
| 288 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 289 | // Move Instructions... |
| 290 | // |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 291 | def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), |
| 292 | "mov{b} {$src, $dst|$dst, $src}">; |
| 293 | def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), |
| 294 | "mov{w} {$src, $dst|$dst, $src}">, OpSize; |
| 295 | def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), |
| 296 | "mov{l} {$src, $dst|$dst, $src}">; |
| 297 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), |
| 298 | "mov{b} {$src, $dst|$dst, $src}">; |
| 299 | def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), |
| 300 | "mov{w} {$src, $dst|$dst, $src}">, OpSize; |
| 301 | def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), |
| 302 | "mov{l} {$src, $dst|$dst, $src}">; |
| 303 | def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), |
| 304 | "mov{b} {$src, $dst|$dst, $src}">; |
| 305 | def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), |
| 306 | "mov{w} {$src, $dst|$dst, $src}">, OpSize; |
| 307 | def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), |
| 308 | "mov{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 309 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 310 | def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), |
| 311 | "mov{b} {$src, $dst|$dst, $src}">; |
| 312 | def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), |
| 313 | "mov{w} {$src, $dst|$dst, $src}">, OpSize; |
| 314 | def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), |
| 315 | "mov{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 316 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 317 | def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), |
| 318 | "mov{b} {$src, $dst|$dst, $src}">; |
| 319 | def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), |
| 320 | "mov{w} {$src, $dst|$dst, $src}">, OpSize; |
| 321 | def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), |
| 322 | "mov{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 323 | |
| 324 | //===----------------------------------------------------------------------===// |
| 325 | // Fixed-Register Multiplication and Division Instructions... |
| 326 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 327 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 328 | // Extra precision multiplication |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 329 | def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 330 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 331 | def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 332 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 333 | def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src">, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 334 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 335 | def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 336 | "mul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 337 | def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 338 | "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 339 | def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 340 | "mul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 341 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 342 | // unsigned division/remainder |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 343 | def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH |
| 344 | "div{b} $src">, Imp<[AX],[AX]>; |
| 345 | def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX |
| 346 | "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; |
| 347 | def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
| 348 | "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; |
| 349 | def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
| 350 | "div{b} $src">, Imp<[AX],[AX]>; |
| 351 | def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
| 352 | "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; |
| 353 | def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
| 354 | "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 355 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 356 | // Signed division/remainder. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 357 | def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH |
| 358 | "idiv{b} $src">, Imp<[AX],[AX]>; |
| 359 | def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX |
| 360 | "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; |
| 361 | def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
| 362 | "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; |
| 363 | def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
| 364 | "idiv{b} $src">, Imp<[AX],[AX]>; |
| 365 | def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
| 366 | "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; |
| 367 | def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
| 368 | "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 369 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 370 | // Sign-extenders for division. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 371 | def CBW : I<0x98, RawFrm, (ops), |
| 372 | "{cbtw|cbw}">, Imp<[AL],[AH]>; // AX = signext(AL) |
| 373 | def CWD : I<0x99, RawFrm, (ops), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 374 | "{cwtd|cwd}">, Imp<[AX],[DX]>; // DX:AX = signext(AX) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 375 | def CDQ : I<0x99, RawFrm, (ops), |
| 376 | "{cltd|cdq}">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 377 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 378 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 379 | //===----------------------------------------------------------------------===// |
| 380 | // Two address Instructions... |
| 381 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 382 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 383 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 384 | // Conditional moves |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 385 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16 |
| 386 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 387 | "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 388 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16] |
| 389 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 390 | "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 391 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32 |
| 392 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 393 | "cmovb {$src2, $dst|$dst, $src2}">, TB; |
| 394 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32] |
| 395 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 396 | "cmovb {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 397 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 398 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 |
| 399 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 400 | "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 401 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] |
| 402 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 403 | "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 404 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 |
| 405 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 406 | "cmovae {$src2, $dst|$dst, $src2}">, TB; |
| 407 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] |
| 408 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 409 | "cmovae {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 410 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 411 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 |
| 412 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 413 | "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 414 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] |
| 415 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 416 | "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 417 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 |
| 418 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 419 | "cmove {$src2, $dst|$dst, $src2}">, TB; |
| 420 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] |
| 421 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 422 | "cmove {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 423 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 424 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 |
| 425 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 426 | "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 427 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] |
| 428 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 429 | "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 430 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 |
| 431 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 432 | "cmovne {$src2, $dst|$dst, $src2}">, TB; |
| 433 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] |
| 434 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 435 | "cmovne {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 436 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 437 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 |
| 438 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 439 | "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 440 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] |
| 441 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 442 | "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 443 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 |
| 444 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 445 | "cmovbe {$src2, $dst|$dst, $src2}">, TB; |
| 446 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] |
| 447 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 448 | "cmovbe {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 449 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 450 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 |
| 451 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 452 | "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 453 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] |
| 454 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 455 | "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 456 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 |
| 457 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 458 | "cmova {$src2, $dst|$dst, $src2}">, TB; |
| 459 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] |
| 460 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 461 | "cmova {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 462 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 463 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 |
| 464 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 465 | "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 466 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] |
| 467 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 468 | "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 469 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 |
| 470 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 471 | "cmovs {$src2, $dst|$dst, $src2}">, TB; |
| 472 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] |
| 473 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 474 | "cmovs {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 475 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 476 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 |
| 477 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 478 | "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 479 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] |
| 480 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 481 | "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 482 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 |
| 483 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 484 | "cmovns {$src2, $dst|$dst, $src2}">, TB; |
| 485 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] |
| 486 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 487 | "cmovns {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 488 | |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 489 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16 |
| 490 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 491 | "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 492 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16] |
| 493 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 494 | "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 495 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32 |
| 496 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 497 | "cmovp {$src2, $dst|$dst, $src2}">, TB; |
| 498 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32] |
| 499 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 500 | "cmovp {$src2, $dst|$dst, $src2}">, TB; |
| 501 | |
| 502 | |
| 503 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16 |
| 504 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 505 | "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 506 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16] |
| 507 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 508 | "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 509 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32 |
| 510 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 511 | "cmovnp {$src2, $dst|$dst, $src2}">, TB; |
| 512 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32] |
| 513 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 514 | "cmovnp {$src2, $dst|$dst, $src2}">, TB; |
| 515 | |
| 516 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 517 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16 |
| 518 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 519 | "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 520 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16] |
| 521 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 522 | "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 523 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32 |
| 524 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 525 | "cmovl {$src2, $dst|$dst, $src2}">, TB; |
| 526 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32] |
| 527 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 528 | "cmovl {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 529 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 530 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 |
| 531 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 532 | "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 533 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] |
| 534 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 535 | "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 536 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 |
| 537 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 538 | "cmovge {$src2, $dst|$dst, $src2}">, TB; |
| 539 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] |
| 540 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 541 | "cmovge {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 542 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 543 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 |
| 544 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 545 | "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 546 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] |
| 547 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 548 | "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 549 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 |
| 550 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 551 | "cmovle {$src2, $dst|$dst, $src2}">, TB; |
| 552 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] |
| 553 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 554 | "cmovle {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 555 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 556 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 |
| 557 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 558 | "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 559 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] |
| 560 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 561 | "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 562 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 |
| 563 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 564 | "cmovg {$src2, $dst|$dst, $src2}">, TB; |
| 565 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] |
| 566 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 567 | "cmovg {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 568 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 569 | // unary instructions |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 570 | def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst">; |
| 571 | def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst">, OpSize; |
| 572 | def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 573 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 574 | def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst">; |
| 575 | def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst">, OpSize; |
| 576 | def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 577 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 578 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 579 | def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst">; |
| 580 | def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst">, OpSize; |
| 581 | def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 582 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 583 | def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst">; |
| 584 | def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst">, OpSize; |
| 585 | def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 586 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 587 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 588 | def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 589 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 590 | def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst">, OpSize; |
| 591 | def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 592 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 593 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 594 | def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst">; |
| 595 | def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst">, OpSize; |
| 596 | def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 597 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 598 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 599 | def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 600 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 601 | def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst">, OpSize; |
| 602 | def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 603 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 604 | |
| 605 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 606 | def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst">; |
| 607 | def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst">, OpSize; |
| 608 | def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 609 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 610 | |
| 611 | // Logical operators... |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 612 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 613 | def AND8rr : I<0x20, MRMDestReg, |
| 614 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
| 615 | "and{b} {$src2, $dst|$dst, $src2}">; |
| 616 | def AND16rr : I<0x21, MRMDestReg, |
| 617 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 618 | "and{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 619 | def AND32rr : I<0x21, MRMDestReg, |
| 620 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 621 | "and{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 622 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 623 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 624 | def AND8rm : I<0x22, MRMSrcMem, |
| 625 | (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
| 626 | "and{b} {$src2, $dst|$dst, $src2}">; |
| 627 | def AND16rm : I<0x23, MRMSrcMem, |
| 628 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 629 | "and{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 630 | def AND32rm : I<0x23, MRMSrcMem, |
| 631 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 632 | "and{l} {$src2, $dst|$dst, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 633 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 634 | def AND8ri : Ii8<0x80, MRM4r, |
| 635 | (ops R8 :$dst, R8 :$src1, i8imm :$src2), |
| 636 | "and{b} {$src2, $dst|$dst, $src2}">; |
| 637 | def AND16ri : Ii16<0x81, MRM4r, |
| 638 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
| 639 | "and{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 640 | def AND32ri : Ii32<0x81, MRM4r, |
| 641 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
| 642 | "and{l} {$src2, $dst|$dst, $src2}">; |
| 643 | def AND16ri8 : Ii8<0x83, MRM4r, |
| 644 | (ops R16:$dst, R16:$src1, i8imm:$src2), |
| 645 | "and{w} {$src2, $dst|$dst, $src2}" >, OpSize; |
| 646 | def AND32ri8 : Ii8<0x83, MRM4r, |
| 647 | (ops R32:$dst, R32:$src1, i8imm:$src2), |
| 648 | "and{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 649 | |
| 650 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 651 | def AND8mr : I<0x20, MRMDestMem, |
| 652 | (ops i8mem :$dst, R8 :$src), |
| 653 | "and{b} {$src, $dst|$dst, $src}">; |
| 654 | def AND16mr : I<0x21, MRMDestMem, |
| 655 | (ops i16mem:$dst, R16:$src), |
| 656 | "and{w} {$src, $dst|$dst, $src}">, OpSize; |
| 657 | def AND32mr : I<0x21, MRMDestMem, |
| 658 | (ops i32mem:$dst, R32:$src), |
| 659 | "and{l} {$src, $dst|$dst, $src}">; |
| 660 | def AND8mi : Ii8<0x80, MRM4m, |
| 661 | (ops i8mem :$dst, i8imm :$src), |
| 662 | "and{b} {$src, $dst|$dst, $src}">; |
| 663 | def AND16mi : Ii16<0x81, MRM4m, |
| 664 | (ops i16mem:$dst, i16imm:$src), |
| 665 | "and{w} {$src, $dst|$dst, $src}">, OpSize; |
| 666 | def AND32mi : Ii32<0x81, MRM4m, |
| 667 | (ops i32mem:$dst, i32imm:$src), |
| 668 | "and{l} {$src, $dst|$dst, $src}">; |
| 669 | def AND16mi8 : Ii8<0x83, MRM4m, |
| 670 | (ops i16mem:$dst, i8imm :$src), |
| 671 | "and{w} {$src, $dst|$dst, $src}">, OpSize; |
| 672 | def AND32mi8 : Ii8<0x83, MRM4m, |
| 673 | (ops i32mem:$dst, i8imm :$src), |
| 674 | "and{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 675 | } |
| 676 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 677 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 678 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 679 | def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 680 | "or{b} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 681 | def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 682 | "or{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 683 | def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 684 | "or{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 685 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 686 | def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 687 | "or{b} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 688 | def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 689 | "or{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 690 | def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 691 | "or{l} {$src2, $dst|$dst, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 692 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 693 | def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 694 | "or{b} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 695 | def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 696 | "or{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 697 | def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 698 | "or{l} {$src2, $dst|$dst, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 699 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 700 | def OR16ri8 : Ii8<0x83, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 701 | "or{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 702 | def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 703 | "or{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 704 | let isTwoAddress = 0 in { |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 705 | def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), |
Chris Lattner | 8f99eff | 2004-10-04 07:23:07 +0000 | [diff] [blame] | 706 | "or{b} {$src, $dst|$dst, $src}">; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 707 | def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Chris Lattner | 8f99eff | 2004-10-04 07:23:07 +0000 | [diff] [blame] | 708 | "or{w} {$src, $dst|$dst, $src}">, OpSize; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 709 | def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Chris Lattner | 8f99eff | 2004-10-04 07:23:07 +0000 | [diff] [blame] | 710 | "or{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 711 | def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Chris Lattner | 8f99eff | 2004-10-04 07:23:07 +0000 | [diff] [blame] | 712 | "or{b} {$src, $dst|$dst, $src}">; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 713 | def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), |
Chris Lattner | 8f99eff | 2004-10-04 07:23:07 +0000 | [diff] [blame] | 714 | "or{w} {$src, $dst|$dst, $src}">, OpSize; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 715 | def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), |
Chris Lattner | 8f99eff | 2004-10-04 07:23:07 +0000 | [diff] [blame] | 716 | "or{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 717 | def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src), |
Chris Lattner | 8f99eff | 2004-10-04 07:23:07 +0000 | [diff] [blame] | 718 | "or{w} {$src, $dst|$dst, $src}">, OpSize; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 719 | def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i8imm:$src), |
Chris Lattner | 8f99eff | 2004-10-04 07:23:07 +0000 | [diff] [blame] | 720 | "or{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 721 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 722 | |
| 723 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 724 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 725 | def XOR8rr : I<0x30, MRMDestReg, |
| 726 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
| 727 | "xor{b} {$src2, $dst|$dst, $src2}">; |
| 728 | def XOR16rr : I<0x31, MRMDestReg, |
| 729 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 730 | "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 731 | def XOR32rr : I<0x31, MRMDestReg, |
| 732 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 733 | "xor{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 734 | } |
| 735 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 736 | def XOR8rm : I<0x32, MRMSrcMem , |
| 737 | (ops R8 :$dst, R8:$src1, i8mem :$src2), |
| 738 | "xor{b} {$src2, $dst|$dst, $src2}">; |
| 739 | def XOR16rm : I<0x33, MRMSrcMem , |
| 740 | (ops R16:$dst, R8:$src1, i16mem:$src2), |
| 741 | "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 742 | def XOR32rm : I<0x33, MRMSrcMem , |
| 743 | (ops R32:$dst, R8:$src1, i32mem:$src2), |
| 744 | "xor{l} {$src2, $dst|$dst, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 745 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 746 | def XOR8ri : Ii8<0x80, MRM6r, |
| 747 | (ops R8:$dst, R8:$src1, i8imm:$src2), |
| 748 | "xor{b} {$src2, $dst|$dst, $src2}">; |
| 749 | def XOR16ri : Ii16<0x81, MRM6r, |
| 750 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
| 751 | "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 752 | def XOR32ri : Ii32<0x81, MRM6r, |
| 753 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
| 754 | "xor{l} {$src2, $dst|$dst, $src2}">; |
| 755 | def XOR16ri8 : Ii8<0x83, MRM6r, |
| 756 | (ops R16:$dst, R16:$src1, i8imm:$src2), |
| 757 | "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 758 | def XOR32ri8 : Ii8<0x83, MRM6r, |
| 759 | (ops R32:$dst, R32:$src1, i8imm:$src2), |
| 760 | "xor{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 761 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 762 | def XOR8mr : I<0x30, MRMDestMem, |
| 763 | (ops i8mem :$dst, R8 :$src), |
| 764 | "xor{b} {$src, $dst|$dst, $src}">; |
| 765 | def XOR16mr : I<0x31, MRMDestMem, |
| 766 | (ops i16mem:$dst, R16:$src), |
| 767 | "xor{w} {$src, $dst|$dst, $src}">, OpSize; |
| 768 | def XOR32mr : I<0x31, MRMDestMem, |
| 769 | (ops i32mem:$dst, R32:$src), |
| 770 | "xor{l} {$src, $dst|$dst, $src}">; |
| 771 | def XOR8mi : Ii8<0x80, MRM6m, |
| 772 | (ops i8mem :$dst, i8imm :$src), |
| 773 | "xor{b} {$src, $dst|$dst, $src}">; |
| 774 | def XOR16mi : Ii16<0x81, MRM6m, |
| 775 | (ops i16mem:$dst, i16imm:$src), |
| 776 | "xor{w} {$src, $dst|$dst, $src}">, OpSize; |
| 777 | def XOR32mi : Ii32<0x81, MRM6m, |
| 778 | (ops i32mem:$dst, i32imm:$src), |
| 779 | "xor{l} {$src, $dst|$dst, $src}">; |
| 780 | def XOR16mi8 : Ii8<0x83, MRM6m, |
| 781 | (ops i16mem:$dst, i8imm :$src), |
| 782 | "xor{w} {$src, $dst|$dst, $src}">, OpSize; |
| 783 | def XOR32mi8 : Ii8<0x83, MRM6m, |
| 784 | (ops i32mem:$dst, i8imm :$src), |
| 785 | "xor{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 786 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 787 | |
| 788 | // Shift instructions |
Alkis Evlogimenos | 13d362f | 2004-03-07 03:19:11 +0000 | [diff] [blame] | 789 | // FIXME: provide shorter instructions when imm8 == 1 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 790 | def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 791 | "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 792 | def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 793 | "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 794 | def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 795 | "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 796 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 797 | def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 798 | "shl{b} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 799 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 800 | def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 801 | "shl{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 802 | def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 803 | "shl{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 804 | } |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 805 | |
| 806 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 807 | def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 808 | "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 809 | def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 810 | "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 811 | def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 812 | "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 813 | def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), |
| 814 | "shl{b} {$src, $dst|$dst, $src}">; |
| 815 | def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), |
| 816 | "shl{w} {$src, $dst|$dst, $src}">, OpSize; |
| 817 | def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), |
| 818 | "shl{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 819 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 820 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 821 | def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 822 | "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 823 | def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 824 | "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 825 | def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 826 | "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 827 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 828 | def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
| 829 | "shr{b} {$src2, $dst|$dst, $src2}">; |
| 830 | def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
| 831 | "shr{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 832 | def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
| 833 | "shr{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 834 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 835 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 836 | def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 837 | "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 838 | def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 839 | "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 840 | def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 841 | "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 842 | def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), |
| 843 | "shr{b} {$src, $dst|$dst, $src}">; |
| 844 | def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), |
| 845 | "shr{w} {$src, $dst|$dst, $src}">, OpSize; |
| 846 | def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), |
| 847 | "shr{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 848 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 849 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 850 | def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 851 | "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 852 | def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 853 | "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 854 | def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 855 | "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 856 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 857 | def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 858 | "sar{b} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 859 | def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 860 | "sar{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 861 | def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 862 | "sar{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 863 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 864 | def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 865 | "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 866 | def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 867 | "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 868 | def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 869 | "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 870 | def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), |
| 871 | "sar{b} {$src, $dst|$dst, $src}">; |
| 872 | def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), |
| 873 | "sar{w} {$src, $dst|$dst, $src}">, OpSize; |
| 874 | def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), |
| 875 | "sar{l} {$src, $dst|$dst, $src}">; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 876 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 877 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 878 | def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 879 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 880 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 881 | def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 882 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 883 | Imp<[CL],[]>, TB; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame^] | 884 | |
| 885 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 886 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
| 887 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
| 888 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; |
| 889 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
| 890 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
| 891 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame^] | 892 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 893 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 894 | let isTwoAddress = 0 in { |
| 895 | def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 896 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 897 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 898 | def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 899 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 900 | Imp<[CL],[]>, TB; |
| 901 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
| 902 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
| 903 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; |
| 904 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
| 905 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
| 906 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 907 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 908 | |
| 909 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 910 | // Arithmetic. |
| 911 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 912 | def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
| 913 | "add{b} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 914 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 915 | def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
| 916 | "add{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 917 | def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
| 918 | "add{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 919 | } // end isConvertibleToThreeAddress |
| 920 | } // end isCommutable |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 921 | def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
| 922 | "add{b} {$src2, $dst|$dst, $src2}">; |
| 923 | def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 924 | "add{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 925 | def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 926 | "add{l} {$src2, $dst|$dst, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 927 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 928 | def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
| 929 | "add{b} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 930 | |
| 931 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 932 | def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
| 933 | "add{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 934 | def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
| 935 | "add{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 936 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 937 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 938 | def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
| 939 | "add{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 940 | def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
| 941 | "add{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 942 | |
| 943 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 944 | def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
| 945 | "add{b} {$src2, $dst|$dst, $src2}">; |
| 946 | def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
| 947 | "add{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 948 | def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
| 949 | "add{l} {$src2, $dst|$dst, $src2}">; |
| 950 | def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), |
| 951 | "add{b} {$src2, $dst|$dst, $src2}">; |
| 952 | def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), |
| 953 | "add{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 954 | def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), |
| 955 | "add{l} {$src2, $dst|$dst, $src2}">; |
| 956 | def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2), |
| 957 | "add{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 958 | def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i8imm :$src2), |
| 959 | "add{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 960 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 961 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 962 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 963 | def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
| 964 | "adc{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 965 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 966 | def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 967 | "adc{l} {$src2, $dst|$dst, $src2}">; |
| 968 | def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
| 969 | "adc{l} {$src2, $dst|$dst, $src2}">; |
| 970 | def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
| 971 | "adc{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 972 | |
| 973 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 974 | def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
| 975 | "adc{l} {$src2, $dst|$dst, $src2}">; |
| 976 | def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), |
| 977 | "adc{l} {$src2, $dst|$dst, $src2}">; |
| 978 | def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2), |
| 979 | "adc{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 980 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 981 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 982 | def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
| 983 | "sub{b} {$src2, $dst|$dst, $src2}">; |
| 984 | def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
| 985 | "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 986 | def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
| 987 | "sub{l} {$src2, $dst|$dst, $src2}">; |
| 988 | def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
| 989 | "sub{b} {$src2, $dst|$dst, $src2}">; |
| 990 | def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 991 | "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 992 | def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 993 | "sub{l} {$src2, $dst|$dst, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 994 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 995 | def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 996 | "sub{b} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 997 | def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 998 | "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 999 | def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1000 | "sub{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1001 | def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1002 | "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1003 | def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1004 | "sub{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1005 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1006 | def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
| 1007 | "sub{b} {$src2, $dst|$dst, $src2}">; |
| 1008 | def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
| 1009 | "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 1010 | def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
| 1011 | "sub{l} {$src2, $dst|$dst, $src2}">; |
| 1012 | def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), |
| 1013 | "sub{b} {$src2, $dst|$dst, $src2}">; |
| 1014 | def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), |
| 1015 | "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 1016 | def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), |
| 1017 | "sub{l} {$src2, $dst|$dst, $src2}">; |
| 1018 | def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2), |
| 1019 | "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 1020 | def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i8imm :$src2), |
| 1021 | "sub{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1022 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1023 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1024 | def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1025 | "sbb{l} {$src2, $dst|$dst, $src2}">; |
| 1026 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1027 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1028 | def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
| 1029 | "sbb{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1030 | def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), |
| 1031 | "sbb{b} {$src2, $dst|$dst, $src2}">; |
| 1032 | def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), |
| 1033 | "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1034 | def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), |
| 1035 | "sbb{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1036 | def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2), |
| 1037 | "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1038 | def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2), |
| 1039 | "sbb{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1040 | } |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1041 | def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
| 1042 | "sbb{b} {$src2, $dst|$dst, $src2}">; |
| 1043 | def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
| 1044 | "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; |
| 1045 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1046 | def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1047 | "sbb{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1048 | def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1049 | "sbb{l} {$src2, $dst|$dst, $src2}">; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1050 | |
Chris Lattner | 09c750f | 2004-10-06 14:31:50 +0000 | [diff] [blame] | 1051 | def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
| 1052 | "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1053 | def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1054 | "sbb{l} {$src2, $dst|$dst, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1055 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1056 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1057 | def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), |
| 1058 | "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 1059 | def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), |
| 1060 | "imul{l} {$src2, $dst|$dst, $src2}">, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1061 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1062 | def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 1063 | "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize; |
| 1064 | def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 1065 | "imul{l} {$src2, $dst|$dst, $src2}">, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1066 | |
| 1067 | } // end Two Address instructions |
| 1068 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1069 | // Suprisingly enough, these are not two address instructions! |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1070 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16 |
| 1071 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
| 1072 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, |
| 1073 | OpSize; |
| 1074 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32 |
| 1075 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
| 1076 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">; |
| 1077 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8 |
| 1078 | (ops R16:$dst, R16:$src1, i8imm:$src2), |
| 1079 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize; |
| 1080 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 |
| 1081 | (ops R32:$dst, R32:$src1, i8imm:$src2), |
| 1082 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1083 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1084 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 |
| 1085 | (ops R32:$dst, i16mem:$src1, i16imm:$src2), |
| 1086 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize; |
| 1087 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32 |
| 1088 | (ops R32:$dst, i32mem:$src1, i32imm:$src2), |
| 1089 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">; |
| 1090 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8 |
| 1091 | (ops R32:$dst, i16mem:$src1, i8imm :$src2), |
| 1092 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize; |
| 1093 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 |
| 1094 | (ops R32:$dst, i32mem:$src1, i8imm: $src2), |
| 1095 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1096 | |
| 1097 | //===----------------------------------------------------------------------===// |
| 1098 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1099 | // |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1100 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1101 | def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1102 | "test{b} {$src2, $src1|$src1, $src2}">; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1103 | def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1104 | "test{w} {$src2, $src1|$src1, $src2}">, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1105 | def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1106 | "test{l} {$src2, $src1|$src1, $src2}">; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1107 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1108 | def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1109 | "test{b} {$src2, $src1|$src1, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1110 | def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1111 | "test{w} {$src2, $src1|$src1, $src2}">, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1112 | def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1113 | "test{l} {$src2, $src1|$src1, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1114 | def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1115 | "test{b} {$src2, $src1|$src1, $src2}">; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1116 | def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1117 | "test{w} {$src2, $src1|$src1, $src2}">, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1118 | def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1119 | "test{l} {$src2, $src1|$src1, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1120 | |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1121 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 |
| 1122 | (ops R8:$src1, i8imm:$src2), |
| 1123 | "test{b} {$src2, $src1|$src1, $src2}">; |
| 1124 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16 |
| 1125 | (ops R16:$src1, i16imm:$src2), |
| 1126 | "test{w} {$src2, $src1|$src1, $src2}">, OpSize; |
| 1127 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32 |
| 1128 | (ops R32:$src1, i32imm:$src2), |
| 1129 | "test{l} {$src2, $src1|$src1, $src2}">; |
| 1130 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
| 1131 | (ops i32mem:$src1, i8imm:$src2), |
| 1132 | "test{b} {$src2, $src1|$src1, $src2}">; |
| 1133 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
| 1134 | (ops i16mem:$src1, i16imm:$src2), |
| 1135 | "test{w} {$src2, $src1|$src1, $src2}">, OpSize; |
| 1136 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
| 1137 | (ops i32mem:$src1, i32imm:$src2), |
| 1138 | "test{l} {$src2, $src1|$src1, $src2}">; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1139 | |
| 1140 | |
| 1141 | |
| 1142 | // Condition code ops, incl. set if equal/not equal/... |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 1143 | def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH |
| 1144 | def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1145 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1146 | def SETBr : I<0x92, MRM0r, |
| 1147 | (ops R8 :$dst), "setb $dst">, TB; // R8 = < unsign |
| 1148 | def SETBm : I<0x92, MRM0m, |
| 1149 | (ops i8mem:$dst), "setb $dst">, TB; // [mem8] = < unsign |
| 1150 | def SETAEr : I<0x93, MRM0r, |
| 1151 | (ops R8 :$dst), "setae $dst">, TB; // R8 = >= unsign |
| 1152 | def SETAEm : I<0x93, MRM0m, |
| 1153 | (ops i8mem:$dst), "setae $dst">, TB; // [mem8] = >= unsign |
| 1154 | def SETEr : I<0x94, MRM0r, |
| 1155 | (ops R8 :$dst), "sete $dst">, TB; // R8 = == |
| 1156 | def SETEm : I<0x94, MRM0m, |
| 1157 | (ops i8mem:$dst), "sete $dst">, TB; // [mem8] = == |
| 1158 | def SETNEr : I<0x95, MRM0r, |
| 1159 | (ops R8 :$dst), "setne $dst">, TB; // R8 = != |
| 1160 | def SETNEm : I<0x95, MRM0m, |
| 1161 | (ops i8mem:$dst), "setne $dst">, TB; // [mem8] = != |
| 1162 | def SETBEr : I<0x96, MRM0r, |
| 1163 | (ops R8 :$dst), "setbe $dst">, TB; // R8 = <= unsign |
| 1164 | def SETBEm : I<0x96, MRM0m, |
| 1165 | (ops i8mem:$dst), "setbe $dst">, TB; // [mem8] = <= unsign |
| 1166 | def SETAr : I<0x97, MRM0r, |
| 1167 | (ops R8 :$dst), "seta $dst">, TB; // R8 = > signed |
| 1168 | def SETAm : I<0x97, MRM0m, |
| 1169 | (ops i8mem:$dst), "seta $dst">, TB; // [mem8] = > signed |
| 1170 | def SETSr : I<0x98, MRM0r, |
| 1171 | (ops R8 :$dst), "sets $dst">, TB; // R8 = <sign bit> |
| 1172 | def SETSm : I<0x98, MRM0m, |
| 1173 | (ops i8mem:$dst), "sets $dst">, TB; // [mem8] = <sign bit> |
| 1174 | def SETNSr : I<0x99, MRM0r, |
| 1175 | (ops R8 :$dst), "setns $dst">, TB; // R8 = !<sign bit> |
| 1176 | def SETNSm : I<0x99, MRM0m, |
| 1177 | (ops i8mem:$dst), "setns $dst">, TB; // [mem8] = !<sign bit> |
| 1178 | def SETPr : I<0x9A, MRM0r, |
| 1179 | (ops R8 :$dst), "setp $dst">, TB; // R8 = parity |
| 1180 | def SETPm : I<0x9A, MRM0m, |
| 1181 | (ops i8mem:$dst), "setp $dst">, TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1182 | def SETNPr : I<0x9B, MRM0r, |
| 1183 | (ops R8 :$dst), "setnp $dst">, TB; // R8 = not parity |
| 1184 | def SETNPm : I<0x9B, MRM0m, |
| 1185 | (ops i8mem:$dst), "setnp $dst">, TB; // [mem8] = not parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1186 | def SETLr : I<0x9C, MRM0r, |
| 1187 | (ops R8 :$dst), "setl $dst">, TB; // R8 = < signed |
| 1188 | def SETLm : I<0x9C, MRM0m, |
| 1189 | (ops i8mem:$dst), "setl $dst">, TB; // [mem8] = < signed |
| 1190 | def SETGEr : I<0x9D, MRM0r, |
| 1191 | (ops R8 :$dst), "setge $dst">, TB; // R8 = >= signed |
| 1192 | def SETGEm : I<0x9D, MRM0m, |
| 1193 | (ops i8mem:$dst), "setge $dst">, TB; // [mem8] = >= signed |
| 1194 | def SETLEr : I<0x9E, MRM0r, |
| 1195 | (ops R8 :$dst), "setle $dst">, TB; // R8 = <= signed |
| 1196 | def SETLEm : I<0x9E, MRM0m, |
| 1197 | (ops i8mem:$dst), "setle $dst">, TB; // [mem8] = <= signed |
| 1198 | def SETGr : I<0x9F, MRM0r, |
| 1199 | (ops R8 :$dst), "setg $dst">, TB; // R8 = < signed |
| 1200 | def SETGm : I<0x9F, MRM0m, |
| 1201 | (ops i8mem:$dst), "setg $dst">, TB; // [mem8] = < signed |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1202 | |
| 1203 | // Integer comparisons |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1204 | def CMP8rr : I<0x38, MRMDestReg, |
| 1205 | (ops R8 :$src1, R8 :$src2), |
| 1206 | "cmp{b} {$src2, $src1|$src1, $src2}">; |
| 1207 | def CMP16rr : I<0x39, MRMDestReg, |
| 1208 | (ops R16:$src1, R16:$src2), |
| 1209 | "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; |
| 1210 | def CMP32rr : I<0x39, MRMDestReg, |
| 1211 | (ops R32:$src1, R32:$src2), |
| 1212 | "cmp{l} {$src2, $src1|$src1, $src2}">; |
| 1213 | def CMP8mr : I<0x38, MRMDestMem, |
| 1214 | (ops i8mem :$src1, R8 :$src2), |
| 1215 | "cmp{b} {$src2, $src1|$src1, $src2}">; |
| 1216 | def CMP16mr : I<0x39, MRMDestMem, |
| 1217 | (ops i16mem:$src1, R16:$src2), |
| 1218 | "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; |
| 1219 | def CMP32mr : I<0x39, MRMDestMem, |
| 1220 | (ops i32mem:$src1, R32:$src2), |
| 1221 | "cmp{l} {$src2, $src1|$src1, $src2}">; |
| 1222 | def CMP8rm : I<0x3A, MRMSrcMem, |
| 1223 | (ops R8 :$src1, i8mem :$src2), |
| 1224 | "cmp{b} {$src2, $src1|$src1, $src2}">; |
| 1225 | def CMP16rm : I<0x3B, MRMSrcMem, |
| 1226 | (ops R16:$src1, i16mem:$src2), |
| 1227 | "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; |
| 1228 | def CMP32rm : I<0x3B, MRMSrcMem, |
| 1229 | (ops R32:$src1, i32mem:$src2), |
| 1230 | "cmp{l} {$src2, $src1|$src1, $src2}">; |
| 1231 | def CMP8ri : Ii8<0x80, MRM7r, |
| 1232 | (ops R16:$src1, i8imm:$src2), |
| 1233 | "cmp{b} {$src2, $src1|$src1, $src2}">; |
| 1234 | def CMP16ri : Ii16<0x81, MRM7r, |
| 1235 | (ops R16:$src1, i16imm:$src2), |
| 1236 | "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; |
| 1237 | def CMP32ri : Ii32<0x81, MRM7r, |
| 1238 | (ops R32:$src1, i32imm:$src2), |
| 1239 | "cmp{l} {$src2, $src1|$src1, $src2}">; |
| 1240 | def CMP8mi : Ii8 <0x80, MRM7m, |
| 1241 | (ops i8mem :$src1, i8imm :$src2), |
| 1242 | "cmp{b} {$src2, $src1|$src1, $src2}">; |
| 1243 | def CMP16mi : Ii16<0x81, MRM7m, |
| 1244 | (ops i16mem:$src1, i16imm:$src2), |
| 1245 | "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; |
| 1246 | def CMP32mi : Ii32<0x81, MRM7m, |
| 1247 | (ops i32mem:$src1, i32imm:$src2), |
| 1248 | "cmp{l} {$src2, $src1|$src1, $src2}">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1249 | |
| 1250 | // Sign/Zero extenders |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1251 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), |
| 1252 | "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; |
| 1253 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
| 1254 | "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; |
| 1255 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), |
| 1256 | "movs{bl|x} {$src, $dst|$dst, $src}">, TB; |
| 1257 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
| 1258 | "movs{bl|x} {$src, $dst|$dst, $src}">, TB; |
| 1259 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), |
| 1260 | "movs{wl|x} {$src, $dst|$dst, $src}">, TB; |
| 1261 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
| 1262 | "movs{wl|x} {$src, $dst|$dst, $src}">, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 1263 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1264 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), |
| 1265 | "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; |
| 1266 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
| 1267 | "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; |
| 1268 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), |
| 1269 | "movz{bl|x} {$src, $dst|$dst, $src}">, TB; |
| 1270 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
| 1271 | "movz{bl|x} {$src, $dst|$dst, $src}">, TB; |
| 1272 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), |
| 1273 | "movz{wl|x} {$src, $dst|$dst, $src}">, TB; |
| 1274 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
| 1275 | "movz{wl|x} {$src, $dst|$dst, $src}">, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1276 | |
| 1277 | |
| 1278 | //===----------------------------------------------------------------------===// |
| 1279 | // Floating point support |
| 1280 | //===----------------------------------------------------------------------===// |
| 1281 | |
| 1282 | // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP' |
| 1283 | |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 1284 | // Floating point instruction template |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1285 | class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm> |
Chris Lattner | c96bb81 | 2004-08-11 07:12:04 +0000 | [diff] [blame] | 1286 | : X86Inst<o, F, NoImm, ops, asm> { |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 1287 | let FPForm = fp; let FPFormBits = FPForm.Value; |
| 1288 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1289 | |
Chris Lattner | 9f8fd6d | 2004-02-02 19:31:38 +0000 | [diff] [blame] | 1290 | // Pseudo instructions for floating point. We use these pseudo instructions |
| 1291 | // because they can be expanded by the fp spackifier into one of many different |
| 1292 | // forms of instructions for doing these operations. Until the stackifier runs, |
| 1293 | // we prefer to be abstract. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1294 | def FpMOV : FPI<0, Pseudo, SpecialFP, |
| 1295 | (ops RFP, RFP), "">; // f1 = fmov f2 |
| 1296 | def FpADD : FPI<0, Pseudo, TwoArgFP , |
| 1297 | (ops RFP, RFP, RFP), "">; // f1 = fadd f2, f3 |
| 1298 | def FpSUB : FPI<0, Pseudo, TwoArgFP , |
| 1299 | (ops RFP, RFP, RFP), "">; // f1 = fsub f2, f3 |
| 1300 | def FpMUL : FPI<0, Pseudo, TwoArgFP , |
| 1301 | (ops RFP, RFP, RFP), "">; // f1 = fmul f2, f3 |
| 1302 | def FpDIV : FPI<0, Pseudo, TwoArgFP , |
| 1303 | (ops RFP, RFP, RFP), "">; // f1 = fdiv f2, f3 |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1304 | |
Alkis Evlogimenos | 93c1ab2 | 2004-09-08 18:29:31 +0000 | [diff] [blame] | 1305 | def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">, |
| 1306 | Imp<[ST0], []>; // FPR = ST(0) |
Alkis Evlogimenos | 978f629 | 2004-09-08 16:54:54 +0000 | [diff] [blame] | 1307 | |
Alkis Evlogimenos | 93c1ab2 | 2004-09-08 18:29:31 +0000 | [diff] [blame] | 1308 | def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">, |
| 1309 | Imp<[], [ST0]>; // ST(0) = FPR |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1310 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1311 | // FADD reg, mem: Before stackification, these are represented by: |
| 1312 | // R1 = FADD* R2, [mem] |
| 1313 | def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real] |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1314 | (ops f32mem:$src), "fadd{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1315 | def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real] |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1316 | (ops f64mem:$src), "fadd{l} $src">; |
| 1317 | //def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int] |
| 1318 | //def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int] |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1319 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1320 | // FMUL reg, mem: Before stackification, these are represented by: |
| 1321 | // R1 = FMUL* R2, [mem] |
| 1322 | def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real] |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1323 | (ops f32mem:$src), "fmul{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1324 | def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real] |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1325 | (ops f64mem:$src), "fmul{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1326 | // ST(0) = ST(0) * [mem16int] |
| 1327 | //def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>; |
| 1328 | // ST(0) = ST(0) * [mem32int] |
| 1329 | //def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1330 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1331 | // FSUB reg, mem: Before stackification, these are represented by: |
| 1332 | // R1 = FSUB* R2, [mem] |
| 1333 | def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real] |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1334 | (ops f32mem:$src), "fsub{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1335 | def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real] |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1336 | (ops f64mem:$src), "fsub{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1337 | // ST(0) = ST(0) - [mem16int] |
| 1338 | //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; |
| 1339 | // ST(0) = ST(0) - [mem32int] |
| 1340 | //def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1341 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1342 | // FSUBR reg, mem: Before stackification, these are represented by: |
| 1343 | // R1 = FSUBR* R2, [mem] |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1344 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1345 | // Note that the order of operands does not reflect the operation being |
| 1346 | // performed. |
| 1347 | def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0) |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1348 | (ops f32mem:$src), "fsubr{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1349 | def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0) |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1350 | (ops f64mem:$src), "fsubr{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1351 | // ST(0) = [mem16int] - ST(0) |
| 1352 | //def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>; |
| 1353 | // ST(0) = [mem32int] - ST(0) |
| 1354 | //def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1355 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1356 | // FDIV reg, mem: Before stackification, these are represented by: |
| 1357 | // R1 = FDIV* R2, [mem] |
| 1358 | def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real] |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1359 | (ops f32mem:$src), "fdiv{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1360 | def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real] |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1361 | (ops f64mem:$src), "fdiv{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1362 | // ST(0) = ST(0) / [mem16int] |
| 1363 | //def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>; |
| 1364 | // ST(0) = ST(0) / [mem32int] |
| 1365 | //def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>; |
| 1366 | |
| 1367 | // FDIVR reg, mem: Before stackification, these are represented by: |
| 1368 | // R1 = FDIVR* R2, [mem] |
| 1369 | // Note that the order of operands does not reflect the operation being |
| 1370 | // performed. |
| 1371 | def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0) |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1372 | (ops f32mem:$src), "fdivr{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1373 | def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0) |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1374 | (ops f64mem:$src), "fdivr{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1375 | // ST(0) = [mem16int] / ST(0) |
| 1376 | //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; |
| 1377 | // ST(0) = [mem32int] / ST(0) |
| 1378 | //def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1379 | |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 1380 | |
| 1381 | // Floating point cmovs... |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1382 | let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in { |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1383 | def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1384 | (ops RST:$op), "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1385 | def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1386 | (ops RST:$op), "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1387 | def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1388 | (ops RST:$op), "fcmove {$op, %ST(0)|%ST(0), $op}">, DA; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1389 | def FCMOVP : FPI<0xD8, AddRegFrm, CondMovFP, |
| 1390 | (ops RST:$op), "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1391 | def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1392 | (ops RST:$op), "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1393 | def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1394 | (ops RST:$op), "fcmova {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1395 | def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1396 | (ops RST:$op), "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1397 | def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP, |
| 1398 | (ops RST:$op), "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 1399 | } |
| 1400 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1401 | // Floating point loads & stores... |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 1402 | def FLDrr : FPI<0xC0, AddRegFrm, NotFP, (ops RST:$src), "fld $src">, D9; |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1403 | def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP, (ops f32mem:$src), "fld{s} $src">; |
| 1404 | def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP, (ops f64mem:$src), "fld{l} $src">; |
| 1405 | def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP, (ops f80mem:$src), "fld{t} $src">; |
| 1406 | def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP, (ops i16mem:$src), "fild{s} $src">; |
| 1407 | def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP, (ops i32mem:$src), "fild{l} $src">; |
Chris Lattner | ac6a475 | 2004-10-04 05:20:16 +0000 | [diff] [blame] | 1408 | def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP, (ops i64mem:$src), "fild{ll} $src">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1409 | |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 1410 | def FSTrr : FPI<0xD0, AddRegFrm, NotFP, (ops RST:$op), "fst $op">, DD; |
| 1411 | def FSTPrr : FPI<0xD8, AddRegFrm, NotFP, (ops RST:$op), "fstp $op">, DD; |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1412 | def FST32m : FPI<0xD9, MRM2m, OneArgFP, (ops f32mem:$op), "fst{s} $op">; |
| 1413 | def FST64m : FPI<0xDD, MRM2m, OneArgFP, (ops f64mem:$op), "fst{l} $op">; |
| 1414 | def FSTP32m : FPI<0xD9, MRM3m, OneArgFP, (ops f32mem:$op), "fstp{s} $op">; |
| 1415 | def FSTP64m : FPI<0xDD, MRM3m, OneArgFP, (ops f64mem:$op), "fstp{l} $op">; |
| 1416 | def FSTP80m : FPI<0xDB, MRM7m, OneArgFP, (ops f80mem:$op), "fstp{t} $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1417 | |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1418 | def FIST16m : FPI<0xDF, MRM2m , OneArgFP, (ops i16mem:$op), "fist{s} $op">; |
| 1419 | def FIST32m : FPI<0xDB, MRM2m , OneArgFP, (ops i32mem:$op), "fist{l} $op">; |
| 1420 | def FISTP16m : FPI<0xDF, MRM3m , NotFP , (ops i16mem:$op), "fistp{s} $op">; |
| 1421 | def FISTP32m : FPI<0xDB, MRM3m , NotFP , (ops i32mem:$op), "fistp{l} $op">; |
| 1422 | def FISTP64m : FPI<0xDF, MRM7m , OneArgFP, (ops i64mem:$op), "fistp{ll} $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1423 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1424 | def FXCH : FPI<0xC8, AddRegFrm, NotFP, |
| 1425 | (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0) |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1426 | |
| 1427 | // Floating point constant loads... |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1428 | def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops), "fldz">, D9; |
| 1429 | def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops), "fld1">, D9; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1430 | |
Chris Lattner | 9f8fd6d | 2004-02-02 19:31:38 +0000 | [diff] [blame] | 1431 | |
Chris Lattner | 3b904eb | 2004-02-03 07:27:50 +0000 | [diff] [blame] | 1432 | // Unary operations... |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1433 | def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, (ops), "fchs">, D9; // f1 = fchs f2 |
| 1434 | def FTST : FPI<0xE4, RawFrm, OneArgFP, (ops), "ftst">, D9; // ftst ST(0) |
Chris Lattner | 3b904eb | 2004-02-03 07:27:50 +0000 | [diff] [blame] | 1435 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1436 | // Binary arithmetic operations... |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1437 | class FPST0rInst<bits<8> o, dag ops, string asm> |
| 1438 | : I<o, AddRegFrm, ops, asm>, D8 { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1439 | list<Register> Uses = [ST0]; |
| 1440 | list<Register> Defs = [ST0]; |
| 1441 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1442 | class FPrST0Inst<bits<8> o, dag ops, string asm> |
| 1443 | : I<o, AddRegFrm, ops, asm>, DC { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1444 | list<Register> Uses = [ST0]; |
| 1445 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1446 | class FPrST0PInst<bits<8> o, dag ops, string asm> |
| 1447 | : I<o, AddRegFrm, ops, asm>, DE { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1448 | list<Register> Uses = [ST0]; |
| 1449 | } |
| 1450 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1451 | def FADDST0r : FPST0rInst <0xC0, (ops RST:$op), |
| 1452 | "fadd $op">; |
| 1453 | def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op), |
| 1454 | "fadd {%ST(0), $op|$op, %ST(0)}">; |
| 1455 | def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op), |
| 1456 | "faddp $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1457 | |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1458 | // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion |
| 1459 | // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, |
| 1460 | // we have to put some 'r's in and take them out of wierd places. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1461 | def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op), |
| 1462 | "fsubr $op">; |
| 1463 | def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1464 | "fsub{r} {%ST(0), $op|$op, %ST(0)}">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1465 | def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1466 | "fsub{r}p $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1467 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1468 | def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op), |
| 1469 | "fsub $op">; |
| 1470 | def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1471 | "fsub{|r} {%ST(0), $op|$op, %ST(0)}">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1472 | def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1473 | "fsub{|r}p $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1474 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1475 | def FMULST0r : FPST0rInst <0xC8, (ops RST:$op), |
| 1476 | "fmul $op">; |
| 1477 | def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op), |
| 1478 | "fmul {%ST(0), $op|$op, %ST(0)}">; |
| 1479 | def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op), |
| 1480 | "fmulp $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1481 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1482 | def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op), |
| 1483 | "fdivr $op">; |
| 1484 | def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1485 | "fdiv{r} {%ST(0), $op|$op, %ST(0)}">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1486 | def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1487 | "fdiv{r}p $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1488 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1489 | def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i) |
| 1490 | "fdiv $op">; |
| 1491 | def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i) |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1492 | "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1493 | def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 1494 | "fdiv{|r}p $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1495 | |
| 1496 | // Floating point compares |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1497 | def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i) |
| 1498 | (ops RST:$reg), |
| 1499 | "fucom $reg">, DD, Imp<[ST0],[]>; |
| 1500 | def FUCOMPr : I<0xE8, AddRegFrm, |
| 1501 | (ops RST:$reg), // FPSW = cmp ST(0) with ST(i), pop |
| 1502 | "fucomp $reg">, DD, Imp<[ST0],[]>; |
| 1503 | def FUCOMPPr : I<0xE9, RawFrm, |
| 1504 | (ops), // cmp ST(0) with ST(1), pop, pop |
| 1505 | "fucompp">, DA, Imp<[ST0],[]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1506 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1507 | def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i) |
| 1508 | (ops RST:$reg), |
| 1509 | "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; |
| 1510 | def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop |
| 1511 | (ops RST:$reg), |
| 1512 | "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1513 | |
Chris Lattner | a1b5e16 | 2004-04-12 01:38:55 +0000 | [diff] [blame] | 1514 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 1515 | // Floating point flag ops |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1516 | def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags |
| 1517 | (ops), "fnstsw">, DF, Imp<[],[AX]>; |
Chris Lattner | 96563df | 2004-08-01 06:01:00 +0000 | [diff] [blame] | 1518 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1519 | def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world |
| 1520 | (ops i16mem:$dst), "fnstcw $dst">; |
| 1521 | def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] |
| 1522 | (ops i16mem:$dst), "fldcw $dst">; |