Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 16 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 17 | // |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 18 | class X86MemOperand<ValueType Ty, string printMethod> : Operand<Ty> { |
| 19 | let PrintMethod = printMethod; |
Chris Lattner | 6adaf79 | 2005-11-19 07:01:30 +0000 | [diff] [blame] | 20 | let NumMIOperands = 4; |
| 21 | let MIOperandInfo = (ops R32, i8imm, R32, i32imm); |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 22 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 23 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 24 | def i8mem : X86MemOperand<i32, "printi8mem">; |
| 25 | def i16mem : X86MemOperand<i32, "printi16mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 26 | def i32mem : X86MemOperand<i32, "printi32mem">; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 27 | def i64mem : X86MemOperand<i32, "printi64mem">; |
| 28 | def f32mem : X86MemOperand<i32, "printf32mem">; |
| 29 | def f64mem : X86MemOperand<i32, "printf64mem">; |
| 30 | def f80mem : X86MemOperand<i32, "printf80mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 31 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 32 | def SSECC : Operand<i8> { |
| 33 | let PrintMethod = "printSSECC"; |
| 34 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 35 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 36 | // A couple of more descriptive operand definitions. |
| 37 | // 16-bits but only 8 bits are significant. |
| 38 | def i16i8imm : Operand<i16>; |
| 39 | // 32-bits but only 8 bits are significant. |
| 40 | def i32i8imm : Operand<i32>; |
| 41 | |
Chris Lattner | e4ead0c | 2004-08-11 06:59:12 +0000 | [diff] [blame] | 42 | // PCRelative calls need special operand formatting. |
| 43 | let PrintMethod = "printCallOperand" in |
| 44 | def calltarget : Operand<i32>; |
| 45 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 46 | // Branch targets have OtherVT type. |
| 47 | def brtarget : Operand<OtherVT>; |
| 48 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 49 | // Define X86 specific addressing mode. |
Evan Cheng | 670fd8f | 2005-12-08 02:15:07 +0000 | [diff] [blame] | 50 | def addr : ComplexPattern<i32, 4, "SelectAddr", []>; |
| 51 | def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr", [add]>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 52 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 53 | // Format specifies the encoding used by the instruction. This is part of the |
| 54 | // ad-hoc solution used to emit machine instruction encodings by our machine |
| 55 | // code emitter. |
| 56 | class Format<bits<5> val> { |
| 57 | bits<5> Value = val; |
| 58 | } |
| 59 | |
| 60 | def Pseudo : Format<0>; def RawFrm : Format<1>; |
| 61 | def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; |
| 62 | def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; |
| 63 | def MRMSrcMem : Format<6>; |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 64 | def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; |
| 65 | def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; |
| 66 | def MRM6r : Format<22>; def MRM7r : Format<23>; |
| 67 | def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; |
| 68 | def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; |
| 69 | def MRM6m : Format<30>; def MRM7m : Format<31>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 70 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 71 | // ImmType - This specifies the immediate type used by an instruction. This is |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 72 | // part of the ad-hoc solution used to emit machine instruction encodings by our |
| 73 | // machine code emitter. |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 74 | class ImmType<bits<2> val> { |
| 75 | bits<2> Value = val; |
| 76 | } |
| 77 | def NoImm : ImmType<0>; |
| 78 | def Imm8 : ImmType<1>; |
| 79 | def Imm16 : ImmType<2>; |
| 80 | def Imm32 : ImmType<3>; |
| 81 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 82 | // FPFormat - This specifies what form this FP instruction has. This is used by |
| 83 | // the Floating-Point stackifier pass. |
| 84 | class FPFormat<bits<3> val> { |
| 85 | bits<3> Value = val; |
| 86 | } |
| 87 | def NotFP : FPFormat<0>; |
| 88 | def ZeroArgFP : FPFormat<1>; |
| 89 | def OneArgFP : FPFormat<2>; |
| 90 | def OneArgFPRW : FPFormat<3>; |
| 91 | def TwoArgFP : FPFormat<4>; |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 92 | def CompareFP : FPFormat<5>; |
| 93 | def CondMovFP : FPFormat<6>; |
| 94 | def SpecialFP : FPFormat<7>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 95 | |
| 96 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 97 | class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> |
| 98 | : Instruction { |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 99 | let Namespace = "X86"; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 100 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 101 | bits<8> Opcode = opcod; |
| 102 | Format Form = f; |
| 103 | bits<5> FormBits = Form.Value; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 104 | ImmType ImmT = i; |
| 105 | bits<2> ImmTypeBits = ImmT.Value; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 106 | |
Chris Lattner | c96bb81 | 2004-08-11 07:12:04 +0000 | [diff] [blame] | 107 | dag OperandList = ops; |
| 108 | string AsmString = AsmStr; |
| 109 | |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 110 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 111 | // Attributes specific to X86 instructions... |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 112 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 113 | bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 114 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 115 | bits<4> Prefix = 0; // Which prefix byte does this inst have? |
| 116 | FPFormat FPForm; // What flavor of FP instruction is this? |
| 117 | bits<3> FPFormBits = 0; |
| 118 | } |
| 119 | |
| 120 | class Imp<list<Register> uses, list<Register> defs> { |
| 121 | list<Register> Uses = uses; |
| 122 | list<Register> Defs = defs; |
| 123 | } |
| 124 | |
| 125 | |
| 126 | // Prefix byte classes which are used to indicate to the ad-hoc machine code |
| 127 | // emitter that various prefix bytes are required. |
| 128 | class OpSize { bit hasOpSizePrefix = 1; } |
| 129 | class TB { bits<4> Prefix = 1; } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 130 | class REP { bits<4> Prefix = 2; } |
| 131 | class D8 { bits<4> Prefix = 3; } |
| 132 | class D9 { bits<4> Prefix = 4; } |
| 133 | class DA { bits<4> Prefix = 5; } |
| 134 | class DB { bits<4> Prefix = 6; } |
| 135 | class DC { bits<4> Prefix = 7; } |
| 136 | class DD { bits<4> Prefix = 8; } |
| 137 | class DE { bits<4> Prefix = 9; } |
| 138 | class DF { bits<4> Prefix = 10; } |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 139 | class XD { bits<4> Prefix = 11; } |
| 140 | class XS { bits<4> Prefix = 12; } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 141 | |
| 142 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 143 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 144 | // Pattern fragments... |
| 145 | // |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 146 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 147 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 148 | // sign extended field. |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 149 | return (int)N->getValue() == (signed char)N->getValue(); |
| 150 | }]>; |
| 151 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 152 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 153 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 154 | // sign extended field. |
| 155 | return (int)N->getValue() == (signed char)N->getValue(); |
| 156 | }]>; |
| 157 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 158 | def i16immZExt8 : PatLeaf<(i16 imm), [{ |
| 159 | // i16immZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 160 | // extended field. |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 161 | return (unsigned)N->getValue() == (unsigned char)N->getValue(); |
| 162 | }]>; |
| 163 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 164 | // Helper fragments for loads. |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame^] | 165 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
| 166 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>; |
| 167 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>; |
| 168 | |
| 169 | def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>; |
| 170 | def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>; |
| 171 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>; |
| 172 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>; |
| 173 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>; |
| 174 | |
| 175 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>; |
| 176 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>; |
| 177 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>; |
| 178 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>; |
| 179 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>; |
| 180 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 181 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 182 | //===----------------------------------------------------------------------===// |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 183 | // Instruction templates... |
| 184 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 185 | class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 186 | : X86Inst<o, f, NoImm, ops, asm> { |
| 187 | let Pattern = pattern; |
| 188 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 189 | class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 190 | : X86Inst<o, f, Imm8 , ops, asm> { |
| 191 | let Pattern = pattern; |
| 192 | } |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 193 | class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 194 | : X86Inst<o, f, Imm16, ops, asm> { |
| 195 | let Pattern = pattern; |
| 196 | } |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 197 | class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 198 | : X86Inst<o, f, Imm32, ops, asm> { |
| 199 | let Pattern = pattern; |
| 200 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 201 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 202 | //===----------------------------------------------------------------------===// |
| 203 | // Instruction list... |
| 204 | // |
| 205 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 206 | def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node. |
| 207 | def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // nop |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 208 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 209 | def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", []>; |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 210 | def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 211 | "#ADJCALLSTACKUP", []>; |
| 212 | def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>; |
| 213 | def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>; |
Alkis Evlogimenos | e0bb3e7 | 2003-12-20 16:22:59 +0000 | [diff] [blame] | 214 | let isTerminator = 1 in |
| 215 | let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 216 | def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>; |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 217 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 218 | //===----------------------------------------------------------------------===// |
| 219 | // Control Flow Instructions... |
| 220 | // |
| 221 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 222 | // Return instructions. |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 223 | let isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 224 | def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 225 | let isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 226 | def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 227 | |
| 228 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 229 | let isBranch = 1, isTerminator = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 230 | class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> : |
| 231 | I<opcode, RawFrm, ops, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 232 | |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 233 | let isBarrier = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 234 | def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>; |
| 235 | def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst", |
| 236 | []>, TB; |
| 237 | def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", []>, TB; |
| 238 | def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", []>, TB; |
| 239 | def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", []>, TB; |
| 240 | def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", []>, TB; |
| 241 | def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", []>, TB; |
| 242 | def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", []>, TB; |
| 243 | def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", []>, TB; |
| 244 | def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", []>, TB; |
| 245 | def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", []>, TB; |
| 246 | def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", []>, TB; |
| 247 | def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", []>, TB; |
| 248 | def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", []>, TB; |
| 249 | def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", []>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 250 | |
| 251 | //===----------------------------------------------------------------------===// |
| 252 | // Call Instructions... |
| 253 | // |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 254 | let isCall = 1 in |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 255 | // All calls clobber the non-callee saved registers... |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 256 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 257 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 258 | def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", []>; |
| 259 | def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", []>; |
| 260 | def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 261 | } |
| 262 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 263 | // Tail call stuff. |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 264 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 265 | def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL", []>; |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 266 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 267 | def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>; |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 268 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 269 | def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), |
| 270 | "jmp {*}$dst # TAIL CALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 271 | |
| 272 | // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every |
| 273 | // way, except that it is marked as being a terminator. This causes the epilog |
| 274 | // inserter to insert reloads of callee saved registers BEFORE this. We need |
| 275 | // this until we have a more accurate way of tracking where the stack pointer is |
| 276 | // within a function. |
| 277 | let isTerminator = 1, isTwoAddress = 1 in |
| 278 | def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 279 | "add{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 280 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 281 | //===----------------------------------------------------------------------===// |
| 282 | // Miscellaneous Instructions... |
| 283 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 284 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 285 | (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 286 | def POP32r : I<0x58, AddRegFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 287 | (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 288 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 289 | let isTwoAddress = 1 in // R32 = bswap R32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 290 | def BSWAP32r : I<0xC8, AddRegFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 291 | (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 292 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 293 | def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 294 | (ops R8:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 295 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 296 | def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 297 | (ops R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 298 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 299 | def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 300 | (ops R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 301 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 302 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 303 | def XCHG8mr : I<0x86, MRMDestMem, |
| 304 | (ops i8mem:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 305 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 306 | def XCHG16mr : I<0x87, MRMDestMem, |
| 307 | (ops i16mem:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 308 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 309 | def XCHG32mr : I<0x87, MRMDestMem, |
| 310 | (ops i32mem:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 311 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 312 | def XCHG8rm : I<0x86, MRMSrcMem, |
| 313 | (ops R8:$src1, i8mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 314 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 315 | def XCHG16rm : I<0x87, MRMSrcMem, |
| 316 | (ops R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 317 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 318 | def XCHG32rm : I<0x87, MRMSrcMem, |
| 319 | (ops R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 320 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 321 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 322 | def LEA16r : I<0x8D, MRMSrcMem, |
| 323 | (ops R16:$dst, i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 324 | "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 325 | def LEA32r : I<0x8D, MRMSrcMem, |
| 326 | (ops R32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 327 | "lea{l} {$src|$dst}, {$dst|$src}", |
| 328 | [(set R32:$dst, leaaddr:$src)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 329 | |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 330 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 331 | def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 332 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 333 | def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 334 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 335 | def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 336 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 337 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 338 | def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 339 | Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 340 | def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 341 | Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 342 | def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 343 | Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; |
| 344 | |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 345 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 346 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 347 | // Input/Output Instructions... |
| 348 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 349 | def IN8rr : I<0xEC, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 350 | "in{b} {%dx, %al|%AL, %DX}", []>, Imp<[DX], [AL]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 351 | def IN16rr : I<0xED, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 352 | "in{w} {%dx, %ax|%AX, %DX}", []>, Imp<[DX], [AX]>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 353 | def IN32rr : I<0xED, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 354 | "in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 355 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 356 | def IN8ri : Ii8<0xE4, RawFrm, (ops i8imm:$port), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 357 | "in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>; |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 358 | def IN16ri : Ii8<0xE5, RawFrm, (ops i8imm:$port), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 359 | "in{w} {$port, %ax|%AX, $port}", []>, Imp<[], [AX]>, OpSize; |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 360 | def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 361 | "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 362 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 363 | def OUT8rr : I<0xEE, RawFrm, (ops), |
| 364 | "out{b} {%al, %dx|%DX, %AL}", |
| 365 | [(writeport AL, DX)]>, Imp<[DX, AL], []>; |
| 366 | def OUT16rr : I<0xEF, RawFrm, (ops), |
| 367 | "out{w} {%ax, %dx|%DX, %AX}", |
| 368 | [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize; |
| 369 | def OUT32rr : I<0xEF, RawFrm, (ops), |
| 370 | "out{l} {%eax, %dx|%DX, %EAX}", |
| 371 | [(writeport EAX, DX)]>, Imp<[DX, EAX], []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 372 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 373 | def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port), |
| 374 | "out{b} {%al, $port|$port, %AL}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 375 | [(writeport AL, i16immZExt8:$port)]>, |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 376 | Imp<[AL], []>; |
| 377 | def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 378 | "out{w} {%ax, $port|$port, %AX}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 379 | [(writeport AX, i16immZExt8:$port)]>, |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 380 | Imp<[AX], []>, OpSize; |
| 381 | def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 382 | "out{l} {%eax, $port|$port, %EAX}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 383 | [(writeport EAX, i16immZExt8:$port)]>, |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 384 | Imp<[EAX], []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 385 | |
| 386 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 387 | // Move Instructions... |
| 388 | // |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 389 | def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 390 | "mov{b} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 391 | def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 392 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 393 | def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 394 | "mov{l} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 395 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 396 | "mov{b} {$src, $dst|$dst, $src}", |
| 397 | [(set R8:$dst, imm:$src)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 398 | def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 399 | "mov{w} {$src, $dst|$dst, $src}", |
| 400 | [(set R16:$dst, imm:$src)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 401 | def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 402 | "mov{l} {$src, $dst|$dst, $src}", |
| 403 | [(set R32:$dst, imm:$src)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 404 | def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 405 | "mov{b} {$src, $dst|$dst, $src}", |
| 406 | [(store (i8 imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 407 | def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 408 | "mov{w} {$src, $dst|$dst, $src}", |
| 409 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 410 | def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 411 | "mov{l} {$src, $dst|$dst, $src}", |
| 412 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 413 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 414 | def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 415 | "mov{b} {$src, $dst|$dst, $src}", |
| 416 | [(set R8:$dst, (load addr:$src))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 417 | def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 418 | "mov{w} {$src, $dst|$dst, $src}", |
| 419 | [(set R16:$dst, (load addr:$src))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 420 | def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 421 | "mov{l} {$src, $dst|$dst, $src}", |
| 422 | [(set R32:$dst, (load addr:$src))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 423 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 424 | def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 425 | "mov{b} {$src, $dst|$dst, $src}", |
| 426 | [(store R8:$src, addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 427 | def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 428 | "mov{w} {$src, $dst|$dst, $src}", |
| 429 | [(store R16:$src, addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 430 | def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 431 | "mov{l} {$src, $dst|$dst, $src}", |
| 432 | [(store R32:$src, addr:$dst)]>; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 433 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 434 | //===----------------------------------------------------------------------===// |
| 435 | // Fixed-Register Multiplication and Division Instructions... |
| 436 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 437 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 438 | // Extra precision multiplication |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 439 | def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 440 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 441 | def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 442 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 443 | def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 444 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 445 | def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 446 | "mul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 447 | def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 448 | "mul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 449 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 450 | def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 451 | "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 452 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 453 | def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 454 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 455 | def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 456 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 457 | def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 458 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
| 459 | def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 460 | "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 461 | def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 462 | "imul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 463 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 464 | def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 465 | "imul{l} $src", []>, |
| 466 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 467 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 468 | // unsigned division/remainder |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 469 | def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 470 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 471 | def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 472 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 473 | def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 474 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 475 | def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 476 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 477 | def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 478 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 479 | def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 480 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 481 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 482 | // Signed division/remainder. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 483 | def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 484 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 485 | def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 486 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 487 | def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 488 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 489 | def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 490 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 491 | def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 492 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 493 | def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 494 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 495 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 496 | // Sign-extenders for division. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 497 | def CBW : I<0x98, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 498 | "{cbtw|cbw}", []>, Imp<[AL],[AH]>; // AX = signext(AL) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 499 | def CWD : I<0x99, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 500 | "{cwtd|cwd}", []>, Imp<[AX],[DX]>; // DX:AX = signext(AX) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 501 | def CDQ : I<0x99, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 502 | "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 503 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 504 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 505 | //===----------------------------------------------------------------------===// |
| 506 | // Two address Instructions... |
| 507 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 508 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 509 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 510 | // Conditional moves |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 511 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16 |
| 512 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 513 | "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 514 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16] |
| 515 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 516 | "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 517 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32 |
| 518 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 519 | "cmovb {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 520 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32] |
| 521 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 522 | "cmovb {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 523 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 524 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 |
| 525 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 526 | "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 527 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] |
| 528 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 529 | "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 530 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 |
| 531 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 532 | "cmovae {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 533 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] |
| 534 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 535 | "cmovae {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 536 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 537 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 |
| 538 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 539 | "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 540 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] |
| 541 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 542 | "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 543 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 |
| 544 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 545 | "cmove {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 546 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] |
| 547 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 548 | "cmove {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 549 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 550 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 |
| 551 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 552 | "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 553 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] |
| 554 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 555 | "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 556 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 |
| 557 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 558 | "cmovne {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 559 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] |
| 560 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 561 | "cmovne {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 562 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 563 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 |
| 564 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 565 | "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 566 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] |
| 567 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 568 | "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 569 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 |
| 570 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 571 | "cmovbe {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 572 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] |
| 573 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 574 | "cmovbe {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 575 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 576 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 |
| 577 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 578 | "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 579 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] |
| 580 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 581 | "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 582 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 |
| 583 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 584 | "cmova {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 585 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] |
| 586 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 587 | "cmova {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 588 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 589 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 |
| 590 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 591 | "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 592 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] |
| 593 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 594 | "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 595 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 |
| 596 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 597 | "cmovs {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 598 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] |
| 599 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 600 | "cmovs {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 601 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 602 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 |
| 603 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 604 | "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 605 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] |
| 606 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 607 | "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 608 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 |
| 609 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 610 | "cmovns {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 611 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] |
| 612 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 613 | "cmovns {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 614 | |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 615 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16 |
| 616 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 617 | "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 618 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16] |
| 619 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 620 | "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 621 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32 |
| 622 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 623 | "cmovp {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 624 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32] |
| 625 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 626 | "cmovp {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 627 | |
| 628 | |
| 629 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16 |
| 630 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 631 | "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 632 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16] |
| 633 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 634 | "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 635 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32 |
| 636 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 637 | "cmovnp {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 638 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32] |
| 639 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 640 | "cmovnp {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 641 | |
| 642 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 643 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16 |
| 644 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 645 | "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 646 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16] |
| 647 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 648 | "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 649 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32 |
| 650 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 651 | "cmovl {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 652 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32] |
| 653 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 654 | "cmovl {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 655 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 656 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 |
| 657 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 658 | "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 659 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] |
| 660 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 661 | "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 662 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 |
| 663 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 664 | "cmovge {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 665 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] |
| 666 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 667 | "cmovge {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 668 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 669 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 |
| 670 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 671 | "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 672 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] |
| 673 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 674 | "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 675 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 |
| 676 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 677 | "cmovle {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 678 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] |
| 679 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 680 | "cmovle {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 681 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 682 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 |
| 683 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 684 | "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 685 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] |
| 686 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 687 | "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 688 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 |
| 689 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 690 | "cmovg {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 691 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] |
| 692 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 693 | "cmovg {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 694 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 695 | // unary instructions |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 696 | def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst", |
| 697 | [(set R8:$dst, (ineg R8:$src))]>; |
| 698 | def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst", |
| 699 | [(set R16:$dst, (ineg R16:$src))]>, OpSize; |
| 700 | def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst", |
| 701 | [(set R32:$dst, (ineg R32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 702 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 703 | def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 704 | [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 705 | def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 706 | [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 707 | def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 708 | [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>; |
| 709 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 710 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 711 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 712 | def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst", |
| 713 | [(set R8:$dst, (not R8:$src))]>; |
| 714 | def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst", |
| 715 | [(set R16:$dst, (not R16:$src))]>, OpSize; |
| 716 | def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst", |
| 717 | [(set R32:$dst, (not R32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 718 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 719 | def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 720 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 721 | def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 722 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 723 | def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 724 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 725 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 726 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 727 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 728 | def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst", |
| 729 | [(set R8:$dst, (add R8:$src, 1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 730 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 731 | def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst", |
| 732 | [(set R16:$dst, (add R16:$src, 1))]>, OpSize; |
| 733 | def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst", |
| 734 | [(set R32:$dst, (add R32:$src, 1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 735 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 736 | let isTwoAddress = 0 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 737 | def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 738 | [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 739 | def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 740 | [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 741 | def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 742 | [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 743 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 744 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 745 | def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", |
| 746 | [(set R8:$dst, (add R8:$src, -1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 747 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 748 | def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", |
| 749 | [(set R16:$dst, (add R16:$src, -1))]>, OpSize; |
| 750 | def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", |
| 751 | [(set R32:$dst, (add R32:$src, -1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 752 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 753 | |
| 754 | let isTwoAddress = 0 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 755 | def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 756 | [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 757 | def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 758 | [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 759 | def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 760 | [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 761 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 762 | |
| 763 | // Logical operators... |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 764 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 765 | def AND8rr : I<0x20, MRMDestReg, |
| 766 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 767 | "and{b} {$src2, $dst|$dst, $src2}", |
| 768 | [(set R8:$dst, (and R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 769 | def AND16rr : I<0x21, MRMDestReg, |
| 770 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 771 | "and{w} {$src2, $dst|$dst, $src2}", |
| 772 | [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 773 | def AND32rr : I<0x21, MRMDestReg, |
| 774 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 775 | "and{l} {$src2, $dst|$dst, $src2}", |
| 776 | [(set R32:$dst, (and R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 777 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 778 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 779 | def AND8rm : I<0x22, MRMSrcMem, |
| 780 | (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 781 | "and{b} {$src2, $dst|$dst, $src2}", |
| 782 | [(set R8:$dst, (and R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 783 | def AND16rm : I<0x23, MRMSrcMem, |
| 784 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 785 | "and{w} {$src2, $dst|$dst, $src2}", |
| 786 | [(set R16:$dst, (and R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 787 | def AND32rm : I<0x23, MRMSrcMem, |
| 788 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 789 | "and{l} {$src2, $dst|$dst, $src2}", |
| 790 | [(set R32:$dst, (and R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 791 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 792 | def AND8ri : Ii8<0x80, MRM4r, |
| 793 | (ops R8 :$dst, R8 :$src1, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 794 | "and{b} {$src2, $dst|$dst, $src2}", |
| 795 | [(set R8:$dst, (and R8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 796 | def AND16ri : Ii16<0x81, MRM4r, |
| 797 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 798 | "and{w} {$src2, $dst|$dst, $src2}", |
| 799 | [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 800 | def AND32ri : Ii32<0x81, MRM4r, |
| 801 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 802 | "and{l} {$src2, $dst|$dst, $src2}", |
| 803 | [(set R32:$dst, (and R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 804 | def AND16ri8 : Ii8<0x83, MRM4r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 805 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 806 | "and{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 807 | [(set R16:$dst, (and R16:$src1, i16immSExt8:$src2))]>, |
| 808 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 809 | def AND32ri8 : Ii8<0x83, MRM4r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 810 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 811 | "and{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 812 | [(set R32:$dst, (and R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 813 | |
| 814 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 815 | def AND8mr : I<0x20, MRMDestMem, |
| 816 | (ops i8mem :$dst, R8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 817 | "and{b} {$src, $dst|$dst, $src}", |
| 818 | [(store (and (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 819 | def AND16mr : I<0x21, MRMDestMem, |
| 820 | (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 821 | "and{w} {$src, $dst|$dst, $src}", |
| 822 | [(store (and (load addr:$dst), R16:$src), addr:$dst)]>, |
| 823 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 824 | def AND32mr : I<0x21, MRMDestMem, |
| 825 | (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 826 | "and{l} {$src, $dst|$dst, $src}", |
| 827 | [(store (and (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 828 | def AND8mi : Ii8<0x80, MRM4m, |
| 829 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 830 | "and{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 831 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 832 | def AND16mi : Ii16<0x81, MRM4m, |
| 833 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 834 | "and{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 835 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 836 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 837 | def AND32mi : Ii32<0x81, MRM4m, |
| 838 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 839 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 840 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 841 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 842 | (ops i16mem:$dst, i16i8imm :$src), |
| 843 | "and{w} {$src, $dst|$dst, $src}", |
| 844 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 845 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 846 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 847 | (ops i32mem:$dst, i32i8imm :$src), |
| 848 | "and{l} {$src, $dst|$dst, $src}", |
| 849 | [(store (add (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 850 | } |
| 851 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 852 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 853 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 854 | def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 855 | "or{b} {$src2, $dst|$dst, $src2}", |
| 856 | [(set R8:$dst, (or R8:$src1, R8:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 857 | def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 858 | "or{w} {$src2, $dst|$dst, $src2}", |
| 859 | [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 860 | def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 861 | "or{l} {$src2, $dst|$dst, $src2}", |
| 862 | [(set R32:$dst, (or R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 863 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 864 | def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 865 | "or{b} {$src2, $dst|$dst, $src2}", |
| 866 | [(set R8:$dst, (or R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 867 | def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 868 | "or{w} {$src2, $dst|$dst, $src2}", |
| 869 | [(set R16:$dst, (or R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 870 | def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 871 | "or{l} {$src2, $dst|$dst, $src2}", |
| 872 | [(set R32:$dst, (or R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 873 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 874 | def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 875 | "or{b} {$src2, $dst|$dst, $src2}", |
| 876 | [(set R8:$dst, (or R8:$src1, imm:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 877 | def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 878 | "or{w} {$src2, $dst|$dst, $src2}", |
| 879 | [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 880 | def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 881 | "or{l} {$src2, $dst|$dst, $src2}", |
| 882 | [(set R32:$dst, (or R32:$src1, imm:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 883 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 884 | def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 885 | "or{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 886 | [(set R16:$dst, (or R16:$src1, i16immSExt8:$src2))]>, OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 887 | def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 888 | "or{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 889 | [(set R32:$dst, (or R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 890 | let isTwoAddress = 0 in { |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 891 | def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 892 | "or{b} {$src, $dst|$dst, $src}", |
| 893 | [(store (or (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 894 | def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 895 | "or{w} {$src, $dst|$dst, $src}", |
| 896 | [(store (or (load addr:$dst), R16:$src), addr:$dst)]>, OpSize; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 897 | def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 898 | "or{l} {$src, $dst|$dst, $src}", |
| 899 | [(store (or (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 900 | def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 901 | "or{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 902 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 903 | def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 904 | "or{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 905 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 906 | OpSize; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 907 | def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 908 | "or{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 909 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 910 | def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src), |
| 911 | "or{w} {$src, $dst|$dst, $src}", |
| 912 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 913 | OpSize; |
| 914 | def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src), |
| 915 | "or{l} {$src, $dst|$dst, $src}", |
| 916 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 917 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 918 | |
| 919 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 920 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 921 | def XOR8rr : I<0x30, MRMDestReg, |
| 922 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 923 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 924 | [(set R8:$dst, (xor R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 925 | def XOR16rr : I<0x31, MRMDestReg, |
| 926 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 927 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 928 | [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 929 | def XOR32rr : I<0x31, MRMDestReg, |
| 930 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 931 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 932 | [(set R32:$dst, (xor R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 933 | } |
| 934 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 935 | def XOR8rm : I<0x32, MRMSrcMem , |
| 936 | (ops R8 :$dst, R8:$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 937 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 938 | [(set R8:$dst, (xor R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 939 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 940 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 941 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 942 | [(set R16:$dst, (xor R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 943 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 944 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 945 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 946 | [(set R32:$dst, (xor R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 947 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 948 | def XOR8ri : Ii8<0x80, MRM6r, |
| 949 | (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 950 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 951 | [(set R8:$dst, (xor R8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 952 | def XOR16ri : Ii16<0x81, MRM6r, |
| 953 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 954 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 955 | [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 956 | def XOR32ri : Ii32<0x81, MRM6r, |
| 957 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 958 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 959 | [(set R32:$dst, (xor R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 960 | def XOR16ri8 : Ii8<0x83, MRM6r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 961 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 962 | "xor{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 963 | [(set R16:$dst, (xor R16:$src1, i16immSExt8:$src2))]>, |
| 964 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 965 | def XOR32ri8 : Ii8<0x83, MRM6r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 966 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 967 | "xor{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 968 | [(set R32:$dst, (xor R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 969 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 970 | def XOR8mr : I<0x30, MRMDestMem, |
| 971 | (ops i8mem :$dst, R8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 972 | "xor{b} {$src, $dst|$dst, $src}", |
| 973 | [(store (xor (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 974 | def XOR16mr : I<0x31, MRMDestMem, |
| 975 | (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 976 | "xor{w} {$src, $dst|$dst, $src}", |
| 977 | [(store (xor (load addr:$dst), R16:$src), addr:$dst)]>, |
| 978 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 979 | def XOR32mr : I<0x31, MRMDestMem, |
| 980 | (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 981 | "xor{l} {$src, $dst|$dst, $src}", |
| 982 | [(store (xor (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 983 | def XOR8mi : Ii8<0x80, MRM6m, |
| 984 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 985 | "xor{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 986 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 987 | def XOR16mi : Ii16<0x81, MRM6m, |
| 988 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 989 | "xor{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 990 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 991 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 992 | def XOR32mi : Ii32<0x81, MRM6m, |
| 993 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 994 | "xor{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 995 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 996 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 997 | (ops i16mem:$dst, i16i8imm :$src), |
| 998 | "xor{w} {$src, $dst|$dst, $src}", |
| 999 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1000 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1001 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1002 | (ops i32mem:$dst, i32i8imm :$src), |
| 1003 | "xor{l} {$src, $dst|$dst, $src}", |
| 1004 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1005 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1006 | |
| 1007 | // Shift instructions |
Alkis Evlogimenos | 13d362f | 2004-03-07 03:19:11 +0000 | [diff] [blame] | 1008 | // FIXME: provide shorter instructions when imm8 == 1 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1009 | def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1010 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1011 | [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1012 | def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1013 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1014 | [(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1015 | def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1016 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1017 | [(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1018 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1019 | def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1020 | "shl{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1021 | [(set R8:$dst, (shl R8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1022 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1023 | def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1024 | "shl{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1025 | [(set R16:$dst, (shl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1026 | def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1027 | "shl{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1028 | [(set R32:$dst, (shl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1029 | } |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1030 | |
| 1031 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1032 | def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1033 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1034 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1035 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1036 | def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1037 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1038 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1039 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1040 | def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1041 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1042 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1043 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1044 | def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1045 | "shl{b} {$src, $dst|$dst, $src}", |
| 1046 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1047 | def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1048 | "shl{w} {$src, $dst|$dst, $src}", |
| 1049 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1050 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1051 | def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1052 | "shl{l} {$src, $dst|$dst, $src}", |
| 1053 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1054 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1055 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1056 | def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1057 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1058 | [(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1059 | def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1060 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1061 | [(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1062 | def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1063 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1064 | [(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1065 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1066 | def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1067 | "shr{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1068 | [(set R8:$dst, (srl R8:$src1, (i8 imm:$src2)))]>; |
| 1069 | def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1070 | "shr{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1071 | [(set R16:$dst, (srl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1072 | def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1073 | "shr{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1074 | [(set R32:$dst, (srl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1075 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1076 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1077 | def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1078 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1079 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1080 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1081 | def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1082 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1083 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1084 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1085 | def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1086 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1087 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1088 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1089 | def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1090 | "shr{b} {$src, $dst|$dst, $src}", |
| 1091 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1092 | def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1093 | "shr{w} {$src, $dst|$dst, $src}", |
| 1094 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1095 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1096 | def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1097 | "shr{l} {$src, $dst|$dst, $src}", |
| 1098 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1099 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1100 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1101 | def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1102 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1103 | [(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1104 | def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1105 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1106 | [(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1107 | def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1108 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1109 | [(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1110 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1111 | def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1112 | "sar{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1113 | [(set R8:$dst, (sra R8:$src1, (i8 imm:$src2)))]>; |
| 1114 | def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1115 | "sar{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1116 | [(set R16:$dst, (sra R16:$src1, (i8 imm:$src2)))]>, |
| 1117 | OpSize; |
| 1118 | def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1119 | "sar{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1120 | [(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1121 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1122 | def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1123 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1124 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1125 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1126 | def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1127 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1128 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1129 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1130 | def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1131 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1132 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1133 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1134 | def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1135 | "sar{b} {$src, $dst|$dst, $src}", |
| 1136 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1137 | def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1138 | "sar{w} {$src, $dst|$dst, $src}", |
| 1139 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1140 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1141 | def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1142 | "sar{l} {$src, $dst|$dst, $src}", |
| 1143 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1144 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1145 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1146 | // Rotate instructions |
| 1147 | // FIXME: provide shorter instructions when imm8 == 1 |
| 1148 | def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1149 | "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1150 | def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1151 | "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1152 | def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1153 | "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1154 | |
| 1155 | def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1156 | "rol{b} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1157 | def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1158 | "rol{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1159 | def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1160 | "rol{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1161 | |
| 1162 | let isTwoAddress = 0 in { |
| 1163 | def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1164 | "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1165 | def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1166 | "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1167 | def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1168 | "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1169 | def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1170 | "rol{b} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1171 | def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1172 | "rol{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1173 | def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1174 | "rol{l} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1175 | } |
| 1176 | |
| 1177 | def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1178 | "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1179 | def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1180 | "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1181 | def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1182 | "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1183 | |
| 1184 | def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1185 | "ror{b} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1186 | def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1187 | "ror{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1188 | def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1189 | "ror{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1190 | let isTwoAddress = 0 in { |
| 1191 | def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1192 | "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1193 | def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1194 | "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1195 | def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1196 | "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1197 | def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1198 | "ror{b} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1199 | def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1200 | "ror{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1201 | def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1202 | "ror{l} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1203 | } |
| 1204 | |
| 1205 | |
| 1206 | |
| 1207 | // Double shift instructions (generalizations of rotate) |
| 1208 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1209 | def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1210 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1211 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1212 | def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1213 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1214 | Imp<[CL],[]>, TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1215 | def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1216 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1217 | Imp<[CL],[]>, TB, OpSize; |
| 1218 | def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1219 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1220 | Imp<[CL],[]>, TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1221 | |
| 1222 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1223 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
| 1224 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1225 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1226 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
| 1227 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1228 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1229 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
| 1230 | (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1231 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1232 | TB, OpSize; |
| 1233 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
| 1234 | (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1235 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1236 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1237 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1238 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1239 | let isTwoAddress = 0 in { |
| 1240 | def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1241 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1242 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1243 | def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1244 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1245 | Imp<[CL],[]>, TB; |
| 1246 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
| 1247 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1248 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
| 1249 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1250 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
| 1251 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1252 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
| 1253 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1254 | |
| 1255 | def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1256 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1257 | Imp<[CL],[]>, TB, OpSize; |
| 1258 | def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1259 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1260 | Imp<[CL],[]>, TB, OpSize; |
| 1261 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
| 1262 | (ops i16mem:$dst, R16:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1263 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1264 | TB, OpSize; |
| 1265 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
| 1266 | (ops i16mem:$dst, R16:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1267 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1268 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1269 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1270 | |
| 1271 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1272 | // Arithmetic. |
| 1273 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1274 | def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1275 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1276 | [(set R8:$dst, (add R8:$src1, R8:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1277 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1278 | def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1279 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1280 | [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1281 | def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1282 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1283 | [(set R32:$dst, (add R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1284 | } // end isConvertibleToThreeAddress |
| 1285 | } // end isCommutable |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1286 | def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1287 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1288 | [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1289 | def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1290 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1291 | [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1292 | def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1293 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1294 | [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1295 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1296 | def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1297 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1298 | [(set R8:$dst, (add R8:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1299 | |
| 1300 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1301 | def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1302 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1303 | [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1304 | def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1305 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1306 | [(set R32:$dst, (add R32:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1307 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1308 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1309 | // FIXME: move ADD16ri8 above ADD16ri to optimize for space. |
| 1310 | def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1311 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1312 | [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>, |
| 1313 | OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1314 | def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1315 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1316 | [(set R32:$dst, (add R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1317 | |
| 1318 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1319 | def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1320 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1321 | [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1322 | def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1323 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1324 | [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>, |
| 1325 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1326 | def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1327 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1328 | [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1329 | def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1330 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1331 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1332 | def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1333 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1334 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1335 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1336 | def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1337 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1338 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1339 | def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1340 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1341 | [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1342 | OpSize; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1343 | def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1344 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1345 | [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1346 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1347 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1348 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1349 | def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1350 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1351 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1352 | def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1353 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1354 | def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1355 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1356 | def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1357 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1358 | |
| 1359 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1360 | def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1361 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1362 | def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1363 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1364 | def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1365 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1366 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1367 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1368 | def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1369 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1370 | [(set R8:$dst, (sub R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1371 | def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1372 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1373 | [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1374 | def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1375 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1376 | [(set R32:$dst, (sub R32:$src1, R32:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1377 | def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1378 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1379 | [(set R8:$dst, (sub R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1380 | def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1381 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1382 | [(set R16:$dst, (sub R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1383 | def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1384 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1385 | [(set R32:$dst, (sub R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1386 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1387 | def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1388 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1389 | [(set R8:$dst, (sub R8:$src1, imm:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1390 | def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1391 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1392 | [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1393 | def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1394 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1395 | [(set R32:$dst, (sub R32:$src1, imm:$src2))]>; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1396 | def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1397 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1398 | [(set R16:$dst, (sub R16:$src1, i16immSExt8:$src2))]>, |
| 1399 | OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1400 | def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1401 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1402 | [(set R32:$dst, (sub R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1403 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1404 | def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1405 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1406 | [(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1407 | def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1408 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1409 | [(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>, |
| 1410 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1411 | def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1412 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1413 | [(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1414 | def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1415 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1416 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1417 | def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1418 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1419 | [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1420 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1421 | def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1422 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1423 | [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1424 | def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1425 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1426 | [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1427 | OpSize; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1428 | def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1429 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1430 | [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1431 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1432 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1433 | def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1434 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1435 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1436 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1437 | def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1438 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1439 | def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1440 | "sbb{b} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1441 | def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1442 | "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1443 | def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1444 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1445 | def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1446 | "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1447 | def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1448 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1449 | } |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1450 | def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1451 | "sbb{b} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1452 | def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1453 | "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1454 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1455 | def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1456 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1457 | def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1458 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1459 | |
Chris Lattner | 09c750f | 2004-10-06 14:31:50 +0000 | [diff] [blame] | 1460 | def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1461 | "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1462 | def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1463 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1464 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1465 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1466 | def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1467 | "imul{w} {$src2, $dst|$dst, $src2}", |
| 1468 | [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1469 | def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1470 | "imul{l} {$src2, $dst|$dst, $src2}", |
| 1471 | [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1472 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1473 | def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1474 | "imul{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1475 | [(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>, |
| 1476 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1477 | def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1478 | "imul{l} {$src2, $dst|$dst, $src2}", |
| 1479 | [(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1480 | |
| 1481 | } // end Two Address instructions |
| 1482 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1483 | // Suprisingly enough, these are not two address instructions! |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1484 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16 |
| 1485 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1486 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1487 | [(set R16:$dst, (mul R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1488 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32 |
| 1489 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1490 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 1491 | [(set R32:$dst, (mul R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1492 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8 |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1493 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1494 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1495 | [(set R16:$dst, (mul R16:$src1, i16immSExt8:$src2))]>, |
| 1496 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1497 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1498 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1499 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1500 | [(set R32:$dst, (mul R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1501 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1502 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1503 | (ops R16:$dst, i16mem:$src1, i16imm:$src2), |
| 1504 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 1505 | [(set R16:$dst, (mul (load addr:$src1), imm:$src2))]>, |
| 1506 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1507 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32 |
| 1508 | (ops R32:$dst, i32mem:$src1, i32imm:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1509 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 1510 | [(set R32:$dst, (mul (load addr:$src1), imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1511 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1512 | (ops R16:$dst, i16mem:$src1, i16i8imm :$src2), |
| 1513 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1514 | [(set R16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, |
| 1515 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1516 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1517 | (ops R32:$dst, i32mem:$src1, i32i8imm: $src2), |
| 1518 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1519 | [(set R32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1520 | |
| 1521 | //===----------------------------------------------------------------------===// |
| 1522 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1523 | // |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1524 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1525 | def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1526 | "test{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1527 | def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1528 | "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1529 | def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1530 | "test{l} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1531 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1532 | def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1533 | "test{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1534 | def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1535 | "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1536 | def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1537 | "test{l} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1538 | def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1539 | "test{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1540 | def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1541 | "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1542 | def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1543 | "test{l} {$src2, $src1|$src1, $src2}", []>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1544 | |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1545 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 |
| 1546 | (ops R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1547 | "test{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1548 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16 |
| 1549 | (ops R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1550 | "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1551 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32 |
| 1552 | (ops R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1553 | "test{l} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1554 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
| 1555 | (ops i32mem:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1556 | "test{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1557 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
| 1558 | (ops i16mem:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1559 | "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1560 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
| 1561 | (ops i32mem:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1562 | "test{l} {$src2, $src1|$src1, $src2}", []>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1563 | |
| 1564 | |
| 1565 | |
| 1566 | // Condition code ops, incl. set if equal/not equal/... |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1567 | def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH |
| 1568 | def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1569 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1570 | def SETBr : I<0x92, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1571 | (ops R8 :$dst), "setb $dst", []>, TB; // R8 = < unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1572 | def SETBm : I<0x92, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1573 | (ops i8mem:$dst), "setb $dst", []>, TB; // [mem8] = < unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1574 | def SETAEr : I<0x93, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1575 | (ops R8 :$dst), "setae $dst", []>, TB; // R8 = >= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1576 | def SETAEm : I<0x93, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1577 | (ops i8mem:$dst), "setae $dst", []>, TB; // [mem8] = >= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1578 | def SETEr : I<0x94, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1579 | (ops R8 :$dst), "sete $dst", []>, TB; // R8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1580 | def SETEm : I<0x94, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1581 | (ops i8mem:$dst), "sete $dst", []>, TB; // [mem8] = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1582 | def SETNEr : I<0x95, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1583 | (ops R8 :$dst), "setne $dst", []>, TB; // R8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1584 | def SETNEm : I<0x95, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1585 | (ops i8mem:$dst), "setne $dst", []>, TB; // [mem8] = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1586 | def SETBEr : I<0x96, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1587 | (ops R8 :$dst), "setbe $dst", []>, TB; // R8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1588 | def SETBEm : I<0x96, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1589 | (ops i8mem:$dst), "setbe $dst", []>, TB; // [mem8] = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1590 | def SETAr : I<0x97, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1591 | (ops R8 :$dst), "seta $dst", []>, TB; // R8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1592 | def SETAm : I<0x97, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1593 | (ops i8mem:$dst), "seta $dst", []>, TB; // [mem8] = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1594 | def SETSr : I<0x98, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1595 | (ops R8 :$dst), "sets $dst", []>, TB; // R8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1596 | def SETSm : I<0x98, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1597 | (ops i8mem:$dst), "sets $dst", []>, TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1598 | def SETNSr : I<0x99, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1599 | (ops R8 :$dst), "setns $dst", []>, TB; // R8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1600 | def SETNSm : I<0x99, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1601 | (ops i8mem:$dst), "setns $dst", []>, TB; // [mem8] = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1602 | def SETPr : I<0x9A, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1603 | (ops R8 :$dst), "setp $dst", []>, TB; // R8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1604 | def SETPm : I<0x9A, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1605 | (ops i8mem:$dst), "setp $dst", []>, TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1606 | def SETNPr : I<0x9B, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1607 | (ops R8 :$dst), "setnp $dst", []>, TB; // R8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1608 | def SETNPm : I<0x9B, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1609 | (ops i8mem:$dst), "setnp $dst", []>, TB; // [mem8] = not parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1610 | def SETLr : I<0x9C, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1611 | (ops R8 :$dst), "setl $dst", []>, TB; // R8 = < signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1612 | def SETLm : I<0x9C, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1613 | (ops i8mem:$dst), "setl $dst", []>, TB; // [mem8] = < signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1614 | def SETGEr : I<0x9D, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1615 | (ops R8 :$dst), "setge $dst", []>, TB; // R8 = >= signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1616 | def SETGEm : I<0x9D, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1617 | (ops i8mem:$dst), "setge $dst", []>, TB; // [mem8] = >= signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1618 | def SETLEr : I<0x9E, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1619 | (ops R8 :$dst), "setle $dst", []>, TB; // R8 = <= signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1620 | def SETLEm : I<0x9E, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1621 | (ops i8mem:$dst), "setle $dst", []>, TB; // [mem8] = <= signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1622 | def SETGr : I<0x9F, MRM0r, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1623 | (ops R8 :$dst), "setg $dst", []>, TB; // R8 = < signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1624 | def SETGm : I<0x9F, MRM0m, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1625 | (ops i8mem:$dst), "setg $dst", []>, TB; // [mem8] = < signed |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1626 | |
| 1627 | // Integer comparisons |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1628 | def CMP8rr : I<0x38, MRMDestReg, |
| 1629 | (ops R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1630 | "cmp{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1631 | def CMP16rr : I<0x39, MRMDestReg, |
| 1632 | (ops R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1633 | "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1634 | def CMP32rr : I<0x39, MRMDestReg, |
| 1635 | (ops R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1636 | "cmp{l} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1637 | def CMP8mr : I<0x38, MRMDestMem, |
| 1638 | (ops i8mem :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1639 | "cmp{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1640 | def CMP16mr : I<0x39, MRMDestMem, |
| 1641 | (ops i16mem:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1642 | "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1643 | def CMP32mr : I<0x39, MRMDestMem, |
| 1644 | (ops i32mem:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1645 | "cmp{l} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1646 | def CMP8rm : I<0x3A, MRMSrcMem, |
| 1647 | (ops R8 :$src1, i8mem :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1648 | "cmp{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1649 | def CMP16rm : I<0x3B, MRMSrcMem, |
| 1650 | (ops R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1651 | "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1652 | def CMP32rm : I<0x3B, MRMSrcMem, |
| 1653 | (ops R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1654 | "cmp{l} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1655 | def CMP8ri : Ii8<0x80, MRM7r, |
| 1656 | (ops R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1657 | "cmp{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1658 | def CMP16ri : Ii16<0x81, MRM7r, |
| 1659 | (ops R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1660 | "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1661 | def CMP32ri : Ii32<0x81, MRM7r, |
| 1662 | (ops R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1663 | "cmp{l} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1664 | def CMP8mi : Ii8 <0x80, MRM7m, |
| 1665 | (ops i8mem :$src1, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1666 | "cmp{b} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1667 | def CMP16mi : Ii16<0x81, MRM7m, |
| 1668 | (ops i16mem:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1669 | "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1670 | def CMP32mi : Ii32<0x81, MRM7m, |
| 1671 | (ops i32mem:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1672 | "cmp{l} {$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1673 | |
| 1674 | // Sign/Zero extenders |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1675 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1676 | "movs{bw|x} {$src, $dst|$dst, $src}", |
| 1677 | [(set R16:$dst, (sext R8:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1678 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame^] | 1679 | "movs{bw|x} {$src, $dst|$dst, $src}", |
| 1680 | [(set R16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1681 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1682 | "movs{bl|x} {$src, $dst|$dst, $src}", |
| 1683 | [(set R32:$dst, (sext R8:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1684 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame^] | 1685 | "movs{bl|x} {$src, $dst|$dst, $src}", |
| 1686 | [(set R32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1687 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1688 | "movs{wl|x} {$src, $dst|$dst, $src}", |
| 1689 | [(set R32:$dst, (sext R16:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1690 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame^] | 1691 | "movs{wl|x} {$src, $dst|$dst, $src}", |
| 1692 | [(set R32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 1693 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1694 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1695 | "movz{bw|x} {$src, $dst|$dst, $src}", |
| 1696 | [(set R16:$dst, (zext R8:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1697 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame^] | 1698 | "movz{bw|x} {$src, $dst|$dst, $src}", |
| 1699 | [(set R16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1700 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1701 | "movz{bl|x} {$src, $dst|$dst, $src}", |
| 1702 | [(set R32:$dst, (zext R8:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1703 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame^] | 1704 | "movz{bl|x} {$src, $dst|$dst, $src}", |
| 1705 | [(set R32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1706 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1707 | "movz{wl|x} {$src, $dst|$dst, $src}", |
| 1708 | [(set R32:$dst, (zext R16:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1709 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame^] | 1710 | "movz{wl|x} {$src, $dst|$dst, $src}", |
| 1711 | [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
| 1712 | |
| 1713 | // Handling 1 bit zextload and sextload |
| 1714 | def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>; |
| 1715 | def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>; |
| 1716 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 1717 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1718 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1719 | //===----------------------------------------------------------------------===// |
| 1720 | // XMM Floating point support (requires SSE2) |
| 1721 | //===----------------------------------------------------------------------===// |
| 1722 | |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1723 | def MOVSSrr : I<0x10, MRMSrcReg, (ops V4F4:$dst, V4F4:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1724 | "movss {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1725 | def MOVSSrm : I<0x10, MRMSrcMem, (ops V4F4:$dst, f32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1726 | "movss {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1727 | def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, V4F4:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1728 | "movss {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1729 | def MOVSDrr : I<0x10, MRMSrcReg, (ops V2F8:$dst, V2F8:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1730 | "movsd {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1731 | def MOVSDrm : I<0x10, MRMSrcMem, (ops V2F8:$dst, f64mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1732 | "movsd {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1733 | def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, V2F8:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1734 | "movsd {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1735 | |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1736 | def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V2F8:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1737 | "cvttsd2si {$src, $dst|$dst, $src}", |
| 1738 | [(set R32:$dst, (fp_to_sint V2F8:$src))]>, XD; |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 1739 | def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1740 | "cvttsd2si {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1741 | def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V4F4:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1742 | "cvttss2si {$src, $dst|$dst, $src}", |
| 1743 | [(set R32:$dst, (fp_to_sint V4F4:$src))]>, XS; |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 1744 | def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1745 | "cvttss2si {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1746 | def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops V4F4:$dst, V2F8:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1747 | "cvtsd2ss {$src, $dst|$dst, $src}", |
| 1748 | [(set V4F4:$dst, (fround V2F8:$src))]>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1749 | def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops V4F4:$dst, f64mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1750 | "cvtsd2ss {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1751 | def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops V2F8:$dst, V4F4:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1752 | "cvtss2sd {$src, $dst|$dst, $src}", |
| 1753 | [(set V2F8:$dst, (fextend V4F4:$src))]>, XD; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1754 | def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops V2F8:$dst, f32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1755 | "cvtss2sd {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1756 | def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops V4F4:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1757 | "cvtsi2ss {$src, $dst|$dst, $src}", |
| 1758 | [(set V4F4:$dst, (sint_to_fp R32:$src))]>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1759 | def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops V4F4:$dst, i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1760 | "cvtsi2ss {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1761 | def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops V2F8:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1762 | "cvtsi2sd {$src, $dst|$dst, $src}", |
| 1763 | [(set V2F8:$dst, (sint_to_fp R32:$src))]>, XD; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1764 | def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops V2F8:$dst, i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1765 | "cvtsi2sd {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 1766 | |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1767 | def SQRTSSrm : I<0x51, MRMSrcMem, (ops V4F4:$dst, f32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1768 | "sqrtss {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1769 | def SQRTSSrr : I<0x51, MRMSrcReg, (ops V4F4:$dst, V4F4:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1770 | "sqrtss {$src, $dst|$dst, $src}", |
| 1771 | [(set V4F4:$dst, (fsqrt V4F4:$src))]>, XS; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1772 | def SQRTSDrm : I<0x51, MRMSrcMem, (ops V2F8:$dst, f64mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1773 | "sqrtsd {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1774 | def SQRTSDrr : I<0x51, MRMSrcReg, (ops V2F8:$dst, V2F8:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1775 | "sqrtsd {$src, $dst|$dst, $src}", |
| 1776 | [(set V2F8:$dst, (fsqrt V2F8:$src))]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1777 | |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1778 | def UCOMISDrr: I<0x2E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1779 | "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1780 | def UCOMISDrm: I<0x2E, MRMSrcMem, (ops V2F8:$dst, f64mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1781 | "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1782 | def UCOMISSrr: I<0x2E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1783 | "ucomiss {$src, $dst|$dst, $src}", []>, TB; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1784 | def UCOMISSrm: I<0x2E, MRMSrcMem, (ops V4F4:$dst, f32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1785 | "ucomiss {$src, $dst|$dst, $src}", []>, TB; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1786 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1787 | // Pseudo-instructions that map fld0 to xorps/xorpd for sse. |
Nate Begeman | 1c73c7b | 2005-08-03 23:26:28 +0000 | [diff] [blame] | 1788 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1789 | def FLD0SS : I<0x57, MRMSrcReg, (ops V4F4:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1790 | "xorps $dst, $dst", []>, TB; |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1791 | def FLD0SD : I<0x57, MRMSrcReg, (ops V2F8:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1792 | "xorpd $dst, $dst", []>, TB, OpSize; |
Nate Begeman | 1c73c7b | 2005-08-03 23:26:28 +0000 | [diff] [blame] | 1793 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1794 | let isTwoAddress = 1 in { |
| 1795 | let isCommutable = 1 in { |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1796 | def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), |
| 1797 | "addss {$src2, $dst|$dst, $src2}", |
| 1798 | [(set V4F4:$dst, (fadd V4F4:$src1, V4F4:$src2))]>, XS; |
| 1799 | def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), |
| 1800 | "addsd {$src2, $dst|$dst, $src2}", |
| 1801 | [(set V2F8:$dst, (fadd V2F8:$src1, V2F8:$src2))]>, XD; |
| 1802 | def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), |
| 1803 | "andps {$src2, $dst|$dst, $src2}", []>, TB; |
| 1804 | def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), |
| 1805 | "andpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
| 1806 | def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), |
| 1807 | "mulss {$src2, $dst|$dst, $src2}", |
| 1808 | [(set V4F4:$dst, (fmul V4F4:$src1, V4F4:$src2))]>, XS; |
| 1809 | def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), |
| 1810 | "mulsd {$src2, $dst|$dst, $src2}", |
| 1811 | [(set V2F8:$dst, (fmul V2F8:$src1, V2F8:$src2))]>, XD; |
| 1812 | def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), |
| 1813 | "orps {$src2, $dst|$dst, $src2}", []>, TB; |
| 1814 | def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), |
| 1815 | "orpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
| 1816 | def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), |
| 1817 | "xorps {$src2, $dst|$dst, $src2}", []>, TB; |
| 1818 | def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), |
| 1819 | "xorpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1820 | } |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1821 | def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), |
| 1822 | "andnps {$src2, $dst|$dst, $src2}", []>, TB; |
| 1823 | def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), |
| 1824 | "andnpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
| 1825 | def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2), |
| 1826 | "addss {$src2, $dst|$dst, $src2}", []>, XS; |
| 1827 | def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2), |
| 1828 | "addsd {$src2, $dst|$dst, $src2}", []>, XD; |
| 1829 | def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2), |
| 1830 | "mulss {$src2, $dst|$dst, $src2}", []>, XS; |
| 1831 | def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2), |
| 1832 | "mulsd {$src2, $dst|$dst, $src2}", []>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1833 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1834 | def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2), |
| 1835 | "divss {$src2, $dst|$dst, $src2}", []>, XS; |
| 1836 | def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), |
| 1837 | "divss {$src2, $dst|$dst, $src2}", |
| 1838 | [(set V4F4:$dst, (fdiv V4F4:$src1, V4F4:$src2))]>, XS; |
| 1839 | def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2), |
| 1840 | "divsd {$src2, $dst|$dst, $src2}", []>, XD; |
| 1841 | def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), |
| 1842 | "divsd {$src2, $dst|$dst, $src2}", |
| 1843 | [(set V2F8:$dst, (fdiv V2F8:$src1, V2F8:$src2))]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1844 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1845 | def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2), |
| 1846 | "subss {$src2, $dst|$dst, $src2}", []>, XS; |
| 1847 | def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), |
| 1848 | "subss {$src2, $dst|$dst, $src2}", |
| 1849 | [(set V4F4:$dst, (fsub V4F4:$src1, V4F4:$src2))]>, XS; |
| 1850 | def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2), |
| 1851 | "subsd {$src2, $dst|$dst, $src2}", []>, XD; |
| 1852 | def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), |
| 1853 | "subsd {$src2, $dst|$dst, $src2}", |
| 1854 | [(set V2F8:$dst, (fsub V2F8:$src1, V2F8:$src2))]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1855 | |
| 1856 | def CMPSSrr : I<0xC2, MRMSrcReg, |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1857 | (ops V4F4:$dst, V4F4:$src1, V4F4:$src, SSECC:$cc), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1858 | "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1859 | def CMPSSrm : I<0xC2, MRMSrcMem, |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1860 | (ops V4F4:$dst, V4F4:$src1, f32mem:$src, SSECC:$cc), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1861 | "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1862 | def CMPSDrr : I<0xC2, MRMSrcReg, |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1863 | (ops V2F8:$dst, V2F8:$src1, V2F8:$src, SSECC:$cc), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1864 | "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1865 | def CMPSDrm : I<0xC2, MRMSrcMem, |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 1866 | (ops V2F8:$dst, V2F8:$src1, f64mem:$src, SSECC:$cc), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1867 | "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1868 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1869 | |
| 1870 | //===----------------------------------------------------------------------===// |
Chris Lattner | 441b223 | 2005-11-20 22:13:18 +0000 | [diff] [blame] | 1871 | // Miscellaneous Instructions |
| 1872 | //===----------------------------------------------------------------------===// |
| 1873 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1874 | def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", []>, TB, Imp<[],[EAX,EDX]>; |
Chris Lattner | 441b223 | 2005-11-20 22:13:18 +0000 | [diff] [blame] | 1875 | |
| 1876 | |
| 1877 | //===----------------------------------------------------------------------===// |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 1878 | // Stack-based Floating point support |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1879 | //===----------------------------------------------------------------------===// |
| 1880 | |
| 1881 | // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP' |
| 1882 | |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 1883 | // Floating point instruction template |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1884 | class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm> |
Chris Lattner | c96bb81 | 2004-08-11 07:12:04 +0000 | [diff] [blame] | 1885 | : X86Inst<o, F, NoImm, ops, asm> { |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 1886 | let FPForm = fp; let FPFormBits = FPForm.Value; |
| 1887 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1888 | |
Chris Lattner | 9f8fd6d | 2004-02-02 19:31:38 +0000 | [diff] [blame] | 1889 | // Pseudo instructions for floating point. We use these pseudo instructions |
| 1890 | // because they can be expanded by the fp spackifier into one of many different |
| 1891 | // forms of instructions for doing these operations. Until the stackifier runs, |
| 1892 | // we prefer to be abstract. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1893 | def FpMOV : FPI<0, Pseudo, SpecialFP, |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 1894 | (ops RFP:$dst, RFP:$src), "">; // f1 = fmov f2 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1895 | def FpADD : FPI<0, Pseudo, TwoArgFP , |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 1896 | (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fadd f2, f3 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1897 | def FpSUB : FPI<0, Pseudo, TwoArgFP , |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 1898 | (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fsub f2, f3 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1899 | def FpMUL : FPI<0, Pseudo, TwoArgFP , |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 1900 | (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fmul f2, f3 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1901 | def FpDIV : FPI<0, Pseudo, TwoArgFP , |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 1902 | (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fdiv f2, f3 |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1903 | |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 1904 | def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$dst), "">, |
Alkis Evlogimenos | 93c1ab2 | 2004-09-08 18:29:31 +0000 | [diff] [blame] | 1905 | Imp<[ST0], []>; // FPR = ST(0) |
Alkis Evlogimenos | 978f629 | 2004-09-08 16:54:54 +0000 | [diff] [blame] | 1906 | |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 1907 | def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$src), "">, |
Alkis Evlogimenos | 93c1ab2 | 2004-09-08 18:29:31 +0000 | [diff] [blame] | 1908 | Imp<[], [ST0]>; // ST(0) = FPR |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1909 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1910 | // FADD reg, mem: Before stackification, these are represented by: |
| 1911 | // R1 = FADD* R2, [mem] |
| 1912 | def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real] |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1913 | (ops f32mem:$src, variable_ops), |
| 1914 | "fadd{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1915 | def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real] |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1916 | (ops f64mem:$src, variable_ops), |
| 1917 | "fadd{l} $src">; |
Chris Lattner | 60c715c | 2004-10-04 00:43:31 +0000 | [diff] [blame] | 1918 | //def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int] |
| 1919 | //def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int] |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1920 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1921 | // FMUL reg, mem: Before stackification, these are represented by: |
| 1922 | // R1 = FMUL* R2, [mem] |
| 1923 | def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real] |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1924 | (ops f32mem:$src, variable_ops), |
| 1925 | "fmul{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1926 | def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real] |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1927 | (ops f64mem:$src, variable_ops), |
| 1928 | "fmul{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1929 | // ST(0) = ST(0) * [mem16int] |
| 1930 | //def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>; |
| 1931 | // ST(0) = ST(0) * [mem32int] |
| 1932 | //def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1933 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1934 | // FSUB reg, mem: Before stackification, these are represented by: |
| 1935 | // R1 = FSUB* R2, [mem] |
| 1936 | def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real] |
Chris Lattner | 9d9dc81 | 2005-08-19 00:41:29 +0000 | [diff] [blame] | 1937 | (ops f32mem:$src, variable_ops), |
| 1938 | "fsub{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1939 | def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real] |
Chris Lattner | 9d9dc81 | 2005-08-19 00:41:29 +0000 | [diff] [blame] | 1940 | (ops f64mem:$src, variable_ops), |
| 1941 | "fsub{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1942 | // ST(0) = ST(0) - [mem16int] |
| 1943 | //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; |
| 1944 | // ST(0) = ST(0) - [mem32int] |
| 1945 | //def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1946 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1947 | // FSUBR reg, mem: Before stackification, these are represented by: |
| 1948 | // R1 = FSUBR* R2, [mem] |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1949 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1950 | // Note that the order of operands does not reflect the operation being |
| 1951 | // performed. |
| 1952 | def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0) |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1953 | (ops f32mem:$src, variable_ops), |
| 1954 | "fsubr{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1955 | def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0) |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1956 | (ops f64mem:$src, variable_ops), |
| 1957 | "fsubr{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1958 | // ST(0) = [mem16int] - ST(0) |
| 1959 | //def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>; |
| 1960 | // ST(0) = [mem32int] - ST(0) |
| 1961 | //def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1962 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1963 | // FDIV reg, mem: Before stackification, these are represented by: |
| 1964 | // R1 = FDIV* R2, [mem] |
| 1965 | def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real] |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1966 | (ops f32mem:$src, variable_ops), |
| 1967 | "fdiv{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1968 | def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real] |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1969 | (ops f64mem:$src, variable_ops), |
| 1970 | "fdiv{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1971 | // ST(0) = ST(0) / [mem16int] |
| 1972 | //def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>; |
| 1973 | // ST(0) = ST(0) / [mem32int] |
| 1974 | //def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>; |
| 1975 | |
| 1976 | // FDIVR reg, mem: Before stackification, these are represented by: |
| 1977 | // R1 = FDIVR* R2, [mem] |
| 1978 | // Note that the order of operands does not reflect the operation being |
| 1979 | // performed. |
| 1980 | def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0) |
Chris Lattner | 9d9dc81 | 2005-08-19 00:41:29 +0000 | [diff] [blame] | 1981 | (ops f32mem:$src, variable_ops), |
| 1982 | "fdivr{s} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1983 | def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0) |
Chris Lattner | 9d9dc81 | 2005-08-19 00:41:29 +0000 | [diff] [blame] | 1984 | (ops f64mem:$src, variable_ops), |
| 1985 | "fdivr{l} $src">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1986 | // ST(0) = [mem16int] / ST(0) |
| 1987 | //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; |
| 1988 | // ST(0) = [mem32int] / ST(0) |
| 1989 | //def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 1990 | |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 1991 | |
| 1992 | // Floating point cmovs... |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1993 | let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in { |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1994 | def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP, |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1995 | (ops RST:$op, variable_ops), |
| 1996 | "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 1997 | def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP, |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 1998 | (ops RST:$op, variable_ops), |
| 1999 | "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 2000 | def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP, |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2001 | (ops RST:$op, variable_ops), |
| 2002 | "fcmove {$op, %ST(0)|%ST(0), $op}">, DA; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 2003 | def FCMOVP : FPI<0xD8, AddRegFrm, CondMovFP, |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2004 | (ops RST:$op, variable_ops), |
| 2005 | "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 2006 | def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP, |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2007 | (ops RST:$op, variable_ops), |
| 2008 | "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 2009 | def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP, |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2010 | (ops RST:$op, variable_ops), |
| 2011 | "fcmova {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 0f38e6c | 2004-08-11 05:54:16 +0000 | [diff] [blame] | 2012 | def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP, |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2013 | (ops RST:$op, variable_ops), |
| 2014 | "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 2015 | def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP, |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2016 | (ops RST:$op, variable_ops), |
| 2017 | "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 2018 | } |
| 2019 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2020 | // Floating point loads & stores... |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2021 | // FIXME: these are all marked variable_ops because they have an implicit |
| 2022 | // destination. Instructions like FILD* that are generated by the instruction |
| 2023 | // selector (not the fp stackifier) need more accurate operand accounting. |
| 2024 | def FLDrr : FPI<0xC0, AddRegFrm, NotFP, |
| 2025 | (ops RST:$src, variable_ops), |
| 2026 | "fld $src">, D9; |
| 2027 | def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP, |
| 2028 | (ops f32mem:$src, variable_ops), |
| 2029 | "fld{s} $src">; |
| 2030 | def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP, |
| 2031 | (ops f64mem:$src, variable_ops), |
| 2032 | "fld{l} $src">; |
| 2033 | def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP, |
| 2034 | (ops f80mem:$src, variable_ops), |
| 2035 | "fld{t} $src">; |
| 2036 | def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP, |
| 2037 | (ops i16mem:$src, variable_ops), |
| 2038 | "fild{s} $src">; |
| 2039 | def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP, |
| 2040 | (ops i32mem:$src, variable_ops), |
| 2041 | "fild{l} $src">; |
| 2042 | def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP, |
| 2043 | (ops i64mem:$src, variable_ops), |
| 2044 | "fild{ll} $src">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2045 | |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2046 | def FSTrr : FPI<0xD0, AddRegFrm, NotFP, |
| 2047 | (ops RST:$op, variable_ops), |
| 2048 | "fst $op">, DD; |
| 2049 | def FSTPrr : FPI<0xD8, AddRegFrm, NotFP, |
| 2050 | (ops RST:$op, variable_ops), |
| 2051 | "fstp $op">, DD; |
| 2052 | def FST32m : FPI<0xD9, MRM2m, OneArgFP, |
| 2053 | (ops f32mem:$op, variable_ops), |
| 2054 | "fst{s} $op">; |
| 2055 | def FST64m : FPI<0xDD, MRM2m, OneArgFP, |
| 2056 | (ops f64mem:$op, variable_ops), |
| 2057 | "fst{l} $op">; |
| 2058 | def FSTP32m : FPI<0xD9, MRM3m, OneArgFP, |
| 2059 | (ops f32mem:$op, variable_ops), |
| 2060 | "fstp{s} $op">; |
| 2061 | def FSTP64m : FPI<0xDD, MRM3m, OneArgFP, |
| 2062 | (ops f64mem:$op, variable_ops), |
| 2063 | "fstp{l} $op">; |
| 2064 | def FSTP80m : FPI<0xDB, MRM7m, OneArgFP, |
| 2065 | (ops f80mem:$op, variable_ops), |
| 2066 | "fstp{t} $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2067 | |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2068 | def FIST16m : FPI<0xDF, MRM2m , OneArgFP, |
| 2069 | (ops i16mem:$op, variable_ops), |
| 2070 | "fist{s} $op">; |
| 2071 | def FIST32m : FPI<0xDB, MRM2m , OneArgFP, |
| 2072 | (ops i32mem:$op, variable_ops), |
| 2073 | "fist{l} $op">; |
| 2074 | def FISTP16m : FPI<0xDF, MRM3m , NotFP , |
| 2075 | (ops i16mem:$op, variable_ops), |
| 2076 | "fistp{s} $op">; |
| 2077 | def FISTP32m : FPI<0xDB, MRM3m , NotFP , |
| 2078 | (ops i32mem:$op, variable_ops), |
| 2079 | "fistp{l} $op">; |
| 2080 | def FISTP64m : FPI<0xDF, MRM7m , OneArgFP, |
| 2081 | (ops i64mem:$op, variable_ops), |
| 2082 | "fistp{ll} $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2083 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2084 | def FXCH : FPI<0xC8, AddRegFrm, NotFP, |
| 2085 | (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0) |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2086 | |
| 2087 | // Floating point constant loads... |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2088 | def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops variable_ops), "fldz">, D9; |
| 2089 | def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops variable_ops), "fld1">, D9; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2090 | |
Chris Lattner | 9f8fd6d | 2004-02-02 19:31:38 +0000 | [diff] [blame] | 2091 | |
Chris Lattner | 3b904eb | 2004-02-03 07:27:50 +0000 | [diff] [blame] | 2092 | // Unary operations... |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2093 | def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, // f1 = fchs f2 |
| 2094 | (ops variable_ops), |
| 2095 | "fchs">, D9; |
| 2096 | def FABS : FPI<0xE1, RawFrm, OneArgFPRW, // f1 = fabs f2 |
| 2097 | (ops variable_ops), |
| 2098 | "fabs">, D9; |
| 2099 | def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW, // fsqrt ST(0) |
| 2100 | (ops variable_ops), |
| 2101 | "fsqrt">, D9; |
| 2102 | def FSIN : FPI<0xFE, RawFrm, OneArgFPRW, // fsin ST(0) |
| 2103 | (ops variable_ops), |
| 2104 | "fsin">, D9; |
| 2105 | def FCOS : FPI<0xFF, RawFrm, OneArgFPRW, // fcos ST(0) |
| 2106 | (ops variable_ops), |
| 2107 | "fcos">, D9; |
| 2108 | def FTST : FPI<0xE4, RawFrm, OneArgFP , // ftst ST(0) |
| 2109 | (ops variable_ops), |
| 2110 | "ftst">, D9; |
Chris Lattner | 3b904eb | 2004-02-03 07:27:50 +0000 | [diff] [blame] | 2111 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2112 | // Binary arithmetic operations... |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2113 | class FPST0rInst<bits<8> o, dag ops, string asm> |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2114 | : I<o, AddRegFrm, ops, asm, []>, D8 { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2115 | list<Register> Uses = [ST0]; |
| 2116 | list<Register> Defs = [ST0]; |
| 2117 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2118 | class FPrST0Inst<bits<8> o, dag ops, string asm> |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2119 | : I<o, AddRegFrm, ops, asm, []>, DC { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2120 | list<Register> Uses = [ST0]; |
| 2121 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2122 | class FPrST0PInst<bits<8> o, dag ops, string asm> |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2123 | : I<o, AddRegFrm, ops, asm, []>, DE { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2124 | list<Register> Uses = [ST0]; |
| 2125 | } |
| 2126 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2127 | def FADDST0r : FPST0rInst <0xC0, (ops RST:$op), |
| 2128 | "fadd $op">; |
| 2129 | def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op), |
| 2130 | "fadd {%ST(0), $op|$op, %ST(0)}">; |
| 2131 | def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op), |
| 2132 | "faddp $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2133 | |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2134 | // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion |
| 2135 | // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, |
Chris Lattner | da895d6 | 2005-02-27 06:18:25 +0000 | [diff] [blame] | 2136 | // we have to put some 'r's in and take them out of weird places. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2137 | def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op), |
| 2138 | "fsubr $op">; |
| 2139 | def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2140 | "fsub{r} {%ST(0), $op|$op, %ST(0)}">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2141 | def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2142 | "fsub{r}p $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2143 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2144 | def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op), |
| 2145 | "fsub $op">; |
| 2146 | def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2147 | "fsub{|r} {%ST(0), $op|$op, %ST(0)}">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2148 | def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2149 | "fsub{|r}p $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2150 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2151 | def FMULST0r : FPST0rInst <0xC8, (ops RST:$op), |
| 2152 | "fmul $op">; |
| 2153 | def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op), |
| 2154 | "fmul {%ST(0), $op|$op, %ST(0)}">; |
| 2155 | def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op), |
| 2156 | "fmulp $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2157 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2158 | def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op), |
| 2159 | "fdivr $op">; |
| 2160 | def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2161 | "fdiv{r} {%ST(0), $op|$op, %ST(0)}">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2162 | def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op), |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2163 | "fdiv{r}p $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2164 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2165 | def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i) |
| 2166 | "fdiv $op">; |
| 2167 | def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i) |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2168 | "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2169 | def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop |
Chris Lattner | 10f873b | 2004-10-04 07:08:46 +0000 | [diff] [blame] | 2170 | "fdiv{|r}p $op">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2171 | |
| 2172 | // Floating point compares |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2173 | def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i) |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2174 | (ops RST:$reg, variable_ops), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2175 | "fucom $reg">, DD, Imp<[ST0],[]>; |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2176 | def FUCOMPr : I<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop |
| 2177 | (ops RST:$reg, variable_ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2178 | "fucomp $reg", []>, DD, Imp<[ST0],[]>; |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2179 | def FUCOMPPr : I<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop |
| 2180 | (ops variable_ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2181 | "fucompp", []>, DA, Imp<[ST0],[]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2182 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2183 | def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i) |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2184 | (ops RST:$reg, variable_ops), |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2185 | "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; |
| 2186 | def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop |
Chris Lattner | b822aba | 2005-08-19 00:38:22 +0000 | [diff] [blame] | 2187 | (ops RST:$reg, variable_ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2188 | "fucomip {$reg, %ST(0)|%ST(0), $reg}", []>, DF, Imp<[ST0],[]>; |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 2189 | |
Chris Lattner | a1b5e16 | 2004-04-12 01:38:55 +0000 | [diff] [blame] | 2190 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 2191 | // Floating point flag ops |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2192 | def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2193 | (ops), "fnstsw", []>, DF, Imp<[],[AX]>; |
Chris Lattner | 96563df | 2004-08-01 06:01:00 +0000 | [diff] [blame] | 2194 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2195 | def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2196 | (ops i16mem:$dst), "fnstcw $dst", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2197 | def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2198 | (ops i16mem:$dst), "fldcw $dst", []>; |