Duncan Sands | 9d32f60 | 2011-01-20 13:21:55 +0000 | [diff] [blame] | 1 | ; RUN: opt < %s -instsimplify -S | FileCheck %s |
| 2 | target datalayout = "p:32:32" |
| 3 | |
| 4 | define i1 @ptrtoint() { |
| 5 | ; CHECK: @ptrtoint |
| 6 | %a = alloca i8 |
| 7 | %tmp = ptrtoint i8* %a to i32 |
| 8 | %r = icmp eq i32 %tmp, 0 |
| 9 | ret i1 %r |
| 10 | ; CHECK: ret i1 false |
| 11 | } |
| 12 | |
Benjamin Kramer | fd8779a | 2012-02-16 13:49:39 +0000 | [diff] [blame] | 13 | define i1 @bitcast() { |
| 14 | ; CHECK: @bitcast |
| 15 | %a = alloca i32 |
| 16 | %b = alloca i64 |
| 17 | %x = bitcast i32* %a to i8* |
| 18 | %y = bitcast i64* %b to i8* |
| 19 | %cmp = icmp eq i8* %x, %y |
| 20 | ret i1 %cmp |
| 21 | ; CHECK-NEXT: ret i1 false |
| 22 | } |
| 23 | |
| 24 | define i1 @gep() { |
| 25 | ; CHECK: @gep |
| 26 | %a = alloca [3 x i8], align 8 |
| 27 | %x = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0 |
| 28 | %cmp = icmp eq i8* %x, null |
| 29 | ret i1 %cmp |
| 30 | ; CHECK-NEXT: ret i1 false |
| 31 | } |
| 32 | |
Eli Friedman | 2c3acb0 | 2012-02-18 03:29:25 +0000 | [diff] [blame^] | 33 | define i1 @gep2() { |
| 34 | ; CHECK: @gep2 |
| 35 | %a = alloca [3 x i8], align 8 |
| 36 | %x = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0 |
| 37 | %y = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0 |
| 38 | %cmp = icmp eq i8* %x, %y |
| 39 | ret i1 %cmp |
| 40 | ; CHECK-NEXT: ret i1 true |
| 41 | } |
| 42 | |
Duncan Sands | 9d32f60 | 2011-01-20 13:21:55 +0000 | [diff] [blame] | 43 | define i1 @zext(i32 %x) { |
| 44 | ; CHECK: @zext |
| 45 | %e1 = zext i32 %x to i64 |
| 46 | %e2 = zext i32 %x to i64 |
| 47 | %r = icmp eq i64 %e1, %e2 |
| 48 | ret i1 %r |
| 49 | ; CHECK: ret i1 true |
| 50 | } |
| 51 | |
| 52 | define i1 @zext2(i1 %x) { |
| 53 | ; CHECK: @zext2 |
| 54 | %e = zext i1 %x to i32 |
| 55 | %c = icmp ne i32 %e, 0 |
| 56 | ret i1 %c |
| 57 | ; CHECK: ret i1 %x |
| 58 | } |
| 59 | |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 60 | define i1 @zext3() { |
| 61 | ; CHECK: @zext3 |
| 62 | %e = zext i1 1 to i32 |
| 63 | %c = icmp ne i32 %e, 0 |
| 64 | ret i1 %c |
| 65 | ; CHECK: ret i1 true |
| 66 | } |
| 67 | |
Duncan Sands | 9d32f60 | 2011-01-20 13:21:55 +0000 | [diff] [blame] | 68 | define i1 @sext(i32 %x) { |
| 69 | ; CHECK: @sext |
| 70 | %e1 = sext i32 %x to i64 |
| 71 | %e2 = sext i32 %x to i64 |
| 72 | %r = icmp eq i64 %e1, %e2 |
| 73 | ret i1 %r |
| 74 | ; CHECK: ret i1 true |
| 75 | } |
| 76 | |
| 77 | define i1 @sext2(i1 %x) { |
| 78 | ; CHECK: @sext2 |
| 79 | %e = sext i1 %x to i32 |
| 80 | %c = icmp ne i32 %e, 0 |
| 81 | ret i1 %c |
| 82 | ; CHECK: ret i1 %x |
| 83 | } |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 84 | |
| 85 | define i1 @sext3() { |
| 86 | ; CHECK: @sext3 |
| 87 | %e = sext i1 1 to i32 |
| 88 | %c = icmp ne i32 %e, 0 |
| 89 | ret i1 %c |
| 90 | ; CHECK: ret i1 true |
| 91 | } |
| 92 | |
| 93 | define i1 @add(i32 %x, i32 %y) { |
Duncan Sands | 227fba1 | 2011-01-25 15:14:15 +0000 | [diff] [blame] | 94 | ; CHECK: @add |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 95 | %l = lshr i32 %x, 1 |
Duncan Sands | 227fba1 | 2011-01-25 15:14:15 +0000 | [diff] [blame] | 96 | %q = lshr i32 %y, 1 |
| 97 | %r = or i32 %q, 1 |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 98 | %s = add i32 %l, %r |
| 99 | %c = icmp eq i32 %s, 0 |
| 100 | ret i1 %c |
Duncan Sands | 227fba1 | 2011-01-25 15:14:15 +0000 | [diff] [blame] | 101 | ; CHECK: ret i1 false |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | define i1 @add2(i8 %x, i8 %y) { |
| 105 | ; CHECK: @add2 |
| 106 | %l = or i8 %x, 128 |
| 107 | %r = or i8 %y, 129 |
| 108 | %s = add i8 %l, %r |
| 109 | %c = icmp eq i8 %s, 0 |
| 110 | ret i1 %c |
| 111 | ; CHECK: ret i1 false |
| 112 | } |
| 113 | |
Duncan Sands | 227fba1 | 2011-01-25 15:14:15 +0000 | [diff] [blame] | 114 | define i1 @add3(i8 %x, i8 %y) { |
| 115 | ; CHECK: @add3 |
| 116 | %l = zext i8 %x to i32 |
| 117 | %r = zext i8 %y to i32 |
| 118 | %s = add i32 %l, %r |
| 119 | %c = icmp eq i32 %s, 0 |
| 120 | ret i1 %c |
| 121 | ; CHECK: ret i1 %c |
| 122 | } |
| 123 | |
Duncan Sands | 52fb846 | 2011-02-13 17:15:40 +0000 | [diff] [blame] | 124 | define i1 @add4(i32 %x, i32 %y) { |
| 125 | ; CHECK: @add4 |
| 126 | %z = add nsw i32 %y, 1 |
| 127 | %s1 = add nsw i32 %x, %y |
| 128 | %s2 = add nsw i32 %x, %z |
| 129 | %c = icmp slt i32 %s1, %s2 |
| 130 | ret i1 %c |
| 131 | ; CHECK: ret i1 true |
| 132 | } |
| 133 | |
| 134 | define i1 @add5(i32 %x, i32 %y) { |
| 135 | ; CHECK: @add5 |
| 136 | %z = add nuw i32 %y, 1 |
| 137 | %s1 = add nuw i32 %x, %z |
| 138 | %s2 = add nuw i32 %x, %y |
| 139 | %c = icmp ugt i32 %s1, %s2 |
| 140 | ret i1 %c |
| 141 | ; CHECK: ret i1 true |
| 142 | } |
| 143 | |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 144 | define i1 @addpowtwo(i32 %x, i32 %y) { |
| 145 | ; CHECK: @addpowtwo |
| 146 | %l = lshr i32 %x, 1 |
| 147 | %r = shl i32 1, %y |
| 148 | %s = add i32 %l, %r |
| 149 | %c = icmp eq i32 %s, 0 |
| 150 | ret i1 %c |
| 151 | ; CHECK: ret i1 false |
| 152 | } |
| 153 | |
| 154 | define i1 @or(i32 %x) { |
| 155 | ; CHECK: @or |
| 156 | %o = or i32 %x, 1 |
| 157 | %c = icmp eq i32 %o, 0 |
| 158 | ret i1 %c |
| 159 | ; CHECK: ret i1 false |
| 160 | } |
Duncan Sands | 9136782 | 2011-01-29 13:27:00 +0000 | [diff] [blame] | 161 | |
| 162 | define i1 @shl(i32 %x) { |
| 163 | ; CHECK: @shl |
| 164 | %s = shl i32 1, %x |
| 165 | %c = icmp eq i32 %s, 0 |
| 166 | ret i1 %c |
| 167 | ; CHECK: ret i1 false |
| 168 | } |
| 169 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 170 | define i1 @lshr1(i32 %x) { |
| 171 | ; CHECK: @lshr1 |
Duncan Sands | 9136782 | 2011-01-29 13:27:00 +0000 | [diff] [blame] | 172 | %s = lshr i32 -1, %x |
| 173 | %c = icmp eq i32 %s, 0 |
| 174 | ret i1 %c |
| 175 | ; CHECK: ret i1 false |
| 176 | } |
| 177 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 178 | define i1 @lshr2(i32 %x) { |
| 179 | ; CHECK: @lshr2 |
| 180 | %s = lshr i32 %x, 30 |
| 181 | %c = icmp ugt i32 %s, 8 |
| 182 | ret i1 %c |
| 183 | ; CHECK: ret i1 false |
| 184 | } |
| 185 | |
| 186 | define i1 @ashr1(i32 %x) { |
| 187 | ; CHECK: @ashr1 |
Duncan Sands | 9136782 | 2011-01-29 13:27:00 +0000 | [diff] [blame] | 188 | %s = ashr i32 -1, %x |
| 189 | %c = icmp eq i32 %s, 0 |
| 190 | ret i1 %c |
| 191 | ; CHECK: ret i1 false |
| 192 | } |
Duncan Sands | 50ca4d3 | 2011-02-03 09:37:39 +0000 | [diff] [blame] | 193 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 194 | define i1 @ashr2(i32 %x) { |
| 195 | ; CHECK: @ashr2 |
| 196 | %s = ashr i32 %x, 30 |
| 197 | %c = icmp slt i32 %s, -5 |
| 198 | ret i1 %c |
| 199 | ; CHECK: ret i1 false |
| 200 | } |
| 201 | |
Duncan Sands | 50ca4d3 | 2011-02-03 09:37:39 +0000 | [diff] [blame] | 202 | define i1 @select1(i1 %cond) { |
| 203 | ; CHECK: @select1 |
| 204 | %s = select i1 %cond, i32 1, i32 0 |
| 205 | %c = icmp eq i32 %s, 1 |
| 206 | ret i1 %c |
| 207 | ; CHECK: ret i1 %cond |
| 208 | } |
| 209 | |
| 210 | define i1 @select2(i1 %cond) { |
| 211 | ; CHECK: @select2 |
| 212 | %x = zext i1 %cond to i32 |
| 213 | %s = select i1 %cond, i32 %x, i32 0 |
| 214 | %c = icmp ne i32 %s, 0 |
| 215 | ret i1 %c |
| 216 | ; CHECK: ret i1 %cond |
| 217 | } |
| 218 | |
| 219 | define i1 @select3(i1 %cond) { |
| 220 | ; CHECK: @select3 |
| 221 | %x = zext i1 %cond to i32 |
| 222 | %s = select i1 %cond, i32 1, i32 %x |
| 223 | %c = icmp ne i32 %s, 0 |
| 224 | ret i1 %c |
| 225 | ; CHECK: ret i1 %cond |
| 226 | } |
| 227 | |
| 228 | define i1 @select4(i1 %cond) { |
| 229 | ; CHECK: @select4 |
| 230 | %invert = xor i1 %cond, 1 |
| 231 | %s = select i1 %invert, i32 0, i32 1 |
| 232 | %c = icmp ne i32 %s, 0 |
| 233 | ret i1 %c |
| 234 | ; CHECK: ret i1 %cond |
| 235 | } |
Nick Lewycky | 88cd0aa | 2011-03-01 08:15:50 +0000 | [diff] [blame] | 236 | |
Duncan Sands | 6dc9e2b | 2011-10-30 19:56:36 +0000 | [diff] [blame] | 237 | define i1 @select5(i32 %x) { |
| 238 | ; CHECK: @select5 |
| 239 | %c = icmp eq i32 %x, 0 |
| 240 | %s = select i1 %c, i32 1, i32 %x |
| 241 | %c2 = icmp eq i32 %s, 0 |
| 242 | ret i1 %c2 |
| 243 | ; CHECK: ret i1 false |
| 244 | } |
| 245 | |
| 246 | define i1 @select6(i32 %x) { |
| 247 | ; CHECK: @select6 |
| 248 | %c = icmp sgt i32 %x, 0 |
| 249 | %s = select i1 %c, i32 %x, i32 4 |
| 250 | %c2 = icmp eq i32 %s, 0 |
| 251 | ret i1 %c2 |
| 252 | ; CHECK: ret i1 %c2 |
| 253 | } |
| 254 | |
Nick Lewycky | 88cd0aa | 2011-03-01 08:15:50 +0000 | [diff] [blame] | 255 | define i1 @urem1(i32 %X, i32 %Y) { |
| 256 | ; CHECK: @urem1 |
| 257 | %A = urem i32 %X, %Y |
| 258 | %B = icmp ult i32 %A, %Y |
| 259 | ret i1 %B |
| 260 | ; CHECK: ret i1 true |
| 261 | } |
| 262 | |
| 263 | define i1 @urem2(i32 %X, i32 %Y) { |
| 264 | ; CHECK: @urem2 |
| 265 | %A = urem i32 %X, %Y |
| 266 | %B = icmp eq i32 %A, %Y |
| 267 | ret i1 %B |
Benjamin Kramer | 7bff3e7 | 2011-03-09 22:07:31 +0000 | [diff] [blame] | 268 | ; CHECK: ret i1 false |
Nick Lewycky | 88cd0aa | 2011-03-01 08:15:50 +0000 | [diff] [blame] | 269 | } |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 270 | |
| 271 | define i1 @urem3(i32 %X) { |
| 272 | ; CHECK: @urem3 |
| 273 | %A = urem i32 %X, 10 |
| 274 | %B = icmp ult i32 %A, 15 |
| 275 | ret i1 %B |
| 276 | ; CHECK: ret i1 true |
| 277 | } |
| 278 | |
| 279 | define i1 @urem4(i32 %X) { |
| 280 | ; CHECK: @urem4 |
| 281 | %A = urem i32 %X, 15 |
| 282 | %B = icmp ult i32 %A, 10 |
| 283 | ret i1 %B |
| 284 | ; CHECK: ret i1 %B |
| 285 | } |
| 286 | |
Nick Lewycky | 7867927 | 2011-03-04 10:06:52 +0000 | [diff] [blame] | 287 | define i1 @urem5(i16 %X, i32 %Y) { |
| 288 | ; CHECK: @urem5 |
| 289 | %A = zext i16 %X to i32 |
| 290 | %B = urem i32 %A, %Y |
| 291 | %C = icmp slt i32 %B, %Y |
| 292 | ret i1 %C |
| 293 | ; CHECK: ret i1 true |
| 294 | } |
| 295 | |
Nick Lewycky | 84dd4fa | 2011-03-09 06:26:03 +0000 | [diff] [blame] | 296 | define i1 @urem6(i32 %X, i32 %Y) { |
| 297 | ; CHECK: @urem6 |
| 298 | %A = urem i32 %X, %Y |
| 299 | %B = icmp ugt i32 %Y, %A |
| 300 | ret i1 %B |
| 301 | ; CHECK: ret i1 true |
| 302 | } |
| 303 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 304 | define i1 @srem1(i32 %X) { |
| 305 | ; CHECK: @srem1 |
| 306 | %A = srem i32 %X, -5 |
| 307 | %B = icmp sgt i32 %A, 5 |
| 308 | ret i1 %B |
| 309 | ; CHECK: ret i1 false |
| 310 | } |
| 311 | |
Nick Lewycky | b69050a | 2011-03-11 09:00:19 +0000 | [diff] [blame] | 312 | ; PR9343 #15 |
| 313 | ; CHECK: @srem2 |
| 314 | ; CHECK: ret i1 false |
| 315 | define i1 @srem2(i16 %X, i32 %Y) { |
| 316 | %A = zext i16 %X to i32 |
| 317 | %B = add nsw i32 %A, 1 |
| 318 | %C = srem i32 %B, %Y |
| 319 | %D = icmp slt i32 %C, 0 |
| 320 | ret i1 %D |
| 321 | } |
Benjamin Kramer | 14b2a59 | 2011-03-12 17:18:11 +0000 | [diff] [blame] | 322 | |
| 323 | ; CHECK: @srem3 |
| 324 | ; CHECK-NEXT: ret i1 false |
| 325 | define i1 @srem3(i16 %X, i32 %Y) { |
| 326 | %A = zext i16 %X to i32 |
| 327 | %B = or i32 2147483648, %A |
| 328 | %C = sub nsw i32 1, %B |
| 329 | %D = srem i32 %C, %Y |
| 330 | %E = icmp slt i32 %D, 0 |
| 331 | ret i1 %E |
| 332 | } |
| 333 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 334 | define i1 @udiv1(i32 %X) { |
| 335 | ; CHECK: @udiv1 |
| 336 | %A = udiv i32 %X, 1000000 |
| 337 | %B = icmp ult i32 %A, 5000 |
| 338 | ret i1 %B |
| 339 | ; CHECK: ret i1 true |
| 340 | } |
| 341 | |
Nick Lewycky | 58bfcdb | 2011-03-05 05:19:11 +0000 | [diff] [blame] | 342 | define i1 @udiv2(i32 %X, i32 %Y, i32 %Z) { |
| 343 | ; CHECK: @udiv2 |
| 344 | %A = udiv exact i32 10, %Z |
| 345 | %B = udiv exact i32 20, %Z |
| 346 | %C = icmp ult i32 %A, %B |
| 347 | ret i1 %C |
| 348 | ; CHECK: ret i1 true |
| 349 | } |
| 350 | |
Duncan Sands | c65c747 | 2011-10-28 18:17:44 +0000 | [diff] [blame] | 351 | define i1 @udiv3(i32 %X, i32 %Y) { |
| 352 | ; CHECK: @udiv3 |
| 353 | %A = udiv i32 %X, %Y |
| 354 | %C = icmp ugt i32 %A, %X |
| 355 | ret i1 %C |
| 356 | ; CHECK: ret i1 false |
| 357 | } |
| 358 | |
| 359 | define i1 @udiv4(i32 %X, i32 %Y) { |
| 360 | ; CHECK: @udiv4 |
| 361 | %A = udiv i32 %X, %Y |
| 362 | %C = icmp ule i32 %A, %X |
| 363 | ret i1 %C |
| 364 | ; CHECK: ret i1 true |
| 365 | } |
| 366 | |
| 367 | define i1 @udiv5(i32 %X) { |
| 368 | ; CHECK: @udiv5 |
| 369 | %A = udiv i32 123, %X |
| 370 | %C = icmp ugt i32 %A, 124 |
| 371 | ret i1 %C |
| 372 | ; CHECK: ret i1 false |
| 373 | } |
| 374 | |
Eli Friedman | 7781ae5 | 2011-11-08 21:08:02 +0000 | [diff] [blame] | 375 | ; PR11340 |
| 376 | define i1 @udiv6(i32 %X) nounwind { |
| 377 | ; CHECK: @udiv6 |
| 378 | %A = udiv i32 1, %X |
| 379 | %C = icmp eq i32 %A, 0 |
| 380 | ret i1 %C |
| 381 | ; CHECK: ret i1 %C |
| 382 | } |
| 383 | |
| 384 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 385 | define i1 @sdiv1(i32 %X) { |
| 386 | ; CHECK: @sdiv1 |
| 387 | %A = sdiv i32 %X, 1000000 |
| 388 | %B = icmp slt i32 %A, 3000 |
| 389 | ret i1 %B |
| 390 | ; CHECK: ret i1 true |
| 391 | } |
| 392 | |
| 393 | define i1 @or1(i32 %X) { |
| 394 | ; CHECK: @or1 |
| 395 | %A = or i32 %X, 62 |
| 396 | %B = icmp ult i32 %A, 50 |
| 397 | ret i1 %B |
| 398 | ; CHECK: ret i1 false |
| 399 | } |
| 400 | |
| 401 | define i1 @and1(i32 %X) { |
| 402 | ; CHECK: @and1 |
| 403 | %A = and i32 %X, 62 |
| 404 | %B = icmp ugt i32 %A, 70 |
| 405 | ret i1 %B |
| 406 | ; CHECK: ret i1 false |
| 407 | } |
Duncan Sands | 32a43cc | 2011-10-27 19:16:21 +0000 | [diff] [blame] | 408 | |
| 409 | define i1 @mul1(i32 %X) { |
| 410 | ; CHECK: @mul1 |
| 411 | ; Square of a non-zero number is non-zero if there is no overflow. |
| 412 | %Y = or i32 %X, 1 |
| 413 | %M = mul nuw i32 %Y, %Y |
| 414 | %C = icmp eq i32 %M, 0 |
| 415 | ret i1 %C |
| 416 | ; CHECK: ret i1 false |
| 417 | } |
| 418 | |
| 419 | define i1 @mul2(i32 %X) { |
| 420 | ; CHECK: @mul2 |
| 421 | ; Square of a non-zero number is positive if there is no signed overflow. |
| 422 | %Y = or i32 %X, 1 |
| 423 | %M = mul nsw i32 %Y, %Y |
| 424 | %C = icmp sgt i32 %M, 0 |
| 425 | ret i1 %C |
| 426 | ; CHECK: ret i1 true |
| 427 | } |
| 428 | |
| 429 | define i1 @mul3(i32 %X, i32 %Y) { |
| 430 | ; CHECK: @mul3 |
| 431 | ; Product of non-negative numbers is non-negative if there is no signed overflow. |
| 432 | %XX = mul nsw i32 %X, %X |
| 433 | %YY = mul nsw i32 %Y, %Y |
| 434 | %M = mul nsw i32 %XX, %YY |
| 435 | %C = icmp sge i32 %M, 0 |
| 436 | ret i1 %C |
| 437 | ; CHECK: ret i1 true |
| 438 | } |
Duncan Sands | edfb931 | 2012-02-10 14:26:42 +0000 | [diff] [blame] | 439 | |
| 440 | define <2 x i1> @vectorselect1(<2 x i1> %cond) { |
| 441 | ; CHECK: @vectorselect1 |
| 442 | %invert = xor <2 x i1> %cond, <i1 1, i1 1> |
| 443 | %s = select <2 x i1> %invert, <2 x i32> <i32 0, i32 0>, <2 x i32> <i32 1, i32 1> |
| 444 | %c = icmp ne <2 x i32> %s, <i32 0, i32 0> |
| 445 | ret <2 x i1> %c |
| 446 | ; CHECK: ret <2 x i1> %cond |
| 447 | } |
Duncan Sands | aa97bb5 | 2012-02-10 14:31:24 +0000 | [diff] [blame] | 448 | |
| 449 | define <2 x i1> @vectorselectcrash(i32 %arg1) { ; PR11948 |
| 450 | %tobool40 = icmp ne i32 %arg1, 0 |
| 451 | %cond43 = select i1 %tobool40, <2 x i16> <i16 -5, i16 66>, <2 x i16> <i16 46, i16 1> |
| 452 | %cmp45 = icmp ugt <2 x i16> %cond43, <i16 73, i16 21> |
| 453 | ret <2 x i1> %cmp45 |
| 454 | } |