Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
| 8 | * license, and/or sell copies of the Software, and to permit persons to whom |
| 9 | * the Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 19 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 20 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 21 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
Marek Olšák | 330b6c8 | 2012-03-05 15:17:00 +0100 | [diff] [blame] | 23 | #include "r600_formats.h" |
Marek Olšák | 555c8d5 | 2012-10-12 18:30:51 +0200 | [diff] [blame] | 24 | #include "r600_shader.h" |
Marek Olšák | 330b6c8 | 2012-03-05 15:17:00 +0100 | [diff] [blame] | 25 | #include "r600d.h" |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 26 | |
Marek Olšák | 330b6c8 | 2012-03-05 15:17:00 +0100 | [diff] [blame] | 27 | #include "pipe/p_shader_tokens.h" |
Kai Wasserbäch | 8fb7f1a | 2011-08-27 17:51:51 +0200 | [diff] [blame] | 28 | #include "util/u_pack_color.h" |
| 29 | #include "util/u_memory.h" |
Kai Wasserbäch | 8fb7f1a | 2011-08-27 17:51:51 +0200 | [diff] [blame] | 30 | #include "util/u_framebuffer.h" |
Dave Airlie | d1cc87c | 2012-03-24 13:37:16 +0000 | [diff] [blame] | 31 | #include "util/u_dual_blend.h" |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 32 | |
| 33 | static uint32_t r600_translate_blend_function(int blend_func) |
| 34 | { |
| 35 | switch (blend_func) { |
| 36 | case PIPE_BLEND_ADD: |
| 37 | return V_028804_COMB_DST_PLUS_SRC; |
| 38 | case PIPE_BLEND_SUBTRACT: |
| 39 | return V_028804_COMB_SRC_MINUS_DST; |
| 40 | case PIPE_BLEND_REVERSE_SUBTRACT: |
| 41 | return V_028804_COMB_DST_MINUS_SRC; |
| 42 | case PIPE_BLEND_MIN: |
| 43 | return V_028804_COMB_MIN_DST_SRC; |
| 44 | case PIPE_BLEND_MAX: |
| 45 | return V_028804_COMB_MAX_DST_SRC; |
| 46 | default: |
| 47 | R600_ERR("Unknown blend function %d\n", blend_func); |
| 48 | assert(0); |
| 49 | break; |
| 50 | } |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | static uint32_t r600_translate_blend_factor(int blend_fact) |
| 55 | { |
| 56 | switch (blend_fact) { |
| 57 | case PIPE_BLENDFACTOR_ONE: |
| 58 | return V_028804_BLEND_ONE; |
| 59 | case PIPE_BLENDFACTOR_SRC_COLOR: |
| 60 | return V_028804_BLEND_SRC_COLOR; |
| 61 | case PIPE_BLENDFACTOR_SRC_ALPHA: |
| 62 | return V_028804_BLEND_SRC_ALPHA; |
| 63 | case PIPE_BLENDFACTOR_DST_ALPHA: |
| 64 | return V_028804_BLEND_DST_ALPHA; |
| 65 | case PIPE_BLENDFACTOR_DST_COLOR: |
| 66 | return V_028804_BLEND_DST_COLOR; |
| 67 | case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: |
| 68 | return V_028804_BLEND_SRC_ALPHA_SATURATE; |
| 69 | case PIPE_BLENDFACTOR_CONST_COLOR: |
| 70 | return V_028804_BLEND_CONST_COLOR; |
| 71 | case PIPE_BLENDFACTOR_CONST_ALPHA: |
| 72 | return V_028804_BLEND_CONST_ALPHA; |
| 73 | case PIPE_BLENDFACTOR_ZERO: |
| 74 | return V_028804_BLEND_ZERO; |
| 75 | case PIPE_BLENDFACTOR_INV_SRC_COLOR: |
| 76 | return V_028804_BLEND_ONE_MINUS_SRC_COLOR; |
| 77 | case PIPE_BLENDFACTOR_INV_SRC_ALPHA: |
| 78 | return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; |
| 79 | case PIPE_BLENDFACTOR_INV_DST_ALPHA: |
| 80 | return V_028804_BLEND_ONE_MINUS_DST_ALPHA; |
| 81 | case PIPE_BLENDFACTOR_INV_DST_COLOR: |
| 82 | return V_028804_BLEND_ONE_MINUS_DST_COLOR; |
| 83 | case PIPE_BLENDFACTOR_INV_CONST_COLOR: |
| 84 | return V_028804_BLEND_ONE_MINUS_CONST_COLOR; |
| 85 | case PIPE_BLENDFACTOR_INV_CONST_ALPHA: |
| 86 | return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; |
| 87 | case PIPE_BLENDFACTOR_SRC1_COLOR: |
| 88 | return V_028804_BLEND_SRC1_COLOR; |
| 89 | case PIPE_BLENDFACTOR_SRC1_ALPHA: |
| 90 | return V_028804_BLEND_SRC1_ALPHA; |
| 91 | case PIPE_BLENDFACTOR_INV_SRC1_COLOR: |
| 92 | return V_028804_BLEND_INV_SRC1_COLOR; |
| 93 | case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: |
| 94 | return V_028804_BLEND_INV_SRC1_ALPHA; |
| 95 | default: |
| 96 | R600_ERR("Bad blend factor %d not supported!\n", blend_fact); |
| 97 | assert(0); |
| 98 | break; |
| 99 | } |
| 100 | return 0; |
| 101 | } |
| 102 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 103 | static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples) |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 104 | { |
| 105 | switch (dim) { |
| 106 | default: |
| 107 | case PIPE_TEXTURE_1D: |
| 108 | return V_038000_SQ_TEX_DIM_1D; |
| 109 | case PIPE_TEXTURE_1D_ARRAY: |
| 110 | return V_038000_SQ_TEX_DIM_1D_ARRAY; |
| 111 | case PIPE_TEXTURE_2D: |
| 112 | case PIPE_TEXTURE_RECT: |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 113 | return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA : |
| 114 | V_038000_SQ_TEX_DIM_2D; |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 115 | case PIPE_TEXTURE_2D_ARRAY: |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 116 | return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA : |
| 117 | V_038000_SQ_TEX_DIM_2D_ARRAY; |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 118 | case PIPE_TEXTURE_3D: |
| 119 | return V_038000_SQ_TEX_DIM_3D; |
| 120 | case PIPE_TEXTURE_CUBE: |
Dave Airlie | eb44c36d | 2012-11-03 20:53:33 +1000 | [diff] [blame] | 121 | case PIPE_TEXTURE_CUBE_ARRAY: |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 122 | return V_038000_SQ_TEX_DIM_CUBEMAP; |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | static uint32_t r600_translate_dbformat(enum pipe_format format) |
| 127 | { |
| 128 | switch (format) { |
| 129 | case PIPE_FORMAT_Z16_UNORM: |
| 130 | return V_028010_DEPTH_16; |
| 131 | case PIPE_FORMAT_Z24X8_UNORM: |
| 132 | return V_028010_DEPTH_X8_24; |
Dave Airlie | 866f9b1 | 2011-09-11 09:45:10 +0100 | [diff] [blame] | 133 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 134 | return V_028010_DEPTH_8_24; |
Marek Olšák | 8995472 | 2011-06-20 19:40:41 +0200 | [diff] [blame] | 135 | case PIPE_FORMAT_Z32_FLOAT: |
| 136 | return V_028010_DEPTH_32_FLOAT; |
Dave Airlie | 866f9b1 | 2011-09-11 09:45:10 +0100 | [diff] [blame] | 137 | case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: |
Marek Olšák | 8995472 | 2011-06-20 19:40:41 +0200 | [diff] [blame] | 138 | return V_028010_DEPTH_X24_8_32_FLOAT; |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 139 | default: |
| 140 | return ~0U; |
| 141 | } |
| 142 | } |
| 143 | |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 144 | static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) |
| 145 | { |
| 146 | return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U; |
| 147 | } |
| 148 | |
Marek Olšák | ac35ded | 2014-02-23 18:46:43 +0100 | [diff] [blame] | 149 | static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format) |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 150 | { |
Marek Olšák | ac35ded | 2014-02-23 18:46:43 +0100 | [diff] [blame] | 151 | return r600_translate_colorformat(chip, format) != ~0U && |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 152 | r600_translate_colorswap(format) != ~0U; |
| 153 | } |
| 154 | |
| 155 | static bool r600_is_zs_format_supported(enum pipe_format format) |
| 156 | { |
| 157 | return r600_translate_dbformat(format) != ~0U; |
| 158 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 159 | |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 160 | boolean r600_is_format_supported(struct pipe_screen *screen, |
| 161 | enum pipe_format format, |
| 162 | enum pipe_texture_target target, |
| 163 | unsigned sample_count, |
| 164 | unsigned usage) |
| 165 | { |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 166 | struct r600_screen *rscreen = (struct r600_screen*)screen; |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 167 | unsigned retval = 0; |
| 168 | |
| 169 | if (target >= PIPE_MAX_TEXTURE_TYPES) { |
| 170 | R600_ERR("r600: unsupported texture type %d\n", target); |
| 171 | return FALSE; |
| 172 | } |
| 173 | |
| 174 | if (!util_format_is_supported(format, usage)) |
| 175 | return FALSE; |
| 176 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 177 | if (sample_count > 1) { |
Marek Olšák | 96ed6c9 | 2012-10-12 18:46:32 +0200 | [diff] [blame] | 178 | if (!rscreen->has_msaa) |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 179 | return FALSE; |
Marek Olšák | c2e9dd0 | 2012-08-26 23:03:51 +0200 | [diff] [blame] | 180 | |
| 181 | /* R11G11B10 is broken on R6xx. */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 182 | if (rscreen->b.chip_class == R600 && |
Marek Olšák | c2e9dd0 | 2012-08-26 23:03:51 +0200 | [diff] [blame] | 183 | format == PIPE_FORMAT_R11G11B10_FLOAT) |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 184 | return FALSE; |
| 185 | |
Marek Olšák | df5e2c0 | 2012-09-08 15:50:30 +0200 | [diff] [blame] | 186 | /* MSAA integer colorbuffers hang. */ |
Marek Olšák | fc887d6 | 2012-09-13 00:45:05 +0200 | [diff] [blame] | 187 | if (util_format_is_pure_integer(format) && |
| 188 | !util_format_is_depth_or_stencil(format)) |
Marek Olšák | df5e2c0 | 2012-09-08 15:50:30 +0200 | [diff] [blame] | 189 | return FALSE; |
| 190 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 191 | switch (sample_count) { |
| 192 | case 2: |
| 193 | case 4: |
| 194 | case 8: |
| 195 | break; |
| 196 | default: |
| 197 | return FALSE; |
| 198 | } |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 199 | } |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 200 | |
Marek Olšák | 6a25087 | 2013-10-31 15:32:30 +0100 | [diff] [blame] | 201 | if (usage & PIPE_BIND_SAMPLER_VIEW) { |
| 202 | if (target == PIPE_BUFFER) { |
| 203 | if (r600_is_vertex_format_supported(format)) |
| 204 | retval |= PIPE_BIND_SAMPLER_VIEW; |
| 205 | } else { |
| 206 | if (r600_is_sampler_format_supported(screen, format)) |
| 207 | retval |= PIPE_BIND_SAMPLER_VIEW; |
| 208 | } |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | if ((usage & (PIPE_BIND_RENDER_TARGET | |
| 212 | PIPE_BIND_DISPLAY_TARGET | |
| 213 | PIPE_BIND_SCANOUT | |
Marek Olšák | 770719e | 2014-08-23 11:18:43 +0200 | [diff] [blame] | 214 | PIPE_BIND_SHARED | |
| 215 | PIPE_BIND_BLENDABLE)) && |
Marek Olšák | ac35ded | 2014-02-23 18:46:43 +0100 | [diff] [blame] | 216 | r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) { |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 217 | retval |= usage & |
| 218 | (PIPE_BIND_RENDER_TARGET | |
| 219 | PIPE_BIND_DISPLAY_TARGET | |
| 220 | PIPE_BIND_SCANOUT | |
| 221 | PIPE_BIND_SHARED); |
Marek Olšák | 770719e | 2014-08-23 11:18:43 +0200 | [diff] [blame] | 222 | if (!util_format_is_pure_integer(format) && |
| 223 | !util_format_is_depth_or_stencil(format)) |
| 224 | retval |= usage & PIPE_BIND_BLENDABLE; |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | if ((usage & PIPE_BIND_DEPTH_STENCIL) && |
| 228 | r600_is_zs_format_supported(format)) { |
| 229 | retval |= PIPE_BIND_DEPTH_STENCIL; |
| 230 | } |
| 231 | |
| 232 | if ((usage & PIPE_BIND_VERTEX_BUFFER) && |
| 233 | r600_is_vertex_format_supported(format)) { |
| 234 | retval |= PIPE_BIND_VERTEX_BUFFER; |
| 235 | } |
| 236 | |
| 237 | if (usage & PIPE_BIND_TRANSFER_READ) |
| 238 | retval |= PIPE_BIND_TRANSFER_READ; |
| 239 | if (usage & PIPE_BIND_TRANSFER_WRITE) |
| 240 | retval |= PIPE_BIND_TRANSFER_WRITE; |
| 241 | |
| 242 | return retval == usage; |
| 243 | } |
| 244 | |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 245 | static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a) |
Jerome Glisse | 0b841b0 | 2010-12-03 12:20:40 -0500 | [diff] [blame] | 246 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 247 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 248 | struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a; |
| 249 | float offset_units = state->offset_units; |
| 250 | float offset_scale = state->offset_scale; |
Jerome Glisse | 0b841b0 | 2010-12-03 12:20:40 -0500 | [diff] [blame] | 251 | |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 252 | switch (state->zs_format) { |
| 253 | case PIPE_FORMAT_Z24X8_UNORM: |
| 254 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: |
| 255 | offset_units *= 2.0f; |
| 256 | break; |
| 257 | case PIPE_FORMAT_Z16_UNORM: |
| 258 | offset_units *= 4.0f; |
| 259 | break; |
| 260 | default:; |
Jerome Glisse | 0b841b0 | 2010-12-03 12:20:40 -0500 | [diff] [blame] | 261 | } |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 262 | |
| 263 | r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 264 | radeon_emit(cs, fui(offset_scale)); |
| 265 | radeon_emit(cs, fui(offset_units)); |
| 266 | radeon_emit(cs, fui(offset_scale)); |
| 267 | radeon_emit(cs, fui(offset_units)); |
Jerome Glisse | 0b841b0 | 2010-12-03 12:20:40 -0500 | [diff] [blame] | 268 | } |
| 269 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 270 | static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i) |
| 271 | { |
| 272 | int j = state->independent_blend_enable ? i : 0; |
| 273 | |
| 274 | unsigned eqRGB = state->rt[j].rgb_func; |
| 275 | unsigned srcRGB = state->rt[j].rgb_src_factor; |
| 276 | unsigned dstRGB = state->rt[j].rgb_dst_factor; |
| 277 | |
| 278 | unsigned eqA = state->rt[j].alpha_func; |
| 279 | unsigned srcA = state->rt[j].alpha_src_factor; |
| 280 | unsigned dstA = state->rt[j].alpha_dst_factor; |
| 281 | uint32_t bc = 0; |
| 282 | |
| 283 | if (!state->rt[j].blend_enable) |
| 284 | return 0; |
| 285 | |
| 286 | bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); |
| 287 | bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); |
| 288 | bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); |
| 289 | |
| 290 | if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { |
| 291 | bc |= S_028804_SEPARATE_ALPHA_BLEND(1); |
| 292 | bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); |
| 293 | bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); |
| 294 | bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); |
| 295 | } |
| 296 | return bc; |
| 297 | } |
| 298 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 299 | static void *r600_create_blend_state_mode(struct pipe_context *ctx, |
| 300 | const struct pipe_blend_state *state, |
| 301 | int mode) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 302 | { |
Marek Olšák | e4340c1 | 2012-01-29 23:25:42 +0100 | [diff] [blame] | 303 | struct r600_context *rctx = (struct r600_context *)ctx; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 304 | uint32_t color_control = 0, target_mask = 0; |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 305 | struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 306 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 307 | if (!blend) { |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 308 | return NULL; |
| 309 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 310 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 311 | r600_init_command_buffer(&blend->buffer, 20); |
| 312 | r600_init_command_buffer(&blend->buffer_no_blend, 20); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 313 | |
Alex Deucher | 3e30148 | 2011-03-14 17:53:00 -0400 | [diff] [blame] | 314 | /* R600 does not support per-MRT blends */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 315 | if (rctx->b.family > CHIP_R600) |
Alex Deucher | 3e30148 | 2011-03-14 17:53:00 -0400 | [diff] [blame] | 316 | color_control |= S_028808_PER_MRT_BLEND(1); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 317 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 318 | if (state->logicop_enable) { |
| 319 | color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); |
| 320 | } else { |
| 321 | color_control |= (0xcc << 16); |
| 322 | } |
| 323 | /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ |
| 324 | if (state->independent_blend_enable) { |
| 325 | for (int i = 0; i < 8; i++) { |
| 326 | if (state->rt[i].blend_enable) { |
| 327 | color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); |
| 328 | } |
| 329 | target_mask |= (state->rt[i].colormask << (4 * i)); |
| 330 | } |
| 331 | } else { |
| 332 | for (int i = 0; i < 8; i++) { |
| 333 | if (state->rt[0].blend_enable) { |
| 334 | color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); |
| 335 | } |
| 336 | target_mask |= (state->rt[0].colormask << (4 * i)); |
| 337 | } |
| 338 | } |
Marek Olšák | 43e3f19 | 2012-07-07 17:11:32 +0200 | [diff] [blame] | 339 | |
| 340 | if (target_mask) |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 341 | color_control |= S_028808_SPECIAL_OP(mode); |
Marek Olšák | 43e3f19 | 2012-07-07 17:11:32 +0200 | [diff] [blame] | 342 | else |
| 343 | color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE); |
| 344 | |
Dave Airlie | d1cc87c | 2012-03-24 13:37:16 +0000 | [diff] [blame] | 345 | /* only MRT0 has dual src blend */ |
| 346 | blend->dual_src_blend = util_blend_state_is_dual(state, 0); |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 347 | blend->cb_target_mask = target_mask; |
| 348 | blend->cb_color_control = color_control; |
| 349 | blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE; |
| 350 | blend->alpha_to_one = state->alpha_to_one; |
Jerome Glisse | 7ffd4e9 | 2010-11-17 17:20:59 -0500 | [diff] [blame] | 351 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 352 | r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK, |
| 353 | S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | |
| 354 | S_028D44_ALPHA_TO_MASK_OFFSET0(2) | |
| 355 | S_028D44_ALPHA_TO_MASK_OFFSET1(2) | |
| 356 | S_028D44_ALPHA_TO_MASK_OFFSET2(2) | |
| 357 | S_028D44_ALPHA_TO_MASK_OFFSET3(2)); |
Julian Adams | 3f8455d | 2011-04-06 21:04:08 +0200 | [diff] [blame] | 358 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 359 | /* Copy over the registers set so far into buffer_no_blend. */ |
| 360 | memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4); |
| 361 | blend->buffer_no_blend.num_dw = blend->buffer.num_dw; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 362 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 363 | /* Only add blend registers if blending is enabled. */ |
| 364 | if (!G_028808_TARGET_BLEND_ENABLE(color_control)) { |
| 365 | return blend; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 366 | } |
Marek Olšák | 26cb887 | 2012-08-04 01:50:10 +0200 | [diff] [blame] | 367 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 368 | /* The first R600 does not support per-MRT blends */ |
| 369 | r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL, |
| 370 | r600_get_blend_control(state, 0)); |
Marek Olšák | 6517225 | 2012-07-22 06:36:58 +0200 | [diff] [blame] | 371 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 372 | if (rctx->b.family > CHIP_R600) { |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 373 | r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8); |
| 374 | for (int i = 0; i < 8; i++) { |
| 375 | r600_store_value(&blend->buffer, r600_get_blend_control(state, i)); |
| 376 | } |
| 377 | } |
| 378 | return blend; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 379 | } |
| 380 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 381 | static void *r600_create_blend_state(struct pipe_context *ctx, |
| 382 | const struct pipe_blend_state *state) |
| 383 | { |
| 384 | return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL); |
| 385 | } |
| 386 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 387 | static void *r600_create_dsa_state(struct pipe_context *ctx, |
| 388 | const struct pipe_depth_stencil_alpha_state *state) |
| 389 | { |
Marek Olšák | 3d061ca | 2012-01-28 06:03:53 +0100 | [diff] [blame] | 390 | unsigned db_depth_control, alpha_test_control, alpha_ref; |
Marek Olšák | ef72361 | 2012-10-05 20:11:15 +0200 | [diff] [blame] | 391 | struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 392 | |
Henri Verbeet | f60235e | 2011-05-05 20:54:36 +0200 | [diff] [blame] | 393 | if (dsa == NULL) { |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 394 | return NULL; |
| 395 | } |
| 396 | |
Marek Olšák | ef72361 | 2012-10-05 20:11:15 +0200 | [diff] [blame] | 397 | r600_init_command_buffer(&dsa->buffer, 3); |
| 398 | |
Marek Olšák | a236194 | 2012-01-28 05:50:00 +0100 | [diff] [blame] | 399 | dsa->valuemask[0] = state->stencil[0].valuemask; |
| 400 | dsa->valuemask[1] = state->stencil[1].valuemask; |
| 401 | dsa->writemask[0] = state->stencil[0].writemask; |
| 402 | dsa->writemask[1] = state->stencil[1].writemask; |
Jerome Glisse | 6bc7605 | 2013-02-20 16:20:17 -0500 | [diff] [blame] | 403 | dsa->zwritemask = state->depth.writemask; |
Marek Olšák | a236194 | 2012-01-28 05:50:00 +0100 | [diff] [blame] | 404 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 405 | db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | |
| 406 | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | |
| 407 | S_028800_ZFUNC(state->depth.func); |
| 408 | |
| 409 | /* stencil */ |
| 410 | if (state->stencil[0].enabled) { |
| 411 | db_depth_control |= S_028800_STENCIL_ENABLE(1); |
Marek Olšák | d214275 | 2012-02-14 15:14:58 +0100 | [diff] [blame] | 412 | db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 413 | db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); |
| 414 | db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); |
| 415 | db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); |
| 416 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 417 | if (state->stencil[1].enabled) { |
| 418 | db_depth_control |= S_028800_BACKFACE_ENABLE(1); |
Marek Olšák | d214275 | 2012-02-14 15:14:58 +0100 | [diff] [blame] | 419 | db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 420 | db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); |
| 421 | db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); |
| 422 | db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 423 | } |
| 424 | } |
| 425 | |
| 426 | /* alpha */ |
| 427 | alpha_test_control = 0; |
| 428 | alpha_ref = 0; |
| 429 | if (state->alpha.enabled) { |
| 430 | alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); |
| 431 | alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); |
| 432 | alpha_ref = fui(state->alpha.ref_value); |
| 433 | } |
Dave Airlie | 4a26454 | 2012-04-22 20:51:43 +0100 | [diff] [blame] | 434 | dsa->sx_alpha_test_control = alpha_test_control & 0xff; |
Henri Verbeet | f60235e | 2011-05-05 20:54:36 +0200 | [diff] [blame] | 435 | dsa->alpha_ref = alpha_ref; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 436 | |
Marek Olšák | ef72361 | 2012-10-05 20:11:15 +0200 | [diff] [blame] | 437 | r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control); |
| 438 | return dsa; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 439 | } |
| 440 | |
| 441 | static void *r600_create_rs_state(struct pipe_context *ctx, |
Marek Olšák | 543b233 | 2011-11-08 21:58:27 +0100 | [diff] [blame] | 442 | const struct pipe_rasterizer_state *state) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 443 | { |
Marek Olšák | e4340c1 | 2012-01-29 23:25:42 +0100 | [diff] [blame] | 444 | struct r600_context *rctx = (struct r600_context *)ctx; |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 445 | unsigned tmp, sc_mode_cntl, spi_interp; |
Marek Olšák | f183cc9 | 2012-01-27 21:20:27 +0100 | [diff] [blame] | 446 | float psize_min, psize_max; |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 447 | struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 448 | |
| 449 | if (rs == NULL) { |
| 450 | return NULL; |
| 451 | } |
| 452 | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 453 | r600_init_command_buffer(&rs->buffer, 30); |
Marek Olšák | a652cc4 | 2012-01-29 05:48:28 +0100 | [diff] [blame] | 454 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 455 | rs->flatshade = state->flatshade; |
| 456 | rs->sprite_coord_enable = state->sprite_coord_enable; |
Vadim Girlin | 725a820 | 2012-01-06 08:13:18 +0400 | [diff] [blame] | 457 | rs->two_side = state->light_twoside; |
Vadim Girlin | 91d4729 | 2012-01-15 09:29:50 -0500 | [diff] [blame] | 458 | rs->clip_plane_enable = state->clip_plane_enable; |
Marek Olšák | 2000086 | 2012-01-29 05:22:00 +0100 | [diff] [blame] | 459 | rs->pa_sc_line_stipple = state->line_stipple_enable ? |
| 460 | S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | |
| 461 | S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; |
Marek Olšák | a494301 | 2012-01-29 07:16:10 +0100 | [diff] [blame] | 462 | rs->pa_cl_clip_cntl = |
| 463 | S_028810_PS_UCP_MODE(3) | |
| 464 | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | |
| 465 | S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | |
| 466 | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); |
Marek Olšák | 3a3b1bf | 2014-04-20 18:17:51 +0200 | [diff] [blame] | 467 | if (rctx->b.chip_class == R700) { |
| 468 | rs->pa_cl_clip_cntl |= |
| 469 | S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard); |
| 470 | } |
Marek Olšák | 26cb887 | 2012-08-04 01:50:10 +0200 | [diff] [blame] | 471 | rs->multisample_enable = state->multisample; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 472 | |
Jerome Glisse | 58c2439 | 2010-09-24 21:34:56 -0400 | [diff] [blame] | 473 | /* offset */ |
| 474 | rs->offset_units = state->offset_units; |
| 475 | rs->offset_scale = state->offset_scale * 12.0f; |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 476 | rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri; |
Jerome Glisse | 58c2439 | 2010-09-24 21:34:56 -0400 | [diff] [blame] | 477 | |
Marek Olšák | c7eaf274 | 2012-03-08 11:15:32 +0100 | [diff] [blame] | 478 | if (state->point_size_per_vertex) { |
Marek Olšák | e3032a0 | 2012-01-28 15:05:06 +0100 | [diff] [blame] | 479 | psize_min = util_get_min_point_size(state); |
| 480 | psize_max = 8192; |
| 481 | } else { |
| 482 | /* Force the point size to be as if the vertex output was disabled. */ |
| 483 | psize_min = state->point_size; |
| 484 | psize_max = state->point_size; |
| 485 | } |
Keith Whitwell | c28f764 | 2010-10-14 16:42:39 +0100 | [diff] [blame] | 486 | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 487 | sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) | |
| 488 | S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | |
| 489 | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 490 | if (rctx->b.chip_class >= R700) { |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 491 | sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) | |
| 492 | S_028A4C_R700_ZMM_LINE_OFFSET(1) | |
| 493 | S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor); |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 494 | } else { |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 495 | sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1); |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 496 | rs->scissor_enable = state->scissor; |
| 497 | } |
Jerome Glisse | 7ffd4e9 | 2010-11-17 17:20:59 -0500 | [diff] [blame] | 498 | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 499 | spi_interp = S_0286D4_FLAT_SHADE_ENA(1); |
| 500 | if (state->sprite_coord_enable) { |
| 501 | spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) | |
| 502 | S_0286D4_PNT_SPRITE_OVRD_X(2) | |
| 503 | S_0286D4_PNT_SPRITE_OVRD_Y(3) | |
| 504 | S_0286D4_PNT_SPRITE_OVRD_Z(0) | |
| 505 | S_0286D4_PNT_SPRITE_OVRD_W(1); |
| 506 | if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { |
| 507 | spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1); |
| 508 | } |
| 509 | } |
Keith Whitwell | c3974dc | 2010-10-17 11:45:49 -0700 | [diff] [blame] | 510 | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 511 | r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3); |
| 512 | /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */ |
| 513 | tmp = r600_pack_float_12p4(state->point_size/2); |
| 514 | r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */ |
| 515 | S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); |
| 516 | r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */ |
| 517 | S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | |
| 518 | S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); |
| 519 | r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */ |
| 520 | S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2))); |
| 521 | |
| 522 | r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp); |
| 523 | r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl); |
| 524 | r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL, |
José Fonseca | 2737abb | 2013-04-23 19:40:05 +0100 | [diff] [blame] | 525 | S_028C08_PIX_CENTER_HALF(state->half_pixel_center) | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 526 | S_028C08_QUANT_MODE(V_028C08_X_1_256TH)); |
| 527 | r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); |
Marek Olšák | ecc8a37 | 2014-04-20 15:19:43 +0200 | [diff] [blame] | 528 | |
| 529 | rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) | |
| 530 | S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | |
| 531 | S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | |
| 532 | S_028814_FACE(!state->front_ccw) | |
| 533 | S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | |
| 534 | S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | |
| 535 | S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | |
| 536 | S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL || |
| 537 | state->fill_back != PIPE_POLYGON_MODE_FILL) | |
| 538 | S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | |
| 539 | S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)); |
| 540 | if (rctx->b.chip_class == R700) { |
| 541 | r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl); |
| 542 | } |
Marek Olšák | 3a3b1bf | 2014-04-20 18:17:51 +0200 | [diff] [blame] | 543 | if (rctx->b.chip_class == R600) { |
| 544 | r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, |
| 545 | S_028350_MULTIPASS(state->rasterizer_discard)); |
| 546 | } |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 547 | return rs; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 548 | } |
| 549 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 550 | static void *r600_create_sampler_state(struct pipe_context *ctx, |
| 551 | const struct pipe_sampler_state *state) |
| 552 | { |
Marek Olšák | badf033 | 2011-06-19 23:41:02 +0200 | [diff] [blame] | 553 | struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); |
Jerome Glisse | b9e8ea6 | 2011-05-09 12:09:51 -0400 | [diff] [blame] | 554 | unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 555 | |
Marek Olšák | badf033 | 2011-06-19 23:41:02 +0200 | [diff] [blame] | 556 | if (ss == NULL) { |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 557 | return NULL; |
| 558 | } |
| 559 | |
Marek Olšák | badf033 | 2011-06-19 23:41:02 +0200 | [diff] [blame] | 560 | ss->seamless_cube_map = state->seamless_cube_map; |
Marek Olšák | 023dae7 | 2012-10-14 04:12:32 +0200 | [diff] [blame] | 561 | ss->border_color_use = sampler_state_needs_border_color(state); |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 562 | |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 563 | /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */ |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 564 | ss->tex_sampler_words[0] = |
| 565 | S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | |
| 566 | S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | |
| 567 | S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | |
| 568 | S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | |
| 569 | S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | |
| 570 | S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | |
| 571 | S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | |
| 572 | S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | |
| 573 | S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 574 | /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */ |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 575 | ss->tex_sampler_words[1] = |
| 576 | S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | |
| 577 | S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | |
| 578 | S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 579 | /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */ |
| 580 | ss->tex_sampler_words[2] = S_03C008_TYPE(1); |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 581 | |
| 582 | if (ss->border_color_use) { |
| 583 | memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color)); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 584 | } |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 585 | return ss; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 586 | } |
| 587 | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 588 | static struct pipe_sampler_view * |
| 589 | texture_buffer_sampler_view(struct r600_pipe_sampler_view *view, |
| 590 | unsigned width0, unsigned height0) |
| 591 | |
| 592 | { |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 593 | struct r600_texture *tmp = (struct r600_texture*)view->base.texture; |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 594 | int stride = util_format_get_blocksize(view->base.format); |
| 595 | unsigned format, num_format, format_comp, endian; |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 596 | uint64_t offset = view->base.u.buf.first_element * stride; |
Fredrik Höglund | fb69dbb | 2013-03-22 17:14:43 +0100 | [diff] [blame] | 597 | unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride; |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 598 | |
| 599 | r600_vertex_data_type(view->base.format, |
| 600 | &format, &num_format, &format_comp, |
| 601 | &endian); |
| 602 | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 603 | view->tex_resource = &tmp->resource; |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 604 | view->skip_mip_address_reloc = true; |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 605 | |
| 606 | view->tex_resource_words[0] = offset; |
Fredrik Höglund | fb69dbb | 2013-03-22 17:14:43 +0100 | [diff] [blame] | 607 | view->tex_resource_words[1] = size - 1; |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 608 | view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 609 | S_038008_STRIDE(stride) | |
| 610 | S_038008_DATA_FORMAT(format) | |
| 611 | S_038008_NUM_FORMAT_ALL(num_format) | |
| 612 | S_038008_FORMAT_COMP_ALL(format_comp) | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 613 | S_038008_ENDIAN_SWAP(endian); |
| 614 | view->tex_resource_words[3] = 0; |
| 615 | /* |
| 616 | * in theory dword 4 is for number of elements, for use with resinfo, |
| 617 | * but it seems to utterly fail to work, the amd gpu shader analyser |
| 618 | * uses a const buffer to store the element sizes for buffer txq |
| 619 | */ |
| 620 | view->tex_resource_words[4] = 0; |
| 621 | view->tex_resource_words[5] = 0; |
| 622 | view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER); |
| 623 | return &view->base; |
| 624 | } |
| 625 | |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 626 | struct pipe_sampler_view * |
| 627 | r600_create_sampler_view_custom(struct pipe_context *ctx, |
| 628 | struct pipe_resource *texture, |
| 629 | const struct pipe_sampler_view *state, |
| 630 | unsigned width_first_level, unsigned height_first_level) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 631 | { |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 632 | struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); |
Marek Olšák | 951ac46 | 2012-08-14 02:29:17 +0200 | [diff] [blame] | 633 | struct r600_texture *tmp = (struct r600_texture*)texture; |
Cédric Cano | 843dfe3 | 2011-04-19 13:02:14 -0400 | [diff] [blame] | 634 | unsigned format, endian; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 635 | uint32_t word4 = 0, yuv_format = 0, pitch = 0; |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 636 | unsigned char swizzle[4], array_mode = 0; |
Marek Olšák | 677a440 | 2011-06-15 02:24:03 +0200 | [diff] [blame] | 637 | unsigned width, height, depth, offset_level, last_level; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 638 | |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 639 | if (view == NULL) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 640 | return NULL; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 641 | |
| 642 | /* initialize base object */ |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 643 | view->base = *state; |
| 644 | view->base.texture = NULL; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 645 | pipe_reference(NULL, &texture->reference); |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 646 | view->base.texture = texture; |
| 647 | view->base.reference.count = 1; |
| 648 | view->base.context = ctx; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 649 | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 650 | if (texture->target == PIPE_BUFFER) |
| 651 | return texture_buffer_sampler_view(view, texture->width0, 1); |
| 652 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 653 | swizzle[0] = state->swizzle_r; |
| 654 | swizzle[1] = state->swizzle_g; |
| 655 | swizzle[2] = state->swizzle_b; |
| 656 | swizzle[3] = state->swizzle_a; |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 657 | |
Dave Airlie | 929be6e | 2011-03-01 14:55:35 +1000 | [diff] [blame] | 658 | format = r600_translate_texformat(ctx->screen, state->format, |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 659 | swizzle, |
| 660 | &word4, &yuv_format); |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 661 | assert(format != ~0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 662 | if (format == ~0) { |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 663 | FREE(view); |
| 664 | return NULL; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 665 | } |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 666 | |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 667 | if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) { |
Marek Olšák | 611dd52 | 2012-07-18 00:05:14 +0200 | [diff] [blame] | 668 | if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) { |
Marek Olšák | da98bb6 | 2012-06-25 12:45:32 +0200 | [diff] [blame] | 669 | FREE(view); |
| 670 | return NULL; |
| 671 | } |
Marek Olšák | 611dd52 | 2012-07-18 00:05:14 +0200 | [diff] [blame] | 672 | tmp = tmp->flushed_depth_texture; |
Henri Verbeet | d171ae0 | 2011-02-01 01:17:02 +0100 | [diff] [blame] | 673 | } |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 674 | |
Cédric Cano | 843dfe3 | 2011-04-19 13:02:14 -0400 | [diff] [blame] | 675 | endian = r600_colorformat_endian_swap(format); |
Dave Airlie | 231bf88 | 2011-02-17 10:25:57 +1000 | [diff] [blame] | 676 | |
Marek Olšák | 677a440 | 2011-06-15 02:24:03 +0200 | [diff] [blame] | 677 | offset_level = state->u.tex.first_level; |
| 678 | last_level = state->u.tex.last_level - offset_level; |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 679 | width = width_first_level; |
| 680 | height = height_first_level; |
Marek Olšák | 26c872c | 2013-01-25 18:27:05 +0100 | [diff] [blame] | 681 | depth = u_minify(texture->depth0, offset_level); |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 682 | pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); |
Marek Olšák | 677a440 | 2011-06-15 02:24:03 +0200 | [diff] [blame] | 683 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 684 | if (texture->target == PIPE_TEXTURE_1D_ARRAY) { |
| 685 | height = 1; |
| 686 | depth = texture->array_size; |
| 687 | } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { |
| 688 | depth = texture->array_size; |
Dave Airlie | eb44c36d | 2012-11-03 20:53:33 +1000 | [diff] [blame] | 689 | } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY) |
| 690 | depth = texture->array_size / 6; |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 691 | switch (tmp->surface.level[offset_level].mode) { |
| 692 | case RADEON_SURF_MODE_LINEAR_ALIGNED: |
| 693 | array_mode = V_038000_ARRAY_LINEAR_ALIGNED; |
| 694 | break; |
| 695 | case RADEON_SURF_MODE_1D: |
| 696 | array_mode = V_038000_ARRAY_1D_TILED_THIN1; |
| 697 | break; |
| 698 | case RADEON_SURF_MODE_2D: |
| 699 | array_mode = V_038000_ARRAY_2D_TILED_THIN1; |
| 700 | break; |
| 701 | case RADEON_SURF_MODE_LINEAR: |
| 702 | default: |
| 703 | array_mode = V_038000_ARRAY_LINEAR_GENERAL; |
| 704 | break; |
| 705 | } |
| 706 | |
| 707 | view->tex_resource = &tmp->resource; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 708 | view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 709 | S_038000_TILE_MODE(array_mode) | |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 710 | S_038000_TILE_TYPE(tmp->non_disp_tiling) | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 711 | S_038000_PITCH((pitch / 8) - 1) | |
| 712 | S_038000_TEX_WIDTH(width - 1)); |
| 713 | view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) | |
| 714 | S_038004_TEX_DEPTH(depth - 1) | |
| 715 | S_038004_DATA_FORMAT(format)); |
| 716 | view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8; |
| 717 | if (offset_level >= tmp->surface.last_level) { |
| 718 | view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8; |
| 719 | } else { |
| 720 | view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8; |
| 721 | } |
| 722 | view->tex_resource_words[4] = (word4 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 723 | S_038010_REQUEST_SIZE(1) | |
| 724 | S_038010_ENDIAN_SWAP(endian) | |
| 725 | S_038010_BASE_LEVEL(0)); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 726 | view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 727 | S_038014_LAST_ARRAY(state->u.tex.last_layer)); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 728 | if (texture->nr_samples > 1) { |
| 729 | /* LAST_LEVEL holds log2(nr_samples) for multisample textures */ |
| 730 | view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples)); |
| 731 | } else { |
| 732 | view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level); |
| 733 | } |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 734 | view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | |
| 735 | S_038018_MAX_ANISO(4 /* max 16 samples */)); |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 736 | return &view->base; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 737 | } |
| 738 | |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 739 | static struct pipe_sampler_view * |
| 740 | r600_create_sampler_view(struct pipe_context *ctx, |
| 741 | struct pipe_resource *tex, |
| 742 | const struct pipe_sampler_view *state) |
| 743 | { |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 744 | return r600_create_sampler_view_custom(ctx, tex, state, |
Marek Olšák | 26c872c | 2013-01-25 18:27:05 +0100 | [diff] [blame] | 745 | u_minify(tex->width0, state->u.tex.first_level), |
| 746 | u_minify(tex->height0, state->u.tex.first_level)); |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 747 | } |
| 748 | |
Marek Olšák | 2b8d39b | 2012-09-10 20:03:09 +0200 | [diff] [blame] | 749 | static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 750 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 751 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | 2b8d39b | 2012-09-10 20:03:09 +0200 | [diff] [blame] | 752 | struct pipe_clip_state *state = &rctx->clip_state.state; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 753 | |
Marek Olšák | 2b8d39b | 2012-09-10 20:03:09 +0200 | [diff] [blame] | 754 | r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 755 | radeon_emit_array(cs, (unsigned*)state, 6*4); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 756 | } |
| 757 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 758 | static void r600_set_polygon_stipple(struct pipe_context *ctx, |
| 759 | const struct pipe_poly_stipple *state) |
| 760 | { |
| 761 | } |
| 762 | |
Marek Olšák | 18a1891 | 2012-10-05 05:37:38 +0200 | [diff] [blame] | 763 | static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 764 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 765 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 766 | struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom; |
| 767 | struct pipe_scissor_state *state = &rstate->scissor; |
| 768 | unsigned offset = rstate->idx * 4 * 2; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 769 | |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 770 | if (rctx->b.chip_class != R600 || rctx->scissor[0].enable) { |
| 771 | r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 772 | radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | |
Marek Olšák | 18a1891 | 2012-10-05 05:37:38 +0200 | [diff] [blame] | 773 | S_028240_WINDOW_OFFSET_DISABLE(1)); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 774 | radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy)); |
Marek Olšák | 18a1891 | 2012-10-05 05:37:38 +0200 | [diff] [blame] | 775 | } else { |
| 776 | r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 777 | radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) | |
Marek Olšák | 18a1891 | 2012-10-05 05:37:38 +0200 | [diff] [blame] | 778 | S_028240_WINDOW_OFFSET_DISABLE(1)); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 779 | radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); |
Marek Olšák | 18a1891 | 2012-10-05 05:37:38 +0200 | [diff] [blame] | 780 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 781 | } |
| 782 | |
Zack Rusin | eaabb4e | 2013-05-24 16:08:39 -0400 | [diff] [blame] | 783 | static void r600_set_scissor_states(struct pipe_context *ctx, |
| 784 | unsigned start_slot, |
| 785 | unsigned num_scissors, |
| 786 | const struct pipe_scissor_state *state) |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 787 | { |
| 788 | struct r600_context *rctx = (struct r600_context *)ctx; |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 789 | int i; |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 790 | |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 791 | for (i = start_slot ; i < start_slot + num_scissors; i++) { |
| 792 | rctx->scissor[i].scissor = state[i - start_slot]; |
| 793 | } |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 794 | |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 795 | if (rctx->b.chip_class == R600 && !rctx->scissor[0].enable) |
Marek Olšák | fc887d6 | 2012-09-13 00:45:05 +0200 | [diff] [blame] | 796 | return; |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 797 | |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 798 | for (i = start_slot ; i < start_slot + num_scissors; i++) { |
| 799 | rctx->scissor[i].atom.dirty = true; |
| 800 | } |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 801 | } |
| 802 | |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 803 | static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen, |
| 804 | unsigned size, unsigned alignment) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 805 | { |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 806 | struct pipe_resource buffer; |
| 807 | |
| 808 | memset(&buffer, 0, sizeof buffer); |
| 809 | buffer.target = PIPE_BUFFER; |
| 810 | buffer.format = PIPE_FORMAT_R8_UNORM; |
| 811 | buffer.bind = PIPE_BIND_CUSTOM; |
Marek Olšák | c321144 | 2014-02-03 03:42:17 +0100 | [diff] [blame] | 812 | buffer.usage = PIPE_USAGE_DEFAULT; |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 813 | buffer.flags = 0; |
| 814 | buffer.width0 = size; |
| 815 | buffer.height0 = 1; |
| 816 | buffer.depth0 = 1; |
| 817 | buffer.array_size = 1; |
| 818 | |
| 819 | return (struct r600_resource*) |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 820 | r600_buffer_create(&rscreen->b.b, &buffer, alignment); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 821 | } |
| 822 | |
| 823 | static void r600_init_color_surface(struct r600_context *rctx, |
| 824 | struct r600_surface *surf, |
| 825 | bool force_cmask_fmask) |
| 826 | { |
| 827 | struct r600_screen *rscreen = rctx->screen; |
Marek Olšák | 951ac46 | 2012-08-14 02:29:17 +0200 | [diff] [blame] | 828 | struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 829 | unsigned level = surf->base.u.tex.level; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 830 | unsigned pitch, slice; |
| 831 | unsigned color_info; |
Dave Airlie | 7863611 | 2014-01-28 23:15:29 +0000 | [diff] [blame] | 832 | unsigned color_view; |
Cédric Cano | 843dfe3 | 2011-04-19 13:02:14 -0400 | [diff] [blame] | 833 | unsigned format, swap, ntype, endian; |
Roland Scheidegger | 4c70014 | 2010-12-02 04:33:43 +0100 | [diff] [blame] | 834 | unsigned offset; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 835 | const struct util_format_description *desc; |
Dave Airlie | 0d851f6 | 2011-02-10 14:07:06 +1000 | [diff] [blame] | 836 | int i; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 837 | bool blend_bypass = 0, blend_clamp = 1; |
Dave Airlie | 3e9bc43 | 2011-02-04 09:07:08 +1000 | [diff] [blame] | 838 | |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 839 | if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 840 | r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL); |
Dave Airlie | 3e9bc43 | 2011-02-04 09:07:08 +1000 | [diff] [blame] | 841 | rtex = rtex->flushed_depth_texture; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 842 | assert(rtex); |
Dave Airlie | 3e9bc43 | 2011-02-04 09:07:08 +1000 | [diff] [blame] | 843 | } |
| 844 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 845 | offset = rtex->surface.level[level].offset; |
Dave Airlie | 7863611 | 2014-01-28 23:15:29 +0000 | [diff] [blame] | 846 | if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { |
| 847 | assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 848 | offset += rtex->surface.level[level].slice_size * |
Dave Airlie | 7863611 | 2014-01-28 23:15:29 +0000 | [diff] [blame] | 849 | surf->base.u.tex.first_layer; |
| 850 | color_view = 0; |
| 851 | } else |
| 852 | color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | |
| 853 | S_028080_SLICE_MAX(surf->base.u.tex.last_layer); |
| 854 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 855 | pitch = rtex->surface.level[level].nblk_x / 8 - 1; |
| 856 | slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; |
| 857 | if (slice) { |
| 858 | slice = slice - 1; |
| 859 | } |
| 860 | color_info = 0; |
| 861 | switch (rtex->surface.level[level].mode) { |
| 862 | case RADEON_SURF_MODE_LINEAR_ALIGNED: |
| 863 | color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); |
| 864 | break; |
| 865 | case RADEON_SURF_MODE_1D: |
| 866 | color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); |
| 867 | break; |
| 868 | case RADEON_SURF_MODE_2D: |
| 869 | color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); |
| 870 | break; |
| 871 | case RADEON_SURF_MODE_LINEAR: |
| 872 | default: |
| 873 | color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL); |
| 874 | break; |
| 875 | } |
| 876 | |
Dave Airlie | 780c183 | 2011-02-06 18:57:11 +1000 | [diff] [blame] | 877 | desc = util_format_description(surf->base.format); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 878 | |
Dave Airlie | 0d851f6 | 2011-02-10 14:07:06 +1000 | [diff] [blame] | 879 | for (i = 0; i < 4; i++) { |
| 880 | if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { |
| 881 | break; |
| 882 | } |
| 883 | } |
Dave Airlie | 8d3e505 | 2011-10-10 20:27:51 +0100 | [diff] [blame] | 884 | |
Dave Airlie | 66866d6 | 2011-04-19 20:42:48 +1000 | [diff] [blame] | 885 | ntype = V_0280A0_NUMBER_UNORM; |
| 886 | if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) |
| 887 | ntype = V_0280A0_NUMBER_SRGB; |
Dave Airlie | 8d3e505 | 2011-10-10 20:27:51 +0100 | [diff] [blame] | 888 | else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { |
| 889 | if (desc->channel[i].normalized) |
| 890 | ntype = V_0280A0_NUMBER_SNORM; |
| 891 | else if (desc->channel[i].pure_integer) |
| 892 | ntype = V_0280A0_NUMBER_SINT; |
| 893 | } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { |
| 894 | if (desc->channel[i].normalized) |
| 895 | ntype = V_0280A0_NUMBER_UNORM; |
| 896 | else if (desc->channel[i].pure_integer) |
| 897 | ntype = V_0280A0_NUMBER_UINT; |
| 898 | } |
Dave Airlie | 0d851f6 | 2011-02-10 14:07:06 +1000 | [diff] [blame] | 899 | |
Marek Olšák | ac35ded | 2014-02-23 18:46:43 +0100 | [diff] [blame] | 900 | format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format); |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 901 | assert(format != ~0); |
| 902 | |
Dave Airlie | 780c183 | 2011-02-06 18:57:11 +1000 | [diff] [blame] | 903 | swap = r600_translate_colorswap(surf->base.format); |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 904 | assert(swap != ~0); |
| 905 | |
| 906 | if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { |
Cédric Cano | 843dfe3 | 2011-04-19 13:02:14 -0400 | [diff] [blame] | 907 | endian = ENDIAN_NONE; |
| 908 | } else { |
| 909 | endian = r600_colorformat_endian_swap(format); |
| 910 | } |
Dave Airlie | 231bf88 | 2011-02-17 10:25:57 +1000 | [diff] [blame] | 911 | |
Dave Airlie | a33937d | 2012-01-29 19:38:28 +0000 | [diff] [blame] | 912 | /* set blend bypass according to docs if SINT/UINT or |
| 913 | 8/24 COLOR variants */ |
| 914 | if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || |
| 915 | format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || |
| 916 | format == V_0280A0_COLOR_X24_8_32_FLOAT) { |
| 917 | blend_clamp = 0; |
| 918 | blend_bypass = 1; |
| 919 | } |
| 920 | |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 921 | surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT; |
Dave Airlie | 4a26454 | 2012-04-22 20:51:43 +0100 | [diff] [blame] | 922 | |
Jerome Glisse | c0c979e | 2012-01-30 17:22:13 -0500 | [diff] [blame] | 923 | color_info |= S_0280A0_FORMAT(format) | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 924 | S_0280A0_COMP_SWAP(swap) | |
Dave Airlie | a33937d | 2012-01-29 19:38:28 +0000 | [diff] [blame] | 925 | S_0280A0_BLEND_BYPASS(blend_bypass) | |
| 926 | S_0280A0_BLEND_CLAMP(blend_clamp) | |
Cédric Cano | 843dfe3 | 2011-04-19 13:02:14 -0400 | [diff] [blame] | 927 | S_0280A0_NUMBER_TYPE(ntype) | |
| 928 | S_0280A0_ENDIAN(endian); |
Dave Airlie | 0d851f6 | 2011-02-10 14:07:06 +1000 | [diff] [blame] | 929 | |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 930 | /* EXPORT_NORM is an optimzation that can be enabled for better |
| 931 | * performance in certain cases |
| 932 | */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 933 | if (rctx->b.chip_class == R600) { |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 934 | /* EXPORT_NORM can be enabled if: |
| 935 | * - 11-bit or smaller UNORM/SNORM/SRGB |
| 936 | * - BLEND_CLAMP is enabled |
| 937 | * - BLEND_FLOAT32 is disabled |
| 938 | */ |
| 939 | if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && |
| 940 | (desc->channel[i].size < 12 && |
| 941 | desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && |
| 942 | ntype != V_0280A0_NUMBER_UINT && |
| 943 | ntype != V_0280A0_NUMBER_SINT) && |
| 944 | G_0280A0_BLEND_CLAMP(color_info) && |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 945 | !G_0280A0_BLEND_FLOAT32(color_info)) { |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 946 | color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 947 | surf->export_16bpc = true; |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 948 | } |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 949 | } else { |
| 950 | /* EXPORT_NORM can be enabled if: |
| 951 | * - 11-bit or smaller UNORM/SNORM/SRGB |
| 952 | * - 16-bit or smaller FLOAT |
| 953 | */ |
| 954 | if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && |
| 955 | ((desc->channel[i].size < 12 && |
| 956 | desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && |
| 957 | ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || |
| 958 | (desc->channel[i].size < 17 && |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 959 | desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) { |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 960 | color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 961 | surf->export_16bpc = true; |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 962 | } |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 963 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 964 | |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 965 | /* These might not always be initialized to zero. */ |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 966 | surf->cb_color_base = offset >> 8; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 967 | surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) | |
| 968 | S_028060_SLICE_TILE_MAX(slice); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 969 | surf->cb_color_fmask = surf->cb_color_base; |
| 970 | surf->cb_color_cmask = surf->cb_color_base; |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 971 | surf->cb_color_mask = 0; |
| 972 | |
| 973 | pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, |
| 974 | &rtex->resource.b.b); |
| 975 | pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, |
| 976 | &rtex->resource.b.b); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 977 | |
Marek Olšák | 39801d4 | 2013-09-21 19:56:24 +0200 | [diff] [blame] | 978 | if (rtex->cmask.size) { |
| 979 | surf->cb_color_cmask = rtex->cmask.offset >> 8; |
| 980 | surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 981 | |
Marek Olšák | 39801d4 | 2013-09-21 19:56:24 +0200 | [diff] [blame] | 982 | if (rtex->fmask.size) { |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 983 | color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE); |
Marek Olšák | 39801d4 | 2013-09-21 19:56:24 +0200 | [diff] [blame] | 984 | surf->cb_color_fmask = rtex->fmask.offset >> 8; |
| 985 | surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 986 | } else { /* cmask only */ |
| 987 | color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE); |
| 988 | } |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 989 | } else if (force_cmask_fmask) { |
| 990 | /* Allocate dummy FMASK and CMASK if they aren't allocated already. |
| 991 | * |
| 992 | * R6xx needs FMASK and CMASK for the destination buffer of color resolve, |
| 993 | * otherwise it hangs. We don't have FMASK and CMASK pre-allocated, |
| 994 | * because it's not an MSAA buffer. |
| 995 | */ |
| 996 | struct r600_cmask_info cmask; |
| 997 | struct r600_fmask_info fmask; |
| 998 | |
Marek Olšák | e64633e | 2013-09-22 13:06:27 +0200 | [diff] [blame] | 999 | r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask); |
| 1000 | r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 1001 | |
| 1002 | /* CMASK. */ |
| 1003 | if (!rctx->dummy_cmask || |
| 1004 | rctx->dummy_cmask->buf->size < cmask.size || |
| 1005 | rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) { |
| 1006 | struct pipe_transfer *transfer; |
| 1007 | void *ptr; |
| 1008 | |
| 1009 | pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL); |
| 1010 | rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment); |
| 1011 | |
| 1012 | /* Set the contents to 0xCC. */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1013 | ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 1014 | memset(ptr, 0xCC, cmask.size); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1015 | pipe_buffer_unmap(&rctx->b.b, transfer); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 1016 | } |
| 1017 | pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, |
| 1018 | &rctx->dummy_cmask->b.b); |
| 1019 | |
| 1020 | /* FMASK. */ |
| 1021 | if (!rctx->dummy_fmask || |
| 1022 | rctx->dummy_fmask->buf->size < fmask.size || |
| 1023 | rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) { |
| 1024 | pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL); |
| 1025 | rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment); |
| 1026 | |
| 1027 | } |
| 1028 | pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, |
| 1029 | &rctx->dummy_fmask->b.b); |
| 1030 | |
| 1031 | /* Init the registers. */ |
| 1032 | color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE); |
| 1033 | surf->cb_color_cmask = 0; |
| 1034 | surf->cb_color_fmask = 0; |
| 1035 | surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) | |
Marek Olšák | 61c995b | 2013-04-11 14:54:40 +0200 | [diff] [blame] | 1036 | S_028100_FMASK_TILE_MAX(fmask.slice_tile_max); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1037 | } |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 1038 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1039 | surf->cb_color_info = color_info; |
Dave Airlie | 7863611 | 2014-01-28 23:15:29 +0000 | [diff] [blame] | 1040 | surf->cb_color_view = color_view; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1041 | surf->color_initialized = true; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1042 | } |
| 1043 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1044 | static void r600_init_depth_surface(struct r600_context *rctx, |
| 1045 | struct r600_surface *surf) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1046 | { |
Marek Olšák | 951ac46 | 2012-08-14 02:29:17 +0200 | [diff] [blame] | 1047 | struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; |
Marek Olšák | faa16dc | 2011-10-25 01:28:39 +0200 | [diff] [blame] | 1048 | unsigned level, pitch, slice, format, offset, array_mode; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1049 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1050 | level = surf->base.u.tex.level; |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 1051 | offset = rtex->surface.level[level].offset; |
| 1052 | pitch = rtex->surface.level[level].nblk_x / 8 - 1; |
| 1053 | slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; |
| 1054 | if (slice) { |
| 1055 | slice = slice - 1; |
| 1056 | } |
| 1057 | switch (rtex->surface.level[level].mode) { |
| 1058 | case RADEON_SURF_MODE_2D: |
| 1059 | array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; |
| 1060 | break; |
| 1061 | case RADEON_SURF_MODE_1D: |
| 1062 | case RADEON_SURF_MODE_LINEAR_ALIGNED: |
| 1063 | case RADEON_SURF_MODE_LINEAR: |
| 1064 | default: |
| 1065 | array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; |
| 1066 | break; |
Jerome Glisse | c0c979e | 2012-01-30 17:22:13 -0500 | [diff] [blame] | 1067 | } |
| 1068 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1069 | format = r600_translate_dbformat(surf->base.format); |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 1070 | assert(format != ~0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1071 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1072 | surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); |
| 1073 | surf->db_depth_base = offset >> 8; |
| 1074 | surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) | |
| 1075 | S_028004_SLICE_MAX(surf->base.u.tex.last_layer); |
| 1076 | surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); |
| 1077 | surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1; |
| 1078 | |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 1079 | switch (surf->base.format) { |
| 1080 | case PIPE_FORMAT_Z24X8_UNORM: |
| 1081 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: |
| 1082 | surf->pa_su_poly_offset_db_fmt_cntl = |
| 1083 | S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24); |
| 1084 | break; |
| 1085 | case PIPE_FORMAT_Z32_FLOAT: |
| 1086 | case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: |
| 1087 | surf->pa_su_poly_offset_db_fmt_cntl = |
| 1088 | S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) | |
| 1089 | S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); |
| 1090 | break; |
| 1091 | case PIPE_FORMAT_Z16_UNORM: |
| 1092 | surf->pa_su_poly_offset_db_fmt_cntl = |
| 1093 | S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16); |
| 1094 | break; |
| 1095 | default:; |
| 1096 | } |
| 1097 | |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1098 | /* use htile only for first level */ |
Andreas Hartmetz | ca5812b | 2013-12-07 02:08:27 +0100 | [diff] [blame] | 1099 | if (rtex->htile_buffer && !level) { |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 1100 | surf->db_htile_data_base = 0; |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1101 | surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | |
Marek Olšák | 6d75106 | 2014-08-20 01:34:37 +0200 | [diff] [blame^] | 1102 | S_028D24_HTILE_HEIGHT(1) | |
| 1103 | S_028D24_FULL_CACHE(1); |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1104 | /* preload is not working properly on r6xx/r7xx */ |
| 1105 | surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1); |
| 1106 | } |
| 1107 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1108 | surf->depth_initialized = true; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1109 | } |
| 1110 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1111 | static void r600_set_framebuffer_state(struct pipe_context *ctx, |
| 1112 | const struct pipe_framebuffer_state *state) |
| 1113 | { |
| 1114 | struct r600_context *rctx = (struct r600_context *)ctx; |
| 1115 | struct r600_surface *surf; |
| 1116 | struct r600_texture *rtex; |
| 1117 | unsigned i; |
| 1118 | |
| 1119 | if (rctx->framebuffer.state.nr_cbufs) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1120 | rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1121 | rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | |
| 1122 | R600_CONTEXT_FLUSH_AND_INV_CB_META; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1123 | } |
| 1124 | if (rctx->framebuffer.state.zsbuf) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1125 | rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV; |
| 1126 | rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB; |
Marek Olšák | e5a250f | 2013-02-26 22:31:03 +0100 | [diff] [blame] | 1127 | |
| 1128 | rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture; |
Andreas Hartmetz | ca5812b | 2013-12-07 02:08:27 +0100 | [diff] [blame] | 1129 | if (rctx->b.chip_class >= R700 && rtex->htile_buffer) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1130 | rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META; |
Marek Olšák | e5a250f | 2013-02-26 22:31:03 +0100 | [diff] [blame] | 1131 | } |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1132 | } |
| 1133 | |
| 1134 | /* Set the new state. */ |
| 1135 | util_copy_framebuffer_state(&rctx->framebuffer.state, state); |
| 1136 | |
| 1137 | rctx->framebuffer.export_16bpc = state->nr_cbufs != 0; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1138 | rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] && |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1139 | util_format_is_pure_integer(state->cbufs[0]->format); |
| 1140 | rctx->framebuffer.compressed_cb_mask = 0; |
| 1141 | rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 && |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1142 | state->cbufs[0] && state->cbufs[1] && |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1143 | state->cbufs[0]->texture->nr_samples > 1 && |
| 1144 | state->cbufs[1]->texture->nr_samples <= 1; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1145 | rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1146 | |
| 1147 | /* Colorbuffers. */ |
| 1148 | for (i = 0; i < state->nr_cbufs; i++) { |
| 1149 | /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1150 | bool force_cmask_fmask = rctx->b.chip_class == R600 && |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1151 | rctx->framebuffer.is_msaa_resolve && |
| 1152 | i == 1; |
| 1153 | |
| 1154 | surf = (struct r600_surface*)state->cbufs[i]; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1155 | if (!surf) |
| 1156 | continue; |
| 1157 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1158 | rtex = (struct r600_texture*)surf->base.texture; |
Jerome Glisse | 5e0c956 | 2013-01-29 12:52:17 -0500 | [diff] [blame] | 1159 | r600_context_add_resource_size(ctx, state->cbufs[i]->texture); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1160 | |
| 1161 | if (!surf->color_initialized || force_cmask_fmask) { |
| 1162 | r600_init_color_surface(rctx, surf, force_cmask_fmask); |
| 1163 | if (force_cmask_fmask) { |
| 1164 | /* re-initialize later without compression */ |
| 1165 | surf->color_initialized = false; |
| 1166 | } |
| 1167 | } |
| 1168 | |
| 1169 | if (!surf->export_16bpc) { |
| 1170 | rctx->framebuffer.export_16bpc = false; |
| 1171 | } |
| 1172 | |
Marek Olšák | 39801d4 | 2013-09-21 19:56:24 +0200 | [diff] [blame] | 1173 | if (rtex->fmask.size && rtex->cmask.size) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1174 | rctx->framebuffer.compressed_cb_mask |= 1 << i; |
| 1175 | } |
| 1176 | } |
| 1177 | |
| 1178 | /* Update alpha-test state dependencies. |
| 1179 | * Alpha-test is done on the first colorbuffer only. */ |
| 1180 | if (state->nr_cbufs) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1181 | bool alphatest_bypass = false; |
| 1182 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1183 | surf = (struct r600_surface*)state->cbufs[0]; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1184 | if (surf) { |
| 1185 | alphatest_bypass = surf->alphatest_bypass; |
| 1186 | } |
| 1187 | |
| 1188 | if (rctx->alphatest_state.bypass != alphatest_bypass) { |
| 1189 | rctx->alphatest_state.bypass = alphatest_bypass; |
Marek Olšák | eb65fef | 2012-10-07 03:47:43 +0200 | [diff] [blame] | 1190 | rctx->alphatest_state.atom.dirty = true; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1191 | } |
| 1192 | } |
| 1193 | |
| 1194 | /* ZS buffer. */ |
| 1195 | if (state->zsbuf) { |
| 1196 | surf = (struct r600_surface*)state->zsbuf; |
| 1197 | |
Jerome Glisse | 5e0c956 | 2013-01-29 12:52:17 -0500 | [diff] [blame] | 1198 | r600_context_add_resource_size(ctx, state->zsbuf->texture); |
| 1199 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1200 | if (!surf->depth_initialized) { |
| 1201 | r600_init_depth_surface(rctx, surf); |
| 1202 | } |
| 1203 | |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 1204 | if (state->zsbuf->format != rctx->poly_offset_state.zs_format) { |
| 1205 | rctx->poly_offset_state.zs_format = state->zsbuf->format; |
| 1206 | rctx->poly_offset_state.atom.dirty = true; |
| 1207 | } |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1208 | |
| 1209 | if (rctx->db_state.rsurf != surf) { |
| 1210 | rctx->db_state.rsurf = surf; |
| 1211 | rctx->db_state.atom.dirty = true; |
| 1212 | rctx->db_misc_state.atom.dirty = true; |
| 1213 | } |
| 1214 | } else if (rctx->db_state.rsurf) { |
| 1215 | rctx->db_state.rsurf = NULL; |
| 1216 | rctx->db_state.atom.dirty = true; |
| 1217 | rctx->db_misc_state.atom.dirty = true; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1218 | } |
| 1219 | |
| 1220 | if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) { |
| 1221 | rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; |
Marek Olšák | eb65fef | 2012-10-07 03:47:43 +0200 | [diff] [blame] | 1222 | rctx->cb_misc_state.atom.dirty = true; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1223 | } |
| 1224 | |
| 1225 | if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) { |
| 1226 | rctx->alphatest_state.bypass = false; |
Marek Olšák | eb65fef | 2012-10-07 03:47:43 +0200 | [diff] [blame] | 1227 | rctx->alphatest_state.atom.dirty = true; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1228 | } |
| 1229 | |
| 1230 | /* Calculate the CS size. */ |
| 1231 | rctx->framebuffer.atom.num_dw = |
| 1232 | 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/; |
| 1233 | |
| 1234 | if (rctx->framebuffer.state.nr_cbufs) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1235 | rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs; |
| 1236 | rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1237 | } |
| 1238 | if (rctx->framebuffer.state.zsbuf) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1239 | rctx->framebuffer.atom.num_dw += 16; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1240 | } else if (rctx->screen->b.info.drm_minor >= 18) { |
Marek Olšák | 9f5d632 | 2012-08-14 20:42:35 +0200 | [diff] [blame] | 1241 | rctx->framebuffer.atom.num_dw += 3; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1242 | } |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1243 | if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1244 | rctx->framebuffer.atom.num_dw += 2; |
| 1245 | } |
| 1246 | |
Marek Olšák | eb65fef | 2012-10-07 03:47:43 +0200 | [diff] [blame] | 1247 | rctx->framebuffer.atom.dirty = true; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1248 | } |
| 1249 | |
Dave Airlie | f024c72 | 2013-03-04 06:19:07 +1000 | [diff] [blame] | 1250 | static uint32_t sample_locs_2x[] = { |
| 1251 | FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), |
| 1252 | FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), |
| 1253 | }; |
| 1254 | static unsigned max_dist_2x = 4; |
| 1255 | |
| 1256 | static uint32_t sample_locs_4x[] = { |
| 1257 | FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), |
| 1258 | FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), |
| 1259 | }; |
| 1260 | static unsigned max_dist_4x = 6; |
| 1261 | static uint32_t sample_locs_8x[] = { |
| 1262 | FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3), |
| 1263 | FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7), |
| 1264 | }; |
| 1265 | static unsigned max_dist_8x = 7; |
| 1266 | |
| 1267 | static void r600_get_sample_position(struct pipe_context *ctx, |
| 1268 | unsigned sample_count, |
| 1269 | unsigned sample_index, |
| 1270 | float *out_value) |
| 1271 | { |
| 1272 | int offset, index; |
| 1273 | struct { |
| 1274 | int idx:4; |
| 1275 | } val; |
| 1276 | switch (sample_count) { |
| 1277 | case 1: |
| 1278 | default: |
| 1279 | out_value[0] = out_value[1] = 0.5; |
| 1280 | break; |
| 1281 | case 2: |
| 1282 | offset = 4 * (sample_index * 2); |
| 1283 | val.idx = (sample_locs_2x[0] >> offset) & 0xf; |
| 1284 | out_value[0] = (float)(val.idx + 8) / 16.0f; |
| 1285 | val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf; |
| 1286 | out_value[1] = (float)(val.idx + 8) / 16.0f; |
| 1287 | break; |
| 1288 | case 4: |
| 1289 | offset = 4 * (sample_index * 2); |
| 1290 | val.idx = (sample_locs_4x[0] >> offset) & 0xf; |
| 1291 | out_value[0] = (float)(val.idx + 8) / 16.0f; |
| 1292 | val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf; |
| 1293 | out_value[1] = (float)(val.idx + 8) / 16.0f; |
| 1294 | break; |
| 1295 | case 8: |
| 1296 | offset = 4 * (sample_index % 4 * 2); |
| 1297 | index = (sample_index / 4); |
| 1298 | val.idx = (sample_locs_8x[index] >> offset) & 0xf; |
| 1299 | out_value[0] = (float)(val.idx + 8) / 16.0f; |
| 1300 | val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf; |
| 1301 | out_value[1] = (float)(val.idx + 8) / 16.0f; |
| 1302 | break; |
| 1303 | } |
| 1304 | } |
| 1305 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1306 | static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples) |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1307 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1308 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1309 | unsigned max_dist = 0; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1310 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1311 | if (rctx->b.family == CHIP_R600) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1312 | switch (nr_samples) { |
| 1313 | default: |
| 1314 | nr_samples = 0; |
| 1315 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1316 | case 2: |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1317 | r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]); |
| 1318 | max_dist = max_dist_2x; |
| 1319 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1320 | case 4: |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1321 | r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]); |
| 1322 | max_dist = max_dist_4x; |
| 1323 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1324 | case 8: |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1325 | r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1326 | radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */ |
| 1327 | radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1328 | max_dist = max_dist_8x; |
| 1329 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1330 | } |
| 1331 | } else { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1332 | switch (nr_samples) { |
| 1333 | default: |
| 1334 | r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1335 | radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ |
| 1336 | radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1337 | nr_samples = 0; |
| 1338 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1339 | case 2: |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1340 | r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1341 | radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ |
| 1342 | radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1343 | max_dist = max_dist_2x; |
| 1344 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1345 | case 4: |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1346 | r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1347 | radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ |
| 1348 | radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1349 | max_dist = max_dist_4x; |
| 1350 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1351 | case 8: |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1352 | r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1353 | radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ |
| 1354 | radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1355 | max_dist = max_dist_8x; |
| 1356 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1357 | } |
| 1358 | } |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1359 | |
| 1360 | if (nr_samples > 1) { |
| 1361 | r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1362 | radeon_emit(cs, S_028C00_LAST_PIXEL(1) | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1363 | S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1364 | radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1365 | S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */ |
| 1366 | } else { |
| 1367 | r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1368 | radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ |
| 1369 | radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1370 | } |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1371 | } |
| 1372 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1373 | static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1374 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1375 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1376 | struct pipe_framebuffer_state *state = &rctx->framebuffer.state; |
| 1377 | unsigned nr_cbufs = state->nr_cbufs; |
| 1378 | struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0]; |
| 1379 | unsigned i, sbu = 0; |
Marek Olšák | fd2e34d | 2012-09-09 06:08:39 +0200 | [diff] [blame] | 1380 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1381 | /* Colorbuffers. */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1382 | r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8); |
| 1383 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1384 | radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1385 | } |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1386 | /* set CB_COLOR1_INFO for possible dual-src blending */ |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1387 | if (i == 1 && cb[0]) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1388 | radeon_emit(cs, cb[0]->cb_color_info); |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1389 | i++; |
| 1390 | } |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1391 | for (; i < 8; i++) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1392 | radeon_emit(cs, 0); |
Marek Olšák | 0d7e002 | 2012-08-14 22:10:35 +0200 | [diff] [blame] | 1393 | } |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1394 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1395 | if (nr_cbufs) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1396 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1397 | unsigned reloc; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1398 | |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1399 | if (!cb[i]) |
| 1400 | continue; |
| 1401 | |
| 1402 | /* COLOR_BASE */ |
| 1403 | r600_write_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base); |
| 1404 | |
| 1405 | reloc = r600_context_bo_reloc(&rctx->b, |
| 1406 | &rctx->b.rings.gfx, |
| 1407 | (struct r600_resource*)cb[i]->base.texture, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1408 | RADEON_USAGE_READWRITE, |
| 1409 | cb[i]->base.texture->nr_samples > 1 ? |
| 1410 | RADEON_PRIO_COLOR_BUFFER_MSAA : |
| 1411 | RADEON_PRIO_COLOR_BUFFER); |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1412 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1413 | radeon_emit(cs, reloc); |
| 1414 | |
| 1415 | /* FMASK */ |
| 1416 | r600_write_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask); |
| 1417 | |
| 1418 | reloc = r600_context_bo_reloc(&rctx->b, |
| 1419 | &rctx->b.rings.gfx, |
| 1420 | cb[i]->cb_buffer_fmask, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1421 | RADEON_USAGE_READWRITE, |
| 1422 | cb[i]->base.texture->nr_samples > 1 ? |
| 1423 | RADEON_PRIO_COLOR_BUFFER_MSAA : |
| 1424 | RADEON_PRIO_COLOR_BUFFER); |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1425 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1426 | radeon_emit(cs, reloc); |
| 1427 | |
| 1428 | /* CMASK */ |
| 1429 | r600_write_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask); |
| 1430 | |
| 1431 | reloc = r600_context_bo_reloc(&rctx->b, |
| 1432 | &rctx->b.rings.gfx, |
| 1433 | cb[i]->cb_buffer_cmask, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1434 | RADEON_USAGE_READWRITE, |
| 1435 | cb[i]->base.texture->nr_samples > 1 ? |
| 1436 | RADEON_PRIO_COLOR_BUFFER_MSAA : |
| 1437 | RADEON_PRIO_COLOR_BUFFER); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1438 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1439 | radeon_emit(cs, reloc); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1440 | } |
| 1441 | |
| 1442 | r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs); |
| 1443 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1444 | radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1445 | } |
| 1446 | |
| 1447 | r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs); |
| 1448 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1449 | radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1450 | } |
| 1451 | |
| 1452 | r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs); |
| 1453 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1454 | radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1455 | } |
| 1456 | |
| 1457 | sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs); |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1458 | } |
| 1459 | |
Jerome Glisse | 24b1206 | 2012-11-01 16:09:40 -0400 | [diff] [blame] | 1460 | /* SURFACE_BASE_UPDATE */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1461 | if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) { |
| 1462 | radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); |
| 1463 | radeon_emit(cs, sbu); |
Jerome Glisse | 24b1206 | 2012-11-01 16:09:40 -0400 | [diff] [blame] | 1464 | sbu = 0; |
| 1465 | } |
| 1466 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1467 | /* Zbuffer. */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1468 | if (state->zsbuf) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1469 | struct r600_surface *surf = (struct r600_surface*)state->zsbuf; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1470 | unsigned reloc = r600_context_bo_reloc(&rctx->b, |
| 1471 | &rctx->b.rings.gfx, |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1472 | (struct r600_resource*)state->zsbuf->texture, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1473 | RADEON_USAGE_READWRITE, |
| 1474 | surf->base.texture->nr_samples > 1 ? |
| 1475 | RADEON_PRIO_DEPTH_BUFFER_MSAA : |
| 1476 | RADEON_PRIO_DEPTH_BUFFER); |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1477 | |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 1478 | r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, |
| 1479 | surf->pa_su_poly_offset_db_fmt_cntl); |
| 1480 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1481 | r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1482 | radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */ |
| 1483 | radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1484 | r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1485 | radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */ |
| 1486 | radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */ |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1487 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1488 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1489 | radeon_emit(cs, reloc); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1490 | |
| 1491 | r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); |
| 1492 | |
| 1493 | sbu |= SURFACE_BASE_UPDATE_DEPTH; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1494 | } else if (rctx->screen->b.info.drm_minor >= 18) { |
Marek Olšák | 9f5d632 | 2012-08-14 20:42:35 +0200 | [diff] [blame] | 1495 | /* DRM 2.6.18 allows the INVALID format to disable depth/stencil. |
| 1496 | * Older kernels are out of luck. */ |
| 1497 | r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID)); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1498 | } |
| 1499 | |
| 1500 | /* SURFACE_BASE_UPDATE */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1501 | if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) { |
| 1502 | radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); |
| 1503 | radeon_emit(cs, sbu); |
Jerome Glisse | 24b1206 | 2012-11-01 16:09:40 -0400 | [diff] [blame] | 1504 | sbu = 0; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1505 | } |
| 1506 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1507 | /* Framebuffer dimensions. */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1508 | r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1509 | radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1510 | S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1511 | radeon_emit(cs, S_028244_BR_X(state->width) | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1512 | S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1513 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1514 | if (rctx->framebuffer.is_msaa_resolve) { |
| 1515 | r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1516 | } else { |
| 1517 | /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This |
| 1518 | * will assure that the alpha-test will work even if there is |
| 1519 | * no colorbuffer bound. */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1520 | r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, |
| 1521 | (1ull << MAX2(nr_cbufs, 1)) - 1); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1522 | } |
Marek Olšák | 82a1d24 | 2012-07-18 04:31:56 +0200 | [diff] [blame] | 1523 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1524 | r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples); |
Marek Olšák | 0ea7691 | 2012-07-07 07:15:04 +0200 | [diff] [blame] | 1525 | } |
| 1526 | |
| 1527 | static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) |
| 1528 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1529 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | 0ea7691 | 2012-07-07 07:15:04 +0200 | [diff] [blame] | 1530 | struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; |
Marek Olšák | 0ea7691 | 2012-07-07 07:15:04 +0200 | [diff] [blame] | 1531 | |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1532 | if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) { |
| 1533 | r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1534 | if (rctx->b.chip_class == R600) { |
| 1535 | radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */ |
| 1536 | radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */ |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1537 | } else { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1538 | radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */ |
| 1539 | radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */ |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1540 | } |
| 1541 | r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control); |
| 1542 | } else { |
| 1543 | unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1; |
| 1544 | unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1; |
| 1545 | unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1; |
| 1546 | |
| 1547 | r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1548 | radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */ |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1549 | /* Always enable the first color output to make sure alpha-test works even without one. */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1550 | radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */ |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1551 | r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, |
| 1552 | a->cb_color_control | |
| 1553 | S_028808_MULTIWRITE_ENABLE(multiwrite)); |
| 1554 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1555 | } |
| 1556 | |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1557 | static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom) |
| 1558 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1559 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1560 | struct r600_db_state *a = (struct r600_db_state*)atom; |
| 1561 | |
Marek Olšák | ec266d0 | 2014-02-09 19:30:09 +0100 | [diff] [blame] | 1562 | if (a->rsurf && a->rsurf->db_htile_surface) { |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1563 | struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture; |
| 1564 | unsigned reloc_idx; |
| 1565 | |
Andreas Hartmetz | ca5812b | 2013-12-07 02:08:27 +0100 | [diff] [blame] | 1566 | r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1567 | r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); |
| 1568 | r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1569 | reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, |
| 1570 | RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META); |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1571 | cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); |
| 1572 | cs->buf[cs->cdw++] = reloc_idx; |
| 1573 | } else { |
| 1574 | r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0); |
| 1575 | } |
| 1576 | } |
| 1577 | |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1578 | static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) |
| 1579 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1580 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | e363dd5 | 2012-03-05 16:20:05 +0100 | [diff] [blame] | 1581 | struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1582 | unsigned db_render_control = 0; |
| 1583 | unsigned db_render_override = |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1584 | S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | |
| 1585 | S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); |
| 1586 | |
| 1587 | if (a->occlusion_query_enabled) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1588 | if (rctx->b.chip_class >= R700) { |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1589 | db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); |
| 1590 | } |
| 1591 | db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); |
| 1592 | } |
Marek Olšák | ec266d0 | 2014-02-09 19:30:09 +0100 | [diff] [blame] | 1593 | if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1594 | /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */ |
| 1595 | db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF); |
Jerome Glisse | 974b482 | 2013-02-08 16:02:32 -0500 | [diff] [blame] | 1596 | /* This is to fix a lockup when hyperz and alpha test are enabled at |
| 1597 | * the same time somehow GPU get confuse on which order to pick for |
| 1598 | * z test |
| 1599 | */ |
| 1600 | if (rctx->alphatest_state.sx_alpha_test_control) { |
| 1601 | db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1); |
| 1602 | } |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1603 | } else { |
| 1604 | db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); |
| 1605 | } |
Marek Olšák | df79eb5 | 2012-07-07 19:33:11 +0200 | [diff] [blame] | 1606 | if (a->flush_depthstencil_through_cb) { |
Marek Olšák | e2f623f | 2012-07-28 13:55:59 +0200 | [diff] [blame] | 1607 | assert(a->copy_depth || a->copy_stencil); |
| 1608 | |
| 1609 | db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) | |
| 1610 | S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1611 | S_028D0C_COPY_CENTROID(1) | |
| 1612 | S_028D0C_COPY_SAMPLE(a->copy_sample); |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 1613 | } else if (a->flush_depthstencil_in_place) { |
| 1614 | db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) | |
| 1615 | S_028D0C_STENCIL_COMPRESS_DISABLE(1); |
| 1616 | db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1617 | } |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1618 | if (a->htile_clear) { |
| 1619 | db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1); |
| 1620 | } |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1621 | |
Marek Olšák | 3d0c4f3 | 2014-04-20 18:11:56 +0200 | [diff] [blame] | 1622 | /* RV770 workaround for a hang with 8x MSAA. */ |
| 1623 | if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) { |
| 1624 | db_render_override |= S_028D10_MAX_TILES_IN_DTT(6); |
| 1625 | } |
| 1626 | |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1627 | r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1628 | radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ |
| 1629 | radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ |
Marek Olšák | c5584e9 | 2012-10-06 06:05:32 +0200 | [diff] [blame] | 1630 | r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control); |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1631 | } |
| 1632 | |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 1633 | static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom) |
| 1634 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1635 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 1636 | struct r600_config_state *a = (struct r600_config_state*)atom; |
| 1637 | |
| 1638 | r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1639 | r600_write_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2); |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 1640 | } |
| 1641 | |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1642 | static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom) |
| 1643 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1644 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1645 | uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask; |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1646 | |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1647 | while (dirty_mask) { |
| 1648 | struct pipe_vertex_buffer *vb; |
| 1649 | struct r600_resource *rbuffer; |
| 1650 | unsigned offset; |
| 1651 | unsigned buffer_index = u_bit_scan(&dirty_mask); |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1652 | |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1653 | vb = &rctx->vertex_buffer_state.vb[buffer_index]; |
| 1654 | rbuffer = (struct r600_resource*)vb->buffer; |
| 1655 | assert(rbuffer); |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1656 | |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1657 | offset = vb->buffer_offset; |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1658 | |
| 1659 | /* fetch resources start at index 320 */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1660 | radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); |
| 1661 | radeon_emit(cs, (320 + buffer_index) * 7); |
| 1662 | radeon_emit(cs, offset); /* RESOURCEi_WORD0 */ |
| 1663 | radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ |
| 1664 | radeon_emit(cs, /* RESOURCEi_WORD2 */ |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1665 | S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1666 | S_038008_STRIDE(vb->stride)); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1667 | radeon_emit(cs, 0); /* RESOURCEi_WORD3 */ |
| 1668 | radeon_emit(cs, 0); /* RESOURCEi_WORD4 */ |
| 1669 | radeon_emit(cs, 0); /* RESOURCEi_WORD5 */ |
| 1670 | radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */ |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1671 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1672 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1673 | radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, |
| 1674 | RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO)); |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1675 | } |
| 1676 | } |
| 1677 | |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1678 | static void r600_emit_constant_buffers(struct r600_context *rctx, |
| 1679 | struct r600_constbuf_state *state, |
| 1680 | unsigned buffer_id_base, |
| 1681 | unsigned reg_alu_constbuf_size, |
| 1682 | unsigned reg_alu_const_cache) |
| 1683 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1684 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1685 | uint32_t dirty_mask = state->dirty_mask; |
| 1686 | |
| 1687 | while (dirty_mask) { |
Marek Olšák | 5073378 | 2012-04-24 19:52:26 +0200 | [diff] [blame] | 1688 | struct pipe_constant_buffer *cb; |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1689 | struct r600_resource *rbuffer; |
| 1690 | unsigned offset; |
| 1691 | unsigned buffer_index = ffs(dirty_mask) - 1; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1692 | unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER); |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1693 | cb = &state->cb[buffer_index]; |
| 1694 | rbuffer = (struct r600_resource*)cb->buffer; |
| 1695 | assert(rbuffer); |
| 1696 | |
| 1697 | offset = cb->buffer_offset; |
| 1698 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1699 | if (!gs_ring_buffer) { |
| 1700 | r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, |
| 1701 | ALIGN_DIVUP(cb->buffer_size >> 4, 16)); |
| 1702 | r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); |
| 1703 | } |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1704 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1705 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1706 | radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, |
| 1707 | RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO)); |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1708 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1709 | radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); |
| 1710 | radeon_emit(cs, (buffer_id_base + buffer_index) * 7); |
| 1711 | radeon_emit(cs, offset); /* RESOURCEi_WORD0 */ |
| 1712 | radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ |
| 1713 | radeon_emit(cs, /* RESOURCEi_WORD2 */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1714 | S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) | |
| 1715 | S_038008_STRIDE(gs_ring_buffer ? 4 : 16)); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1716 | radeon_emit(cs, 0); /* RESOURCEi_WORD3 */ |
| 1717 | radeon_emit(cs, 0); /* RESOURCEi_WORD4 */ |
| 1718 | radeon_emit(cs, 0); /* RESOURCEi_WORD5 */ |
| 1719 | radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */ |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1720 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1721 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1722 | radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, |
| 1723 | RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO)); |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1724 | |
| 1725 | dirty_mask &= ~(1 << buffer_index); |
| 1726 | } |
| 1727 | state->dirty_mask = 0; |
| 1728 | } |
| 1729 | |
Marek Olšák | 0b4c5db | 2012-07-14 18:14:16 +0200 | [diff] [blame] | 1730 | static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1731 | { |
Marek Olšák | 1bce17e | 2012-09-10 00:56:45 +0200 | [diff] [blame] | 1732 | r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160, |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1733 | R_028180_ALU_CONST_BUFFER_SIZE_VS_0, |
| 1734 | R_028980_ALU_CONST_CACHE_VS_0); |
| 1735 | } |
| 1736 | |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1737 | static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) |
| 1738 | { |
| 1739 | r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336, |
| 1740 | R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, |
| 1741 | R_0289C0_ALU_CONST_CACHE_GS_0); |
| 1742 | } |
| 1743 | |
Marek Olšák | 0b4c5db | 2012-07-14 18:14:16 +0200 | [diff] [blame] | 1744 | static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1745 | { |
Marek Olšák | 1bce17e | 2012-09-10 00:56:45 +0200 | [diff] [blame] | 1746 | r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0, |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1747 | R_028140_ALU_CONST_BUFFER_SIZE_PS_0, |
| 1748 | R_028940_ALU_CONST_CACHE_PS_0); |
| 1749 | } |
| 1750 | |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1751 | static void r600_emit_sampler_views(struct r600_context *rctx, |
| 1752 | struct r600_samplerview_state *state, |
| 1753 | unsigned resource_id_base) |
| 1754 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1755 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1756 | uint32_t dirty_mask = state->dirty_mask; |
| 1757 | |
| 1758 | while (dirty_mask) { |
| 1759 | struct r600_pipe_sampler_view *rview; |
| 1760 | unsigned resource_index = u_bit_scan(&dirty_mask); |
| 1761 | unsigned reloc; |
| 1762 | |
| 1763 | rview = state->views[resource_index]; |
| 1764 | assert(rview); |
| 1765 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1766 | radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); |
| 1767 | radeon_emit(cs, (resource_id_base + resource_index) * 7); |
| 1768 | radeon_emit_array(cs, rview->tex_resource_words, 7); |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1769 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1770 | reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1771 | RADEON_USAGE_READ, |
| 1772 | rview->tex_resource->b.b.nr_samples > 1 ? |
| 1773 | RADEON_PRIO_SHADER_TEXTURE_MSAA : |
| 1774 | RADEON_PRIO_SHADER_TEXTURE_RO); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1775 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1776 | radeon_emit(cs, reloc); |
| 1777 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1778 | radeon_emit(cs, reloc); |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1779 | } |
| 1780 | state->dirty_mask = 0; |
| 1781 | } |
| 1782 | |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1783 | /* Resource IDs: |
| 1784 | * PS: 0 .. +160 |
| 1785 | * VS: 160 .. +160 |
| 1786 | * FS: 320 .. +16 |
| 1787 | * GS: 336 .. +160 |
| 1788 | */ |
| 1789 | |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1790 | static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) |
| 1791 | { |
Marek Olšák | f2eac14 | 2012-09-10 04:53:33 +0200 | [diff] [blame] | 1792 | r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS); |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1793 | } |
| 1794 | |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1795 | static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) |
| 1796 | { |
| 1797 | r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS); |
| 1798 | } |
| 1799 | |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1800 | static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom) |
| 1801 | { |
Marek Olšák | f2eac14 | 2012-09-10 04:53:33 +0200 | [diff] [blame] | 1802 | r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS); |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1803 | } |
| 1804 | |
Marek Olšák | 3bffd8a | 2012-09-10 00:34:37 +0200 | [diff] [blame] | 1805 | static void r600_emit_sampler_states(struct r600_context *rctx, |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1806 | struct r600_textures_info *texinfo, |
| 1807 | unsigned resource_id_base, |
| 1808 | unsigned border_color_reg) |
| 1809 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1810 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1811 | uint32_t dirty_mask = texinfo->states.dirty_mask; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1812 | |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1813 | while (dirty_mask) { |
| 1814 | struct r600_pipe_sampler_state *rstate; |
| 1815 | struct r600_pipe_sampler_view *rview; |
| 1816 | unsigned i = u_bit_scan(&dirty_mask); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1817 | |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1818 | rstate = texinfo->states.states[i]; |
| 1819 | assert(rstate); |
| 1820 | rview = texinfo->views.views[i]; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1821 | |
| 1822 | /* TEX_ARRAY_OVERRIDE must be set for array textures to disable |
| 1823 | * filtering between layers. |
| 1824 | * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. |
| 1825 | */ |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1826 | if (rview) { |
| 1827 | enum pipe_texture_target target = rview->base.texture->target; |
| 1828 | if (target == PIPE_TEXTURE_1D_ARRAY || |
| 1829 | target == PIPE_TEXTURE_2D_ARRAY) { |
| 1830 | rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1831 | texinfo->is_array_sampler[i] = true; |
| 1832 | } else { |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1833 | rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1834 | texinfo->is_array_sampler[i] = false; |
| 1835 | } |
| 1836 | } |
| 1837 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1838 | radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0)); |
| 1839 | radeon_emit(cs, (resource_id_base + i) * 3); |
| 1840 | radeon_emit_array(cs, rstate->tex_sampler_words, 3); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1841 | |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1842 | if (rstate->border_color_use) { |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1843 | unsigned offset; |
| 1844 | |
| 1845 | offset = border_color_reg; |
| 1846 | offset += i * 16; |
| 1847 | r600_write_config_reg_seq(cs, offset, 4); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1848 | radeon_emit_array(cs, rstate->border_color.ui, 4); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1849 | } |
| 1850 | } |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1851 | texinfo->states.dirty_mask = 0; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1852 | } |
| 1853 | |
Marek Olšák | 3bffd8a | 2012-09-10 00:34:37 +0200 | [diff] [blame] | 1854 | static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1855 | { |
Marek Olšák | f2eac14 | 2012-09-10 04:53:33 +0200 | [diff] [blame] | 1856 | r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1857 | } |
| 1858 | |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1859 | static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) |
| 1860 | { |
| 1861 | r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED); |
| 1862 | } |
| 1863 | |
Marek Olšák | 3bffd8a | 2012-09-10 00:34:37 +0200 | [diff] [blame] | 1864 | static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1865 | { |
Marek Olšák | f2eac14 | 2012-09-10 04:53:33 +0200 | [diff] [blame] | 1866 | r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1867 | } |
| 1868 | |
| 1869 | static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom) |
| 1870 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1871 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1872 | unsigned tmp; |
| 1873 | |
| 1874 | tmp = S_009508_DISABLE_CUBE_ANISO(1) | |
| 1875 | S_009508_SYNC_GRADIENT(1) | |
| 1876 | S_009508_SYNC_WALKER(1) | |
| 1877 | S_009508_SYNC_ALIGNER(1); |
| 1878 | if (!rctx->seamless_cube_map.enabled) { |
| 1879 | tmp |= S_009508_DISABLE_CUBE_WRAP(1); |
| 1880 | } |
| 1881 | r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp); |
| 1882 | } |
| 1883 | |
Marek Olšák | a01791a | 2012-07-22 07:48:52 +0200 | [diff] [blame] | 1884 | static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a) |
| 1885 | { |
| 1886 | struct r600_sample_mask *s = (struct r600_sample_mask*)a; |
| 1887 | uint8_t mask = s->sample_mask; |
| 1888 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1889 | r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK, |
Marek Olšák | a01791a | 2012-07-22 07:48:52 +0200 | [diff] [blame] | 1890 | mask | (mask << 8) | (mask << 16) | (mask << 24)); |
| 1891 | } |
| 1892 | |
Marek Olšák | a50edc8 | 2012-10-05 04:02:22 +0200 | [diff] [blame] | 1893 | static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a) |
| 1894 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1895 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
Marek Olšák | a50edc8 | 2012-10-05 04:02:22 +0200 | [diff] [blame] | 1896 | struct r600_cso_state *state = (struct r600_cso_state*)a; |
Marek Olšák | d225d07 | 2012-12-09 18:51:31 +0100 | [diff] [blame] | 1897 | struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso; |
Marek Olšák | a50edc8 | 2012-10-05 04:02:22 +0200 | [diff] [blame] | 1898 | |
Marek Olšák | d225d07 | 2012-12-09 18:51:31 +0100 | [diff] [blame] | 1899 | r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1900 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1901 | radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, |
| 1902 | RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA)); |
Marek Olšák | a50edc8 | 2012-10-05 04:02:22 +0200 | [diff] [blame] | 1903 | } |
| 1904 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1905 | static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a) |
| 1906 | { |
| 1907 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
| 1908 | struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a; |
| 1909 | |
| 1910 | uint32_t v2 = 0, primid = 0; |
| 1911 | |
| 1912 | if (state->geom_enable) { |
| 1913 | uint32_t cut_val; |
| 1914 | |
| 1915 | if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128) |
| 1916 | cut_val = V_028A40_GS_CUT_128; |
| 1917 | else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256) |
| 1918 | cut_val = V_028A40_GS_CUT_256; |
| 1919 | else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512) |
| 1920 | cut_val = V_028A40_GS_CUT_512; |
| 1921 | else |
| 1922 | cut_val = V_028A40_GS_CUT_1024; |
| 1923 | |
| 1924 | v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) | |
| 1925 | S_028A40_CUT_MODE(cut_val); |
| 1926 | |
| 1927 | if (rctx->gs_shader->current->shader.gs_prim_id_input) |
| 1928 | primid = 1; |
| 1929 | } |
| 1930 | |
| 1931 | r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2); |
| 1932 | r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid); |
| 1933 | } |
| 1934 | |
| 1935 | static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) |
| 1936 | { |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1937 | struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; |
| 1938 | struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a; |
| 1939 | struct r600_resource *rbuffer; |
| 1940 | |
| 1941 | r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); |
| 1942 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); |
| 1943 | radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH)); |
| 1944 | |
| 1945 | if (state->enable) { |
| 1946 | rbuffer =(struct r600_resource*)state->esgs_ring.buffer; |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 1947 | r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1948 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1949 | radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, |
| 1950 | RADEON_USAGE_READWRITE, |
| 1951 | RADEON_PRIO_SHADER_RESOURCE_RW)); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1952 | r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, |
| 1953 | state->esgs_ring.buffer_size >> 8); |
| 1954 | |
| 1955 | rbuffer =(struct r600_resource*)state->gsvs_ring.buffer; |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 1956 | r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1957 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1958 | radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, |
| 1959 | RADEON_USAGE_READWRITE, |
| 1960 | RADEON_PRIO_SHADER_RESOURCE_RW)); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1961 | r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, |
| 1962 | state->gsvs_ring.buffer_size >> 8); |
| 1963 | } else { |
| 1964 | r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0); |
| 1965 | r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0); |
| 1966 | } |
| 1967 | |
| 1968 | r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); |
| 1969 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); |
| 1970 | radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH)); |
| 1971 | } |
| 1972 | |
Vadim Girlin | 4acf71f | 2012-06-11 13:11:47 +0400 | [diff] [blame] | 1973 | /* Adjust GPR allocation on R6xx/R7xx */ |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 1974 | bool r600_adjust_gprs(struct r600_context *rctx) |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 1975 | { |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 1976 | unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1977 | unsigned num_vs_gprs, num_es_gprs, num_gs_gprs; |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 1978 | unsigned new_num_ps_gprs = num_ps_gprs; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1979 | unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs; |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 1980 | unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); |
| 1981 | unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1982 | unsigned cur_num_gs_gprs = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); |
| 1983 | unsigned cur_num_es_gprs = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 1984 | unsigned def_num_ps_gprs = rctx->default_ps_gprs; |
| 1985 | unsigned def_num_vs_gprs = rctx->default_vs_gprs; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1986 | unsigned def_num_gs_gprs = 0; |
| 1987 | unsigned def_num_es_gprs = 0; |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 1988 | unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs; |
| 1989 | /* hardware will reserve twice num_clause_temp_gprs */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1990 | unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2; |
| 1991 | unsigned tmp, tmp2; |
| 1992 | |
| 1993 | if (rctx->gs_shader) { |
| 1994 | num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr; |
| 1995 | num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr; |
| 1996 | num_vs_gprs = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr; |
| 1997 | } else { |
| 1998 | num_es_gprs = 0; |
| 1999 | num_gs_gprs = 0; |
| 2000 | num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr; |
| 2001 | } |
| 2002 | new_num_vs_gprs = num_vs_gprs; |
| 2003 | new_num_es_gprs = num_es_gprs; |
| 2004 | new_num_gs_gprs = num_gs_gprs; |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2005 | |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2006 | /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2007 | if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs || |
| 2008 | new_num_es_gprs > cur_num_es_gprs || new_num_gs_gprs > cur_num_gs_gprs) { |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2009 | /* try to use switch back to default */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2010 | if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs || |
| 2011 | new_num_gs_gprs > def_num_gs_gprs || new_num_es_gprs > def_num_es_gprs) { |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2012 | /* always privilege vs stage so that at worst we have the |
| 2013 | * pixel stage producing wrong output (not the vertex |
| 2014 | * stage) */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2015 | new_num_ps_gprs = max_gprs - ((new_num_vs_gprs - new_num_es_gprs - new_num_gs_gprs) + def_num_clause_temp_gprs * 2); |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2016 | new_num_vs_gprs = num_vs_gprs; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2017 | new_num_gs_gprs = num_gs_gprs; |
| 2018 | new_num_es_gprs = num_es_gprs; |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2019 | } else { |
| 2020 | new_num_ps_gprs = def_num_ps_gprs; |
| 2021 | new_num_vs_gprs = def_num_vs_gprs; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2022 | new_num_es_gprs = def_num_es_gprs; |
| 2023 | new_num_gs_gprs = def_num_gs_gprs; |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2024 | } |
| 2025 | } else { |
| 2026 | return true; |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2027 | } |
| 2028 | |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2029 | /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <= |
| 2030 | * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup |
| 2031 | * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS |
| 2032 | * it will lockup. So in this case just discard the draw command |
| 2033 | * and don't change the current gprs repartitions. |
| 2034 | */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2035 | if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs || |
| 2036 | num_gs_gprs > new_num_gs_gprs || num_es_gprs > new_num_es_gprs) { |
| 2037 | R600_ERR("shaders require too many register (%d + %d + %d + %d) " |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2038 | "for a combined maximum of %d\n", |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2039 | num_ps_gprs, num_vs_gprs, num_es_gprs, num_gs_gprs, max_gprs); |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2040 | return false; |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2041 | } |
| 2042 | |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2043 | /* in some case we endup recomputing the current value */ |
| 2044 | tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) | |
| 2045 | S_008C04_NUM_VS_GPRS(new_num_vs_gprs) | |
| 2046 | S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2047 | |
| 2048 | tmp2 = S_008C08_NUM_ES_GPRS(new_num_es_gprs) | |
| 2049 | S_008C08_NUM_GS_GPRS(new_num_gs_gprs); |
| 2050 | if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) { |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 2051 | rctx->config_state.sq_gpr_resource_mgmt_1 = tmp; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2052 | rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2; |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 2053 | rctx->config_state.atom.dirty = true; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2054 | rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE; |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 2055 | } |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2056 | return true; |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2057 | } |
| 2058 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2059 | void r600_init_atom_start_cs(struct r600_context *rctx) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2060 | { |
| 2061 | int ps_prio; |
| 2062 | int vs_prio; |
| 2063 | int gs_prio; |
| 2064 | int es_prio; |
| 2065 | int num_ps_gprs; |
| 2066 | int num_vs_gprs; |
| 2067 | int num_gs_gprs; |
| 2068 | int num_es_gprs; |
| 2069 | int num_temp_gprs; |
| 2070 | int num_ps_threads; |
| 2071 | int num_vs_threads; |
| 2072 | int num_gs_threads; |
| 2073 | int num_es_threads; |
| 2074 | int num_ps_stack_entries; |
| 2075 | int num_vs_stack_entries; |
| 2076 | int num_gs_stack_entries; |
| 2077 | int num_es_stack_entries; |
| 2078 | enum radeon_family family; |
Marek Olšák | e363dd5 | 2012-03-05 16:20:05 +0100 | [diff] [blame] | 2079 | struct r600_command_buffer *cb = &rctx->start_cs_cmd; |
Marek Olšák | d522021 | 2014-07-31 02:33:12 +0200 | [diff] [blame] | 2080 | uint32_t tmp, i; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2081 | |
Marek Olšák | d8ea646 | 2012-10-05 00:20:27 +0200 | [diff] [blame] | 2082 | r600_init_command_buffer(cb, 256); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2083 | |
| 2084 | /* R6xx requires this packet at the start of each command buffer */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2085 | if (rctx->b.chip_class == R600) { |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2086 | r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); |
| 2087 | r600_store_value(cb, 0); |
| 2088 | } |
| 2089 | /* All asics require this one */ |
| 2090 | r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); |
| 2091 | r600_store_value(cb, 0x80000000); |
| 2092 | r600_store_value(cb, 0x80000000); |
| 2093 | |
Marek Olšák | ae25b93 | 2012-10-07 15:38:32 +0200 | [diff] [blame] | 2094 | /* We're setting config registers here. */ |
| 2095 | r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); |
| 2096 | r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); |
| 2097 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2098 | family = rctx->b.family; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2099 | ps_prio = 0; |
| 2100 | vs_prio = 1; |
| 2101 | gs_prio = 2; |
| 2102 | es_prio = 3; |
| 2103 | switch (family) { |
| 2104 | case CHIP_R600: |
| 2105 | num_ps_gprs = 192; |
| 2106 | num_vs_gprs = 56; |
| 2107 | num_temp_gprs = 4; |
| 2108 | num_gs_gprs = 0; |
| 2109 | num_es_gprs = 0; |
| 2110 | num_ps_threads = 136; |
| 2111 | num_vs_threads = 48; |
| 2112 | num_gs_threads = 4; |
| 2113 | num_es_threads = 4; |
| 2114 | num_ps_stack_entries = 128; |
| 2115 | num_vs_stack_entries = 128; |
| 2116 | num_gs_stack_entries = 0; |
| 2117 | num_es_stack_entries = 0; |
| 2118 | break; |
| 2119 | case CHIP_RV630: |
| 2120 | case CHIP_RV635: |
| 2121 | num_ps_gprs = 84; |
| 2122 | num_vs_gprs = 36; |
| 2123 | num_temp_gprs = 4; |
| 2124 | num_gs_gprs = 0; |
| 2125 | num_es_gprs = 0; |
| 2126 | num_ps_threads = 144; |
| 2127 | num_vs_threads = 40; |
| 2128 | num_gs_threads = 4; |
| 2129 | num_es_threads = 4; |
| 2130 | num_ps_stack_entries = 40; |
| 2131 | num_vs_stack_entries = 40; |
| 2132 | num_gs_stack_entries = 32; |
| 2133 | num_es_stack_entries = 16; |
| 2134 | break; |
| 2135 | case CHIP_RV610: |
| 2136 | case CHIP_RV620: |
| 2137 | case CHIP_RS780: |
| 2138 | case CHIP_RS880: |
| 2139 | default: |
| 2140 | num_ps_gprs = 84; |
| 2141 | num_vs_gprs = 36; |
| 2142 | num_temp_gprs = 4; |
| 2143 | num_gs_gprs = 0; |
| 2144 | num_es_gprs = 0; |
| 2145 | num_ps_threads = 136; |
| 2146 | num_vs_threads = 48; |
| 2147 | num_gs_threads = 4; |
| 2148 | num_es_threads = 4; |
| 2149 | num_ps_stack_entries = 40; |
| 2150 | num_vs_stack_entries = 40; |
| 2151 | num_gs_stack_entries = 32; |
| 2152 | num_es_stack_entries = 16; |
| 2153 | break; |
| 2154 | case CHIP_RV670: |
| 2155 | num_ps_gprs = 144; |
| 2156 | num_vs_gprs = 40; |
| 2157 | num_temp_gprs = 4; |
| 2158 | num_gs_gprs = 0; |
| 2159 | num_es_gprs = 0; |
| 2160 | num_ps_threads = 136; |
| 2161 | num_vs_threads = 48; |
| 2162 | num_gs_threads = 4; |
| 2163 | num_es_threads = 4; |
| 2164 | num_ps_stack_entries = 40; |
| 2165 | num_vs_stack_entries = 40; |
| 2166 | num_gs_stack_entries = 32; |
| 2167 | num_es_stack_entries = 16; |
| 2168 | break; |
| 2169 | case CHIP_RV770: |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2170 | num_ps_gprs = 130; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2171 | num_vs_gprs = 56; |
| 2172 | num_temp_gprs = 4; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2173 | num_gs_gprs = 31; |
| 2174 | num_es_gprs = 31; |
| 2175 | num_ps_threads = 180; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2176 | num_vs_threads = 60; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2177 | num_gs_threads = 4; |
| 2178 | num_es_threads = 4; |
| 2179 | num_ps_stack_entries = 128; |
| 2180 | num_vs_stack_entries = 128; |
| 2181 | num_gs_stack_entries = 128; |
| 2182 | num_es_stack_entries = 128; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2183 | break; |
| 2184 | case CHIP_RV730: |
| 2185 | case CHIP_RV740: |
| 2186 | num_ps_gprs = 84; |
| 2187 | num_vs_gprs = 36; |
| 2188 | num_temp_gprs = 4; |
| 2189 | num_gs_gprs = 0; |
| 2190 | num_es_gprs = 0; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2191 | num_ps_threads = 180; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2192 | num_vs_threads = 60; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2193 | num_gs_threads = 4; |
| 2194 | num_es_threads = 4; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2195 | num_ps_stack_entries = 128; |
| 2196 | num_vs_stack_entries = 128; |
| 2197 | num_gs_stack_entries = 0; |
| 2198 | num_es_stack_entries = 0; |
| 2199 | break; |
| 2200 | case CHIP_RV710: |
| 2201 | num_ps_gprs = 192; |
| 2202 | num_vs_gprs = 56; |
| 2203 | num_temp_gprs = 4; |
| 2204 | num_gs_gprs = 0; |
| 2205 | num_es_gprs = 0; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2206 | num_ps_threads = 136; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2207 | num_vs_threads = 48; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2208 | num_gs_threads = 4; |
| 2209 | num_es_threads = 4; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2210 | num_ps_stack_entries = 128; |
| 2211 | num_vs_stack_entries = 128; |
| 2212 | num_gs_stack_entries = 0; |
| 2213 | num_es_stack_entries = 0; |
| 2214 | break; |
| 2215 | } |
| 2216 | |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2217 | rctx->default_ps_gprs = num_ps_gprs; |
| 2218 | rctx->default_vs_gprs = num_vs_gprs; |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2219 | rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2220 | |
| 2221 | /* SQ_CONFIG */ |
| 2222 | tmp = 0; |
| 2223 | switch (family) { |
| 2224 | case CHIP_RV610: |
| 2225 | case CHIP_RV620: |
| 2226 | case CHIP_RS780: |
| 2227 | case CHIP_RS880: |
| 2228 | case CHIP_RV710: |
| 2229 | break; |
| 2230 | default: |
| 2231 | tmp |= S_008C00_VC_ENABLE(1); |
| 2232 | break; |
| 2233 | } |
Jerome Glisse | 153105c | 2010-09-30 10:43:26 -0400 | [diff] [blame] | 2234 | tmp |= S_008C00_DX9_CONSTS(0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2235 | tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); |
| 2236 | tmp |= S_008C00_PS_PRIO(ps_prio); |
| 2237 | tmp |= S_008C00_VS_PRIO(vs_prio); |
| 2238 | tmp |= S_008C00_GS_PRIO(gs_prio); |
| 2239 | tmp |= S_008C00_ES_PRIO(es_prio); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2240 | r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2241 | |
| 2242 | /* SQ_GPR_RESOURCE_MGMT_2 */ |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2243 | tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); |
Mathias Fröhlich | e252944 | 2011-06-08 17:33:57 +0200 | [diff] [blame] | 2244 | tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2245 | r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); |
| 2246 | r600_store_value(cb, tmp); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2247 | |
| 2248 | /* SQ_THREAD_RESOURCE_MGMT */ |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2249 | tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2250 | tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); |
| 2251 | tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); |
| 2252 | tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2253 | r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2254 | |
| 2255 | /* SQ_STACK_RESOURCE_MGMT_1 */ |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2256 | tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2257 | tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2258 | r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2259 | |
| 2260 | /* SQ_STACK_RESOURCE_MGMT_2 */ |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2261 | tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2262 | tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2263 | r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2264 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2265 | r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); |
| 2266 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2267 | if (rctx->b.chip_class >= R700) { |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2268 | r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); |
| 2269 | r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); |
| 2270 | r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); |
| 2271 | r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2272 | } else { |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2273 | r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); |
| 2274 | r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); |
| 2275 | r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); |
| 2276 | r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2277 | } |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2278 | r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); |
| 2279 | r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ |
| 2280 | r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ |
| 2281 | r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ |
| 2282 | r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ |
| 2283 | r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ |
| 2284 | r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ |
| 2285 | r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ |
| 2286 | r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ |
| 2287 | r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2288 | |
Jerome Glisse | 841c1b5 | 2012-09-07 15:00:20 -0400 | [diff] [blame] | 2289 | /* to avoid GPU doing any preloading of constant from random address */ |
Marek Olšák | d522021 | 2014-07-31 02:33:12 +0200 | [diff] [blame] | 2290 | r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16); |
| 2291 | for (i = 0; i < 16; i++) |
| 2292 | r600_store_value(cb, 0); |
| 2293 | |
| 2294 | r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16); |
| 2295 | for (i = 0; i < 16; i++) |
| 2296 | r600_store_value(cb, 0); |
| 2297 | |
| 2298 | r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16); |
| 2299 | for (i = 0; i < 16; i++) |
| 2300 | r600_store_value(cb, 0); |
Jerome Glisse | 841c1b5 | 2012-09-07 15:00:20 -0400 | [diff] [blame] | 2301 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2302 | r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); |
| 2303 | r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ |
| 2304 | r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ |
| 2305 | r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ |
| 2306 | r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ |
| 2307 | r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ |
| 2308 | r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ |
| 2309 | r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ |
| 2310 | r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ |
| 2311 | r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ |
| 2312 | r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ |
| 2313 | r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ |
| 2314 | r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ |
| 2315 | r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ |
Marek Olšák | 0569f13 | 2012-01-29 07:21:03 +0100 | [diff] [blame] | 2316 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2317 | r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); |
| 2318 | r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); |
| 2319 | r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); |
| 2320 | |
Marek Olšák | f549129 | 2014-03-09 22:12:26 +0100 | [diff] [blame] | 2321 | r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2322 | r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ |
| 2323 | r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ |
| 2324 | |
| 2325 | r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); |
Marek Olšák | 182fd4c | 2012-02-02 08:27:01 +0100 | [diff] [blame] | 2326 | |
Marek Olšák | 182fd4c | 2012-02-02 08:27:01 +0100 | [diff] [blame] | 2327 | r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2328 | |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 2329 | r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2330 | |
| 2331 | r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3); |
| 2332 | r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */ |
| 2333 | r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ |
| 2334 | r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ |
| 2335 | |
Alex Deucher | a991411 | 2013-03-19 14:25:32 -0400 | [diff] [blame] | 2336 | r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3); |
| 2337 | r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */ |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2338 | r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ |
| 2339 | r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ |
| 2340 | |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2341 | r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); |
| 2342 | r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0); |
| 2343 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2344 | r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2345 | r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */ |
| 2346 | r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */ |
| 2347 | r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */ |
| 2348 | r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */ |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2349 | |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 2350 | r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16); |
| 2351 | for (tmp = 0; tmp < 16; tmp++) { |
| 2352 | r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ |
| 2353 | r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ |
| 2354 | } |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2355 | |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2356 | r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 2357 | r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2358 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2359 | if (rctx->b.chip_class >= R700) { |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2360 | r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); |
| 2361 | } |
| 2362 | |
| 2363 | r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4); |
| 2364 | r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */ |
| 2365 | r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */ |
| 2366 | r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */ |
| 2367 | r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */ |
| 2368 | |
Marek Olšák | c7eaf274 | 2012-03-08 11:15:32 +0100 | [diff] [blame] | 2369 | r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); |
| 2370 | r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ |
| 2371 | r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ |
Marek Olšák | ca78a47 | 2012-02-26 14:05:35 +0100 | [diff] [blame] | 2372 | |
| 2373 | r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); |
| 2374 | r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ |
| 2375 | r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ |
| 2376 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2377 | r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2378 | r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */ |
| 2379 | r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2380 | r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */ |
| 2381 | r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */ |
| 2382 | r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */ |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2383 | |
Marek Olšák | 91107a3 | 2012-10-29 13:18:03 +0100 | [diff] [blame] | 2384 | r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0); |
| 2385 | |
| 2386 | r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); |
Marek Olšák | 30bcc55 | 2012-10-05 05:50:30 +0200 | [diff] [blame] | 2387 | r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ |
| 2388 | r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ |
| 2389 | |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2390 | r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2391 | |
Marek Olšák | 3a3b1bf | 2014-04-20 18:17:51 +0200 | [diff] [blame] | 2392 | if (rctx->b.chip_class == R700) |
| 2393 | r600_store_context_reg(cb, R_028350_SX_MISC, 0); |
Marek Olšák | bba39d8 | 2013-11-28 15:09:35 +0100 | [diff] [blame] | 2394 | if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout) |
Marek Olšák | 6187503 | 2012-02-27 13:55:27 +0100 | [diff] [blame] | 2395 | r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); |
Marek Olšák | 3a3b1bf | 2014-04-20 18:17:51 +0200 | [diff] [blame] | 2396 | |
Marek Olšák | 96ef4dd | 2012-02-27 14:34:52 +0100 | [diff] [blame] | 2397 | r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); |
Marek Olšák | bba39d8 | 2013-11-28 15:09:35 +0100 | [diff] [blame] | 2398 | if (rctx->screen->b.has_streamout) { |
Jerome Glisse | b7b5a77 | 2012-07-23 11:26:24 -0400 | [diff] [blame] | 2399 | r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); |
| 2400 | } |
Marek Olšák | 6187503 | 2012-02-27 13:55:27 +0100 | [diff] [blame] | 2401 | |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2402 | r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF); |
| 2403 | r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2404 | r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2405 | } |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2406 | |
Marek Olšák | 167263e | 2013-03-01 18:42:52 +0100 | [diff] [blame] | 2407 | void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2408 | { |
Marek Olšák | e4340c1 | 2012-01-29 23:25:42 +0100 | [diff] [blame] | 2409 | struct r600_context *rctx = (struct r600_context *)ctx; |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2410 | struct r600_command_buffer *cb = &shader->command_buffer; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2411 | struct r600_shader *rshader = &shader->shader; |
| 2412 | unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; |
| 2413 | int pos_index = -1, face_index = -1; |
Alex Deucher | 46ce257 | 2012-01-17 18:44:47 -0500 | [diff] [blame] | 2414 | unsigned tmp, sid, ufi = 0; |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2415 | int need_linear = 0; |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2416 | unsigned z_export = 0, stencil_export = 0; |
Marek Olšák | 9a683d1 | 2012-10-05 16:51:41 +0200 | [diff] [blame] | 2417 | unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2418 | |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2419 | if (!cb->buf) { |
| 2420 | r600_init_command_buffer(cb, 64); |
| 2421 | } else { |
| 2422 | cb->num_dw = 0; |
| 2423 | } |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2424 | |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2425 | r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2426 | for (i = 0; i < rshader->ninput; i++) { |
| 2427 | if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) |
| 2428 | pos_index = i; |
| 2429 | if (rshader->input[i].name == TGSI_SEMANTIC_FACE) |
| 2430 | face_index = i; |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2431 | |
| 2432 | sid = rshader->input[i].spi_sid; |
| 2433 | |
| 2434 | tmp = S_028644_SEMANTIC(sid); |
| 2435 | |
Vadim Girlin | 1a9d2b7 | 2012-01-24 23:32:50 +0400 | [diff] [blame] | 2436 | if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || |
| 2437 | rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || |
| 2438 | (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && |
| 2439 | rctx->rasterizer && rctx->rasterizer->flatshade)) |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2440 | tmp |= S_028644_FLAT_SHADE(1); |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2441 | |
| 2442 | if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && |
Marek Olšák | 9a683d1 | 2012-10-05 16:51:41 +0200 | [diff] [blame] | 2443 | sprite_coord_enable & (1 << rshader->input[i].sid)) { |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2444 | tmp |= S_028644_PT_SPRITE_TEX(1); |
| 2445 | } |
| 2446 | |
| 2447 | if (rshader->input[i].centroid) |
| 2448 | tmp |= S_028644_SEL_CENTROID(1); |
| 2449 | |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2450 | if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { |
| 2451 | need_linear = 1; |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2452 | tmp |= S_028644_SEL_LINEAR(1); |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2453 | } |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2454 | |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2455 | r600_store_value(cb, tmp); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2456 | } |
| 2457 | |
Jerome Glisse | 974b482 | 2013-02-08 16:02:32 -0500 | [diff] [blame] | 2458 | db_shader_control = 0; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2459 | for (i = 0; i < rshader->noutput; i++) { |
| 2460 | if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2461 | z_export = 1; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2462 | if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2463 | stencil_export = 1; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2464 | } |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2465 | db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export); |
| 2466 | db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2467 | if (rshader->uses_kill) |
| 2468 | db_shader_control |= S_02880C_KILL_ENABLE(1); |
| 2469 | |
| 2470 | exports_ps = 0; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2471 | for (i = 0; i < rshader->noutput; i++) { |
| 2472 | if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2473 | rshader->output[i].name == TGSI_SEMANTIC_STENCIL) { |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2474 | exports_ps |= 1; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2475 | } |
| 2476 | } |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2477 | num_cout = rshader->nr_ps_color_exports; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2478 | exports_ps |= S_028854_EXPORT_COLORS(num_cout); |
| 2479 | if (!exports_ps) { |
| 2480 | /* always at least export 1 component per pixel */ |
| 2481 | exports_ps = 2; |
| 2482 | } |
| 2483 | |
Marek Olšák | 4fe7441 | 2012-07-07 09:01:38 +0200 | [diff] [blame] | 2484 | shader->nr_ps_color_outputs = num_cout; |
Dave Airlie | d1cc87c | 2012-03-24 13:37:16 +0000 | [diff] [blame] | 2485 | |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2486 | spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2487 | S_0286CC_PERSP_GRADIENT_ENA(1)| |
| 2488 | S_0286CC_LINEAR_GRADIENT_ENA(need_linear); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2489 | spi_input_z = 0; |
| 2490 | if (pos_index != -1) { |
| 2491 | spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | |
| 2492 | S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | |
| 2493 | S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | |
| 2494 | S_0286CC_BARYC_SAMPLE_CNTL(1)); |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2495 | spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2496 | } |
| 2497 | |
| 2498 | spi_ps_in_control_1 = 0; |
| 2499 | if (face_index != -1) { |
| 2500 | spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | |
| 2501 | S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); |
| 2502 | } |
| 2503 | |
Alex Deucher | 46ce257 | 2012-01-17 18:44:47 -0500 | [diff] [blame] | 2504 | /* HW bug in original R600 */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2505 | if (rctx->b.family == CHIP_R600) |
Alex Deucher | 46ce257 | 2012-01-17 18:44:47 -0500 | [diff] [blame] | 2506 | ufi = 1; |
| 2507 | |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2508 | r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2); |
| 2509 | r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */ |
| 2510 | r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */ |
| 2511 | |
| 2512 | r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z); |
| 2513 | |
| 2514 | r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2); |
| 2515 | r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/ |
| 2516 | S_028850_NUM_GPRS(rshader->bc.ngpr) | |
| 2517 | S_028850_STACK_SIZE(rshader->bc.nstack) | |
| 2518 | S_028850_UNCACHED_FIRST_INST(ufi)); |
| 2519 | r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */ |
| 2520 | |
| 2521 | r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0); |
| 2522 | /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ |
| 2523 | |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2524 | /* only set some bits here, the other bits are set in the dsa state */ |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2525 | shader->db_shader_control = db_shader_control; |
| 2526 | shader->ps_depth_export = z_export | stencil_export; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2527 | |
Marek Olšák | 9a683d1 | 2012-10-05 16:51:41 +0200 | [diff] [blame] | 2528 | shader->sprite_coord_enable = sprite_coord_enable; |
Vadim Girlin | 1a9d2b7 | 2012-01-24 23:32:50 +0400 | [diff] [blame] | 2529 | if (rctx->rasterizer) |
| 2530 | shader->flatshade = rctx->rasterizer->flatshade; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2531 | } |
| 2532 | |
Marek Olšák | 167263e | 2013-03-01 18:42:52 +0100 | [diff] [blame] | 2533 | void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2534 | { |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2535 | struct r600_command_buffer *cb = &shader->command_buffer; |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2536 | struct r600_shader *rshader = &shader->shader; |
Vadim Girlin | 5b27b63 | 2011-11-05 08:48:02 +0400 | [diff] [blame] | 2537 | unsigned spi_vs_out_id[10] = {}; |
| 2538 | unsigned i, tmp, nparams = 0; |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2539 | |
Vadim Girlin | 5b27b63 | 2011-11-05 08:48:02 +0400 | [diff] [blame] | 2540 | for (i = 0; i < rshader->noutput; i++) { |
| 2541 | if (rshader->output[i].spi_sid) { |
| 2542 | tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); |
| 2543 | spi_vs_out_id[nparams / 4] |= tmp; |
| 2544 | nparams++; |
| 2545 | } |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2546 | } |
Vadim Girlin | 5b27b63 | 2011-11-05 08:48:02 +0400 | [diff] [blame] | 2547 | |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2548 | r600_init_command_buffer(cb, 32); |
| 2549 | |
| 2550 | r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10); |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2551 | for (i = 0; i < 10; i++) { |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2552 | r600_store_value(cb, spi_vs_out_id[i]); |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2553 | } |
| 2554 | |
Alex Deucher | dc1c0ca | 2011-07-29 11:29:53 -0400 | [diff] [blame] | 2555 | /* Certain attributes (position, psize, etc.) don't count as params. |
| 2556 | * VS is required to export at least one param and r600_shader_from_tgsi() |
| 2557 | * takes care of adding a dummy export. |
| 2558 | */ |
Alex Deucher | dc1c0ca | 2011-07-29 11:29:53 -0400 | [diff] [blame] | 2559 | if (nparams < 1) |
| 2560 | nparams = 1; |
| 2561 | |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2562 | r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG, |
| 2563 | S_0286C4_VS_EXPORT_COUNT(nparams - 1)); |
| 2564 | r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS, |
| 2565 | S_028868_NUM_GPRS(rshader->bc.ngpr) | |
| 2566 | S_028868_STACK_SIZE(rshader->bc.nstack)); |
Christoph Bumiller | b206f59 | 2014-05-17 01:20:20 +0200 | [diff] [blame] | 2567 | if (rshader->vs_position_window_space) { |
| 2568 | r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, |
| 2569 | S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1)); |
| 2570 | } else { |
| 2571 | r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, |
| 2572 | S_028818_VTX_W0_FMT(1) | |
| 2573 | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | |
| 2574 | S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | |
| 2575 | S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1)); |
| 2576 | |
| 2577 | } |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2578 | r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0); |
| 2579 | /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2580 | |
Marek Olšák | 97acf2c | 2012-01-29 06:31:47 +0100 | [diff] [blame] | 2581 | shader->pa_cl_vs_out_cntl = |
| 2582 | S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | |
| 2583 | S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | |
| 2584 | S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | |
Marek Olšák | e5741f1 | 2014-04-19 17:21:57 +0200 | [diff] [blame] | 2585 | S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) | |
| 2586 | S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) | |
| 2587 | S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) | |
| 2588 | S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport); |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2589 | } |
| 2590 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2591 | void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) |
| 2592 | { |
| 2593 | struct r600_context *rctx = (struct r600_context *)ctx; |
| 2594 | struct r600_command_buffer *cb = &shader->command_buffer; |
| 2595 | struct r600_shader *rshader = &shader->shader; |
| 2596 | struct r600_shader *cp_shader = &shader->gs_copy_shader->shader; |
| 2597 | unsigned gsvs_itemsize = |
| 2598 | (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2; |
| 2599 | |
| 2600 | r600_init_command_buffer(cb, 64); |
| 2601 | |
| 2602 | /* VGT_GS_MODE is written by r600_emit_shader_stages */ |
| 2603 | r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1); |
| 2604 | |
| 2605 | if (rctx->b.chip_class >= R700) { |
| 2606 | r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT, |
| 2607 | S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices)); |
| 2608 | } |
| 2609 | r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE, |
| 2610 | r600_conv_prim_to_gs_out(rshader->gs_output_prim)); |
| 2611 | |
| 2612 | r600_store_context_reg_seq(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, 4); |
| 2613 | r600_store_value(cb, cp_shader->ring_item_size >> 2); |
| 2614 | r600_store_value(cb, 0); |
| 2615 | r600_store_value(cb, 0); |
| 2616 | r600_store_value(cb, 0); |
| 2617 | |
| 2618 | r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, |
| 2619 | (rshader->ring_item_size) >> 2); |
| 2620 | |
| 2621 | r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE, |
| 2622 | gsvs_itemsize); |
| 2623 | |
| 2624 | /* FIXME calculate these values somehow ??? */ |
| 2625 | r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2); |
| 2626 | r600_store_value(cb, 0x80); /* GS_PER_ES */ |
| 2627 | r600_store_value(cb, 0x100); /* ES_PER_GS */ |
| 2628 | r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1); |
| 2629 | r600_store_value(cb, 0x2); /* GS_PER_VS */ |
| 2630 | |
| 2631 | r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS, |
| 2632 | S_02887C_NUM_GPRS(rshader->bc.ngpr) | |
| 2633 | S_02887C_STACK_SIZE(rshader->bc.nstack)); |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 2634 | r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2635 | /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ |
| 2636 | } |
| 2637 | |
| 2638 | void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) |
| 2639 | { |
| 2640 | struct r600_command_buffer *cb = &shader->command_buffer; |
| 2641 | struct r600_shader *rshader = &shader->shader; |
| 2642 | |
| 2643 | r600_init_command_buffer(cb, 32); |
| 2644 | |
| 2645 | r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES, |
| 2646 | S_028890_NUM_GPRS(rshader->bc.ngpr) | |
| 2647 | S_028890_STACK_SIZE(rshader->bc.nstack)); |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 2648 | r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2649 | /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ |
| 2650 | } |
| 2651 | |
| 2652 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2653 | void *r600_create_resolve_blend(struct r600_context *rctx) |
| 2654 | { |
| 2655 | struct pipe_blend_state blend; |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 2656 | unsigned i; |
| 2657 | |
| 2658 | memset(&blend, 0, sizeof(blend)); |
| 2659 | blend.independent_blend_enable = true; |
| 2660 | for (i = 0; i < 2; i++) { |
| 2661 | blend.rt[i].colormask = 0xf; |
| 2662 | blend.rt[i].blend_enable = 1; |
| 2663 | blend.rt[i].rgb_func = PIPE_BLEND_ADD; |
| 2664 | blend.rt[i].alpha_func = PIPE_BLEND_ADD; |
| 2665 | blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO; |
| 2666 | blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO; |
| 2667 | blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO; |
| 2668 | blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO; |
| 2669 | } |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2670 | return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 2671 | } |
| 2672 | |
| 2673 | void *r700_create_resolve_blend(struct r600_context *rctx) |
| 2674 | { |
| 2675 | struct pipe_blend_state blend; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2676 | |
| 2677 | memset(&blend, 0, sizeof(blend)); |
| 2678 | blend.independent_blend_enable = true; |
| 2679 | blend.rt[0].colormask = 0xf; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2680 | return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2681 | } |
| 2682 | |
| 2683 | void *r600_create_decompress_blend(struct r600_context *rctx) |
| 2684 | { |
| 2685 | struct pipe_blend_state blend; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2686 | |
| 2687 | memset(&blend, 0, sizeof(blend)); |
| 2688 | blend.independent_blend_enable = true; |
| 2689 | blend.rt[0].colormask = 0xf; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2690 | return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2691 | } |
| 2692 | |
Marek Olšák | e4340c1 | 2012-01-29 23:25:42 +0100 | [diff] [blame] | 2693 | void *r600_create_db_flush_dsa(struct r600_context *rctx) |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2694 | { |
| 2695 | struct pipe_depth_stencil_alpha_state dsa; |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2696 | boolean quirk = false; |
| 2697 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2698 | if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 || |
| 2699 | rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635) |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2700 | quirk = true; |
| 2701 | |
| 2702 | memset(&dsa, 0, sizeof(dsa)); |
| 2703 | |
| 2704 | if (quirk) { |
| 2705 | dsa.depth.enabled = 1; |
| 2706 | dsa.depth.func = PIPE_FUNC_LEQUAL; |
| 2707 | dsa.stencil[0].enabled = 1; |
| 2708 | dsa.stencil[0].func = PIPE_FUNC_ALWAYS; |
| 2709 | dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; |
| 2710 | dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; |
| 2711 | dsa.stencil[0].writemask = 0xff; |
| 2712 | } |
| 2713 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2714 | return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa); |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2715 | } |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2716 | |
Marek Olšák | c5584e9 | 2012-10-06 06:05:32 +0200 | [diff] [blame] | 2717 | void r600_update_db_shader_control(struct r600_context * rctx) |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2718 | { |
Grigori Goronzy | 3de7e11 | 2013-10-11 01:23:20 +0200 | [diff] [blame] | 2719 | bool dual_export; |
| 2720 | unsigned db_shader_control; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 2721 | |
Grigori Goronzy | 3de7e11 | 2013-10-11 01:23:20 +0200 | [diff] [blame] | 2722 | if (!rctx->ps_shader) { |
| 2723 | return; |
| 2724 | } |
| 2725 | |
| 2726 | dual_export = rctx->framebuffer.export_16bpc && |
| 2727 | !rctx->ps_shader->current->ps_depth_export; |
| 2728 | |
| 2729 | db_shader_control = rctx->ps_shader->current->db_shader_control | |
| 2730 | S_02880C_DUAL_EXPORT_ENABLE(dual_export); |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2731 | |
Jerome Glisse | 974b482 | 2013-02-08 16:02:32 -0500 | [diff] [blame] | 2732 | /* When alpha test is enabled we can't trust the hw to make the proper |
| 2733 | * decision on the order in which ztest should be run related to fragment |
| 2734 | * shader execution. |
| 2735 | * |
| 2736 | * If alpha test is enabled perform z test after fragment. RE_Z (early |
| 2737 | * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx |
| 2738 | */ |
| 2739 | if (rctx->alphatest_state.sx_alpha_test_control) { |
| 2740 | db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z); |
| 2741 | } else { |
| 2742 | db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); |
| 2743 | } |
| 2744 | |
Marek Olšák | c5584e9 | 2012-10-06 06:05:32 +0200 | [diff] [blame] | 2745 | if (db_shader_control != rctx->db_misc_state.db_shader_control) { |
| 2746 | rctx->db_misc_state.db_shader_control = db_shader_control; |
| 2747 | rctx->db_misc_state.atom.dirty = true; |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2748 | } |
| 2749 | } |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2750 | |
| 2751 | static INLINE unsigned r600_array_mode(unsigned mode) |
| 2752 | { |
| 2753 | switch (mode) { |
| 2754 | case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED; |
| 2755 | break; |
| 2756 | case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1; |
| 2757 | break; |
| 2758 | case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1; |
| 2759 | default: |
| 2760 | case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL; |
| 2761 | } |
| 2762 | } |
| 2763 | |
| 2764 | static boolean r600_dma_copy_tile(struct r600_context *rctx, |
| 2765 | struct pipe_resource *dst, |
| 2766 | unsigned dst_level, |
| 2767 | unsigned dst_x, |
| 2768 | unsigned dst_y, |
| 2769 | unsigned dst_z, |
| 2770 | struct pipe_resource *src, |
| 2771 | unsigned src_level, |
| 2772 | unsigned src_x, |
| 2773 | unsigned src_y, |
| 2774 | unsigned src_z, |
| 2775 | unsigned copy_height, |
| 2776 | unsigned pitch, |
| 2777 | unsigned bpp) |
| 2778 | { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2779 | struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2780 | struct r600_texture *rsrc = (struct r600_texture*)src; |
| 2781 | struct r600_texture *rdst = (struct r600_texture*)dst; |
| 2782 | unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; |
| 2783 | unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode; |
Jerome Glisse | e1598cb | 2013-01-28 19:07:10 -0500 | [diff] [blame] | 2784 | uint64_t base, addr; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2785 | |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2786 | dst_mode = rdst->surface.level[dst_level].mode; |
| 2787 | src_mode = rsrc->surface.level[src_level].mode; |
| 2788 | /* downcast linear aligned to linear to simplify test */ |
| 2789 | src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; |
| 2790 | dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; |
| 2791 | assert(dst_mode != src_mode); |
| 2792 | |
| 2793 | y = 0; |
| 2794 | lbpp = util_logbase2(bpp); |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2795 | pitch_tile_max = ((pitch / bpp) / 8) - 1; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2796 | |
| 2797 | if (dst_mode == RADEON_SURF_MODE_LINEAR) { |
| 2798 | /* T2L */ |
| 2799 | array_mode = r600_array_mode(src_mode); |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2800 | slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8); |
Jerome Glisse | 681707a | 2013-02-06 13:54:02 -0500 | [diff] [blame] | 2801 | slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2802 | /* linear height must be the same as the slice tile max height, it's ok even |
| 2803 | * if the linear destination/source have smaller heigh as the size of the |
| 2804 | * dma packet will be using the copy_height which is always smaller or equal |
| 2805 | * to the linear height |
| 2806 | */ |
| 2807 | height = rsrc->surface.level[src_level].npix_y; |
| 2808 | detile = 1; |
| 2809 | x = src_x; |
| 2810 | y = src_y; |
| 2811 | z = src_z; |
| 2812 | base = rsrc->surface.level[src_level].offset; |
| 2813 | addr = rdst->surface.level[dst_level].offset; |
| 2814 | addr += rdst->surface.level[dst_level].slice_size * dst_z; |
| 2815 | addr += dst_y * pitch + dst_x * bpp; |
| 2816 | } else { |
| 2817 | /* L2T */ |
| 2818 | array_mode = r600_array_mode(dst_mode); |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2819 | slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8); |
Jerome Glisse | 681707a | 2013-02-06 13:54:02 -0500 | [diff] [blame] | 2820 | slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2821 | /* linear height must be the same as the slice tile max height, it's ok even |
| 2822 | * if the linear destination/source have smaller heigh as the size of the |
| 2823 | * dma packet will be using the copy_height which is always smaller or equal |
| 2824 | * to the linear height |
| 2825 | */ |
| 2826 | height = rdst->surface.level[dst_level].npix_y; |
| 2827 | detile = 0; |
| 2828 | x = dst_x; |
| 2829 | y = dst_y; |
| 2830 | z = dst_z; |
| 2831 | base = rdst->surface.level[dst_level].offset; |
| 2832 | addr = rsrc->surface.level[src_level].offset; |
| 2833 | addr += rsrc->surface.level[src_level].slice_size * src_z; |
| 2834 | addr += src_y * pitch + src_x * bpp; |
| 2835 | } |
| 2836 | /* check that we are in dw/base alignment constraint */ |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2837 | if (addr % 4 || base % 256) { |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2838 | return FALSE; |
| 2839 | } |
| 2840 | |
Jerome Glisse | 323a448 | 2013-02-06 15:03:17 -0500 | [diff] [blame] | 2841 | /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number |
| 2842 | * line in the blit. Compute max 8 line we can copy in the size limit |
| 2843 | */ |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2844 | cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8; |
Jerome Glisse | 323a448 | 2013-02-06 15:03:17 -0500 | [diff] [blame] | 2845 | ncopy = (copy_height / cheight) + !!(copy_height % cheight); |
Niels Ole Salscheider | acf55e7 | 2014-03-17 18:48:05 +0100 | [diff] [blame] | 2846 | r600_need_dma_space(&rctx->b, ncopy * 7); |
Jerome Glisse | 323a448 | 2013-02-06 15:03:17 -0500 | [diff] [blame] | 2847 | |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2848 | for (i = 0; i < ncopy; i++) { |
Jerome Glisse | 323a448 | 2013-02-06 15:03:17 -0500 | [diff] [blame] | 2849 | cheight = cheight > copy_height ? copy_height : cheight; |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2850 | size = (cheight * pitch) / 4; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2851 | /* emit reloc before writting cs so that cs is always in consistent state */ |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 2852 | r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ, |
| 2853 | RADEON_PRIO_MIN); |
| 2854 | r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE, |
| 2855 | RADEON_PRIO_MIN); |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2856 | cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size); |
| 2857 | cs->buf[cs->cdw++] = base >> 8; |
| 2858 | cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) | |
| 2859 | (lbpp << 24) | ((height - 1) << 10) | |
| 2860 | pitch_tile_max; |
| 2861 | cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0); |
| 2862 | cs->buf[cs->cdw++] = (x << 3) | (y << 17); |
| 2863 | cs->buf[cs->cdw++] = addr & 0xfffffffc; |
| 2864 | cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff; |
| 2865 | copy_height -= cheight; |
| 2866 | addr += cheight * pitch; |
| 2867 | y += cheight; |
| 2868 | } |
| 2869 | return TRUE; |
| 2870 | } |
| 2871 | |
Marek Olšák | 54690a5 | 2014-03-17 01:19:51 +0100 | [diff] [blame] | 2872 | static void r600_dma_copy(struct pipe_context *ctx, |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2873 | struct pipe_resource *dst, |
| 2874 | unsigned dst_level, |
| 2875 | unsigned dstx, unsigned dsty, unsigned dstz, |
| 2876 | struct pipe_resource *src, |
| 2877 | unsigned src_level, |
| 2878 | const struct pipe_box *src_box) |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2879 | { |
| 2880 | struct r600_context *rctx = (struct r600_context *)ctx; |
| 2881 | struct r600_texture *rsrc = (struct r600_texture*)src; |
| 2882 | struct r600_texture *rdst = (struct r600_texture*)dst; |
| 2883 | unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height; |
| 2884 | unsigned src_w, dst_w; |
Christoph Bumiller | 9974593 | 2013-07-05 20:55:36 +0200 | [diff] [blame] | 2885 | unsigned src_x, src_y; |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2886 | unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2887 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2888 | if (rctx->b.rings.dma.cs == NULL) { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2889 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2890 | } |
Marek Olšák | 171e484 | 2013-11-27 12:43:40 +0100 | [diff] [blame] | 2891 | |
| 2892 | if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2893 | if (dst_x % 4 || src_box->x % 4 || src_box->width % 4) |
| 2894 | goto fallback; |
| 2895 | |
Marek Olšák | 54690a5 | 2014-03-17 01:19:51 +0100 | [diff] [blame] | 2896 | r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width); |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2897 | return; |
Marek Olšák | 171e484 | 2013-11-27 12:43:40 +0100 | [diff] [blame] | 2898 | } |
| 2899 | |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2900 | if (src->format != dst->format || src_box->depth > 1) { |
| 2901 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2902 | } |
| 2903 | |
Christoph Bumiller | 9974593 | 2013-07-05 20:55:36 +0200 | [diff] [blame] | 2904 | src_x = util_format_get_nblocksx(src->format, src_box->x); |
| 2905 | dst_x = util_format_get_nblocksx(src->format, dst_x); |
| 2906 | src_y = util_format_get_nblocksy(src->format, src_box->y); |
| 2907 | dst_y = util_format_get_nblocksy(src->format, dst_y); |
| 2908 | |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2909 | bpp = rdst->surface.bpe; |
| 2910 | dst_pitch = rdst->surface.level[dst_level].pitch_bytes; |
| 2911 | src_pitch = rsrc->surface.level[src_level].pitch_bytes; |
| 2912 | src_w = rsrc->surface.level[src_level].npix_x; |
| 2913 | dst_w = rdst->surface.level[dst_level].npix_x; |
| 2914 | copy_height = src_box->height / rsrc->surface.blk_h; |
| 2915 | |
| 2916 | dst_mode = rdst->surface.level[dst_level].mode; |
| 2917 | src_mode = rsrc->surface.level[src_level].mode; |
| 2918 | /* downcast linear aligned to linear to simplify test */ |
| 2919 | src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; |
| 2920 | dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; |
| 2921 | |
| 2922 | if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) { |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2923 | /* strict requirement on r6xx/r7xx */ |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2924 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2925 | } |
| 2926 | /* lot of constraint on alignment this should capture them all */ |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2927 | if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2928 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2929 | } |
| 2930 | |
| 2931 | if (src_mode == dst_mode) { |
Jerome Glisse | e1598cb | 2013-01-28 19:07:10 -0500 | [diff] [blame] | 2932 | uint64_t dst_offset, src_offset, size; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2933 | |
| 2934 | /* simple dma blit would do NOTE code here assume : |
| 2935 | * src_box.x/y == 0 |
| 2936 | * dst_x/y == 0 |
| 2937 | * dst_pitch == src_pitch |
| 2938 | */ |
| 2939 | src_offset= rsrc->surface.level[src_level].offset; |
| 2940 | src_offset += rsrc->surface.level[src_level].slice_size * src_box->z; |
Christoph Bumiller | 9974593 | 2013-07-05 20:55:36 +0200 | [diff] [blame] | 2941 | src_offset += src_y * src_pitch + src_x * bpp; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2942 | dst_offset = rdst->surface.level[dst_level].offset; |
| 2943 | dst_offset += rdst->surface.level[dst_level].slice_size * dst_z; |
| 2944 | dst_offset += dst_y * dst_pitch + dst_x * bpp; |
| 2945 | size = src_box->height * src_pitch; |
| 2946 | /* must be dw aligned */ |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2947 | if (dst_offset % 4 || src_offset % 4 || size % 4) { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2948 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2949 | } |
Marek Olšák | 54690a5 | 2014-03-17 01:19:51 +0100 | [diff] [blame] | 2950 | r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size); |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2951 | } else { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2952 | if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z, |
Christoph Bumiller | 9974593 | 2013-07-05 20:55:36 +0200 | [diff] [blame] | 2953 | src, src_level, src_x, src_y, src_box->z, |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2954 | copy_height, dst_pitch, bpp)) { |
| 2955 | goto fallback; |
| 2956 | } |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2957 | } |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2958 | return; |
| 2959 | |
| 2960 | fallback: |
| 2961 | ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz, |
| 2962 | src, src_level, src_box); |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2963 | } |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2964 | |
| 2965 | void r600_init_state_functions(struct r600_context *rctx) |
| 2966 | { |
| 2967 | unsigned id = 4; |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 2968 | int i; |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2969 | |
| 2970 | /* !!! |
| 2971 | * To avoid GPU lockup registers must be emited in a specific order |
| 2972 | * (no kidding ...). The order below is important and have been |
| 2973 | * partialy infered from analyzing fglrx command stream. |
| 2974 | * |
| 2975 | * Don't reorder atom without carefully checking the effect (GPU lockup |
| 2976 | * or piglit regression). |
| 2977 | * !!! |
| 2978 | */ |
| 2979 | |
| 2980 | r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0); |
| 2981 | |
| 2982 | /* shader const */ |
| 2983 | r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0); |
| 2984 | r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0); |
| 2985 | r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0); |
| 2986 | |
| 2987 | /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change |
| 2988 | * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map) |
| 2989 | */ |
| 2990 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0); |
| 2991 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0); |
| 2992 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0); |
| 2993 | /* resource */ |
| 2994 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0); |
| 2995 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0); |
| 2996 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0); |
| 2997 | r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0); |
| 2998 | |
| 2999 | r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7); |
| 3000 | |
| 3001 | r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3); |
| 3002 | r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3); |
| 3003 | rctx->sample_mask.sample_mask = ~0; |
| 3004 | |
| 3005 | r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6); |
| 3006 | r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6); |
| 3007 | r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0); |
| 3008 | r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7); |
| 3009 | r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6); |
| 3010 | r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26); |
| 3011 | r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7); |
| 3012 | r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11); |
| 3013 | r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0); |
| 3014 | r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6); |
| 3015 | r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0); |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 3016 | for (i = 0;i < 16; i++) { |
| 3017 | r600_init_atom(rctx, &rctx->scissor[i].atom, id++, r600_emit_scissor_state, 4); |
| 3018 | r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8); |
| 3019 | rctx->scissor[i].idx = i; |
| 3020 | rctx->viewport[i].idx = i; |
| 3021 | } |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3022 | r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3); |
| 3023 | r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4); |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3024 | r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 3025 | rctx->atoms[id++] = &rctx->b.streamout.begin_atom; |
Marek Olšák | f549129 | 2014-03-09 22:12:26 +0100 | [diff] [blame] | 3026 | rctx->atoms[id++] = &rctx->b.streamout.enable_atom; |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3027 | r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23); |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 3028 | r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 3029 | r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0); |
| 3030 | r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0); |
| 3031 | r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0); |
| 3032 | r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0); |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3033 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 3034 | rctx->b.b.create_blend_state = r600_create_blend_state; |
| 3035 | rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state; |
| 3036 | rctx->b.b.create_rasterizer_state = r600_create_rs_state; |
| 3037 | rctx->b.b.create_sampler_state = r600_create_sampler_state; |
| 3038 | rctx->b.b.create_sampler_view = r600_create_sampler_view; |
| 3039 | rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state; |
| 3040 | rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple; |
| 3041 | rctx->b.b.set_scissor_states = r600_set_scissor_states; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 3042 | rctx->b.b.get_sample_position = r600_get_sample_position; |
Marek Olšák | 54690a5 | 2014-03-17 01:19:51 +0100 | [diff] [blame] | 3043 | rctx->b.dma_copy = r600_dma_copy; |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3044 | } |
| 3045 | /* this function must be last */ |