blob: 7ee1a3fa9cf9668e0b99c2e4c9eaafba68d51919 [file] [log] [blame]
Rob Clark6173cc12012-10-27 11:07:34 -05001/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3/*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30#include "pipe/p_defines.h"
31#include "pipe/p_screen.h"
32#include "pipe/p_state.h"
33
34#include "util/u_memory.h"
35#include "util/u_inlines.h"
36#include "util/u_format.h"
37#include "util/u_format_s3tc.h"
38#include "util/u_string.h"
Rob Clark634fb832013-03-25 14:57:24 -040039#include "util/u_debug.h"
Rob Clark6173cc12012-10-27 11:07:34 -050040
41#include "os/os_time.h"
42
43#include <stdio.h>
44#include <errno.h>
45#include <stdlib.h>
46
Rob Clark6173cc12012-10-27 11:07:34 -050047#include "freedreno_screen.h"
48#include "freedreno_resource.h"
49#include "freedreno_fence.h"
Rob Clark646c16a2014-01-07 21:39:13 -050050#include "freedreno_query.h"
Rob Clark6173cc12012-10-27 11:07:34 -050051#include "freedreno_util.h"
52
Emil Velikov458d03a2014-07-28 19:45:09 +010053#include "a2xx/fd2_screen.h"
54#include "a3xx/fd3_screen.h"
Rob Clark61c68b62014-07-31 15:42:55 -040055#include "a4xx/fd4_screen.h"
Rob Clark18c317b2013-05-26 17:13:27 -040056
Rob Clark6173cc12012-10-27 11:07:34 -050057/* XXX this should go away */
58#include "state_tracker/drm_driver.h"
59
Rob Clark634fb832013-03-25 14:57:24 -040060static const struct debug_named_value debug_options[] = {
61 {"msgs", FD_DBG_MSGS, "Print debug messages"},
62 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
Rob Clark9495ee12013-04-24 10:50:51 -040063 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
Rob Clarkef7a5632015-10-15 16:28:17 -040064 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
Rob Clark33193542014-10-22 13:27:35 -040065 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
Rob Clark1a42d4e2013-09-06 18:21:25 -040066 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
Rob Clark33193542014-10-22 13:27:35 -040067 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
Rob Clarka53fe222013-10-31 09:59:49 -040068 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
Rob Clark1b886072014-02-03 11:28:30 -050069 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
Rob Clark62cc0032015-03-18 09:51:27 -040070 {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
Timothy Arceri1de93f92015-06-23 07:53:24 +100071 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
Rob Clark65b2ae52015-07-05 18:23:25 -040072 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
Rob Clarkef7a5632015-10-15 16:28:17 -040073 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
Rob Clark634fb832013-03-25 14:57:24 -040074 DEBUG_NAMED_VALUE_END
75};
76
77DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
78
Rob Clark6173cc12012-10-27 11:07:34 -050079int fd_mesa_debug = 0;
Rob Clark1b886072014-02-03 11:28:30 -050080bool fd_binning_enabled = true;
Rob Clarkfd17db62015-03-08 13:38:51 -040081static bool glsl120 = false;
Rob Clark6173cc12012-10-27 11:07:34 -050082
83static const char *
84fd_screen_get_name(struct pipe_screen *pscreen)
85{
86 static char buffer[128];
87 util_snprintf(buffer, sizeof(buffer), "FD%03d",
88 fd_screen(pscreen)->device_id);
89 return buffer;
90}
91
92static const char *
93fd_screen_get_vendor(struct pipe_screen *pscreen)
94{
95 return "freedreno";
96}
97
Giuseppe Bilotta76039b32015-03-22 07:21:01 +010098static const char *
99fd_screen_get_device_vendor(struct pipe_screen *pscreen)
100{
101 return "Qualcomm";
102}
103
104
Rob Clark6173cc12012-10-27 11:07:34 -0500105static uint64_t
106fd_screen_get_timestamp(struct pipe_screen *pscreen)
107{
108 int64_t cpu_time = os_time_get() * 1000;
109 return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
110}
111
112static void
Rob Clark6173cc12012-10-27 11:07:34 -0500113fd_screen_destroy(struct pipe_screen *pscreen)
114{
Rob Clark38d8b022013-04-22 13:42:55 -0400115 struct fd_screen *screen = fd_screen(pscreen);
116
117 if (screen->pipe)
118 fd_pipe_del(screen->pipe);
119
120 if (screen->dev)
121 fd_device_del(screen->dev);
122
123 free(screen);
Rob Clark6173cc12012-10-27 11:07:34 -0500124}
125
126/*
Rob Clark18c317b2013-05-26 17:13:27 -0400127TODO either move caps to a2xx/a3xx specific code, or maybe have some
128tables for things that differ if the delta is not too much..
Rob Clark6173cc12012-10-27 11:07:34 -0500129 */
130static int
131fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
132{
Rob Clarkf999c132014-05-11 14:15:32 -0400133 struct fd_screen *screen = fd_screen(pscreen);
134
Rob Clark6173cc12012-10-27 11:07:34 -0500135 /* this is probably not totally correct.. but it's a start: */
136 switch (param) {
137 /* Supported features (boolean caps). */
138 case PIPE_CAP_NPOT_TEXTURES:
Ilia Mirkin12d39b42013-10-04 04:32:15 -0400139 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
Rob Clark6173cc12012-10-27 11:07:34 -0500140 case PIPE_CAP_TWO_SIDED_STENCIL:
141 case PIPE_CAP_ANISOTROPIC_FILTER:
142 case PIPE_CAP_POINT_SPRITE:
143 case PIPE_CAP_TEXTURE_SHADOW_MAP:
Rob Clark6173cc12012-10-27 11:07:34 -0500144 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
145 case PIPE_CAP_TEXTURE_SWIZZLE:
Rob Clark6173cc12012-10-27 11:07:34 -0500146 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
147 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
Ilia Mirkinf0ca2672014-10-03 16:23:19 -0400148 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
Rob Clark6173cc12012-10-27 11:07:34 -0500149 case PIPE_CAP_SEAMLESS_CUBE_MAP:
Rob Clark6173cc12012-10-27 11:07:34 -0500150 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
151 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
Rob Clark6173cc12012-10-27 11:07:34 -0500152 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
153 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
154 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
Rob Clark6173cc12012-10-27 11:07:34 -0500155 case PIPE_CAP_USER_CONSTANT_BUFFERS:
Rob Clark28686392014-05-24 10:07:13 -0400156 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
Ilia Mirkinf6b2e8a2014-10-01 23:13:22 -0400157 case PIPE_CAP_VERTEXID_NOBASE:
Rob Clark6173cc12012-10-27 11:07:34 -0500158 return 1;
Rob Clark980f1cf2013-03-25 11:55:18 -0400159
Rob Clark8d27be22014-01-14 13:03:20 -0500160 case PIPE_CAP_SHADER_STENCIL_EXPORT:
Christoph Bumiller8acaf862013-03-15 22:11:31 +0100161 case PIPE_CAP_TGSI_TEXCOORD:
Rob Clark980f1cf2013-03-25 11:55:18 -0400162 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
Rob Clark6f84f642014-05-18 08:02:08 -0400163 case PIPE_CAP_CONDITIONAL_RENDER:
Rob Clark28686392014-05-24 10:07:13 -0400164 case PIPE_CAP_TEXTURE_MULTISAMPLE:
165 case PIPE_CAP_TEXTURE_BARRIER:
Rob Clark5c726722014-09-26 10:35:52 -0400166 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
Ilia Mirkinbe008522014-10-02 03:39:05 -0400167 case PIPE_CAP_START_INSTANCE:
168 case PIPE_CAP_COMPUTE:
Christoph Bumiller8acaf862013-03-15 22:11:31 +0100169 return 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500170
Ilia Mirkine6acf3a2014-09-27 10:50:40 -0400171 case PIPE_CAP_SM3:
Rob Clark720cfb62014-09-09 11:20:40 -0400172 case PIPE_CAP_PRIMITIVE_RESTART:
Rob Clark283bb482014-12-21 11:38:34 -0500173 case PIPE_CAP_TGSI_INSTANCEID:
Ilia Mirkin92fc8f02014-12-02 00:32:57 -0500174 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
Rob Clarkf72fead2015-08-10 20:41:45 -0400175 case PIPE_CAP_INDEP_BLEND_ENABLE:
176 case PIPE_CAP_INDEP_BLEND_FUNC:
Rob Clark500025a2015-08-11 16:47:16 -0400177 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
Ilia Mirkind19a98e2015-08-14 10:49:46 -0400178 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
Rob Clarkdaccbd22014-12-21 11:52:44 -0500179 return is_a3xx(screen) || is_a4xx(screen);
Ilia Mirkinf6b2e8a2014-10-01 23:13:22 -0400180
Rob Clark500025a2015-08-11 16:47:16 -0400181 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
182 /* ignoring first/last_element.. but I guess that should be
183 * easy to add..
184 */
185 return 0;
186 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
187 /* I think 32k on a4xx.. and we could possibly emulate more
188 * by pretending 2d/rect textures and splitting high bits
189 * of index into 2nd dimension..
190 */
191 return 16383;
192
Ilia Mirkinf5c11012015-04-24 21:44:05 -0400193 case PIPE_CAP_DEPTH_CLIP_DISABLE:
Ilia Mirkina5a96112015-08-26 00:11:23 -0400194 case PIPE_CAP_CLIP_HALFZ:
Ilia Mirkinca628082015-08-07 23:11:45 -0400195 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
Ilia Mirkinf27ec592015-03-29 20:04:38 -0400196 return is_a3xx(screen);
197
Ilia Mirkind19a98e2015-08-14 10:49:46 -0400198 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
Ilia Mirkinb4ace132015-08-03 02:13:33 -0400199 case PIPE_CAP_CUBE_MAP_ARRAY:
Ilia Mirkind19a98e2015-08-14 10:49:46 -0400200 return is_a4xx(screen);
201
Rob Clark6173cc12012-10-27 11:07:34 -0500202 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
203 return 256;
204
205 case PIPE_CAP_GLSL_FEATURE_LEVEL:
Rob Clarkfd17db62015-03-08 13:38:51 -0400206 if (glsl120)
207 return 120;
Rob Clarkf72fead2015-08-10 20:41:45 -0400208 return is_ir3(screen) ? 130 : 120;
Rob Clark6173cc12012-10-27 11:07:34 -0500209
210 /* Unsupported features. */
Rob Clark6173cc12012-10-27 11:07:34 -0500211 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
Ilia Mirkinf0ca2672014-10-03 16:23:19 -0400212 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
Rob Clark6173cc12012-10-27 11:07:34 -0500213 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
214 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
215 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
216 case PIPE_CAP_USER_VERTEX_BUFFERS:
217 case PIPE_CAP_USER_INDEX_BUFFERS:
Christoph Bumillerf35e96d2013-03-29 13:02:49 +0100218 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
Christoph Bumiller729abfd2013-04-12 13:42:01 +0200219 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
Ilia Mirkin32b71242014-07-03 11:15:18 -0400220 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
Dave Airlie2fcbec42013-09-21 18:45:43 +1000221 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
222 case PIPE_CAP_TEXTURE_GATHER_SM5:
Ilia Mirkind95df4f2014-04-26 23:44:57 -0400223 case PIPE_CAP_FAKE_SW_MSAA:
Dave Airliebe5276a2014-02-11 13:26:08 +1000224 case PIPE_CAP_TEXTURE_QUERY_LOD:
Ilia Mirkind95df4f2014-04-26 23:44:57 -0400225 case PIPE_CAP_SAMPLE_SHADING:
226 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
Christoph Bumiller4b586a22014-05-17 01:20:19 +0200227 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
Christoph Bumillerbc198f82013-04-05 14:29:36 +0200228 case PIPE_CAP_DRAW_INDIRECT:
Ilia Mirkin8ee74ce2014-08-14 00:04:41 -0400229 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
Tobias Klausmannfd5edee2014-08-17 03:37:19 +0200230 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
Ilia Mirkinc1130952014-08-20 19:45:10 -0400231 case PIPE_CAP_SAMPLER_VIEW_TARGET:
Ilia Mirkin7c211a12015-02-01 09:01:50 -0500232 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
Axel Davyeb1c12d2015-01-17 14:30:17 +0100233 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
Ilia Mirkin069dab72015-02-18 22:36:13 -0500234 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
Marek Olšák79ffc08a2015-04-29 15:44:55 +0200235 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
Marek Olšák26222932015-06-12 14:24:17 +0200236 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
Marek Olšák3b7800e2015-08-10 02:11:48 +0200237 case PIPE_CAP_DEPTH_BOUNDS_TEST:
Ilia Mirkinf46a53f2015-09-11 17:29:49 -0400238 case PIPE_CAP_TGSI_TXQS:
Marek Olšákf3b37e32015-09-27 19:32:07 +0200239 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
Marek Olšákd74e7b62015-09-27 21:02:15 +0200240 case PIPE_CAP_SHAREABLE_SHADERS:
Marek Olšákce9db162015-08-24 01:19:35 +0200241 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
Rob Clark6173cc12012-10-27 11:07:34 -0500242 return 0;
243
Rob Clark546d6c82014-09-26 15:40:35 -0400244 case PIPE_CAP_MAX_VIEWPORTS:
245 return 1;
246
Rob Clark6173cc12012-10-27 11:07:34 -0500247 /* Stream output. */
248 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
Rob Clarkf72fead2015-08-10 20:41:45 -0400249 if (is_ir3(screen))
Rob Clark98a4b112015-07-25 12:53:23 -0400250 return PIPE_MAX_SO_BUFFERS;
251 return 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500252 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
Rob Clarkf72fead2015-08-10 20:41:45 -0400253 if (is_ir3(screen))
Rob Clark98a4b112015-07-25 12:53:23 -0400254 return 1;
255 return 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500256 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
257 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
Rob Clarkf72fead2015-08-10 20:41:45 -0400258 if (is_ir3(screen))
Rob Clarkc7deea52015-07-31 10:54:23 -0400259 return 16 * 4; /* should only be shader out limit? */
Rob Clark6173cc12012-10-27 11:07:34 -0500260 return 0;
261
Grigori Goronzyd34d5fd2014-02-09 22:56:20 +0100262 /* Geometry shader output, unsupported. */
263 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
264 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
Ilia Mirkin746e5262014-06-26 20:01:50 -0400265 case PIPE_CAP_MAX_VERTEX_STREAMS:
Grigori Goronzyd34d5fd2014-02-09 22:56:20 +0100266 return 0;
267
Timothy Arceri89e68062014-08-19 21:09:58 -1000268 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
269 return 2048;
270
Rob Clark6173cc12012-10-27 11:07:34 -0500271 /* Texturing. */
272 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
Rob Clark6173cc12012-10-27 11:07:34 -0500273 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
Rob Clarkcb9e07a2013-08-31 09:14:27 -0400274 return MAX_MIP_LEVELS;
Rob Clark49b8fb92014-09-13 16:14:17 -0400275 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
276 return 11;
277
Rob Clark6173cc12012-10-27 11:07:34 -0500278 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
Rob Clarkf24e9102014-12-12 18:51:36 -0500279 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500280
281 /* Render targets. */
282 case PIPE_CAP_MAX_RENDER_TARGETS:
Ilia Mirkin6f4c1972015-04-01 01:14:39 -0400283 return screen->max_rts;
Ilia Mirkinee6b95c2015-09-13 19:50:45 -0400284 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
285 return is_a3xx(screen) ? 1 : 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500286
Rob Clarkf999c132014-05-11 14:15:32 -0400287 /* Queries. */
Rob Clark6173cc12012-10-27 11:07:34 -0500288 case PIPE_CAP_QUERY_TIME_ELAPSED:
Rob Clark6173cc12012-10-27 11:07:34 -0500289 case PIPE_CAP_QUERY_TIMESTAMP:
290 return 0;
Rob Clarkf999c132014-05-11 14:15:32 -0400291 case PIPE_CAP_OCCLUSION_QUERY:
Rob Clarkf24e9102014-12-12 18:51:36 -0500292 return is_a3xx(screen) || is_a4xx(screen);
Rob Clark6173cc12012-10-27 11:07:34 -0500293
Ilia Mirkinc2f9ad52014-04-09 14:58:53 -0400294 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
Rob Clark6173cc12012-10-27 11:07:34 -0500295 case PIPE_CAP_MIN_TEXEL_OFFSET:
296 return -8;
297
Ilia Mirkinc2f9ad52014-04-09 14:58:53 -0400298 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
Rob Clark6173cc12012-10-27 11:07:34 -0500299 case PIPE_CAP_MAX_TEXEL_OFFSET:
300 return 7;
301
Tom Stellard4e90bc92013-07-09 21:21:39 -0700302 case PIPE_CAP_ENDIANNESS:
303 return PIPE_ENDIAN_LITTLE;
304
Rob Clarkf999c132014-05-11 14:15:32 -0400305 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
Ian Romanick25c14f42014-01-22 14:02:42 -0800306 return 64;
307
Emil Velikove9c43b12014-08-14 19:42:39 +0100308 case PIPE_CAP_VENDOR_ID:
309 return 0x5143;
310 case PIPE_CAP_DEVICE_ID:
311 return 0xFFFFFFFF;
312 case PIPE_CAP_ACCELERATED:
313 return 1;
314 case PIPE_CAP_VIDEO_MEMORY:
315 DBG("FINISHME: The value returned is incorrect\n");
316 return 10;
317 case PIPE_CAP_UMA:
318 return 1;
Rob Clark6173cc12012-10-27 11:07:34 -0500319 }
Rob Clarkf7259942014-09-26 17:56:08 -0400320 debug_printf("unknown param %d\n", param);
321 return 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500322}
323
324static float
325fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
326{
327 switch (param) {
328 case PIPE_CAPF_MAX_LINE_WIDTH:
329 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
330 case PIPE_CAPF_MAX_POINT_WIDTH:
331 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
Ilia Mirkin7fc5da82015-03-17 01:00:38 -0400332 return 4092.0f;
Rob Clark6173cc12012-10-27 11:07:34 -0500333 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
334 return 16.0f;
335 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
Rob Clark204dd73c2014-10-01 07:26:39 -0400336 return 15.0f;
Rob Clark6173cc12012-10-27 11:07:34 -0500337 case PIPE_CAPF_GUARD_BAND_LEFT:
338 case PIPE_CAPF_GUARD_BAND_TOP:
339 case PIPE_CAPF_GUARD_BAND_RIGHT:
340 case PIPE_CAPF_GUARD_BAND_BOTTOM:
341 return 0.0f;
Rob Clark6173cc12012-10-27 11:07:34 -0500342 }
Rob Clarkf7259942014-09-26 17:56:08 -0400343 debug_printf("unknown paramf %d\n", param);
344 return 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500345}
346
347static int
348fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
349 enum pipe_shader_cap param)
350{
Rob Clark4317c4e2013-10-24 17:45:27 -0400351 struct fd_screen *screen = fd_screen(pscreen);
352
Rob Clark6173cc12012-10-27 11:07:34 -0500353 switch(shader)
354 {
355 case PIPE_SHADER_FRAGMENT:
356 case PIPE_SHADER_VERTEX:
357 break;
358 case PIPE_SHADER_COMPUTE:
359 case PIPE_SHADER_GEOMETRY:
360 /* maye we could emulate.. */
361 return 0;
362 default:
363 DBG("unknown shader type %d", shader);
364 return 0;
365 }
366
367 /* this is probably not totally correct.. but it's a start: */
368 switch (param) {
369 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
370 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
371 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
372 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
373 return 16384;
374 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
375 return 8; /* XXX */
376 case PIPE_SHADER_CAP_MAX_INPUTS:
Rob Clark33193542014-10-22 13:27:35 -0400377 case PIPE_SHADER_CAP_MAX_OUTPUTS:
Rob Clark5dcf59e2014-05-14 11:15:26 -0400378 return 16;
Rob Clark6173cc12012-10-27 11:07:34 -0500379 case PIPE_SHADER_CAP_MAX_TEMPS:
Rob Clark4317c4e2013-10-24 17:45:27 -0400380 return 64; /* Max native temporaries. */
Marek Olšák04f2c882014-07-24 20:32:08 +0200381 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
Rob Clark652b8fb2014-10-15 13:08:00 -0400382 /* NOTE: seems to be limit for a3xx is actually 512 but
383 * split between VS and FS. Use lower limit of 256 to
384 * avoid getting into impossible situations:
385 */
Ilia Mirkin1de72df2015-03-31 11:51:00 -0400386 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
Rob Clark6173cc12012-10-27 11:07:34 -0500387 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
Rob Clarkf72fead2015-08-10 20:41:45 -0400388 return is_ir3(screen) ? 16 : 1;
Rob Clark6173cc12012-10-27 11:07:34 -0500389 case PIPE_SHADER_CAP_MAX_PREDS:
390 return 0; /* nothing uses this */
391 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
392 return 1;
393 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
394 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
395 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
396 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
397 return 1;
398 case PIPE_SHADER_CAP_SUBROUTINES:
Rob Clarkf7259942014-09-26 17:56:08 -0400399 case PIPE_SHADER_CAP_DOUBLES:
Ilia Mirkinc85a6862015-02-19 23:30:36 -0500400 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
401 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
Marek Olšák216543e2015-02-28 00:26:31 +0100402 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
Marek Olšákb6ebe7e2015-05-25 19:30:44 +0200403 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
Rob Clark6173cc12012-10-27 11:07:34 -0500404 return 0;
405 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
Rob Clark4ddd4e82013-10-25 11:48:24 -0400406 return 1;
Rob Clark6173cc12012-10-27 11:07:34 -0500407 case PIPE_SHADER_CAP_INTEGERS:
Rob Clarkfd17db62015-03-08 13:38:51 -0400408 if (glsl120)
409 return 0;
Rob Clarkf72fead2015-08-10 20:41:45 -0400410 return is_ir3(screen) ? 1 : 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500411 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
Roland Scheidegger2983c032013-11-26 02:30:41 +0100412 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
Rob Clark6173cc12012-10-27 11:07:34 -0500413 return 16;
414 case PIPE_SHADER_CAP_PREFERRED_IR:
415 return PIPE_SHADER_IR_TGSI;
Marek Olšák814f3142015-10-20 18:26:02 +0200416 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
417 return 32;
Rob Clark6173cc12012-10-27 11:07:34 -0500418 }
Rob Clarkf7259942014-09-26 17:56:08 -0400419 debug_printf("unknown shader param %d\n", param);
Rob Clark6173cc12012-10-27 11:07:34 -0500420 return 0;
421}
422
Rob Clark6173cc12012-10-27 11:07:34 -0500423boolean
424fd_screen_bo_get_handle(struct pipe_screen *pscreen,
425 struct fd_bo *bo,
426 unsigned stride,
427 struct winsys_handle *whandle)
428{
429 whandle->stride = stride;
430
431 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
432 return fd_bo_get_name(bo, &whandle->handle) == 0;
433 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
434 whandle->handle = fd_bo_handle(bo);
435 return TRUE;
Rob Clark18291ee2014-09-16 19:10:23 -0400436 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
437 whandle->handle = fd_bo_dmabuf(bo);
Rob Clarke4c678c2014-09-26 10:35:33 -0400438 return TRUE;
Rob Clark6173cc12012-10-27 11:07:34 -0500439 } else {
440 return FALSE;
441 }
442}
443
444struct fd_bo *
445fd_screen_bo_from_handle(struct pipe_screen *pscreen,
446 struct winsys_handle *whandle,
447 unsigned *out_stride)
448{
449 struct fd_screen *screen = fd_screen(pscreen);
450 struct fd_bo *bo;
451
Rob Clark18291ee2014-09-16 19:10:23 -0400452 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
453 bo = fd_bo_from_name(screen->dev, whandle->handle);
454 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
455 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
456 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
457 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
458 } else {
Christopher James Halse Rogersd5a3a2d2013-11-21 15:11:39 +1100459 DBG("Attempt to import unsupported handle type %d", whandle->type);
460 return NULL;
461 }
462
Rob Clark6173cc12012-10-27 11:07:34 -0500463 if (!bo) {
464 DBG("ref name 0x%08x failed", whandle->handle);
465 return NULL;
466 }
467
468 *out_stride = whandle->stride;
469
470 return bo;
471}
472
473struct pipe_screen *
474fd_screen_create(struct fd_device *dev)
475{
476 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
477 struct pipe_screen *pscreen;
478 uint64_t val;
479
Rob Clark634fb832013-03-25 14:57:24 -0400480 fd_mesa_debug = debug_get_option_fd_mesa_debug();
Rob Clark6173cc12012-10-27 11:07:34 -0500481
Rob Clark1b886072014-02-03 11:28:30 -0500482 if (fd_mesa_debug & FD_DBG_NOBIN)
Rob Clarkc0766522014-01-07 10:55:07 -0500483 fd_binning_enabled = false;
484
Rob Clarkfd17db62015-03-08 13:38:51 -0400485 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
Rob Clarke1896942014-05-14 11:06:21 -0400486
Rob Clark6173cc12012-10-27 11:07:34 -0500487 if (!screen)
488 return NULL;
489
Rob Clark38d8b022013-04-22 13:42:55 -0400490 pscreen = &screen->base;
Rob Clark6173cc12012-10-27 11:07:34 -0500491
492 screen->dev = dev;
Rob Clark5bb41d92015-09-04 11:35:33 -0400493 screen->refcnt = 1;
Rob Clark6173cc12012-10-27 11:07:34 -0500494
495 // maybe this should be in context?
496 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
Rob Clark38d8b022013-04-22 13:42:55 -0400497 if (!screen->pipe) {
498 DBG("could not create 3d pipe");
499 goto fail;
500 }
Rob Clark6173cc12012-10-27 11:07:34 -0500501
Rob Clark38d8b022013-04-22 13:42:55 -0400502 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
503 DBG("could not get GMEM size");
504 goto fail;
505 }
Rob Clark6173cc12012-10-27 11:07:34 -0500506 screen->gmemsize_bytes = val;
507
Rob Clark38d8b022013-04-22 13:42:55 -0400508 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
509 DBG("could not get device-id");
510 goto fail;
511 }
Rob Clark6173cc12012-10-27 11:07:34 -0500512 screen->device_id = val;
513
Rob Clark18c317b2013-05-26 17:13:27 -0400514 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
515 DBG("could not get gpu-id");
516 goto fail;
517 }
518 screen->gpu_id = val;
519
Rob Clarkd48faad2014-06-18 10:24:04 -0400520 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
521 DBG("could not get chip-id");
522 /* older kernels may not have this property: */
523 unsigned core = screen->gpu_id / 100;
524 unsigned major = (screen->gpu_id % 100) / 10;
525 unsigned minor = screen->gpu_id % 10;
526 unsigned patch = 0; /* assume the worst */
527 val = (patch & 0xff) | ((minor & 0xff) << 8) |
528 ((major & 0xff) << 16) | ((core & 0xff) << 24);
529 }
530 screen->chip_id = val;
531
532 DBG("Pipe Info:");
533 DBG(" GPU-id: %d", screen->gpu_id);
534 DBG(" Chip-id: 0x%08x", screen->chip_id);
535 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
536
Rob Clark18c317b2013-05-26 17:13:27 -0400537 /* explicitly checking for GPU revisions that are known to work. This
538 * may be overly conservative for a3xx, where spoofing the gpu_id with
539 * the blob driver seems to generate identical cmdstream dumps. But
540 * on a2xx, there seem to be small differences between the GPU revs
541 * so it is probably better to actually test first on real hardware
542 * before enabling:
543 *
544 * If you have a different adreno version, feel free to add it to one
Rob Clark61c68b62014-07-31 15:42:55 -0400545 * of the cases below and see what happens. And if it works, please
Rob Clark18c317b2013-05-26 17:13:27 -0400546 * send a patch ;-)
547 */
548 switch (screen->gpu_id) {
549 case 220:
550 fd2_screen_init(pscreen);
551 break;
Guillaume Charifi6f5e0c02015-11-06 11:17:25 -0500552 case 305:
Rob Clarkfcc7d632015-05-12 14:46:50 -0400553 case 307:
Rob Clark2855f3f2013-05-26 17:13:44 -0400554 case 320:
Rob Clarka1d80862013-12-07 08:47:10 -0500555 case 330:
Rob Clark2855f3f2013-05-26 17:13:44 -0400556 fd3_screen_init(pscreen);
557 break;
Rob Clark61c68b62014-07-31 15:42:55 -0400558 case 420:
559 fd4_screen_init(pscreen);
560 break;
Rob Clark18c317b2013-05-26 17:13:27 -0400561 default:
562 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
563 goto fail;
564 }
Rob Clark6173cc12012-10-27 11:07:34 -0500565
566 pscreen->destroy = fd_screen_destroy;
567 pscreen->get_param = fd_screen_get_param;
568 pscreen->get_paramf = fd_screen_get_paramf;
569 pscreen->get_shader_param = fd_screen_get_shader_param;
Rob Clark6173cc12012-10-27 11:07:34 -0500570
571 fd_resource_screen_init(pscreen);
Rob Clark646c16a2014-01-07 21:39:13 -0500572 fd_query_screen_init(pscreen);
Rob Clark6173cc12012-10-27 11:07:34 -0500573
574 pscreen->get_name = fd_screen_get_name;
575 pscreen->get_vendor = fd_screen_get_vendor;
Giuseppe Bilotta76039b32015-03-22 07:21:01 +0100576 pscreen->get_device_vendor = fd_screen_get_device_vendor;
Rob Clark6173cc12012-10-27 11:07:34 -0500577
578 pscreen->get_timestamp = fd_screen_get_timestamp;
579
580 pscreen->fence_reference = fd_screen_fence_ref;
Rob Clark6173cc12012-10-27 11:07:34 -0500581 pscreen->fence_finish = fd_screen_fence_finish;
582
583 util_format_s3tc_init();
584
585 return pscreen;
Rob Clark38d8b022013-04-22 13:42:55 -0400586
587fail:
588 fd_screen_destroy(pscreen);
589 return NULL;
Rob Clark6173cc12012-10-27 11:07:34 -0500590}