blob: 87bb438aa219ab0fb41c6e5840e5a6aa0fd87377 [file] [log] [blame]
Stéphane Marchesin25a26062014-09-12 16:18:59 -07001/*
Daniele Castagna7a755de2016-12-16 17:32:30 -05002 * Copyright 2014 The Chromium OS Authors. All rights reserved.
Stéphane Marchesin25a26062014-09-12 16:18:59 -07003 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_I915
Stéphane Marchesin25a26062014-09-12 16:18:59 -07008
9#include <errno.h>
Gurchetan Singh82a8eed2017-01-03 13:01:37 -080010#include <i915_drm.h>
Gurchetan Singhcc015e82017-01-17 16:15:25 -080011#include <stdio.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070012#include <string.h>
Gurchetan Singhef920532016-08-12 16:38:25 -070013#include <sys/mman.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070014#include <xf86drm.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070015
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070016#include "drv_priv.h"
Stéphane Marchesin25a26062014-09-12 16:18:59 -070017#include "helpers.h"
18#include "util.h"
19
Gurchetan Singh68af9c22017-01-18 13:48:11 -080020#define I915_CACHELINE_SIZE 64
21#define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
22
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070023static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888,
24 DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
25 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555,
26 DRM_FORMAT_XRGB8888 };
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080027
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070028static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
29 DRM_FORMAT_UYVY, DRM_FORMAT_YUYV };
30
31static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
Gurchetan Singh179687e2016-10-28 10:07:35 -070032
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080033struct i915_device {
Gurchetan Singh68af9c22017-01-18 13:48:11 -080034 uint32_t gen;
35 int32_t has_llc;
Stéphane Marchesin25a26062014-09-12 16:18:59 -070036};
37
Gurchetan Singh68af9c22017-01-18 13:48:11 -080038static uint32_t i915_get_gen(int device_id)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070039{
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080040 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
41 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
Stéphane Marchesina39dfde2014-09-15 15:38:25 -070042 unsigned i;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080043 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070044 if (gen3_ids[i] == device_id)
45 return 3;
46
47 return 4;
48}
49
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080050static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
51{
52 uint32_t i;
53 struct combination *combo;
54
55 /*
56 * Older hardware can't scanout Y-tiled formats. Newer devices can, and
57 * report this functionality via format modifiers.
58 */
59 for (i = 0; i < drv->backend->combos.size; i++) {
60 combo = &drv->backend->combos.data[i];
61 if (combo->format == item->format) {
62 if ((combo->metadata.tiling == I915_TILING_Y &&
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080063 item->modifier == I915_FORMAT_MOD_Y_TILED) ||
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080064 (combo->metadata.tiling == I915_TILING_X &&
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080065 item->modifier == I915_FORMAT_MOD_X_TILED)) {
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080066 combo->metadata.modifier = item->modifier;
67 combo->usage |= item->usage;
68 } else if (combo->metadata.tiling != I915_TILING_Y) {
69 combo->usage |= item->usage;
70 }
71 }
72 }
73
74 return 0;
75}
76
77static int i915_add_combinations(struct driver *drv)
78{
79 int ret;
80 uint32_t i, num_items;
81 struct kms_item *items;
82 struct format_metadata metadata;
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070083 uint64_t render_flags, texture_flags;
84
85 render_flags = BO_USE_RENDER_MASK;
86 texture_flags = BO_USE_TEXTURE_MASK;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080087
88 metadata.tiling = I915_TILING_NONE;
89 metadata.priority = 1;
90 metadata.modifier = DRM_FORMAT_MOD_NONE;
91
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070092 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
93 &metadata, render_flags);
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080094 if (ret)
95 return ret;
96
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070097 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
98 &metadata, texture_flags);
99 if (ret)
100 return ret;
101
102 ret = drv_add_combinations(drv, tileable_texture_source_formats,
Dongseong Hwang3c5be5a2017-06-14 10:47:11 -0700103 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
104 texture_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800105 if (ret)
106 return ret;
107
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800108 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
109 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800110
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700111 render_flags &= ~BO_USE_SW_WRITE_OFTEN;
112 render_flags &= ~BO_USE_SW_READ_OFTEN;
113 render_flags &= ~BO_USE_LINEAR;
114
115 texture_flags &= ~BO_USE_SW_WRITE_OFTEN;
116 texture_flags &= ~BO_USE_SW_READ_OFTEN;
117 texture_flags &= ~BO_USE_LINEAR;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800118
119 metadata.tiling = I915_TILING_X;
120 metadata.priority = 2;
121
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700122 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
123 &metadata, render_flags);
124 if (ret)
125 return ret;
126
127 ret = drv_add_combinations(drv, tileable_texture_source_formats,
128 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
129 texture_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800130 if (ret)
131 return ret;
132
133 metadata.tiling = I915_TILING_Y;
134 metadata.priority = 3;
135
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700136 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
137 &metadata, render_flags);
138 if (ret)
139 return ret;
140
141 ret = drv_add_combinations(drv, tileable_texture_source_formats,
142 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
143 texture_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800144 if (ret)
145 return ret;
146
147 items = drv_query_kms(drv, &num_items);
148 if (!items || !num_items)
149 return 0;
150
151 for (i = 0; i < num_items; i++) {
152 ret = i915_add_kms_item(drv, &items[i]);
153 if (ret) {
154 free(items);
155 return ret;
156 }
157 }
158
159 free(items);
160 return 0;
161}
162
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800163static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
164 uint32_t *aligned_height)
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700165{
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700166 struct i915_device *i915 = bo->drv->priv;
167 uint32_t horizontal_alignment = 4;
168 uint32_t vertical_alignment = 4;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700169
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700170 switch (tiling) {
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700171 default:
172 case I915_TILING_NONE:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700173 horizontal_alignment = 64;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700174 break;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800175
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700176 case I915_TILING_X:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700177 horizontal_alignment = 512;
178 vertical_alignment = 8;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700179 break;
180
181 case I915_TILING_Y:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700182 if (i915->gen == 3) {
183 horizontal_alignment = 512;
184 vertical_alignment = 8;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800185 } else {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700186 horizontal_alignment = 128;
187 vertical_alignment = 32;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700188 }
189 break;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700190 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800191
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700192 *aligned_height = ALIGN(bo->height, vertical_alignment);
193 if (i915->gen > 3) {
194 *stride = ALIGN(*stride, horizontal_alignment);
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800195 } else {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700196 while (*stride > horizontal_alignment)
197 horizontal_alignment <<= 1;
198
199 *stride = horizontal_alignment;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800200 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800201
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700202 if (i915->gen <= 3 && *stride > 8192)
203 return -EINVAL;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800204
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700205 return 0;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700206}
207
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800208static void i915_clflush(void *start, size_t size)
209{
210 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
211 void *end = (void *)((uintptr_t)start + size);
212
213 __builtin_ia32_mfence();
214 while (p < end) {
215 __builtin_ia32_clflush(p);
216 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
217 }
218}
219
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800220static int i915_init(struct driver *drv)
221{
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800222 int ret;
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800223 int device_id;
224 struct i915_device *i915;
225 drm_i915_getparam_t get_param;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800226
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800227 i915 = calloc(1, sizeof(*i915));
228 if (!i915)
229 return -ENOMEM;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800230
231 memset(&get_param, 0, sizeof(get_param));
232 get_param.param = I915_PARAM_CHIPSET_ID;
233 get_param.value = &device_id;
234 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
235 if (ret) {
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800236 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800237 free(i915);
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800238 return -EINVAL;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800239 }
240
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800241 i915->gen = i915_get_gen(device_id);
242
243 memset(&get_param, 0, sizeof(get_param));
244 get_param.param = I915_PARAM_HAS_LLC;
245 get_param.value = &i915->has_llc;
246 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
247 if (ret) {
248 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
249 free(i915);
250 return -EINVAL;
251 }
252
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800253 drv->priv = i915;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800254
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800255 return i915_add_combinations(drv);
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800256}
257
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800258static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
259 uint32_t flags)
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700260{
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700261 int ret;
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800262 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700263 uint32_t stride;
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800264 struct drm_i915_gem_create gem_create;
265 struct drm_i915_gem_set_tiling gem_set_tiling;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700266
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800267 if (flags & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800268 bo->tiling = I915_TILING_NONE;
Gurchetan Singh458976f2016-11-23 17:32:33 -0800269 else if (flags & BO_USE_SCANOUT)
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800270 bo->tiling = I915_TILING_X;
Gurchetan Singh6bab0c12016-10-13 19:08:48 -0700271 else
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800272 bo->tiling = I915_TILING_Y;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700273
Owen Linbbb69fd2017-06-05 14:33:08 +0800274 if (format == DRM_FORMAT_YVU420 || format == DRM_FORMAT_YVU420_ANDROID)
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800275 bo->tiling = I915_TILING_NONE;
Owen Linbbb69fd2017-06-05 14:33:08 +0800276
277 stride = drv_stride_from_format(format, width, 0);
Gurchetan Singh507f5dd2017-03-16 13:14:30 -0700278
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800279 ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700280 if (ret)
281 return ret;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800282
Owen Linbbb69fd2017-06-05 14:33:08 +0800283 /*
284 * Align the Y plane to 128 bytes so the chroma planes would be aligned
285 * to 64 byte boundaries. This is an Intel HW requirement.
286 */
287 if (format == DRM_FORMAT_YVU420)
288 stride = ALIGN(stride, 128);
289
290 /*
291 * HAL_PIXEL_FORMAT_YV12 requires that the buffer's height not be aligned.
292 */
293 if (format == DRM_FORMAT_YVU420_ANDROID)
294 height = bo->height;
295
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700296 drv_bo_from_format(bo, stride, height, format);
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800297
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800298 memset(&gem_create, 0, sizeof(gem_create));
299 gem_create.size = bo->total_size;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800300
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800301 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
302 if (ret) {
303 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
304 gem_create.size);
305 return ret;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -0700306 }
Gurchetan Singh83dc4fb2016-07-19 15:52:33 -0700307
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800308 for (plane = 0; plane < bo->num_planes; plane++)
309 bo->handles[plane].u32 = gem_create.handle;
Daniel Nicoara1de26dc2014-09-25 18:53:19 -0400310
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800311 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
312 gem_set_tiling.handle = bo->handles[0].u32;
313 gem_set_tiling.tiling_mode = bo->tiling;
314 gem_set_tiling.stride = bo->strides[0];
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700315
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800316 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
317 if (ret) {
318 struct drm_gem_close gem_close;
319 memset(&gem_close, 0, sizeof(gem_close));
320 gem_close.handle = bo->handles[0].u32;
321 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800322
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800323 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700324 return -errno;
325 }
326
327 return 0;
328}
329
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800330static void i915_close(struct driver *drv)
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800331{
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800332 free(drv->priv);
333 drv->priv = NULL;
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800334}
335
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800336static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
337{
338 int ret;
339 struct drm_i915_gem_get_tiling gem_get_tiling;
340
341 ret = drv_prime_bo_import(bo, data);
342 if (ret)
343 return ret;
344
345 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
346 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
347 gem_get_tiling.handle = bo->handles[0].u32;
348
349 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
350 if (ret) {
351 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
352 return ret;
353 }
354
355 bo->tiling = gem_get_tiling.tiling_mode;
356 return 0;
357}
358
Gurchetan Singh1a31e602016-10-06 10:58:00 -0700359static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane)
Gurchetan Singhef920532016-08-12 16:38:25 -0700360{
361 int ret;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800362 void *addr;
363 struct drm_i915_gem_set_domain set_domain;
Gurchetan Singhef920532016-08-12 16:38:25 -0700364
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800365 memset(&set_domain, 0, sizeof(set_domain));
366 set_domain.handle = bo->handles[0].u32;
367 if (bo->tiling == I915_TILING_NONE) {
368 struct drm_i915_gem_mmap gem_map;
369 memset(&gem_map, 0, sizeof(gem_map));
Gurchetan Singhef920532016-08-12 16:38:25 -0700370
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800371 gem_map.handle = bo->handles[0].u32;
372 gem_map.offset = 0;
373 gem_map.size = bo->total_size;
374
375 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
376 if (ret) {
377 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
378 return MAP_FAILED;
379 }
380
381 addr = (void *)(uintptr_t)gem_map.addr_ptr;
382 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
383 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
384
385 } else {
386 struct drm_i915_gem_mmap_gtt gem_map;
387 memset(&gem_map, 0, sizeof(gem_map));
388
389 gem_map.handle = bo->handles[0].u32;
390
391 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
392 if (ret) {
393 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
394 return MAP_FAILED;
395 }
396
397 addr = mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd,
398 gem_map.offset);
399
400 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
401 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
402 }
403
404 if (addr == MAP_FAILED) {
405 fprintf(stderr, "drv: i915 GEM mmap failed\n");
406 return addr;
407 }
408
409 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
Gurchetan Singhef920532016-08-12 16:38:25 -0700410 if (ret) {
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800411 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN failed\n");
Gurchetan Singhef920532016-08-12 16:38:25 -0700412 return MAP_FAILED;
413 }
414
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800415 data->length = bo->total_size;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800416 return addr;
417}
Gurchetan Singh1a31e602016-10-06 10:58:00 -0700418
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800419static int i915_bo_unmap(struct bo *bo, struct map_info *data)
420{
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800421 struct i915_device *i915 = bo->drv->priv;
422 if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
423 i915_clflush(data->addr, data->length);
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800424
425 return munmap(data->addr, data->length);
Gurchetan Singhef920532016-08-12 16:38:25 -0700426}
427
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800428static uint32_t i915_resolve_format(uint32_t format)
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700429{
430 switch (format) {
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800431 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700432 /*HACK: See b/28671744 */
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800433 return DRM_FORMAT_XBGR8888;
434 case DRM_FORMAT_FLEX_YCbCr_420_888:
Owen Linbbb69fd2017-06-05 14:33:08 +0800435 return DRM_FORMAT_YVU420;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700436 default:
437 return format;
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700438 }
439}
440
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800441struct backend backend_i915 = {
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700442 .name = "i915",
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700443 .init = i915_init,
444 .close = i915_close,
445 .bo_create = i915_bo_create,
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800446 .bo_destroy = drv_gem_bo_destroy,
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800447 .bo_import = i915_bo_import,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700448 .bo_map = i915_bo_map,
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800449 .bo_unmap = i915_bo_unmap,
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700450 .resolve_format = i915_resolve_format,
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700451};
452
453#endif