cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin host_ppc_defs.c ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
| 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 9 | |
sewardj | 89ae847 | 2013-10-18 14:12:58 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2013 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
| 36 | #include "libvex_basictypes.h" |
| 37 | #include "libvex.h" |
| 38 | #include "libvex_trc_values.h" |
| 39 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 40 | #include "main_util.h" |
| 41 | #include "host_generic_regs.h" |
| 42 | #include "host_ppc_defs.h" |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 43 | |
| 44 | |
| 45 | /* --------- Registers. --------- */ |
| 46 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 47 | void ppHRegPPC ( HReg reg ) |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 48 | { |
| 49 | Int r; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 50 | static const HChar* ireg32_names[32] |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 51 | = { "%r0", "%r1", "%r2", "%r3", |
| 52 | "%r4", "%r5", "%r6", "%r7", |
| 53 | "%r8", "%r9", "%r10", "%r11", |
| 54 | "%r12", "%r13", "%r14", "%r15", |
| 55 | "%r16", "%r17", "%r18", "%r19", |
| 56 | "%r20", "%r21", "%r22", "%r23", |
| 57 | "%r24", "%r25", "%r26", "%r27", |
| 58 | "%r28", "%r29", "%r30", "%r31" }; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 59 | /* Be generic for all virtual regs. */ |
| 60 | if (hregIsVirtual(reg)) { |
| 61 | ppHReg(reg); |
| 62 | return; |
| 63 | } |
| 64 | /* But specific for real regs. */ |
| 65 | switch (hregClass(reg)) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 66 | case HRcInt64: |
| 67 | r = hregNumber(reg); |
| 68 | vassert(r >= 0 && r < 32); |
| 69 | vex_printf("%s", ireg32_names[r]); |
| 70 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 71 | case HRcInt32: |
| 72 | r = hregNumber(reg); |
| 73 | vassert(r >= 0 && r < 32); |
| 74 | vex_printf("%s", ireg32_names[r]); |
| 75 | return; |
| 76 | case HRcFlt64: |
| 77 | r = hregNumber(reg); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 78 | vassert(r >= 0 && r < 32); |
| 79 | vex_printf("%%fr%d", r); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 80 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 81 | case HRcVec128: |
| 82 | r = hregNumber(reg); |
| 83 | vassert(r >= 0 && r < 32); |
| 84 | vex_printf("%%v%d", r); |
| 85 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 86 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 87 | vpanic("ppHRegPPC"); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 88 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 89 | } |
| 90 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 91 | |
| 92 | #define MkHRegGPR(_n, _mode64) \ |
| 93 | mkHReg(_n, _mode64 ? HRcInt64 : HRcInt32, False) |
| 94 | |
| 95 | HReg hregPPC_GPR0 ( Bool mode64 ) { return MkHRegGPR( 0, mode64); } |
| 96 | HReg hregPPC_GPR1 ( Bool mode64 ) { return MkHRegGPR( 1, mode64); } |
| 97 | HReg hregPPC_GPR2 ( Bool mode64 ) { return MkHRegGPR( 2, mode64); } |
| 98 | HReg hregPPC_GPR3 ( Bool mode64 ) { return MkHRegGPR( 3, mode64); } |
| 99 | HReg hregPPC_GPR4 ( Bool mode64 ) { return MkHRegGPR( 4, mode64); } |
| 100 | HReg hregPPC_GPR5 ( Bool mode64 ) { return MkHRegGPR( 5, mode64); } |
| 101 | HReg hregPPC_GPR6 ( Bool mode64 ) { return MkHRegGPR( 6, mode64); } |
| 102 | HReg hregPPC_GPR7 ( Bool mode64 ) { return MkHRegGPR( 7, mode64); } |
| 103 | HReg hregPPC_GPR8 ( Bool mode64 ) { return MkHRegGPR( 8, mode64); } |
| 104 | HReg hregPPC_GPR9 ( Bool mode64 ) { return MkHRegGPR( 9, mode64); } |
| 105 | HReg hregPPC_GPR10 ( Bool mode64 ) { return MkHRegGPR(10, mode64); } |
| 106 | HReg hregPPC_GPR11 ( Bool mode64 ) { return MkHRegGPR(11, mode64); } |
| 107 | HReg hregPPC_GPR12 ( Bool mode64 ) { return MkHRegGPR(12, mode64); } |
| 108 | HReg hregPPC_GPR13 ( Bool mode64 ) { return MkHRegGPR(13, mode64); } |
| 109 | HReg hregPPC_GPR14 ( Bool mode64 ) { return MkHRegGPR(14, mode64); } |
| 110 | HReg hregPPC_GPR15 ( Bool mode64 ) { return MkHRegGPR(15, mode64); } |
| 111 | HReg hregPPC_GPR16 ( Bool mode64 ) { return MkHRegGPR(16, mode64); } |
| 112 | HReg hregPPC_GPR17 ( Bool mode64 ) { return MkHRegGPR(17, mode64); } |
| 113 | HReg hregPPC_GPR18 ( Bool mode64 ) { return MkHRegGPR(18, mode64); } |
| 114 | HReg hregPPC_GPR19 ( Bool mode64 ) { return MkHRegGPR(19, mode64); } |
| 115 | HReg hregPPC_GPR20 ( Bool mode64 ) { return MkHRegGPR(20, mode64); } |
| 116 | HReg hregPPC_GPR21 ( Bool mode64 ) { return MkHRegGPR(21, mode64); } |
| 117 | HReg hregPPC_GPR22 ( Bool mode64 ) { return MkHRegGPR(22, mode64); } |
| 118 | HReg hregPPC_GPR23 ( Bool mode64 ) { return MkHRegGPR(23, mode64); } |
| 119 | HReg hregPPC_GPR24 ( Bool mode64 ) { return MkHRegGPR(24, mode64); } |
| 120 | HReg hregPPC_GPR25 ( Bool mode64 ) { return MkHRegGPR(25, mode64); } |
| 121 | HReg hregPPC_GPR26 ( Bool mode64 ) { return MkHRegGPR(26, mode64); } |
| 122 | HReg hregPPC_GPR27 ( Bool mode64 ) { return MkHRegGPR(27, mode64); } |
| 123 | HReg hregPPC_GPR28 ( Bool mode64 ) { return MkHRegGPR(28, mode64); } |
| 124 | HReg hregPPC_GPR29 ( Bool mode64 ) { return MkHRegGPR(29, mode64); } |
| 125 | HReg hregPPC_GPR30 ( Bool mode64 ) { return MkHRegGPR(30, mode64); } |
| 126 | HReg hregPPC_GPR31 ( Bool mode64 ) { return MkHRegGPR(31, mode64); } |
| 127 | |
| 128 | #undef MK_INT_HREG |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 129 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 130 | HReg hregPPC_FPR0 ( void ) { return mkHReg( 0, HRcFlt64, False); } |
| 131 | HReg hregPPC_FPR1 ( void ) { return mkHReg( 1, HRcFlt64, False); } |
| 132 | HReg hregPPC_FPR2 ( void ) { return mkHReg( 2, HRcFlt64, False); } |
| 133 | HReg hregPPC_FPR3 ( void ) { return mkHReg( 3, HRcFlt64, False); } |
| 134 | HReg hregPPC_FPR4 ( void ) { return mkHReg( 4, HRcFlt64, False); } |
| 135 | HReg hregPPC_FPR5 ( void ) { return mkHReg( 5, HRcFlt64, False); } |
| 136 | HReg hregPPC_FPR6 ( void ) { return mkHReg( 6, HRcFlt64, False); } |
| 137 | HReg hregPPC_FPR7 ( void ) { return mkHReg( 7, HRcFlt64, False); } |
| 138 | HReg hregPPC_FPR8 ( void ) { return mkHReg( 8, HRcFlt64, False); } |
| 139 | HReg hregPPC_FPR9 ( void ) { return mkHReg( 9, HRcFlt64, False); } |
| 140 | HReg hregPPC_FPR10 ( void ) { return mkHReg(10, HRcFlt64, False); } |
| 141 | HReg hregPPC_FPR11 ( void ) { return mkHReg(11, HRcFlt64, False); } |
| 142 | HReg hregPPC_FPR12 ( void ) { return mkHReg(12, HRcFlt64, False); } |
| 143 | HReg hregPPC_FPR13 ( void ) { return mkHReg(13, HRcFlt64, False); } |
| 144 | HReg hregPPC_FPR14 ( void ) { return mkHReg(14, HRcFlt64, False); } |
| 145 | HReg hregPPC_FPR15 ( void ) { return mkHReg(15, HRcFlt64, False); } |
| 146 | HReg hregPPC_FPR16 ( void ) { return mkHReg(16, HRcFlt64, False); } |
| 147 | HReg hregPPC_FPR17 ( void ) { return mkHReg(17, HRcFlt64, False); } |
| 148 | HReg hregPPC_FPR18 ( void ) { return mkHReg(18, HRcFlt64, False); } |
| 149 | HReg hregPPC_FPR19 ( void ) { return mkHReg(19, HRcFlt64, False); } |
| 150 | HReg hregPPC_FPR20 ( void ) { return mkHReg(20, HRcFlt64, False); } |
| 151 | HReg hregPPC_FPR21 ( void ) { return mkHReg(21, HRcFlt64, False); } |
| 152 | HReg hregPPC_FPR22 ( void ) { return mkHReg(22, HRcFlt64, False); } |
| 153 | HReg hregPPC_FPR23 ( void ) { return mkHReg(23, HRcFlt64, False); } |
| 154 | HReg hregPPC_FPR24 ( void ) { return mkHReg(24, HRcFlt64, False); } |
| 155 | HReg hregPPC_FPR25 ( void ) { return mkHReg(25, HRcFlt64, False); } |
| 156 | HReg hregPPC_FPR26 ( void ) { return mkHReg(26, HRcFlt64, False); } |
| 157 | HReg hregPPC_FPR27 ( void ) { return mkHReg(27, HRcFlt64, False); } |
| 158 | HReg hregPPC_FPR28 ( void ) { return mkHReg(28, HRcFlt64, False); } |
| 159 | HReg hregPPC_FPR29 ( void ) { return mkHReg(29, HRcFlt64, False); } |
| 160 | HReg hregPPC_FPR30 ( void ) { return mkHReg(30, HRcFlt64, False); } |
| 161 | HReg hregPPC_FPR31 ( void ) { return mkHReg(31, HRcFlt64, False); } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 162 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 163 | HReg hregPPC_VR0 ( void ) { return mkHReg( 0, HRcVec128, False); } |
| 164 | HReg hregPPC_VR1 ( void ) { return mkHReg( 1, HRcVec128, False); } |
| 165 | HReg hregPPC_VR2 ( void ) { return mkHReg( 2, HRcVec128, False); } |
| 166 | HReg hregPPC_VR3 ( void ) { return mkHReg( 3, HRcVec128, False); } |
| 167 | HReg hregPPC_VR4 ( void ) { return mkHReg( 4, HRcVec128, False); } |
| 168 | HReg hregPPC_VR5 ( void ) { return mkHReg( 5, HRcVec128, False); } |
| 169 | HReg hregPPC_VR6 ( void ) { return mkHReg( 6, HRcVec128, False); } |
| 170 | HReg hregPPC_VR7 ( void ) { return mkHReg( 7, HRcVec128, False); } |
| 171 | HReg hregPPC_VR8 ( void ) { return mkHReg( 8, HRcVec128, False); } |
| 172 | HReg hregPPC_VR9 ( void ) { return mkHReg( 9, HRcVec128, False); } |
| 173 | HReg hregPPC_VR10 ( void ) { return mkHReg(10, HRcVec128, False); } |
| 174 | HReg hregPPC_VR11 ( void ) { return mkHReg(11, HRcVec128, False); } |
| 175 | HReg hregPPC_VR12 ( void ) { return mkHReg(12, HRcVec128, False); } |
| 176 | HReg hregPPC_VR13 ( void ) { return mkHReg(13, HRcVec128, False); } |
| 177 | HReg hregPPC_VR14 ( void ) { return mkHReg(14, HRcVec128, False); } |
| 178 | HReg hregPPC_VR15 ( void ) { return mkHReg(15, HRcVec128, False); } |
| 179 | HReg hregPPC_VR16 ( void ) { return mkHReg(16, HRcVec128, False); } |
| 180 | HReg hregPPC_VR17 ( void ) { return mkHReg(17, HRcVec128, False); } |
| 181 | HReg hregPPC_VR18 ( void ) { return mkHReg(18, HRcVec128, False); } |
| 182 | HReg hregPPC_VR19 ( void ) { return mkHReg(19, HRcVec128, False); } |
| 183 | HReg hregPPC_VR20 ( void ) { return mkHReg(20, HRcVec128, False); } |
| 184 | HReg hregPPC_VR21 ( void ) { return mkHReg(21, HRcVec128, False); } |
| 185 | HReg hregPPC_VR22 ( void ) { return mkHReg(22, HRcVec128, False); } |
| 186 | HReg hregPPC_VR23 ( void ) { return mkHReg(23, HRcVec128, False); } |
| 187 | HReg hregPPC_VR24 ( void ) { return mkHReg(24, HRcVec128, False); } |
| 188 | HReg hregPPC_VR25 ( void ) { return mkHReg(25, HRcVec128, False); } |
| 189 | HReg hregPPC_VR26 ( void ) { return mkHReg(26, HRcVec128, False); } |
| 190 | HReg hregPPC_VR27 ( void ) { return mkHReg(27, HRcVec128, False); } |
| 191 | HReg hregPPC_VR28 ( void ) { return mkHReg(28, HRcVec128, False); } |
| 192 | HReg hregPPC_VR29 ( void ) { return mkHReg(29, HRcVec128, False); } |
| 193 | HReg hregPPC_VR30 ( void ) { return mkHReg(30, HRcVec128, False); } |
| 194 | HReg hregPPC_VR31 ( void ) { return mkHReg(31, HRcVec128, False); } |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 195 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 196 | void getAllocableRegs_PPC ( Int* nregs, HReg** arr, Bool mode64 ) |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 197 | { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 198 | UInt i=0; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 199 | if (mode64) |
sewardj | f774505 | 2005-12-16 01:06:42 +0000 | [diff] [blame] | 200 | *nregs = (32-9) + (32-24) + (32-24); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 201 | else |
sewardj | f774505 | 2005-12-16 01:06:42 +0000 | [diff] [blame] | 202 | *nregs = (32-7) + (32-24) + (32-24); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 203 | *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 204 | // GPR0 = scratch reg where poss. - some ops interpret as value zero |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 205 | // GPR1 = stack pointer |
| 206 | // GPR2 = TOC pointer |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 207 | (*arr)[i++] = hregPPC_GPR3(mode64); |
| 208 | (*arr)[i++] = hregPPC_GPR4(mode64); |
| 209 | (*arr)[i++] = hregPPC_GPR5(mode64); |
| 210 | (*arr)[i++] = hregPPC_GPR6(mode64); |
| 211 | (*arr)[i++] = hregPPC_GPR7(mode64); |
| 212 | (*arr)[i++] = hregPPC_GPR8(mode64); |
| 213 | (*arr)[i++] = hregPPC_GPR9(mode64); |
| 214 | (*arr)[i++] = hregPPC_GPR10(mode64); |
| 215 | if (!mode64) { |
| 216 | /* in mode64: |
| 217 | r11 used for calls by ptr / env ptr for some langs |
| 218 | r12 used for exception handling and global linkage code */ |
| 219 | (*arr)[i++] = hregPPC_GPR11(mode64); |
| 220 | (*arr)[i++] = hregPPC_GPR12(mode64); |
| 221 | } |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 222 | // GPR13 = thread specific pointer |
sewardj | f774505 | 2005-12-16 01:06:42 +0000 | [diff] [blame] | 223 | // GPR14 and above are callee save. Yay. |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 224 | (*arr)[i++] = hregPPC_GPR14(mode64); |
| 225 | (*arr)[i++] = hregPPC_GPR15(mode64); |
| 226 | (*arr)[i++] = hregPPC_GPR16(mode64); |
| 227 | (*arr)[i++] = hregPPC_GPR17(mode64); |
| 228 | (*arr)[i++] = hregPPC_GPR18(mode64); |
| 229 | (*arr)[i++] = hregPPC_GPR19(mode64); |
| 230 | (*arr)[i++] = hregPPC_GPR20(mode64); |
| 231 | (*arr)[i++] = hregPPC_GPR21(mode64); |
| 232 | (*arr)[i++] = hregPPC_GPR22(mode64); |
| 233 | (*arr)[i++] = hregPPC_GPR23(mode64); |
| 234 | (*arr)[i++] = hregPPC_GPR24(mode64); |
| 235 | (*arr)[i++] = hregPPC_GPR25(mode64); |
| 236 | (*arr)[i++] = hregPPC_GPR26(mode64); |
| 237 | (*arr)[i++] = hregPPC_GPR27(mode64); |
| 238 | (*arr)[i++] = hregPPC_GPR28(mode64); |
sewardj | f774505 | 2005-12-16 01:06:42 +0000 | [diff] [blame] | 239 | // GPR29 is reserved for the dispatcher |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 240 | // GPR30 is reserved as AltiVec spill reg temporary |
| 241 | // GPR31 is reserved for the GuestStatePtr |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 242 | |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 243 | /* Don't waste the reg-allocs's time trawling through zillions of |
| 244 | FP registers - they mostly will never be used. We'll tolerate |
| 245 | the occasional extra spill instead. */ |
sewardj | cb1f68e | 2005-12-30 03:39:14 +0000 | [diff] [blame] | 246 | /* For both ppc32-linux and ppc64-linux, f14-f31 are callee save. |
| 247 | So use them. */ |
| 248 | (*arr)[i++] = hregPPC_FPR14(); |
| 249 | (*arr)[i++] = hregPPC_FPR15(); |
| 250 | (*arr)[i++] = hregPPC_FPR16(); |
| 251 | (*arr)[i++] = hregPPC_FPR17(); |
| 252 | (*arr)[i++] = hregPPC_FPR18(); |
| 253 | (*arr)[i++] = hregPPC_FPR19(); |
| 254 | (*arr)[i++] = hregPPC_FPR20(); |
| 255 | (*arr)[i++] = hregPPC_FPR21(); |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 256 | |
| 257 | /* Same deal re Altivec */ |
sewardj | cb1f68e | 2005-12-30 03:39:14 +0000 | [diff] [blame] | 258 | /* For both ppc32-linux and ppc64-linux, v20-v31 are callee save. |
| 259 | So use them. */ |
sewardj | f774505 | 2005-12-16 01:06:42 +0000 | [diff] [blame] | 260 | /* NB, vr29 is used as a scratch temporary -- do not allocate */ |
sewardj | cb1f68e | 2005-12-30 03:39:14 +0000 | [diff] [blame] | 261 | (*arr)[i++] = hregPPC_VR20(); |
| 262 | (*arr)[i++] = hregPPC_VR21(); |
| 263 | (*arr)[i++] = hregPPC_VR22(); |
| 264 | (*arr)[i++] = hregPPC_VR23(); |
| 265 | (*arr)[i++] = hregPPC_VR24(); |
| 266 | (*arr)[i++] = hregPPC_VR25(); |
| 267 | (*arr)[i++] = hregPPC_VR26(); |
| 268 | (*arr)[i++] = hregPPC_VR27(); |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 269 | |
cerion | 0171310 | 2005-06-29 19:05:08 +0000 | [diff] [blame] | 270 | vassert(i == *nregs); |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | |
| 274 | /* --------- Condition codes, Intel encoding. --------- */ |
| 275 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 276 | const HChar* showPPCCondCode ( PPCCondCode cond ) |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 277 | { |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 278 | if (cond.test == Pct_ALWAYS) return "always"; |
| 279 | |
| 280 | switch (cond.flag) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 281 | case Pcf_7SO: |
| 282 | return (cond.test == Pct_TRUE) ? "cr7.so=1" : "cr7.so=0"; |
| 283 | case Pcf_7EQ: |
| 284 | return (cond.test == Pct_TRUE) ? "cr7.eq=1" : "cr7.eq=0"; |
| 285 | case Pcf_7GT: |
| 286 | return (cond.test == Pct_TRUE) ? "cr7.gt=1" : "cr7.gt=0"; |
| 287 | case Pcf_7LT: |
| 288 | return (cond.test == Pct_TRUE) ? "cr7.lt=1" : "cr7.lt=0"; |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 289 | case Pcf_NONE: |
| 290 | return "no-flag"; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 291 | default: vpanic("ppPPCCondCode"); |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 292 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 293 | } |
| 294 | |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 295 | /* construct condition code */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 296 | PPCCondCode mk_PPCCondCode ( PPCCondTest test, PPCCondFlag flag ) |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 297 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 298 | PPCCondCode cc; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 299 | cc.flag = flag; |
| 300 | cc.test = test; |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 301 | if (test == Pct_ALWAYS) { |
| 302 | vassert(flag == Pcf_NONE); |
| 303 | } else { |
| 304 | vassert(flag != Pcf_NONE); |
| 305 | } |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 306 | return cc; |
| 307 | } |
| 308 | |
| 309 | /* false->true, true->false */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 310 | PPCCondTest invertCondTest ( PPCCondTest ct ) |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 311 | { |
| 312 | vassert(ct != Pct_ALWAYS); |
| 313 | return (ct == Pct_TRUE) ? Pct_FALSE : Pct_TRUE; |
| 314 | } |
| 315 | |
| 316 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 317 | /* --------- PPCAMode: memory address expressions. --------- */ |
| 318 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 319 | PPCAMode* PPCAMode_IR ( Int idx, HReg base ) { |
| 320 | PPCAMode* am = LibVEX_Alloc(sizeof(PPCAMode)); |
sewardj | a5f957d | 2005-07-02 01:29:32 +0000 | [diff] [blame] | 321 | vassert(idx >= -0x8000 && idx < 0x8000); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 322 | am->tag = Pam_IR; |
| 323 | am->Pam.IR.base = base; |
| 324 | am->Pam.IR.index = idx; |
| 325 | return am; |
| 326 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 327 | PPCAMode* PPCAMode_RR ( HReg idx, HReg base ) { |
| 328 | PPCAMode* am = LibVEX_Alloc(sizeof(PPCAMode)); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 329 | am->tag = Pam_RR; |
| 330 | am->Pam.RR.base = base; |
| 331 | am->Pam.RR.index = idx; |
| 332 | return am; |
| 333 | } |
| 334 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 335 | PPCAMode* dopyPPCAMode ( PPCAMode* am ) { |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 336 | switch (am->tag) { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 337 | case Pam_IR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 338 | return PPCAMode_IR( am->Pam.IR.index, am->Pam.IR.base ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 339 | case Pam_RR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 340 | return PPCAMode_RR( am->Pam.RR.index, am->Pam.RR.base ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 341 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 342 | vpanic("dopyPPCAMode"); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 343 | } |
| 344 | } |
| 345 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 346 | void ppPPCAMode ( PPCAMode* am ) { |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 347 | switch (am->tag) { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 348 | case Pam_IR: |
| 349 | if (am->Pam.IR.index == 0) |
cerion | f9d6e22 | 2005-02-23 18:21:31 +0000 | [diff] [blame] | 350 | vex_printf("0("); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 351 | else |
sewardj | a5f957d | 2005-07-02 01:29:32 +0000 | [diff] [blame] | 352 | vex_printf("%d(", (Int)am->Pam.IR.index); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 353 | ppHRegPPC(am->Pam.IR.base); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 354 | vex_printf(")"); |
| 355 | return; |
| 356 | case Pam_RR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 357 | ppHRegPPC(am->Pam.RR.base); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 358 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 359 | ppHRegPPC(am->Pam.RR.index); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 360 | return; |
| 361 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 362 | vpanic("ppPPCAMode"); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 363 | } |
| 364 | } |
| 365 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 366 | static void addRegUsage_PPCAMode ( HRegUsage* u, PPCAMode* am ) { |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 367 | switch (am->tag) { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 368 | case Pam_IR: |
| 369 | addHRegUse(u, HRmRead, am->Pam.IR.base); |
| 370 | return; |
| 371 | case Pam_RR: |
| 372 | addHRegUse(u, HRmRead, am->Pam.RR.base); |
| 373 | addHRegUse(u, HRmRead, am->Pam.RR.index); |
| 374 | return; |
| 375 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 376 | vpanic("addRegUsage_PPCAMode"); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 377 | } |
| 378 | } |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 379 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 380 | static void mapRegs_PPCAMode ( HRegRemap* m, PPCAMode* am ) { |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 381 | switch (am->tag) { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 382 | case Pam_IR: |
| 383 | am->Pam.IR.base = lookupHRegRemap(m, am->Pam.IR.base); |
| 384 | return; |
| 385 | case Pam_RR: |
| 386 | am->Pam.RR.base = lookupHRegRemap(m, am->Pam.RR.base); |
| 387 | am->Pam.RR.index = lookupHRegRemap(m, am->Pam.RR.index); |
| 388 | return; |
| 389 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 390 | vpanic("mapRegs_PPCAMode"); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 391 | } |
| 392 | } |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 393 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 394 | /* --------- Operand, which can be a reg or a u16/s16. --------- */ |
| 395 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 396 | PPCRH* PPCRH_Imm ( Bool syned, UShort imm16 ) { |
| 397 | PPCRH* op = LibVEX_Alloc(sizeof(PPCRH)); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 398 | op->tag = Prh_Imm; |
| 399 | op->Prh.Imm.syned = syned; |
| 400 | op->Prh.Imm.imm16 = imm16; |
| 401 | /* If this is a signed value, ensure it's not -32768, so that we |
| 402 | are guaranteed always to be able to negate if needed. */ |
| 403 | if (syned) |
| 404 | vassert(imm16 != 0x8000); |
| 405 | vassert(syned == True || syned == False); |
| 406 | return op; |
| 407 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 408 | PPCRH* PPCRH_Reg ( HReg reg ) { |
| 409 | PPCRH* op = LibVEX_Alloc(sizeof(PPCRH)); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 410 | op->tag = Prh_Reg; |
| 411 | op->Prh.Reg.reg = reg; |
| 412 | return op; |
| 413 | } |
| 414 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 415 | void ppPPCRH ( PPCRH* op ) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 416 | switch (op->tag) { |
| 417 | case Prh_Imm: |
| 418 | if (op->Prh.Imm.syned) |
| 419 | vex_printf("%d", (Int)(Short)op->Prh.Imm.imm16); |
| 420 | else |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 421 | vex_printf("%u", (UInt)(UShort)op->Prh.Imm.imm16); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 422 | return; |
| 423 | case Prh_Reg: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 424 | ppHRegPPC(op->Prh.Reg.reg); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 425 | return; |
| 426 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 427 | vpanic("ppPPCRH"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 428 | } |
| 429 | } |
| 430 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 431 | /* An PPCRH can only be used in a "read" context (what would it mean |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 432 | to write or modify a literal?) and so we enumerate its registers |
| 433 | accordingly. */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 434 | static void addRegUsage_PPCRH ( HRegUsage* u, PPCRH* op ) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 435 | switch (op->tag) { |
| 436 | case Prh_Imm: |
| 437 | return; |
| 438 | case Prh_Reg: |
| 439 | addHRegUse(u, HRmRead, op->Prh.Reg.reg); |
| 440 | return; |
| 441 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 442 | vpanic("addRegUsage_PPCRH"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 443 | } |
| 444 | } |
| 445 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 446 | static void mapRegs_PPCRH ( HRegRemap* m, PPCRH* op ) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 447 | switch (op->tag) { |
| 448 | case Prh_Imm: |
| 449 | return; |
| 450 | case Prh_Reg: |
| 451 | op->Prh.Reg.reg = lookupHRegRemap(m, op->Prh.Reg.reg); |
| 452 | return; |
| 453 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 454 | vpanic("mapRegs_PPCRH"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 455 | } |
| 456 | } |
| 457 | |
| 458 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 459 | /* --------- Operand, which can be a reg or a u32/64. --------- */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 460 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 461 | PPCRI* PPCRI_Imm ( ULong imm64 ) { |
| 462 | PPCRI* op = LibVEX_Alloc(sizeof(PPCRI)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 463 | op->tag = Pri_Imm; |
| 464 | op->Pri.Imm = imm64; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 465 | return op; |
| 466 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 467 | PPCRI* PPCRI_Reg ( HReg reg ) { |
| 468 | PPCRI* op = LibVEX_Alloc(sizeof(PPCRI)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 469 | op->tag = Pri_Reg; |
| 470 | op->Pri.Reg = reg; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 471 | return op; |
| 472 | } |
| 473 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 474 | void ppPPCRI ( PPCRI* dst ) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 475 | switch (dst->tag) { |
| 476 | case Pri_Imm: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 477 | vex_printf("0x%llx", dst->Pri.Imm); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 478 | break; |
| 479 | case Pri_Reg: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 480 | ppHRegPPC(dst->Pri.Reg); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 481 | break; |
| 482 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 483 | vpanic("ppPPCRI"); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 484 | } |
| 485 | } |
| 486 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 487 | /* An PPCRI can only be used in a "read" context (what would it |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 488 | mean to write or modify a literal?) and so we enumerate its |
| 489 | registers accordingly. */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 490 | static void addRegUsage_PPCRI ( HRegUsage* u, PPCRI* dst ) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 491 | switch (dst->tag) { |
| 492 | case Pri_Imm: |
| 493 | return; |
| 494 | case Pri_Reg: |
| 495 | addHRegUse(u, HRmRead, dst->Pri.Reg); |
| 496 | return; |
| 497 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 498 | vpanic("addRegUsage_PPCRI"); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 499 | } |
| 500 | } |
| 501 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 502 | static void mapRegs_PPCRI ( HRegRemap* m, PPCRI* dst ) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 503 | switch (dst->tag) { |
| 504 | case Pri_Imm: |
| 505 | return; |
| 506 | case Pri_Reg: |
| 507 | dst->Pri.Reg = lookupHRegRemap(m, dst->Pri.Reg); |
| 508 | return; |
| 509 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 510 | vpanic("mapRegs_PPCRI"); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 511 | } |
| 512 | } |
| 513 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 514 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 515 | /* --------- Operand, which can be a vector reg or a simm5. --------- */ |
| 516 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 517 | PPCVI5s* PPCVI5s_Imm ( Char simm5 ) { |
| 518 | PPCVI5s* op = LibVEX_Alloc(sizeof(PPCVI5s)); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 519 | op->tag = Pvi_Imm; |
| 520 | op->Pvi.Imm5s = simm5; |
| 521 | vassert(simm5 >= -16 && simm5 <= 15); |
| 522 | return op; |
| 523 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 524 | PPCVI5s* PPCVI5s_Reg ( HReg reg ) { |
| 525 | PPCVI5s* op = LibVEX_Alloc(sizeof(PPCVI5s)); |
| 526 | op->tag = Pvi_Reg; |
| 527 | op->Pvi.Reg = reg; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 528 | vassert(hregClass(reg) == HRcVec128); |
| 529 | return op; |
| 530 | } |
| 531 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 532 | void ppPPCVI5s ( PPCVI5s* src ) { |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 533 | switch (src->tag) { |
| 534 | case Pvi_Imm: |
| 535 | vex_printf("%d", (Int)src->Pvi.Imm5s); |
| 536 | break; |
| 537 | case Pvi_Reg: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 538 | ppHRegPPC(src->Pvi.Reg); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 539 | break; |
| 540 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 541 | vpanic("ppPPCVI5s"); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 542 | } |
| 543 | } |
| 544 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 545 | /* An PPCVI5s can only be used in a "read" context (what would it |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 546 | mean to write or modify a literal?) and so we enumerate its |
| 547 | registers accordingly. */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 548 | static void addRegUsage_PPCVI5s ( HRegUsage* u, PPCVI5s* dst ) { |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 549 | switch (dst->tag) { |
| 550 | case Pvi_Imm: |
| 551 | return; |
| 552 | case Pvi_Reg: |
| 553 | addHRegUse(u, HRmRead, dst->Pvi.Reg); |
| 554 | return; |
| 555 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 556 | vpanic("addRegUsage_PPCVI5s"); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 557 | } |
| 558 | } |
| 559 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 560 | static void mapRegs_PPCVI5s ( HRegRemap* m, PPCVI5s* dst ) { |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 561 | switch (dst->tag) { |
| 562 | case Pvi_Imm: |
| 563 | return; |
| 564 | case Pvi_Reg: |
| 565 | dst->Pvi.Reg = lookupHRegRemap(m, dst->Pvi.Reg); |
| 566 | return; |
| 567 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 568 | vpanic("mapRegs_PPCVI5s"); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 569 | } |
| 570 | } |
| 571 | |
| 572 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 573 | /* --------- Instructions. --------- */ |
| 574 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 575 | const HChar* showPPCUnaryOp ( PPCUnaryOp op ) { |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 576 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 577 | case Pun_NOT: return "not"; |
| 578 | case Pun_NEG: return "neg"; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 579 | case Pun_CLZ32: return "cntlzw"; |
| 580 | case Pun_CLZ64: return "cntlzd"; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 581 | case Pun_EXTSW: return "extsw"; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 582 | default: vpanic("showPPCUnaryOp"); |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 583 | } |
| 584 | } |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 585 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 586 | const HChar* showPPCAluOp ( PPCAluOp op, Bool immR ) { |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 587 | switch (op) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 588 | case Palu_ADD: return immR ? "addi" : "add"; |
| 589 | case Palu_SUB: return immR ? "subi" : "sub"; |
| 590 | case Palu_AND: return immR ? "andi." : "and"; |
| 591 | case Palu_OR: return immR ? "ori" : "or"; |
| 592 | case Palu_XOR: return immR ? "xori" : "xor"; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 593 | default: vpanic("showPPCAluOp"); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 594 | } |
| 595 | } |
| 596 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 597 | const HChar* showPPCShftOp ( PPCShftOp op, Bool immR, Bool sz32 ) { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 598 | switch (op) { |
| 599 | case Pshft_SHL: return sz32 ? (immR ? "slwi" : "slw") : |
| 600 | (immR ? "sldi" : "sld"); |
| 601 | case Pshft_SHR: return sz32 ? (immR ? "srwi" : "srw") : |
| 602 | (immR ? "srdi" : "srd"); |
| 603 | case Pshft_SAR: return sz32 ? (immR ? "srawi" : "sraw") : |
| 604 | (immR ? "sradi" : "srad"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 605 | default: vpanic("showPPCShftOp"); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 606 | } |
| 607 | } |
| 608 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 609 | const HChar* showPPCFpOp ( PPCFpOp op ) { |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 610 | switch (op) { |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 611 | case Pfp_ADDD: return "fadd"; |
| 612 | case Pfp_SUBD: return "fsub"; |
| 613 | case Pfp_MULD: return "fmul"; |
| 614 | case Pfp_DIVD: return "fdiv"; |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 615 | case Pfp_MADDD: return "fmadd"; |
| 616 | case Pfp_MSUBD: return "fmsub"; |
| 617 | case Pfp_MADDS: return "fmadds"; |
| 618 | case Pfp_MSUBS: return "fmsubs"; |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 619 | case Pfp_ADDS: return "fadds"; |
| 620 | case Pfp_SUBS: return "fsubs"; |
| 621 | case Pfp_MULS: return "fmuls"; |
| 622 | case Pfp_DIVS: return "fdivs"; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 623 | case Pfp_SQRT: return "fsqrt"; |
| 624 | case Pfp_ABS: return "fabs"; |
| 625 | case Pfp_NEG: return "fneg"; |
| 626 | case Pfp_MOV: return "fmr"; |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 627 | case Pfp_RES: return "fres"; |
| 628 | case Pfp_RSQRTE: return "frsqrte"; |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 629 | case Pfp_FRIM: return "frim"; |
| 630 | case Pfp_FRIN: return "frin"; |
| 631 | case Pfp_FRIP: return "frip"; |
| 632 | case Pfp_FRIZ: return "friz"; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 633 | case Pfp_DFPADD: return "dadd"; |
| 634 | case Pfp_DFPADDQ: return "daddq"; |
| 635 | case Pfp_DFPSUB: return "dsub"; |
| 636 | case Pfp_DFPSUBQ: return "dsubq"; |
| 637 | case Pfp_DFPMUL: return "dmul"; |
| 638 | case Pfp_DFPMULQ: return "dmulq"; |
| 639 | case Pfp_DFPDIV: return "ddivd"; |
| 640 | case Pfp_DFPDIVQ: return "ddivq"; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 641 | case Pfp_DCTDP: return "dctdp"; |
| 642 | case Pfp_DRSP: return "drsp"; |
| 643 | case Pfp_DCTFIX: return "dctfix"; |
| 644 | case Pfp_DCFFIX: return "dcffix"; |
| 645 | case Pfp_DCTQPQ: return "dctqpq"; |
| 646 | case Pfp_DCFFIXQ: return "dcffixq"; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 647 | case Pfp_DQUA: return "dqua"; |
| 648 | case Pfp_DQUAQ: return "dquaq"; |
| 649 | case Pfp_DXEX: return "dxex"; |
| 650 | case Pfp_DXEXQ: return "dxexq"; |
| 651 | case Pfp_DIEX: return "diex"; |
| 652 | case Pfp_DIEXQ: return "diexq"; |
| 653 | case Pfp_RRDTR: return "rrdtr"; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 654 | default: vpanic("showPPCFpOp"); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 655 | } |
| 656 | } |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 657 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 658 | const HChar* showPPCAvOp ( PPCAvOp op ) { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 659 | switch (op) { |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 660 | |
| 661 | /* Unary */ |
| 662 | case Pav_MOV: return "vmr"; /* Mov */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 663 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 664 | case Pav_AND: return "vand"; /* Bitwise */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 665 | case Pav_OR: return "vor"; |
| 666 | case Pav_XOR: return "vxor"; |
| 667 | case Pav_NOT: return "vnot"; |
| 668 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 669 | case Pav_UNPCKH8S: return "vupkhsb"; /* Unpack */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 670 | case Pav_UNPCKH16S: return "vupkhsh"; |
| 671 | case Pav_UNPCKL8S: return "vupklsb"; |
| 672 | case Pav_UNPCKL16S: return "vupklsh"; |
| 673 | case Pav_UNPCKHPIX: return "vupkhpx"; |
| 674 | case Pav_UNPCKLPIX: return "vupklpx"; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 675 | |
| 676 | /* Integer binary */ |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 677 | case Pav_ADDU: return "vaddu_m"; // b,h,w,dw |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 678 | case Pav_QADDU: return "vaddu_s"; // b,h,w,dw |
| 679 | case Pav_QADDS: return "vadds_s"; // b,h,w,dw |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 680 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 681 | case Pav_SUBU: return "vsubu_m"; // b,h,w,dw |
| 682 | case Pav_QSUBU: return "vsubu_s"; // b,h,w,dw |
| 683 | case Pav_QSUBS: return "vsubs_s"; // b,h,w,dw |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 684 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 685 | case Pav_MULU: return "vmulu"; // w |
| 686 | case Pav_OMULU: return "vmulou"; // b,h,w |
| 687 | case Pav_OMULS: return "vmulos"; // b,h,w |
| 688 | case Pav_EMULU: return "vmuleu"; // b,h,w |
| 689 | case Pav_EMULS: return "vmules"; // b,h,w |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 690 | |
| 691 | case Pav_AVGU: return "vavgu"; // b,h,w |
| 692 | case Pav_AVGS: return "vavgs"; // b,h,w |
| 693 | |
| 694 | case Pav_MAXU: return "vmaxu"; // b,h,w |
| 695 | case Pav_MAXS: return "vmaxs"; // b,h,w |
| 696 | |
| 697 | case Pav_MINU: return "vminu"; // b,h,w |
| 698 | case Pav_MINS: return "vmins"; // b,h,w |
| 699 | |
| 700 | /* Compare (always affects CR field 6) */ |
| 701 | case Pav_CMPEQU: return "vcmpequ"; // b,h,w |
| 702 | case Pav_CMPGTU: return "vcmpgtu"; // b,h,w |
| 703 | case Pav_CMPGTS: return "vcmpgts"; // b,h,w |
| 704 | |
| 705 | /* Shift */ |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 706 | case Pav_SHL: return "vsl"; // ' ',b,h,w,dw |
| 707 | case Pav_SHR: return "vsr"; // ' ',b,h,w,dw |
| 708 | case Pav_SAR: return "vsra"; // b,h,w,dw |
| 709 | case Pav_ROTL: return "vrl"; // b,h,w,dw |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 710 | |
| 711 | /* Pack */ |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 712 | case Pav_PACKUU: return "vpku_um"; // h,w,dw |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 713 | case Pav_QPACKUU: return "vpku_us"; // h,w |
| 714 | case Pav_QPACKSU: return "vpks_us"; // h,w |
| 715 | case Pav_QPACKSS: return "vpks_ss"; // h,w |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 716 | case Pav_PACKPXL: return "vpkpx"; |
| 717 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 718 | /* Merge */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 719 | case Pav_MRGHI: return "vmrgh"; // b,h,w |
| 720 | case Pav_MRGLO: return "vmrgl"; // b,h,w |
| 721 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 722 | /* Concatenation */ |
| 723 | case Pav_CATODD: return "vmrgow"; // w |
| 724 | case Pav_CATEVEN: return "vmrgew"; // w |
| 725 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 726 | /* SHA */ |
| 727 | case Pav_SHA256: return "vshasigmaw"; // w |
| 728 | case Pav_SHA512: return "vshasigmaw"; // dw |
| 729 | |
| 730 | /* BCD */ |
| 731 | case Pav_BCDAdd: return "bcdadd."; // qw |
| 732 | case Pav_BCDSub: return "bcdsub."; // qw |
| 733 | |
| 734 | /* Polynomial arith */ |
| 735 | case Pav_POLYMULADD: return "vpmsum"; // b, h, w, d |
| 736 | |
| 737 | /* Cipher */ |
| 738 | case Pav_CIPHERV128: case Pav_CIPHERLV128: |
| 739 | case Pav_NCIPHERV128: case Pav_NCIPHERLV128: |
| 740 | case Pav_CIPHERSUBV128: return "v_cipher_"; // qw |
| 741 | |
| 742 | /* zero count */ |
| 743 | case Pav_ZEROCNTBYTE: case Pav_ZEROCNTWORD: |
| 744 | case Pav_ZEROCNTHALF: case Pav_ZEROCNTDBL: |
| 745 | return "vclz_"; // b, h, w, d |
| 746 | |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 747 | /* vector gather (byte-by-byte bit matrix transpose) */ |
| 748 | case Pav_BITMTXXPOSE: |
| 749 | return "vgbbd"; |
| 750 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 751 | default: vpanic("showPPCAvOp"); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 752 | } |
| 753 | } |
| 754 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 755 | const HChar* showPPCAvFpOp ( PPCAvFpOp op ) { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 756 | switch (op) { |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 757 | /* Floating Point Binary */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 758 | case Pavfp_ADDF: return "vaddfp"; |
| 759 | case Pavfp_SUBF: return "vsubfp"; |
| 760 | case Pavfp_MULF: return "vmaddfp"; |
| 761 | case Pavfp_MAXF: return "vmaxfp"; |
| 762 | case Pavfp_MINF: return "vminfp"; |
| 763 | case Pavfp_CMPEQF: return "vcmpeqfp"; |
| 764 | case Pavfp_CMPGTF: return "vcmpgtfp"; |
| 765 | case Pavfp_CMPGEF: return "vcmpgefp"; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 766 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 767 | /* Floating Point Unary */ |
| 768 | case Pavfp_RCPF: return "vrefp"; |
| 769 | case Pavfp_RSQRTF: return "vrsqrtefp"; |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 770 | case Pavfp_CVTU2F: return "vcfux"; |
| 771 | case Pavfp_CVTS2F: return "vcfsx"; |
| 772 | case Pavfp_QCVTF2U: return "vctuxs"; |
| 773 | case Pavfp_QCVTF2S: return "vctsxs"; |
| 774 | case Pavfp_ROUNDM: return "vrfim"; |
| 775 | case Pavfp_ROUNDP: return "vrfip"; |
| 776 | case Pavfp_ROUNDN: return "vrfin"; |
| 777 | case Pavfp_ROUNDZ: return "vrfiz"; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 778 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 779 | default: vpanic("showPPCAvFpOp"); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 780 | } |
| 781 | } |
| 782 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 783 | PPCInstr* PPCInstr_LI ( HReg dst, ULong imm64, Bool mode64 ) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 784 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 785 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 786 | i->tag = Pin_LI; |
| 787 | i->Pin.LI.dst = dst; |
| 788 | i->Pin.LI.imm64 = imm64; |
| 789 | if (!mode64) |
| 790 | vassert( (Long)imm64 == (Long)(Int)(UInt)imm64 ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 791 | return i; |
| 792 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 793 | PPCInstr* PPCInstr_Alu ( PPCAluOp op, HReg dst, |
| 794 | HReg srcL, PPCRH* srcR ) { |
| 795 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 796 | i->tag = Pin_Alu; |
| 797 | i->Pin.Alu.op = op; |
| 798 | i->Pin.Alu.dst = dst; |
| 799 | i->Pin.Alu.srcL = srcL; |
| 800 | i->Pin.Alu.srcR = srcR; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 801 | return i; |
| 802 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 803 | PPCInstr* PPCInstr_Shft ( PPCShftOp op, Bool sz32, |
| 804 | HReg dst, HReg srcL, PPCRH* srcR ) { |
| 805 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 806 | i->tag = Pin_Shft; |
| 807 | i->Pin.Shft.op = op; |
| 808 | i->Pin.Shft.sz32 = sz32; |
| 809 | i->Pin.Shft.dst = dst; |
| 810 | i->Pin.Shft.srcL = srcL; |
| 811 | i->Pin.Shft.srcR = srcR; |
| 812 | return i; |
| 813 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 814 | PPCInstr* PPCInstr_AddSubC ( Bool isAdd, Bool setC, |
| 815 | HReg dst, HReg srcL, HReg srcR ) { |
| 816 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 817 | i->tag = Pin_AddSubC; |
| 818 | i->Pin.AddSubC.isAdd = isAdd; |
| 819 | i->Pin.AddSubC.setC = setC; |
| 820 | i->Pin.AddSubC.dst = dst; |
| 821 | i->Pin.AddSubC.srcL = srcL; |
| 822 | i->Pin.AddSubC.srcR = srcR; |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 823 | return i; |
| 824 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 825 | PPCInstr* PPCInstr_Cmp ( Bool syned, Bool sz32, |
| 826 | UInt crfD, HReg srcL, PPCRH* srcR ) { |
| 827 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 828 | i->tag = Pin_Cmp; |
| 829 | i->Pin.Cmp.syned = syned; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 830 | i->Pin.Cmp.sz32 = sz32; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 831 | i->Pin.Cmp.crfD = crfD; |
| 832 | i->Pin.Cmp.srcL = srcL; |
| 833 | i->Pin.Cmp.srcR = srcR; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 834 | return i; |
| 835 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 836 | PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src ) { |
| 837 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 838 | i->tag = Pin_Unary; |
| 839 | i->Pin.Unary.op = op; |
| 840 | i->Pin.Unary.dst = dst; |
| 841 | i->Pin.Unary.src = src; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 842 | return i; |
| 843 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 844 | PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi, Bool sz32, |
| 845 | HReg dst, HReg srcL, HReg srcR ) { |
| 846 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 847 | i->tag = Pin_MulL; |
| 848 | i->Pin.MulL.syned = syned; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 849 | i->Pin.MulL.hi = hi; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 850 | i->Pin.MulL.sz32 = sz32; |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 851 | i->Pin.MulL.dst = dst; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 852 | i->Pin.MulL.srcL = srcL; |
| 853 | i->Pin.MulL.srcR = srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 854 | /* if doing the low word, the signedness is irrelevant, but tie it |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 855 | down anyway. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 856 | if (!hi) vassert(!syned); |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 857 | return i; |
| 858 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 859 | PPCInstr* PPCInstr_Div ( Bool extended, Bool syned, Bool sz32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 860 | HReg dst, HReg srcL, HReg srcR ) { |
| 861 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 862 | i->tag = Pin_Div; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 863 | i->Pin.Div.extended = extended; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 864 | i->Pin.Div.syned = syned; |
| 865 | i->Pin.Div.sz32 = sz32; |
| 866 | i->Pin.Div.dst = dst; |
| 867 | i->Pin.Div.srcL = srcL; |
| 868 | i->Pin.Div.srcR = srcR; |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 869 | return i; |
| 870 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 871 | PPCInstr* PPCInstr_Call ( PPCCondCode cond, |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 872 | Addr64 target, UInt argiregs, RetLoc rloc ) { |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 873 | UInt mask; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 874 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 875 | i->tag = Pin_Call; |
| 876 | i->Pin.Call.cond = cond; |
| 877 | i->Pin.Call.target = target; |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 878 | i->Pin.Call.argiregs = argiregs; |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 879 | i->Pin.Call.rloc = rloc; |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 880 | /* Only r3 .. r10 inclusive may be used as arg regs. Hence: */ |
| 881 | mask = (1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<10); |
| 882 | vassert(0 == (argiregs & ~mask)); |
sewardj | 74142b8 | 2013-08-08 10:28:59 +0000 | [diff] [blame] | 883 | vassert(is_sane_RetLoc(rloc)); |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 884 | return i; |
| 885 | } |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 886 | PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA, |
| 887 | PPCCondCode cond, Bool toFastEP ) { |
| 888 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 889 | i->tag = Pin_XDirect; |
| 890 | i->Pin.XDirect.dstGA = dstGA; |
| 891 | i->Pin.XDirect.amCIA = amCIA; |
| 892 | i->Pin.XDirect.cond = cond; |
| 893 | i->Pin.XDirect.toFastEP = toFastEP; |
| 894 | return i; |
| 895 | } |
| 896 | PPCInstr* PPCInstr_XIndir ( HReg dstGA, PPCAMode* amCIA, |
| 897 | PPCCondCode cond ) { |
| 898 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 899 | i->tag = Pin_XIndir; |
| 900 | i->Pin.XIndir.dstGA = dstGA; |
| 901 | i->Pin.XIndir.amCIA = amCIA; |
| 902 | i->Pin.XIndir.cond = cond; |
| 903 | return i; |
| 904 | } |
| 905 | PPCInstr* PPCInstr_XAssisted ( HReg dstGA, PPCAMode* amCIA, |
| 906 | PPCCondCode cond, IRJumpKind jk ) { |
| 907 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 908 | i->tag = Pin_XAssisted; |
| 909 | i->Pin.XAssisted.dstGA = dstGA; |
| 910 | i->Pin.XAssisted.amCIA = amCIA; |
| 911 | i->Pin.XAssisted.cond = cond; |
| 912 | i->Pin.XAssisted.jk = jk; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 913 | return i; |
| 914 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 915 | PPCInstr* PPCInstr_CMov ( PPCCondCode cond, |
| 916 | HReg dst, PPCRI* src ) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 917 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 918 | i->tag = Pin_CMov; |
| 919 | i->Pin.CMov.cond = cond; |
| 920 | i->Pin.CMov.src = src; |
| 921 | i->Pin.CMov.dst = dst; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 922 | vassert(cond.test != Pct_ALWAYS); |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 923 | return i; |
| 924 | } |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 925 | PPCInstr* PPCInstr_Load ( UChar sz, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 926 | HReg dst, PPCAMode* src, Bool mode64 ) { |
| 927 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 928 | i->tag = Pin_Load; |
| 929 | i->Pin.Load.sz = sz; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 930 | i->Pin.Load.src = src; |
| 931 | i->Pin.Load.dst = dst; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 932 | vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8); |
| 933 | if (sz == 8) vassert(mode64); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 934 | return i; |
| 935 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 936 | PPCInstr* PPCInstr_LoadL ( UChar sz, |
| 937 | HReg dst, HReg src, Bool mode64 ) |
| 938 | { |
| 939 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 940 | i->tag = Pin_LoadL; |
| 941 | i->Pin.LoadL.sz = sz; |
| 942 | i->Pin.LoadL.src = src; |
| 943 | i->Pin.LoadL.dst = dst; |
| 944 | vassert(sz == 4 || sz == 8); |
| 945 | if (sz == 8) vassert(mode64); |
| 946 | return i; |
| 947 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 948 | PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst, HReg src, |
| 949 | Bool mode64 ) { |
| 950 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 951 | i->tag = Pin_Store; |
| 952 | i->Pin.Store.sz = sz; |
| 953 | i->Pin.Store.src = src; |
| 954 | i->Pin.Store.dst = dst; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 955 | vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8); |
| 956 | if (sz == 8) vassert(mode64); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 957 | return i; |
| 958 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 959 | PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src, Bool mode64 ) { |
| 960 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 961 | i->tag = Pin_StoreC; |
| 962 | i->Pin.StoreC.sz = sz; |
| 963 | i->Pin.StoreC.src = src; |
| 964 | i->Pin.StoreC.dst = dst; |
| 965 | vassert(sz == 4 || sz == 8); |
| 966 | if (sz == 8) vassert(mode64); |
| 967 | return i; |
| 968 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 969 | PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst ) { |
| 970 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 971 | i->tag = Pin_Set; |
| 972 | i->Pin.Set.cond = cond; |
| 973 | i->Pin.Set.dst = dst; |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 974 | return i; |
| 975 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 976 | PPCInstr* PPCInstr_MfCR ( HReg dst ) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 977 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 978 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 979 | i->tag = Pin_MfCR; |
| 980 | i->Pin.MfCR.dst = dst; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 981 | return i; |
| 982 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 983 | PPCInstr* PPCInstr_MFence ( void ) |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 984 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 985 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 986 | i->tag = Pin_MFence; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 987 | return i; |
| 988 | } |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 989 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 990 | PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src ) { |
| 991 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 992 | i->tag = Pin_FpUnary; |
| 993 | i->Pin.FpUnary.op = op; |
| 994 | i->Pin.FpUnary.dst = dst; |
| 995 | i->Pin.FpUnary.src = src; |
| 996 | return i; |
| 997 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 998 | PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, |
| 999 | HReg srcL, HReg srcR ) { |
| 1000 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1001 | i->tag = Pin_FpBinary; |
| 1002 | i->Pin.FpBinary.op = op; |
| 1003 | i->Pin.FpBinary.dst = dst; |
| 1004 | i->Pin.FpBinary.srcL = srcL; |
| 1005 | i->Pin.FpBinary.srcR = srcR; |
| 1006 | return i; |
| 1007 | } |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 1008 | PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, |
| 1009 | HReg srcMR, HReg srcAcc ) |
| 1010 | { |
| 1011 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1012 | i->tag = Pin_FpMulAcc; |
| 1013 | i->Pin.FpMulAcc.op = op; |
| 1014 | i->Pin.FpMulAcc.dst = dst; |
| 1015 | i->Pin.FpMulAcc.srcML = srcML; |
| 1016 | i->Pin.FpMulAcc.srcMR = srcMR; |
| 1017 | i->Pin.FpMulAcc.srcAcc = srcAcc; |
| 1018 | return i; |
| 1019 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1020 | PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, |
| 1021 | HReg reg, PPCAMode* addr ) { |
| 1022 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1023 | i->tag = Pin_FpLdSt; |
| 1024 | i->Pin.FpLdSt.isLoad = isLoad; |
| 1025 | i->Pin.FpLdSt.sz = sz; |
| 1026 | i->Pin.FpLdSt.reg = reg; |
| 1027 | i->Pin.FpLdSt.addr = addr; |
| 1028 | vassert(sz == 4 || sz == 8); |
| 1029 | return i; |
| 1030 | } |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1031 | PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data ) |
| 1032 | { |
| 1033 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1034 | i->tag = Pin_FpSTFIW; |
| 1035 | i->Pin.FpSTFIW.addr = addr; |
| 1036 | i->Pin.FpSTFIW.data = data; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1037 | return i; |
| 1038 | } |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1039 | PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ) { |
| 1040 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1041 | i->tag = Pin_FpRSP; |
| 1042 | i->Pin.FpRSP.dst = dst; |
| 1043 | i->Pin.FpRSP.src = src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1044 | return i; |
| 1045 | } |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1046 | PPCInstr* PPCInstr_Dfp64Unary(PPCFpOp op, HReg dst, HReg src) { |
| 1047 | PPCInstr* i = LibVEX_Alloc( sizeof(PPCInstr) ); |
| 1048 | i->tag = Pin_Dfp64Unary; |
| 1049 | i->Pin.Dfp64Unary.op = op; |
| 1050 | i->Pin.Dfp64Unary.dst = dst; |
| 1051 | i->Pin.Dfp64Unary.src = src; |
| 1052 | return i; |
| 1053 | } |
| 1054 | PPCInstr* PPCInstr_Dfp64Binary(PPCFpOp op, HReg dst, HReg srcL, HReg srcR) { |
| 1055 | PPCInstr* i = LibVEX_Alloc( sizeof(PPCInstr) ); |
| 1056 | i->tag = Pin_Dfp64Binary; |
| 1057 | i->Pin.Dfp64Binary.op = op; |
| 1058 | i->Pin.Dfp64Binary.dst = dst; |
| 1059 | i->Pin.Dfp64Binary.srcL = srcL; |
| 1060 | i->Pin.Dfp64Binary.srcR = srcR; |
| 1061 | return i; |
| 1062 | } |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1063 | PPCInstr* PPCInstr_DfpShift ( PPCFpOp op, HReg dst, HReg src, PPCRI* shift ) { |
| 1064 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1065 | i->tag = Pin_DfpShift; |
| 1066 | i->Pin.DfpShift.op = op; |
| 1067 | i->Pin.DfpShift.shift = shift; |
| 1068 | i->Pin.DfpShift.src = src; |
| 1069 | i->Pin.DfpShift.dst = dst; |
| 1070 | return i; |
| 1071 | } |
| 1072 | PPCInstr* PPCInstr_Dfp128Unary(PPCFpOp op, HReg dst_hi, HReg dst_lo, |
| 1073 | HReg src_hi, HReg src_lo) { |
| 1074 | PPCInstr* i = LibVEX_Alloc( sizeof(PPCInstr) ); |
| 1075 | i->tag = Pin_Dfp128Unary; |
| 1076 | i->Pin.Dfp128Unary.op = op; |
| 1077 | i->Pin.Dfp128Unary.dst_hi = dst_hi; |
| 1078 | i->Pin.Dfp128Unary.dst_lo = dst_lo; |
| 1079 | i->Pin.Dfp128Unary.src_hi = src_hi; |
| 1080 | i->Pin.Dfp128Unary.src_lo = src_lo; |
| 1081 | return i; |
| 1082 | } |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1083 | PPCInstr* PPCInstr_Dfp128Binary(PPCFpOp op, HReg dst_hi, HReg dst_lo, |
| 1084 | HReg srcR_hi, HReg srcR_lo) { |
| 1085 | /* dst is used to pass the srcL argument and return the result */ |
| 1086 | PPCInstr* i = LibVEX_Alloc( sizeof(PPCInstr) ); |
| 1087 | i->tag = Pin_Dfp128Binary; |
| 1088 | i->Pin.Dfp128Binary.op = op; |
| 1089 | i->Pin.Dfp128Binary.dst_hi = dst_hi; |
| 1090 | i->Pin.Dfp128Binary.dst_lo = dst_lo; |
| 1091 | i->Pin.Dfp128Binary.srcR_hi = srcR_hi; |
| 1092 | i->Pin.Dfp128Binary.srcR_lo = srcR_lo; |
| 1093 | return i; |
| 1094 | } |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1095 | PPCInstr* PPCInstr_DfpShift128 ( PPCFpOp op, HReg dst_hi, HReg dst_lo, |
| 1096 | HReg src_hi, HReg src_lo, |
| 1097 | PPCRI* shift ) { |
| 1098 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1099 | i->tag = Pin_DfpShift128; |
| 1100 | i->Pin.DfpShift128.op = op; |
| 1101 | i->Pin.DfpShift128.shift = shift; |
| 1102 | i->Pin.DfpShift128.src_hi = src_hi; |
| 1103 | i->Pin.DfpShift128.src_lo = src_lo; |
| 1104 | i->Pin.DfpShift128.dst_hi = dst_hi; |
| 1105 | i->Pin.DfpShift128.dst_lo = dst_lo; |
| 1106 | return i; |
| 1107 | } |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1108 | PPCInstr* PPCInstr_DfpRound ( HReg dst, HReg src, PPCRI* r_rmc ) { |
| 1109 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1110 | i->tag = Pin_DfpRound; |
| 1111 | i->Pin.DfpRound.dst = dst; |
| 1112 | i->Pin.DfpRound.src = src; |
| 1113 | i->Pin.DfpRound.r_rmc = r_rmc; |
| 1114 | return i; |
| 1115 | } |
| 1116 | PPCInstr* PPCInstr_DfpRound128 ( HReg dst_hi, HReg dst_lo, HReg src_hi, |
| 1117 | HReg src_lo, PPCRI* r_rmc ) { |
| 1118 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1119 | i->tag = Pin_DfpRound128; |
| 1120 | i->Pin.DfpRound128.dst_hi = dst_hi; |
| 1121 | i->Pin.DfpRound128.dst_lo = dst_lo; |
| 1122 | i->Pin.DfpRound128.src_hi = src_hi; |
| 1123 | i->Pin.DfpRound128.src_lo = src_lo; |
| 1124 | i->Pin.DfpRound128.r_rmc = r_rmc; |
| 1125 | return i; |
| 1126 | } |
florian | a7b0d10 | 2012-06-15 20:55:43 +0000 | [diff] [blame] | 1127 | PPCInstr* PPCInstr_DfpQuantize ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1128 | PPCRI* rmc ) { |
| 1129 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1130 | i->tag = Pin_DfpQuantize; |
| 1131 | i->Pin.DfpQuantize.op = op; |
| 1132 | i->Pin.DfpQuantize.dst = dst; |
| 1133 | i->Pin.DfpQuantize.srcL = srcL; |
| 1134 | i->Pin.DfpQuantize.srcR = srcR; |
| 1135 | i->Pin.DfpQuantize.rmc = rmc; |
| 1136 | return i; |
| 1137 | } |
florian | a7b0d10 | 2012-06-15 20:55:43 +0000 | [diff] [blame] | 1138 | PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi, HReg dst_lo, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1139 | HReg src_hi, HReg src_lo, PPCRI* rmc ) { |
| 1140 | /* dst is used to pass left operand in and return result */ |
| 1141 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1142 | i->tag = Pin_DfpQuantize128; |
| 1143 | i->Pin.DfpQuantize128.op = op; |
| 1144 | i->Pin.DfpQuantize128.dst_hi = dst_hi; |
| 1145 | i->Pin.DfpQuantize128.dst_lo = dst_lo; |
| 1146 | i->Pin.DfpQuantize128.src_hi = src_hi; |
| 1147 | i->Pin.DfpQuantize128.src_lo = src_lo; |
| 1148 | i->Pin.DfpQuantize128.rmc = rmc; |
| 1149 | return i; |
| 1150 | } |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1151 | PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst, |
| 1152 | HReg src_hi, HReg src_lo ) { |
| 1153 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1154 | i->tag = Pin_DfpD128toD64; |
| 1155 | i->Pin.DfpD128toD64.op = op; |
| 1156 | i->Pin.DfpD128toD64.src_hi = src_hi; |
| 1157 | i->Pin.DfpD128toD64.src_lo = src_lo; |
| 1158 | i->Pin.DfpD128toD64.dst = dst; |
| 1159 | return i; |
| 1160 | } |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1161 | PPCInstr* PPCInstr_DfpI64StoD128 ( PPCFpOp op, HReg dst_hi, |
| 1162 | HReg dst_lo, HReg src ) { |
| 1163 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1164 | i->tag = Pin_DfpI64StoD128; |
| 1165 | i->Pin.DfpI64StoD128.op = op; |
| 1166 | i->Pin.DfpI64StoD128.src = src; |
| 1167 | i->Pin.DfpI64StoD128.dst_hi = dst_hi; |
| 1168 | i->Pin.DfpI64StoD128.dst_lo = dst_lo; |
| 1169 | return i; |
| 1170 | } |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1171 | PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op, HReg dst, |
| 1172 | HReg src_hi, HReg src_lo ) { |
| 1173 | /* dst is used to pass the srcL argument */ |
| 1174 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1175 | i->tag = Pin_ExtractExpD128; |
| 1176 | i->Pin.ExtractExpD128.op = op; |
| 1177 | i->Pin.ExtractExpD128.dst = dst; |
| 1178 | i->Pin.ExtractExpD128.src_hi = src_hi; |
| 1179 | i->Pin.ExtractExpD128.src_lo = src_lo; |
| 1180 | return i; |
| 1181 | } |
| 1182 | PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi, HReg dst_lo, |
| 1183 | HReg srcL, HReg srcR_hi, HReg srcR_lo ) { |
| 1184 | /* dst is used to pass the srcL argument */ |
| 1185 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1186 | i->tag = Pin_InsertExpD128; |
| 1187 | i->Pin.InsertExpD128.op = op; |
| 1188 | i->Pin.InsertExpD128.dst_hi = dst_hi; |
| 1189 | i->Pin.InsertExpD128.dst_lo = dst_lo; |
| 1190 | i->Pin.InsertExpD128.srcL = srcL; |
| 1191 | i->Pin.InsertExpD128.srcR_hi = srcR_hi; |
| 1192 | i->Pin.InsertExpD128.srcR_lo = srcR_lo; |
| 1193 | return i; |
| 1194 | } |
| 1195 | PPCInstr* PPCInstr_Dfp64Cmp (/* UInt crfD,*/ HReg dst, HReg srcL, HReg srcR ) { |
| 1196 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1197 | i->tag = Pin_Dfp64Cmp; |
| 1198 | i->Pin.Dfp64Cmp.dst = dst; |
| 1199 | i->Pin.Dfp64Cmp.srcL = srcL; |
| 1200 | i->Pin.Dfp64Cmp.srcR = srcR; |
| 1201 | return i; |
| 1202 | } |
| 1203 | PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo, |
| 1204 | HReg srcR_hi, HReg srcR_lo ) { |
| 1205 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1206 | i->tag = Pin_Dfp128Cmp; |
| 1207 | i->Pin.Dfp128Cmp.dst = dst; |
| 1208 | i->Pin.Dfp128Cmp.srcL_hi = srcL_hi; |
| 1209 | i->Pin.Dfp128Cmp.srcL_lo = srcL_lo; |
| 1210 | i->Pin.Dfp128Cmp.srcR_hi = srcR_hi; |
| 1211 | i->Pin.Dfp128Cmp.srcR_lo = srcR_lo; |
| 1212 | return i; |
| 1213 | } |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1214 | PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter, |
| 1215 | PPCAMode* amFailAddr ) { |
| 1216 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1217 | i->tag = Pin_EvCheck; |
| 1218 | i->Pin.EvCheck.amCounter = amCounter; |
| 1219 | i->Pin.EvCheck.amFailAddr = amFailAddr; |
| 1220 | return i; |
| 1221 | } |
| 1222 | PPCInstr* PPCInstr_ProfInc ( void ) { |
| 1223 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1224 | i->tag = Pin_ProfInc; |
| 1225 | return i; |
| 1226 | } |
| 1227 | |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 1228 | /* |
| 1229 | Valid combo | fromI | int32 | syned | flt64 | |
| 1230 | -------------------------------------------- |
| 1231 | | n n n n | |
| 1232 | -------------------------------------------- |
| 1233 | F64->I64U | n n n y | |
| 1234 | -------------------------------------------- |
| 1235 | | n n y n | |
| 1236 | -------------------------------------------- |
| 1237 | F64->I64S | n n y y | |
| 1238 | -------------------------------------------- |
| 1239 | | n y n n | |
| 1240 | -------------------------------------------- |
| 1241 | F64->I32U | n y n y | |
| 1242 | -------------------------------------------- |
| 1243 | | n y y n | |
| 1244 | -------------------------------------------- |
| 1245 | F64->I32S | n y y y | |
| 1246 | -------------------------------------------- |
| 1247 | I64U->F32 | y n n n | |
| 1248 | -------------------------------------------- |
| 1249 | I64U->F64 | y n n y | |
| 1250 | -------------------------------------------- |
| 1251 | | y n y n | |
| 1252 | -------------------------------------------- |
| 1253 | I64S->F64 | y n y y | |
| 1254 | -------------------------------------------- |
| 1255 | | y y n n | |
| 1256 | -------------------------------------------- |
| 1257 | | y y n y | |
| 1258 | -------------------------------------------- |
| 1259 | | y y y n | |
| 1260 | -------------------------------------------- |
| 1261 | | y y y y | |
| 1262 | -------------------------------------------- |
| 1263 | */ |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1264 | PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, Bool syned, |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 1265 | Bool flt64, HReg dst, HReg src ) { |
| 1266 | Bool tmp = fromI | int32 | syned | flt64; |
| 1267 | vassert(tmp == True || tmp == False); // iow, no high bits set |
| 1268 | UShort conversion = 0; |
| 1269 | conversion = (fromI << 3) | (int32 << 2) | (syned << 1) | flt64; |
| 1270 | switch (conversion) { |
| 1271 | // Supported conversion operations |
| 1272 | case 1: case 3: case 5: case 7: |
| 1273 | case 8: case 9: case 11: |
| 1274 | break; |
| 1275 | default: |
| 1276 | vpanic("PPCInstr_FpCftI(ppc_host)"); |
| 1277 | } |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1278 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1279 | i->tag = Pin_FpCftI; |
| 1280 | i->Pin.FpCftI.fromI = fromI; |
| 1281 | i->Pin.FpCftI.int32 = int32; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1282 | i->Pin.FpCftI.syned = syned; |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 1283 | i->Pin.FpCftI.flt64 = flt64; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1284 | i->Pin.FpCftI.dst = dst; |
| 1285 | i->Pin.FpCftI.src = src; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 1286 | return i; |
| 1287 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1288 | PPCInstr* PPCInstr_FpCMov ( PPCCondCode cond, HReg dst, HReg src ) { |
| 1289 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1290 | i->tag = Pin_FpCMov; |
| 1291 | i->Pin.FpCMov.cond = cond; |
| 1292 | i->Pin.FpCMov.dst = dst; |
| 1293 | i->Pin.FpCMov.src = src; |
| 1294 | vassert(cond.test != Pct_ALWAYS); |
| 1295 | return i; |
| 1296 | } |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1297 | PPCInstr* PPCInstr_FpLdFPSCR ( HReg src, Bool dfp_rm ) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1298 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1299 | i->tag = Pin_FpLdFPSCR; |
| 1300 | i->Pin.FpLdFPSCR.src = src; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1301 | i->Pin.FpLdFPSCR.dfp_rm = dfp_rm ? 1 : 0; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1302 | return i; |
| 1303 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1304 | PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR ) { |
| 1305 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1306 | i->tag = Pin_FpCmp; |
| 1307 | i->Pin.FpCmp.dst = dst; |
| 1308 | i->Pin.FpCmp.srcL = srcL; |
| 1309 | i->Pin.FpCmp.srcR = srcR; |
| 1310 | return i; |
| 1311 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1312 | |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 1313 | /* Read/Write Link Register */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1314 | PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr ) { |
| 1315 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 1316 | i->tag = Pin_RdWrLR; |
| 1317 | i->Pin.RdWrLR.wrLR = wrLR; |
| 1318 | i->Pin.RdWrLR.gpr = gpr; |
| 1319 | return i; |
| 1320 | } |
| 1321 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1322 | /* AltiVec */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1323 | PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, |
| 1324 | HReg reg, PPCAMode* addr ) { |
| 1325 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1326 | i->tag = Pin_AvLdSt; |
| 1327 | i->Pin.AvLdSt.isLoad = isLoad; |
| 1328 | i->Pin.AvLdSt.sz = sz; |
| 1329 | i->Pin.AvLdSt.reg = reg; |
| 1330 | i->Pin.AvLdSt.addr = addr; |
| 1331 | return i; |
| 1332 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1333 | PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src ) { |
| 1334 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 1335 | i->tag = Pin_AvUnary; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1336 | i->Pin.AvUnary.op = op; |
| 1337 | i->Pin.AvUnary.dst = dst; |
| 1338 | i->Pin.AvUnary.src = src; |
| 1339 | return i; |
| 1340 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1341 | PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, |
| 1342 | HReg srcL, HReg srcR ) { |
| 1343 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1344 | i->tag = Pin_AvBinary; |
| 1345 | i->Pin.AvBinary.op = op; |
| 1346 | i->Pin.AvBinary.dst = dst; |
| 1347 | i->Pin.AvBinary.srcL = srcL; |
| 1348 | i->Pin.AvBinary.srcR = srcR; |
| 1349 | return i; |
| 1350 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1351 | PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, |
| 1352 | HReg srcL, HReg srcR ) { |
| 1353 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1354 | i->tag = Pin_AvBin8x16; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1355 | i->Pin.AvBin8x16.op = op; |
| 1356 | i->Pin.AvBin8x16.dst = dst; |
| 1357 | i->Pin.AvBin8x16.srcL = srcL; |
| 1358 | i->Pin.AvBin8x16.srcR = srcR; |
| 1359 | return i; |
| 1360 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1361 | PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, |
| 1362 | HReg srcL, HReg srcR ) { |
| 1363 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1364 | i->tag = Pin_AvBin16x8; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1365 | i->Pin.AvBin16x8.op = op; |
| 1366 | i->Pin.AvBin16x8.dst = dst; |
| 1367 | i->Pin.AvBin16x8.srcL = srcL; |
| 1368 | i->Pin.AvBin16x8.srcR = srcR; |
| 1369 | return i; |
| 1370 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1371 | PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, |
| 1372 | HReg srcL, HReg srcR ) { |
| 1373 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1374 | i->tag = Pin_AvBin32x4; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1375 | i->Pin.AvBin32x4.op = op; |
| 1376 | i->Pin.AvBin32x4.dst = dst; |
| 1377 | i->Pin.AvBin32x4.srcL = srcL; |
| 1378 | i->Pin.AvBin32x4.srcR = srcR; |
| 1379 | return i; |
| 1380 | } |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1381 | PPCInstr* PPCInstr_AvBin64x2 ( PPCAvOp op, HReg dst, |
| 1382 | HReg srcL, HReg srcR ) { |
| 1383 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1384 | i->tag = Pin_AvBin64x2; |
| 1385 | i->Pin.AvBin64x2.op = op; |
| 1386 | i->Pin.AvBin64x2.dst = dst; |
| 1387 | i->Pin.AvBin64x2.srcL = srcL; |
| 1388 | i->Pin.AvBin64x2.srcR = srcR; |
| 1389 | return i; |
| 1390 | } |
| 1391 | |
sewardj | e522d4b | 2011-04-26 21:36:09 +0000 | [diff] [blame] | 1392 | PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1393 | HReg srcL, HReg srcR ) { |
| 1394 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1395 | i->tag = Pin_AvBin32Fx4; |
| 1396 | i->Pin.AvBin32Fx4.op = op; |
| 1397 | i->Pin.AvBin32Fx4.dst = dst; |
| 1398 | i->Pin.AvBin32Fx4.srcL = srcL; |
| 1399 | i->Pin.AvBin32Fx4.srcR = srcR; |
| 1400 | return i; |
| 1401 | } |
sewardj | e522d4b | 2011-04-26 21:36:09 +0000 | [diff] [blame] | 1402 | PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvFpOp op, HReg dst, HReg src ) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1403 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 1404 | i->tag = Pin_AvUn32Fx4; |
| 1405 | i->Pin.AvUn32Fx4.op = op; |
| 1406 | i->Pin.AvUn32Fx4.dst = dst; |
| 1407 | i->Pin.AvUn32Fx4.src = src; |
| 1408 | return i; |
| 1409 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1410 | PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl ) { |
| 1411 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1412 | i->tag = Pin_AvPerm; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1413 | i->Pin.AvPerm.dst = dst; |
| 1414 | i->Pin.AvPerm.srcL = srcL; |
| 1415 | i->Pin.AvPerm.srcR = srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 1416 | i->Pin.AvPerm.ctl = ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1417 | return i; |
| 1418 | } |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 1419 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1420 | PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR ) { |
| 1421 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1422 | i->tag = Pin_AvSel; |
| 1423 | i->Pin.AvSel.ctl = ctl; |
| 1424 | i->Pin.AvSel.dst = dst; |
| 1425 | i->Pin.AvSel.srcL = srcL; |
| 1426 | i->Pin.AvSel.srcR = srcR; |
| 1427 | return i; |
| 1428 | } |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 1429 | PPCInstr* PPCInstr_AvSh ( Bool shLeft, HReg dst, PPCAMode* addr ) { |
carll | 99de41e | 2014-10-07 18:20:39 +0000 | [diff] [blame] | 1430 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 1431 | i->tag = Pin_AvSh; |
| 1432 | i->Pin.AvSh.shLeft = shLeft; |
| 1433 | i->Pin.AvSh.dst = dst; |
| 1434 | i->Pin.AvSh.addr = addr; |
| 1435 | return i; |
| 1436 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1437 | PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, |
| 1438 | HReg srcL, HReg srcR ) { |
| 1439 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1440 | i->tag = Pin_AvShlDbl; |
| 1441 | i->Pin.AvShlDbl.shift = shift; |
| 1442 | i->Pin.AvShlDbl.dst = dst; |
| 1443 | i->Pin.AvShlDbl.srcL = srcL; |
| 1444 | i->Pin.AvShlDbl.srcR = srcR; |
| 1445 | return i; |
| 1446 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1447 | PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src ) { |
| 1448 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1449 | i->tag = Pin_AvSplat; |
| 1450 | i->Pin.AvSplat.sz = sz; |
| 1451 | i->Pin.AvSplat.dst = dst; |
| 1452 | i->Pin.AvSplat.src = src; |
| 1453 | return i; |
| 1454 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1455 | PPCInstr* PPCInstr_AvCMov ( PPCCondCode cond, HReg dst, HReg src ) { |
| 1456 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1457 | i->tag = Pin_AvCMov; |
| 1458 | i->Pin.AvCMov.cond = cond; |
| 1459 | i->Pin.AvCMov.dst = dst; |
| 1460 | i->Pin.AvCMov.src = src; |
| 1461 | vassert(cond.test != Pct_ALWAYS); |
| 1462 | return i; |
| 1463 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1464 | PPCInstr* PPCInstr_AvLdVSCR ( HReg src ) { |
| 1465 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1466 | i->tag = Pin_AvLdVSCR; |
| 1467 | i->Pin.AvLdVSCR.src = src; |
| 1468 | return i; |
| 1469 | } |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1470 | PPCInstr* PPCInstr_AvCipherV128Unary ( PPCAvOp op, HReg dst, HReg src ) { |
| 1471 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1472 | i->tag = Pin_AvCipherV128Unary; |
| 1473 | i->Pin.AvCipherV128Unary.op = op; |
| 1474 | i->Pin.AvCipherV128Unary.dst = dst; |
| 1475 | i->Pin.AvCipherV128Unary.src = src; |
| 1476 | return i; |
| 1477 | } |
| 1478 | PPCInstr* PPCInstr_AvCipherV128Binary ( PPCAvOp op, HReg dst, |
| 1479 | HReg srcL, HReg srcR ) { |
| 1480 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1481 | i->tag = Pin_AvCipherV128Binary; |
| 1482 | i->Pin.AvCipherV128Binary.op = op; |
| 1483 | i->Pin.AvCipherV128Binary.dst = dst; |
| 1484 | i->Pin.AvCipherV128Binary.srcL = srcL; |
| 1485 | i->Pin.AvCipherV128Binary.srcR = srcR; |
| 1486 | return i; |
| 1487 | } |
| 1488 | PPCInstr* PPCInstr_AvHashV128Binary ( PPCAvOp op, HReg dst, |
| 1489 | HReg src, PPCRI* s_field ) { |
| 1490 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1491 | i->tag = Pin_AvHashV128Binary; |
| 1492 | i->Pin.AvHashV128Binary.op = op; |
| 1493 | i->Pin.AvHashV128Binary.dst = dst; |
| 1494 | i->Pin.AvHashV128Binary.src = src; |
| 1495 | i->Pin.AvHashV128Binary.s_field = s_field; |
| 1496 | return i; |
| 1497 | } |
| 1498 | PPCInstr* PPCInstr_AvBCDV128Trinary ( PPCAvOp op, HReg dst, |
| 1499 | HReg src1, HReg src2, PPCRI* ps ) { |
| 1500 | PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr)); |
| 1501 | i->tag = Pin_AvBCDV128Trinary; |
| 1502 | i->Pin.AvBCDV128Trinary.op = op; |
| 1503 | i->Pin.AvBCDV128Trinary.dst = dst; |
| 1504 | i->Pin.AvBCDV128Trinary.src1 = src1; |
| 1505 | i->Pin.AvBCDV128Trinary.src2 = src2; |
| 1506 | i->Pin.AvBCDV128Trinary.ps = ps; |
| 1507 | return i; |
| 1508 | } |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1509 | |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 1510 | |
| 1511 | /* Pretty Print instructions */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1512 | static void ppLoadImm ( HReg dst, ULong imm, Bool mode64 ) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1513 | vex_printf("li_word "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1514 | ppHRegPPC(dst); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1515 | if (!mode64) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1516 | vex_printf(",0x%08x", (UInt)imm); |
| 1517 | } else { |
| 1518 | vex_printf(",0x%016llx", imm); |
| 1519 | } |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 1520 | } |
| 1521 | |
| 1522 | static void ppMovReg ( HReg dst, HReg src ) { |
| 1523 | if (hregNumber(dst) != hregNumber(src)) { |
| 1524 | vex_printf("mr "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1525 | ppHRegPPC(dst); |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 1526 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1527 | ppHRegPPC(src); |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 1528 | } |
| 1529 | } |
| 1530 | |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1531 | void ppPPCInstr ( const PPCInstr* i, Bool mode64 ) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1532 | { |
| 1533 | switch (i->tag) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1534 | case Pin_LI: |
| 1535 | ppLoadImm(i->Pin.LI.dst, i->Pin.LI.imm64, mode64); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1536 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1537 | case Pin_Alu: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1538 | HReg r_srcL = i->Pin.Alu.srcL; |
| 1539 | PPCRH* rh_srcR = i->Pin.Alu.srcR; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1540 | /* special-case "mr" */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1541 | if (i->Pin.Alu.op == Palu_OR && // or Rd,Rs,Rs == mr Rd,Rs |
| 1542 | rh_srcR->tag == Prh_Reg && |
florian | 79efdc6 | 2013-02-11 00:47:35 +0000 | [diff] [blame] | 1543 | sameHReg(rh_srcR->Prh.Reg.reg, r_srcL)) { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1544 | vex_printf("mr "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1545 | ppHRegPPC(i->Pin.Alu.dst); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 1546 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1547 | ppHRegPPC(r_srcL); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1548 | return; |
| 1549 | } |
| 1550 | /* special-case "li" */ |
| 1551 | if (i->Pin.Alu.op == Palu_ADD && // addi Rd,0,imm == li Rd,imm |
| 1552 | rh_srcR->tag == Prh_Imm && |
| 1553 | hregNumber(r_srcL) == 0) { |
| 1554 | vex_printf("li "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1555 | ppHRegPPC(i->Pin.Alu.dst); |
cerion | b8c3b7f | 2005-03-01 20:27:49 +0000 | [diff] [blame] | 1556 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1557 | ppPPCRH(rh_srcR); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1558 | return; |
cerion | b8c3b7f | 2005-03-01 20:27:49 +0000 | [diff] [blame] | 1559 | } |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1560 | /* generic */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1561 | vex_printf("%s ", showPPCAluOp(i->Pin.Alu.op, |
| 1562 | toBool(rh_srcR->tag == Prh_Imm))); |
| 1563 | ppHRegPPC(i->Pin.Alu.dst); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1564 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1565 | ppHRegPPC(r_srcL); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1566 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1567 | ppPPCRH(rh_srcR); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1568 | return; |
| 1569 | } |
| 1570 | case Pin_Shft: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1571 | HReg r_srcL = i->Pin.Shft.srcL; |
| 1572 | PPCRH* rh_srcR = i->Pin.Shft.srcR; |
| 1573 | vex_printf("%s ", showPPCShftOp(i->Pin.Shft.op, |
| 1574 | toBool(rh_srcR->tag == Prh_Imm), |
| 1575 | i->Pin.Shft.sz32)); |
| 1576 | ppHRegPPC(i->Pin.Shft.dst); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1577 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1578 | ppHRegPPC(r_srcL); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1579 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1580 | ppPPCRH(rh_srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1581 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1582 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1583 | case Pin_AddSubC: |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 1584 | vex_printf("%s%s ", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1585 | i->Pin.AddSubC.isAdd ? "add" : "sub", |
| 1586 | i->Pin.AddSubC.setC ? "c" : "e"); |
| 1587 | ppHRegPPC(i->Pin.AddSubC.dst); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 1588 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1589 | ppHRegPPC(i->Pin.AddSubC.srcL); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 1590 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1591 | ppHRegPPC(i->Pin.AddSubC.srcR); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 1592 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1593 | case Pin_Cmp: |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1594 | vex_printf("%s%c%s %%cr%u,", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1595 | i->Pin.Cmp.syned ? "cmp" : "cmpl", |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1596 | i->Pin.Cmp.sz32 ? 'w' : 'd', |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1597 | i->Pin.Cmp.srcR->tag == Prh_Imm ? "i" : "", |
| 1598 | i->Pin.Cmp.crfD); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1599 | ppHRegPPC(i->Pin.Cmp.srcL); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1600 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1601 | ppPPCRH(i->Pin.Cmp.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1602 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1603 | case Pin_Unary: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1604 | vex_printf("%s ", showPPCUnaryOp(i->Pin.Unary.op)); |
| 1605 | ppHRegPPC(i->Pin.Unary.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1606 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1607 | ppHRegPPC(i->Pin.Unary.src); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1608 | return; |
| 1609 | case Pin_MulL: |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1610 | vex_printf("mul%c%c%s ", |
| 1611 | i->Pin.MulL.hi ? 'h' : 'l', |
| 1612 | i->Pin.MulL.sz32 ? 'w' : 'd', |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1613 | i->Pin.MulL.hi ? (i->Pin.MulL.syned ? "s" : "u") : ""); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1614 | ppHRegPPC(i->Pin.MulL.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1615 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1616 | ppHRegPPC(i->Pin.MulL.srcL); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1617 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1618 | ppHRegPPC(i->Pin.MulL.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1619 | return; |
| 1620 | case Pin_Div: |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 1621 | vex_printf("div%c%s%s ", |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1622 | i->Pin.Div.sz32 ? 'w' : 'd', |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 1623 | i->Pin.Div.extended ? "e" : "", |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1624 | i->Pin.Div.syned ? "" : "u"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1625 | ppHRegPPC(i->Pin.Div.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1626 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1627 | ppHRegPPC(i->Pin.Div.srcL); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1628 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1629 | ppHRegPPC(i->Pin.Div.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1630 | return; |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 1631 | case Pin_Call: { |
| 1632 | Int n; |
cerion | 8c51ed4 | 2005-02-22 11:16:54 +0000 | [diff] [blame] | 1633 | vex_printf("call: "); |
| 1634 | if (i->Pin.Call.cond.test != Pct_ALWAYS) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1635 | vex_printf("if (%s) ", showPPCCondCode(i->Pin.Call.cond)); |
cerion | 8c51ed4 | 2005-02-22 11:16:54 +0000 | [diff] [blame] | 1636 | } |
| 1637 | vex_printf("{ "); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1638 | ppLoadImm(hregPPC_GPR10(mode64), i->Pin.Call.target, mode64); |
| 1639 | vex_printf(" ; mtctr r10 ; bctrl ["); |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 1640 | for (n = 0; n < 32; n++) { |
| 1641 | if (i->Pin.Call.argiregs & (1<<n)) { |
| 1642 | vex_printf("r%d", n); |
| 1643 | if ((i->Pin.Call.argiregs >> n) > 1) |
| 1644 | vex_printf(","); |
| 1645 | } |
| 1646 | } |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 1647 | vex_printf(","); |
| 1648 | ppRetLoc(i->Pin.Call.rloc); |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 1649 | vex_printf("] }"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1650 | break; |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 1651 | } |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1652 | case Pin_XDirect: |
| 1653 | vex_printf("(xDirect) "); |
| 1654 | vex_printf("if (%s) { ", |
| 1655 | showPPCCondCode(i->Pin.XDirect.cond)); |
| 1656 | if (mode64) { |
| 1657 | vex_printf("imm64 r30,0x%llx; ", i->Pin.XDirect.dstGA); |
| 1658 | vex_printf("std r30,"); |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 1659 | } else { |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1660 | vex_printf("imm32 r30,0x%llx; ", i->Pin.XDirect.dstGA); |
| 1661 | vex_printf("stw r30,"); |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 1662 | } |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1663 | ppPPCAMode(i->Pin.XDirect.amCIA); |
| 1664 | vex_printf("; "); |
| 1665 | if (mode64) { |
| 1666 | vex_printf("imm64-fixed5 r30,$disp_cp_chain_me_to_%sEP; ", |
| 1667 | i->Pin.XDirect.toFastEP ? "fast" : "slow"); |
| 1668 | } else { |
| 1669 | vex_printf("imm32-fixed2 r30,$disp_cp_chain_me_to_%sEP; ", |
| 1670 | i->Pin.XDirect.toFastEP ? "fast" : "slow"); |
| 1671 | } |
| 1672 | vex_printf("mtctr r30; bctrl }"); |
| 1673 | return; |
| 1674 | case Pin_XIndir: |
| 1675 | vex_printf("(xIndir) "); |
| 1676 | vex_printf("if (%s) { ", |
| 1677 | showPPCCondCode(i->Pin.XIndir.cond)); |
| 1678 | vex_printf("%s ", mode64 ? "std" : "stw"); |
| 1679 | ppHRegPPC(i->Pin.XIndir.dstGA); |
| 1680 | vex_printf(","); |
| 1681 | ppPPCAMode(i->Pin.XIndir.amCIA); |
| 1682 | vex_printf("; "); |
| 1683 | vex_printf("imm%s r30,$disp_cp_xindir; ", mode64 ? "64" : "32"); |
| 1684 | vex_printf("mtctr r30; bctr }"); |
| 1685 | return; |
| 1686 | case Pin_XAssisted: |
| 1687 | vex_printf("(xAssisted) "); |
| 1688 | vex_printf("if (%s) { ", |
| 1689 | showPPCCondCode(i->Pin.XAssisted.cond)); |
| 1690 | vex_printf("%s ", mode64 ? "std" : "stw"); |
| 1691 | ppHRegPPC(i->Pin.XAssisted.dstGA); |
| 1692 | vex_printf(","); |
| 1693 | ppPPCAMode(i->Pin.XAssisted.amCIA); |
| 1694 | vex_printf("; "); |
| 1695 | vex_printf("li r31,$IRJumpKind_to_TRCVAL(%d); ", |
| 1696 | (Int)i->Pin.XAssisted.jk); |
| 1697 | vex_printf("imm%s r30,$disp_cp_xindir; ", mode64 ? "64" : "32"); |
| 1698 | vex_printf("mtctr r30; bctr }"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1699 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1700 | case Pin_CMov: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1701 | vex_printf("cmov (%s) ", showPPCCondCode(i->Pin.CMov.cond)); |
| 1702 | ppHRegPPC(i->Pin.CMov.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1703 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1704 | ppPPCRI(i->Pin.CMov.src); |
cerion | 8c51ed4 | 2005-02-22 11:16:54 +0000 | [diff] [blame] | 1705 | vex_printf(": "); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1706 | if (i->Pin.CMov.cond.test != Pct_ALWAYS) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1707 | vex_printf("if (%s) ", showPPCCondCode(i->Pin.CMov.cond)); |
cerion | 8c51ed4 | 2005-02-22 11:16:54 +0000 | [diff] [blame] | 1708 | } |
| 1709 | vex_printf("{ "); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1710 | if (i->Pin.CMov.src->tag == Pri_Imm) { |
| 1711 | ppLoadImm(i->Pin.CMov.dst, i->Pin.CMov.src->Pri.Imm, mode64); |
cerion | 8c51ed4 | 2005-02-22 11:16:54 +0000 | [diff] [blame] | 1712 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1713 | ppMovReg(i->Pin.CMov.dst, i->Pin.CMov.src->Pri.Reg); |
cerion | 8c51ed4 | 2005-02-22 11:16:54 +0000 | [diff] [blame] | 1714 | } |
| 1715 | vex_printf(" }"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1716 | return; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 1717 | case Pin_Load: { |
sewardj | 428fabd | 2005-03-21 03:11:17 +0000 | [diff] [blame] | 1718 | Bool idxd = toBool(i->Pin.Load.src->tag == Pam_RR); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1719 | UChar sz = i->Pin.Load.sz; |
florian | 5df8ab0 | 2012-10-13 19:34:19 +0000 | [diff] [blame] | 1720 | HChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : 'd'; |
sewardj | 34085e3 | 2007-03-09 18:07:00 +0000 | [diff] [blame] | 1721 | vex_printf("l%c%s%s ", c_sz, sz==8 ? "" : "z", idxd ? "x" : "" ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1722 | ppHRegPPC(i->Pin.Load.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1723 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1724 | ppPPCAMode(i->Pin.Load.src); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1725 | return; |
| 1726 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1727 | case Pin_LoadL: |
| 1728 | vex_printf("l%carx ", i->Pin.LoadL.sz==4 ? 'w' : 'd'); |
| 1729 | ppHRegPPC(i->Pin.LoadL.dst); |
| 1730 | vex_printf(",%%r0,"); |
| 1731 | ppHRegPPC(i->Pin.LoadL.src); |
| 1732 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1733 | case Pin_Store: { |
| 1734 | UChar sz = i->Pin.Store.sz; |
sewardj | 428fabd | 2005-03-21 03:11:17 +0000 | [diff] [blame] | 1735 | Bool idxd = toBool(i->Pin.Store.dst->tag == Pam_RR); |
florian | 5df8ab0 | 2012-10-13 19:34:19 +0000 | [diff] [blame] | 1736 | HChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : /*8*/ 'd'; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1737 | vex_printf("st%c%s ", c_sz, idxd ? "x" : "" ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1738 | ppHRegPPC(i->Pin.Store.src); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1739 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1740 | ppPPCAMode(i->Pin.Store.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1741 | return; |
| 1742 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1743 | case Pin_StoreC: |
| 1744 | vex_printf("st%ccx. ", i->Pin.StoreC.sz==4 ? 'w' : 'd'); |
| 1745 | ppHRegPPC(i->Pin.StoreC.src); |
| 1746 | vex_printf(",%%r0,"); |
| 1747 | ppHRegPPC(i->Pin.StoreC.dst); |
| 1748 | return; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1749 | case Pin_Set: { |
| 1750 | PPCCondCode cc = i->Pin.Set.cond; |
| 1751 | vex_printf("set (%s),", showPPCCondCode(cc)); |
| 1752 | ppHRegPPC(i->Pin.Set.dst); |
cerion | f9d6e22 | 2005-02-23 18:21:31 +0000 | [diff] [blame] | 1753 | if (cc.test == Pct_ALWAYS) { |
| 1754 | vex_printf(": { li "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1755 | ppHRegPPC(i->Pin.Set.dst); |
cerion | f9d6e22 | 2005-02-23 18:21:31 +0000 | [diff] [blame] | 1756 | vex_printf(",1 }"); |
| 1757 | } else { |
| 1758 | vex_printf(": { mfcr r0 ; rlwinm "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1759 | ppHRegPPC(i->Pin.Set.dst); |
sewardj | 428fabd | 2005-03-21 03:11:17 +0000 | [diff] [blame] | 1760 | vex_printf(",r0,%u,31,31", cc.flag+1); |
cerion | f9d6e22 | 2005-02-23 18:21:31 +0000 | [diff] [blame] | 1761 | if (cc.test == Pct_FALSE) { |
| 1762 | vex_printf("; xori "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1763 | ppHRegPPC(i->Pin.Set.dst); |
cerion | f9d6e22 | 2005-02-23 18:21:31 +0000 | [diff] [blame] | 1764 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1765 | ppHRegPPC(i->Pin.Set.dst); |
sewardj | f774505 | 2005-12-16 01:06:42 +0000 | [diff] [blame] | 1766 | vex_printf(",1"); |
cerion | f9d6e22 | 2005-02-23 18:21:31 +0000 | [diff] [blame] | 1767 | } |
| 1768 | vex_printf(" }"); |
| 1769 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1770 | return; |
cerion | f9d6e22 | 2005-02-23 18:21:31 +0000 | [diff] [blame] | 1771 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1772 | case Pin_MfCR: |
| 1773 | vex_printf("mfcr "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1774 | ppHRegPPC(i->Pin.MfCR.dst); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1775 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1776 | case Pin_MFence: |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 1777 | vex_printf("mfence (=sync)"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1778 | return; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1779 | |
| 1780 | case Pin_FpUnary: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1781 | vex_printf("%s ", showPPCFpOp(i->Pin.FpUnary.op)); |
| 1782 | ppHRegPPC(i->Pin.FpUnary.dst); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1783 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1784 | ppHRegPPC(i->Pin.FpUnary.src); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1785 | return; |
| 1786 | case Pin_FpBinary: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1787 | vex_printf("%s ", showPPCFpOp(i->Pin.FpBinary.op)); |
| 1788 | ppHRegPPC(i->Pin.FpBinary.dst); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1789 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1790 | ppHRegPPC(i->Pin.FpBinary.srcL); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1791 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1792 | ppHRegPPC(i->Pin.FpBinary.srcR); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1793 | return; |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 1794 | case Pin_FpMulAcc: |
| 1795 | vex_printf("%s ", showPPCFpOp(i->Pin.FpMulAcc.op)); |
| 1796 | ppHRegPPC(i->Pin.FpMulAcc.dst); |
| 1797 | vex_printf(","); |
| 1798 | ppHRegPPC(i->Pin.FpMulAcc.srcML); |
| 1799 | vex_printf(","); |
| 1800 | ppHRegPPC(i->Pin.FpMulAcc.srcMR); |
| 1801 | vex_printf(","); |
| 1802 | ppHRegPPC(i->Pin.FpMulAcc.srcAcc); |
| 1803 | return; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1804 | case Pin_FpLdSt: { |
| 1805 | UChar sz = i->Pin.FpLdSt.sz; |
| 1806 | Bool idxd = toBool(i->Pin.FpLdSt.addr->tag == Pam_RR); |
| 1807 | if (i->Pin.FpLdSt.isLoad) { |
| 1808 | vex_printf("lf%c%s ", |
| 1809 | (sz==4 ? 's' : 'd'), |
| 1810 | idxd ? "x" : "" ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1811 | ppHRegPPC(i->Pin.FpLdSt.reg); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1812 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1813 | ppPPCAMode(i->Pin.FpLdSt.addr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1814 | } else { |
| 1815 | vex_printf("stf%c%s ", |
| 1816 | (sz==4 ? 's' : 'd'), |
| 1817 | idxd ? "x" : "" ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1818 | ppHRegPPC(i->Pin.FpLdSt.reg); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1819 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1820 | ppPPCAMode(i->Pin.FpLdSt.addr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1821 | } |
| 1822 | return; |
| 1823 | } |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1824 | case Pin_FpSTFIW: |
| 1825 | vex_printf("stfiwz "); |
| 1826 | ppHRegPPC(i->Pin.FpSTFIW.data); |
| 1827 | vex_printf(",0("); |
| 1828 | ppHRegPPC(i->Pin.FpSTFIW.addr); |
| 1829 | vex_printf(")"); |
| 1830 | return; |
| 1831 | case Pin_FpRSP: |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1832 | vex_printf("frsp "); |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1833 | ppHRegPPC(i->Pin.FpRSP.dst); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1834 | vex_printf(","); |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1835 | ppHRegPPC(i->Pin.FpRSP.src); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1836 | return; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1837 | case Pin_FpCftI: { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1838 | const HChar* str = "fc?????"; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 1839 | /* Note that "fcfids" is missing from below. That instruction would |
| 1840 | * satisfy the predicate: |
| 1841 | * (i->Pin.FpCftI.fromI == True && i->Pin.FpCftI.int32 == False) |
| 1842 | * which would go into a final "else" clause to make this if-else |
| 1843 | * block balanced. But we're able to implement fcfids by leveraging |
| 1844 | * the fcfid implementation, so it wasn't necessary to include it here. |
| 1845 | */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1846 | if (i->Pin.FpCftI.fromI == False && i->Pin.FpCftI.int32 == False) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1847 | if (i->Pin.FpCftI.syned == True) |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 1848 | str = "fctid"; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1849 | else |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 1850 | str = "fctidu"; |
| 1851 | else if (i->Pin.FpCftI.fromI == False && i->Pin.FpCftI.int32 == True) |
| 1852 | if (i->Pin.FpCftI.syned == True) |
| 1853 | str = "fctiw"; |
| 1854 | else |
| 1855 | str = "fctiwu"; |
| 1856 | else if (i->Pin.FpCftI.fromI == True && i->Pin.FpCftI.int32 == False) { |
| 1857 | if (i->Pin.FpCftI.syned == True) { |
| 1858 | str = "fcfid"; |
| 1859 | } else { |
| 1860 | if (i->Pin.FpCftI.flt64 == True) |
| 1861 | str = "fcfidu"; |
| 1862 | else |
| 1863 | str = "fcfidus"; |
| 1864 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1865 | } |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1866 | vex_printf("%s ", str); |
| 1867 | ppHRegPPC(i->Pin.FpCftI.dst); |
| 1868 | vex_printf(","); |
| 1869 | ppHRegPPC(i->Pin.FpCftI.src); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1870 | return; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1871 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1872 | case Pin_FpCMov: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1873 | vex_printf("fpcmov (%s) ", showPPCCondCode(i->Pin.FpCMov.cond)); |
| 1874 | ppHRegPPC(i->Pin.FpCMov.dst); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1875 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1876 | ppHRegPPC(i->Pin.FpCMov.src); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1877 | vex_printf(": "); |
| 1878 | vex_printf("if (fr_dst != fr_src) { "); |
| 1879 | if (i->Pin.FpCMov.cond.test != Pct_ALWAYS) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1880 | vex_printf("if (%s) { ", showPPCCondCode(i->Pin.FpCMov.cond)); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1881 | } |
| 1882 | vex_printf("fmr "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1883 | ppHRegPPC(i->Pin.FpCMov.dst); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1884 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1885 | ppHRegPPC(i->Pin.FpCMov.src); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1886 | if (i->Pin.FpCMov.cond.test != Pct_ALWAYS) |
| 1887 | vex_printf(" }"); |
| 1888 | vex_printf(" }"); |
| 1889 | return; |
| 1890 | case Pin_FpLdFPSCR: |
| 1891 | vex_printf("mtfsf 0xFF,"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1892 | ppHRegPPC(i->Pin.FpLdFPSCR.src); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1893 | vex_printf(",0, %s", i->Pin.FpLdFPSCR.dfp_rm ? "1" : "0"); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1894 | return; |
| 1895 | case Pin_FpCmp: |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1896 | vex_printf("fcmpo %%cr1,"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1897 | ppHRegPPC(i->Pin.FpCmp.srcL); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1898 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1899 | ppHRegPPC(i->Pin.FpCmp.srcR); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1900 | vex_printf("; mfcr "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1901 | ppHRegPPC(i->Pin.FpCmp.dst); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1902 | vex_printf("; rlwinm "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1903 | ppHRegPPC(i->Pin.FpCmp.dst); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1904 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1905 | ppHRegPPC(i->Pin.FpCmp.dst); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 1906 | vex_printf(",8,28,31"); |
| 1907 | return; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1908 | |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 1909 | case Pin_RdWrLR: |
| 1910 | vex_printf("%s ", i->Pin.RdWrLR.wrLR ? "mtlr" : "mflr"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1911 | ppHRegPPC(i->Pin.RdWrLR.gpr); |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 1912 | return; |
| 1913 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1914 | case Pin_AvLdSt: { |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 1915 | UChar sz = i->Pin.AvLdSt.sz; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1916 | const HChar* str_size; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1917 | if (i->Pin.AvLdSt.addr->tag == Pam_IR) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1918 | ppLoadImm(hregPPC_GPR30(mode64), |
florian | e6be61f | 2013-02-01 16:11:51 +0000 | [diff] [blame] | 1919 | i->Pin.AvLdSt.addr->Pam.IR.index, mode64); |
cerion | 0171310 | 2005-06-29 19:05:08 +0000 | [diff] [blame] | 1920 | vex_printf(" ; "); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1921 | } |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 1922 | str_size = sz==1 ? "eb" : sz==2 ? "eh" : sz==4 ? "ew" : ""; |
cerion | 0171310 | 2005-06-29 19:05:08 +0000 | [diff] [blame] | 1923 | if (i->Pin.AvLdSt.isLoad) |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 1924 | vex_printf("lv%sx ", str_size); |
cerion | 0171310 | 2005-06-29 19:05:08 +0000 | [diff] [blame] | 1925 | else |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 1926 | vex_printf("stv%sx ", str_size); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1927 | ppHRegPPC(i->Pin.AvLdSt.reg); |
cerion | 0171310 | 2005-06-29 19:05:08 +0000 | [diff] [blame] | 1928 | vex_printf(","); |
| 1929 | if (i->Pin.AvLdSt.addr->tag == Pam_IR) |
| 1930 | vex_printf("%%r30"); |
| 1931 | else |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1932 | ppHRegPPC(i->Pin.AvLdSt.addr->Pam.RR.index); |
cerion | 0171310 | 2005-06-29 19:05:08 +0000 | [diff] [blame] | 1933 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1934 | ppHRegPPC(i->Pin.AvLdSt.addr->Pam.RR.base); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1935 | return; |
| 1936 | } |
| 1937 | case Pin_AvUnary: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1938 | vex_printf("%s ", showPPCAvOp(i->Pin.AvUnary.op)); |
| 1939 | ppHRegPPC(i->Pin.AvUnary.dst); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1940 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1941 | ppHRegPPC(i->Pin.AvUnary.src); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1942 | return; |
| 1943 | case Pin_AvBinary: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1944 | vex_printf("%s ", showPPCAvOp(i->Pin.AvBinary.op)); |
| 1945 | ppHRegPPC(i->Pin.AvBinary.dst); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1946 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1947 | ppHRegPPC(i->Pin.AvBinary.srcL); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1948 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1949 | ppHRegPPC(i->Pin.AvBinary.srcR); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1950 | return; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1951 | case Pin_AvBin8x16: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1952 | vex_printf("%s(b) ", showPPCAvOp(i->Pin.AvBin8x16.op)); |
| 1953 | ppHRegPPC(i->Pin.AvBin8x16.dst); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1954 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1955 | ppHRegPPC(i->Pin.AvBin8x16.srcL); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1956 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1957 | ppHRegPPC(i->Pin.AvBin8x16.srcR); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1958 | return; |
| 1959 | case Pin_AvBin16x8: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1960 | vex_printf("%s(h) ", showPPCAvOp(i->Pin.AvBin16x8.op)); |
| 1961 | ppHRegPPC(i->Pin.AvBin16x8.dst); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1962 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1963 | ppHRegPPC(i->Pin.AvBin16x8.srcL); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1964 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1965 | ppHRegPPC(i->Pin.AvBin16x8.srcR); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1966 | return; |
| 1967 | case Pin_AvBin32x4: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1968 | vex_printf("%s(w) ", showPPCAvOp(i->Pin.AvBin32x4.op)); |
| 1969 | ppHRegPPC(i->Pin.AvBin32x4.dst); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1970 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1971 | ppHRegPPC(i->Pin.AvBin32x4.srcL); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1972 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1973 | ppHRegPPC(i->Pin.AvBin32x4.srcR); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1974 | return; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1975 | case Pin_AvBin64x2: |
| 1976 | vex_printf("%s(w) ", showPPCAvOp(i->Pin.AvBin64x2.op)); |
| 1977 | ppHRegPPC(i->Pin.AvBin64x2.dst); |
| 1978 | vex_printf(","); |
| 1979 | ppHRegPPC(i->Pin.AvBin64x2.srcL); |
| 1980 | vex_printf(","); |
| 1981 | ppHRegPPC(i->Pin.AvBin64x2.srcR); |
| 1982 | return; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1983 | case Pin_AvBin32Fx4: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1984 | vex_printf("%s ", showPPCAvFpOp(i->Pin.AvBin32Fx4.op)); |
| 1985 | ppHRegPPC(i->Pin.AvBin32Fx4.dst); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1986 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1987 | ppHRegPPC(i->Pin.AvBin32Fx4.srcL); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1988 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1989 | ppHRegPPC(i->Pin.AvBin32Fx4.srcR); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 1990 | return; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 1991 | case Pin_AvUn32Fx4: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1992 | vex_printf("%s ", showPPCAvFpOp(i->Pin.AvUn32Fx4.op)); |
| 1993 | ppHRegPPC(i->Pin.AvUn32Fx4.dst); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 1994 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1995 | ppHRegPPC(i->Pin.AvUn32Fx4.src); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 1996 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 1997 | case Pin_AvPerm: |
| 1998 | vex_printf("vperm "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1999 | ppHRegPPC(i->Pin.AvPerm.dst); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2000 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2001 | ppHRegPPC(i->Pin.AvPerm.srcL); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2002 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2003 | ppHRegPPC(i->Pin.AvPerm.srcR); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2004 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2005 | ppHRegPPC(i->Pin.AvPerm.ctl); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2006 | return; |
| 2007 | |
| 2008 | case Pin_AvSel: |
| 2009 | vex_printf("vsel "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2010 | ppHRegPPC(i->Pin.AvSel.dst); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2011 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2012 | ppHRegPPC(i->Pin.AvSel.srcL); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2013 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2014 | ppHRegPPC(i->Pin.AvSel.srcR); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2015 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2016 | ppHRegPPC(i->Pin.AvSel.ctl); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2017 | return; |
| 2018 | |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 2019 | case Pin_AvSh: |
| 2020 | /* This only generates the following instructions with RA |
| 2021 | * register number set to 0. |
| 2022 | */ |
| 2023 | if (i->Pin.AvSh.addr->tag == Pam_IR) { |
| 2024 | ppLoadImm(hregPPC_GPR30(mode64), |
| 2025 | i->Pin.AvSh.addr->Pam.IR.index, mode64); |
| 2026 | vex_printf(" ; "); |
| 2027 | } |
| 2028 | |
| 2029 | if (i->Pin.AvSh.shLeft) |
| 2030 | vex_printf("lvsl "); |
| 2031 | else |
| 2032 | vex_printf("lvsr "); |
| 2033 | |
| 2034 | ppHRegPPC(i->Pin.AvSh.dst); |
| 2035 | if (i->Pin.AvSh.addr->tag == Pam_IR) |
| 2036 | vex_printf("%%r30"); |
| 2037 | else |
| 2038 | ppHRegPPC(i->Pin.AvSh.addr->Pam.RR.index); |
| 2039 | vex_printf(","); |
| 2040 | ppHRegPPC(i->Pin.AvSh.addr->Pam.RR.base); |
| 2041 | return; |
| 2042 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2043 | case Pin_AvShlDbl: |
| 2044 | vex_printf("vsldoi "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2045 | ppHRegPPC(i->Pin.AvShlDbl.dst); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2046 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2047 | ppHRegPPC(i->Pin.AvShlDbl.srcL); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2048 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2049 | ppHRegPPC(i->Pin.AvShlDbl.srcR); |
sewardj | db36c0f | 2005-07-03 00:05:31 +0000 | [diff] [blame] | 2050 | vex_printf(",%d", i->Pin.AvShlDbl.shift); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2051 | return; |
| 2052 | |
| 2053 | case Pin_AvSplat: { |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 2054 | UChar sz = i->Pin.AvSplat.sz; |
florian | 5df8ab0 | 2012-10-13 19:34:19 +0000 | [diff] [blame] | 2055 | HChar ch_sz = toUChar( (sz == 8) ? 'b' : (sz == 16) ? 'h' : 'w' ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2056 | vex_printf("vsplt%s%c ", |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 2057 | i->Pin.AvSplat.src->tag == Pvi_Imm ? "is" : "", ch_sz); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2058 | ppHRegPPC(i->Pin.AvSplat.dst); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2059 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2060 | ppPPCVI5s(i->Pin.AvSplat.src); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 2061 | if (i->Pin.AvSplat.src->tag == Pvi_Reg) |
sewardj | 62d0543 | 2005-10-29 22:30:47 +0000 | [diff] [blame] | 2062 | vex_printf(", %d", (128/sz)-1); /* louis lane */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2063 | return; |
| 2064 | } |
| 2065 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2066 | case Pin_AvCMov: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2067 | vex_printf("avcmov (%s) ", showPPCCondCode(i->Pin.AvCMov.cond)); |
| 2068 | ppHRegPPC(i->Pin.AvCMov.dst); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2069 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2070 | ppHRegPPC(i->Pin.AvCMov.src); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2071 | vex_printf(": "); |
| 2072 | vex_printf("if (v_dst != v_src) { "); |
| 2073 | if (i->Pin.AvCMov.cond.test != Pct_ALWAYS) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2074 | vex_printf("if (%s) { ", showPPCCondCode(i->Pin.AvCMov.cond)); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2075 | } |
| 2076 | vex_printf("vmr "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2077 | ppHRegPPC(i->Pin.AvCMov.dst); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2078 | vex_printf(","); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2079 | ppHRegPPC(i->Pin.AvCMov.src); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2080 | if (i->Pin.FpCMov.cond.test != Pct_ALWAYS) |
| 2081 | vex_printf(" }"); |
| 2082 | vex_printf(" }"); |
| 2083 | return; |
| 2084 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2085 | case Pin_AvLdVSCR: |
| 2086 | vex_printf("mtvscr "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2087 | ppHRegPPC(i->Pin.AvLdVSCR.src); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2088 | return; |
| 2089 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 2090 | case Pin_AvCipherV128Unary: |
| 2091 | vex_printf("%s(w) ", showPPCAvOp(i->Pin.AvCipherV128Unary.op)); |
| 2092 | ppHRegPPC(i->Pin.AvCipherV128Unary.dst); |
| 2093 | vex_printf(","); |
| 2094 | ppHRegPPC(i->Pin.AvCipherV128Unary.src); |
| 2095 | return; |
| 2096 | |
| 2097 | case Pin_AvCipherV128Binary: |
| 2098 | vex_printf("%s(w) ", showPPCAvOp(i->Pin.AvCipherV128Binary.op)); |
| 2099 | ppHRegPPC(i->Pin.AvCipherV128Binary.dst); |
| 2100 | vex_printf(","); |
| 2101 | ppHRegPPC(i->Pin.AvCipherV128Binary.srcL); |
| 2102 | vex_printf(","); |
| 2103 | ppHRegPPC(i->Pin.AvCipherV128Binary.srcR); |
| 2104 | return; |
| 2105 | |
| 2106 | case Pin_AvHashV128Binary: |
| 2107 | vex_printf("%s(w) ", showPPCAvOp(i->Pin.AvHashV128Binary.op)); |
| 2108 | ppHRegPPC(i->Pin.AvHashV128Binary.dst); |
| 2109 | vex_printf(","); |
| 2110 | ppHRegPPC(i->Pin.AvHashV128Binary.src); |
| 2111 | vex_printf(","); |
| 2112 | ppPPCRI(i->Pin.AvHashV128Binary.s_field); |
| 2113 | return; |
| 2114 | |
| 2115 | case Pin_AvBCDV128Trinary: |
| 2116 | vex_printf("%s(w) ", showPPCAvOp(i->Pin.AvBCDV128Trinary.op)); |
| 2117 | ppHRegPPC(i->Pin.AvBCDV128Trinary.dst); |
| 2118 | vex_printf(","); |
| 2119 | ppHRegPPC(i->Pin.AvBCDV128Trinary.src1); |
| 2120 | vex_printf(","); |
| 2121 | ppHRegPPC(i->Pin.AvBCDV128Trinary.src2); |
| 2122 | vex_printf(","); |
| 2123 | ppPPCRI(i->Pin.AvBCDV128Trinary.ps); |
| 2124 | return; |
| 2125 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2126 | case Pin_Dfp64Unary: |
| 2127 | vex_printf("%s ", showPPCFpOp(i->Pin.Dfp64Unary.op)); |
| 2128 | ppHRegPPC(i->Pin.Dfp64Unary.dst); |
| 2129 | vex_printf(","); |
| 2130 | ppHRegPPC(i->Pin.Dfp64Unary.src); |
| 2131 | return; |
| 2132 | |
| 2133 | case Pin_Dfp64Binary: |
| 2134 | vex_printf("%s ", showPPCFpOp(i->Pin.Dfp64Binary.op)); |
| 2135 | ppHRegPPC(i->Pin.Dfp64Binary.dst); |
| 2136 | vex_printf(","); |
| 2137 | ppHRegPPC(i->Pin.Dfp64Binary.srcL); |
| 2138 | vex_printf(","); |
| 2139 | ppHRegPPC(i->Pin.Dfp64Binary.srcR); |
| 2140 | return; |
| 2141 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 2142 | case Pin_DfpShift: |
| 2143 | vex_printf("%s ", showPPCFpOp(i->Pin.DfpShift.op)); |
| 2144 | ppHRegPPC(i->Pin.DfpShift.dst); |
| 2145 | vex_printf(","); |
| 2146 | ppHRegPPC(i->Pin.DfpShift.src); |
| 2147 | vex_printf(","); |
| 2148 | ppPPCRI(i->Pin.DfpShift.shift); |
| 2149 | return; |
| 2150 | |
| 2151 | case Pin_Dfp128Unary: |
| 2152 | vex_printf("%s ", showPPCFpOp(i->Pin.Dfp128Unary.op)); |
| 2153 | ppHRegPPC(i->Pin.Dfp128Unary.dst_hi); |
| 2154 | vex_printf(","); |
| 2155 | ppHRegPPC(i->Pin.Dfp128Unary.src_hi); |
| 2156 | return; |
| 2157 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2158 | case Pin_Dfp128Binary: |
| 2159 | vex_printf("%s ", showPPCFpOp(i->Pin.Dfp128Binary.op)); |
| 2160 | ppHRegPPC(i->Pin.Dfp128Binary.dst_hi); |
| 2161 | vex_printf(","); |
| 2162 | ppHRegPPC(i->Pin.Dfp128Binary.srcR_hi); |
| 2163 | return; |
| 2164 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 2165 | case Pin_DfpShift128: |
| 2166 | vex_printf("%s ", showPPCFpOp(i->Pin.DfpShift128.op)); |
| 2167 | ppHRegPPC(i->Pin.DfpShift128.dst_hi); |
| 2168 | vex_printf(","); |
| 2169 | ppHRegPPC(i->Pin.DfpShift128.src_hi); |
| 2170 | vex_printf(","); |
| 2171 | ppPPCRI(i->Pin.DfpShift128.shift); |
| 2172 | return; |
| 2173 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 2174 | case Pin_DfpRound: |
| 2175 | vex_printf("drintx "); |
| 2176 | ppHRegPPC(i->Pin.DfpRound.dst); |
| 2177 | vex_printf(","); |
| 2178 | ppHRegPPC(i->Pin.DfpRound.src); |
| 2179 | vex_printf(","); |
| 2180 | ppPPCRI(i->Pin.DfpRound.r_rmc); /* R in bit 3 and RMC in bits 2:0 */ |
| 2181 | return; |
| 2182 | |
| 2183 | case Pin_DfpRound128: |
| 2184 | vex_printf("drintxq "); |
| 2185 | ppHRegPPC(i->Pin.DfpRound128.dst_hi); |
| 2186 | vex_printf(","); |
| 2187 | ppHRegPPC(i->Pin.DfpRound128.src_hi); |
| 2188 | vex_printf(","); |
| 2189 | ppPPCRI(i->Pin.DfpRound128.r_rmc); /* R in bit 3 and RMC in bits 2:0 */ |
| 2190 | return; |
| 2191 | |
| 2192 | case Pin_DfpQuantize: |
| 2193 | vex_printf("%s ", showPPCFpOp(i->Pin.DfpQuantize.op)); |
| 2194 | ppHRegPPC(i->Pin.DfpQuantize.dst); |
| 2195 | vex_printf(","); |
| 2196 | ppHRegPPC(i->Pin.DfpQuantize.srcL); |
| 2197 | vex_printf(","); |
| 2198 | ppHRegPPC(i->Pin.DfpQuantize.srcR); |
| 2199 | vex_printf(","); |
| 2200 | ppPPCRI(i->Pin.DfpQuantize.rmc); |
| 2201 | return; |
| 2202 | |
| 2203 | case Pin_DfpQuantize128: |
| 2204 | /* Dst is used to pass in left source and return result */ |
| 2205 | vex_printf("dquaq "); |
| 2206 | ppHRegPPC(i->Pin.DfpQuantize128.dst_hi); |
| 2207 | vex_printf(","); |
| 2208 | ppHRegPPC(i->Pin.DfpQuantize128.dst_hi); |
| 2209 | vex_printf(","); |
| 2210 | ppHRegPPC(i->Pin.DfpQuantize128.src_hi); |
| 2211 | vex_printf(","); |
| 2212 | ppPPCRI(i->Pin.DfpQuantize128.rmc); |
| 2213 | return; |
| 2214 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 2215 | case Pin_DfpD128toD64: |
| 2216 | vex_printf("%s ", showPPCFpOp(i->Pin.DfpD128toD64.op)); |
| 2217 | ppHRegPPC(i->Pin.DfpD128toD64.dst); |
| 2218 | vex_printf(","); |
| 2219 | ppHRegPPC(i->Pin.DfpD128toD64.src_hi); |
| 2220 | vex_printf(","); |
| 2221 | return; |
| 2222 | |
| 2223 | case Pin_DfpI64StoD128: |
| 2224 | vex_printf("%s ", showPPCFpOp(i->Pin.DfpI64StoD128.op)); |
| 2225 | ppHRegPPC(i->Pin.DfpI64StoD128.dst_hi); |
| 2226 | vex_printf(","); |
| 2227 | ppHRegPPC(i->Pin.DfpI64StoD128.src); |
| 2228 | vex_printf(","); |
| 2229 | return; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 2230 | case Pin_ExtractExpD128: |
| 2231 | vex_printf("dxexq "); |
| 2232 | ppHRegPPC(i->Pin.ExtractExpD128.dst); |
| 2233 | vex_printf(","); |
| 2234 | ppHRegPPC(i->Pin.ExtractExpD128.src_hi); |
| 2235 | return; |
| 2236 | case Pin_InsertExpD128: |
| 2237 | vex_printf("diexq "); |
| 2238 | ppHRegPPC(i->Pin.InsertExpD128.dst_hi); |
| 2239 | vex_printf(","); |
| 2240 | ppHRegPPC(i->Pin.InsertExpD128.srcL); |
| 2241 | vex_printf(","); |
| 2242 | ppHRegPPC(i->Pin.InsertExpD128.srcR_hi); |
| 2243 | return; |
| 2244 | case Pin_Dfp64Cmp: |
| 2245 | vex_printf("dcmpo %%cr1,"); |
| 2246 | ppHRegPPC(i->Pin.Dfp64Cmp.srcL); |
| 2247 | vex_printf(","); |
| 2248 | ppHRegPPC(i->Pin.Dfp64Cmp.srcR); |
| 2249 | vex_printf("; mfcr "); |
| 2250 | ppHRegPPC(i->Pin.Dfp64Cmp.dst); |
| 2251 | vex_printf("; rlwinm "); |
| 2252 | ppHRegPPC(i->Pin.Dfp64Cmp.dst); |
| 2253 | vex_printf(","); |
| 2254 | ppHRegPPC(i->Pin.Dfp64Cmp.dst); |
| 2255 | vex_printf(",8,28,31"); |
| 2256 | return; |
| 2257 | case Pin_Dfp128Cmp: |
| 2258 | vex_printf("dcmpoq %%cr1,"); |
| 2259 | ppHRegPPC(i->Pin.Dfp128Cmp.srcL_hi); |
| 2260 | vex_printf(","); |
| 2261 | ppHRegPPC(i->Pin.Dfp128Cmp.srcR_hi); |
| 2262 | vex_printf("; mfcr "); |
| 2263 | ppHRegPPC(i->Pin.Dfp128Cmp.dst); |
| 2264 | vex_printf("; rlwinm "); |
| 2265 | ppHRegPPC(i->Pin.Dfp128Cmp.dst); |
| 2266 | vex_printf(","); |
| 2267 | ppHRegPPC(i->Pin.Dfp128Cmp.dst); |
| 2268 | vex_printf(",8,28,31"); |
| 2269 | return; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 2270 | case Pin_EvCheck: |
| 2271 | /* Note that the counter dec is 32 bit even in 64-bit mode. */ |
| 2272 | vex_printf("(evCheck) "); |
| 2273 | vex_printf("lwz r30,"); |
| 2274 | ppPPCAMode(i->Pin.EvCheck.amCounter); |
| 2275 | vex_printf("; addic. r30,r30,-1; "); |
| 2276 | vex_printf("stw r30,"); |
| 2277 | ppPPCAMode(i->Pin.EvCheck.amCounter); |
| 2278 | vex_printf("; bge nofail; lwz r30,"); |
| 2279 | ppPPCAMode(i->Pin.EvCheck.amFailAddr); |
| 2280 | vex_printf("; mtctr r30; bctr; nofail:"); |
| 2281 | return; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 2282 | case Pin_ProfInc: |
| 2283 | if (mode64) { |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 2284 | vex_printf("(profInc) imm64-fixed5 r30,$NotKnownYet; "); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 2285 | vex_printf("ld r29,(r30); addi r29,r29,1; std r29,(r30)"); |
| 2286 | } else { |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 2287 | vex_printf("(profInc) imm32-fixed2 r30,$NotKnownYet; "); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 2288 | vex_printf("lwz r29,4(r30); addic. r29,r29,1; stw r29,4(r30)"); |
| 2289 | vex_printf("lwz r29,0(r30); addze r29,r29; stw r29,0(r30)"); |
| 2290 | } |
| 2291 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2292 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2293 | vex_printf("\nppPPCInstr: No such tag(%d)\n", (Int)i->tag); |
| 2294 | vpanic("ppPPCInstr"); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 2295 | } |
| 2296 | } |
| 2297 | |
| 2298 | /* --------- Helpers for register allocation. --------- */ |
| 2299 | |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 2300 | void getRegUsage_PPCInstr ( HRegUsage* u, const PPCInstr* i, Bool mode64 ) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 2301 | { |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 2302 | initHRegUsage(u); |
| 2303 | switch (i->tag) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2304 | case Pin_LI: |
| 2305 | addHRegUse(u, HRmWrite, i->Pin.LI.dst); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2306 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2307 | case Pin_Alu: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2308 | addHRegUse(u, HRmRead, i->Pin.Alu.srcL); |
| 2309 | addRegUsage_PPCRH(u, i->Pin.Alu.srcR); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2310 | addHRegUse(u, HRmWrite, i->Pin.Alu.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2311 | return; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2312 | case Pin_Shft: |
| 2313 | addHRegUse(u, HRmRead, i->Pin.Shft.srcL); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2314 | addRegUsage_PPCRH(u, i->Pin.Shft.srcR); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2315 | addHRegUse(u, HRmWrite, i->Pin.Shft.dst); |
| 2316 | return; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2317 | case Pin_AddSubC: |
| 2318 | addHRegUse(u, HRmWrite, i->Pin.AddSubC.dst); |
| 2319 | addHRegUse(u, HRmRead, i->Pin.AddSubC.srcL); |
| 2320 | addHRegUse(u, HRmRead, i->Pin.AddSubC.srcR); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 2321 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2322 | case Pin_Cmp: |
| 2323 | addHRegUse(u, HRmRead, i->Pin.Cmp.srcL); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2324 | addRegUsage_PPCRH(u, i->Pin.Cmp.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2325 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2326 | case Pin_Unary: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2327 | addHRegUse(u, HRmWrite, i->Pin.Unary.dst); |
| 2328 | addHRegUse(u, HRmRead, i->Pin.Unary.src); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2329 | return; |
| 2330 | case Pin_MulL: |
| 2331 | addHRegUse(u, HRmWrite, i->Pin.MulL.dst); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2332 | addHRegUse(u, HRmRead, i->Pin.MulL.srcL); |
| 2333 | addHRegUse(u, HRmRead, i->Pin.MulL.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2334 | return; |
| 2335 | case Pin_Div: |
| 2336 | addHRegUse(u, HRmWrite, i->Pin.Div.dst); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2337 | addHRegUse(u, HRmRead, i->Pin.Div.srcL); |
| 2338 | addHRegUse(u, HRmRead, i->Pin.Div.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2339 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2340 | case Pin_Call: { |
| 2341 | UInt argir; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2342 | /* This is a bit subtle. */ |
| 2343 | /* First off, claim it trashes all the caller-saved regs |
| 2344 | which fall within the register allocator's jurisdiction. |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2345 | These I believe to be: |
| 2346 | mode32: r3 to r12 |
| 2347 | mode64: r3 to r10 |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2348 | */ |
sewardj | cb1f68e | 2005-12-30 03:39:14 +0000 | [diff] [blame] | 2349 | /* XXXXXXXXXXXXXXXXX BUG! This doesn't say anything about the FP |
| 2350 | or Altivec registers. We get away with this ONLY because |
| 2351 | getAllocatableRegs_PPC gives the allocator callee-saved fp |
| 2352 | and Altivec regs, and no caller-save ones. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2353 | addHRegUse(u, HRmWrite, hregPPC_GPR3(mode64)); |
| 2354 | addHRegUse(u, HRmWrite, hregPPC_GPR4(mode64)); |
| 2355 | addHRegUse(u, HRmWrite, hregPPC_GPR5(mode64)); |
| 2356 | addHRegUse(u, HRmWrite, hregPPC_GPR6(mode64)); |
| 2357 | addHRegUse(u, HRmWrite, hregPPC_GPR7(mode64)); |
| 2358 | addHRegUse(u, HRmWrite, hregPPC_GPR8(mode64)); |
| 2359 | addHRegUse(u, HRmWrite, hregPPC_GPR9(mode64)); |
| 2360 | addHRegUse(u, HRmWrite, hregPPC_GPR10(mode64)); |
| 2361 | if (!mode64) { |
| 2362 | addHRegUse(u, HRmWrite, hregPPC_GPR11(mode64)); |
| 2363 | addHRegUse(u, HRmWrite, hregPPC_GPR12(mode64)); |
| 2364 | } |
| 2365 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2366 | /* Now we have to state any parameter-carrying registers |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 2367 | which might be read. This depends on the argiregs field. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2368 | argir = i->Pin.Call.argiregs; |
| 2369 | if (argir &(1<<10)) addHRegUse(u, HRmRead, hregPPC_GPR10(mode64)); |
| 2370 | if (argir & (1<<9)) addHRegUse(u, HRmRead, hregPPC_GPR9(mode64)); |
| 2371 | if (argir & (1<<8)) addHRegUse(u, HRmRead, hregPPC_GPR8(mode64)); |
| 2372 | if (argir & (1<<7)) addHRegUse(u, HRmRead, hregPPC_GPR7(mode64)); |
| 2373 | if (argir & (1<<6)) addHRegUse(u, HRmRead, hregPPC_GPR6(mode64)); |
| 2374 | if (argir & (1<<5)) addHRegUse(u, HRmRead, hregPPC_GPR5(mode64)); |
| 2375 | if (argir & (1<<4)) addHRegUse(u, HRmRead, hregPPC_GPR4(mode64)); |
| 2376 | if (argir & (1<<3)) addHRegUse(u, HRmRead, hregPPC_GPR3(mode64)); |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 2377 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2378 | vassert(0 == (argir & ~((1<<3)|(1<<4)|(1<<5)|(1<<6) |
| 2379 | |(1<<7)|(1<<8)|(1<<9)|(1<<10)))); |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 2380 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2381 | /* Finally, there is the issue that the insn trashes a |
| 2382 | register because the literal target address has to be |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2383 | loaded into a register. %r10 seems a suitable victim. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2384 | (Can't use %r0, as some insns interpret it as value zero). */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2385 | addHRegUse(u, HRmWrite, hregPPC_GPR10(mode64)); |
| 2386 | /* Upshot of this is that the assembler really must use %r10, |
cerion | a56e9cc | 2005-02-16 18:08:25 +0000 | [diff] [blame] | 2387 | and no other, as a destination temporary. */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2388 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2389 | } |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 2390 | /* XDirect/XIndir/XAssisted are also a bit subtle. They |
| 2391 | conditionally exit the block. Hence we only need to list (1) |
| 2392 | the registers that they read, and (2) the registers that they |
| 2393 | write in the case where the block is not exited. (2) is empty, |
| 2394 | hence only (1) is relevant here. */ |
| 2395 | case Pin_XDirect: |
| 2396 | addRegUsage_PPCAMode(u, i->Pin.XDirect.amCIA); |
| 2397 | return; |
| 2398 | case Pin_XIndir: |
| 2399 | addHRegUse(u, HRmRead, i->Pin.XIndir.dstGA); |
| 2400 | addRegUsage_PPCAMode(u, i->Pin.XIndir.amCIA); |
| 2401 | return; |
| 2402 | case Pin_XAssisted: |
| 2403 | addHRegUse(u, HRmRead, i->Pin.XAssisted.dstGA); |
| 2404 | addRegUsage_PPCAMode(u, i->Pin.XAssisted.amCIA); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2405 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2406 | case Pin_CMov: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2407 | addRegUsage_PPCRI(u, i->Pin.CMov.src); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2408 | addHRegUse(u, HRmWrite, i->Pin.CMov.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2409 | return; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 2410 | case Pin_Load: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2411 | addRegUsage_PPCAMode(u, i->Pin.Load.src); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 2412 | addHRegUse(u, HRmWrite, i->Pin.Load.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2413 | return; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2414 | case Pin_LoadL: |
| 2415 | addHRegUse(u, HRmRead, i->Pin.LoadL.src); |
| 2416 | addHRegUse(u, HRmWrite, i->Pin.LoadL.dst); |
| 2417 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2418 | case Pin_Store: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2419 | addHRegUse(u, HRmRead, i->Pin.Store.src); |
| 2420 | addRegUsage_PPCAMode(u, i->Pin.Store.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2421 | return; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2422 | case Pin_StoreC: |
| 2423 | addHRegUse(u, HRmRead, i->Pin.StoreC.src); |
| 2424 | addHRegUse(u, HRmRead, i->Pin.StoreC.dst); |
| 2425 | return; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2426 | case Pin_Set: |
| 2427 | addHRegUse(u, HRmWrite, i->Pin.Set.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2428 | return; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2429 | case Pin_MfCR: |
| 2430 | addHRegUse(u, HRmWrite, i->Pin.MfCR.dst); |
| 2431 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2432 | case Pin_MFence: |
| 2433 | return; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2434 | |
| 2435 | case Pin_FpUnary: |
| 2436 | addHRegUse(u, HRmWrite, i->Pin.FpUnary.dst); |
| 2437 | addHRegUse(u, HRmRead, i->Pin.FpUnary.src); |
| 2438 | return; |
| 2439 | case Pin_FpBinary: |
| 2440 | addHRegUse(u, HRmWrite, i->Pin.FpBinary.dst); |
| 2441 | addHRegUse(u, HRmRead, i->Pin.FpBinary.srcL); |
| 2442 | addHRegUse(u, HRmRead, i->Pin.FpBinary.srcR); |
| 2443 | return; |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 2444 | case Pin_FpMulAcc: |
| 2445 | addHRegUse(u, HRmWrite, i->Pin.FpMulAcc.dst); |
| 2446 | addHRegUse(u, HRmRead, i->Pin.FpMulAcc.srcML); |
| 2447 | addHRegUse(u, HRmRead, i->Pin.FpMulAcc.srcMR); |
| 2448 | addHRegUse(u, HRmRead, i->Pin.FpMulAcc.srcAcc); |
| 2449 | return; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2450 | case Pin_FpLdSt: |
| 2451 | addHRegUse(u, (i->Pin.FpLdSt.isLoad ? HRmWrite : HRmRead), |
| 2452 | i->Pin.FpLdSt.reg); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2453 | addRegUsage_PPCAMode(u, i->Pin.FpLdSt.addr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2454 | return; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 2455 | case Pin_FpSTFIW: |
| 2456 | addHRegUse(u, HRmRead, i->Pin.FpSTFIW.addr); |
| 2457 | addHRegUse(u, HRmRead, i->Pin.FpSTFIW.data); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2458 | return; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 2459 | case Pin_FpRSP: |
| 2460 | addHRegUse(u, HRmWrite, i->Pin.FpRSP.dst); |
| 2461 | addHRegUse(u, HRmRead, i->Pin.FpRSP.src); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2462 | return; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 2463 | case Pin_FpCftI: |
| 2464 | addHRegUse(u, HRmWrite, i->Pin.FpCftI.dst); |
| 2465 | addHRegUse(u, HRmRead, i->Pin.FpCftI.src); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2466 | return; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2467 | case Pin_FpCMov: |
| 2468 | addHRegUse(u, HRmModify, i->Pin.FpCMov.dst); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2469 | addHRegUse(u, HRmRead, i->Pin.FpCMov.src); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2470 | return; |
| 2471 | case Pin_FpLdFPSCR: |
| 2472 | addHRegUse(u, HRmRead, i->Pin.FpLdFPSCR.src); |
| 2473 | return; |
| 2474 | case Pin_FpCmp: |
| 2475 | addHRegUse(u, HRmWrite, i->Pin.FpCmp.dst); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2476 | addHRegUse(u, HRmRead, i->Pin.FpCmp.srcL); |
| 2477 | addHRegUse(u, HRmRead, i->Pin.FpCmp.srcR); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2478 | return; |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 2479 | |
| 2480 | case Pin_RdWrLR: |
| 2481 | addHRegUse(u, (i->Pin.RdWrLR.wrLR ? HRmRead : HRmWrite), |
| 2482 | i->Pin.RdWrLR.gpr); |
| 2483 | return; |
| 2484 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2485 | case Pin_AvLdSt: |
| 2486 | addHRegUse(u, (i->Pin.AvLdSt.isLoad ? HRmWrite : HRmRead), |
| 2487 | i->Pin.AvLdSt.reg); |
| 2488 | if (i->Pin.AvLdSt.addr->tag == Pam_IR) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2489 | addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2490 | addRegUsage_PPCAMode(u, i->Pin.AvLdSt.addr); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2491 | return; |
| 2492 | case Pin_AvUnary: |
| 2493 | addHRegUse(u, HRmWrite, i->Pin.AvUnary.dst); |
| 2494 | addHRegUse(u, HRmRead, i->Pin.AvUnary.src); |
| 2495 | return; |
| 2496 | case Pin_AvBinary: |
sewardj | dc1f913 | 2005-10-22 12:49:49 +0000 | [diff] [blame] | 2497 | if (i->Pin.AvBinary.op == Pav_XOR |
florian | 79efdc6 | 2013-02-11 00:47:35 +0000 | [diff] [blame] | 2498 | && sameHReg(i->Pin.AvBinary.dst, i->Pin.AvBinary.srcL) |
| 2499 | && sameHReg(i->Pin.AvBinary.dst, i->Pin.AvBinary.srcR)) { |
sewardj | dc1f913 | 2005-10-22 12:49:49 +0000 | [diff] [blame] | 2500 | /* reg-alloc needs to understand 'xor r,r,r' as a write of r */ |
| 2501 | /* (as opposed to a rite of passage :-) */ |
| 2502 | addHRegUse(u, HRmWrite, i->Pin.AvBinary.dst); |
| 2503 | } else { |
| 2504 | addHRegUse(u, HRmWrite, i->Pin.AvBinary.dst); |
| 2505 | addHRegUse(u, HRmRead, i->Pin.AvBinary.srcL); |
| 2506 | addHRegUse(u, HRmRead, i->Pin.AvBinary.srcR); |
| 2507 | } |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2508 | return; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2509 | case Pin_AvBin8x16: |
| 2510 | addHRegUse(u, HRmWrite, i->Pin.AvBin8x16.dst); |
| 2511 | addHRegUse(u, HRmRead, i->Pin.AvBin8x16.srcL); |
| 2512 | addHRegUse(u, HRmRead, i->Pin.AvBin8x16.srcR); |
| 2513 | return; |
| 2514 | case Pin_AvBin16x8: |
| 2515 | addHRegUse(u, HRmWrite, i->Pin.AvBin16x8.dst); |
| 2516 | addHRegUse(u, HRmRead, i->Pin.AvBin16x8.srcL); |
| 2517 | addHRegUse(u, HRmRead, i->Pin.AvBin16x8.srcR); |
| 2518 | return; |
| 2519 | case Pin_AvBin32x4: |
| 2520 | addHRegUse(u, HRmWrite, i->Pin.AvBin32x4.dst); |
| 2521 | addHRegUse(u, HRmRead, i->Pin.AvBin32x4.srcL); |
| 2522 | addHRegUse(u, HRmRead, i->Pin.AvBin32x4.srcR); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2523 | return; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 2524 | case Pin_AvBin64x2: |
| 2525 | addHRegUse(u, HRmWrite, i->Pin.AvBin64x2.dst); |
| 2526 | addHRegUse(u, HRmRead, i->Pin.AvBin64x2.srcL); |
| 2527 | addHRegUse(u, HRmRead, i->Pin.AvBin64x2.srcR); |
| 2528 | return; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2529 | case Pin_AvBin32Fx4: |
| 2530 | addHRegUse(u, HRmWrite, i->Pin.AvBin32Fx4.dst); |
| 2531 | addHRegUse(u, HRmRead, i->Pin.AvBin32Fx4.srcL); |
| 2532 | addHRegUse(u, HRmRead, i->Pin.AvBin32Fx4.srcR); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 2533 | if (i->Pin.AvBin32Fx4.op == Pavfp_MULF) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2534 | addHRegUse(u, HRmWrite, hregPPC_VR29()); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 2535 | return; |
| 2536 | case Pin_AvUn32Fx4: |
| 2537 | addHRegUse(u, HRmWrite, i->Pin.AvUn32Fx4.dst); |
| 2538 | addHRegUse(u, HRmRead, i->Pin.AvUn32Fx4.src); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2539 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2540 | case Pin_AvPerm: |
| 2541 | addHRegUse(u, HRmWrite, i->Pin.AvPerm.dst); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2542 | addHRegUse(u, HRmRead, i->Pin.AvPerm.srcL); |
| 2543 | addHRegUse(u, HRmRead, i->Pin.AvPerm.srcR); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 2544 | addHRegUse(u, HRmRead, i->Pin.AvPerm.ctl); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2545 | return; |
| 2546 | case Pin_AvSel: |
| 2547 | addHRegUse(u, HRmWrite, i->Pin.AvSel.dst); |
| 2548 | addHRegUse(u, HRmRead, i->Pin.AvSel.ctl); |
| 2549 | addHRegUse(u, HRmRead, i->Pin.AvSel.srcL); |
| 2550 | addHRegUse(u, HRmRead, i->Pin.AvSel.srcR); |
| 2551 | return; |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 2552 | case Pin_AvSh: |
| 2553 | addHRegUse(u, HRmWrite, i->Pin.AvSh.dst); |
| 2554 | if (i->Pin.AvSh.addr->tag == Pam_IR) |
| 2555 | addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64)); |
| 2556 | addRegUsage_PPCAMode(u, i->Pin.AvSh.addr); |
| 2557 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2558 | case Pin_AvShlDbl: |
| 2559 | addHRegUse(u, HRmWrite, i->Pin.AvShlDbl.dst); |
| 2560 | addHRegUse(u, HRmRead, i->Pin.AvShlDbl.srcL); |
| 2561 | addHRegUse(u, HRmRead, i->Pin.AvShlDbl.srcR); |
| 2562 | return; |
| 2563 | case Pin_AvSplat: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2564 | addHRegUse(u, HRmWrite, i->Pin.AvSplat.dst); |
| 2565 | addRegUsage_PPCVI5s(u, i->Pin.AvSplat.src); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2566 | return; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2567 | case Pin_AvCMov: |
| 2568 | addHRegUse(u, HRmModify, i->Pin.AvCMov.dst); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2569 | addHRegUse(u, HRmRead, i->Pin.AvCMov.src); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2570 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2571 | case Pin_AvLdVSCR: |
| 2572 | addHRegUse(u, HRmRead, i->Pin.AvLdVSCR.src); |
| 2573 | return; |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 2574 | case Pin_AvCipherV128Unary: |
| 2575 | addHRegUse(u, HRmWrite, i->Pin.AvCipherV128Unary.dst); |
| 2576 | addHRegUse(u, HRmRead, i->Pin.AvCipherV128Unary.src); |
| 2577 | return; |
| 2578 | case Pin_AvCipherV128Binary: |
| 2579 | addHRegUse(u, HRmWrite, i->Pin.AvCipherV128Binary.dst); |
| 2580 | addHRegUse(u, HRmRead, i->Pin.AvCipherV128Binary.srcL); |
| 2581 | addHRegUse(u, HRmRead, i->Pin.AvCipherV128Binary.srcR); |
| 2582 | return; |
| 2583 | case Pin_AvHashV128Binary: |
| 2584 | addHRegUse(u, HRmWrite, i->Pin.AvHashV128Binary.dst); |
| 2585 | addHRegUse(u, HRmRead, i->Pin.AvHashV128Binary.src); |
| 2586 | addRegUsage_PPCRI(u, i->Pin.AvHashV128Binary.s_field); |
| 2587 | return; |
| 2588 | case Pin_AvBCDV128Trinary: |
| 2589 | addHRegUse(u, HRmWrite, i->Pin.AvBCDV128Trinary.dst); |
| 2590 | addHRegUse(u, HRmRead, i->Pin.AvBCDV128Trinary.src1); |
| 2591 | addHRegUse(u, HRmRead, i->Pin.AvBCDV128Trinary.src2); |
| 2592 | addRegUsage_PPCRI(u, i->Pin.AvBCDV128Trinary.ps); |
| 2593 | return; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2594 | case Pin_Dfp64Unary: |
| 2595 | addHRegUse(u, HRmWrite, i->Pin.Dfp64Unary.dst); |
| 2596 | addHRegUse(u, HRmRead, i->Pin.Dfp64Unary.src); |
| 2597 | return; |
| 2598 | case Pin_Dfp64Binary: |
| 2599 | addHRegUse(u, HRmWrite, i->Pin.Dfp64Binary.dst); |
| 2600 | addHRegUse(u, HRmRead, i->Pin.Dfp64Binary.srcL); |
| 2601 | addHRegUse(u, HRmRead, i->Pin.Dfp64Binary.srcR); |
| 2602 | return; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 2603 | case Pin_DfpShift: |
| 2604 | addRegUsage_PPCRI(u, i->Pin.DfpShift.shift); |
| 2605 | addHRegUse(u, HRmWrite, i->Pin.DfpShift.src); |
| 2606 | addHRegUse(u, HRmWrite, i->Pin.DfpShift.dst); |
| 2607 | return; |
| 2608 | case Pin_Dfp128Unary: |
| 2609 | addHRegUse(u, HRmWrite, i->Pin.Dfp128Unary.dst_hi); |
| 2610 | addHRegUse(u, HRmWrite, i->Pin.Dfp128Unary.dst_lo); |
| 2611 | addHRegUse(u, HRmRead, i->Pin.Dfp128Unary.src_hi); |
| 2612 | addHRegUse(u, HRmRead, i->Pin.Dfp128Unary.src_lo); |
| 2613 | return; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2614 | case Pin_Dfp128Binary: |
| 2615 | addHRegUse(u, HRmWrite, i->Pin.Dfp128Binary.dst_hi); |
| 2616 | addHRegUse(u, HRmWrite, i->Pin.Dfp128Binary.dst_lo); |
| 2617 | addHRegUse(u, HRmRead, i->Pin.Dfp128Binary.srcR_hi); |
| 2618 | addHRegUse(u, HRmRead, i->Pin.Dfp128Binary.srcR_lo); |
| 2619 | return; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 2620 | case Pin_DfpRound: |
| 2621 | addHRegUse(u, HRmWrite, i->Pin.DfpRound.dst); |
| 2622 | addHRegUse(u, HRmRead, i->Pin.DfpRound.src); |
| 2623 | return; |
| 2624 | case Pin_DfpRound128: |
| 2625 | addHRegUse(u, HRmWrite, i->Pin.DfpRound128.dst_hi); |
| 2626 | addHRegUse(u, HRmWrite, i->Pin.DfpRound128.dst_lo); |
| 2627 | addHRegUse(u, HRmRead, i->Pin.DfpRound128.src_hi); |
| 2628 | addHRegUse(u, HRmRead, i->Pin.DfpRound128.src_lo); |
| 2629 | return; |
| 2630 | case Pin_DfpQuantize: |
| 2631 | addRegUsage_PPCRI(u, i->Pin.DfpQuantize.rmc); |
| 2632 | addHRegUse(u, HRmWrite, i->Pin.DfpQuantize.dst); |
| 2633 | addHRegUse(u, HRmRead, i->Pin.DfpQuantize.srcL); |
| 2634 | addHRegUse(u, HRmRead, i->Pin.DfpQuantize.srcR); |
| 2635 | return; |
| 2636 | case Pin_DfpQuantize128: |
| 2637 | addHRegUse(u, HRmWrite, i->Pin.DfpQuantize128.dst_hi); |
| 2638 | addHRegUse(u, HRmWrite, i->Pin.DfpQuantize128.dst_lo); |
| 2639 | addHRegUse(u, HRmRead, i->Pin.DfpQuantize128.src_hi); |
| 2640 | addHRegUse(u, HRmRead, i->Pin.DfpQuantize128.src_lo); |
| 2641 | return; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 2642 | case Pin_DfpShift128: |
| 2643 | addRegUsage_PPCRI(u, i->Pin.DfpShift128.shift); |
| 2644 | addHRegUse(u, HRmWrite, i->Pin.DfpShift128.src_hi); |
| 2645 | addHRegUse(u, HRmWrite, i->Pin.DfpShift128.src_lo); |
| 2646 | addHRegUse(u, HRmWrite, i->Pin.DfpShift128.dst_hi); |
| 2647 | addHRegUse(u, HRmWrite, i->Pin.DfpShift128.dst_lo); |
| 2648 | return; |
| 2649 | case Pin_DfpD128toD64: |
| 2650 | addHRegUse(u, HRmWrite, i->Pin.DfpD128toD64.src_hi); |
| 2651 | addHRegUse(u, HRmWrite, i->Pin.DfpD128toD64.src_lo); |
| 2652 | addHRegUse(u, HRmWrite, i->Pin.DfpD128toD64.dst); |
| 2653 | return; |
| 2654 | case Pin_DfpI64StoD128: |
| 2655 | addHRegUse(u, HRmWrite, i->Pin.DfpI64StoD128.src); |
| 2656 | addHRegUse(u, HRmWrite, i->Pin.DfpI64StoD128.dst_hi); |
| 2657 | addHRegUse(u, HRmWrite, i->Pin.DfpI64StoD128.dst_lo); |
| 2658 | return; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 2659 | case Pin_ExtractExpD128: |
| 2660 | addHRegUse(u, HRmWrite, i->Pin.ExtractExpD128.dst); |
| 2661 | addHRegUse(u, HRmRead, i->Pin.ExtractExpD128.src_hi); |
| 2662 | addHRegUse(u, HRmRead, i->Pin.ExtractExpD128.src_lo); |
| 2663 | return; |
| 2664 | case Pin_InsertExpD128: |
| 2665 | addHRegUse(u, HRmWrite, i->Pin.InsertExpD128.dst_hi); |
| 2666 | addHRegUse(u, HRmWrite, i->Pin.InsertExpD128.dst_lo); |
| 2667 | addHRegUse(u, HRmRead, i->Pin.InsertExpD128.srcL); |
| 2668 | addHRegUse(u, HRmRead, i->Pin.InsertExpD128.srcR_hi); |
| 2669 | addHRegUse(u, HRmRead, i->Pin.InsertExpD128.srcR_lo); |
| 2670 | return; |
| 2671 | case Pin_Dfp64Cmp: |
| 2672 | addHRegUse(u, HRmWrite, i->Pin.Dfp64Cmp.dst); |
| 2673 | addHRegUse(u, HRmRead, i->Pin.Dfp64Cmp.srcL); |
| 2674 | addHRegUse(u, HRmRead, i->Pin.Dfp64Cmp.srcR); |
| 2675 | return; |
| 2676 | case Pin_Dfp128Cmp: |
| 2677 | addHRegUse(u, HRmWrite, i->Pin.Dfp128Cmp.dst); |
| 2678 | addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcL_hi); |
| 2679 | addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcL_lo); |
| 2680 | addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcR_hi); |
| 2681 | addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcR_lo); |
| 2682 | return; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 2683 | case Pin_EvCheck: |
| 2684 | /* We expect both amodes only to mention the GSP (r31), so this |
| 2685 | is in fact pointless, since GSP isn't allocatable, but |
| 2686 | anyway.. */ |
| 2687 | addRegUsage_PPCAMode(u, i->Pin.EvCheck.amCounter); |
| 2688 | addRegUsage_PPCAMode(u, i->Pin.EvCheck.amFailAddr); |
| 2689 | addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64)); /* also unavail to RA */ |
| 2690 | return; |
| 2691 | case Pin_ProfInc: |
| 2692 | addHRegUse(u, HRmWrite, hregPPC_GPR29(mode64)); |
| 2693 | addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64)); |
| 2694 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2695 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2696 | ppPPCInstr(i, mode64); |
| 2697 | vpanic("getRegUsage_PPCInstr"); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 2698 | } |
| 2699 | } |
| 2700 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 2701 | /* local helper */ |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 2702 | static void mapReg( HRegRemap* m, HReg* r ) |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 2703 | { |
| 2704 | *r = lookupHRegRemap(m, *r); |
| 2705 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 2706 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2707 | void mapRegs_PPCInstr ( HRegRemap* m, PPCInstr* i, Bool mode64 ) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 2708 | { |
| 2709 | switch (i->tag) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2710 | case Pin_LI: |
| 2711 | mapReg(m, &i->Pin.LI.dst); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2712 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2713 | case Pin_Alu: |
| 2714 | mapReg(m, &i->Pin.Alu.dst); |
| 2715 | mapReg(m, &i->Pin.Alu.srcL); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2716 | mapRegs_PPCRH(m, i->Pin.Alu.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2717 | return; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2718 | case Pin_Shft: |
| 2719 | mapReg(m, &i->Pin.Shft.dst); |
| 2720 | mapReg(m, &i->Pin.Shft.srcL); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2721 | mapRegs_PPCRH(m, i->Pin.Shft.srcR); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2722 | return; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2723 | case Pin_AddSubC: |
| 2724 | mapReg(m, &i->Pin.AddSubC.dst); |
| 2725 | mapReg(m, &i->Pin.AddSubC.srcL); |
| 2726 | mapReg(m, &i->Pin.AddSubC.srcR); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 2727 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2728 | case Pin_Cmp: |
| 2729 | mapReg(m, &i->Pin.Cmp.srcL); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2730 | mapRegs_PPCRH(m, i->Pin.Cmp.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2731 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2732 | case Pin_Unary: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2733 | mapReg(m, &i->Pin.Unary.dst); |
| 2734 | mapReg(m, &i->Pin.Unary.src); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2735 | return; |
| 2736 | case Pin_MulL: |
| 2737 | mapReg(m, &i->Pin.MulL.dst); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 2738 | mapReg(m, &i->Pin.MulL.srcL); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2739 | mapReg(m, &i->Pin.MulL.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2740 | return; |
| 2741 | case Pin_Div: |
| 2742 | mapReg(m, &i->Pin.Div.dst); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 2743 | mapReg(m, &i->Pin.Div.srcL); |
| 2744 | mapReg(m, &i->Pin.Div.srcR); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2745 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2746 | case Pin_Call: |
| 2747 | return; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 2748 | case Pin_XDirect: |
| 2749 | mapRegs_PPCAMode(m, i->Pin.XDirect.amCIA); |
| 2750 | return; |
| 2751 | case Pin_XIndir: |
| 2752 | mapReg(m, &i->Pin.XIndir.dstGA); |
| 2753 | mapRegs_PPCAMode(m, i->Pin.XIndir.amCIA); |
| 2754 | return; |
| 2755 | case Pin_XAssisted: |
| 2756 | mapReg(m, &i->Pin.XAssisted.dstGA); |
| 2757 | mapRegs_PPCAMode(m, i->Pin.XAssisted.amCIA); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2758 | return; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2759 | case Pin_CMov: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2760 | mapRegs_PPCRI(m, i->Pin.CMov.src); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2761 | mapReg(m, &i->Pin.CMov.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2762 | return; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 2763 | case Pin_Load: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2764 | mapRegs_PPCAMode(m, i->Pin.Load.src); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 2765 | mapReg(m, &i->Pin.Load.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2766 | return; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2767 | case Pin_LoadL: |
| 2768 | mapReg(m, &i->Pin.LoadL.src); |
| 2769 | mapReg(m, &i->Pin.LoadL.dst); |
| 2770 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2771 | case Pin_Store: |
| 2772 | mapReg(m, &i->Pin.Store.src); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2773 | mapRegs_PPCAMode(m, i->Pin.Store.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2774 | return; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2775 | case Pin_StoreC: |
| 2776 | mapReg(m, &i->Pin.StoreC.src); |
| 2777 | mapReg(m, &i->Pin.StoreC.dst); |
| 2778 | return; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2779 | case Pin_Set: |
| 2780 | mapReg(m, &i->Pin.Set.dst); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2781 | return; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2782 | case Pin_MfCR: |
| 2783 | mapReg(m, &i->Pin.MfCR.dst); |
| 2784 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2785 | case Pin_MFence: |
| 2786 | return; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 2787 | case Pin_FpUnary: |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2788 | mapReg(m, &i->Pin.FpUnary.dst); |
| 2789 | mapReg(m, &i->Pin.FpUnary.src); |
| 2790 | return; |
| 2791 | case Pin_FpBinary: |
| 2792 | mapReg(m, &i->Pin.FpBinary.dst); |
| 2793 | mapReg(m, &i->Pin.FpBinary.srcL); |
| 2794 | mapReg(m, &i->Pin.FpBinary.srcR); |
| 2795 | return; |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 2796 | case Pin_FpMulAcc: |
| 2797 | mapReg(m, &i->Pin.FpMulAcc.dst); |
| 2798 | mapReg(m, &i->Pin.FpMulAcc.srcML); |
| 2799 | mapReg(m, &i->Pin.FpMulAcc.srcMR); |
| 2800 | mapReg(m, &i->Pin.FpMulAcc.srcAcc); |
| 2801 | return; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2802 | case Pin_FpLdSt: |
| 2803 | mapReg(m, &i->Pin.FpLdSt.reg); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2804 | mapRegs_PPCAMode(m, i->Pin.FpLdSt.addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2805 | return; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 2806 | case Pin_FpSTFIW: |
| 2807 | mapReg(m, &i->Pin.FpSTFIW.addr); |
| 2808 | mapReg(m, &i->Pin.FpSTFIW.data); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2809 | return; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 2810 | case Pin_FpRSP: |
| 2811 | mapReg(m, &i->Pin.FpRSP.dst); |
| 2812 | mapReg(m, &i->Pin.FpRSP.src); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2813 | return; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 2814 | case Pin_FpCftI: |
| 2815 | mapReg(m, &i->Pin.FpCftI.dst); |
| 2816 | mapReg(m, &i->Pin.FpCftI.src); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2817 | return; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2818 | case Pin_FpCMov: |
| 2819 | mapReg(m, &i->Pin.FpCMov.dst); |
| 2820 | mapReg(m, &i->Pin.FpCMov.src); |
| 2821 | return; |
| 2822 | case Pin_FpLdFPSCR: |
| 2823 | mapReg(m, &i->Pin.FpLdFPSCR.src); |
| 2824 | return; |
| 2825 | case Pin_FpCmp: |
| 2826 | mapReg(m, &i->Pin.FpCmp.dst); |
| 2827 | mapReg(m, &i->Pin.FpCmp.srcL); |
| 2828 | mapReg(m, &i->Pin.FpCmp.srcR); |
| 2829 | return; |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 2830 | case Pin_RdWrLR: |
| 2831 | mapReg(m, &i->Pin.RdWrLR.gpr); |
| 2832 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2833 | case Pin_AvLdSt: |
| 2834 | mapReg(m, &i->Pin.AvLdSt.reg); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2835 | mapRegs_PPCAMode(m, i->Pin.AvLdSt.addr); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2836 | return; |
| 2837 | case Pin_AvUnary: |
| 2838 | mapReg(m, &i->Pin.AvUnary.dst); |
| 2839 | mapReg(m, &i->Pin.AvUnary.src); |
| 2840 | return; |
| 2841 | case Pin_AvBinary: |
| 2842 | mapReg(m, &i->Pin.AvBinary.dst); |
| 2843 | mapReg(m, &i->Pin.AvBinary.srcL); |
| 2844 | mapReg(m, &i->Pin.AvBinary.srcR); |
| 2845 | return; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2846 | case Pin_AvBin8x16: |
| 2847 | mapReg(m, &i->Pin.AvBin8x16.dst); |
| 2848 | mapReg(m, &i->Pin.AvBin8x16.srcL); |
| 2849 | mapReg(m, &i->Pin.AvBin8x16.srcR); |
| 2850 | return; |
| 2851 | case Pin_AvBin16x8: |
| 2852 | mapReg(m, &i->Pin.AvBin16x8.dst); |
| 2853 | mapReg(m, &i->Pin.AvBin16x8.srcL); |
| 2854 | mapReg(m, &i->Pin.AvBin16x8.srcR); |
| 2855 | return; |
| 2856 | case Pin_AvBin32x4: |
| 2857 | mapReg(m, &i->Pin.AvBin32x4.dst); |
| 2858 | mapReg(m, &i->Pin.AvBin32x4.srcL); |
| 2859 | mapReg(m, &i->Pin.AvBin32x4.srcR); |
| 2860 | return; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 2861 | case Pin_AvBin64x2: |
| 2862 | mapReg(m, &i->Pin.AvBin64x2.dst); |
| 2863 | mapReg(m, &i->Pin.AvBin64x2.srcL); |
| 2864 | mapReg(m, &i->Pin.AvBin64x2.srcR); |
| 2865 | return; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2866 | case Pin_AvBin32Fx4: |
| 2867 | mapReg(m, &i->Pin.AvBin32Fx4.dst); |
| 2868 | mapReg(m, &i->Pin.AvBin32Fx4.srcL); |
| 2869 | mapReg(m, &i->Pin.AvBin32Fx4.srcR); |
| 2870 | return; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 2871 | case Pin_AvUn32Fx4: |
| 2872 | mapReg(m, &i->Pin.AvUn32Fx4.dst); |
| 2873 | mapReg(m, &i->Pin.AvUn32Fx4.src); |
| 2874 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2875 | case Pin_AvPerm: |
| 2876 | mapReg(m, &i->Pin.AvPerm.dst); |
| 2877 | mapReg(m, &i->Pin.AvPerm.srcL); |
| 2878 | mapReg(m, &i->Pin.AvPerm.srcR); |
| 2879 | mapReg(m, &i->Pin.AvPerm.ctl); |
| 2880 | return; |
| 2881 | case Pin_AvSel: |
| 2882 | mapReg(m, &i->Pin.AvSel.dst); |
| 2883 | mapReg(m, &i->Pin.AvSel.srcL); |
| 2884 | mapReg(m, &i->Pin.AvSel.srcR); |
| 2885 | mapReg(m, &i->Pin.AvSel.ctl); |
| 2886 | return; |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 2887 | case Pin_AvSh: |
| 2888 | mapReg(m, &i->Pin.AvSh.dst); |
| 2889 | mapRegs_PPCAMode(m, i->Pin.AvSh.addr); |
| 2890 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2891 | case Pin_AvShlDbl: |
| 2892 | mapReg(m, &i->Pin.AvShlDbl.dst); |
| 2893 | mapReg(m, &i->Pin.AvShlDbl.srcL); |
| 2894 | mapReg(m, &i->Pin.AvShlDbl.srcR); |
| 2895 | return; |
| 2896 | case Pin_AvSplat: |
| 2897 | mapReg(m, &i->Pin.AvSplat.dst); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2898 | mapRegs_PPCVI5s(m, i->Pin.AvSplat.src); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2899 | return; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 2900 | case Pin_AvCMov: |
| 2901 | mapReg(m, &i->Pin.AvCMov.dst); |
| 2902 | mapReg(m, &i->Pin.AvCMov.src); |
| 2903 | return; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 2904 | case Pin_AvLdVSCR: |
| 2905 | mapReg(m, &i->Pin.AvLdVSCR.src); |
| 2906 | return; |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 2907 | case Pin_AvCipherV128Unary: |
| 2908 | mapReg(m, &i->Pin.AvCipherV128Unary.dst); |
| 2909 | mapReg(m, &i->Pin.AvCipherV128Unary.src); |
| 2910 | return; |
| 2911 | case Pin_AvCipherV128Binary: |
| 2912 | mapReg(m, &i->Pin.AvCipherV128Binary.dst); |
| 2913 | mapReg(m, &i->Pin.AvCipherV128Binary.srcL); |
| 2914 | mapReg(m, &i->Pin.AvCipherV128Binary.srcR); |
| 2915 | return; |
| 2916 | case Pin_AvHashV128Binary: |
| 2917 | mapRegs_PPCRI(m, i->Pin.AvHashV128Binary.s_field); |
| 2918 | mapReg(m, &i->Pin.AvHashV128Binary.dst); |
| 2919 | mapReg(m, &i->Pin.AvHashV128Binary.src); |
| 2920 | return; |
| 2921 | case Pin_AvBCDV128Trinary: |
| 2922 | mapReg(m, &i->Pin.AvBCDV128Trinary.dst); |
| 2923 | mapReg(m, &i->Pin.AvBCDV128Trinary.src1); |
| 2924 | mapReg(m, &i->Pin.AvBCDV128Trinary.src2); |
| 2925 | mapRegs_PPCRI(m, i->Pin.AvBCDV128Trinary.ps); |
| 2926 | return; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2927 | case Pin_Dfp64Unary: |
| 2928 | mapReg(m, &i->Pin.Dfp64Unary.dst); |
| 2929 | mapReg(m, &i->Pin.Dfp64Unary.src); |
| 2930 | return; |
| 2931 | case Pin_Dfp64Binary: |
| 2932 | mapReg(m, &i->Pin.Dfp64Binary.dst); |
| 2933 | mapReg(m, &i->Pin.Dfp64Binary.srcL); |
| 2934 | mapReg(m, &i->Pin.Dfp64Binary.srcR); |
| 2935 | return; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 2936 | case Pin_DfpShift: |
| 2937 | mapRegs_PPCRI(m, i->Pin.DfpShift.shift); |
| 2938 | mapReg(m, &i->Pin.DfpShift.src); |
| 2939 | mapReg(m, &i->Pin.DfpShift.dst); |
| 2940 | return; |
| 2941 | case Pin_Dfp128Unary: |
| 2942 | mapReg(m, &i->Pin.Dfp128Unary.dst_hi); |
| 2943 | mapReg(m, &i->Pin.Dfp128Unary.dst_lo); |
| 2944 | mapReg(m, &i->Pin.Dfp128Unary.src_hi); |
| 2945 | mapReg(m, &i->Pin.Dfp128Unary.src_lo); |
| 2946 | return; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2947 | case Pin_Dfp128Binary: |
| 2948 | mapReg(m, &i->Pin.Dfp128Binary.dst_hi); |
| 2949 | mapReg(m, &i->Pin.Dfp128Binary.dst_lo); |
| 2950 | mapReg(m, &i->Pin.Dfp128Binary.srcR_hi); |
| 2951 | mapReg(m, &i->Pin.Dfp128Binary.srcR_lo); |
| 2952 | return; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 2953 | case Pin_DfpShift128: |
| 2954 | mapRegs_PPCRI(m, i->Pin.DfpShift128.shift); |
| 2955 | mapReg(m, &i->Pin.DfpShift128.src_hi); |
| 2956 | mapReg(m, &i->Pin.DfpShift128.src_lo); |
| 2957 | mapReg(m, &i->Pin.DfpShift128.dst_hi); |
| 2958 | mapReg(m, &i->Pin.DfpShift128.dst_lo); |
| 2959 | return; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 2960 | case Pin_DfpRound: |
| 2961 | mapReg(m, &i->Pin.DfpRound.dst); |
| 2962 | mapReg(m, &i->Pin.DfpRound.src); |
| 2963 | return; |
| 2964 | case Pin_DfpRound128: |
| 2965 | mapReg(m, &i->Pin.DfpRound128.dst_hi); |
| 2966 | mapReg(m, &i->Pin.DfpRound128.dst_lo); |
| 2967 | mapReg(m, &i->Pin.DfpRound128.src_hi); |
| 2968 | mapReg(m, &i->Pin.DfpRound128.src_lo); |
| 2969 | return; |
| 2970 | case Pin_DfpQuantize: |
| 2971 | mapRegs_PPCRI(m, i->Pin.DfpQuantize.rmc); |
| 2972 | mapReg(m, &i->Pin.DfpQuantize.dst); |
| 2973 | mapReg(m, &i->Pin.DfpQuantize.srcL); |
| 2974 | mapReg(m, &i->Pin.DfpQuantize.srcR); |
| 2975 | return; |
| 2976 | case Pin_DfpQuantize128: |
| 2977 | mapRegs_PPCRI(m, i->Pin.DfpQuantize128.rmc); |
| 2978 | mapReg(m, &i->Pin.DfpQuantize128.dst_hi); |
| 2979 | mapReg(m, &i->Pin.DfpQuantize128.dst_lo); |
| 2980 | mapReg(m, &i->Pin.DfpQuantize128.src_hi); |
| 2981 | mapReg(m, &i->Pin.DfpQuantize128.src_lo); |
florian | a7b0d10 | 2012-06-15 20:55:43 +0000 | [diff] [blame] | 2982 | return; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 2983 | case Pin_DfpD128toD64: |
| 2984 | mapReg(m, &i->Pin.DfpD128toD64.src_hi); |
| 2985 | mapReg(m, &i->Pin.DfpD128toD64.src_lo); |
| 2986 | mapReg(m, &i->Pin.DfpD128toD64.dst); |
| 2987 | return; |
| 2988 | case Pin_DfpI64StoD128: |
| 2989 | mapReg(m, &i->Pin.DfpI64StoD128.src); |
| 2990 | mapReg(m, &i->Pin.DfpI64StoD128.dst_hi); |
| 2991 | mapReg(m, &i->Pin.DfpI64StoD128.dst_lo); |
| 2992 | return; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 2993 | case Pin_ExtractExpD128: |
| 2994 | mapReg(m, &i->Pin.ExtractExpD128.dst); |
| 2995 | mapReg(m, &i->Pin.ExtractExpD128.src_hi); |
| 2996 | mapReg(m, &i->Pin.ExtractExpD128.src_lo); |
| 2997 | return; |
| 2998 | case Pin_InsertExpD128: |
| 2999 | mapReg(m, &i->Pin.InsertExpD128.dst_hi); |
| 3000 | mapReg(m, &i->Pin.InsertExpD128.dst_lo); |
| 3001 | mapReg(m, &i->Pin.InsertExpD128.srcL); |
| 3002 | mapReg(m, &i->Pin.InsertExpD128.srcR_hi); |
| 3003 | mapReg(m, &i->Pin.InsertExpD128.srcR_lo); |
| 3004 | return; |
| 3005 | case Pin_Dfp64Cmp: |
| 3006 | mapReg(m, &i->Pin.Dfp64Cmp.dst); |
| 3007 | mapReg(m, &i->Pin.Dfp64Cmp.srcL); |
| 3008 | mapReg(m, &i->Pin.Dfp64Cmp.srcR); |
| 3009 | return; |
| 3010 | case Pin_Dfp128Cmp: |
| 3011 | mapReg(m, &i->Pin.Dfp128Cmp.dst); |
| 3012 | mapReg(m, &i->Pin.Dfp128Cmp.srcL_hi); |
| 3013 | mapReg(m, &i->Pin.Dfp128Cmp.srcL_lo); |
| 3014 | mapReg(m, &i->Pin.Dfp128Cmp.srcR_hi); |
| 3015 | mapReg(m, &i->Pin.Dfp128Cmp.srcR_lo); |
| 3016 | return; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3017 | case Pin_EvCheck: |
| 3018 | /* We expect both amodes only to mention the GSP (r31), so this |
| 3019 | is in fact pointless, since GSP isn't allocatable, but |
| 3020 | anyway.. */ |
| 3021 | mapRegs_PPCAMode(m, i->Pin.EvCheck.amCounter); |
| 3022 | mapRegs_PPCAMode(m, i->Pin.EvCheck.amFailAddr); |
| 3023 | return; |
| 3024 | case Pin_ProfInc: |
| 3025 | /* hardwires r29 and r30 -- nothing to modify. */ |
| 3026 | return; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3027 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3028 | ppPPCInstr(i, mode64); |
| 3029 | vpanic("mapRegs_PPCInstr"); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3030 | } |
| 3031 | } |
| 3032 | |
| 3033 | /* Figure out if i represents a reg-reg move, and if so assign the |
| 3034 | source and destination to *src and *dst. If in doubt say No. Used |
| 3035 | by the register allocator to do move coalescing. |
| 3036 | */ |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 3037 | Bool isMove_PPCInstr ( const PPCInstr* i, HReg* src, HReg* dst ) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3038 | { |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3039 | /* Moves between integer regs */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3040 | if (i->tag == Pin_Alu) { |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3041 | // or Rd,Rs,Rs == mr Rd,Rs |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3042 | if (i->Pin.Alu.op != Palu_OR) |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3043 | return False; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3044 | if (i->Pin.Alu.srcR->tag != Prh_Reg) |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3045 | return False; |
florian | 79efdc6 | 2013-02-11 00:47:35 +0000 | [diff] [blame] | 3046 | if (! sameHReg(i->Pin.Alu.srcR->Prh.Reg.reg, i->Pin.Alu.srcL)) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3047 | return False; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3048 | *src = i->Pin.Alu.srcL; |
| 3049 | *dst = i->Pin.Alu.dst; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3050 | return True; |
| 3051 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3052 | /* Moves between FP regs */ |
| 3053 | if (i->tag == Pin_FpUnary) { |
| 3054 | if (i->Pin.FpUnary.op != Pfp_MOV) |
| 3055 | return False; |
| 3056 | *src = i->Pin.FpUnary.src; |
| 3057 | *dst = i->Pin.FpUnary.dst; |
| 3058 | return True; |
| 3059 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3060 | return False; |
| 3061 | } |
| 3062 | |
| 3063 | |
cerion | 7594920 | 2005-12-24 13:14:11 +0000 | [diff] [blame] | 3064 | /* Generate ppc spill/reload instructions under the direction of the |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3065 | register allocator. Note it's critical these don't write the |
| 3066 | condition codes. */ |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 3067 | |
| 3068 | void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 3069 | HReg rreg, Int offsetB, Bool mode64 ) |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 3070 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3071 | PPCAMode* am; |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 3072 | vassert(!hregIsVirtual(rreg)); |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 3073 | *i1 = *i2 = NULL; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3074 | am = PPCAMode_IR( offsetB, GuestStatePtr(mode64) ); |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 3075 | switch (hregClass(rreg)) { |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 3076 | case HRcInt64: |
| 3077 | vassert(mode64); |
| 3078 | *i1 = PPCInstr_Store( 8, am, rreg, mode64 ); |
| 3079 | return; |
| 3080 | case HRcInt32: |
| 3081 | vassert(!mode64); |
| 3082 | *i1 = PPCInstr_Store( 4, am, rreg, mode64 ); |
| 3083 | return; |
| 3084 | case HRcFlt64: |
| 3085 | *i1 = PPCInstr_FpLdSt ( False/*store*/, 8, rreg, am ); |
| 3086 | return; |
| 3087 | case HRcVec128: |
| 3088 | // XXX: GPR30 used as spill register to kludge AltiVec |
| 3089 | // AMode_IR |
| 3090 | *i1 = PPCInstr_AvLdSt ( False/*store*/, 16, rreg, am ); |
| 3091 | return; |
| 3092 | default: |
| 3093 | ppHRegClass(hregClass(rreg)); |
| 3094 | vpanic("genSpill_PPC: unimplemented regclass"); |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 3095 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3096 | } |
| 3097 | |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 3098 | void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 3099 | HReg rreg, Int offsetB, Bool mode64 ) |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 3100 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3101 | PPCAMode* am; |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 3102 | vassert(!hregIsVirtual(rreg)); |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 3103 | *i1 = *i2 = NULL; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3104 | am = PPCAMode_IR( offsetB, GuestStatePtr(mode64) ); |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 3105 | switch (hregClass(rreg)) { |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 3106 | case HRcInt64: |
| 3107 | vassert(mode64); |
| 3108 | *i1 = PPCInstr_Load( 8, rreg, am, mode64 ); |
| 3109 | return; |
| 3110 | case HRcInt32: |
| 3111 | vassert(!mode64); |
| 3112 | *i1 = PPCInstr_Load( 4, rreg, am, mode64 ); |
| 3113 | return; |
| 3114 | case HRcFlt64: |
| 3115 | *i1 = PPCInstr_FpLdSt ( True/*load*/, 8, rreg, am ); |
| 3116 | return; |
| 3117 | case HRcVec128: |
| 3118 | // XXX: GPR30 used as spill register to kludge AltiVec AMode_IR |
| 3119 | *i1 = PPCInstr_AvLdSt ( True/*load*/, 16, rreg, am ); |
| 3120 | return; |
| 3121 | default: |
| 3122 | ppHRegClass(hregClass(rreg)); |
| 3123 | vpanic("genReload_PPC: unimplemented regclass"); |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 3124 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3125 | } |
| 3126 | |
| 3127 | |
cerion | 7594920 | 2005-12-24 13:14:11 +0000 | [diff] [blame] | 3128 | /* --------- The ppc assembler (bleh.) --------- */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 3129 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3130 | static UInt iregNo ( HReg r, Bool mode64 ) |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 3131 | { |
| 3132 | UInt n; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3133 | vassert(hregClass(r) == mode64 ? HRcInt64 : HRcInt32); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 3134 | vassert(!hregIsVirtual(r)); |
| 3135 | n = hregNumber(r); |
| 3136 | vassert(n <= 32); |
| 3137 | return n; |
| 3138 | } |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 3139 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3140 | static UInt fregNo ( HReg fr ) |
| 3141 | { |
| 3142 | UInt n; |
| 3143 | vassert(hregClass(fr) == HRcFlt64); |
| 3144 | vassert(!hregIsVirtual(fr)); |
| 3145 | n = hregNumber(fr); |
| 3146 | vassert(n <= 32); |
| 3147 | return n; |
| 3148 | } |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 3149 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 3150 | static UInt vregNo ( HReg v ) |
| 3151 | { |
| 3152 | UInt n; |
| 3153 | vassert(hregClass(v) == HRcVec128); |
| 3154 | vassert(!hregIsVirtual(v)); |
| 3155 | n = hregNumber(v); |
| 3156 | vassert(n <= 32); |
| 3157 | return n; |
| 3158 | } |
| 3159 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3160 | /* Emit an instruction ppc-endianly */ |
| 3161 | static UChar* emit32 ( UChar* p, UInt w32, VexEndness endness_host ) |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3162 | { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3163 | if (endness_host == VexEndnessBE) { |
| 3164 | *p++ = toUChar((w32 >> 24) & 0x000000FF); |
| 3165 | *p++ = toUChar((w32 >> 16) & 0x000000FF); |
| 3166 | *p++ = toUChar((w32 >> 8) & 0x000000FF); |
| 3167 | *p++ = toUChar((w32) & 0x000000FF); |
| 3168 | } else { |
| 3169 | *p++ = toUChar((w32) & 0x000000FF); |
| 3170 | *p++ = toUChar((w32 >> 8) & 0x000000FF); |
| 3171 | *p++ = toUChar((w32 >> 16) & 0x000000FF); |
| 3172 | *p++ = toUChar((w32 >> 24) & 0x000000FF); |
| 3173 | } |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3174 | return p; |
| 3175 | } |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 3176 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3177 | /* Fetch an instruction ppc-endianly */ |
| 3178 | static UInt fetch32 ( UChar* p, VexEndness endness_host ) |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3179 | { |
| 3180 | UInt w32 = 0; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3181 | if (endness_host == VexEndnessBE) { |
| 3182 | w32 |= ((0xFF & (UInt)p[0]) << 24); |
| 3183 | w32 |= ((0xFF & (UInt)p[1]) << 16); |
| 3184 | w32 |= ((0xFF & (UInt)p[2]) << 8); |
| 3185 | w32 |= ((0xFF & (UInt)p[3]) << 0); |
| 3186 | } else { |
| 3187 | w32 |= ((0xFF & (UInt)p[3]) << 24); |
| 3188 | w32 |= ((0xFF & (UInt)p[2]) << 16); |
| 3189 | w32 |= ((0xFF & (UInt)p[1]) << 8); |
| 3190 | w32 |= ((0xFF & (UInt)p[0]) << 0); |
| 3191 | } |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3192 | return w32; |
| 3193 | } |
| 3194 | |
cerion | 7594920 | 2005-12-24 13:14:11 +0000 | [diff] [blame] | 3195 | /* The following mkForm[...] functions refer to ppc instruction forms |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3196 | as per PPC32 p576 |
| 3197 | */ |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 3198 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3199 | static UChar* mkFormD ( UChar* p, UInt opc1, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3200 | UInt r1, UInt r2, UInt imm, VexEndness endness_host ) |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3201 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3202 | UInt theInstr; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3203 | vassert(opc1 < 0x40); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3204 | vassert(r1 < 0x20); |
| 3205 | vassert(r2 < 0x20); |
cerion | 35663a7 | 2005-03-01 09:11:49 +0000 | [diff] [blame] | 3206 | imm = imm & 0xFFFF; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3207 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (imm)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3208 | return emit32(p, theInstr, endness_host); |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3209 | } |
| 3210 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3211 | static UChar* mkFormMD ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3212 | UInt imm1, UInt imm2, UInt opc2, |
| 3213 | VexEndness endness_host ) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3214 | { |
| 3215 | UInt theInstr; |
| 3216 | vassert(opc1 < 0x40); |
| 3217 | vassert(r1 < 0x20); |
| 3218 | vassert(r2 < 0x20); |
| 3219 | vassert(imm1 < 0x40); |
| 3220 | vassert(imm2 < 0x40); |
| 3221 | vassert(opc2 < 0x08); |
| 3222 | imm2 = ((imm2 & 0x1F) << 1) | (imm2 >> 5); |
| 3223 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3224 | ((imm1 & 0x1F)<<11) | (imm2<<5) | |
| 3225 | (opc2<<2) | ((imm1 >> 5)<<1)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3226 | return emit32(p, theInstr, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3227 | } |
| 3228 | |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3229 | static UChar* mkFormX ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3230 | UInt r3, UInt opc2, UInt b0, VexEndness endness_host ) |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3231 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3232 | UInt theInstr; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3233 | vassert(opc1 < 0x40); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3234 | vassert(r1 < 0x20); |
| 3235 | vassert(r2 < 0x20); |
| 3236 | vassert(r3 < 0x20); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3237 | vassert(opc2 < 0x400); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3238 | vassert(b0 < 0x2); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3239 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
| 3240 | (r3<<11) | (opc2<<1) | (b0)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3241 | return emit32(p, theInstr, endness_host); |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3242 | } |
| 3243 | |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3244 | static UChar* mkFormXO ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3245 | UInt r3, UInt b10, UInt opc2, UInt b0, |
| 3246 | VexEndness endness_host ) |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3247 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3248 | UInt theInstr; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3249 | vassert(opc1 < 0x40); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3250 | vassert(r1 < 0x20); |
| 3251 | vassert(r2 < 0x20); |
| 3252 | vassert(r3 < 0x20); |
| 3253 | vassert(b10 < 0x2); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3254 | vassert(opc2 < 0x200); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3255 | vassert(b0 < 0x2); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3256 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
| 3257 | (r3<<11) | (b10 << 10) | (opc2<<1) | (b0)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3258 | return emit32(p, theInstr, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3259 | } |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3260 | |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3261 | static UChar* mkFormXL ( UChar* p, UInt opc1, UInt f1, UInt f2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3262 | UInt f3, UInt opc2, UInt b0, VexEndness endness_host ) |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3263 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3264 | UInt theInstr; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3265 | vassert(opc1 < 0x40); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3266 | vassert(f1 < 0x20); |
| 3267 | vassert(f2 < 0x20); |
| 3268 | vassert(f3 < 0x20); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3269 | vassert(opc2 < 0x400); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3270 | vassert(b0 < 0x2); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3271 | theInstr = ((opc1<<26) | (f1<<21) | (f2<<16) | |
| 3272 | (f3<<11) | (opc2<<1) | (b0)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3273 | return emit32(p, theInstr, endness_host); |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3274 | } |
| 3275 | |
| 3276 | // Note: for split field ops, give mnemonic arg |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3277 | static UChar* mkFormXFX ( UChar* p, UInt r1, UInt f2, UInt opc2, |
| 3278 | VexEndness endness_host ) |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3279 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3280 | UInt theInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3281 | vassert(r1 < 0x20); |
| 3282 | vassert(f2 < 0x20); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3283 | vassert(opc2 < 0x400); |
| 3284 | switch (opc2) { |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3285 | case 144: // mtcrf |
| 3286 | vassert(f2 < 0x100); |
| 3287 | f2 = f2 << 1; |
| 3288 | break; |
| 3289 | case 339: // mfspr |
| 3290 | case 371: // mftb |
| 3291 | case 467: // mtspr |
| 3292 | vassert(f2 < 0x400); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3293 | // re-arrange split field |
| 3294 | f2 = ((f2>>5) & 0x1F) | ((f2 & 0x1F)<<5); |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3295 | break; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3296 | default: vpanic("mkFormXFX(ppch)"); |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3297 | } |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3298 | theInstr = ((31<<26) | (r1<<21) | (f2<<11) | (opc2<<1)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3299 | return emit32(p, theInstr, endness_host); |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3300 | } |
| 3301 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3302 | // Only used by mtfsf |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3303 | static UChar* mkFormXFL ( UChar* p, UInt FM, UInt freg, UInt dfp_rm, |
| 3304 | VexEndness endness_host ) |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3305 | { |
| 3306 | UInt theInstr; |
| 3307 | vassert(FM < 0x100); |
| 3308 | vassert(freg < 0x20); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 3309 | theInstr = ((63<<26) | (FM<<17) | (dfp_rm<<16) | (freg<<11) | (711<<1)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3310 | return emit32(p, theInstr, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3311 | } |
| 3312 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3313 | static UChar* mkFormXS ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3314 | UInt imm, UInt opc2, UInt b0, |
| 3315 | VexEndness endness_host ) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3316 | { |
| 3317 | UInt theInstr; |
| 3318 | vassert(opc1 < 0x40); |
| 3319 | vassert(r1 < 0x20); |
| 3320 | vassert(r2 < 0x20); |
| 3321 | vassert(imm < 0x40); |
| 3322 | vassert(opc2 < 0x400); |
| 3323 | vassert(b0 < 0x2); |
| 3324 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
| 3325 | ((imm & 0x1F)<<11) | (opc2<<2) | ((imm>>5)<<1) | (b0)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3326 | return emit32(p, theInstr, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3327 | } |
| 3328 | |
| 3329 | |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3330 | #if 0 |
| 3331 | // 'b' |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3332 | static UChar* mkFormI ( UChar* p, UInt LI, UInt AA, UInt LK, |
| 3333 | VexEndness endness_host ) |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3334 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3335 | UInt theInstr; |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3336 | vassert(LI < 0x1000000); |
| 3337 | vassert(AA < 0x2); |
| 3338 | vassert(LK < 0x2); |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3339 | theInstr = ((18<<26) | (LI<<2) | (AA<<1) | (LK)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3340 | return emit32(p, theInstr, endness_host); |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3341 | } |
| 3342 | #endif |
| 3343 | |
| 3344 | // 'bc' |
| 3345 | static UChar* mkFormB ( UChar* p, UInt BO, UInt BI, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3346 | UInt BD, UInt AA, UInt LK, VexEndness endness_host ) |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3347 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3348 | UInt theInstr; |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3349 | vassert(BO < 0x20); |
| 3350 | vassert(BI < 0x20); |
| 3351 | vassert(BD < 0x4000); |
| 3352 | vassert(AA < 0x2); |
| 3353 | vassert(LK < 0x2); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3354 | theInstr = ((16<<26) | (BO<<21) | (BI<<16) | |
| 3355 | (BD<<2) | (AA<<1) | (LK)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3356 | return emit32(p, theInstr, endness_host); |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3357 | } |
| 3358 | |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3359 | // rotates |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3360 | static UChar* mkFormM ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3361 | UInt f3, UInt MB, UInt ME, UInt Rc, |
| 3362 | VexEndness endness_host ) |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3363 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3364 | UInt theInstr; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3365 | vassert(opc1 < 0x40); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3366 | vassert(r1 < 0x20); |
| 3367 | vassert(r2 < 0x20); |
| 3368 | vassert(f3 < 0x20); |
| 3369 | vassert(MB < 0x20); |
| 3370 | vassert(ME < 0x20); |
| 3371 | vassert(Rc < 0x2); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3372 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3373 | (f3<<11) | (MB<<6) | (ME<<1) | (Rc)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3374 | return emit32(p, theInstr, endness_host); |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3375 | } |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 3376 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3377 | static UChar* mkFormA ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3378 | UInt r3, UInt r4, UInt opc2, UInt b0, |
| 3379 | VexEndness endness_host ) |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3380 | { |
| 3381 | UInt theInstr; |
| 3382 | vassert(opc1 < 0x40); |
| 3383 | vassert(r1 < 0x20); |
| 3384 | vassert(r2 < 0x20); |
| 3385 | vassert(r3 < 0x20); |
| 3386 | vassert(r4 < 0x20); |
| 3387 | vassert(opc2 < 0x20); |
| 3388 | vassert(b0 < 0x2 ); |
| 3389 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | |
| 3390 | (r4<<6) | (opc2<<1) | (b0)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3391 | return emit32(p, theInstr, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 3392 | } |
| 3393 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 3394 | static UChar* mkFormZ22 ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3395 | UInt constant, UInt opc2, UInt b0, |
| 3396 | VexEndness endness_host) |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 3397 | { |
| 3398 | UInt theInstr; |
| 3399 | vassert(opc1 < 0x40); |
| 3400 | vassert(r1 < 0x20); |
| 3401 | vassert(r2 < 0x20); |
| 3402 | vassert(constant < 0x40); /* 6 bit constant */ |
| 3403 | vassert(opc2 < 0x200); /* 9 bit field */ |
| 3404 | vassert(b0 < 0x2); |
| 3405 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
| 3406 | (constant<<10) | (opc2<<1) | (b0)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3407 | return emit32(p, theInstr, endness_host); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 3408 | } |
| 3409 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 3410 | static UChar* mkFormZ23 ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3411 | UInt r3, UInt rmc, UInt opc2, UInt b0, |
| 3412 | VexEndness endness_host) |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 3413 | { |
| 3414 | UInt theInstr; |
| 3415 | vassert(opc1 < 0x40); |
| 3416 | vassert(r1 < 0x20); |
| 3417 | vassert(r2 < 0x20); |
| 3418 | vassert(r3 < 0x20); |
| 3419 | vassert(rmc < 0x4); |
| 3420 | vassert(opc2 < 0x100); |
| 3421 | vassert(b0 < 0x2); |
| 3422 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
| 3423 | (r3<<11) | (rmc<<9) | (opc2<<1) | (b0)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3424 | return emit32(p, theInstr, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 3425 | } |
| 3426 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3427 | static UChar* doAMode_IR ( UChar* p, UInt opc1, UInt rSD, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3428 | PPCAMode* am, Bool mode64, VexEndness endness_host ) |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3429 | { |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 3430 | UInt rA, idx; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3431 | vassert(am->tag == Pam_IR); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3432 | vassert(am->Pam.IR.index < 0x10000); |
| 3433 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3434 | rA = iregNo(am->Pam.IR.base, mode64); |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 3435 | idx = am->Pam.IR.index; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3436 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3437 | if (opc1 == 58 || opc1 == 62) { // ld/std: mode64 only |
| 3438 | vassert(mode64); |
sewardj | 34085e3 | 2007-03-09 18:07:00 +0000 | [diff] [blame] | 3439 | /* stay sane with DS form: lowest 2 bits must be 00. This |
| 3440 | should be guaranteed to us by iselWordExpr_AMode. */ |
| 3441 | vassert(0 == (idx & 3)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3442 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3443 | p = mkFormD(p, opc1, rSD, rA, idx, endness_host); |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3444 | return p; |
| 3445 | } |
| 3446 | |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3447 | static UChar* doAMode_RR ( UChar* p, UInt opc1, UInt opc2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3448 | UInt rSD, PPCAMode* am, Bool mode64, |
| 3449 | VexEndness endness_host ) |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3450 | { |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 3451 | UInt rA, rB; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3452 | vassert(am->tag == Pam_RR); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3453 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3454 | rA = iregNo(am->Pam.RR.base, mode64); |
| 3455 | rB = iregNo(am->Pam.RR.index, mode64); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 3456 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3457 | p = mkFormX(p, opc1, rSD, rA, rB, opc2, 0, endness_host); |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3458 | return p; |
| 3459 | } |
| 3460 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3461 | |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 3462 | /* Load imm to r_dst */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3463 | static UChar* mkLoadImm ( UChar* p, UInt r_dst, ULong imm, Bool mode64, |
| 3464 | VexEndness endness_host ) |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 3465 | { |
| 3466 | vassert(r_dst < 0x20); |
| 3467 | |
sewardj | afd1639 | 2006-05-06 14:40:40 +0000 | [diff] [blame] | 3468 | if (!mode64) { |
| 3469 | /* In 32-bit mode, make sure the top 32 bits of imm are a sign |
| 3470 | extension of the bottom 32 bits, so that the range tests |
| 3471 | below work correctly. */ |
| 3472 | UInt u32 = (UInt)imm; |
| 3473 | Int s32 = (Int)u32; |
| 3474 | Long s64 = (Long)s32; |
| 3475 | imm = (ULong)s64; |
| 3476 | } |
| 3477 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3478 | if (imm >= 0xFFFFFFFFFFFF8000ULL || imm < 0x8000) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3479 | // sign-extendable from 16 bits |
| 3480 | |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 3481 | // addi r_dst,0,imm => li r_dst,imm |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3482 | p = mkFormD(p, 14, r_dst, 0, imm & 0xFFFF, endness_host); |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 3483 | } else { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3484 | if (imm >= 0xFFFFFFFF80000000ULL || imm < 0x80000000ULL) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3485 | // sign-extendable from 32 bits |
| 3486 | |
| 3487 | // addis r_dst,r0,(imm>>16) => lis r_dst, (imm>>16) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3488 | p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3489 | // ori r_dst, r_dst, (imm & 0xFFFF) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3490 | p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3491 | } else { |
| 3492 | // full 64bit immediate load: 5 (five!) insns. |
| 3493 | vassert(mode64); |
| 3494 | |
| 3495 | // load high word |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 3496 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3497 | // lis r_dst, (imm>>48) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3498 | p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF, endness_host); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 3499 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3500 | // ori r_dst, r_dst, (imm>>32) & 0xFFFF |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 3501 | if ((imm>>32) & 0xFFFF) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3502 | p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3503 | |
| 3504 | // shift r_dst low word to high word => rldicr |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3505 | p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3506 | |
| 3507 | // load low word |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 3508 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3509 | // oris r_dst, r_dst, (imm>>16) & 0xFFFF |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 3510 | if ((imm>>16) & 0xFFFF) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3511 | p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF, endness_host); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 3512 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3513 | // ori r_dst, r_dst, (imm) & 0xFFFF |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 3514 | if (imm & 0xFFFF) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3515 | p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3516 | } |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 3517 | } |
| 3518 | return p; |
| 3519 | } |
| 3520 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3521 | /* A simplified version of mkLoadImm that always generates 2 or 5 |
| 3522 | instructions (32 or 64 bits respectively) even if it could generate |
| 3523 | fewer. This is needed for generating fixed sized patchable |
| 3524 | sequences. */ |
| 3525 | static UChar* mkLoadImm_EXACTLY2or5 ( UChar* p, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3526 | UInt r_dst, ULong imm, Bool mode64, |
| 3527 | VexEndness endness_host ) |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3528 | { |
| 3529 | vassert(r_dst < 0x20); |
| 3530 | |
| 3531 | if (!mode64) { |
| 3532 | /* In 32-bit mode, make sure the top 32 bits of imm are a sign |
| 3533 | extension of the bottom 32 bits. (Probably unnecessary.) */ |
| 3534 | UInt u32 = (UInt)imm; |
| 3535 | Int s32 = (Int)u32; |
| 3536 | Long s64 = (Long)s32; |
| 3537 | imm = (ULong)s64; |
| 3538 | } |
| 3539 | |
| 3540 | if (!mode64) { |
| 3541 | // addis r_dst,r0,(imm>>16) => lis r_dst, (imm>>16) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3542 | p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3543 | // ori r_dst, r_dst, (imm & 0xFFFF) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3544 | p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3545 | |
| 3546 | } else { |
| 3547 | // full 64bit immediate load: 5 (five!) insns. |
| 3548 | |
| 3549 | // load high word |
| 3550 | // lis r_dst, (imm>>48) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3551 | p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3552 | |
| 3553 | // ori r_dst, r_dst, (imm>>32) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3554 | p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3555 | |
| 3556 | // shift r_dst low word to high word => rldicr |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3557 | p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3558 | |
| 3559 | // load low word |
| 3560 | // oris r_dst, r_dst, (imm>>16) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3561 | p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3562 | |
| 3563 | // ori r_dst, r_dst, (imm) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3564 | p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3565 | } |
| 3566 | return p; |
| 3567 | } |
| 3568 | |
| 3569 | /* Checks whether the sequence of bytes at p was indeed created |
| 3570 | by mkLoadImm_EXACTLY2or5 with the given parameters. */ |
| 3571 | static Bool isLoadImm_EXACTLY2or5 ( UChar* p_to_check, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3572 | UInt r_dst, ULong imm, Bool mode64, |
| 3573 | VexEndness endness_host ) |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3574 | { |
| 3575 | vassert(r_dst < 0x20); |
| 3576 | |
| 3577 | if (!mode64) { |
| 3578 | /* In 32-bit mode, make sure the top 32 bits of imm are a sign |
| 3579 | extension of the bottom 32 bits. (Probably unnecessary.) */ |
| 3580 | UInt u32 = (UInt)imm; |
| 3581 | Int s32 = (Int)u32; |
| 3582 | Long s64 = (Long)s32; |
| 3583 | imm = (ULong)s64; |
| 3584 | } |
| 3585 | |
| 3586 | if (!mode64) { |
| 3587 | UInt expect[2] = { 0, 0 }; |
| 3588 | UChar* p = (UChar*)&expect[0]; |
| 3589 | // addis r_dst,r0,(imm>>16) => lis r_dst, (imm>>16) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3590 | p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3591 | // ori r_dst, r_dst, (imm & 0xFFFF) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3592 | p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3593 | vassert(p == (UChar*)&expect[2]); |
| 3594 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3595 | return fetch32(p_to_check + 0, endness_host) == expect[0] |
| 3596 | && fetch32(p_to_check + 4, endness_host) == expect[1]; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3597 | |
| 3598 | } else { |
| 3599 | UInt expect[5] = { 0, 0, 0, 0, 0 }; |
| 3600 | UChar* p = (UChar*)&expect[0]; |
| 3601 | // full 64bit immediate load: 5 (five!) insns. |
| 3602 | |
| 3603 | // load high word |
| 3604 | // lis r_dst, (imm>>48) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3605 | p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3606 | |
| 3607 | // ori r_dst, r_dst, (imm>>32) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3608 | p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3609 | |
| 3610 | // shift r_dst low word to high word => rldicr |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3611 | p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3612 | |
| 3613 | // load low word |
| 3614 | // oris r_dst, r_dst, (imm>>16) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3615 | p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3616 | |
| 3617 | // ori r_dst, r_dst, (imm) & 0xFFFF |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3618 | p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3619 | |
| 3620 | vassert(p == (UChar*)&expect[5]); |
| 3621 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3622 | return fetch32(p_to_check + 0, endness_host) == expect[0] |
| 3623 | && fetch32(p_to_check + 4, endness_host) == expect[1] |
| 3624 | && fetch32(p_to_check + 8, endness_host) == expect[2] |
| 3625 | && fetch32(p_to_check + 12, endness_host) == expect[3] |
| 3626 | && fetch32(p_to_check + 16, endness_host) == expect[4]; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3627 | } |
| 3628 | } |
| 3629 | |
| 3630 | |
| 3631 | /* Generate a machine-word sized load or store. Simplified version of |
| 3632 | the Pin_Load and Pin_Store cases below. */ |
| 3633 | static UChar* do_load_or_store_machine_word ( |
| 3634 | UChar* p, Bool isLoad, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3635 | UInt reg, PPCAMode* am, Bool mode64, VexEndness endness_host ) |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3636 | { |
| 3637 | if (isLoad) { |
| 3638 | UInt opc1, sz = mode64 ? 8 : 4; |
| 3639 | switch (am->tag) { |
| 3640 | case Pam_IR: |
| 3641 | if (mode64) { |
| 3642 | vassert(0 == (am->Pam.IR.index & 3)); |
| 3643 | } |
| 3644 | switch (sz) { |
| 3645 | case 4: opc1 = 32; vassert(!mode64); break; |
| 3646 | case 8: opc1 = 58; vassert(mode64); break; |
| 3647 | default: vassert(0); |
| 3648 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3649 | p = doAMode_IR(p, opc1, reg, am, mode64, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3650 | break; |
| 3651 | case Pam_RR: |
| 3652 | /* we could handle this case, but we don't expect to ever |
| 3653 | need to. */ |
| 3654 | vassert(0); |
| 3655 | default: |
| 3656 | vassert(0); |
| 3657 | } |
| 3658 | } else /*store*/ { |
| 3659 | UInt opc1, sz = mode64 ? 8 : 4; |
| 3660 | switch (am->tag) { |
| 3661 | case Pam_IR: |
| 3662 | if (mode64) { |
| 3663 | vassert(0 == (am->Pam.IR.index & 3)); |
| 3664 | } |
| 3665 | switch (sz) { |
| 3666 | case 4: opc1 = 36; vassert(!mode64); break; |
| 3667 | case 8: opc1 = 62; vassert(mode64); break; |
| 3668 | default: vassert(0); |
| 3669 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3670 | p = doAMode_IR(p, opc1, reg, am, mode64, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3671 | break; |
| 3672 | case Pam_RR: |
| 3673 | /* we could handle this case, but we don't expect to ever |
| 3674 | need to. */ |
| 3675 | vassert(0); |
| 3676 | default: |
| 3677 | vassert(0); |
| 3678 | } |
| 3679 | } |
| 3680 | return p; |
| 3681 | } |
| 3682 | |
| 3683 | /* Generate a 32-bit sized load or store. Simplified version of |
| 3684 | do_load_or_store_machine_word above. */ |
| 3685 | static UChar* do_load_or_store_word32 ( |
| 3686 | UChar* p, Bool isLoad, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3687 | UInt reg, PPCAMode* am, Bool mode64, VexEndness endness_host ) |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3688 | { |
| 3689 | if (isLoad) { |
| 3690 | UInt opc1; |
| 3691 | switch (am->tag) { |
| 3692 | case Pam_IR: |
| 3693 | if (mode64) { |
| 3694 | vassert(0 == (am->Pam.IR.index & 3)); |
| 3695 | } |
| 3696 | opc1 = 32; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3697 | p = doAMode_IR(p, opc1, reg, am, mode64, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3698 | break; |
| 3699 | case Pam_RR: |
| 3700 | /* we could handle this case, but we don't expect to ever |
| 3701 | need to. */ |
| 3702 | vassert(0); |
| 3703 | default: |
| 3704 | vassert(0); |
| 3705 | } |
| 3706 | } else /*store*/ { |
| 3707 | UInt opc1; |
| 3708 | switch (am->tag) { |
| 3709 | case Pam_IR: |
| 3710 | if (mode64) { |
| 3711 | vassert(0 == (am->Pam.IR.index & 3)); |
| 3712 | } |
| 3713 | opc1 = 36; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3714 | p = doAMode_IR(p, opc1, reg, am, mode64, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3715 | break; |
| 3716 | case Pam_RR: |
| 3717 | /* we could handle this case, but we don't expect to ever |
| 3718 | need to. */ |
| 3719 | vassert(0); |
| 3720 | default: |
| 3721 | vassert(0); |
| 3722 | } |
| 3723 | } |
| 3724 | return p; |
| 3725 | } |
| 3726 | |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 3727 | /* Move r_dst to r_src */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3728 | static UChar* mkMoveReg ( UChar* p, UInt r_dst, UInt r_src, |
| 3729 | VexEndness endness_host ) |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 3730 | { |
| 3731 | vassert(r_dst < 0x20); |
| 3732 | vassert(r_src < 0x20); |
| 3733 | |
| 3734 | if (r_dst != r_src) { |
| 3735 | /* or r_dst, r_src, r_src */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3736 | p = mkFormX(p, 31, r_src, r_dst, r_src, 444, 0, endness_host ); |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 3737 | } |
| 3738 | return p; |
| 3739 | } |
| 3740 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 3741 | static UChar* mkFormVX ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3742 | UInt r3, UInt opc2, VexEndness endness_host ) |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 3743 | { |
| 3744 | UInt theInstr; |
| 3745 | vassert(opc1 < 0x40); |
| 3746 | vassert(r1 < 0x20); |
| 3747 | vassert(r2 < 0x20); |
| 3748 | vassert(r3 < 0x20); |
| 3749 | vassert(opc2 < 0x800); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 3750 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | opc2); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3751 | return emit32(p, theInstr, endness_host); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 3752 | } |
| 3753 | |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 3754 | static UChar* mkFormVXI ( UChar* p, UInt opc1, UInt r1, UInt r2, |
| 3755 | UInt r3, UInt opc2, VexEndness endness_host ) |
| 3756 | { |
| 3757 | UInt theInstr; |
| 3758 | vassert(opc1 < 0x40); |
| 3759 | vassert(r1 < 0x20); |
| 3760 | vassert(r2 < 0x20); |
| 3761 | vassert(r3 < 0x20); |
| 3762 | vassert(opc2 < 0x27); |
| 3763 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | opc2<<1); |
| 3764 | return emit32(p, theInstr, endness_host); |
| 3765 | } |
| 3766 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 3767 | static UChar* mkFormVXR ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3768 | UInt r3, UInt Rc, UInt opc2, |
| 3769 | VexEndness endness_host ) |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 3770 | { |
| 3771 | UInt theInstr; |
| 3772 | vassert(opc1 < 0x40); |
| 3773 | vassert(r1 < 0x20); |
| 3774 | vassert(r2 < 0x20); |
| 3775 | vassert(r3 < 0x20); |
| 3776 | vassert(Rc < 0x2); |
| 3777 | vassert(opc2 < 0x400); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3778 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
| 3779 | (r3<<11) | (Rc<<10) | opc2); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3780 | return emit32(p, theInstr, endness_host); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 3781 | } |
| 3782 | |
| 3783 | static UChar* mkFormVA ( UChar* p, UInt opc1, UInt r1, UInt r2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3784 | UInt r3, UInt r4, UInt opc2, VexEndness endness_host ) |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 3785 | { |
| 3786 | UInt theInstr; |
| 3787 | vassert(opc1 < 0x40); |
| 3788 | vassert(r1 < 0x20); |
| 3789 | vassert(r2 < 0x20); |
| 3790 | vassert(r3 < 0x20); |
| 3791 | vassert(r4 < 0x20); |
| 3792 | vassert(opc2 < 0x40); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3793 | theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | |
| 3794 | (r3<<11) | (r4<<6) | opc2); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3795 | return emit32(p, theInstr, endness_host); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 3796 | } |
| 3797 | |
| 3798 | |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 3799 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3800 | /* Emit an instruction into buf and return the number of bytes used. |
| 3801 | Note that buf is not the insn's final place, and therefore it is |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3802 | imperative to emit position-independent code. If the emitted |
| 3803 | instruction was a profiler inc, set *is_profInc to True, else leave |
| 3804 | it unchanged. |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 3805 | */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 3806 | Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 3807 | UChar* buf, Int nbuf, const PPCInstr* i, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 3808 | Bool mode64, VexEndness endness_host, |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 3809 | const void* disp_cp_chain_me_to_slowEP, |
| 3810 | const void* disp_cp_chain_me_to_fastEP, |
| 3811 | const void* disp_cp_xindir, |
| 3812 | const void* disp_cp_xassisted) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3813 | { |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3814 | UChar* p = &buf[0]; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 3815 | vassert(nbuf >= 32); |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 3816 | |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 3817 | if (0) { |
| 3818 | vex_printf("asm ");ppPPCInstr(i, mode64); vex_printf("\n"); |
| 3819 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 3820 | |
| 3821 | switch (i->tag) { |
| 3822 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3823 | case Pin_LI: |
| 3824 | p = mkLoadImm(p, iregNo(i->Pin.LI.dst, mode64), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3825 | i->Pin.LI.imm64, mode64, endness_host); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3826 | goto done; |
| 3827 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3828 | case Pin_Alu: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3829 | PPCRH* srcR = i->Pin.Alu.srcR; |
| 3830 | Bool immR = toBool(srcR->tag == Prh_Imm); |
| 3831 | UInt r_dst = iregNo(i->Pin.Alu.dst, mode64); |
| 3832 | UInt r_srcL = iregNo(i->Pin.Alu.srcL, mode64); |
| 3833 | UInt r_srcR = immR ? (-1)/*bogus*/ : |
| 3834 | iregNo(srcR->Prh.Reg.reg, mode64); |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 3835 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3836 | switch (i->Pin.Alu.op) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3837 | case Palu_ADD: |
| 3838 | if (immR) { |
| 3839 | /* addi (PPC32 p350) */ |
| 3840 | vassert(srcR->Prh.Imm.syned); |
| 3841 | vassert(srcR->Prh.Imm.imm16 != 0x8000); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3842 | p = mkFormD(p, 14, r_dst, r_srcL, srcR->Prh.Imm.imm16, endness_host); |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 3843 | } else { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3844 | /* add (PPC32 p347) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3845 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 266, 0, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3846 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3847 | break; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3848 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3849 | case Palu_SUB: |
| 3850 | if (immR) { |
| 3851 | /* addi (PPC32 p350), but with negated imm */ |
| 3852 | vassert(srcR->Prh.Imm.syned); |
| 3853 | vassert(srcR->Prh.Imm.imm16 != 0x8000); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3854 | p = mkFormD(p, 14, r_dst, r_srcL, (- srcR->Prh.Imm.imm16), |
| 3855 | endness_host); |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 3856 | } else { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3857 | /* subf (PPC32 p537), with args the "wrong" way round */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3858 | p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 40, 0, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 3859 | } |
cerion | 5e2527e | 2005-02-25 16:39:58 +0000 | [diff] [blame] | 3860 | break; |
cerion | 5e2527e | 2005-02-25 16:39:58 +0000 | [diff] [blame] | 3861 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3862 | case Palu_AND: |
| 3863 | if (immR) { |
| 3864 | /* andi. (PPC32 p358) */ |
| 3865 | vassert(!srcR->Prh.Imm.syned); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3866 | p = mkFormD(p, 28, r_srcL, r_dst, srcR->Prh.Imm.imm16, endness_host); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3867 | } else { |
| 3868 | /* and (PPC32 p356) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3869 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 28, 0, endness_host); |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 3870 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3871 | break; |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 3872 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3873 | case Palu_OR: |
| 3874 | if (immR) { |
| 3875 | /* ori (PPC32 p497) */ |
| 3876 | vassert(!srcR->Prh.Imm.syned); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3877 | p = mkFormD(p, 24, r_srcL, r_dst, srcR->Prh.Imm.imm16, endness_host); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3878 | } else { |
| 3879 | /* or (PPC32 p495) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3880 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 444, 0, endness_host); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3881 | } |
| 3882 | break; |
| 3883 | |
| 3884 | case Palu_XOR: |
| 3885 | if (immR) { |
| 3886 | /* xori (PPC32 p550) */ |
| 3887 | vassert(!srcR->Prh.Imm.syned); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3888 | p = mkFormD(p, 26, r_srcL, r_dst, srcR->Prh.Imm.imm16, endness_host); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3889 | } else { |
| 3890 | /* xor (PPC32 p549) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3891 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 316, 0, endness_host); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3892 | } |
| 3893 | break; |
| 3894 | |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3895 | default: |
| 3896 | goto bad; |
| 3897 | } |
| 3898 | goto done; |
| 3899 | } |
| 3900 | |
| 3901 | case Pin_Shft: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3902 | PPCRH* srcR = i->Pin.Shft.srcR; |
| 3903 | Bool sz32 = i->Pin.Shft.sz32; |
| 3904 | Bool immR = toBool(srcR->tag == Prh_Imm); |
| 3905 | UInt r_dst = iregNo(i->Pin.Shft.dst, mode64); |
| 3906 | UInt r_srcL = iregNo(i->Pin.Shft.srcL, mode64); |
| 3907 | UInt r_srcR = immR ? (-1)/*bogus*/ : |
| 3908 | iregNo(srcR->Prh.Reg.reg, mode64); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3909 | if (!mode64) |
| 3910 | vassert(sz32); |
| 3911 | |
| 3912 | switch (i->Pin.Shft.op) { |
| 3913 | case Pshft_SHL: |
| 3914 | if (sz32) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3915 | if (immR) { |
| 3916 | /* rd = rs << n, 1 <= n <= 31 |
| 3917 | is |
| 3918 | rlwinm rd,rs,n,0,31-n (PPC32 p501) |
| 3919 | */ |
| 3920 | UInt n = srcR->Prh.Imm.imm16; |
| 3921 | vassert(!srcR->Prh.Imm.syned); |
| 3922 | vassert(n > 0 && n < 32); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3923 | p = mkFormM(p, 21, r_srcL, r_dst, n, 0, 31-n, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3924 | } else { |
| 3925 | /* slw (PPC32 p505) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3926 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 24, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3927 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3928 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3929 | if (immR) { |
| 3930 | /* rd = rs << n, 1 <= n <= 63 |
| 3931 | is |
| 3932 | rldicr rd,rs,n,63-n (PPC64 p559) |
| 3933 | */ |
| 3934 | UInt n = srcR->Prh.Imm.imm16; |
| 3935 | vassert(!srcR->Prh.Imm.syned); |
| 3936 | vassert(n > 0 && n < 64); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3937 | p = mkFormMD(p, 30, r_srcL, r_dst, n, 63-n, 1, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3938 | } else { |
| 3939 | /* sld (PPC64 p568) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3940 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 27, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3941 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3942 | } |
| 3943 | break; |
| 3944 | |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3945 | case Pshft_SHR: |
| 3946 | if (sz32) { |
| 3947 | if (immR) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3948 | /* rd = rs >>u n, 1 <= n <= 31 |
| 3949 | is |
| 3950 | rlwinm rd,rs,32-n,n,31 (PPC32 p501) |
| 3951 | */ |
| 3952 | UInt n = srcR->Prh.Imm.imm16; |
| 3953 | vassert(!srcR->Prh.Imm.syned); |
| 3954 | vassert(n > 0 && n < 32); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3955 | p = mkFormM(p, 21, r_srcL, r_dst, 32-n, n, 31, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3956 | } else { |
| 3957 | /* srw (PPC32 p508) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3958 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 536, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3959 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3960 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3961 | if (immR) { |
| 3962 | /* rd = rs >>u n, 1 <= n <= 63 |
| 3963 | is |
| 3964 | rldicl rd,rs,64-n,n (PPC64 p558) |
| 3965 | */ |
| 3966 | UInt n = srcR->Prh.Imm.imm16; |
| 3967 | vassert(!srcR->Prh.Imm.syned); |
| 3968 | vassert(n > 0 && n < 64); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3969 | p = mkFormMD(p, 30, r_srcL, r_dst, 64-n, n, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3970 | } else { |
| 3971 | /* srd (PPC64 p574) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3972 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 539, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3973 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3974 | } |
| 3975 | break; |
| 3976 | |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3977 | case Pshft_SAR: |
| 3978 | if (sz32) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3979 | if (immR) { |
| 3980 | /* srawi (PPC32 p507) */ |
| 3981 | UInt n = srcR->Prh.Imm.imm16; |
| 3982 | vassert(!srcR->Prh.Imm.syned); |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 3983 | /* In 64-bit mode, we allow right shifts by zero bits |
| 3984 | as that is a handy way to sign extend the lower 32 |
| 3985 | bits into the upper 32 bits. */ |
| 3986 | if (mode64) |
| 3987 | vassert(n >= 0 && n < 32); |
| 3988 | else |
| 3989 | vassert(n > 0 && n < 32); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3990 | p = mkFormX(p, 31, r_srcL, r_dst, n, 824, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3991 | } else { |
| 3992 | /* sraw (PPC32 p506) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3993 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 792, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3994 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3995 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3996 | if (immR) { |
| 3997 | /* sradi (PPC64 p571) */ |
| 3998 | UInt n = srcR->Prh.Imm.imm16; |
| 3999 | vassert(!srcR->Prh.Imm.syned); |
| 4000 | vassert(n > 0 && n < 64); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4001 | p = mkFormXS(p, 31, r_srcL, r_dst, n, 413, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4002 | } else { |
| 4003 | /* srad (PPC32 p570) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4004 | p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 794, 0, endness_host); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4005 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4006 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4007 | break; |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 4008 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4009 | default: |
| 4010 | goto bad; |
| 4011 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4012 | goto done; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4013 | } |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 4014 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4015 | case Pin_AddSubC: { |
| 4016 | Bool isAdd = i->Pin.AddSubC.isAdd; |
| 4017 | Bool setC = i->Pin.AddSubC.setC; |
| 4018 | UInt r_srcL = iregNo(i->Pin.AddSubC.srcL, mode64); |
| 4019 | UInt r_srcR = iregNo(i->Pin.AddSubC.srcR, mode64); |
| 4020 | UInt r_dst = iregNo(i->Pin.AddSubC.dst, mode64); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 4021 | |
| 4022 | if (isAdd) { |
| 4023 | if (setC) /* addc (PPC32 p348) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4024 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 10, 0, endness_host); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 4025 | else /* adde (PPC32 p349) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4026 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 138, 0, endness_host); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 4027 | } else { |
| 4028 | /* subfX, with args the "wrong" way round */ |
| 4029 | if (setC) /* subfc (PPC32 p538) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4030 | p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 8, 0, endness_host); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 4031 | else /* subfe (PPC32 p539) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4032 | p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 136, 0, endness_host); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 4033 | } |
| 4034 | goto done; |
| 4035 | } |
| 4036 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4037 | case Pin_Cmp: { |
| 4038 | Bool syned = i->Pin.Cmp.syned; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4039 | Bool sz32 = i->Pin.Cmp.sz32; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4040 | UInt fld1 = i->Pin.Cmp.crfD << 2; |
| 4041 | UInt r_srcL = iregNo(i->Pin.Cmp.srcL, mode64); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 4042 | UInt r_srcR, imm_srcR; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4043 | PPCRH* srcR = i->Pin.Cmp.srcR; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4044 | |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4045 | if (!mode64) // cmp double word invalid for mode32 |
| 4046 | vassert(sz32); |
| 4047 | else if (!sz32) // mode64 && cmp64: set L=1 |
| 4048 | fld1 |= 1; |
| 4049 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4050 | switch (srcR->tag) { |
| 4051 | case Prh_Imm: |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4052 | vassert(syned == srcR->Prh.Imm.syned); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4053 | imm_srcR = srcR->Prh.Imm.imm16; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4054 | if (syned) { // cmpw/di (signed) (PPC32 p368) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4055 | vassert(imm_srcR != 0x8000); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4056 | p = mkFormD(p, 11, fld1, r_srcL, imm_srcR, endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4057 | } else { // cmplw/di (unsigned) (PPC32 p370) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4058 | p = mkFormD(p, 10, fld1, r_srcL, imm_srcR, endness_host); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4059 | } |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4060 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4061 | case Prh_Reg: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4062 | r_srcR = iregNo(srcR->Prh.Reg.reg, mode64); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4063 | if (syned) // cmpwi (signed) (PPC32 p367) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4064 | p = mkFormX(p, 31, fld1, r_srcL, r_srcR, 0, 0, endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4065 | else // cmplwi (unsigned) (PPC32 p379) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4066 | p = mkFormX(p, 31, fld1, r_srcL, r_srcR, 32, 0, endness_host); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4067 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4068 | default: |
| 4069 | goto bad; |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4070 | } |
| 4071 | goto done; |
| 4072 | } |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 4073 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4074 | case Pin_Unary: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4075 | UInt r_dst = iregNo(i->Pin.Unary.dst, mode64); |
| 4076 | UInt r_src = iregNo(i->Pin.Unary.src, mode64); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4077 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4078 | switch (i->Pin.Unary.op) { |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4079 | case Pun_NOT: // nor r_dst,r_src,r_src |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4080 | p = mkFormX(p, 31, r_src, r_dst, r_src, 124, 0, endness_host); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4081 | break; |
| 4082 | case Pun_NEG: // neg r_dst,r_src |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4083 | p = mkFormXO(p, 31, r_dst, r_src, 0, 0, 104, 0, endness_host); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4084 | break; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4085 | case Pun_CLZ32: // cntlzw r_dst, r_src |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4086 | p = mkFormX(p, 31, r_src, r_dst, 0, 26, 0, endness_host); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4087 | break; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4088 | case Pun_CLZ64: // cntlzd r_dst, r_src |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 4089 | vassert(mode64); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4090 | p = mkFormX(p, 31, r_src, r_dst, 0, 58, 0, endness_host); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4091 | break; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 4092 | case Pun_EXTSW: // extsw r_dst, r_src |
| 4093 | vassert(mode64); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4094 | p = mkFormX(p, 31, r_src, r_dst, 0, 986, 0, endness_host); |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 4095 | break; |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4096 | default: goto bad; |
| 4097 | } |
| 4098 | goto done; |
| 4099 | } |
| 4100 | |
| 4101 | case Pin_MulL: { |
| 4102 | Bool syned = i->Pin.MulL.syned; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4103 | Bool sz32 = i->Pin.MulL.sz32; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4104 | UInt r_dst = iregNo(i->Pin.MulL.dst, mode64); |
| 4105 | UInt r_srcL = iregNo(i->Pin.MulL.srcL, mode64); |
| 4106 | UInt r_srcR = iregNo(i->Pin.MulL.srcR, mode64); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4107 | |
| 4108 | if (!mode64) |
| 4109 | vassert(sz32); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4110 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4111 | if (i->Pin.MulL.hi) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4112 | // mul hi words, must consider sign |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4113 | if (sz32) { |
| 4114 | if (syned) // mulhw r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4115 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 75, 0, |
| 4116 | endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4117 | else // mulhwu r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4118 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 11, 0, |
| 4119 | endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4120 | } else { |
| 4121 | if (syned) // mulhd r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4122 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 73, 0, |
| 4123 | endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4124 | else // mulhdu r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4125 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 9, 0, endness_host); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4126 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4127 | } else { |
| 4128 | // mul low word, sign is irrelevant |
| 4129 | vassert(!i->Pin.MulL.syned); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4130 | if (sz32) // mullw r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4131 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 235, 0, endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4132 | else // mulld r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4133 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 233, 0, endness_host); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4134 | } |
| 4135 | goto done; |
| 4136 | } |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 4137 | |
cerion | fd0b87f | 2005-02-16 14:43:14 +0000 | [diff] [blame] | 4138 | case Pin_Div: { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4139 | Bool syned = i->Pin.Div.syned; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4140 | Bool sz32 = i->Pin.Div.sz32; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4141 | UInt r_dst = iregNo(i->Pin.Div.dst, mode64); |
| 4142 | UInt r_srcL = iregNo(i->Pin.Div.srcL, mode64); |
| 4143 | UInt r_srcR = iregNo(i->Pin.Div.srcR, mode64); |
cerion | fd0b87f | 2005-02-16 14:43:14 +0000 | [diff] [blame] | 4144 | |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4145 | if (!mode64) |
| 4146 | vassert(sz32); |
| 4147 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4148 | if (i->Pin.Div.extended) { |
| 4149 | if (sz32) { |
| 4150 | if (syned) |
| 4151 | // divwe r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4152 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 427, 0, |
| 4153 | endness_host); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4154 | else |
| 4155 | // divweu r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4156 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 395, 0, |
| 4157 | endness_host); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4158 | } else { |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 4159 | if (syned) |
| 4160 | // divde r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4161 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 425, 0, |
| 4162 | endness_host); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 4163 | else |
| 4164 | // divdeu r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4165 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 393, 0, |
| 4166 | endness_host); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4167 | } |
| 4168 | } else if (sz32) { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4169 | if (syned) // divw r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4170 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 491, 0, endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4171 | else // divwu r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4172 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 459, 0, endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4173 | } else { |
| 4174 | if (syned) // divd r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4175 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 489, 0, endness_host); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4176 | else // divdu r_dst,r_srcL,r_srcR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4177 | p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 457, 0, endness_host); |
cerion | fd0b87f | 2005-02-16 14:43:14 +0000 | [diff] [blame] | 4178 | } |
| 4179 | goto done; |
| 4180 | } |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 4181 | |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 4182 | case Pin_Call: { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 4183 | if (i->Pin.Call.cond.test != Pct_ALWAYS |
sewardj | 74142b8 | 2013-08-08 10:28:59 +0000 | [diff] [blame] | 4184 | && i->Pin.Call.rloc.pri != RLPri_None) { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 4185 | /* The call might not happen (it isn't unconditional) and it |
| 4186 | returns a result. In this case we will need to generate a |
| 4187 | control flow diamond to put 0x555..555 in the return |
| 4188 | register(s) in the case where the call doesn't happen. If |
| 4189 | this ever becomes necessary, maybe copy code from the ARM |
| 4190 | equivalent. Until that day, just give up. */ |
| 4191 | goto bad; |
| 4192 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4193 | PPCCondCode cond = i->Pin.Call.cond; |
| 4194 | UInt r_dst = 10; |
cerion | a56e9cc | 2005-02-16 18:08:25 +0000 | [diff] [blame] | 4195 | /* As per detailed comment for Pin_Call in |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4196 | getRegUsage_PPCInstr above, %r10 is used as an address temp */ |
cerion | a56e9cc | 2005-02-16 18:08:25 +0000 | [diff] [blame] | 4197 | |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 4198 | /* jump over the following insns if condition does not hold */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4199 | UChar* ptmp = NULL; |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 4200 | if (cond.test != Pct_ALWAYS) { |
cerion | 9762bbf | 2005-06-23 08:44:52 +0000 | [diff] [blame] | 4201 | /* jmp fwds if !condition */ |
| 4202 | /* don't know how many bytes to jump over yet... |
| 4203 | make space for a jump instruction and fill in later. */ |
| 4204 | ptmp = p; /* fill in this bit later */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4205 | p += 4; // p += 4 |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4206 | } |
| 4207 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4208 | /* load target to r_dst */ // p += 4|8|20 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4209 | p = mkLoadImm(p, r_dst, i->Pin.Call.target, mode64, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4210 | |
cerion | a56e9cc | 2005-02-16 18:08:25 +0000 | [diff] [blame] | 4211 | /* mtspr 9,r_dst => move r_dst to count register */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4212 | p = mkFormXFX(p, r_dst, 9, 467, endness_host); // p += 4 |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 4213 | |
cerion | 8c51ed4 | 2005-02-22 11:16:54 +0000 | [diff] [blame] | 4214 | /* bctrl => branch to count register (and save to lr) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4215 | p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1, endness_host); // p += 4 |
cerion | 9762bbf | 2005-06-23 08:44:52 +0000 | [diff] [blame] | 4216 | |
| 4217 | /* Fix up the conditional jump, if there was one. */ |
| 4218 | if (cond.test != Pct_ALWAYS) { |
| 4219 | Int delta = p - ptmp; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4220 | vassert(delta >= 16 && delta <= 32); |
cerion | 9762bbf | 2005-06-23 08:44:52 +0000 | [diff] [blame] | 4221 | /* bc !ct,cf,delta */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4222 | mkFormB(ptmp, invertCondTest(cond.test), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4223 | cond.flag, (delta>>2), 0, 0, endness_host); |
cerion | 9762bbf | 2005-06-23 08:44:52 +0000 | [diff] [blame] | 4224 | } |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 4225 | goto done; |
| 4226 | } |
| 4227 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4228 | case Pin_XDirect: { |
| 4229 | /* NB: what goes on here has to be very closely coordinated |
| 4230 | with the chainXDirect_PPC and unchainXDirect_PPC below. */ |
| 4231 | /* We're generating chain-me requests here, so we need to be |
| 4232 | sure this is actually allowed -- no-redir translations |
| 4233 | can't use chain-me's. Hence: */ |
| 4234 | vassert(disp_cp_chain_me_to_slowEP != NULL); |
| 4235 | vassert(disp_cp_chain_me_to_fastEP != NULL); |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 4236 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4237 | /* First off, if this is conditional, create a conditional jump |
| 4238 | over the rest of it. Or at least, leave a space for it that |
| 4239 | we will shortly fill in. */ |
| 4240 | UChar* ptmp = NULL; |
| 4241 | if (i->Pin.XDirect.cond.test != Pct_ALWAYS) { |
| 4242 | vassert(i->Pin.XDirect.cond.flag != Pcf_NONE); |
| 4243 | ptmp = p; |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 4244 | p += 4; |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 4245 | } else { |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4246 | vassert(i->Pin.XDirect.cond.flag == Pcf_NONE); |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 4247 | } |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4248 | |
| 4249 | /* Update the guest CIA. */ |
| 4250 | /* imm32/64 r30, dstGA */ |
| 4251 | if (!mode64) vassert(0 == (((ULong)i->Pin.XDirect.dstGA) >> 32)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4252 | p = mkLoadImm(p, /*r*/30, (ULong)i->Pin.XDirect.dstGA, mode64, |
| 4253 | endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4254 | /* stw/std r30, amCIA */ |
| 4255 | p = do_load_or_store_machine_word( |
| 4256 | p, False/*!isLoad*/, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4257 | /*r*/30, i->Pin.XDirect.amCIA, mode64, endness_host |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4258 | ); |
| 4259 | |
| 4260 | /* --- FIRST PATCHABLE BYTE follows --- */ |
| 4261 | /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're calling |
| 4262 | to) backs up the return address, so as to find the address of |
| 4263 | the first patchable byte. So: don't change the number of |
| 4264 | instructions (32-bit: 4, 64-bit: 7) below. */ |
| 4265 | /* imm32/64-fixed r30, VG_(disp_cp_chain_me_to_{slowEP,fastEP} */ |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 4266 | const void* disp_cp_chain_me |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4267 | = i->Pin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP |
| 4268 | : disp_cp_chain_me_to_slowEP; |
| 4269 | p = mkLoadImm_EXACTLY2or5( |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4270 | p, /*r*/30, Ptr_to_ULong(disp_cp_chain_me), mode64, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4271 | /* mtctr r30 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4272 | p = mkFormXFX(p, /*r*/30, 9, 467, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4273 | /* bctrl */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4274 | p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4275 | /* --- END of PATCHABLE BYTES --- */ |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 4276 | |
| 4277 | /* Fix up the conditional jump, if there was one. */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4278 | if (i->Pin.XDirect.cond.test != Pct_ALWAYS) { |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 4279 | Int delta = p - ptmp; |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 4280 | vassert(delta >= 16 && delta <= 64 && 0 == (delta & 3)); |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 4281 | /* bc !ct,cf,delta */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4282 | mkFormB(ptmp, invertCondTest(i->Pin.XDirect.cond.test), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4283 | i->Pin.XDirect.cond.flag, (delta>>2), 0, 0, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4284 | } |
| 4285 | goto done; |
| 4286 | } |
| 4287 | |
| 4288 | case Pin_XIndir: { |
| 4289 | /* We're generating transfers that could lead indirectly to a |
| 4290 | chain-me, so we need to be sure this is actually allowed -- |
| 4291 | no-redir translations are not allowed to reach normal |
| 4292 | translations without going through the scheduler. That means |
| 4293 | no XDirects or XIndirs out from no-redir translations. |
| 4294 | Hence: */ |
| 4295 | vassert(disp_cp_xindir != NULL); |
| 4296 | |
| 4297 | /* First off, if this is conditional, create a conditional jump |
| 4298 | over the rest of it. Or at least, leave a space for it that |
| 4299 | we will shortly fill in. */ |
| 4300 | UChar* ptmp = NULL; |
| 4301 | if (i->Pin.XIndir.cond.test != Pct_ALWAYS) { |
| 4302 | vassert(i->Pin.XIndir.cond.flag != Pcf_NONE); |
| 4303 | ptmp = p; |
| 4304 | p += 4; |
| 4305 | } else { |
| 4306 | vassert(i->Pin.XIndir.cond.flag == Pcf_NONE); |
| 4307 | } |
| 4308 | |
| 4309 | /* Update the guest CIA. */ |
| 4310 | /* stw/std r-dstGA, amCIA */ |
| 4311 | p = do_load_or_store_machine_word( |
| 4312 | p, False/*!isLoad*/, |
| 4313 | iregNo(i->Pin.XIndir.dstGA, mode64), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4314 | i->Pin.XIndir.amCIA, mode64, endness_host |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4315 | ); |
| 4316 | |
| 4317 | /* imm32/64 r30, VG_(disp_cp_xindir) */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4318 | p = mkLoadImm(p, /*r*/30, (ULong)Ptr_to_ULong(disp_cp_xindir), mode64, |
| 4319 | endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4320 | /* mtctr r30 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4321 | p = mkFormXFX(p, /*r*/30, 9, 467, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4322 | /* bctr */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4323 | p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4324 | |
| 4325 | /* Fix up the conditional jump, if there was one. */ |
| 4326 | if (i->Pin.XIndir.cond.test != Pct_ALWAYS) { |
| 4327 | Int delta = p - ptmp; |
| 4328 | vassert(delta >= 16 && delta <= 32 && 0 == (delta & 3)); |
| 4329 | /* bc !ct,cf,delta */ |
| 4330 | mkFormB(ptmp, invertCondTest(i->Pin.XIndir.cond.test), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4331 | i->Pin.XIndir.cond.flag, (delta>>2), 0, 0, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4332 | } |
| 4333 | goto done; |
| 4334 | } |
| 4335 | |
| 4336 | case Pin_XAssisted: { |
| 4337 | /* First off, if this is conditional, create a conditional jump |
| 4338 | over the rest of it. Or at least, leave a space for it that |
| 4339 | we will shortly fill in. */ |
| 4340 | UChar* ptmp = NULL; |
| 4341 | if (i->Pin.XAssisted.cond.test != Pct_ALWAYS) { |
| 4342 | vassert(i->Pin.XAssisted.cond.flag != Pcf_NONE); |
| 4343 | ptmp = p; |
| 4344 | p += 4; |
| 4345 | } else { |
| 4346 | vassert(i->Pin.XAssisted.cond.flag == Pcf_NONE); |
| 4347 | } |
| 4348 | |
| 4349 | /* Update the guest CIA. */ |
| 4350 | /* stw/std r-dstGA, amCIA */ |
| 4351 | p = do_load_or_store_machine_word( |
| 4352 | p, False/*!isLoad*/, |
| 4353 | iregNo(i->Pin.XIndir.dstGA, mode64), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4354 | i->Pin.XIndir.amCIA, mode64, endness_host |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4355 | ); |
| 4356 | |
| 4357 | /* imm32/64 r31, $magic_number */ |
| 4358 | UInt trcval = 0; |
| 4359 | switch (i->Pin.XAssisted.jk) { |
| 4360 | case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break; |
| 4361 | case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break; |
| 4362 | //case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break; |
| 4363 | //case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break; |
| 4364 | case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 4365 | case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4366 | //case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; |
| 4367 | case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 4368 | case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4369 | case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; |
| 4370 | case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; |
| 4371 | //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; |
| 4372 | case Ijk_SigBUS: trcval = VEX_TRC_JMP_SIGBUS; break; |
| 4373 | case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break; |
| 4374 | /* We don't expect to see the following being assisted. */ |
| 4375 | //case Ijk_Ret: |
| 4376 | //case Ijk_Call: |
| 4377 | /* fallthrough */ |
| 4378 | default: |
| 4379 | ppIRJumpKind(i->Pin.XAssisted.jk); |
| 4380 | vpanic("emit_ARMInstr.Pin_XAssisted: unexpected jump kind"); |
| 4381 | } |
| 4382 | vassert(trcval != 0); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4383 | p = mkLoadImm(p, /*r*/31, trcval, mode64, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4384 | |
| 4385 | /* imm32/64 r30, VG_(disp_cp_xassisted) */ |
| 4386 | p = mkLoadImm(p, /*r*/30, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4387 | (ULong)Ptr_to_ULong(disp_cp_xassisted), mode64, |
| 4388 | endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4389 | /* mtctr r30 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4390 | p = mkFormXFX(p, /*r*/30, 9, 467, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4391 | /* bctr */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4392 | p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4393 | |
| 4394 | /* Fix up the conditional jump, if there was one. */ |
| 4395 | if (i->Pin.XAssisted.cond.test != Pct_ALWAYS) { |
| 4396 | Int delta = p - ptmp; |
| 4397 | vassert(delta >= 16 && delta <= 32 && 0 == (delta & 3)); |
| 4398 | /* bc !ct,cf,delta */ |
| 4399 | mkFormB(ptmp, invertCondTest(i->Pin.XAssisted.cond.test), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4400 | i->Pin.XAssisted.cond.flag, (delta>>2), 0, 0, endness_host); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 4401 | } |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 4402 | goto done; |
| 4403 | } |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 4404 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4405 | case Pin_CMov: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4406 | UInt r_dst, r_src; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4407 | ULong imm_src; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4408 | PPCCondCode cond; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4409 | vassert(i->Pin.CMov.cond.test != Pct_ALWAYS); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 4410 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4411 | r_dst = iregNo(i->Pin.CMov.dst, mode64); |
| 4412 | cond = i->Pin.CMov.cond; |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4413 | |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 4414 | /* branch (if cond fails) over move instrs */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 4415 | UChar* ptmp = NULL; |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 4416 | if (cond.test != Pct_ALWAYS) { |
| 4417 | /* don't know how many bytes to jump over yet... |
| 4418 | make space for a jump instruction and fill in later. */ |
| 4419 | ptmp = p; /* fill in this bit later */ |
| 4420 | p += 4; |
| 4421 | } |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4422 | |
| 4423 | // cond true: move src => dst |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4424 | switch (i->Pin.CMov.src->tag) { |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4425 | case Pri_Imm: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4426 | imm_src = i->Pin.CMov.src->Pri.Imm; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4427 | p = mkLoadImm(p, r_dst, imm_src, mode64, endness_host); // p += 4|8|20 |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4428 | break; |
| 4429 | case Pri_Reg: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4430 | r_src = iregNo(i->Pin.CMov.src->Pri.Reg, mode64); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4431 | p = mkMoveReg(p, r_dst, r_src, endness_host); // p += 4 |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4432 | break; |
| 4433 | default: goto bad; |
| 4434 | } |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 4435 | |
| 4436 | /* Fix up the conditional jump, if there was one. */ |
| 4437 | if (cond.test != Pct_ALWAYS) { |
| 4438 | Int delta = p - ptmp; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4439 | vassert(delta >= 8 && delta <= 24); |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 4440 | /* bc !ct,cf,delta */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4441 | mkFormB(ptmp, invertCondTest(cond.test), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4442 | cond.flag, (delta>>2), 0, 0, endness_host); |
cerion | e97e106 | 2005-02-21 15:09:19 +0000 | [diff] [blame] | 4443 | } |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4444 | goto done; |
| 4445 | } |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 4446 | |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 4447 | case Pin_Load: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4448 | PPCAMode* am_addr = i->Pin.Load.src; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4449 | UInt r_dst = iregNo(i->Pin.Load.dst, mode64); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 4450 | UInt opc1, opc2, sz = i->Pin.Load.sz; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4451 | switch (am_addr->tag) { |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4452 | case Pam_IR: |
sewardj | 34085e3 | 2007-03-09 18:07:00 +0000 | [diff] [blame] | 4453 | if (mode64 && (sz == 4 || sz == 8)) { |
| 4454 | /* should be guaranteed to us by iselWordExpr_AMode */ |
| 4455 | vassert(0 == (am_addr->Pam.IR.index & 3)); |
| 4456 | } |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4457 | switch(sz) { |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 4458 | case 1: opc1 = 34; break; |
| 4459 | case 2: opc1 = 40; break; |
| 4460 | case 4: opc1 = 32; break; |
| 4461 | case 8: opc1 = 58; vassert(mode64); break; |
| 4462 | default: goto bad; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4463 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4464 | p = doAMode_IR(p, opc1, r_dst, am_addr, mode64, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4465 | goto done; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4466 | case Pam_RR: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4467 | switch(sz) { |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 4468 | case 1: opc2 = 87; break; |
| 4469 | case 2: opc2 = 279; break; |
| 4470 | case 4: opc2 = 23; break; |
| 4471 | case 8: opc2 = 21; vassert(mode64); break; |
| 4472 | default: goto bad; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4473 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4474 | p = doAMode_RR(p, 31, opc2, r_dst, am_addr, mode64, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4475 | goto done; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4476 | default: |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4477 | goto bad; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4478 | } |
| 4479 | } |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 4480 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4481 | case Pin_LoadL: { |
| 4482 | if (i->Pin.LoadL.sz == 4) { |
| 4483 | p = mkFormX(p, 31, iregNo(i->Pin.LoadL.dst, mode64), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4484 | 0, iregNo(i->Pin.LoadL.src, mode64), 20, 0, endness_host); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4485 | goto done; |
| 4486 | } |
| 4487 | if (i->Pin.LoadL.sz == 8 && mode64) { |
| 4488 | p = mkFormX(p, 31, iregNo(i->Pin.LoadL.dst, mode64), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4489 | 0, iregNo(i->Pin.LoadL.src, mode64), 84, 0, endness_host); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4490 | goto done; |
| 4491 | } |
| 4492 | goto bad; |
| 4493 | } |
| 4494 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4495 | case Pin_Set: { |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4496 | /* Make the destination register be 1 or 0, depending on whether |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 4497 | the relevant condition holds. */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4498 | UInt r_dst = iregNo(i->Pin.Set.dst, mode64); |
| 4499 | PPCCondCode cond = i->Pin.Set.cond; |
| 4500 | UInt rot_imm, r_tmp; |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4501 | |
| 4502 | if (cond.test == Pct_ALWAYS) { |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 4503 | // Just load 1 to dst => li dst,1 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4504 | p = mkFormD(p, 14, r_dst, 0, 1, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4505 | } else { |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 4506 | vassert(cond.flag != Pcf_NONE); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 4507 | rot_imm = 1 + cond.flag; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4508 | r_tmp = 0; // Not set in getAllocable, so no need to declare. |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4509 | |
| 4510 | // r_tmp = CR => mfcr r_tmp |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4511 | p = mkFormX(p, 31, r_tmp, 0, 0, 19, 0, endness_host); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4512 | |
| 4513 | // r_dst = flag (rotate left and mask) |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 4514 | // => rlwinm r_dst,r_tmp,rot_imm,31,31 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4515 | p = mkFormM(p, 21, r_tmp, r_dst, rot_imm, 31, 31, 0, endness_host); |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4516 | |
| 4517 | if (cond.test == Pct_FALSE) { |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 4518 | // flip bit => xori r_dst,r_dst,1 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4519 | p = mkFormD(p, 26, r_dst, r_dst, 1, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4520 | } |
| 4521 | } |
| 4522 | goto done; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4523 | } |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 4524 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4525 | case Pin_MfCR: |
| 4526 | // mfcr dst |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4527 | p = mkFormX(p, 31, iregNo(i->Pin.MfCR.dst, mode64), 0, 0, 19, 0, |
| 4528 | endness_host); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4529 | goto done; |
| 4530 | |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4531 | case Pin_MFence: { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4532 | p = mkFormX(p, 31, 0, 0, 0, 598, 0, endness_host); // sync, PPC32 p616 |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4533 | // CAB: Should this be isync? |
| 4534 | // p = mkFormXL(p, 19, 0, 0, 0, 150, 0); // isync, PPC32 p467 |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 4535 | goto done; |
| 4536 | } |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 4537 | |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4538 | case Pin_Store: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4539 | PPCAMode* am_addr = i->Pin.Store.dst; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4540 | UInt r_src = iregNo(i->Pin.Store.src, mode64); |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 4541 | UInt opc1, opc2, sz = i->Pin.Store.sz; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4542 | switch (i->Pin.Store.dst->tag) { |
| 4543 | case Pam_IR: |
sewardj | 34085e3 | 2007-03-09 18:07:00 +0000 | [diff] [blame] | 4544 | if (mode64 && (sz == 4 || sz == 8)) { |
| 4545 | /* should be guaranteed to us by iselWordExpr_AMode */ |
| 4546 | vassert(0 == (am_addr->Pam.IR.index & 3)); |
| 4547 | } |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4548 | switch(sz) { |
| 4549 | case 1: opc1 = 38; break; |
| 4550 | case 2: opc1 = 44; break; |
| 4551 | case 4: opc1 = 36; break; |
| 4552 | case 8: vassert(mode64); |
| 4553 | opc1 = 62; break; |
| 4554 | default: |
| 4555 | goto bad; |
| 4556 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4557 | p = doAMode_IR(p, opc1, r_src, am_addr, mode64, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4558 | goto done; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4559 | case Pam_RR: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4560 | switch(sz) { |
| 4561 | case 1: opc2 = 215; break; |
| 4562 | case 2: opc2 = 407; break; |
| 4563 | case 4: opc2 = 151; break; |
| 4564 | case 8: vassert(mode64); |
| 4565 | opc2 = 149; break; |
| 4566 | default: |
| 4567 | goto bad; |
| 4568 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4569 | p = doAMode_RR(p, 31, opc2, r_src, am_addr, mode64, endness_host); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4570 | goto done; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4571 | default: |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 4572 | goto bad; |
cerion | d5e3838 | 2005-02-11 13:38:15 +0000 | [diff] [blame] | 4573 | } |
| 4574 | goto done; |
| 4575 | } |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 4576 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4577 | case Pin_StoreC: { |
| 4578 | if (i->Pin.StoreC.sz == 4) { |
| 4579 | p = mkFormX(p, 31, iregNo(i->Pin.StoreC.src, mode64), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4580 | 0, iregNo(i->Pin.StoreC.dst, mode64), 150, 1, endness_host); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4581 | goto done; |
| 4582 | } |
| 4583 | if (i->Pin.StoreC.sz == 8 && mode64) { |
| 4584 | p = mkFormX(p, 31, iregNo(i->Pin.StoreC.src, mode64), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4585 | 0, iregNo(i->Pin.StoreC.dst, mode64), 214, 1, endness_host); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4586 | goto done; |
| 4587 | } |
| 4588 | goto bad; |
| 4589 | } |
| 4590 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4591 | case Pin_FpUnary: { |
| 4592 | UInt fr_dst = fregNo(i->Pin.FpUnary.dst); |
| 4593 | UInt fr_src = fregNo(i->Pin.FpUnary.src); |
| 4594 | switch (i->Pin.FpUnary.op) { |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 4595 | case Pfp_RSQRTE: // frsqrtre, PPC32 p424 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4596 | p = mkFormA( p, 63, fr_dst, 0, fr_src, 0, 26, 0, endness_host ); |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 4597 | break; |
| 4598 | case Pfp_RES: // fres, PPC32 p421 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4599 | p = mkFormA( p, 59, fr_dst, 0, fr_src, 0, 24, 0, endness_host ); |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 4600 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4601 | case Pfp_SQRT: // fsqrt, PPC32 p427 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4602 | p = mkFormA( p, 63, fr_dst, 0, fr_src, 0, 22, 0, endness_host ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4603 | break; |
| 4604 | case Pfp_ABS: // fabs, PPC32 p399 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4605 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 264, 0, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4606 | break; |
| 4607 | case Pfp_NEG: // fneg, PPC32 p416 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4608 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 40, 0, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4609 | break; |
| 4610 | case Pfp_MOV: // fmr, PPC32 p410 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4611 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 72, 0, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4612 | break; |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 4613 | case Pfp_FRIM: // frim, PPC ISA 2.05 p137 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4614 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 488, 0, endness_host); |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 4615 | break; |
| 4616 | case Pfp_FRIP: // frip, PPC ISA 2.05 p137 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4617 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 456, 0, endness_host); |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 4618 | break; |
| 4619 | case Pfp_FRIN: // frin, PPC ISA 2.05 p137 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4620 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 392, 0, endness_host); |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 4621 | break; |
| 4622 | case Pfp_FRIZ: // friz, PPC ISA 2.05 p137 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4623 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 424, 0, endness_host); |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 4624 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4625 | default: |
| 4626 | goto bad; |
| 4627 | } |
| 4628 | goto done; |
| 4629 | } |
| 4630 | |
| 4631 | case Pin_FpBinary: { |
| 4632 | UInt fr_dst = fregNo(i->Pin.FpBinary.dst); |
| 4633 | UInt fr_srcL = fregNo(i->Pin.FpBinary.srcL); |
| 4634 | UInt fr_srcR = fregNo(i->Pin.FpBinary.srcR); |
| 4635 | switch (i->Pin.FpBinary.op) { |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4636 | case Pfp_ADDD: // fadd, PPC32 p400 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4637 | p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 21, 0, endness_host ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4638 | break; |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4639 | case Pfp_ADDS: // fadds, PPC32 p401 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4640 | p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 21, 0, endness_host ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4641 | break; |
| 4642 | case Pfp_SUBD: // fsub, PPC32 p429 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4643 | p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 20, 0, endness_host ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4644 | break; |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4645 | case Pfp_SUBS: // fsubs, PPC32 p430 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4646 | p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 20, 0, endness_host ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4647 | break; |
| 4648 | case Pfp_MULD: // fmul, PPC32 p413 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4649 | p = mkFormA( p, 63, fr_dst, fr_srcL, 0, fr_srcR, 25, 0, endness_host ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4650 | break; |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4651 | case Pfp_MULS: // fmuls, PPC32 p414 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4652 | p = mkFormA( p, 59, fr_dst, fr_srcL, 0, fr_srcR, 25, 0, endness_host ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4653 | break; |
| 4654 | case Pfp_DIVD: // fdiv, PPC32 p406 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4655 | p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 18, 0, endness_host ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4656 | break; |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4657 | case Pfp_DIVS: // fdivs, PPC32 p407 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4658 | p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 18, 0, endness_host ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4659 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4660 | default: |
| 4661 | goto bad; |
| 4662 | } |
| 4663 | goto done; |
| 4664 | } |
| 4665 | |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 4666 | case Pin_FpMulAcc: { |
| 4667 | UInt fr_dst = fregNo(i->Pin.FpMulAcc.dst); |
| 4668 | UInt fr_srcML = fregNo(i->Pin.FpMulAcc.srcML); |
| 4669 | UInt fr_srcMR = fregNo(i->Pin.FpMulAcc.srcMR); |
| 4670 | UInt fr_srcAcc = fregNo(i->Pin.FpMulAcc.srcAcc); |
| 4671 | switch (i->Pin.FpMulAcc.op) { |
| 4672 | case Pfp_MADDD: // fmadd, PPC32 p408 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4673 | p = mkFormA( p, 63, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 29, 0, |
| 4674 | endness_host ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 4675 | break; |
| 4676 | case Pfp_MADDS: // fmadds, PPC32 p409 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4677 | p = mkFormA( p, 59, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 29, 0, |
| 4678 | endness_host ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 4679 | break; |
| 4680 | case Pfp_MSUBD: // fmsub, PPC32 p411 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4681 | p = mkFormA( p, 63, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 28, 0, |
| 4682 | endness_host ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 4683 | break; |
| 4684 | case Pfp_MSUBS: // fmsubs, PPC32 p412 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4685 | p = mkFormA( p, 59, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 28, 0, |
| 4686 | endness_host ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 4687 | break; |
| 4688 | default: |
| 4689 | goto bad; |
| 4690 | } |
| 4691 | goto done; |
| 4692 | } |
| 4693 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4694 | case Pin_FpLdSt: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4695 | PPCAMode* am_addr = i->Pin.FpLdSt.addr; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4696 | UInt f_reg = fregNo(i->Pin.FpLdSt.reg); |
| 4697 | Bool idxd = toBool(i->Pin.FpLdSt.addr->tag == Pam_RR); |
| 4698 | UChar sz = i->Pin.FpLdSt.sz; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4699 | UInt opc; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4700 | vassert(sz == 4 || sz == 8); |
| 4701 | |
| 4702 | if (i->Pin.FpLdSt.isLoad) { // Load from memory |
| 4703 | if (idxd) { // lf[s|d]x, PPC32 p444|440 |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4704 | opc = (sz == 4) ? 535 : 599; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4705 | p = doAMode_RR(p, 31, opc, f_reg, am_addr, mode64, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4706 | } else { // lf[s|d], PPC32 p441|437 |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4707 | opc = (sz == 4) ? 48 : 50; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4708 | p = doAMode_IR(p, opc, f_reg, am_addr, mode64, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4709 | } |
| 4710 | } else { // Store to memory |
| 4711 | if (idxd) { // stf[s|d]x, PPC32 p521|516 |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4712 | opc = (sz == 4) ? 663 : 727; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4713 | p = doAMode_RR(p, 31, opc, f_reg, am_addr, mode64, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4714 | } else { // stf[s|d], PPC32 p518|513 |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4715 | opc = (sz == 4) ? 52 : 54; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4716 | p = doAMode_IR(p, opc, f_reg, am_addr, mode64, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4717 | } |
| 4718 | } |
| 4719 | goto done; |
| 4720 | } |
| 4721 | |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 4722 | case Pin_FpSTFIW: { |
| 4723 | UInt ir_addr = iregNo(i->Pin.FpSTFIW.addr, mode64); |
| 4724 | UInt fr_data = fregNo(i->Pin.FpSTFIW.data); |
| 4725 | // stfiwx (store fp64[lo32] as int32), PPC32 p517 |
| 4726 | // Use rA==0, so that EA == rB == ir_addr |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4727 | p = mkFormX(p, 31, fr_data, 0/*rA=0*/, ir_addr, 983, 0, endness_host); |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 4728 | goto done; |
| 4729 | } |
| 4730 | |
| 4731 | case Pin_FpRSP: { |
| 4732 | UInt fr_dst = fregNo(i->Pin.FpRSP.dst); |
| 4733 | UInt fr_src = fregNo(i->Pin.FpRSP.src); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4734 | // frsp, PPC32 p423 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4735 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 12, 0, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4736 | goto done; |
| 4737 | } |
| 4738 | |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 4739 | case Pin_FpCftI: { |
| 4740 | UInt fr_dst = fregNo(i->Pin.FpCftI.dst); |
| 4741 | UInt fr_src = fregNo(i->Pin.FpCftI.src); |
| 4742 | if (i->Pin.FpCftI.fromI == False && i->Pin.FpCftI.int32 == True) { |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4743 | if (i->Pin.FpCftI.syned == True) { |
| 4744 | // fctiw (conv f64 to i32), PPC32 p404 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4745 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 14, 0, endness_host); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4746 | goto done; |
| 4747 | } else { |
| 4748 | // fctiwu (conv f64 to u32) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4749 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 142, 0, endness_host); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4750 | goto done; |
| 4751 | } |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 4752 | } |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 4753 | if (i->Pin.FpCftI.fromI == False && i->Pin.FpCftI.int32 == False) { |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4754 | if (i->Pin.FpCftI.syned == True) { |
| 4755 | // fctid (conv f64 to i64), PPC64 p437 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4756 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 814, 0, endness_host); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4757 | goto done; |
| 4758 | } else { |
| 4759 | // fctidu (conv f64 to u64) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4760 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 942, 0, endness_host); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4761 | goto done; |
| 4762 | } |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 4763 | } |
| 4764 | if (i->Pin.FpCftI.fromI == True && i->Pin.FpCftI.int32 == False) { |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 4765 | if (i->Pin.FpCftI.syned == True) { |
| 4766 | // fcfid (conv i64 to f64), PPC64 p434 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4767 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 846, 0, endness_host); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 4768 | goto done; |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 4769 | } else if (i->Pin.FpCftI.flt64 == True) { |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 4770 | // fcfidu (conv u64 to f64) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4771 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 974, 0, endness_host); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 4772 | goto done; |
| 4773 | } else { |
| 4774 | // fcfidus (conv u64 to f32) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4775 | p = mkFormX(p, 59, fr_dst, 0, fr_src, 974, 0, endness_host); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 4776 | goto done; |
| 4777 | } |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 4778 | } |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 4779 | goto bad; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4780 | } |
| 4781 | |
| 4782 | case Pin_FpCMov: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4783 | UInt fr_dst = fregNo(i->Pin.FpCMov.dst); |
| 4784 | UInt fr_src = fregNo(i->Pin.FpCMov.src); |
| 4785 | PPCCondCode cc = i->Pin.FpCMov.cond; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4786 | |
| 4787 | if (fr_dst == fr_src) goto done; |
| 4788 | |
| 4789 | vassert(cc.test != Pct_ALWAYS); |
| 4790 | |
| 4791 | /* jmp fwds if !condition */ |
| 4792 | if (cc.test != Pct_ALWAYS) { |
| 4793 | /* bc !ct,cf,n_bytes>>2 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4794 | p = mkFormB(p, invertCondTest(cc.test), cc.flag, 8>>2, 0, 0, |
| 4795 | endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4796 | } |
| 4797 | |
| 4798 | // fmr, PPC32 p410 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4799 | p = mkFormX(p, 63, fr_dst, 0, fr_src, 72, 0, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4800 | goto done; |
| 4801 | } |
| 4802 | |
| 4803 | case Pin_FpLdFPSCR: { |
| 4804 | UInt fr_src = fregNo(i->Pin.FpLdFPSCR.src); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4805 | p = mkFormXFL(p, 0xFF, fr_src, i->Pin.FpLdFPSCR.dfp_rm, endness_host); // mtfsf, PPC32 p480 |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4806 | goto done; |
| 4807 | } |
| 4808 | |
| 4809 | case Pin_FpCmp: { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4810 | UChar crfD = 1; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4811 | UInt r_dst = iregNo(i->Pin.FpCmp.dst, mode64); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4812 | UInt fr_srcL = fregNo(i->Pin.FpCmp.srcL); |
| 4813 | UInt fr_srcR = fregNo(i->Pin.FpCmp.srcR); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4814 | vassert(crfD < 8); |
| 4815 | // fcmpo, PPC32 p402 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4816 | p = mkFormX(p, 63, crfD<<2, fr_srcL, fr_srcR, 32, 0, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4817 | |
| 4818 | // mfcr (mv CR to r_dst), PPC32 p467 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4819 | p = mkFormX(p, 31, r_dst, 0, 0, 19, 0, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4820 | |
| 4821 | // rlwinm r_dst,r_dst,8,28,31, PPC32 p501 |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4822 | // => rotate field 1 to bottomw of word, masking out upper 28 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4823 | p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0, endness_host); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4824 | goto done; |
| 4825 | } |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 4826 | |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 4827 | case Pin_RdWrLR: { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4828 | UInt reg = iregNo(i->Pin.RdWrLR.gpr, mode64); |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 4829 | /* wrLR==True ? mtlr r4 : mflr r4 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4830 | p = mkFormXFX(p, reg, 8, (i->Pin.RdWrLR.wrLR==True) ? 467 : 339, |
| 4831 | endness_host); |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 4832 | goto done; |
| 4833 | } |
| 4834 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4835 | |
| 4836 | /* AltiVec */ |
| 4837 | case Pin_AvLdSt: { |
| 4838 | UInt opc2, v_reg, r_idx, r_base; |
| 4839 | UChar sz = i->Pin.AvLdSt.sz; |
| 4840 | Bool idxd = toBool(i->Pin.AvLdSt.addr->tag == Pam_RR); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 4841 | vassert(sz == 1 || sz == 2 || sz == 4 || sz == 16); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4842 | |
| 4843 | v_reg = vregNo(i->Pin.AvLdSt.reg); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4844 | r_base = iregNo(i->Pin.AvLdSt.addr->Pam.RR.base, mode64); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4845 | |
| 4846 | // Only have AltiVec AMode_RR: kludge AMode_IR |
| 4847 | if (!idxd) { |
| 4848 | r_idx = 30; // XXX: Using r30 as temp |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4849 | p = mkLoadImm(p, r_idx, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4850 | i->Pin.AvLdSt.addr->Pam.IR.index, mode64, endness_host); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4851 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4852 | r_idx = iregNo(i->Pin.AvLdSt.addr->Pam.RR.index, mode64); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4853 | } |
| 4854 | |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 4855 | if (i->Pin.FpLdSt.isLoad) { // Load from memory (1,2,4,16) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4856 | opc2 = (sz==1) ? 7 : (sz==2) ? 39 : (sz==4) ? 71 : 103; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4857 | p = mkFormX(p, 31, v_reg, r_idx, r_base, opc2, 0, endness_host); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 4858 | } else { // Store to memory (1,2,4,16) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4859 | opc2 = (sz==1) ? 135 : (sz==2) ? 167 : (sz==4) ? 199 : 231; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4860 | p = mkFormX(p, 31, v_reg, r_idx, r_base, opc2, 0, endness_host); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4861 | } |
| 4862 | goto done; |
| 4863 | } |
| 4864 | |
| 4865 | case Pin_AvUnary: { |
| 4866 | UInt v_dst = vregNo(i->Pin.AvUnary.dst); |
| 4867 | UInt v_src = vregNo(i->Pin.AvUnary.src); |
| 4868 | UInt opc2; |
| 4869 | switch (i->Pin.AvUnary.op) { |
| 4870 | case Pav_MOV: opc2 = 1156; break; // vor vD,vS,vS |
| 4871 | case Pav_NOT: opc2 = 1284; break; // vnor vD,vS,vS |
| 4872 | case Pav_UNPCKH8S: opc2 = 526; break; // vupkhsb |
| 4873 | case Pav_UNPCKH16S: opc2 = 590; break; // vupkhsh |
| 4874 | case Pav_UNPCKL8S: opc2 = 654; break; // vupklsb |
| 4875 | case Pav_UNPCKL16S: opc2 = 718; break; // vupklsh |
| 4876 | case Pav_UNPCKHPIX: opc2 = 846; break; // vupkhpx |
| 4877 | case Pav_UNPCKLPIX: opc2 = 974; break; // vupklpx |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 4878 | |
| 4879 | case Pav_ZEROCNTBYTE: opc2 = 1794; break; // vclzb |
| 4880 | case Pav_ZEROCNTHALF: opc2 = 1858; break; // vclzh |
| 4881 | case Pav_ZEROCNTWORD: opc2 = 1922; break; // vclzw |
| 4882 | case Pav_ZEROCNTDBL: opc2 = 1986; break; // vclzd |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 4883 | case Pav_BITMTXXPOSE: opc2 = 1292; break; // vgbbd |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4884 | default: |
| 4885 | goto bad; |
| 4886 | } |
| 4887 | switch (i->Pin.AvUnary.op) { |
| 4888 | case Pav_MOV: |
| 4889 | case Pav_NOT: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4890 | p = mkFormVX( p, 4, v_dst, v_src, v_src, opc2, endness_host ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4891 | break; |
| 4892 | default: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4893 | p = mkFormVX( p, 4, v_dst, 0, v_src, opc2, endness_host ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 4894 | break; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4895 | } |
| 4896 | goto done; |
| 4897 | } |
| 4898 | |
| 4899 | case Pin_AvBinary: { |
| 4900 | UInt v_dst = vregNo(i->Pin.AvBinary.dst); |
| 4901 | UInt v_srcL = vregNo(i->Pin.AvBinary.srcL); |
| 4902 | UInt v_srcR = vregNo(i->Pin.AvBinary.srcR); |
| 4903 | UInt opc2; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 4904 | if (i->Pin.AvBinary.op == Pav_SHL) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4905 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1036, endness_host ); // vslo |
| 4906 | p = mkFormVX( p, 4, v_dst, v_dst, v_srcR, 452, endness_host ); // vsl |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 4907 | goto done; |
| 4908 | } |
| 4909 | if (i->Pin.AvBinary.op == Pav_SHR) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4910 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1100, endness_host ); // vsro |
| 4911 | p = mkFormVX( p, 4, v_dst, v_dst, v_srcR, 708, endness_host ); // vsr |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 4912 | goto done; |
| 4913 | } |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4914 | switch (i->Pin.AvBinary.op) { |
| 4915 | /* Bitwise */ |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 4916 | case Pav_AND: opc2 = 1028; break; // vand |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4917 | case Pav_OR: opc2 = 1156; break; // vor |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 4918 | case Pav_XOR: opc2 = 1220; break; // vxor |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4919 | default: |
| 4920 | goto bad; |
| 4921 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4922 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 4923 | goto done; |
| 4924 | } |
| 4925 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4926 | case Pin_AvBin8x16: { |
| 4927 | UInt v_dst = vregNo(i->Pin.AvBin8x16.dst); |
| 4928 | UInt v_srcL = vregNo(i->Pin.AvBin8x16.srcL); |
| 4929 | UInt v_srcR = vregNo(i->Pin.AvBin8x16.srcR); |
| 4930 | UInt opc2; |
| 4931 | switch (i->Pin.AvBin8x16.op) { |
| 4932 | |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 4933 | case Pav_ADDU: opc2 = 0; break; // vaddubm |
| 4934 | case Pav_QADDU: opc2 = 512; break; // vaddubs |
| 4935 | case Pav_QADDS: opc2 = 768; break; // vaddsbs |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4936 | |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 4937 | case Pav_SUBU: opc2 = 1024; break; // vsububm |
| 4938 | case Pav_QSUBU: opc2 = 1536; break; // vsububs |
| 4939 | case Pav_QSUBS: opc2 = 1792; break; // vsubsbs |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4940 | |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 4941 | case Pav_OMULU: opc2 = 8; break; // vmuloub |
| 4942 | case Pav_OMULS: opc2 = 264; break; // vmulosb |
| 4943 | case Pav_EMULU: opc2 = 520; break; // vmuleub |
| 4944 | case Pav_EMULS: opc2 = 776; break; // vmulesb |
| 4945 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4946 | case Pav_AVGU: opc2 = 1026; break; // vavgub |
| 4947 | case Pav_AVGS: opc2 = 1282; break; // vavgsb |
| 4948 | case Pav_MAXU: opc2 = 2; break; // vmaxub |
| 4949 | case Pav_MAXS: opc2 = 258; break; // vmaxsb |
| 4950 | case Pav_MINU: opc2 = 514; break; // vminub |
| 4951 | case Pav_MINS: opc2 = 770; break; // vminsb |
| 4952 | |
| 4953 | case Pav_CMPEQU: opc2 = 6; break; // vcmpequb |
| 4954 | case Pav_CMPGTU: opc2 = 518; break; // vcmpgtub |
| 4955 | case Pav_CMPGTS: opc2 = 774; break; // vcmpgtsb |
| 4956 | |
| 4957 | case Pav_SHL: opc2 = 260; break; // vslb |
| 4958 | case Pav_SHR: opc2 = 516; break; // vsrb |
| 4959 | case Pav_SAR: opc2 = 772; break; // vsrab |
| 4960 | case Pav_ROTL: opc2 = 4; break; // vrlb |
| 4961 | |
| 4962 | case Pav_MRGHI: opc2 = 12; break; // vmrghb |
| 4963 | case Pav_MRGLO: opc2 = 268; break; // vmrglb |
| 4964 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 4965 | case Pav_POLYMULADD: opc2 = 1032; break; // vpmsumb |
| 4966 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4967 | default: |
| 4968 | goto bad; |
| 4969 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4970 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4971 | goto done; |
| 4972 | } |
| 4973 | |
| 4974 | case Pin_AvBin16x8: { |
| 4975 | UInt v_dst = vregNo(i->Pin.AvBin16x8.dst); |
| 4976 | UInt v_srcL = vregNo(i->Pin.AvBin16x8.srcL); |
| 4977 | UInt v_srcR = vregNo(i->Pin.AvBin16x8.srcR); |
| 4978 | UInt opc2; |
| 4979 | switch (i->Pin.AvBin16x8.op) { |
| 4980 | |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 4981 | case Pav_ADDU: opc2 = 64; break; // vadduhm |
| 4982 | case Pav_QADDU: opc2 = 576; break; // vadduhs |
| 4983 | case Pav_QADDS: opc2 = 832; break; // vaddshs |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4984 | |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 4985 | case Pav_SUBU: opc2 = 1088; break; // vsubuhm |
| 4986 | case Pav_QSUBU: opc2 = 1600; break; // vsubuhs |
| 4987 | case Pav_QSUBS: opc2 = 1856; break; // vsubshs |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4988 | |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 4989 | case Pav_OMULU: opc2 = 72; break; // vmulouh |
| 4990 | case Pav_OMULS: opc2 = 328; break; // vmulosh |
| 4991 | case Pav_EMULU: opc2 = 584; break; // vmuleuh |
| 4992 | case Pav_EMULS: opc2 = 840; break; // vmulesh |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 4993 | |
| 4994 | case Pav_AVGU: opc2 = 1090; break; // vavguh |
| 4995 | case Pav_AVGS: opc2 = 1346; break; // vavgsh |
| 4996 | case Pav_MAXU: opc2 = 66; break; // vmaxuh |
| 4997 | case Pav_MAXS: opc2 = 322; break; // vmaxsh |
| 4998 | case Pav_MINS: opc2 = 834; break; // vminsh |
| 4999 | case Pav_MINU: opc2 = 578; break; // vminuh |
| 5000 | |
| 5001 | case Pav_CMPEQU: opc2 = 70; break; // vcmpequh |
| 5002 | case Pav_CMPGTU: opc2 = 582; break; // vcmpgtuh |
| 5003 | case Pav_CMPGTS: opc2 = 838; break; // vcmpgtsh |
| 5004 | |
| 5005 | case Pav_SHL: opc2 = 324; break; // vslh |
| 5006 | case Pav_SHR: opc2 = 580; break; // vsrh |
| 5007 | case Pav_SAR: opc2 = 836; break; // vsrah |
| 5008 | case Pav_ROTL: opc2 = 68; break; // vrlh |
| 5009 | |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 5010 | case Pav_PACKUU: opc2 = 14; break; // vpkuhum |
| 5011 | case Pav_QPACKUU: opc2 = 142; break; // vpkuhus |
| 5012 | case Pav_QPACKSU: opc2 = 270; break; // vpkshus |
| 5013 | case Pav_QPACKSS: opc2 = 398; break; // vpkshss |
| 5014 | case Pav_PACKPXL: opc2 = 782; break; // vpkpx |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5015 | |
| 5016 | case Pav_MRGHI: opc2 = 76; break; // vmrghh |
| 5017 | case Pav_MRGLO: opc2 = 332; break; // vmrglh |
| 5018 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 5019 | case Pav_POLYMULADD: opc2 = 1224; break; // vpmsumh |
| 5020 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5021 | default: |
| 5022 | goto bad; |
| 5023 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5024 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5025 | goto done; |
| 5026 | } |
| 5027 | |
| 5028 | case Pin_AvBin32x4: { |
| 5029 | UInt v_dst = vregNo(i->Pin.AvBin32x4.dst); |
| 5030 | UInt v_srcL = vregNo(i->Pin.AvBin32x4.srcL); |
| 5031 | UInt v_srcR = vregNo(i->Pin.AvBin32x4.srcR); |
| 5032 | UInt opc2; |
| 5033 | switch (i->Pin.AvBin32x4.op) { |
| 5034 | |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 5035 | case Pav_ADDU: opc2 = 128; break; // vadduwm |
| 5036 | case Pav_QADDU: opc2 = 640; break; // vadduws |
| 5037 | case Pav_QADDS: opc2 = 896; break; // vaddsws |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5038 | |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 5039 | case Pav_SUBU: opc2 = 1152; break; // vsubuwm |
| 5040 | case Pav_QSUBU: opc2 = 1664; break; // vsubuws |
| 5041 | case Pav_QSUBS: opc2 = 1920; break; // vsubsws |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5042 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 5043 | case Pav_MULU: opc2 = 137; break; // vmuluwm |
| 5044 | case Pav_OMULU: opc2 = 136; break; // vmulouw |
| 5045 | case Pav_OMULS: opc2 = 392; break; // vmulosw |
| 5046 | case Pav_EMULU: opc2 = 648; break; // vmuleuw |
| 5047 | case Pav_EMULS: opc2 = 904; break; // vmulesw |
| 5048 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5049 | case Pav_AVGU: opc2 = 1154; break; // vavguw |
| 5050 | case Pav_AVGS: opc2 = 1410; break; // vavgsw |
| 5051 | |
| 5052 | case Pav_MAXU: opc2 = 130; break; // vmaxuw |
| 5053 | case Pav_MAXS: opc2 = 386; break; // vmaxsw |
| 5054 | |
| 5055 | case Pav_MINS: opc2 = 898; break; // vminsw |
| 5056 | case Pav_MINU: opc2 = 642; break; // vminuw |
| 5057 | |
| 5058 | case Pav_CMPEQU: opc2 = 134; break; // vcmpequw |
| 5059 | case Pav_CMPGTS: opc2 = 902; break; // vcmpgtsw |
| 5060 | case Pav_CMPGTU: opc2 = 646; break; // vcmpgtuw |
| 5061 | |
| 5062 | case Pav_SHL: opc2 = 388; break; // vslw |
| 5063 | case Pav_SHR: opc2 = 644; break; // vsrw |
| 5064 | case Pav_SAR: opc2 = 900; break; // vsraw |
| 5065 | case Pav_ROTL: opc2 = 132; break; // vrlw |
| 5066 | |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 5067 | case Pav_PACKUU: opc2 = 78; break; // vpkuwum |
| 5068 | case Pav_QPACKUU: opc2 = 206; break; // vpkuwus |
| 5069 | case Pav_QPACKSU: opc2 = 334; break; // vpkswus |
| 5070 | case Pav_QPACKSS: opc2 = 462; break; // vpkswss |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5071 | |
| 5072 | case Pav_MRGHI: opc2 = 140; break; // vmrghw |
| 5073 | case Pav_MRGLO: opc2 = 396; break; // vmrglw |
| 5074 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 5075 | case Pav_CATODD: opc2 = 1676; break; // vmrgow |
| 5076 | case Pav_CATEVEN: opc2 = 1932; break; // vmrgew |
| 5077 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 5078 | case Pav_POLYMULADD: opc2 = 1160; break; // vpmsumw |
| 5079 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5080 | default: |
| 5081 | goto bad; |
| 5082 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5083 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5084 | goto done; |
| 5085 | } |
| 5086 | |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 5087 | case Pin_AvBin64x2: { |
| 5088 | UInt v_dst = vregNo(i->Pin.AvBin64x2.dst); |
| 5089 | UInt v_srcL = vregNo(i->Pin.AvBin64x2.srcL); |
| 5090 | UInt v_srcR = vregNo(i->Pin.AvBin64x2.srcR); |
| 5091 | UInt opc2; |
| 5092 | switch (i->Pin.AvBin64x2.op) { |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 5093 | case Pav_ADDU: opc2 = 192; break; // vaddudm vector double add |
| 5094 | case Pav_SUBU: opc2 = 1216; break; // vsubudm vector double add |
| 5095 | case Pav_MAXU: opc2 = 194; break; // vmaxud vector double max |
| 5096 | case Pav_MAXS: opc2 = 450; break; // vmaxsd vector double max |
| 5097 | case Pav_MINU: opc2 = 706; break; // vminud vector double min |
| 5098 | case Pav_MINS: opc2 = 962; break; // vminsd vector double min |
| 5099 | case Pav_CMPEQU: opc2 = 199; break; // vcmpequd vector double compare |
| 5100 | case Pav_CMPGTU: opc2 = 711; break; // vcmpgtud vector double compare |
| 5101 | case Pav_CMPGTS: opc2 = 967; break; // vcmpgtsd vector double compare |
| 5102 | case Pav_SHL: opc2 = 1476; break; // vsld |
| 5103 | case Pav_SHR: opc2 = 1732; break; // vsrd |
| 5104 | case Pav_SAR: opc2 = 964; break; // vsrad |
| 5105 | case Pav_ROTL: opc2 = 196; break; // vrld |
| 5106 | case Pav_PACKUU: opc2 = 1102; break; // vpkudum |
| 5107 | case Pav_QPACKUU: opc2 = 1230; break; // vpkudus, vpksdus (emulated) |
| 5108 | case Pav_QPACKSS: opc2 = 1486; break; // vpksdsm |
| 5109 | case Pav_MRGHI: opc2 = 1614; break; // vmrghw |
| 5110 | case Pav_MRGLO: opc2 = 1742; break; // vmrglw |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 5111 | case Pav_POLYMULADD: opc2 = 1096; break; // vpmsumd |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 5112 | default: |
| 5113 | goto bad; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 5114 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5115 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 5116 | goto done; |
| 5117 | } |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 5118 | case Pin_AvCipherV128Unary: { |
| 5119 | UInt v_dst = vregNo(i->Pin.AvCipherV128Unary.dst); |
| 5120 | UInt v_src = vregNo(i->Pin.AvCipherV128Unary.src); |
| 5121 | UInt opc2; |
| 5122 | switch (i->Pin.AvCipherV128Unary.op) { |
| 5123 | case Pav_CIPHERSUBV128: opc2 = 1480; break; // vsbox |
| 5124 | default: |
| 5125 | goto bad; |
| 5126 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5127 | p = mkFormVX( p, 4, v_dst, v_src, 0, opc2, endness_host ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 5128 | goto done; |
| 5129 | } |
| 5130 | case Pin_AvCipherV128Binary: { |
| 5131 | UInt v_dst = vregNo(i->Pin.AvCipherV128Binary.dst); |
| 5132 | UInt v_srcL = vregNo(i->Pin.AvCipherV128Binary.srcL); |
| 5133 | UInt v_srcR = vregNo(i->Pin.AvCipherV128Binary.srcR); |
| 5134 | UInt opc2; |
| 5135 | switch (i->Pin.AvCipherV128Binary.op) { |
| 5136 | case Pav_CIPHERV128: opc2 = 1288; break; // vcipher |
| 5137 | case Pav_CIPHERLV128: opc2 = 1289; break; // vcipherlast |
| 5138 | case Pav_NCIPHERV128: opc2 = 1352; break; // vncipher |
| 5139 | case Pav_NCIPHERLV128: opc2 = 1353; break; // vncipherlast |
| 5140 | default: |
| 5141 | goto bad; |
| 5142 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5143 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 5144 | goto done; |
| 5145 | } |
| 5146 | case Pin_AvHashV128Binary: { |
| 5147 | UInt v_dst = vregNo(i->Pin.AvHashV128Binary.dst); |
| 5148 | UInt v_src = vregNo(i->Pin.AvHashV128Binary.src); |
| 5149 | PPCRI* s_field = i->Pin.AvHashV128Binary.s_field; |
| 5150 | UInt opc2; |
| 5151 | switch (i->Pin.AvHashV128Binary.op) { |
| 5152 | case Pav_SHA256: opc2 = 1666; break; // vshasigmaw |
| 5153 | case Pav_SHA512: opc2 = 1730; break; // vshasigmad |
| 5154 | default: |
| 5155 | goto bad; |
| 5156 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5157 | p = mkFormVX( p, 4, v_dst, v_src, s_field->Pri.Imm, opc2, endness_host ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 5158 | goto done; |
| 5159 | } |
| 5160 | case Pin_AvBCDV128Trinary: { |
| 5161 | UInt v_dst = vregNo(i->Pin.AvBCDV128Trinary.dst); |
| 5162 | UInt v_src1 = vregNo(i->Pin.AvBCDV128Trinary.src1); |
| 5163 | UInt v_src2 = vregNo(i->Pin.AvBCDV128Trinary.src2); |
| 5164 | PPCRI* ps = i->Pin.AvBCDV128Trinary.ps; |
| 5165 | UInt opc2; |
| 5166 | switch (i->Pin.AvBCDV128Trinary.op) { |
| 5167 | case Pav_BCDAdd: opc2 = 1; break; // bcdadd |
| 5168 | case Pav_BCDSub: opc2 = 65; break; // bcdsub |
| 5169 | default: |
| 5170 | goto bad; |
| 5171 | } |
| 5172 | p = mkFormVXR( p, 4, v_dst, v_src1, v_src2, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5173 | 0x1, (ps->Pri.Imm << 9) | opc2, endness_host ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 5174 | goto done; |
| 5175 | } |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5176 | case Pin_AvBin32Fx4: { |
| 5177 | UInt v_dst = vregNo(i->Pin.AvBin32Fx4.dst); |
| 5178 | UInt v_srcL = vregNo(i->Pin.AvBin32Fx4.srcL); |
| 5179 | UInt v_srcR = vregNo(i->Pin.AvBin32Fx4.srcR); |
| 5180 | switch (i->Pin.AvBin32Fx4.op) { |
| 5181 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5182 | case Pavfp_ADDF: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5183 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 10, endness_host ); // vaddfp |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5184 | break; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5185 | case Pavfp_SUBF: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5186 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 74, endness_host ); // vsubfp |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5187 | break; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5188 | case Pavfp_MAXF: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5189 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1034, endness_host ); // vmaxfp |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5190 | break; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5191 | case Pavfp_MINF: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5192 | p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1098, endness_host ); // vminfp |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5193 | break; |
| 5194 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5195 | case Pavfp_MULF: { |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5196 | /* Make a vmulfp from a vmaddfp: |
| 5197 | load -0.0 (0x8000_0000) to each 32-bit word of vB |
| 5198 | this makes the add a noop. |
| 5199 | */ |
sewardj | f774505 | 2005-12-16 01:06:42 +0000 | [diff] [blame] | 5200 | UInt vB = 29; // XXX: Using v29 for temp do not change |
| 5201 | // without also changing |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5202 | // getRegUsage_PPCInstr |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5203 | UInt konst = 0x1F; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5204 | |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 5205 | // Better way to load -0.0 (0x80000000) ? |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5206 | // vspltisw vB,0x1F (0x1F => each word of vB) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5207 | p = mkFormVX( p, 4, vB, konst, 0, 908, endness_host ); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5208 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5209 | // vslw vB,vB,vB (each word of vB = (0x1F << 0x1F) = 0x80000000 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5210 | p = mkFormVX( p, 4, vB, vB, vB, 388, endness_host ); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5211 | |
| 5212 | // Finally, do the multiply: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5213 | p = mkFormVA( p, 4, v_dst, v_srcL, vB, v_srcR, 46, endness_host ); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 5214 | break; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5215 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5216 | case Pavfp_CMPEQF: // vcmpeqfp |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5217 | p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 198, endness_host); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 5218 | break; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5219 | case Pavfp_CMPGTF: // vcmpgtfp |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5220 | p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 710, endness_host ); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 5221 | break; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5222 | case Pavfp_CMPGEF: // vcmpgefp |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5223 | p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 454, endness_host ); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 5224 | break; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5225 | |
| 5226 | default: |
| 5227 | goto bad; |
| 5228 | } |
| 5229 | goto done; |
| 5230 | } |
| 5231 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5232 | case Pin_AvUn32Fx4: { |
| 5233 | UInt v_dst = vregNo(i->Pin.AvUn32Fx4.dst); |
| 5234 | UInt v_src = vregNo(i->Pin.AvUn32Fx4.src); |
| 5235 | UInt opc2; |
| 5236 | switch (i->Pin.AvUn32Fx4.op) { |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 5237 | case Pavfp_RCPF: opc2 = 266; break; // vrefp |
| 5238 | case Pavfp_RSQRTF: opc2 = 330; break; // vrsqrtefp |
| 5239 | case Pavfp_CVTU2F: opc2 = 778; break; // vcfux |
| 5240 | case Pavfp_CVTS2F: opc2 = 842; break; // vcfsx |
| 5241 | case Pavfp_QCVTF2U: opc2 = 906; break; // vctuxs |
| 5242 | case Pavfp_QCVTF2S: opc2 = 970; break; // vctsxs |
| 5243 | case Pavfp_ROUNDM: opc2 = 714; break; // vrfim |
| 5244 | case Pavfp_ROUNDP: opc2 = 650; break; // vrfip |
| 5245 | case Pavfp_ROUNDN: opc2 = 522; break; // vrfin |
| 5246 | case Pavfp_ROUNDZ: opc2 = 586; break; // vrfiz |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5247 | default: |
| 5248 | goto bad; |
| 5249 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5250 | p = mkFormVX( p, 4, v_dst, 0, v_src, opc2, endness_host ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 5251 | goto done; |
| 5252 | } |
| 5253 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5254 | case Pin_AvPerm: { // vperm |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5255 | UInt v_dst = vregNo(i->Pin.AvPerm.dst); |
| 5256 | UInt v_srcL = vregNo(i->Pin.AvPerm.srcL); |
| 5257 | UInt v_srcR = vregNo(i->Pin.AvPerm.srcR); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 5258 | UInt v_ctl = vregNo(i->Pin.AvPerm.ctl); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5259 | p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 43, endness_host ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5260 | goto done; |
| 5261 | } |
| 5262 | |
| 5263 | case Pin_AvSel: { // vsel |
| 5264 | UInt v_ctl = vregNo(i->Pin.AvSel.ctl); |
| 5265 | UInt v_dst = vregNo(i->Pin.AvSel.dst); |
| 5266 | UInt v_srcL = vregNo(i->Pin.AvSel.srcL); |
| 5267 | UInt v_srcR = vregNo(i->Pin.AvSel.srcR); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5268 | p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 42, endness_host ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5269 | goto done; |
| 5270 | } |
| 5271 | |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 5272 | case Pin_AvSh: { // vsl or vsr |
| 5273 | UInt v_dst = vregNo(i->Pin.AvSh.dst); |
| 5274 | Bool idxd = toBool(i->Pin.AvSh.addr->tag == Pam_RR); |
| 5275 | UInt r_idx, r_base; |
| 5276 | |
| 5277 | r_base = iregNo(i->Pin.AvSh.addr->Pam.RR.base, mode64); |
| 5278 | |
| 5279 | if (!idxd) { |
carll | 99de41e | 2014-10-07 18:20:39 +0000 | [diff] [blame] | 5280 | r_idx = 30; // XXX: Using r30 as temp |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 5281 | p = mkLoadImm(p, r_idx, |
| 5282 | i->Pin.AvSh.addr->Pam.IR.index, mode64, endness_host); |
| 5283 | } else { |
| 5284 | r_idx = iregNo(i->Pin.AvSh.addr->Pam.RR.index, mode64); |
| 5285 | } |
| 5286 | |
| 5287 | if (i->Pin.AvSh.shLeft) |
| 5288 | //vsl VRT,RA,RB |
| 5289 | p = mkFormVXI( p, 31, v_dst, r_idx, r_base, 6, endness_host ); |
| 5290 | else |
| 5291 | //vsr VRT,RA,RB |
| 5292 | p = mkFormVXI( p, 31, v_dst, r_idx, r_base, 38, endness_host ); |
| 5293 | goto done; |
| 5294 | } |
| 5295 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5296 | case Pin_AvShlDbl: { // vsldoi |
| 5297 | UInt shift = i->Pin.AvShlDbl.shift; |
| 5298 | UInt v_dst = vregNo(i->Pin.AvShlDbl.dst); |
| 5299 | UInt v_srcL = vregNo(i->Pin.AvShlDbl.srcL); |
| 5300 | UInt v_srcR = vregNo(i->Pin.AvShlDbl.srcR); |
| 5301 | vassert(shift <= 0xF); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5302 | p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, shift, 44, endness_host ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5303 | goto done; |
| 5304 | } |
| 5305 | |
| 5306 | case Pin_AvSplat: { // vsplt(is)(b,h,w) |
| 5307 | UInt v_dst = vregNo(i->Pin.AvShlDbl.dst); |
| 5308 | UChar sz = i->Pin.AvSplat.sz; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 5309 | UInt v_src, opc2; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5310 | vassert(sz == 8 || sz == 16 || sz == 32); |
| 5311 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 5312 | if (i->Pin.AvSplat.src->tag == Pvi_Imm) { |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 5313 | Char simm5; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5314 | opc2 = (sz == 8) ? 780 : (sz == 16) ? 844 : 908; // 8,16,32 |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 5315 | /* expects 5-bit-signed-imm */ |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 5316 | simm5 = i->Pin.AvSplat.src->Pvi.Imm5s; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 5317 | vassert(simm5 >= -16 && simm5 <= 15); |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 5318 | simm5 = simm5 & 0x1F; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5319 | p = mkFormVX( p, 4, v_dst, (UInt)simm5, 0, opc2, endness_host ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 5320 | } |
| 5321 | else { // Pri_Reg |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 5322 | UInt lowest_lane; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5323 | opc2 = (sz == 8) ? 524 : (sz == 16) ? 588 : 652; // 8,16,32 |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 5324 | vassert(hregClass(i->Pin.AvSplat.src->Pvi.Reg) == HRcVec128); |
| 5325 | v_src = vregNo(i->Pin.AvSplat.src->Pvi.Reg); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 5326 | lowest_lane = (128/sz)-1; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5327 | p = mkFormVX( p, 4, v_dst, lowest_lane, v_src, opc2, endness_host ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5328 | } |
| 5329 | goto done; |
| 5330 | } |
| 5331 | |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5332 | case Pin_AvCMov: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5333 | UInt v_dst = vregNo(i->Pin.AvCMov.dst); |
| 5334 | UInt v_src = vregNo(i->Pin.AvCMov.src); |
| 5335 | PPCCondCode cc = i->Pin.AvCMov.cond; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5336 | |
| 5337 | if (v_dst == v_src) goto done; |
| 5338 | |
| 5339 | vassert(cc.test != Pct_ALWAYS); |
| 5340 | |
| 5341 | /* jmp fwds 2 insns if !condition */ |
| 5342 | if (cc.test != Pct_ALWAYS) { |
| 5343 | /* bc !ct,cf,n_bytes>>2 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5344 | p = mkFormB(p, invertCondTest(cc.test), cc.flag, 8>>2, 0, 0, |
| 5345 | endness_host); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5346 | } |
| 5347 | /* vmr */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5348 | p = mkFormVX( p, 4, v_dst, v_src, v_src, 1156, endness_host ); |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 5349 | goto done; |
| 5350 | } |
| 5351 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5352 | case Pin_AvLdVSCR: { // mtvscr |
| 5353 | UInt v_src = vregNo(i->Pin.AvLdVSCR.src); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5354 | p = mkFormVX( p, 4, 0, 0, v_src, 1604, endness_host ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 5355 | goto done; |
| 5356 | } |
| 5357 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5358 | case Pin_Dfp64Unary: { |
| 5359 | UInt fr_dst = fregNo( i->Pin.FpUnary.dst ); |
| 5360 | UInt fr_src = fregNo( i->Pin.FpUnary.src ); |
| 5361 | |
| 5362 | switch (i->Pin.Dfp64Unary.op) { |
| 5363 | case Pfp_MOV: // fmr, PPC32 p410 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5364 | p = mkFormX( p, 63, fr_dst, 0, fr_src, 72, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5365 | break; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5366 | case Pfp_DCTDP: // D32 to D64 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5367 | p = mkFormX( p, 59, fr_dst, 0, fr_src, 258, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5368 | break; |
| 5369 | case Pfp_DRSP: // D64 to D32 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5370 | p = mkFormX( p, 59, fr_dst, 0, fr_src, 770, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5371 | break; |
| 5372 | case Pfp_DCFFIX: // I64 to D64 conversion |
| 5373 | /* ONLY WORKS ON POWER7 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5374 | p = mkFormX( p, 59, fr_dst, 0, fr_src, 802, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5375 | break; |
| 5376 | case Pfp_DCTFIX: // D64 to I64 conversion |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5377 | p = mkFormX( p, 59, fr_dst, 0, fr_src, 290, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5378 | break; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5379 | case Pfp_DXEX: // Extract exponent |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5380 | p = mkFormX( p, 59, fr_dst, 0, fr_src, 354, 0, endness_host ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5381 | break; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5382 | default: |
| 5383 | goto bad; |
| 5384 | } |
| 5385 | goto done; |
| 5386 | } |
| 5387 | |
| 5388 | case Pin_Dfp64Binary: { |
| 5389 | UInt fr_dst = fregNo( i->Pin.Dfp64Binary.dst ); |
| 5390 | UInt fr_srcL = fregNo( i->Pin.Dfp64Binary.srcL ); |
| 5391 | UInt fr_srcR = fregNo( i->Pin.Dfp64Binary.srcR ); |
| 5392 | switch (i->Pin.Dfp64Binary.op) { |
| 5393 | case Pfp_DFPADD: /* dadd, dfp add, use default RM from reg ignore mode |
| 5394 | * from the Iop instruction. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5395 | p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 2, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5396 | break; |
| 5397 | case Pfp_DFPSUB: /* dsub, dfp subtract, use default RM from reg ignore |
| 5398 | * mode from the Iop instruction. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5399 | p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 514, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5400 | break; |
| 5401 | case Pfp_DFPMUL: /* dmul, dfp multipy, use default RM from reg ignore |
| 5402 | * mode from the Iop instruction. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5403 | p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 34, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5404 | break; |
| 5405 | case Pfp_DFPDIV: /* ddiv, dfp divide, use default RM from reg ignore |
| 5406 | * mode from the Iop instruction. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5407 | p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 546, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5408 | break; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5409 | case Pfp_DIEX: /* diex, insert exponent */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5410 | p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 866, 0, endness_host ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5411 | break; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5412 | default: |
| 5413 | goto bad; |
| 5414 | } |
| 5415 | goto done; |
| 5416 | } |
| 5417 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5418 | case Pin_DfpShift: { |
| 5419 | UInt fr_src = fregNo(i->Pin.DfpShift.src); |
| 5420 | UInt fr_dst = fregNo(i->Pin.DfpShift.dst); |
| 5421 | UInt shift; |
| 5422 | |
| 5423 | shift = i->Pin.DfpShift.shift->Pri.Imm; |
| 5424 | |
| 5425 | switch (i->Pin.DfpShift.op) { |
| 5426 | case Pfp_DSCLI: /* dscli, DFP shift left by fr_srcR */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5427 | p = mkFormZ22( p, 59, fr_dst, fr_src, shift, 66, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5428 | break; |
| 5429 | case Pfp_DSCRI: /* dscri, DFP shift right by fr_srcR */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5430 | p = mkFormZ22( p, 59, fr_dst, fr_src, shift, 98, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5431 | break; |
| 5432 | default: |
| 5433 | vex_printf("ERROR: emit_PPCInstr default case\n"); |
| 5434 | goto bad; |
| 5435 | } |
| 5436 | goto done; |
| 5437 | } |
| 5438 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5439 | case Pin_ExtractExpD128: { |
| 5440 | UInt fr_dst = fregNo(i->Pin.ExtractExpD128.dst); |
| 5441 | UInt fr_srcHi = fregNo(i->Pin.ExtractExpD128.src_hi); |
| 5442 | UInt fr_srcLo = fregNo(i->Pin.ExtractExpD128.src_lo); |
| 5443 | |
| 5444 | switch (i->Pin.ExtractExpD128.op) { |
| 5445 | case Pfp_DXEXQ: |
| 5446 | /* Setup the upper and lower registers of the source operand |
| 5447 | * register pair. |
| 5448 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5449 | p = mkFormX( p, 63, 12, 0, fr_srcHi, 72, 0, endness_host ); |
| 5450 | p = mkFormX( p, 63, 13, 0, fr_srcLo, 72, 0, endness_host ); |
| 5451 | p = mkFormX( p, 63, 10, 0, 12, 354, 0, endness_host ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5452 | |
| 5453 | /* The instruction will put the 64-bit result in |
| 5454 | * register 10. |
| 5455 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5456 | p = mkFormX(p, 63, fr_dst, 0, 10, 72, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5457 | break; |
| 5458 | default: |
| 5459 | vex_printf("Error: emit_PPCInstr case Pin_DfpExtractExp, case inst Default\n"); |
| 5460 | goto bad; |
| 5461 | } |
| 5462 | goto done; |
| 5463 | } |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5464 | case Pin_Dfp128Unary: { |
| 5465 | UInt fr_dstHi = fregNo(i->Pin.Dfp128Unary.dst_hi); |
| 5466 | UInt fr_dstLo = fregNo(i->Pin.Dfp128Unary.dst_lo); |
| 5467 | UInt fr_srcLo = fregNo(i->Pin.Dfp128Unary.src_lo); |
| 5468 | |
| 5469 | /* Do instruction with 128-bit source operands in registers (10,11) |
| 5470 | * and (12,13). |
| 5471 | */ |
| 5472 | switch (i->Pin.Dfp128Unary.op) { |
| 5473 | case Pfp_DCTQPQ: // D64 to D128, srcLo holds 64 bit operand |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5474 | p = mkFormX( p, 63, 12, 0, fr_srcLo, 72, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5475 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5476 | p = mkFormX( p, 63, 10, 0, 12, 258, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5477 | |
| 5478 | /* The instruction will put the 128-bit result in |
| 5479 | * registers (10,11). Note, the operand in the instruction only |
| 5480 | * reference the first of the two registers in the pair. |
| 5481 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5482 | p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); |
| 5483 | p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5484 | break; |
| 5485 | default: |
| 5486 | vex_printf("Error: emit_PPCInstr case Pin_Dfp128Unary, case inst Default\ |
| 5487 | \n"); |
| 5488 | goto bad; |
| 5489 | } |
| 5490 | goto done; |
| 5491 | } |
| 5492 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5493 | case Pin_Dfp128Binary: { |
| 5494 | /* dst is used to supply the left source operand and return |
| 5495 | * the result. |
| 5496 | */ |
| 5497 | UInt fr_dstHi = fregNo( i->Pin.Dfp128Binary.dst_hi ); |
| 5498 | UInt fr_dstLo = fregNo( i->Pin.Dfp128Binary.dst_lo ); |
| 5499 | UInt fr_srcRHi = fregNo( i->Pin.Dfp128Binary.srcR_hi ); |
| 5500 | UInt fr_srcRLo = fregNo( i->Pin.Dfp128Binary.srcR_lo ); |
| 5501 | |
| 5502 | /* Setup the upper and lower registers of the source operand |
| 5503 | * register pair. |
| 5504 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5505 | p = mkFormX( p, 63, 10, 0, fr_dstHi, 72, 0, endness_host ); |
| 5506 | p = mkFormX( p, 63, 11, 0, fr_dstLo, 72, 0, endness_host ); |
| 5507 | p = mkFormX( p, 63, 12, 0, fr_srcRHi, 72, 0, endness_host ); |
| 5508 | p = mkFormX( p, 63, 13, 0, fr_srcRLo, 72, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5509 | |
| 5510 | /* Do instruction with 128-bit source operands in registers (10,11) |
| 5511 | * and (12,13). |
| 5512 | */ |
| 5513 | switch (i->Pin.Dfp128Binary.op) { |
| 5514 | case Pfp_DFPADDQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5515 | p = mkFormX( p, 63, 10, 10, 12, 2, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5516 | break; |
| 5517 | case Pfp_DFPSUBQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5518 | p = mkFormX( p, 63, 10, 10, 12, 514, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5519 | break; |
| 5520 | case Pfp_DFPMULQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5521 | p = mkFormX( p, 63, 10, 10, 12, 34, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5522 | break; |
| 5523 | case Pfp_DFPDIVQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5524 | p = mkFormX( p, 63, 10, 10, 12, 546, 0, endness_host ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5525 | break; |
| 5526 | default: |
| 5527 | goto bad; |
| 5528 | } |
| 5529 | |
| 5530 | /* The instruction will put the 128-bit result in |
| 5531 | * registers (10,11). Note, the operand in the instruction only |
| 5532 | * reference the first of the two registers in the pair. |
| 5533 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5534 | p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); |
| 5535 | p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 5536 | goto done; |
| 5537 | } |
| 5538 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5539 | case Pin_DfpShift128: { |
| 5540 | UInt fr_src_hi = fregNo(i->Pin.DfpShift128.src_hi); |
| 5541 | UInt fr_src_lo = fregNo(i->Pin.DfpShift128.src_lo); |
| 5542 | UInt fr_dst_hi = fregNo(i->Pin.DfpShift128.dst_hi); |
| 5543 | UInt fr_dst_lo = fregNo(i->Pin.DfpShift128.dst_lo); |
| 5544 | UInt shift; |
| 5545 | |
| 5546 | shift = i->Pin.DfpShift128.shift->Pri.Imm; |
| 5547 | |
| 5548 | /* setup source operand in register 12, 13 pair */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5549 | p = mkFormX(p, 63, 12, 0, fr_src_hi, 72, 0, endness_host); |
| 5550 | p = mkFormX(p, 63, 13, 0, fr_src_lo, 72, 0, endness_host); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5551 | |
| 5552 | /* execute instruction putting result in register 10, 11 pair */ |
| 5553 | switch (i->Pin.DfpShift128.op) { |
| 5554 | case Pfp_DSCLIQ: /* dscliq, DFP shift left, fr_srcR is the integer |
| 5555 | * shift amount. |
| 5556 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5557 | p = mkFormZ22( p, 63, 10, 12, shift, 66, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5558 | break; |
| 5559 | case Pfp_DSCRIQ: /* dscriq, DFP shift right, fr_srcR is the integer |
| 5560 | * shift amount. |
| 5561 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5562 | p = mkFormZ22( p, 63, 10, 12, shift, 98, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5563 | break; |
| 5564 | default: |
| 5565 | vex_printf("ERROR: emit_PPCInstr quad default case %d \n", |
| 5566 | i->Pin.DfpShift128.op); |
| 5567 | goto bad; |
| 5568 | } |
| 5569 | |
| 5570 | /* The instruction put the 128-bit result in registers (10,11). |
| 5571 | * Note, the operand in the instruction only reference the first of |
| 5572 | * the two registers in the pair. |
| 5573 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5574 | p = mkFormX(p, 63, fr_dst_hi, 0, 10, 72, 0, endness_host); |
| 5575 | p = mkFormX(p, 63, fr_dst_lo, 0, 11, 72, 0, endness_host); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5576 | goto done; |
| 5577 | } |
| 5578 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5579 | case Pin_DfpRound: { |
| 5580 | UInt fr_dst = fregNo(i->Pin.DfpRound.dst); |
| 5581 | UInt fr_src = fregNo(i->Pin.DfpRound.src); |
| 5582 | UInt r_rmc, r, rmc; |
| 5583 | |
| 5584 | r_rmc = i->Pin.DfpRound.r_rmc->Pri.Imm; |
| 5585 | r = (r_rmc & 0x8) >> 3; |
| 5586 | rmc = r_rmc & 0x3; |
| 5587 | |
| 5588 | // drintx |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5589 | p = mkFormZ23(p, 59, fr_dst, r, fr_src, rmc, 99, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5590 | goto done; |
| 5591 | } |
| 5592 | |
| 5593 | case Pin_DfpRound128: { |
| 5594 | UInt fr_dstHi = fregNo(i->Pin.DfpRound128.dst_hi); |
| 5595 | UInt fr_dstLo = fregNo(i->Pin.DfpRound128.dst_lo); |
| 5596 | UInt fr_srcHi = fregNo(i->Pin.DfpRound128.src_hi); |
| 5597 | UInt fr_srcLo = fregNo(i->Pin.DfpRound128.src_lo); |
| 5598 | UInt r_rmc, r, rmc; |
| 5599 | |
| 5600 | r_rmc = i->Pin.DfpRound128.r_rmc->Pri.Imm; |
| 5601 | r = (r_rmc & 0x8) >> 3; |
| 5602 | rmc = r_rmc & 0x3; |
| 5603 | |
| 5604 | /* Setup the upper and lower registers of the source operand |
| 5605 | * register pair. |
| 5606 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5607 | p = mkFormX(p, 63, 12, 0, fr_srcHi, 72, 0, endness_host); |
| 5608 | p = mkFormX(p, 63, 13, 0, fr_srcLo, 72, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5609 | |
| 5610 | /* Do drintx instruction with 128-bit source operands in |
| 5611 | * registers (12,13). |
| 5612 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5613 | p = mkFormZ23(p, 63, 10, r, 12, rmc, 99, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5614 | |
| 5615 | /* The instruction will put the 128-bit result in |
| 5616 | * registers (10,11). Note, the operand in the instruction only |
| 5617 | * reference the first of the two registers in the pair. |
| 5618 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5619 | p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); |
| 5620 | p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5621 | goto done; |
| 5622 | } |
| 5623 | |
| 5624 | case Pin_DfpQuantize: { |
| 5625 | UInt fr_dst = fregNo(i->Pin.DfpQuantize.dst); |
| 5626 | UInt fr_srcL = fregNo(i->Pin.DfpQuantize.srcL); |
| 5627 | UInt fr_srcR = fregNo(i->Pin.DfpQuantize.srcR); |
| 5628 | UInt rmc; |
| 5629 | |
| 5630 | rmc = i->Pin.DfpQuantize.rmc->Pri.Imm; |
| 5631 | |
| 5632 | switch (i->Pin.DfpQuantize.op) { |
| 5633 | case Pfp_DQUA: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5634 | p = mkFormZ23(p, 59, fr_dst, fr_srcL, fr_srcR, rmc, 3, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5635 | break; |
| 5636 | case Pfp_RRDTR: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5637 | p = mkFormZ23(p, 59, fr_dst, fr_srcL, fr_srcR, rmc, 35, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5638 | break; |
| 5639 | default: |
| 5640 | break; |
| 5641 | } |
| 5642 | goto done; |
| 5643 | } |
| 5644 | |
| 5645 | case Pin_DfpQuantize128: { |
| 5646 | UInt fr_dst_hi = fregNo(i->Pin.DfpQuantize128.dst_hi); |
| 5647 | UInt fr_dst_lo = fregNo(i->Pin.DfpQuantize128.dst_lo); |
| 5648 | UInt fr_src_hi = fregNo(i->Pin.DfpQuantize128.src_hi); |
| 5649 | UInt fr_src_lo = fregNo(i->Pin.DfpQuantize128.src_lo); |
| 5650 | UInt rmc; |
| 5651 | |
| 5652 | rmc = i->Pin.DfpQuantize128.rmc->Pri.Imm; |
| 5653 | /* Setup the upper and lower registers of the source operand |
| 5654 | * register pairs. Note, left source operand passed in via the |
| 5655 | * dst register pair. |
| 5656 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5657 | p = mkFormX(p, 63, 10, 0, fr_dst_hi, 72, 0, endness_host); |
| 5658 | p = mkFormX(p, 63, 11, 0, fr_dst_lo, 72, 0, endness_host); |
| 5659 | p = mkFormX(p, 63, 12, 0, fr_src_hi, 72, 0, endness_host); |
| 5660 | p = mkFormX(p, 63, 13, 0, fr_src_lo, 72, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5661 | |
| 5662 | /* Do dquaq instruction with 128-bit source operands in |
| 5663 | * registers (12,13). |
| 5664 | */ |
| 5665 | switch (i->Pin.DfpQuantize128.op) { |
| 5666 | case Pfp_DQUAQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5667 | p = mkFormZ23(p, 63, 10, 10, 12, rmc, 3, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5668 | break; |
| 5669 | case Pfp_DRRNDQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5670 | p = mkFormZ23(p, 63, 10, 10, 12, rmc, 35, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5671 | break; |
| 5672 | default: |
| 5673 | vpanic("Pin_DfpQuantize128: default case, couldn't find inst to issue \n"); |
| 5674 | break; |
| 5675 | } |
| 5676 | |
| 5677 | /* The instruction will put the 128-bit result in |
| 5678 | * registers (10,11). Note, the operand in the instruction only |
| 5679 | * reference the first of the two registers in the pair. |
| 5680 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5681 | p = mkFormX(p, 63, fr_dst_hi, 0, 10, 72, 0, endness_host); |
| 5682 | p = mkFormX(p, 63, fr_dst_lo, 0, 11, 72, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5683 | goto done; |
| 5684 | } |
| 5685 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5686 | case Pin_DfpD128toD64: { |
| 5687 | UInt fr_dst = fregNo( i->Pin.DfpD128toD64.dst ); |
| 5688 | UInt fr_srcHi = fregNo( i->Pin.DfpD128toD64.src_hi ); |
| 5689 | UInt fr_srcLo = fregNo( i->Pin.DfpD128toD64.src_lo ); |
| 5690 | |
| 5691 | /* Setup the upper and lower registers of the source operand |
| 5692 | * register pair. |
| 5693 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5694 | p = mkFormX( p, 63, 10, 0, fr_dst, 72, 0, endness_host ); |
| 5695 | p = mkFormX( p, 63, 12, 0, fr_srcHi, 72, 0, endness_host ); |
| 5696 | p = mkFormX( p, 63, 13, 0, fr_srcLo, 72, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5697 | |
| 5698 | /* Do instruction with 128-bit source operands in registers (10,11) */ |
| 5699 | switch (i->Pin.Dfp128Binary.op) { |
| 5700 | case Pfp_DRDPQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5701 | p = mkFormX( p, 63, 10, 0, 12, 770, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5702 | break; |
| 5703 | case Pfp_DCTFIXQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5704 | p = mkFormX( p, 63, 10, 0, 12, 290, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5705 | break; |
| 5706 | default: |
| 5707 | goto bad; |
| 5708 | } |
| 5709 | |
| 5710 | /* The instruction will put the 64-bit result in registers 10. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5711 | p = mkFormX(p, 63, fr_dst, 0, 10, 72, 0, endness_host); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5712 | goto done; |
| 5713 | } |
sewardj | db01409 | 2012-04-20 23:58:17 +0000 | [diff] [blame] | 5714 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5715 | case Pin_DfpI64StoD128: { |
| 5716 | UInt fr_dstHi = fregNo( i->Pin.DfpI64StoD128.dst_hi ); |
| 5717 | UInt fr_dstLo = fregNo( i->Pin.DfpI64StoD128.dst_lo ); |
| 5718 | UInt fr_src = fregNo( i->Pin.DfpI64StoD128.src ); |
| 5719 | |
| 5720 | switch (i->Pin.Dfp128Binary.op) { |
| 5721 | case Pfp_DCFFIXQ: |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5722 | p = mkFormX( p, 63, 10, 11, fr_src, 802, 0, endness_host ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5723 | break; |
| 5724 | default: |
| 5725 | goto bad; |
| 5726 | } |
| 5727 | |
| 5728 | /* The instruction will put the 64-bit result in registers 10, 11. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5729 | p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); |
| 5730 | p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 5731 | goto done; |
| 5732 | } |
sewardj | db01409 | 2012-04-20 23:58:17 +0000 | [diff] [blame] | 5733 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5734 | case Pin_InsertExpD128: { |
| 5735 | UInt fr_dstHi = fregNo(i->Pin.InsertExpD128.dst_hi); |
| 5736 | UInt fr_dstLo = fregNo(i->Pin.InsertExpD128.dst_lo); |
| 5737 | UInt fr_srcL = fregNo(i->Pin.InsertExpD128.srcL); |
| 5738 | UInt fr_srcRHi = fregNo(i->Pin.InsertExpD128.srcR_hi); |
| 5739 | UInt fr_srcRLo = fregNo(i->Pin.InsertExpD128.srcR_lo); |
| 5740 | |
| 5741 | /* The left operand is a single F64 value, the right is an F128 |
| 5742 | * register pair. |
| 5743 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5744 | p = mkFormX(p, 63, 10, 0, fr_srcL, 72, 0, endness_host); |
| 5745 | p = mkFormX(p, 63, 12, 0, fr_srcRHi, 72, 0, endness_host); |
| 5746 | p = mkFormX(p, 63, 13, 0, fr_srcRLo, 72, 0, endness_host); |
| 5747 | p = mkFormX(p, 63, 10, 10, 12, 866, 0, endness_host ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5748 | |
| 5749 | /* The instruction will put the 128-bit result into |
| 5750 | * registers (10,11). Note, the operand in the instruction only |
| 5751 | * reference the first of the two registers in the pair. |
| 5752 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5753 | p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); |
| 5754 | p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5755 | goto done; |
| 5756 | } |
| 5757 | |
| 5758 | case Pin_Dfp64Cmp:{ |
| 5759 | UChar crfD = 1; |
| 5760 | UInt r_dst = iregNo(i->Pin.Dfp64Cmp.dst, mode64); |
| 5761 | UInt fr_srcL = fregNo(i->Pin.Dfp64Cmp.srcL); |
| 5762 | UInt fr_srcR = fregNo(i->Pin.Dfp64Cmp.srcR); |
| 5763 | vassert(crfD < 8); |
| 5764 | // dcmpo, dcmpu |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5765 | p = mkFormX(p, 59, crfD<<2, fr_srcL, fr_srcR, 130, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5766 | |
| 5767 | // mfcr (mv CR to r_dst) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5768 | p = mkFormX(p, 31, r_dst, 0, 0, 19, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5769 | |
| 5770 | // rlwinm r_dst,r_dst,8,28,31 |
| 5771 | // => rotate field 1 to bottomw of word, masking out upper 28 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5772 | p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5773 | goto done; |
| 5774 | } |
| 5775 | |
| 5776 | case Pin_Dfp128Cmp: { |
| 5777 | UChar crfD = 1; |
| 5778 | UInt r_dst = iregNo(i->Pin.Dfp128Cmp.dst, mode64); |
| 5779 | UInt fr_srcL_hi = fregNo(i->Pin.Dfp128Cmp.srcL_hi); |
| 5780 | UInt fr_srcL_lo = fregNo(i->Pin.Dfp128Cmp.srcL_lo); |
| 5781 | UInt fr_srcR_hi = fregNo(i->Pin.Dfp128Cmp.srcR_hi); |
| 5782 | UInt fr_srcR_lo = fregNo(i->Pin.Dfp128Cmp.srcR_lo); |
| 5783 | vassert(crfD < 8); |
| 5784 | // dcmpoq, dcmpuq |
| 5785 | /* Setup the upper and lower registers of the source operand |
| 5786 | * register pair. |
| 5787 | */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5788 | p = mkFormX(p, 63, 10, 0, fr_srcL_hi, 72, 0, endness_host); |
| 5789 | p = mkFormX(p, 63, 11, 0, fr_srcL_lo, 72, 0, endness_host); |
| 5790 | p = mkFormX(p, 63, 12, 0, fr_srcR_hi, 72, 0, endness_host); |
| 5791 | p = mkFormX(p, 63, 13, 0, fr_srcR_lo, 72, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5792 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5793 | p = mkFormX(p, 63, crfD<<2, 10, 12, 130, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5794 | |
| 5795 | // mfcr (mv CR to r_dst) |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5796 | p = mkFormX(p, 31, r_dst, 0, 0, 19, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5797 | |
| 5798 | // rlwinm r_dst,r_dst,8,28,31 |
| 5799 | // => rotate field 1 to bottomw of word, masking out upper 28 |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5800 | p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0, endness_host); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 5801 | goto done; |
| 5802 | } |
| 5803 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5804 | case Pin_EvCheck: { |
| 5805 | /* This requires a 32-bit dec/test in both 32- and 64-bit |
| 5806 | modes. */ |
| 5807 | /* We generate: |
| 5808 | lwz r30, amCounter |
| 5809 | addic. r30, r30, -1 |
| 5810 | stw r30, amCounter |
| 5811 | bge nofail |
| 5812 | lwz/ld r30, amFailAddr |
| 5813 | mtctr r30 |
| 5814 | bctr |
| 5815 | nofail: |
| 5816 | */ |
| 5817 | UChar* p0 = p; |
| 5818 | /* lwz r30, amCounter */ |
| 5819 | p = do_load_or_store_word32(p, True/*isLoad*/, /*r*/30, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5820 | i->Pin.EvCheck.amCounter, mode64, |
| 5821 | endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5822 | /* addic. r30,r30,-1 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5823 | p = emit32(p, 0x37DEFFFF, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5824 | /* stw r30, amCounter */ |
| 5825 | p = do_load_or_store_word32(p, False/*!isLoad*/, /*r*/30, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5826 | i->Pin.EvCheck.amCounter, mode64, |
| 5827 | endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5828 | /* bge nofail */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5829 | p = emit32(p, 0x40800010, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5830 | /* lwz/ld r30, amFailAddr */ |
| 5831 | p = do_load_or_store_machine_word(p, True/*isLoad*/, /*r*/30, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5832 | i->Pin.EvCheck.amFailAddr, mode64, |
| 5833 | endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5834 | /* mtctr r30 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5835 | p = mkFormXFX(p, /*r*/30, 9, 467, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5836 | /* bctr */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5837 | p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5838 | /* nofail: */ |
| 5839 | |
| 5840 | /* Crosscheck */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 5841 | vassert(evCheckSzB_PPC(endness_host) == (UChar*)p - (UChar*)p0); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5842 | goto done; |
| 5843 | } |
| 5844 | |
| 5845 | case Pin_ProfInc: { |
| 5846 | /* We generate: |
| 5847 | (ctrP is unknown now, so use 0x65556555(65556555) in the |
| 5848 | expectation that a later call to LibVEX_patchProfCtr |
| 5849 | will be used to fill in the immediate fields once the |
| 5850 | right value is known.) |
| 5851 | 32-bit: |
| 5852 | imm32-exactly r30, 0x65556555 |
| 5853 | lwz r29, 4(r30) |
| 5854 | addic. r29, r29, 1 |
| 5855 | stw r29, 4(r30) |
| 5856 | lwz r29, 0(r30) |
| 5857 | addze r29, r29 |
| 5858 | stw r29, 0(r30) |
| 5859 | 64-bit: |
| 5860 | imm64-exactly r30, 0x6555655565556555 |
| 5861 | ld r29, 0(r30) |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 5862 | addi r29, r29, 1 |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5863 | std r29, 0(r30) |
| 5864 | */ |
| 5865 | if (mode64) { |
| 5866 | p = mkLoadImm_EXACTLY2or5( |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5867 | p, /*r*/30, 0x6555655565556555ULL, True/*mode64*/, endness_host); |
| 5868 | p = emit32(p, 0xEBBE0000, endness_host); |
| 5869 | p = emit32(p, 0x3BBD0001, endness_host); |
| 5870 | p = emit32(p, 0xFBBE0000, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5871 | } else { |
| 5872 | p = mkLoadImm_EXACTLY2or5( |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5873 | p, /*r*/30, 0x65556555ULL, False/*!mode64*/, endness_host); |
| 5874 | p = emit32(p, 0x83BE0004, endness_host); |
| 5875 | p = emit32(p, 0x37BD0001, endness_host); |
| 5876 | p = emit32(p, 0x93BE0004, endness_host); |
| 5877 | p = emit32(p, 0x83BE0000, endness_host); |
| 5878 | p = emit32(p, 0x7FBD0194, endness_host); |
| 5879 | p = emit32(p, 0x93BE0000, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5880 | } |
| 5881 | /* Tell the caller .. */ |
| 5882 | vassert(!(*is_profInc)); |
| 5883 | *is_profInc = True; |
| 5884 | goto done; |
| 5885 | } |
| 5886 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 5887 | default: |
| 5888 | goto bad; |
| 5889 | } |
| 5890 | |
| 5891 | bad: |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 5892 | vex_printf("\n=> "); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5893 | ppPPCInstr(i, mode64); |
| 5894 | vpanic("emit_PPCInstr"); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 5895 | /*NOTREACHED*/ |
| 5896 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 5897 | done: |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 5898 | vassert(p - &buf[0] <= 64); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 5899 | return p - &buf[0]; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 5900 | } |
| 5901 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5902 | |
| 5903 | /* How big is an event check? See case for Pin_EvCheck in |
| 5904 | emit_PPCInstr just above. That crosschecks what this returns, so |
| 5905 | we can tell if we're inconsistent. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 5906 | Int evCheckSzB_PPC ( VexEndness endness_host ) |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5907 | { |
| 5908 | return 28; |
| 5909 | } |
| 5910 | |
| 5911 | |
| 5912 | /* NB: what goes on here has to be very closely coordinated with the |
| 5913 | emitInstr case for XDirect, above. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 5914 | VexInvalRange chainXDirect_PPC ( VexEndness endness_host, |
| 5915 | void* place_to_chain, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 5916 | const void* disp_cp_chain_me_EXPECTED, |
| 5917 | const void* place_to_jump_to, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5918 | Bool mode64 ) |
| 5919 | { |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 5920 | if (mode64) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5921 | vassert((endness_host == VexEndnessBE) || |
| 5922 | (endness_host == VexEndnessLE)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 5923 | } else { |
| 5924 | vassert(endness_host == VexEndnessBE); |
| 5925 | } |
| 5926 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5927 | /* What we're expecting to see is: |
| 5928 | imm32/64-fixed r30, disp_cp_chain_me_to_EXPECTED |
| 5929 | mtctr r30 |
| 5930 | bctrl |
| 5931 | viz |
| 5932 | <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5> |
| 5933 | 7F C9 03 A6 |
| 5934 | 4E 80 04 21 |
| 5935 | */ |
| 5936 | UChar* p = (UChar*)place_to_chain; |
| 5937 | vassert(0 == (3 & (HWord)p)); |
| 5938 | vassert(isLoadImm_EXACTLY2or5(p, /*r*/30, |
| 5939 | Ptr_to_ULong(disp_cp_chain_me_EXPECTED), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5940 | mode64, endness_host)); |
| 5941 | vassert(fetch32(p + (mode64 ? 20 : 8) + 0, endness_host) == 0x7FC903A6); |
| 5942 | vassert(fetch32(p + (mode64 ? 20 : 8) + 4, endness_host) == 0x4E800421); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5943 | /* And what we want to change it to is: |
| 5944 | imm32/64-fixed r30, place_to_jump_to |
| 5945 | mtctr r30 |
| 5946 | bctr |
| 5947 | viz |
| 5948 | <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5> |
| 5949 | 7F C9 03 A6 |
| 5950 | 4E 80 04 20 |
| 5951 | The replacement has the same length as the original. |
| 5952 | */ |
| 5953 | p = mkLoadImm_EXACTLY2or5(p, /*r*/30, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5954 | Ptr_to_ULong(place_to_jump_to), mode64, |
| 5955 | endness_host); |
| 5956 | p = emit32(p, 0x7FC903A6, endness_host); |
| 5957 | p = emit32(p, 0x4E800420, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5958 | |
| 5959 | Int len = p - (UChar*)place_to_chain; |
| 5960 | vassert(len == (mode64 ? 28 : 16)); /* stay sane */ |
| 5961 | VexInvalRange vir = {(HWord)place_to_chain, len}; |
| 5962 | return vir; |
| 5963 | } |
| 5964 | |
| 5965 | |
| 5966 | /* NB: what goes on here has to be very closely coordinated with the |
| 5967 | emitInstr case for XDirect, above. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 5968 | VexInvalRange unchainXDirect_PPC ( VexEndness endness_host, |
| 5969 | void* place_to_unchain, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 5970 | const void* place_to_jump_to_EXPECTED, |
| 5971 | const void* disp_cp_chain_me, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5972 | Bool mode64 ) |
| 5973 | { |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 5974 | if (mode64) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5975 | vassert((endness_host == VexEndnessBE) || |
| 5976 | (endness_host == VexEndnessLE)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 5977 | } else { |
| 5978 | vassert(endness_host == VexEndnessBE); |
| 5979 | } |
| 5980 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5981 | /* What we're expecting to see is: |
| 5982 | imm32/64-fixed r30, place_to_jump_to_EXPECTED |
| 5983 | mtctr r30 |
| 5984 | bctr |
| 5985 | viz |
| 5986 | <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5> |
| 5987 | 7F C9 03 A6 |
| 5988 | 4E 80 04 20 |
| 5989 | */ |
| 5990 | UChar* p = (UChar*)place_to_unchain; |
| 5991 | vassert(0 == (3 & (HWord)p)); |
| 5992 | vassert(isLoadImm_EXACTLY2or5(p, /*r*/30, |
| 5993 | Ptr_to_ULong(place_to_jump_to_EXPECTED), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 5994 | mode64, endness_host)); |
| 5995 | vassert(fetch32(p + (mode64 ? 20 : 8) + 0, endness_host) == 0x7FC903A6); |
| 5996 | vassert(fetch32(p + (mode64 ? 20 : 8) + 4, endness_host) == 0x4E800420); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5997 | /* And what we want to change it to is: |
| 5998 | imm32/64-fixed r30, disp_cp_chain_me |
| 5999 | mtctr r30 |
| 6000 | bctrl |
| 6001 | viz |
| 6002 | <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5> |
| 6003 | 7F C9 03 A6 |
| 6004 | 4E 80 04 21 |
| 6005 | The replacement has the same length as the original. |
| 6006 | */ |
| 6007 | p = mkLoadImm_EXACTLY2or5(p, /*r*/30, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 6008 | Ptr_to_ULong(disp_cp_chain_me), mode64, |
| 6009 | endness_host); |
| 6010 | p = emit32(p, 0x7FC903A6, endness_host); |
| 6011 | p = emit32(p, 0x4E800421, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6012 | |
| 6013 | Int len = p - (UChar*)place_to_unchain; |
| 6014 | vassert(len == (mode64 ? 28 : 16)); /* stay sane */ |
| 6015 | VexInvalRange vir = {(HWord)place_to_unchain, len}; |
| 6016 | return vir; |
| 6017 | } |
| 6018 | |
| 6019 | |
| 6020 | /* Patch the counter address into a profile inc point, as previously |
| 6021 | created by the Pin_ProfInc case for emit_PPCInstr. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 6022 | VexInvalRange patchProfInc_PPC ( VexEndness endness_host, |
| 6023 | void* place_to_patch, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 6024 | const ULong* location_of_counter, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6025 | Bool mode64 ) |
| 6026 | { |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 6027 | if (mode64) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 6028 | vassert((endness_host == VexEndnessBE) || |
| 6029 | (endness_host == VexEndnessLE)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 6030 | } else { |
| 6031 | vassert(endness_host == VexEndnessBE); |
| 6032 | } |
| 6033 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6034 | UChar* p = (UChar*)place_to_patch; |
| 6035 | vassert(0 == (3 & (HWord)p)); |
| 6036 | |
| 6037 | Int len = 0; |
| 6038 | if (mode64) { |
| 6039 | vassert(isLoadImm_EXACTLY2or5(p, /*r*/30, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 6040 | 0x6555655565556555ULL, True/*mode64*/, |
| 6041 | endness_host)); |
| 6042 | vassert(fetch32(p + 20, endness_host) == 0xEBBE0000); |
| 6043 | vassert(fetch32(p + 24, endness_host) == 0x3BBD0001); |
| 6044 | vassert(fetch32(p + 28, endness_host) == 0xFBBE0000); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6045 | p = mkLoadImm_EXACTLY2or5(p, /*r*/30, |
| 6046 | Ptr_to_ULong(location_of_counter), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 6047 | True/*mode64*/, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6048 | len = p - (UChar*)place_to_patch; |
| 6049 | vassert(len == 20); |
| 6050 | } else { |
| 6051 | vassert(isLoadImm_EXACTLY2or5(p, /*r*/30, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 6052 | 0x65556555ULL, False/*!mode64*/, |
| 6053 | endness_host)); |
| 6054 | vassert(fetch32(p + 8, endness_host) == 0x83BE0004); |
| 6055 | vassert(fetch32(p + 12, endness_host) == 0x37BD0001); |
| 6056 | vassert(fetch32(p + 16, endness_host) == 0x93BE0004); |
| 6057 | vassert(fetch32(p + 20, endness_host) == 0x83BE0000); |
| 6058 | vassert(fetch32(p + 24, endness_host) == 0x7FBD0194); |
| 6059 | vassert(fetch32(p + 28, endness_host) == 0x93BE0000); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6060 | p = mkLoadImm_EXACTLY2or5(p, /*r*/30, |
| 6061 | Ptr_to_ULong(location_of_counter), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 6062 | False/*!mode64*/, endness_host); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6063 | len = p - (UChar*)place_to_patch; |
| 6064 | vassert(len == 8); |
| 6065 | } |
| 6066 | VexInvalRange vir = {(HWord)place_to_patch, len}; |
| 6067 | return vir; |
| 6068 | } |
| 6069 | |
| 6070 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 6071 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 6072 | /*--- end host_ppc_defs.c ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 6073 | /*---------------------------------------------------------------*/ |