Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
Chia-I Wu | 9f03986 | 2014-08-20 15:39:56 +0800 | [diff] [blame] | 25 | #include "genhw/genhw.h" |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 26 | #include "dset.h" |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 27 | #include "img.h" |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 28 | #include "mem.h" |
Chia-I Wu | 018a396 | 2014-08-21 10:37:52 +0800 | [diff] [blame] | 29 | #include "pipeline.h" |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 30 | #include "state.h" |
| 31 | #include "view.h" |
| 32 | #include "cmd_priv.h" |
| 33 | |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 34 | static void gen6_3DPRIMITIVE(struct intel_cmd *cmd, |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 35 | int prim_type, bool indexed, |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 36 | uint32_t vertex_count, |
| 37 | uint32_t vertex_start, |
| 38 | uint32_t instance_count, |
| 39 | uint32_t instance_start, |
| 40 | uint32_t vertex_base) |
| 41 | { |
| 42 | const uint8_t cmd_len = 6; |
| 43 | uint32_t dw0; |
| 44 | |
| 45 | CMD_ASSERT(cmd, 6, 6); |
| 46 | |
Chia-I Wu | b0b9f69 | 2014-08-21 11:33:29 +0800 | [diff] [blame] | 47 | dw0 = GEN_RENDER_CMD(3D, GEN6, 3DPRIMITIVE) | |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 48 | prim_type << GEN6_3DPRIM_DW0_TYPE__SHIFT | |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 49 | (cmd_len - 2); |
| 50 | |
| 51 | if (indexed) |
| 52 | dw0 |= GEN6_3DPRIM_DW0_ACCESS_RANDOM; |
| 53 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 54 | cmd_batch_reserve(cmd, cmd_len); |
| 55 | cmd_batch_write(cmd, dw0); |
| 56 | cmd_batch_write(cmd, vertex_count); |
| 57 | cmd_batch_write(cmd, vertex_start); |
| 58 | cmd_batch_write(cmd, instance_count); |
| 59 | cmd_batch_write(cmd, instance_start); |
| 60 | cmd_batch_write(cmd, vertex_base); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | static void gen7_3DPRIMITIVE(struct intel_cmd *cmd, |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 64 | int prim_type, bool indexed, |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 65 | uint32_t vertex_count, |
| 66 | uint32_t vertex_start, |
| 67 | uint32_t instance_count, |
| 68 | uint32_t instance_start, |
| 69 | uint32_t vertex_base) |
| 70 | { |
| 71 | const uint8_t cmd_len = 7; |
| 72 | uint32_t dw0, dw1; |
| 73 | |
| 74 | CMD_ASSERT(cmd, 7, 7.5); |
| 75 | |
Chia-I Wu | b0b9f69 | 2014-08-21 11:33:29 +0800 | [diff] [blame] | 76 | dw0 = GEN_RENDER_CMD(3D, GEN6, 3DPRIMITIVE) | (cmd_len - 2); |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 77 | dw1 = prim_type << GEN7_3DPRIM_DW1_TYPE__SHIFT; |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 78 | |
| 79 | if (indexed) |
| 80 | dw1 |= GEN7_3DPRIM_DW1_ACCESS_RANDOM; |
| 81 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 82 | cmd_batch_reserve(cmd, cmd_len); |
| 83 | cmd_batch_write(cmd, dw0); |
| 84 | cmd_batch_write(cmd, dw1); |
| 85 | cmd_batch_write(cmd, vertex_count); |
| 86 | cmd_batch_write(cmd, vertex_start); |
| 87 | cmd_batch_write(cmd, instance_count); |
| 88 | cmd_batch_write(cmd, instance_start); |
| 89 | cmd_batch_write(cmd, vertex_base); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 90 | } |
| 91 | |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 92 | static bool gen6_can_primitive_restart(const struct intel_cmd *cmd) |
| 93 | { |
| 94 | const struct intel_pipeline *p = cmd->bind.pipeline.graphics; |
| 95 | bool supported; |
| 96 | |
| 97 | CMD_ASSERT(cmd, 6, 7.5); |
| 98 | |
| 99 | if (cmd_gen(cmd) >= INTEL_GEN(7.5)) |
| 100 | return (p->prim_type != GEN6_3DPRIM_RECTLIST); |
| 101 | |
| 102 | switch (p->prim_type) { |
| 103 | case GEN6_3DPRIM_POINTLIST: |
| 104 | case GEN6_3DPRIM_LINELIST: |
| 105 | case GEN6_3DPRIM_LINESTRIP: |
| 106 | case GEN6_3DPRIM_TRILIST: |
| 107 | case GEN6_3DPRIM_TRISTRIP: |
| 108 | supported = true; |
| 109 | break; |
| 110 | default: |
| 111 | supported = false; |
| 112 | break; |
| 113 | } |
| 114 | |
| 115 | if (!supported) |
| 116 | return false; |
| 117 | |
| 118 | switch (cmd->bind.index.type) { |
| 119 | case XGL_INDEX_8: |
| 120 | supported = (p->primitive_restart_index != 0xffu); |
| 121 | break; |
| 122 | case XGL_INDEX_16: |
| 123 | supported = (p->primitive_restart_index != 0xffffu); |
| 124 | break; |
| 125 | case XGL_INDEX_32: |
| 126 | supported = (p->primitive_restart_index != 0xffffffffu); |
| 127 | break; |
| 128 | default: |
| 129 | supported = false; |
| 130 | break; |
| 131 | } |
| 132 | |
| 133 | return supported; |
| 134 | } |
| 135 | |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 136 | static void gen6_3DSTATE_INDEX_BUFFER(struct intel_cmd *cmd, |
Chia-I Wu | 958d1b7 | 2014-08-21 11:28:11 +0800 | [diff] [blame] | 137 | const struct intel_mem *mem, |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 138 | XGL_GPU_SIZE offset, |
| 139 | XGL_INDEX_TYPE type, |
| 140 | bool enable_cut_index) |
| 141 | { |
| 142 | const uint8_t cmd_len = 3; |
| 143 | uint32_t dw0, end_offset; |
| 144 | unsigned offset_align; |
| 145 | |
| 146 | CMD_ASSERT(cmd, 6, 7.5); |
| 147 | |
Chia-I Wu | b0b9f69 | 2014-08-21 11:33:29 +0800 | [diff] [blame] | 148 | dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 149 | |
| 150 | /* the bit is moved to 3DSTATE_VF */ |
| 151 | if (cmd_gen(cmd) >= INTEL_GEN(7.5)) |
| 152 | assert(!enable_cut_index); |
| 153 | if (enable_cut_index) |
| 154 | dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE; |
| 155 | |
| 156 | switch (type) { |
| 157 | case XGL_INDEX_8: |
| 158 | dw0 |= GEN6_IB_DW0_FORMAT_BYTE; |
| 159 | offset_align = 1; |
| 160 | break; |
| 161 | case XGL_INDEX_16: |
| 162 | dw0 |= GEN6_IB_DW0_FORMAT_WORD; |
| 163 | offset_align = 2; |
| 164 | break; |
| 165 | case XGL_INDEX_32: |
| 166 | dw0 |= GEN6_IB_DW0_FORMAT_DWORD; |
| 167 | offset_align = 4; |
| 168 | break; |
| 169 | default: |
| 170 | cmd->result = XGL_ERROR_INVALID_VALUE; |
| 171 | return; |
| 172 | break; |
| 173 | } |
| 174 | |
| 175 | if (offset % offset_align) { |
| 176 | cmd->result = XGL_ERROR_INVALID_VALUE; |
| 177 | return; |
| 178 | } |
| 179 | |
| 180 | /* aligned and inclusive */ |
| 181 | end_offset = mem->size - (mem->size % offset_align) - 1; |
| 182 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 183 | cmd_batch_reserve(cmd, cmd_len); |
| 184 | cmd_batch_write(cmd, dw0); |
| 185 | cmd_batch_reloc(cmd, offset, mem, INTEL_DOMAIN_VERTEX, 0); |
| 186 | cmd_batch_reloc(cmd, end_offset, mem, INTEL_DOMAIN_VERTEX, 0); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 187 | } |
| 188 | |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 189 | static inline void |
| 190 | gen75_3DSTATE_VF(struct intel_cmd *cmd, |
| 191 | bool enable_cut_index, |
| 192 | uint32_t cut_index) |
| 193 | { |
| 194 | const uint8_t cmd_len = 2; |
| 195 | uint32_t dw0; |
| 196 | |
| 197 | CMD_ASSERT(cmd, 7.5, 7.5); |
| 198 | |
| 199 | dw0 = GEN_RENDER_CMD(3D, GEN75, 3DSTATE_VF) | (cmd_len - 2); |
| 200 | if (enable_cut_index) |
| 201 | dw0 |= GEN75_VF_DW0_CUT_INDEX_ENABLE; |
| 202 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 203 | cmd_batch_reserve(cmd, cmd_len); |
| 204 | cmd_batch_write(cmd, dw0); |
| 205 | cmd_batch_write(cmd, cut_index); |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 206 | } |
| 207 | |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 208 | static void gen6_3DSTATE_DEPTH_BUFFER(struct intel_cmd *cmd, |
| 209 | const struct intel_ds_view *view) |
| 210 | { |
| 211 | const uint8_t cmd_len = 7; |
| 212 | uint32_t dw0; |
| 213 | |
| 214 | CMD_ASSERT(cmd, 6, 7.5); |
| 215 | |
| 216 | dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ? |
| 217 | GEN_RENDER_CMD(3D, GEN7, 3DSTATE_DEPTH_BUFFER) : |
| 218 | GEN_RENDER_CMD(3D, GEN6, 3DSTATE_DEPTH_BUFFER); |
| 219 | dw0 |= (cmd_len - 2); |
| 220 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 221 | cmd_batch_reserve(cmd, cmd_len); |
| 222 | cmd_batch_write(cmd, dw0); |
| 223 | cmd_batch_write(cmd, view->cmd[0]); |
| 224 | cmd_batch_reloc(cmd, view->cmd[1], view->img->obj.mem, |
| 225 | INTEL_DOMAIN_RENDER, |
| 226 | INTEL_DOMAIN_RENDER); |
| 227 | cmd_batch_write(cmd, view->cmd[2]); |
| 228 | cmd_batch_write(cmd, view->cmd[3]); |
| 229 | cmd_batch_write(cmd, view->cmd[4]); |
| 230 | cmd_batch_write(cmd, view->cmd[5]); |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | static void gen6_3DSTATE_STENCIL_BUFFER(struct intel_cmd *cmd, |
| 234 | const struct intel_ds_view *view) |
| 235 | { |
| 236 | const uint8_t cmd_len = 3; |
| 237 | uint32_t dw0; |
| 238 | |
| 239 | CMD_ASSERT(cmd, 6, 7.5); |
| 240 | |
| 241 | dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ? |
| 242 | GEN_RENDER_CMD(3D, GEN7, 3DSTATE_STENCIL_BUFFER) : |
| 243 | GEN_RENDER_CMD(3D, GEN6, 3DSTATE_STENCIL_BUFFER); |
| 244 | dw0 |= (cmd_len - 2); |
| 245 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 246 | cmd_batch_reserve(cmd, cmd_len); |
| 247 | cmd_batch_write(cmd, dw0); |
| 248 | cmd_batch_write(cmd, view->cmd[6]); |
| 249 | cmd_batch_reloc(cmd, view->cmd[7], view->img->obj.mem, |
| 250 | INTEL_DOMAIN_RENDER, |
| 251 | INTEL_DOMAIN_RENDER); |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | static void gen6_3DSTATE_HIER_DEPTH_BUFFER(struct intel_cmd *cmd, |
| 255 | const struct intel_ds_view *view) |
| 256 | { |
| 257 | const uint8_t cmd_len = 3; |
| 258 | uint32_t dw0; |
| 259 | |
| 260 | CMD_ASSERT(cmd, 6, 7.5); |
| 261 | |
| 262 | dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ? |
| 263 | GEN_RENDER_CMD(3D, GEN7, 3DSTATE_HIER_DEPTH_BUFFER) : |
| 264 | GEN_RENDER_CMD(3D, GEN6, 3DSTATE_HIER_DEPTH_BUFFER); |
| 265 | dw0 |= (cmd_len - 2); |
| 266 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 267 | cmd_batch_reserve(cmd, cmd_len); |
| 268 | cmd_batch_write(cmd, dw0); |
| 269 | cmd_batch_write(cmd, view->cmd[8]); |
| 270 | cmd_batch_reloc(cmd, view->cmd[9], view->img->obj.mem, |
| 271 | INTEL_DOMAIN_RENDER, |
| 272 | INTEL_DOMAIN_RENDER); |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 273 | } |
| 274 | |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 275 | static void gen6_3DSTATE_CC_STATE_POINTERS(struct intel_cmd *cmd, |
| 276 | XGL_UINT blend_pos, |
| 277 | XGL_UINT ds_pos, |
| 278 | XGL_UINT cc_pos) |
| 279 | { |
| 280 | const uint8_t cmd_len = 4; |
| 281 | uint32_t dw0; |
| 282 | |
| 283 | CMD_ASSERT(cmd, 6, 6); |
| 284 | |
| 285 | dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_CC_STATE_POINTERS) | |
| 286 | (cmd_len - 2); |
| 287 | |
| 288 | cmd_batch_reserve(cmd, cmd_len); |
| 289 | cmd_batch_write(cmd, dw0); |
| 290 | cmd_batch_write(cmd, (blend_pos << 2) | 1); |
| 291 | cmd_batch_write(cmd, (ds_pos << 2) | 1); |
| 292 | cmd_batch_write(cmd, (cc_pos << 2) | 1); |
| 293 | } |
| 294 | |
Chia-I Wu | 1744cca | 2014-08-22 11:10:17 +0800 | [diff] [blame^] | 295 | static void gen6_3DSTATE_VIEWPORT_STATE_POINTERS(struct intel_cmd *cmd, |
| 296 | XGL_UINT clip_pos, |
| 297 | XGL_UINT sf_pos, |
| 298 | XGL_UINT cc_pos) |
| 299 | { |
| 300 | const uint8_t cmd_len = 4; |
| 301 | uint32_t dw0; |
| 302 | |
| 303 | CMD_ASSERT(cmd, 6, 6); |
| 304 | |
| 305 | dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_VIEWPORT_STATE_POINTERS) | |
| 306 | GEN6_PTR_VP_DW0_CLIP_CHANGED | |
| 307 | GEN6_PTR_VP_DW0_SF_CHANGED | |
| 308 | GEN6_PTR_VP_DW0_CC_CHANGED | |
| 309 | (cmd_len - 2); |
| 310 | |
| 311 | cmd_batch_reserve(cmd, cmd_len); |
| 312 | cmd_batch_write(cmd, dw0); |
| 313 | cmd_batch_write(cmd, clip_pos << 2); |
| 314 | cmd_batch_write(cmd, sf_pos << 2); |
| 315 | cmd_batch_write(cmd, cc_pos << 2); |
| 316 | } |
| 317 | |
| 318 | static void gen6_3DSTATE_SCISSOR_STATE_POINTERS(struct intel_cmd *cmd, |
| 319 | XGL_UINT scissor_pos) |
| 320 | { |
| 321 | const uint8_t cmd_len = 2; |
| 322 | uint32_t dw0; |
| 323 | |
| 324 | CMD_ASSERT(cmd, 6, 6); |
| 325 | |
| 326 | dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_SCISSOR_STATE_POINTERS) | |
| 327 | (cmd_len - 2); |
| 328 | |
| 329 | cmd_batch_reserve(cmd, cmd_len); |
| 330 | cmd_batch_write(cmd, dw0); |
| 331 | cmd_batch_write(cmd, scissor_pos << 2); |
| 332 | } |
| 333 | |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 334 | static void gen7_3dstate_pointer(struct intel_cmd *cmd, |
| 335 | int subop, XGL_UINT pos) |
| 336 | { |
| 337 | const uint8_t cmd_len = 2; |
| 338 | const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER | |
| 339 | GEN6_RENDER_SUBTYPE_3D | |
| 340 | subop | (cmd_len - 2); |
| 341 | |
| 342 | cmd_batch_reserve(cmd, cmd_len); |
| 343 | cmd_batch_write(cmd, dw0); |
| 344 | cmd_batch_write(cmd, pos << 2); |
| 345 | } |
| 346 | |
| 347 | static XGL_UINT gen6_BLEND_STATE(struct intel_cmd *cmd, |
| 348 | const struct intel_blend_state *state) |
| 349 | { |
| 350 | const uint8_t cmd_align = GEN6_ALIGNMENT_BLEND_STATE; |
| 351 | const uint8_t cmd_len = XGL_MAX_COLOR_ATTACHMENTS * 2; |
| 352 | |
| 353 | CMD_ASSERT(cmd, 6, 7.5); |
| 354 | STATIC_ASSERT(ARRAY_SIZE(state->cmd) >= cmd_len); |
| 355 | |
| 356 | return cmd_state_copy(cmd, state->cmd, cmd_len, cmd_align); |
| 357 | } |
| 358 | |
| 359 | static XGL_UINT gen6_DEPTH_STENCIL_STATE(struct intel_cmd *cmd, |
| 360 | const struct intel_ds_state *state) |
| 361 | { |
| 362 | const uint8_t cmd_align = GEN6_ALIGNMENT_DEPTH_STENCIL_STATE; |
| 363 | const uint8_t cmd_len = 3; |
| 364 | |
| 365 | CMD_ASSERT(cmd, 6, 7.5); |
| 366 | STATIC_ASSERT(ARRAY_SIZE(state->cmd) >= cmd_len); |
| 367 | |
| 368 | return cmd_state_copy(cmd, state->cmd, cmd_len, cmd_align); |
| 369 | } |
| 370 | |
| 371 | static XGL_UINT gen6_COLOR_CALC_STATE(struct intel_cmd *cmd, |
| 372 | uint32_t stencil_ref, |
| 373 | const uint32_t blend_color[4]) |
| 374 | { |
| 375 | const uint8_t cmd_align = GEN6_ALIGNMENT_COLOR_CALC_STATE; |
| 376 | const uint8_t cmd_len = 6; |
| 377 | XGL_UINT pos; |
| 378 | uint32_t *dw; |
| 379 | |
| 380 | CMD_ASSERT(cmd, 6, 7.5); |
| 381 | |
| 382 | dw = cmd_state_reserve(cmd, cmd_len, cmd_align, &pos); |
| 383 | dw[0] = stencil_ref; |
| 384 | dw[1] = 0; |
| 385 | dw[2] = blend_color[0]; |
| 386 | dw[3] = blend_color[1]; |
| 387 | dw[4] = blend_color[2]; |
| 388 | dw[5] = blend_color[3]; |
| 389 | cmd_state_advance(cmd, cmd_len); |
| 390 | |
| 391 | return pos; |
| 392 | } |
| 393 | |
| 394 | static void gen6_cc_states(struct intel_cmd *cmd) |
| 395 | { |
| 396 | const struct intel_blend_state *blend = cmd->bind.state.blend; |
| 397 | const struct intel_ds_state *ds = cmd->bind.state.ds; |
| 398 | XGL_UINT blend_pos, ds_pos, cc_pos; |
Chia-I Wu | ce9f11f | 2014-08-22 10:38:51 +0800 | [diff] [blame] | 399 | uint32_t stencil_ref; |
| 400 | uint32_t blend_color[4]; |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 401 | |
| 402 | CMD_ASSERT(cmd, 6, 6); |
| 403 | |
Chia-I Wu | ce9f11f | 2014-08-22 10:38:51 +0800 | [diff] [blame] | 404 | if (blend) { |
| 405 | blend_pos = gen6_BLEND_STATE(cmd, blend); |
| 406 | memcpy(blend_color, blend->cmd_blend_color, sizeof(blend_color)); |
| 407 | } else { |
| 408 | blend_pos = 0; |
| 409 | memset(blend_color, 0, sizeof(blend_color)); |
| 410 | } |
| 411 | |
| 412 | if (ds) { |
| 413 | ds_pos = gen6_DEPTH_STENCIL_STATE(cmd, ds); |
| 414 | stencil_ref = ds->cmd_stencil_ref; |
| 415 | } else { |
| 416 | ds_pos = 0; |
| 417 | stencil_ref = 0; |
| 418 | } |
| 419 | |
| 420 | cc_pos = gen6_COLOR_CALC_STATE(cmd, stencil_ref, blend_color); |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 421 | |
| 422 | gen6_3DSTATE_CC_STATE_POINTERS(cmd, blend_pos, ds_pos, cc_pos); |
| 423 | } |
| 424 | |
Chia-I Wu | 1744cca | 2014-08-22 11:10:17 +0800 | [diff] [blame^] | 425 | static void gen6_viewport_states(struct intel_cmd *cmd) |
| 426 | { |
| 427 | const struct intel_viewport_state *viewport = cmd->bind.state.viewport; |
| 428 | XGL_UINT pos; |
| 429 | |
| 430 | if (!viewport) |
| 431 | return; |
| 432 | |
| 433 | pos = cmd_state_copy(cmd, viewport->cmd, viewport->cmd_len, |
| 434 | viewport->cmd_align); |
| 435 | |
| 436 | gen6_3DSTATE_VIEWPORT_STATE_POINTERS(cmd, |
| 437 | pos + viewport->cmd_clip_offset, |
| 438 | pos, |
| 439 | pos + viewport->cmd_cc_offset); |
| 440 | |
| 441 | pos = (viewport->scissor_enable) ? |
| 442 | pos + viewport->cmd_scissor_rect_offset : 0; |
| 443 | |
| 444 | gen6_3DSTATE_SCISSOR_STATE_POINTERS(cmd, pos); |
| 445 | } |
| 446 | |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 447 | static void gen7_cc_states(struct intel_cmd *cmd) |
| 448 | { |
| 449 | const struct intel_blend_state *blend = cmd->bind.state.blend; |
| 450 | const struct intel_ds_state *ds = cmd->bind.state.ds; |
Chia-I Wu | ce9f11f | 2014-08-22 10:38:51 +0800 | [diff] [blame] | 451 | uint32_t stencil_ref; |
| 452 | uint32_t blend_color[4]; |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 453 | XGL_UINT pos; |
| 454 | |
| 455 | CMD_ASSERT(cmd, 7, 7.5); |
| 456 | |
Chia-I Wu | ce9f11f | 2014-08-22 10:38:51 +0800 | [diff] [blame] | 457 | if (!blend && !ds) |
| 458 | return; |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 459 | |
Chia-I Wu | ce9f11f | 2014-08-22 10:38:51 +0800 | [diff] [blame] | 460 | if (blend) { |
| 461 | pos = gen6_BLEND_STATE(cmd, blend); |
| 462 | gen7_3dstate_pointer(cmd, |
| 463 | GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS, pos); |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 464 | |
Chia-I Wu | ce9f11f | 2014-08-22 10:38:51 +0800 | [diff] [blame] | 465 | memcpy(blend_color, blend->cmd_blend_color, sizeof(blend_color)); |
| 466 | } else { |
| 467 | memset(blend_color, 0, sizeof(blend_color)); |
| 468 | } |
| 469 | |
| 470 | if (ds) { |
| 471 | pos = gen6_DEPTH_STENCIL_STATE(cmd, ds); |
| 472 | gen7_3dstate_pointer(cmd, |
| 473 | GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, pos); |
| 474 | } else { |
| 475 | stencil_ref = 0; |
| 476 | } |
| 477 | |
| 478 | pos = gen6_COLOR_CALC_STATE(cmd, stencil_ref, blend_color); |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 479 | gen7_3dstate_pointer(cmd, |
| 480 | GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, pos); |
| 481 | } |
| 482 | |
Chia-I Wu | 1744cca | 2014-08-22 11:10:17 +0800 | [diff] [blame^] | 483 | static void gen7_viewport_states(struct intel_cmd *cmd) |
| 484 | { |
| 485 | const struct intel_viewport_state *viewport = cmd->bind.state.viewport; |
| 486 | XGL_UINT pos; |
| 487 | |
| 488 | if (!viewport) |
| 489 | return; |
| 490 | |
| 491 | pos = cmd_state_copy(cmd, viewport->cmd, viewport->cmd_len, |
| 492 | viewport->cmd_align); |
| 493 | |
| 494 | gen7_3dstate_pointer(cmd, |
| 495 | GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, pos); |
| 496 | gen7_3dstate_pointer(cmd, |
| 497 | GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC, |
| 498 | pos + viewport->cmd_cc_offset); |
| 499 | if (viewport->scissor_enable) { |
| 500 | gen7_3dstate_pointer(cmd, |
| 501 | GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS, |
| 502 | pos + viewport->cmd_scissor_rect_offset); |
| 503 | } |
| 504 | } |
| 505 | |
Chia-I Wu | 5250010 | 2014-08-22 00:46:04 +0800 | [diff] [blame] | 506 | static void emit_bounded_states(struct intel_cmd *cmd) |
| 507 | { |
| 508 | const struct intel_msaa_state *msaa = cmd->bind.state.msaa; |
| 509 | |
| 510 | /* TODO more states */ |
| 511 | |
Chia-I Wu | 1744cca | 2014-08-22 11:10:17 +0800 | [diff] [blame^] | 512 | if (cmd_gen(cmd) >= INTEL_GEN(7)) { |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 513 | gen7_cc_states(cmd); |
Chia-I Wu | 1744cca | 2014-08-22 11:10:17 +0800 | [diff] [blame^] | 514 | gen7_viewport_states(cmd); |
| 515 | } else { |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 516 | gen6_cc_states(cmd); |
Chia-I Wu | 1744cca | 2014-08-22 11:10:17 +0800 | [diff] [blame^] | 517 | gen6_viewport_states(cmd); |
| 518 | } |
Chia-I Wu | 302742d | 2014-08-22 10:28:29 +0800 | [diff] [blame] | 519 | |
Chia-I Wu | 5250010 | 2014-08-22 00:46:04 +0800 | [diff] [blame] | 520 | /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */ |
| 521 | cmd_batch_reserve(cmd, msaa->cmd_len); |
| 522 | cmd_batch_write_n(cmd, msaa->cmd, msaa->cmd_len); |
| 523 | } |
| 524 | |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 525 | XGL_VOID XGLAPI intelCmdBindPipeline( |
| 526 | XGL_CMD_BUFFER cmdBuffer, |
| 527 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 528 | XGL_PIPELINE pipeline) |
| 529 | { |
| 530 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 531 | |
| 532 | switch (pipelineBindPoint) { |
| 533 | case XGL_PIPELINE_BIND_POINT_COMPUTE: |
Chia-I Wu | 018a396 | 2014-08-21 10:37:52 +0800 | [diff] [blame] | 534 | cmd->bind.pipeline.compute = intel_pipeline(pipeline); |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 535 | break; |
| 536 | case XGL_PIPELINE_BIND_POINT_GRAPHICS: |
Chia-I Wu | 018a396 | 2014-08-21 10:37:52 +0800 | [diff] [blame] | 537 | cmd->bind.pipeline.graphics = intel_pipeline(pipeline); |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 538 | break; |
| 539 | default: |
| 540 | break; |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | XGL_VOID XGLAPI intelCmdBindPipelineDelta( |
| 545 | XGL_CMD_BUFFER cmdBuffer, |
| 546 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 547 | XGL_PIPELINE_DELTA delta) |
| 548 | { |
| 549 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 550 | |
| 551 | switch (pipelineBindPoint) { |
| 552 | case XGL_PIPELINE_BIND_POINT_COMPUTE: |
| 553 | cmd->bind.pipeline.compute_delta = delta; |
| 554 | break; |
| 555 | case XGL_PIPELINE_BIND_POINT_GRAPHICS: |
| 556 | cmd->bind.pipeline.graphics_delta = delta; |
| 557 | break; |
| 558 | default: |
| 559 | break; |
| 560 | } |
| 561 | } |
| 562 | |
| 563 | XGL_VOID XGLAPI intelCmdBindStateObject( |
| 564 | XGL_CMD_BUFFER cmdBuffer, |
| 565 | XGL_STATE_BIND_POINT stateBindPoint, |
| 566 | XGL_STATE_OBJECT state) |
| 567 | { |
| 568 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 569 | |
| 570 | switch (stateBindPoint) { |
| 571 | case XGL_STATE_BIND_VIEWPORT: |
| 572 | cmd->bind.state.viewport = |
| 573 | intel_viewport_state((XGL_VIEWPORT_STATE_OBJECT) state); |
| 574 | break; |
| 575 | case XGL_STATE_BIND_RASTER: |
| 576 | cmd->bind.state.raster = |
| 577 | intel_raster_state((XGL_RASTER_STATE_OBJECT) state); |
| 578 | break; |
| 579 | case XGL_STATE_BIND_DEPTH_STENCIL: |
| 580 | cmd->bind.state.ds = |
| 581 | intel_ds_state((XGL_DEPTH_STENCIL_STATE_OBJECT) state); |
| 582 | break; |
| 583 | case XGL_STATE_BIND_COLOR_BLEND: |
| 584 | cmd->bind.state.blend = |
| 585 | intel_blend_state((XGL_COLOR_BLEND_STATE_OBJECT) state); |
| 586 | break; |
| 587 | case XGL_STATE_BIND_MSAA: |
| 588 | cmd->bind.state.msaa = |
| 589 | intel_msaa_state((XGL_MSAA_STATE_OBJECT) state); |
| 590 | break; |
| 591 | default: |
| 592 | break; |
| 593 | } |
| 594 | } |
| 595 | |
| 596 | XGL_VOID XGLAPI intelCmdBindDescriptorSet( |
| 597 | XGL_CMD_BUFFER cmdBuffer, |
| 598 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 599 | XGL_UINT index, |
| 600 | XGL_DESCRIPTOR_SET descriptorSet, |
| 601 | XGL_UINT slotOffset) |
| 602 | { |
| 603 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 604 | struct intel_dset *dset = intel_dset(descriptorSet); |
| 605 | |
| 606 | assert(!index); |
| 607 | |
| 608 | switch (pipelineBindPoint) { |
| 609 | case XGL_PIPELINE_BIND_POINT_COMPUTE: |
| 610 | cmd->bind.dset.compute = dset; |
| 611 | cmd->bind.dset.compute_offset = slotOffset; |
| 612 | break; |
| 613 | case XGL_PIPELINE_BIND_POINT_GRAPHICS: |
| 614 | cmd->bind.dset.graphics = dset; |
| 615 | cmd->bind.dset.graphics_offset = slotOffset; |
| 616 | break; |
| 617 | default: |
| 618 | break; |
| 619 | } |
| 620 | } |
| 621 | |
| 622 | XGL_VOID XGLAPI intelCmdBindDynamicMemoryView( |
| 623 | XGL_CMD_BUFFER cmdBuffer, |
| 624 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 625 | const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView) |
| 626 | { |
| 627 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 628 | |
| 629 | switch (pipelineBindPoint) { |
| 630 | case XGL_PIPELINE_BIND_POINT_COMPUTE: |
| 631 | intel_mem_view_init(&cmd->bind.mem_view.compute, cmd->dev, pMemView); |
| 632 | break; |
| 633 | case XGL_PIPELINE_BIND_POINT_GRAPHICS: |
| 634 | intel_mem_view_init(&cmd->bind.mem_view.graphics, cmd->dev, pMemView); |
| 635 | break; |
| 636 | default: |
| 637 | break; |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | XGL_VOID XGLAPI intelCmdBindIndexData( |
| 642 | XGL_CMD_BUFFER cmdBuffer, |
| 643 | XGL_GPU_MEMORY mem_, |
| 644 | XGL_GPU_SIZE offset, |
| 645 | XGL_INDEX_TYPE indexType) |
| 646 | { |
| 647 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 648 | struct intel_mem *mem = intel_mem(mem_); |
| 649 | |
Chia-I Wu | 9f03986 | 2014-08-20 15:39:56 +0800 | [diff] [blame] | 650 | if (cmd_gen(cmd) >= INTEL_GEN(7.5)) { |
| 651 | gen6_3DSTATE_INDEX_BUFFER(cmd, mem, offset, indexType, false); |
| 652 | } else { |
| 653 | cmd->bind.index.mem = mem; |
| 654 | cmd->bind.index.offset = offset; |
| 655 | cmd->bind.index.type = indexType; |
| 656 | } |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 657 | } |
| 658 | |
| 659 | XGL_VOID XGLAPI intelCmdBindAttachments( |
| 660 | XGL_CMD_BUFFER cmdBuffer, |
| 661 | XGL_UINT colorAttachmentCount, |
| 662 | const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments, |
| 663 | const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment) |
| 664 | { |
| 665 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 666 | const struct intel_ds_view *ds; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 667 | XGL_UINT i; |
| 668 | |
| 669 | for (i = 0; i < colorAttachmentCount; i++) { |
| 670 | const XGL_COLOR_ATTACHMENT_BIND_INFO *att = &pColorAttachments[i]; |
| 671 | struct intel_rt_view *rt = intel_rt_view(att->view); |
| 672 | |
| 673 | cmd->bind.att.rt[i] = rt; |
| 674 | } |
| 675 | |
| 676 | cmd->bind.att.rt_count = colorAttachmentCount; |
| 677 | |
| 678 | if (pDepthStencilAttachment) { |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 679 | cmd->bind.att.ds = intel_ds_view(pDepthStencilAttachment->view); |
| 680 | ds = cmd->bind.att.ds; |
| 681 | |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 682 | } else { |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 683 | /* all zeros */ |
| 684 | static const struct intel_ds_view null_ds; |
| 685 | ds = &null_ds; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 686 | } |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 687 | |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 688 | /* TODO workarounds */ |
Chia-I Wu | 7fae4e3 | 2014-08-21 11:39:44 +0800 | [diff] [blame] | 689 | gen6_3DSTATE_DEPTH_BUFFER(cmd, ds); |
| 690 | gen6_3DSTATE_STENCIL_BUFFER(cmd, ds); |
| 691 | gen6_3DSTATE_HIER_DEPTH_BUFFER(cmd, ds); |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 692 | } |
| 693 | |
| 694 | XGL_VOID XGLAPI intelCmdDraw( |
| 695 | XGL_CMD_BUFFER cmdBuffer, |
| 696 | XGL_UINT firstVertex, |
| 697 | XGL_UINT vertexCount, |
| 698 | XGL_UINT firstInstance, |
| 699 | XGL_UINT instanceCount) |
| 700 | { |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 701 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 702 | const struct intel_pipeline *p = cmd->bind.pipeline.graphics; |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 703 | |
Chia-I Wu | 5250010 | 2014-08-22 00:46:04 +0800 | [diff] [blame] | 704 | emit_bounded_states(cmd); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 705 | |
| 706 | if (cmd_gen(cmd) >= INTEL_GEN(7)) { |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 707 | gen7_3DPRIMITIVE(cmd, p->prim_type, false, vertexCount, |
| 708 | firstVertex, instanceCount, firstInstance, 0); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 709 | } else { |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 710 | gen6_3DPRIMITIVE(cmd, p->prim_type, false, vertexCount, |
| 711 | firstVertex, instanceCount, firstInstance, 0); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 712 | } |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 713 | } |
| 714 | |
| 715 | XGL_VOID XGLAPI intelCmdDrawIndexed( |
| 716 | XGL_CMD_BUFFER cmdBuffer, |
| 717 | XGL_UINT firstIndex, |
| 718 | XGL_UINT indexCount, |
| 719 | XGL_INT vertexOffset, |
| 720 | XGL_UINT firstInstance, |
| 721 | XGL_UINT instanceCount) |
| 722 | { |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 723 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 724 | const struct intel_pipeline *p = cmd->bind.pipeline.graphics; |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 725 | |
Chia-I Wu | 5250010 | 2014-08-22 00:46:04 +0800 | [diff] [blame] | 726 | emit_bounded_states(cmd); |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 727 | |
| 728 | if (p->primitive_restart && !gen6_can_primitive_restart(cmd)) |
| 729 | cmd->result = XGL_ERROR_UNKNOWN; |
| 730 | |
| 731 | if (cmd_gen(cmd) >= INTEL_GEN(7.5)) { |
| 732 | gen75_3DSTATE_VF(cmd, p->primitive_restart, |
| 733 | p->primitive_restart_index); |
| 734 | } else { |
| 735 | gen6_3DSTATE_INDEX_BUFFER(cmd, cmd->bind.index.mem, |
| 736 | cmd->bind.index.offset, cmd->bind.index.type, |
| 737 | p->primitive_restart); |
| 738 | } |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 739 | |
| 740 | if (cmd_gen(cmd) >= INTEL_GEN(7)) { |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 741 | gen7_3DPRIMITIVE(cmd, p->prim_type, true, indexCount, |
| 742 | firstIndex, instanceCount, firstInstance, 0); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 743 | } else { |
Chia-I Wu | 254db42 | 2014-08-21 11:54:29 +0800 | [diff] [blame] | 744 | gen6_3DPRIMITIVE(cmd, p->prim_type, true, indexCount, |
| 745 | firstIndex, instanceCount, firstInstance, 0); |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 746 | } |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 747 | } |
| 748 | |
| 749 | XGL_VOID XGLAPI intelCmdDrawIndirect( |
| 750 | XGL_CMD_BUFFER cmdBuffer, |
| 751 | XGL_GPU_MEMORY mem, |
| 752 | XGL_GPU_SIZE offset, |
| 753 | XGL_UINT32 count, |
| 754 | XGL_UINT32 stride) |
| 755 | { |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 756 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 757 | |
| 758 | cmd->result = XGL_ERROR_UNKNOWN; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | XGL_VOID XGLAPI intelCmdDrawIndexedIndirect( |
| 762 | XGL_CMD_BUFFER cmdBuffer, |
| 763 | XGL_GPU_MEMORY mem, |
| 764 | XGL_GPU_SIZE offset, |
| 765 | XGL_UINT32 count, |
| 766 | XGL_UINT32 stride) |
| 767 | { |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 768 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 769 | |
| 770 | cmd->result = XGL_ERROR_UNKNOWN; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 771 | } |
| 772 | |
| 773 | XGL_VOID XGLAPI intelCmdDispatch( |
| 774 | XGL_CMD_BUFFER cmdBuffer, |
| 775 | XGL_UINT x, |
| 776 | XGL_UINT y, |
| 777 | XGL_UINT z) |
| 778 | { |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 779 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 780 | |
| 781 | cmd->result = XGL_ERROR_UNKNOWN; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 782 | } |
| 783 | |
| 784 | XGL_VOID XGLAPI intelCmdDispatchIndirect( |
| 785 | XGL_CMD_BUFFER cmdBuffer, |
| 786 | XGL_GPU_MEMORY mem, |
| 787 | XGL_GPU_SIZE offset) |
| 788 | { |
Chia-I Wu | 59c097e | 2014-08-21 10:51:07 +0800 | [diff] [blame] | 789 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 790 | |
| 791 | cmd->result = XGL_ERROR_UNKNOWN; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 792 | } |