blob: 8d55c88d203d205e016ca837d5d9fda59945f8b3 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu730e5362014-08-19 12:15:09 +080025#include "genhw/genhw.h"
26#include "kmd/winsys.h"
27#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080028#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080030#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080031
Chia-I Wue24c3292014-08-21 14:05:23 +080032static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
33 struct intel_cmd_writer *writer,
34 XGL_UINT size)
Chia-I Wu730e5362014-08-19 12:15:09 +080035{
36 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wue24c3292014-08-21 14:05:23 +080037 const XGL_GPU_SIZE bo_size = sizeof(uint32_t) * size;
Chia-I Wu730e5362014-08-19 12:15:09 +080038 struct intel_bo *bo;
39 void *ptr;
40
41 bo = intel_winsys_alloc_buffer(winsys,
42 "batch buffer", bo_size, INTEL_DOMAIN_CPU);
43 if (!bo)
44 return XGL_ERROR_OUT_OF_GPU_MEMORY;
45
46 ptr = intel_bo_map(bo, true);
47 if (!bo) {
48 intel_bo_unreference(bo);
49 return XGL_ERROR_MEMORY_MAP_FAILED;
50 }
51
Chia-I Wue24c3292014-08-21 14:05:23 +080052 writer->bo = bo;
53 writer->ptr_opaque = ptr;
54 writer->size = size;
55 writer->used = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +080056
57 return XGL_SUCCESS;
58}
59
Chia-I Wu5e25c272014-08-21 20:19:12 +080060static void cmd_writer_copy(struct intel_cmd *cmd,
61 struct intel_cmd_writer *writer,
62 const uint32_t *vals, XGL_UINT len)
63{
64 assert(writer->used + len <= writer->size);
65 memcpy((uint32_t *) writer->ptr_opaque + writer->used,
66 vals, sizeof(uint32_t) * len);
67 writer->used += len;
68}
69
70static void cmd_writer_patch(struct intel_cmd *cmd,
71 struct intel_cmd_writer *writer,
72 XGL_UINT pos, uint32_t val)
73{
74 assert(pos < writer->used);
75 ((uint32_t *) writer->ptr_opaque)[pos] = val;
76}
77
Chia-I Wue24c3292014-08-21 14:05:23 +080078void cmd_writer_grow(struct intel_cmd *cmd,
79 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +080080{
Chia-I Wue24c3292014-08-21 14:05:23 +080081 const XGL_UINT size = writer->size << 1;
82 const XGL_UINT old_used = writer->used;
83 struct intel_bo *old_bo = writer->bo;
84 void *old_ptr = writer->ptr_opaque;
85
86 if (size >= writer->size &&
87 cmd_writer_alloc_and_map(cmd, writer, size) == XGL_SUCCESS) {
88 cmd_writer_copy(cmd, writer, (const uint32_t *) old_ptr, old_used);
89
90 intel_bo_unmap(old_bo);
91 intel_bo_unreference(old_bo);
92 } else {
93 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
94 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
95 "failed to grow command buffer of size %u", writer->size);
96
97 /* wrap it and fail silently */
98 writer->used = 0;
99 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
100 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800101}
102
Chia-I Wue24c3292014-08-21 14:05:23 +0800103static void cmd_writer_unmap(struct intel_cmd *cmd,
104 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +0800105{
Chia-I Wue24c3292014-08-21 14:05:23 +0800106 intel_bo_unmap(writer->bo);
107 writer->ptr_opaque = NULL;
108}
109
110static void cmd_writer_free(struct intel_cmd *cmd,
111 struct intel_cmd_writer *writer)
112{
113 intel_bo_unreference(writer->bo);
114 writer->bo = NULL;
115}
116
117static void cmd_writer_reset(struct intel_cmd *cmd,
118 struct intel_cmd_writer *writer)
119{
120 /* do not reset writer->size as we want to know how big it has grown to */
121 writer->used = 0;
122
123 if (writer->ptr_opaque)
124 cmd_writer_unmap(cmd, writer);
125 if (writer->bo)
126 cmd_writer_free(cmd, writer);
127}
128
129static void cmd_unmap(struct intel_cmd *cmd)
130{
131 cmd_writer_unmap(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800132 cmd_writer_unmap(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800133 cmd_writer_unmap(cmd, &cmd->kernel);
Chia-I Wu730e5362014-08-19 12:15:09 +0800134}
135
136static void cmd_reset(struct intel_cmd *cmd)
137{
Chia-I Wue24c3292014-08-21 14:05:23 +0800138 cmd_writer_reset(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800139 cmd_writer_reset(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800140 cmd_writer_reset(cmd, &cmd->kernel);
Chia-I Wu343b1372014-08-20 16:39:20 +0800141 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800142 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800143}
144
145static void cmd_destroy(struct intel_obj *obj)
146{
147 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
148
149 intel_cmd_destroy(cmd);
150}
151
152XGL_RESULT intel_cmd_create(struct intel_dev *dev,
153 const XGL_CMD_BUFFER_CREATE_INFO *info,
154 struct intel_cmd **cmd_ret)
155{
156 struct intel_cmd *cmd;
157
158 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
159 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
160 if (!cmd)
161 return XGL_ERROR_OUT_OF_MEMORY;
162
163 cmd->obj.destroy = cmd_destroy;
164
165 cmd->dev = dev;
Chia-I Wue24c3292014-08-21 14:05:23 +0800166
Chia-I Wue0cdd832014-08-25 12:38:56 +0800167 /*
168 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
169 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
170 * and end offsets, for each referenced memories.
171 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800172 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
173 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
174 4096, XGL_SYSTEM_ALLOC_INTERNAL);
175 if (!cmd->relocs) {
176 intel_cmd_destroy(cmd);
177 return XGL_ERROR_OUT_OF_MEMORY;
178 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800179
180 *cmd_ret = cmd;
181
182 return XGL_SUCCESS;
183}
184
185void intel_cmd_destroy(struct intel_cmd *cmd)
186{
187 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800188
189 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800190 intel_base_destroy(&cmd->obj.base);
191}
192
193XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
194{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800195 XGL_RESULT ret;
Chia-I Wu730e5362014-08-19 12:15:09 +0800196
197 cmd_reset(cmd);
198
Chia-I Wu24565ee2014-08-21 20:24:31 +0800199 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800200 cmd->flags = flags;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800201 cmd->batch.size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800202 }
203
Chia-I Wu24565ee2014-08-21 20:24:31 +0800204 if (!cmd->batch.size) {
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800205 const XGL_UINT size =
206 cmd->dev->gpu->max_batch_buffer_size / sizeof(uint32_t) / 2;
207 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800208
209 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
210 divider *= 4;
211
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800212 cmd->batch.size = size / divider;
213 cmd->state.size = size / divider;
214 cmd->kernel.size = 16384 / sizeof(uint32_t) / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800215 }
216
217 ret = cmd_writer_alloc_and_map(cmd, &cmd->batch, cmd->batch.size);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800218 if (ret == XGL_SUCCESS)
219 ret = cmd_writer_alloc_and_map(cmd, &cmd->state, cmd->state.size);
220 if (ret == XGL_SUCCESS)
221 ret = cmd_writer_alloc_and_map(cmd, &cmd->kernel, cmd->kernel.size);
222 if (ret != XGL_SUCCESS) {
223 cmd_reset(cmd);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800224 return ret;
225 }
226
227 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800228}
229
230XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
231{
232 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800233 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800234
Chia-I Wue24c3292014-08-21 14:05:23 +0800235 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800236
Chia-I Wu343b1372014-08-20 16:39:20 +0800237 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800238 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800239 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
240 uint64_t presumed_offset;
241 int err;
242
Chia-I Wue24c3292014-08-21 14:05:23 +0800243 err = intel_bo_add_reloc(reloc->writer->bo,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800244 sizeof(uint32_t) * reloc->pos, reloc->bo, reloc->val,
Chia-I Wue24c3292014-08-21 14:05:23 +0800245 reloc->read_domains, reloc->write_domain, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800246 if (err) {
247 cmd->result = XGL_ERROR_UNKNOWN;
248 break;
249 }
250
251 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wue24c3292014-08-21 14:05:23 +0800252 cmd_writer_patch(cmd, reloc->writer, reloc->pos,
253 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800254 }
255
Chia-I Wu730e5362014-08-19 12:15:09 +0800256 cmd_unmap(cmd);
257
Chia-I Wu04966702014-08-20 15:05:03 +0800258 if (cmd->result != XGL_SUCCESS)
259 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800260
261 if (intel_winsys_can_submit_bo(winsys, &cmd->batch.bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800262 return XGL_SUCCESS;
263 else
264 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
265}
266
Chia-I Wu09142132014-08-11 15:42:55 +0800267XGL_RESULT XGLAPI intelCreateCommandBuffer(
268 XGL_DEVICE device,
269 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
270 XGL_CMD_BUFFER* pCmdBuffer)
271{
Chia-I Wu730e5362014-08-19 12:15:09 +0800272 struct intel_dev *dev = intel_dev(device);
273
274 return intel_cmd_create(dev, pCreateInfo,
275 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800276}
277
278XGL_RESULT XGLAPI intelBeginCommandBuffer(
279 XGL_CMD_BUFFER cmdBuffer,
280 XGL_FLAGS flags)
281{
Chia-I Wu730e5362014-08-19 12:15:09 +0800282 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
283
284 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800285}
286
287XGL_RESULT XGLAPI intelEndCommandBuffer(
288 XGL_CMD_BUFFER cmdBuffer)
289{
Chia-I Wu730e5362014-08-19 12:15:09 +0800290 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
291
292 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800293}
294
295XGL_RESULT XGLAPI intelResetCommandBuffer(
296 XGL_CMD_BUFFER cmdBuffer)
297{
Chia-I Wu730e5362014-08-19 12:15:09 +0800298 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
299
300 cmd_reset(cmd);
301
302 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800303}
304
Chia-I Wu09142132014-08-11 15:42:55 +0800305XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
306 XGL_CMD_BUFFER cmdBuffer,
307 XGL_UINT transitionCount,
308 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions)
309{
310}
311
312XGL_VOID XGLAPI intelCmdPrepareImages(
313 XGL_CMD_BUFFER cmdBuffer,
314 XGL_UINT transitionCount,
315 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions)
316{
317}
318
Chia-I Wu09142132014-08-11 15:42:55 +0800319XGL_VOID XGLAPI intelCmdCopyMemory(
320 XGL_CMD_BUFFER cmdBuffer,
321 XGL_GPU_MEMORY srcMem,
322 XGL_GPU_MEMORY destMem,
323 XGL_UINT regionCount,
324 const XGL_MEMORY_COPY* pRegions)
325{
326}
327
328XGL_VOID XGLAPI intelCmdCopyImage(
329 XGL_CMD_BUFFER cmdBuffer,
330 XGL_IMAGE srcImage,
331 XGL_IMAGE destImage,
332 XGL_UINT regionCount,
333 const XGL_IMAGE_COPY* pRegions)
334{
335}
336
337XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
338 XGL_CMD_BUFFER cmdBuffer,
339 XGL_GPU_MEMORY srcMem,
340 XGL_IMAGE destImage,
341 XGL_UINT regionCount,
342 const XGL_MEMORY_IMAGE_COPY* pRegions)
343{
344}
345
346XGL_VOID XGLAPI intelCmdCopyImageToMemory(
347 XGL_CMD_BUFFER cmdBuffer,
348 XGL_IMAGE srcImage,
349 XGL_GPU_MEMORY destMem,
350 XGL_UINT regionCount,
351 const XGL_MEMORY_IMAGE_COPY* pRegions)
352{
353}
354
355XGL_VOID XGLAPI intelCmdCloneImageData(
356 XGL_CMD_BUFFER cmdBuffer,
357 XGL_IMAGE srcImage,
358 XGL_IMAGE_STATE srcImageState,
359 XGL_IMAGE destImage,
360 XGL_IMAGE_STATE destImageState)
361{
362}
363
364XGL_VOID XGLAPI intelCmdUpdateMemory(
365 XGL_CMD_BUFFER cmdBuffer,
366 XGL_GPU_MEMORY destMem,
367 XGL_GPU_SIZE destOffset,
368 XGL_GPU_SIZE dataSize,
369 const XGL_UINT32* pData)
370{
371}
372
373XGL_VOID XGLAPI intelCmdFillMemory(
374 XGL_CMD_BUFFER cmdBuffer,
375 XGL_GPU_MEMORY destMem,
376 XGL_GPU_SIZE destOffset,
377 XGL_GPU_SIZE fillSize,
378 XGL_UINT32 data)
379{
380}
381
382XGL_VOID XGLAPI intelCmdClearColorImage(
383 XGL_CMD_BUFFER cmdBuffer,
384 XGL_IMAGE image,
385 const XGL_FLOAT color[4],
386 XGL_UINT rangeCount,
387 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
388{
389}
390
391XGL_VOID XGLAPI intelCmdClearColorImageRaw(
392 XGL_CMD_BUFFER cmdBuffer,
393 XGL_IMAGE image,
394 const XGL_UINT32 color[4],
395 XGL_UINT rangeCount,
396 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
397{
398}
399
400XGL_VOID XGLAPI intelCmdClearDepthStencil(
401 XGL_CMD_BUFFER cmdBuffer,
402 XGL_IMAGE image,
403 XGL_FLOAT depth,
404 XGL_UINT32 stencil,
405 XGL_UINT rangeCount,
406 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
407{
408}
409
410XGL_VOID XGLAPI intelCmdResolveImage(
411 XGL_CMD_BUFFER cmdBuffer,
412 XGL_IMAGE srcImage,
413 XGL_IMAGE destImage,
414 XGL_UINT rectCount,
415 const XGL_IMAGE_RESOLVE* pRects)
416{
417}
418
419XGL_VOID XGLAPI intelCmdSetEvent(
420 XGL_CMD_BUFFER cmdBuffer,
421 XGL_EVENT event)
422{
423}
424
425XGL_VOID XGLAPI intelCmdResetEvent(
426 XGL_CMD_BUFFER cmdBuffer,
427 XGL_EVENT event)
428{
429}
430
431XGL_VOID XGLAPI intelCmdMemoryAtomic(
432 XGL_CMD_BUFFER cmdBuffer,
433 XGL_GPU_MEMORY destMem,
434 XGL_GPU_SIZE destOffset,
435 XGL_UINT64 srcData,
436 XGL_ATOMIC_OP atomicOp)
437{
438}
439
440XGL_VOID XGLAPI intelCmdBeginQuery(
441 XGL_CMD_BUFFER cmdBuffer,
442 XGL_QUERY_POOL queryPool,
443 XGL_UINT slot,
444 XGL_FLAGS flags)
445{
446}
447
448XGL_VOID XGLAPI intelCmdEndQuery(
449 XGL_CMD_BUFFER cmdBuffer,
450 XGL_QUERY_POOL queryPool,
451 XGL_UINT slot)
452{
453}
454
455XGL_VOID XGLAPI intelCmdResetQueryPool(
456 XGL_CMD_BUFFER cmdBuffer,
457 XGL_QUERY_POOL queryPool,
458 XGL_UINT startQuery,
459 XGL_UINT queryCount)
460{
461}
462
463XGL_VOID XGLAPI intelCmdWriteTimestamp(
464 XGL_CMD_BUFFER cmdBuffer,
465 XGL_TIMESTAMP_TYPE timestampType,
466 XGL_GPU_MEMORY destMem,
467 XGL_GPU_SIZE destOffset)
468{
469}
470
471XGL_VOID XGLAPI intelCmdInitAtomicCounters(
472 XGL_CMD_BUFFER cmdBuffer,
473 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
474 XGL_UINT startCounter,
475 XGL_UINT counterCount,
476 const XGL_UINT32* pData)
477{
478}
479
480XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
481 XGL_CMD_BUFFER cmdBuffer,
482 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
483 XGL_UINT startCounter,
484 XGL_UINT counterCount,
485 XGL_GPU_MEMORY srcMem,
486 XGL_GPU_SIZE srcOffset)
487{
488}
489
490XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
491 XGL_CMD_BUFFER cmdBuffer,
492 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
493 XGL_UINT startCounter,
494 XGL_UINT counterCount,
495 XGL_GPU_MEMORY destMem,
496 XGL_GPU_SIZE destOffset)
497{
498}
499
500XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
501 XGL_CMD_BUFFER cmdBuffer,
502 const XGL_CHAR* pMarker)
503{
504}
505
506XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
507 XGL_CMD_BUFFER cmdBuffer)
508{
509}