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Chia-I Wu00a23b22014-08-20 15:28:08 +08001/*
Courtney Goeltzenleuchter9cc421e2015-04-08 15:36:08 -06002 * Vulkan
Chia-I Wu00a23b22014-08-20 15:28:08 +08003 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu00a23b22014-08-20 15:28:08 +080026 */
27
28#ifndef CMD_PRIV_H
29#define CMD_PRIV_H
30
Chia-I Wue24c3292014-08-21 14:05:23 +080031#include "genhw/genhw.h"
Chia-I Wu32710d72014-08-20 16:05:22 +080032#include "dev.h"
33#include "gpu.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd.h"
35
Chia-I Wu32710d72014-08-20 16:05:22 +080036#define CMD_ASSERT(cmd, min_gen, max_gen) \
37 INTEL_GPU_ASSERT((cmd)->dev->gpu, (min_gen), (max_gen))
38
Chia-I Wu00b51a82014-09-09 12:07:37 +080039enum intel_cmd_item_type {
40 /* for state buffer */
41 INTEL_CMD_ITEM_BLOB,
42 INTEL_CMD_ITEM_CLIP_VIEWPORT,
43 INTEL_CMD_ITEM_SF_VIEWPORT,
44 INTEL_CMD_ITEM_SCISSOR_RECT,
45 INTEL_CMD_ITEM_CC_VIEWPORT,
46 INTEL_CMD_ITEM_COLOR_CALC,
47 INTEL_CMD_ITEM_DEPTH_STENCIL,
48 INTEL_CMD_ITEM_BLEND,
49 INTEL_CMD_ITEM_SAMPLER,
50
51 /* for surface buffer */
52 INTEL_CMD_ITEM_SURFACE,
53 INTEL_CMD_ITEM_BINDING_TABLE,
54
55 /* for instruction buffer */
56 INTEL_CMD_ITEM_KERNEL,
57
58 INTEL_CMD_ITEM_COUNT,
59};
60
61struct intel_cmd_item {
62 enum intel_cmd_item_type type;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060063 size_t offset;
64 size_t size;
Chia-I Wu00b51a82014-09-09 12:07:37 +080065};
66
Chia-I Wud7d1e482014-10-18 13:25:10 +080067#define INTEL_CMD_RELOC_TARGET_IS_WRITER (1u << 31)
Chia-I Wu958d1b72014-08-21 11:28:11 +080068struct intel_cmd_reloc {
Chia-I Wu68f319d2014-09-09 09:43:21 +080069 enum intel_cmd_writer_type which;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060070 size_t offset;
Chia-I Wu958d1b72014-08-21 11:28:11 +080071
Chia-I Wud7d1e482014-10-18 13:25:10 +080072 intptr_t target;
73 uint32_t target_offset;
Chia-I Wu958d1b72014-08-21 11:28:11 +080074
Chia-I Wu32a22462014-08-26 14:13:46 +080075 uint32_t flags;
Chia-I Wu958d1b72014-08-21 11:28:11 +080076};
77
Chia-I Wuc14d1562014-10-17 09:49:22 +080078struct intel_ds_view;
79
Chia-I Wu29e6f502014-11-24 14:27:29 +080080enum intel_cmd_meta_mode {
81 /*
Chia-I Wu4d344e62014-12-20 21:06:04 +080082 * Draw POINTLIST of (width * height) vertices with only VS enabled. The
83 * vertex id is from 0 to (width * height - 1).
Chia-I Wu29e6f502014-11-24 14:27:29 +080084 */
85 INTEL_CMD_META_VS_POINTS,
86
87 /*
88 * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height)
89 * with only FS enabled.
90 */
91 INTEL_CMD_META_FS_RECT,
92
93 /*
94 * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height)
95 * with only depth/stencil enabled.
96 */
97 INTEL_CMD_META_DEPTH_STENCIL_RECT,
98};
99
Chia-I Wu73520ac2015-02-19 11:17:45 -0700100enum intel_cmd_meta_ds_op {
101 INTEL_CMD_META_DS_NOP,
102 INTEL_CMD_META_DS_HIZ_CLEAR,
103 INTEL_CMD_META_DS_HIZ_RESOLVE,
104 INTEL_CMD_META_DS_RESOLVE,
105};
106
Chia-I Wuc14d1562014-10-17 09:49:22 +0800107struct intel_cmd_meta {
Chia-I Wu29e6f502014-11-24 14:27:29 +0800108 enum intel_cmd_meta_mode mode;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800109 enum intel_dev_meta_shader shader_id;
110
111 struct {
112 bool valid;
113
114 uint32_t surface[8];
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600115 uint32_t surface_len;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800116
117 intptr_t reloc_target;
118 uint32_t reloc_offset;
119 uint32_t reloc_flags;
120
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600121 uint32_t lod, layer;
122 uint32_t x, y;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800123 } src, dst;
124
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800125 struct {
126 struct intel_ds_view *view;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700127 uint32_t stencil_ref;
Courtney Goeltzenleuchter382489d2015-04-10 08:34:15 -0600128 VkImageAspect aspect;
Chia-I Wu73520ac2015-02-19 11:17:45 -0700129
130 enum intel_cmd_meta_ds_op op;
131 bool optimal;
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800132 } ds;
133
Chia-I Wuc14d1562014-10-17 09:49:22 +0800134 uint32_t clear_val[4];
135
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600136 uint32_t width, height;
137 uint32_t samples;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800138};
139
Chia-I Wu9f039862014-08-20 15:39:56 +0800140static inline int cmd_gen(const struct intel_cmd *cmd)
141{
142 return intel_gpu_gen(cmd->dev->gpu);
143}
144
Courtney Goeltzenleuchter382489d2015-04-10 08:34:15 -0600145static inline void cmd_fail(struct intel_cmd *cmd, VkResult result)
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700146{
Courtney Goeltzenleuchter9cc421e2015-04-08 15:36:08 -0600147 intel_dev_log(cmd->dev, VK_DBG_MSG_ERROR,
148 VK_VALIDATION_LEVEL_0, VK_NULL_HANDLE, 0, 0,
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700149 "command building error");
150
151 cmd->result = result;
152}
153
Chia-I Wucdff0592014-08-22 09:27:36 +0800154static inline void cmd_reserve_reloc(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600155 uint32_t reloc_len)
Chia-I Wucdff0592014-08-22 09:27:36 +0800156{
157 /* fail silently */
158 if (cmd->reloc_used + reloc_len > cmd->reloc_count) {
159 cmd->reloc_used = 0;
Courtney Goeltzenleuchterac834522015-05-01 17:56:13 -0600160 cmd_fail(cmd, VK_ERROR_UNKNOWN);
Chia-I Wucdff0592014-08-22 09:27:36 +0800161 }
162 assert(cmd->reloc_used + reloc_len <= cmd->reloc_count);
163}
164
Chia-I Wue24c3292014-08-21 14:05:23 +0800165void cmd_writer_grow(struct intel_cmd *cmd,
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800166 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600167 size_t new_size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800168
Chia-I Wu00b51a82014-09-09 12:07:37 +0800169void cmd_writer_record(struct intel_cmd *cmd,
170 enum intel_cmd_writer_type which,
171 enum intel_cmd_item_type type,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600172 size_t offset, size_t size);
Chia-I Wu00b51a82014-09-09 12:07:37 +0800173
Chia-I Wu72292b72014-09-09 10:48:33 +0800174/**
175 * Return an offset to a region that is aligned to \p alignment and has at
176 * least \p size bytes.
177 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600178static inline size_t cmd_writer_reserve(struct intel_cmd *cmd,
179 enum intel_cmd_writer_type which,
180 size_t alignment, size_t size)
Chia-I Wu72292b72014-09-09 10:48:33 +0800181{
182 struct intel_cmd_writer *writer = &cmd->writers[which];
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600183 size_t offset;
Chia-I Wu72292b72014-09-09 10:48:33 +0800184
185 assert(alignment && u_is_pow2(alignment));
186 offset = u_align(writer->used, alignment);
187
188 if (offset + size > writer->size) {
189 cmd_writer_grow(cmd, which, offset + size);
190 /* align again in case of errors */
191 offset = u_align(writer->used, alignment);
192
193 assert(offset + size <= writer->size);
194 }
195
196 return offset;
197}
Chia-I Wu00a23b22014-08-20 15:28:08 +0800198
Chia-I Wu32710d72014-08-20 16:05:22 +0800199/**
Chia-I Wubda55fd2014-08-25 12:46:10 +0800200 * Add a reloc at \p pos. No error checking.
Chia-I Wucdff0592014-08-22 09:27:36 +0800201 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800202static inline void cmd_writer_reloc(struct intel_cmd *cmd,
203 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600204 size_t offset, intptr_t target,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800205 uint32_t target_offset, uint32_t flags)
Chia-I Wucdff0592014-08-22 09:27:36 +0800206{
207 struct intel_cmd_reloc *reloc = &cmd->relocs[cmd->reloc_used];
208
209 assert(cmd->reloc_used < cmd->reloc_count);
210
Chia-I Wu68f319d2014-09-09 09:43:21 +0800211 reloc->which = which;
Chia-I Wu72292b72014-09-09 10:48:33 +0800212 reloc->offset = offset;
Chia-I Wud7d1e482014-10-18 13:25:10 +0800213 reloc->target = target;
214 reloc->target_offset = target_offset;
Chia-I Wu32a22462014-08-26 14:13:46 +0800215 reloc->flags = flags;
Chia-I Wucdff0592014-08-22 09:27:36 +0800216
217 cmd->reloc_used++;
218}
219
220/**
Chia-I Wu5da476a2014-12-10 08:50:28 +0800221 * Reserve a region from the state buffer. The offset, in bytes, to the
222 * reserved region is returned.
Chia-I Wu72292b72014-09-09 10:48:33 +0800223 *
224 * Note that \p alignment is in bytes and \p len is in DWords.
Chia-I Wue24c3292014-08-21 14:05:23 +0800225 */
Chia-I Wu5da476a2014-12-10 08:50:28 +0800226static inline uint32_t cmd_state_reserve(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800227 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600228 size_t alignment, uint32_t len)
Chia-I Wue24c3292014-08-21 14:05:23 +0800229{
Chia-I Wu72292b72014-09-09 10:48:33 +0800230 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600231 const size_t size = len << 2;
232 const size_t offset = cmd_writer_reserve(cmd, which, alignment, size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800233 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +0800234
Chia-I Wu72292b72014-09-09 10:48:33 +0800235 /* all states are at least aligned to 32-bytes */
236 assert(alignment % 32 == 0);
237
Chia-I Wu72292b72014-09-09 10:48:33 +0800238 writer->used = offset + size;
239
Chia-I Wu465fe212015-02-11 11:27:06 -0700240 if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG))
Chia-I Wu00b51a82014-09-09 12:07:37 +0800241 cmd_writer_record(cmd, which, item, offset, size);
242
Chia-I Wu72292b72014-09-09 10:48:33 +0800243 return offset;
Chia-I Wue24c3292014-08-21 14:05:23 +0800244}
245
246/**
Chia-I Wu5da476a2014-12-10 08:50:28 +0800247 * Get the pointer to a reserved region for updating. The pointer is only
248 * valid until the next reserve call.
249 */
250static inline void cmd_state_update(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600251 uint32_t offset, uint32_t len,
Chia-I Wu5da476a2014-12-10 08:50:28 +0800252 uint32_t **dw)
253{
254 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE;
255 struct intel_cmd_writer *writer = &cmd->writers[which];
256
257 assert(offset + (len << 2) <= writer->used);
258
259 *dw = (uint32_t *) ((char *) writer->ptr + offset);
260}
261
262/**
263 * Reserve a region from the state buffer. Both the offset, in bytes, and the
264 * pointer to the reserved region are returned. The pointer is only valid
265 * until the next reserve call.
266 *
267 * Note that \p alignment is in bytes and \p len is in DWords.
268 */
269static inline uint32_t cmd_state_pointer(struct intel_cmd *cmd,
270 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600271 size_t alignment, uint32_t len,
Chia-I Wu5da476a2014-12-10 08:50:28 +0800272 uint32_t **dw)
273{
274 const uint32_t offset = cmd_state_reserve(cmd, item, alignment, len);
275
276 cmd_state_update(cmd, offset, len, dw);
277
278 return offset;
279}
280
281/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800282 * Write a dynamic state to the state buffer.
Chia-I Wucdff0592014-08-22 09:27:36 +0800283 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800284static inline uint32_t cmd_state_write(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800285 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600286 size_t alignment, uint32_t len,
Chia-I Wu72292b72014-09-09 10:48:33 +0800287 const uint32_t *dw)
Chia-I Wucdff0592014-08-22 09:27:36 +0800288{
Chia-I Wu72292b72014-09-09 10:48:33 +0800289 uint32_t offset, *dst;
290
Chia-I Wu00b51a82014-09-09 12:07:37 +0800291 offset = cmd_state_pointer(cmd, item, alignment, len, &dst);
Chia-I Wu72292b72014-09-09 10:48:33 +0800292 memcpy(dst, dw, len << 2);
293
294 return offset;
Chia-I Wucdff0592014-08-22 09:27:36 +0800295}
296
297/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800298 * Write a surface state to the surface buffer. The offset, in bytes, of the
299 * state is returned.
300 *
301 * Note that \p alignment is in bytes and \p len is in DWords.
Chia-I Wue24c3292014-08-21 14:05:23 +0800302 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800303static inline uint32_t cmd_surface_write(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800304 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600305 size_t alignment, uint32_t len,
Chia-I Wu72292b72014-09-09 10:48:33 +0800306 const uint32_t *dw)
Chia-I Wue24c3292014-08-21 14:05:23 +0800307{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800308 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wuf98dd882015-02-10 04:17:47 +0800309 const size_t size = len << 2;
Chia-I Wu15cccf72015-02-10 04:07:40 +0800310 const uint32_t offset = cmd_writer_reserve(cmd, which, alignment, size);
311 struct intel_cmd_writer *writer = &cmd->writers[which];
312 uint32_t *dst;
313
Chia-I Wu00b51a82014-09-09 12:07:37 +0800314 assert(item == INTEL_CMD_ITEM_SURFACE ||
315 item == INTEL_CMD_ITEM_BINDING_TABLE);
316
Chia-I Wu15cccf72015-02-10 04:07:40 +0800317 /* all states are at least aligned to 32-bytes */
318 assert(alignment % 32 == 0);
319
320 writer->used = offset + size;
321
322 if (intel_debug & INTEL_DEBUG_BATCH)
323 cmd_writer_record(cmd, which, item, offset, size);
324
325 dst = (uint32_t *) ((char *) writer->ptr + offset);
326 memcpy(dst, dw, size);
327
328 return offset;
Chia-I Wue24c3292014-08-21 14:05:23 +0800329}
330
331/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800332 * Add a relocation entry for a DWord of a surface state.
Chia-I Wucdff0592014-08-22 09:27:36 +0800333 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800334static inline void cmd_surface_reloc(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600335 uint32_t offset, uint32_t dw_index,
Chia-I Wu72292b72014-09-09 10:48:33 +0800336 struct intel_bo *bo,
337 uint32_t bo_offset, uint32_t reloc_flags)
Chia-I Wucdff0592014-08-22 09:27:36 +0800338{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800339 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wucdff0592014-08-22 09:27:36 +0800340
Chia-I Wu72292b72014-09-09 10:48:33 +0800341 cmd_writer_reloc(cmd, which, offset + (dw_index << 2),
Chia-I Wud7d1e482014-10-18 13:25:10 +0800342 (intptr_t) bo, bo_offset, reloc_flags);
343}
344
345static inline void cmd_surface_reloc_writer(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600346 uint32_t offset, uint32_t dw_index,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800347 enum intel_cmd_writer_type writer,
348 uint32_t writer_offset)
349{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800350 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wud7d1e482014-10-18 13:25:10 +0800351
352 cmd_writer_reloc(cmd, which, offset + (dw_index << 2),
353 (intptr_t) writer, writer_offset,
354 INTEL_CMD_RELOC_TARGET_IS_WRITER);
Chia-I Wucdff0592014-08-22 09:27:36 +0800355}
356
357/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800358 * Write a kernel to the instruction buffer. The offset, in bytes, of the
359 * kernel is returned.
Chia-I Wue24c3292014-08-21 14:05:23 +0800360 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800361static inline uint32_t cmd_instruction_write(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600362 size_t size,
Chia-I Wu72292b72014-09-09 10:48:33 +0800363 const void *kernel)
Chia-I Wue24c3292014-08-21 14:05:23 +0800364{
Chia-I Wu72292b72014-09-09 10:48:33 +0800365 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_INSTRUCTION;
366 /*
367 * From the Sandy Bridge PRM, volume 4 part 2, page 112:
368 *
369 * "Due to prefetch of the instruction stream, the EUs may attempt to
370 * access up to 8 instructions (128 bytes) beyond the end of the
371 * kernel program - possibly into the next memory page. Although
372 * these instructions will not be executed, software must account for
373 * the prefetch in order to avoid invalid page access faults."
374 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600375 const size_t reserved_size = size + 128;
Chia-I Wu72292b72014-09-09 10:48:33 +0800376 /* kernels are aligned to 64 bytes */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600377 const size_t alignment = 64;
378 const size_t offset = cmd_writer_reserve(cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800379 which, alignment, reserved_size);
380 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +0800381
Chia-I Wu72292b72014-09-09 10:48:33 +0800382 memcpy((char *) writer->ptr + offset, kernel, size);
Chia-I Wu5e25c272014-08-21 20:19:12 +0800383
Chia-I Wu72292b72014-09-09 10:48:33 +0800384 writer->used = offset + size;
385
Chia-I Wu465fe212015-02-11 11:27:06 -0700386 if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG))
Chia-I Wu00b51a82014-09-09 12:07:37 +0800387 cmd_writer_record(cmd, which, INTEL_CMD_ITEM_KERNEL, offset, size);
388
Chia-I Wu72292b72014-09-09 10:48:33 +0800389 return offset;
390}
391
392/**
393 * Reserve a region from the batch buffer. Both the offset, in DWords, and
Chia-I Wu5da476a2014-12-10 08:50:28 +0800394 * the pointer to the reserved region are returned. The pointer is only valid
395 * until the next reserve call.
Chia-I Wu72292b72014-09-09 10:48:33 +0800396 *
397 * Note that \p len is in DWords.
398 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600399static inline uint32_t cmd_batch_pointer(struct intel_cmd *cmd,
400 uint32_t len, uint32_t **dw)
Chia-I Wu72292b72014-09-09 10:48:33 +0800401{
402 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
403 /*
404 * We know the batch bo is always aligned. Using 1 here should allow the
405 * compiler to optimize away aligning.
406 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600407 const size_t alignment = 1;
408 const size_t size = len << 2;
409 const size_t offset = cmd_writer_reserve(cmd, which, alignment, size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800410 struct intel_cmd_writer *writer = &cmd->writers[which];
411
412 assert(offset % 4 == 0);
413 *dw = (uint32_t *) ((char *) writer->ptr + offset);
414
415 writer->used = offset + size;
416
417 return offset >> 2;
418}
419
420/**
421 * Write a command to the batch buffer.
422 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600423static inline uint32_t cmd_batch_write(struct intel_cmd *cmd,
424 uint32_t len, const uint32_t *dw)
Chia-I Wu72292b72014-09-09 10:48:33 +0800425{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600426 uint32_t pos;
Chia-I Wu72292b72014-09-09 10:48:33 +0800427 uint32_t *dst;
428
429 pos = cmd_batch_pointer(cmd, len, &dst);
430 memcpy(dst, dw, len << 2);
431
432 return pos;
433}
434
435/**
436 * Add a relocation entry for a DWord of a command.
437 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600438static inline void cmd_batch_reloc(struct intel_cmd *cmd, uint32_t pos,
Chia-I Wu72292b72014-09-09 10:48:33 +0800439 struct intel_bo *bo,
440 uint32_t bo_offset, uint32_t reloc_flags)
441{
442 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
443
Chia-I Wud7d1e482014-10-18 13:25:10 +0800444 cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) bo, bo_offset, reloc_flags);
445}
446
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600447static inline void cmd_batch_reloc_writer(struct intel_cmd *cmd, uint32_t pos,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800448 enum intel_cmd_writer_type writer,
449 uint32_t writer_offset)
450{
451 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
452
453 cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) writer, writer_offset,
454 INTEL_CMD_RELOC_TARGET_IS_WRITER);
Chia-I Wue24c3292014-08-21 14:05:23 +0800455}
456
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800457void cmd_batch_state_base_address(struct intel_cmd *cmd);
Chia-I Wu7c853562015-02-27 14:35:08 -0700458void cmd_batch_push_const_alloc(struct intel_cmd *cmd);
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800459
Chia-I Wue24c3292014-08-21 14:05:23 +0800460/**
Chia-I Wu48c283d2014-08-25 23:13:46 +0800461 * Begin the batch buffer.
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800462 */
463static inline void cmd_batch_begin(struct intel_cmd *cmd)
464{
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800465 cmd_batch_state_base_address(cmd);
Chia-I Wu7c853562015-02-27 14:35:08 -0700466 cmd_batch_push_const_alloc(cmd);
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800467}
468
469/**
Chia-I Wue24c3292014-08-21 14:05:23 +0800470 * End the batch buffer.
471 */
472static inline void cmd_batch_end(struct intel_cmd *cmd)
473{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800474 struct intel_cmd_writer *writer = &cmd->writers[INTEL_CMD_WRITER_BATCH];
Chia-I Wu72292b72014-09-09 10:48:33 +0800475 uint32_t *dw;
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800476
Chia-I Wu72292b72014-09-09 10:48:33 +0800477 if (writer->used & 0x7) {
478 cmd_batch_pointer(cmd, 1, &dw);
479 dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
Chia-I Wue24c3292014-08-21 14:05:23 +0800480 } else {
Chia-I Wu72292b72014-09-09 10:48:33 +0800481 cmd_batch_pointer(cmd, 2, &dw);
482 dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
483 dw[1] = GEN6_MI_CMD(MI_NOOP);
Chia-I Wue24c3292014-08-21 14:05:23 +0800484 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800485}
486
Chia-I Wub5af7c52015-02-18 14:51:59 -0700487static inline void cmd_begin_render_pass(struct intel_cmd *cmd,
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600488 const struct intel_render_pass *rp,
489 const struct intel_fb *fb)
Chia-I Wub5af7c52015-02-18 14:51:59 -0700490{
Chia-I Wuc6025ac2015-02-18 14:59:11 -0700491 cmd->bind.render_pass = rp;
Chia-I Wubbc7d912015-02-27 14:59:50 -0700492 cmd->bind.render_pass_changed = true;
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600493 cmd->bind.fb = fb;
Chia-I Wub5af7c52015-02-18 14:51:59 -0700494}
495
496static inline void cmd_end_render_pass(struct intel_cmd *cmd,
497 const struct intel_render_pass *rp)
498{
499 //note what to do if rp != bound rp
500 cmd->bind.render_pass = 0;
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600501 cmd->bind.fb = 0;
Chia-I Wub5af7c52015-02-18 14:51:59 -0700502}
503
Chia-I Wu525c6602014-08-27 10:22:34 +0800504void cmd_batch_flush(struct intel_cmd *cmd, uint32_t pipe_control_dw0);
Chia-I Wu3fb47ce2014-10-28 11:19:36 +0800505void cmd_batch_flush_all(struct intel_cmd *cmd);
Chia-I Wu525c6602014-08-27 10:22:34 +0800506
Chia-I Wu759fa2e2014-08-30 18:44:47 +0800507void cmd_batch_depth_count(struct intel_cmd *cmd,
508 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600509 VkDeviceSize offset);
Chia-I Wu759fa2e2014-08-30 18:44:47 +0800510
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800511void cmd_batch_timestamp(struct intel_cmd *cmd,
512 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600513 VkDeviceSize offset);
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800514
515void cmd_batch_immediate(struct intel_cmd *cmd,
Mike Stroyan55658c22014-12-04 11:08:39 +0000516 uint32_t pipe_control_flags,
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800517 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600518 VkDeviceSize offset,
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800519 uint64_t val);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800520
Chia-I Wuc14d1562014-10-17 09:49:22 +0800521void cmd_draw_meta(struct intel_cmd *cmd, const struct intel_cmd_meta *meta);
522
Chia-I Wu73520ac2015-02-19 11:17:45 -0700523void cmd_meta_ds_op(struct intel_cmd *cmd,
524 enum intel_cmd_meta_ds_op op,
525 struct intel_img *img,
Courtney Goeltzenleuchter382489d2015-04-10 08:34:15 -0600526 const VkImageSubresourceRange *range);
Chia-I Wu73520ac2015-02-19 11:17:45 -0700527
Chris Forbesfff9bf42015-06-15 15:26:19 +1200528void cmd_meta_clear_color_image(
529 VkCmdBuffer cmdBuffer,
530 VkImage image,
531 VkImageLayout imageLayout,
532 const VkClearColor *pClearColor,
533 uint32_t rangeCount,
534 const VkImageSubresourceRange *pRanges);
535
Chia-I Wu00a23b22014-08-20 15:28:08 +0800536#endif /* CMD_PRIV_H */