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gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / 4d6a6dc9e3aeaa351ba6e8f88863e058fc61c5a6 / . / asoc / sa6155.c
blob: 6ed96e1f88791fd2ba92e16ca6df71198b2b6429 [file] [log] [blame]
Derek Chen4f941542020-01-13 14:37:40 -0800[diff] [blame]1/* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12/*
13 * Copyright 2011, The Android Open Source Project
14
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 * Redistributions of source code must retain the above copyright
18 notice, this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in the
21 documentation and/or other materials provided with the distribution.
22 * Neither the name of The Android Open Source Project nor the names of
23 its contributors may be used to endorse or promote products derived
24 from this software without specific prior written permission.
25
26 * THIS SOFTWARE IS PROVIDED BY The Android Open Source Project ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL The Android Open Source Project BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
36 * DAMAGE.
37 */
38
39#include <linux/clk.h>
40#include <linux/delay.h>
41#include <linux/gpio.h>
42#include <linux/of_gpio.h>
43#include <linux/platform_device.h>
44#include <linux/slab.h>
45#include <linux/io.h>
46#include <linux/module.h>
47#include <linux/input.h>
48#include <linux/of_device.h>
49#include <linux/pm_qos.h>
50#include <sound/core.h>
51#include <sound/soc.h>
52#include <sound/soc-dapm.h>
53#include <sound/pcm.h>
54#include <sound/pcm_params.h>
55#include <sound/info.h>
Erin Yan300664f2019-05-14 10:42:31 +0800[diff] [blame]56#include <soc/snd_event.h>
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]57#include <dsp/audio_notifier.h>
58#include <dsp/q6afe-v2.h>
59#include <dsp/q6core.h>
Derek Chen628c9952019-05-03 17:14:09 +0530[diff] [blame]60#include <soc/qcom/boot_stats.h>
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]61#include "device_event.h"
62#include "msm-pcm-routing-v2.h"
63
64#define DRV_NAME "sa6155-asoc-snd"
65
66#define __CHIPSET__ "SA6155 "
67#define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
68
69#define DEV_NAME_STR_LEN 32
70
71#define SAMPLING_RATE_8KHZ 8000
72#define SAMPLING_RATE_11P025KHZ 11025
73#define SAMPLING_RATE_16KHZ 16000
74#define SAMPLING_RATE_22P05KHZ 22050
75#define SAMPLING_RATE_32KHZ 32000
76#define SAMPLING_RATE_44P1KHZ 44100
77#define SAMPLING_RATE_48KHZ 48000
78#define SAMPLING_RATE_88P2KHZ 88200
79#define SAMPLING_RATE_96KHZ 96000
80#define SAMPLING_RATE_176P4KHZ 176400
81#define SAMPLING_RATE_192KHZ 192000
82#define SAMPLING_RATE_352P8KHZ 352800
83#define SAMPLING_RATE_384KHZ 384000
84
85#define ADSP_STATE_READY_TIMEOUT_MS 3000
86#define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
87
88enum {
89 PRIM_MI2S = 0,
90 SEC_MI2S,
91 TERT_MI2S,
92 QUAT_MI2S,
93 QUIN_MI2S,
94 MI2S_MAX,
95};
96
97enum {
98 PRIM_AUX_PCM = 0,
99 SEC_AUX_PCM,
100 TERT_AUX_PCM,
101 QUAT_AUX_PCM,
102 QUIN_AUX_PCM,
103 AUX_PCM_MAX,
104};
105
106struct mi2s_conf {
107 struct mutex lock;
108 u32 ref_cnt;
109 u32 msm_is_mi2s_master;
110};
111
112static u32 mi2s_ebit_clk[MI2S_MAX] = {
113 Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
114 Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
115 Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
116 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
117 Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
118};
119
120struct dev_config {
121 u32 sample_rate;
122 u32 bit_format;
123 u32 channels;
124};
125
126enum {
127 DP_RX_IDX = 0,
128 EXT_DISP_RX_IDX_MAX,
129};
130
131enum pinctrl_pin_state {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]132 STATE_SLEEP = 0, /* All pins are in sleep state */
133 STATE_ACTIVE, /* TDM = active */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]134};
135
136struct msm_pinctrl_info {
137 struct pinctrl *pinctrl;
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]138 struct pinctrl_state *sleep;
139 struct pinctrl_state *active;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]140 enum pinctrl_pin_state curr_state;
141};
142
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]143static const char *const pin_states[] = {"sleep", "active"};
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]144
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]145static const char *const tdm_gpio_phandle[] = {"qcom,pri-tdm-gpios",
146 "qcom,sec-tdm-gpios",
147 "qcom,tert-tdm-gpios",
148 "qcom,quat-tdm-gpios",
149 "qcom,quin-tdm-gpios"};
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]150
151enum {
152 TDM_0 = 0,
153 TDM_1,
154 TDM_2,
155 TDM_3,
156 TDM_4,
157 TDM_5,
158 TDM_6,
159 TDM_7,
160 TDM_PORT_MAX,
161};
162
163enum {
164 TDM_PRI = 0,
165 TDM_SEC,
166 TDM_TERT,
167 TDM_QUAT,
168 TDM_QUIN,
169 TDM_INTERFACE_MAX,
170};
171
172struct tdm_port {
173 u32 mode;
174 u32 channel;
175};
176
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]177struct tdm_conf {
178 struct mutex lock;
179 u32 ref_cnt;
180};
181
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]182/* TDM default config */
183static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
184 { /* PRI TDM */
Deru Wang5ab8cbd2020-03-25 13:20:06 +0800[diff] [blame]185 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
186 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
187 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_2 */
188 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_3 */
189 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
190 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
191 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
192 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]193 },
194 { /* SEC TDM */
195 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_0 */
196 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_1 */
197 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_2 */
198 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_3 */
199 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
200 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
201 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
202 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
203 },
204 { /* TERT TDM */
205 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* RX_0 */
206 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
207 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
208 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
209 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
210 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
211 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
212 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
213 },
214 { /* QUAT TDM */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]215 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8}, /* RX_0 */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame]216 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8}, /* RX_1 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]217 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
218 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
219 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
220 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
221 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
222 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
223 },
224 { /* QUIN TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame]225 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* RX_0 */
226 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
227 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
228 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]229 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
230 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
231 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
232 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
233 }
234};
235
236/* TDM default config */
237static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
238 { /* PRI TDM */
Deru Wang5ab8cbd2020-03-25 13:20:06 +0800[diff] [blame]239 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
240 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
241 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
242 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_3 */
243 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
244 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
245 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
246 {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]247 },
248 { /* SEC TDM */
249 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* TX_0 */
250 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
251 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
252 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
253 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
254 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
255 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
256 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
257 },
258 { /* TERT TDM */
259 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 4}, /* TX_0 */
260 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
261 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
262 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
263 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
264 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
265 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
266 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
267 },
268 { /* QUAT TDM */
Derek Chen4f941542020-01-13 14:37:40 -0800[diff] [blame]269 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8}, /* TX_0 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]270 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
271 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
272 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
273 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
274 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
275 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
276 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
277 },
278 { /* QUIN TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame]279 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 4}, /* TX_0 */
280 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
281 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]282 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
283 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
284 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
285 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
286 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
287 }
288};
289
290/* Default configuration of external display BE */
291static struct dev_config ext_disp_rx_cfg[] = {
292 [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
293};
294
295static struct dev_config usb_rx_cfg = {
296 .sample_rate = SAMPLING_RATE_48KHZ,
297 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
298 .channels = 2,
299};
300
301static struct dev_config usb_tx_cfg = {
302 .sample_rate = SAMPLING_RATE_48KHZ,
303 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
304 .channels = 1,
305};
306
307static struct dev_config proxy_rx_cfg = {
308 .sample_rate = SAMPLING_RATE_48KHZ,
309 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
310 .channels = 2,
311};
312
313/* Default configuration of MI2S channels */
314static struct dev_config mi2s_rx_cfg[] = {
315 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
316 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
317 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
318 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
319 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
320};
321
322static struct dev_config mi2s_tx_cfg[] = {
323 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
324 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
325 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
326 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
327 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
328};
329
330static struct dev_config aux_pcm_rx_cfg[] = {
331 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
332 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
333 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
334 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
335 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
336};
337
338static struct dev_config aux_pcm_tx_cfg[] = {
339 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
340 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
341 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
342 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
343 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
344};
345
346/* TDM default slot config */
347struct tdm_slot_cfg {
348 u32 width;
349 u32 num;
350};
351
352static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = {
353 /* PRI TDM */
Deru Wang5ab8cbd2020-03-25 13:20:06 +0800[diff] [blame]354 {16, 16},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]355 /* SEC TDM */
356 {32, 8},
357 /* TERT TDM */
358 {32, 8},
359 /* QUAT TDM */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]360 {32, 16},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]361 /* QUIN TDM */
362 {32, 8}
363};
364
365/*****************************************************************************
366* TO BE UPDATED: Codec/Platform specific tdm slot table
367*****************************************************************************/
368static struct tdm_slot_cfg tdm_slot_custom[TDM_INTERFACE_MAX] = {
369 /* PRI TDM */
370 {16, 16},
371 /* SEC TDM */
372 {16, 16},
373 /* TERT TDM */
374 {16, 16},
375 /* QUAT TDM */
376 {16, 16},
377 /* QUIN TDM */
378 {16, 16}
379};
380
381
382/* TDM default slot offset config */
383#define TDM_SLOT_OFFSET_MAX 32
384
385static unsigned int tdm_rx_slot_offset
386 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
387 {/* PRI TDM */
Deru Wang5ab8cbd2020-03-25 13:20:06 +0800[diff] [blame]388 {0, 0xFFFF},
389 {2, 0xFFFF},
390 {4, 6, 0xFFFF},
391 {8, 10, 0xFFFF},
392 {12, 14, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]393 {0xFFFF}, /* not used */
394 {0xFFFF}, /* not used */
395 {0xFFFF}, /* not used */
396 },
397 {/* SEC TDM */
398 {0, 4, 0xFFFF},
399 {8, 12, 0xFFFF},
400 {16, 20, 0xFFFF},
401 {24, 28, 0xFFFF},
402 {0xFFFF}, /* not used */
403 {0xFFFF}, /* not used */
404 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]405 {28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]406 },
407 {/* TERT TDM */
408 {0, 4, 8, 12, 16, 20, 0xFFFF},
409 {24, 0xFFFF},
410 {28, 0xFFFF},
411 {0xFFFF}, /* not used */
412 {0xFFFF}, /* not used */
413 {0xFFFF}, /* not used */
414 {0xFFFF}, /* not used */
415 {0xFFFF}, /* not used */
416 },
417 {/* QUAT TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame]418 {0, 8, 16, 24, 32, 40, 48, 56, 0xFFFF}, /*8 CH SPKR*/
419 {4, 12, 20, 28, 36, 44, 52, 60, 0xFFFF}, /*8 CH SPKR*/
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]420 {0xFFFF}, /* not used */
421 {0xFFFF}, /* not used */
422 {0xFFFF}, /* not used */
423 {0xFFFF}, /* not used */
424 {0xFFFF}, /* not used */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame]425 {60,0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]426 },
427 {/* QUIN TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame]428 {0, 4, 8, 12, 16, 20, 0xFFFF},
429 {24, 0xFFFF},
430 {28, 0xFFFF},
431 {0xFFFF}, /* not used */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]432 {0xFFFF}, /* not used */
433 {0xFFFF}, /* not used */
434 {0xFFFF}, /* not used */
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]435 {28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]436 }
437};
438
439static unsigned int tdm_tx_slot_offset
440 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
441 {/* PRI TDM */
Deru Wang5ab8cbd2020-03-25 13:20:06 +0800[diff] [blame]442 {0, 0xFFFF},
443 {2, 0xFFFF},
444 {4, 6, 0xFFFF},
445 {8, 10, 0xFFFF},
446 {12, 14, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]447 {0xFFFF}, /* not used */
448 {0xFFFF}, /* not used */
449 {0xFFFF}, /* not used */
450 },
451 {/* SEC TDM */
452 {0, 4, 8, 12, 16, 20, 0xFFFF},
453 {24, 0xFFFF},
454 {28, 0xFFFF},
455 {0xFFFF}, /* not used */
456 {0xFFFF}, /* not used */
457 {0xFFFF}, /* not used */
458 {0xFFFF}, /* not used */
459 {0xFFFF}, /* not used */
460 },
461 {/* TERT TDM */
462 {0, 4, 8, 12, 0xFFFF},
463 {16, 20, 0xFFFF},
464 {24, 28, 0xFFFF},
465 {0xFFFF}, /* not used */
466 {0xFFFF}, /* not used */
467 {0xFFFF}, /* not used */
468 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]469 {28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]470 },
471 {/* QUAT TDM */
Derek Chen4f941542020-01-13 14:37:40 -0800[diff] [blame]472 {0, 8, 16, 24, 4, 12, 20, 28, 0xFFFF}, /*8 CH MIC ARR*/
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]473 {0xFFFF}, /* not used */
474 {0xFFFF}, /* not used */
475 {0xFFFF}, /* not used */
476 {0xFFFF}, /* not used */
477 {0xFFFF}, /* not used */
478 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]479 {60,0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]480 },
481 {/* QUIN TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame]482 {0, 4, 8, 12, 0xFFFF},
483 {16, 20, 0xFFFF},
484 {24, 28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]485 {0xFFFF}, /* not used */
486 {0xFFFF}, /* not used */
487 {0xFFFF}, /* not used */
488 {0xFFFF}, /* not used */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame]489 {28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]490 }
491};
492
493/*****************************************************************************
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]494* TO BE UPDATED: Codec/Platform specific tdm slot offset table
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]495* NOTE:
496* Each entry represents the slot offset array of one backend tdm device
497* valid offset represents the starting offset in byte for the channel
498* use 0xFFFF for end or unused slot offset entry.
499*****************************************************************************/
500static unsigned int tdm_rx_slot_offset_custom
501 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
502 {/* PRI TDM */
503 {0xFFFF}, /* not used */
504 {0xFFFF}, /* not used */
505 {0xFFFF}, /* not used */
506 {0xFFFF}, /* not used */
507 {0xFFFF}, /* not used */
508 {0xFFFF}, /* not used */
509 {0xFFFF}, /* not used */
510 {0xFFFF}, /* not used */
511 },
512 {/* SEC TDM */
513 {0, 2, 0xFFFF},
514 {4, 0xFFFF},
515 {6, 0xFFFF},
516 {8, 0xFFFF},
517 {10, 0xFFFF},
518 {12, 14, 16, 18, 20, 22, 24, 26, 0xFFFF},
519 {28, 30, 0xFFFF},
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]520 {30, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]521 },
522 {/* TERT TDM */
523 {0, 2, 0xFFFF},
524 {4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
525 {20, 22, 24, 26, 28, 30, 0xFFFF},
526 {0xFFFF}, /* not used */
527 {0xFFFF}, /* not used */
528 {0xFFFF}, /* not used */
529 {0xFFFF}, /* not used */
530 {0xFFFF}, /* not used */
531 },
532 {/* QUAT TDM */
533 {0xFFFF}, /* not used */
534 {0xFFFF}, /* not used */
535 {0xFFFF}, /* not used */
536 {0xFFFF}, /* not used */
537 {0xFFFF}, /* not used */
538 {0xFFFF}, /* not used */
539 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]540 {0, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]541 },
542 {/* QUIN TDM */
543 {0xFFFF}, /* not used */
544 {0xFFFF}, /* not used */
545 {0xFFFF}, /* not used */
546 {0xFFFF}, /* not used */
547 {0xFFFF}, /* not used */
548 {0xFFFF}, /* not used */
549 {0xFFFF}, /* not used */
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]550 {0, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]551 }
552};
553
554static unsigned int tdm_tx_slot_offset_custom
555 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
556 {/* PRI TDM */
557 {0xFFFF}, /* not used */
558 {0xFFFF}, /* not used */
559 {0xFFFF}, /* not used */
560 {0xFFFF}, /* not used */
561 {0xFFFF}, /* not used */
562 {0xFFFF}, /* not used */
563 {0xFFFF}, /* not used */
564 {0xFFFF}, /* not used */
565 },
566 {/* SEC TDM */
567 {0, 2, 0xFFFF},
568 {4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
569 {20, 22, 24, 26, 28, 30, 0xFFFF},
570 {0xFFFF}, /* not used */
571 {0xFFFF}, /* not used */
572 {0xFFFF}, /* not used */
573 {0xFFFF}, /* not used */
574 {0xFFFF}, /* not used */
575 },
576 {/* TERT TDM */
577 {0, 2, 4, 6, 8, 10, 12, 0xFFFF},
578 {14, 16, 0xFFFF},
579 {18, 20, 22, 24, 26, 28, 30, 0xFFFF},
580 {0xFFFF}, /* not used */
581 {0xFFFF}, /* not used */
582 {0xFFFF}, /* not used */
583 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]584 {30, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]585 },
586 {/* QUAT TDM */
587 {0xFFFF}, /* not used */
588 {0xFFFF}, /* not used */
589 {0xFFFF}, /* not used */
590 {0xFFFF}, /* not used */
591 {0xFFFF}, /* not used */
592 {0xFFFF}, /* not used */
593 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]594 {0, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]595 },
596 {/* QUIN TDM */
597 {0xFFFF}, /* not used */
598 {0xFFFF}, /* not used */
599 {0xFFFF}, /* not used */
600 {0xFFFF}, /* not used */
601 {0xFFFF}, /* not used */
602 {0xFFFF}, /* not used */
603 {0xFFFF}, /* not used */
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]604 {0, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]605 }
606};
607
608
609static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
610 "S32_LE"};
611static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
612 "S24_3LE"};
613static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
614 "Five", "Six", "Seven",
615 "Eight"};
616static char const *ch_text[] = {"Two", "Three", "Four", "Five",
617 "Six", "Seven", "Eight"};
618static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
619 "KHZ_16", "KHZ_22P05",
620 "KHZ_32", "KHZ_44P1", "KHZ_48",
621 "KHZ_88P2", "KHZ_96", "KHZ_176P4",
622 "KHZ_192", "KHZ_352P8", "KHZ_384"};
623static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
624 "KHZ_192", "KHZ_32", "KHZ_44P1",
625 "KHZ_88P2", "KHZ_176P4"};
626static char const *tdm_ch_text[] = {
627 "One", "Two", "Three", "Four",
628 "Five", "Six", "Seven", "Eight",
629 "Nine", "Ten", "Eleven", "Twelve",
630 "Thirteen", "Fourteen", "Fifteen", "Sixteen",
631 "Seventeen", "Eighteen", "Nineteen", "Twenty",
632 "TwentyOne", "TwentyTwo", "TwentyThree", "TwentyFour",
633 "TwentyFive", "TwentySix", "TwentySeven", "TwentyEight",
634 "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo"};
635static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
636static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
637 "KHZ_48", "KHZ_176P4",
638 "KHZ_352P8"};
639static const char *const tdm_slot_num_text[] = {"One", "Two", "Four",
640 "Eight", "Sixteen", "ThirtyTwo"};
641static const char *const tdm_slot_width_text[] = {"16", "24", "32"};
642static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
643static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
644 "KHZ_22P05", "KHZ_32", "KHZ_44P1",
645 "KHZ_48", "KHZ_96", "KHZ_192"};
646static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
647 "Five", "Six", "Seven",
648 "Eight"};
649static const char *const qos_text[] = {"Disable", "Enable"};
650
651static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
652static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
653static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
654static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
655static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
656static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
657static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
658static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
659static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
660static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
661 ext_disp_sample_rate_text);
662static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
663static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
664static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
665static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
666static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
667static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
668static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text);
669static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text);
670static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
671static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
672static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
673static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
674static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
675static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
676static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
677static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
678static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
679static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
680static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
681static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
682static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
683static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
684static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
685static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
686static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
687static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
688static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
689static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
690static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
691static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
692static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
693static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
694static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
695static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
696static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
697static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
698static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
699static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
700static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
701static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
702static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
703static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
704
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]705static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
706 {
707 AFE_API_VERSION_I2S_CONFIG,
708 Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
709 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
710 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
711 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
712 0,
713 },
714 {
715 AFE_API_VERSION_I2S_CONFIG,
716 Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
717 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
718 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
719 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
720 0,
721 },
722 {
723 AFE_API_VERSION_I2S_CONFIG,
724 Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
725 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
726 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
727 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
728 0,
729 },
730 {
731 AFE_API_VERSION_I2S_CONFIG,
732 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
733 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
734 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
735 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
736 0,
737 },
738 {
739 AFE_API_VERSION_I2S_CONFIG,
740 Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
741 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
742 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
743 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
744 0,
745 }
746
747};
748
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]749struct msm_asoc_mach_data {
750 struct msm_pinctrl_info pinctrl_info[TDM_INTERFACE_MAX];
751 struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
752 struct tdm_conf tdm_intf_conf[TDM_INTERFACE_MAX];
753};
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]754
755static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
756 struct snd_ctl_elem_value *ucontrol)
757{
758 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
759 usb_rx_cfg.channels);
760 ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
761 return 0;
762}
763
764static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
765 struct snd_ctl_elem_value *ucontrol)
766{
767 usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
768
769 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
770 return 1;
771}
772
773static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
774 struct snd_ctl_elem_value *ucontrol)
775{
776 int sample_rate_val;
777
778 switch (usb_rx_cfg.sample_rate) {
779 case SAMPLING_RATE_384KHZ:
780 sample_rate_val = 12;
781 break;
782 case SAMPLING_RATE_352P8KHZ:
783 sample_rate_val = 11;
784 break;
785 case SAMPLING_RATE_192KHZ:
786 sample_rate_val = 10;
787 break;
788 case SAMPLING_RATE_176P4KHZ:
789 sample_rate_val = 9;
790 break;
791 case SAMPLING_RATE_96KHZ:
792 sample_rate_val = 8;
793 break;
794 case SAMPLING_RATE_88P2KHZ:
795 sample_rate_val = 7;
796 break;
797 case SAMPLING_RATE_48KHZ:
798 sample_rate_val = 6;
799 break;
800 case SAMPLING_RATE_44P1KHZ:
801 sample_rate_val = 5;
802 break;
803 case SAMPLING_RATE_32KHZ:
804 sample_rate_val = 4;
805 break;
806 case SAMPLING_RATE_22P05KHZ:
807 sample_rate_val = 3;
808 break;
809 case SAMPLING_RATE_16KHZ:
810 sample_rate_val = 2;
811 break;
812 case SAMPLING_RATE_11P025KHZ:
813 sample_rate_val = 1;
814 break;
815 case SAMPLING_RATE_8KHZ:
816 default:
817 sample_rate_val = 0;
818 break;
819 }
820
821 ucontrol->value.integer.value[0] = sample_rate_val;
822 pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
823 usb_rx_cfg.sample_rate);
824 return 0;
825}
826
827static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
828 struct snd_ctl_elem_value *ucontrol)
829{
830 switch (ucontrol->value.integer.value[0]) {
831 case 12:
832 usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
833 break;
834 case 11:
835 usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
836 break;
837 case 10:
838 usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
839 break;
840 case 9:
841 usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
842 break;
843 case 8:
844 usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
845 break;
846 case 7:
847 usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
848 break;
849 case 6:
850 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
851 break;
852 case 5:
853 usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
854 break;
855 case 4:
856 usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
857 break;
858 case 3:
859 usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
860 break;
861 case 2:
862 usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
863 break;
864 case 1:
865 usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
866 break;
867 case 0:
868 usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
869 break;
870 default:
871 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
872 break;
873 }
874
875 pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
876 __func__, ucontrol->value.integer.value[0],
877 usb_rx_cfg.sample_rate);
878 return 0;
879}
880
881static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
882 struct snd_ctl_elem_value *ucontrol)
883{
884 switch (usb_rx_cfg.bit_format) {
885 case SNDRV_PCM_FORMAT_S32_LE:
886 ucontrol->value.integer.value[0] = 3;
887 break;
888 case SNDRV_PCM_FORMAT_S24_3LE:
889 ucontrol->value.integer.value[0] = 2;
890 break;
891 case SNDRV_PCM_FORMAT_S24_LE:
892 ucontrol->value.integer.value[0] = 1;
893 break;
894 case SNDRV_PCM_FORMAT_S16_LE:
895 default:
896 ucontrol->value.integer.value[0] = 0;
897 break;
898 }
899
900 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
901 __func__, usb_rx_cfg.bit_format,
902 ucontrol->value.integer.value[0]);
903 return 0;
904}
905
906static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
907 struct snd_ctl_elem_value *ucontrol)
908{
909 int rc = 0;
910
911 switch (ucontrol->value.integer.value[0]) {
912 case 3:
913 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
914 break;
915 case 2:
916 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
917 break;
918 case 1:
919 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
920 break;
921 case 0:
922 default:
923 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
924 break;
925 }
926 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
927 __func__, usb_rx_cfg.bit_format,
928 ucontrol->value.integer.value[0]);
929
930 return rc;
931}
932
933static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
934 struct snd_ctl_elem_value *ucontrol)
935{
936 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
937 usb_tx_cfg.channels);
938 ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
939 return 0;
940}
941
942static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
943 struct snd_ctl_elem_value *ucontrol)
944{
945 usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
946
947 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
948 return 1;
949}
950
951static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
952 struct snd_ctl_elem_value *ucontrol)
953{
954 int sample_rate_val;
955
956 switch (usb_tx_cfg.sample_rate) {
957 case SAMPLING_RATE_384KHZ:
958 sample_rate_val = 12;
959 break;
960 case SAMPLING_RATE_352P8KHZ:
961 sample_rate_val = 11;
962 break;
963 case SAMPLING_RATE_192KHZ:
964 sample_rate_val = 10;
965 break;
966 case SAMPLING_RATE_176P4KHZ:
967 sample_rate_val = 9;
968 break;
969 case SAMPLING_RATE_96KHZ:
970 sample_rate_val = 8;
971 break;
972 case SAMPLING_RATE_88P2KHZ:
973 sample_rate_val = 7;
974 break;
975 case SAMPLING_RATE_48KHZ:
976 sample_rate_val = 6;
977 break;
978 case SAMPLING_RATE_44P1KHZ:
979 sample_rate_val = 5;
980 break;
981 case SAMPLING_RATE_32KHZ:
982 sample_rate_val = 4;
983 break;
984 case SAMPLING_RATE_22P05KHZ:
985 sample_rate_val = 3;
986 break;
987 case SAMPLING_RATE_16KHZ:
988 sample_rate_val = 2;
989 break;
990 case SAMPLING_RATE_11P025KHZ:
991 sample_rate_val = 1;
992 break;
993 case SAMPLING_RATE_8KHZ:
994 sample_rate_val = 0;
995 break;
996 default:
997 sample_rate_val = 6;
998 break;
999 }
1000
1001 ucontrol->value.integer.value[0] = sample_rate_val;
1002 pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
1003 usb_tx_cfg.sample_rate);
1004 return 0;
1005}
1006
1007static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1008 struct snd_ctl_elem_value *ucontrol)
1009{
1010 switch (ucontrol->value.integer.value[0]) {
1011 case 12:
1012 usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
1013 break;
1014 case 11:
1015 usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
1016 break;
1017 case 10:
1018 usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
1019 break;
1020 case 9:
1021 usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
1022 break;
1023 case 8:
1024 usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
1025 break;
1026 case 7:
1027 usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
1028 break;
1029 case 6:
1030 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1031 break;
1032 case 5:
1033 usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
1034 break;
1035 case 4:
1036 usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
1037 break;
1038 case 3:
1039 usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
1040 break;
1041 case 2:
1042 usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
1043 break;
1044 case 1:
1045 usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
1046 break;
1047 case 0:
1048 usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
1049 break;
1050 default:
1051 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1052 break;
1053 }
1054
1055 pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
1056 __func__, ucontrol->value.integer.value[0],
1057 usb_tx_cfg.sample_rate);
1058 return 0;
1059}
1060
1061static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
1062 struct snd_ctl_elem_value *ucontrol)
1063{
1064 switch (usb_tx_cfg.bit_format) {
1065 case SNDRV_PCM_FORMAT_S32_LE:
1066 ucontrol->value.integer.value[0] = 3;
1067 break;
1068 case SNDRV_PCM_FORMAT_S24_3LE:
1069 ucontrol->value.integer.value[0] = 2;
1070 break;
1071 case SNDRV_PCM_FORMAT_S24_LE:
1072 ucontrol->value.integer.value[0] = 1;
1073 break;
1074 case SNDRV_PCM_FORMAT_S16_LE:
1075 default:
1076 ucontrol->value.integer.value[0] = 0;
1077 break;
1078 }
1079
1080 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
1081 __func__, usb_tx_cfg.bit_format,
1082 ucontrol->value.integer.value[0]);
1083 return 0;
1084}
1085
1086static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
1087 struct snd_ctl_elem_value *ucontrol)
1088{
1089 int rc = 0;
1090
1091 switch (ucontrol->value.integer.value[0]) {
1092 case 3:
1093 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
1094 break;
1095 case 2:
1096 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1097 break;
1098 case 1:
1099 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
1100 break;
1101 case 0:
1102 default:
1103 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
1104 break;
1105 }
1106 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
1107 __func__, usb_tx_cfg.bit_format,
1108 ucontrol->value.integer.value[0]);
1109
1110 return rc;
1111}
1112
1113static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
1114{
1115 int idx = 0;
1116
1117 if (strnstr(kcontrol->id.name, "Display Port RX",
1118 sizeof("Display Port RX"))) {
1119 idx = DP_RX_IDX;
1120 } else {
1121 pr_err("%s: unsupported BE: %s\n",
1122 __func__, kcontrol->id.name);
1123 idx = -EINVAL;
1124 }
1125
1126 return idx;
1127}
1128
1129static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
1130 struct snd_ctl_elem_value *ucontrol)
1131{
1132 int idx = ext_disp_get_port_idx(kcontrol);
1133
1134 if (idx < 0)
1135 return idx;
1136
1137 switch (ext_disp_rx_cfg[idx].bit_format) {
1138 case SNDRV_PCM_FORMAT_S24_3LE:
1139 ucontrol->value.integer.value[0] = 2;
1140 break;
1141 case SNDRV_PCM_FORMAT_S24_LE:
1142 ucontrol->value.integer.value[0] = 1;
1143 break;
1144 case SNDRV_PCM_FORMAT_S16_LE:
1145 default:
1146 ucontrol->value.integer.value[0] = 0;
1147 break;
1148 }
1149
1150 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
1151 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
1152 ucontrol->value.integer.value[0]);
1153 return 0;
1154}
1155
1156static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
1157 struct snd_ctl_elem_value *ucontrol)
1158{
1159 int idx = ext_disp_get_port_idx(kcontrol);
1160
1161 if (idx < 0)
1162 return idx;
1163
1164 switch (ucontrol->value.integer.value[0]) {
1165 case 2:
1166 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1167 break;
1168 case 1:
1169 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
1170 break;
1171 case 0:
1172 default:
1173 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
1174 break;
1175 }
1176 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
1177 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
1178 ucontrol->value.integer.value[0]);
1179
1180 return 0;
1181}
1182
1183static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
1184 struct snd_ctl_elem_value *ucontrol)
1185{
1186 int idx = ext_disp_get_port_idx(kcontrol);
1187
1188 if (idx < 0)
1189 return idx;
1190
1191 ucontrol->value.integer.value[0] =
1192 ext_disp_rx_cfg[idx].channels - 2;
1193
1194 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
1195 idx, ext_disp_rx_cfg[idx].channels);
1196
1197 return 0;
1198}
1199
1200static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
1201 struct snd_ctl_elem_value *ucontrol)
1202{
1203 int idx = ext_disp_get_port_idx(kcontrol);
1204
1205 if (idx < 0)
1206 return idx;
1207
1208 ext_disp_rx_cfg[idx].channels =
1209 ucontrol->value.integer.value[0] + 2;
1210
1211 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
1212 idx, ext_disp_rx_cfg[idx].channels);
1213 return 1;
1214}
1215
1216static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1217 struct snd_ctl_elem_value *ucontrol)
1218{
1219 int sample_rate_val;
1220 int idx = ext_disp_get_port_idx(kcontrol);
1221
1222 if (idx < 0)
1223 return idx;
1224
1225 switch (ext_disp_rx_cfg[idx].sample_rate) {
1226 case SAMPLING_RATE_176P4KHZ:
1227 sample_rate_val = 6;
1228 break;
1229
1230 case SAMPLING_RATE_88P2KHZ:
1231 sample_rate_val = 5;
1232 break;
1233
1234 case SAMPLING_RATE_44P1KHZ:
1235 sample_rate_val = 4;
1236 break;
1237
1238 case SAMPLING_RATE_32KHZ:
1239 sample_rate_val = 3;
1240 break;
1241
1242 case SAMPLING_RATE_192KHZ:
1243 sample_rate_val = 2;
1244 break;
1245
1246 case SAMPLING_RATE_96KHZ:
1247 sample_rate_val = 1;
1248 break;
1249
1250 case SAMPLING_RATE_48KHZ:
1251 default:
1252 sample_rate_val = 0;
1253 break;
1254 }
1255
1256 ucontrol->value.integer.value[0] = sample_rate_val;
1257 pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
1258 idx, ext_disp_rx_cfg[idx].sample_rate);
1259
1260 return 0;
1261}
1262
1263static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1264 struct snd_ctl_elem_value *ucontrol)
1265{
1266 int idx = ext_disp_get_port_idx(kcontrol);
1267
1268 if (idx < 0)
1269 return idx;
1270
1271 switch (ucontrol->value.integer.value[0]) {
1272 case 6:
1273 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
1274 break;
1275 case 5:
1276 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
1277 break;
1278 case 4:
1279 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
1280 break;
1281 case 3:
1282 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
1283 break;
1284 case 2:
1285 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
1286 break;
1287 case 1:
1288 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
1289 break;
1290 case 0:
1291 default:
1292 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
1293 break;
1294 }
1295
1296 pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
1297 __func__, ucontrol->value.integer.value[0], idx,
1298 ext_disp_rx_cfg[idx].sample_rate);
1299 return 0;
1300}
1301
1302static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
1303 struct snd_ctl_elem_value *ucontrol)
1304{
1305 pr_debug("%s: proxy_rx channels = %d\n",
1306 __func__, proxy_rx_cfg.channels);
1307 ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
1308
1309 return 0;
1310}
1311
1312static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
1313 struct snd_ctl_elem_value *ucontrol)
1314{
1315 proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
1316 pr_debug("%s: proxy_rx channels = %d\n",
1317 __func__, proxy_rx_cfg.channels);
1318
1319 return 1;
1320}
1321
1322static int tdm_get_sample_rate(int value)
1323{
1324 int sample_rate = 0;
1325
1326 switch (value) {
1327 case 0:
1328 sample_rate = SAMPLING_RATE_8KHZ;
1329 break;
1330 case 1:
1331 sample_rate = SAMPLING_RATE_16KHZ;
1332 break;
1333 case 2:
1334 sample_rate = SAMPLING_RATE_32KHZ;
1335 break;
1336 case 3:
1337 sample_rate = SAMPLING_RATE_48KHZ;
1338 break;
1339 case 4:
1340 sample_rate = SAMPLING_RATE_176P4KHZ;
1341 break;
1342 case 5:
1343 sample_rate = SAMPLING_RATE_352P8KHZ;
1344 break;
1345 default:
1346 sample_rate = SAMPLING_RATE_48KHZ;
1347 break;
1348 }
1349 return sample_rate;
1350}
1351
1352static int aux_pcm_get_sample_rate(int value)
1353{
1354 int sample_rate;
1355
1356 switch (value) {
1357 case 1:
1358 sample_rate = SAMPLING_RATE_16KHZ;
1359 break;
1360 case 0:
1361 default:
1362 sample_rate = SAMPLING_RATE_8KHZ;
1363 break;
1364 }
1365 return sample_rate;
1366}
1367
1368static int tdm_get_sample_rate_val(int sample_rate)
1369{
1370 int sample_rate_val = 0;
1371
1372 switch (sample_rate) {
1373 case SAMPLING_RATE_8KHZ:
1374 sample_rate_val = 0;
1375 break;
1376 case SAMPLING_RATE_16KHZ:
1377 sample_rate_val = 1;
1378 break;
1379 case SAMPLING_RATE_32KHZ:
1380 sample_rate_val = 2;
1381 break;
1382 case SAMPLING_RATE_48KHZ:
1383 sample_rate_val = 3;
1384 break;
1385 case SAMPLING_RATE_176P4KHZ:
1386 sample_rate_val = 4;
1387 break;
1388 case SAMPLING_RATE_352P8KHZ:
1389 sample_rate_val = 5;
1390 break;
1391 default:
1392 sample_rate_val = 3;
1393 break;
1394 }
1395 return sample_rate_val;
1396}
1397
1398static int aux_pcm_get_sample_rate_val(int sample_rate)
1399{
1400 int sample_rate_val = 0;
1401
1402 switch (sample_rate) {
1403 case SAMPLING_RATE_16KHZ:
1404 sample_rate_val = 1;
1405 break;
1406 case SAMPLING_RATE_8KHZ:
1407 default:
1408 sample_rate_val = 0;
1409 break;
1410 }
1411 return sample_rate_val;
1412}
1413
1414static int tdm_get_mode(struct snd_kcontrol *kcontrol)
1415{
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]1416 int mode = -EINVAL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1417
1418 if (strnstr(kcontrol->id.name, "PRI",
1419 sizeof(kcontrol->id.name))) {
1420 mode = TDM_PRI;
1421 } else if (strnstr(kcontrol->id.name, "SEC",
1422 sizeof(kcontrol->id.name))) {
1423 mode = TDM_SEC;
1424 } else if (strnstr(kcontrol->id.name, "TERT",
1425 sizeof(kcontrol->id.name))) {
1426 mode = TDM_TERT;
1427 } else if (strnstr(kcontrol->id.name, "QUAT",
1428 sizeof(kcontrol->id.name))) {
1429 mode = TDM_QUAT;
1430 } else if (strnstr(kcontrol->id.name, "QUIN",
1431 sizeof(kcontrol->id.name))) {
1432 mode = TDM_QUIN;
1433 } else {
1434 pr_err("%s: unsupported mode in: %s",
1435 __func__, kcontrol->id.name);
1436 mode = -EINVAL;
1437 }
1438
1439 return mode;
1440}
1441
1442static int tdm_get_channel(struct snd_kcontrol *kcontrol)
1443{
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]1444 int channel = -EINVAL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1445
1446 if (strnstr(kcontrol->id.name, "RX_0",
1447 sizeof(kcontrol->id.name)) ||
1448 strnstr(kcontrol->id.name, "TX_0",
1449 sizeof(kcontrol->id.name))) {
1450 channel = TDM_0;
1451 } else if (strnstr(kcontrol->id.name, "RX_1",
1452 sizeof(kcontrol->id.name)) ||
1453 strnstr(kcontrol->id.name, "TX_1",
1454 sizeof(kcontrol->id.name))) {
1455 channel = TDM_1;
1456 } else if (strnstr(kcontrol->id.name, "RX_2",
1457 sizeof(kcontrol->id.name)) ||
1458 strnstr(kcontrol->id.name, "TX_2",
1459 sizeof(kcontrol->id.name))) {
1460 channel = TDM_2;
1461 } else if (strnstr(kcontrol->id.name, "RX_3",
1462 sizeof(kcontrol->id.name)) ||
1463 strnstr(kcontrol->id.name, "TX_3",
1464 sizeof(kcontrol->id.name))) {
1465 channel = TDM_3;
1466 } else if (strnstr(kcontrol->id.name, "RX_4",
1467 sizeof(kcontrol->id.name)) ||
1468 strnstr(kcontrol->id.name, "TX_4",
1469 sizeof(kcontrol->id.name))) {
1470 channel = TDM_4;
1471 } else if (strnstr(kcontrol->id.name, "RX_5",
1472 sizeof(kcontrol->id.name)) ||
1473 strnstr(kcontrol->id.name, "TX_5",
1474 sizeof(kcontrol->id.name))) {
1475 channel = TDM_5;
1476 } else if (strnstr(kcontrol->id.name, "RX_6",
1477 sizeof(kcontrol->id.name)) ||
1478 strnstr(kcontrol->id.name, "TX_6",
1479 sizeof(kcontrol->id.name))) {
1480 channel = TDM_6;
1481 } else if (strnstr(kcontrol->id.name, "RX_7",
1482 sizeof(kcontrol->id.name)) ||
1483 strnstr(kcontrol->id.name, "TX_7",
1484 sizeof(kcontrol->id.name))) {
1485 channel = TDM_7;
1486 } else {
1487 pr_err("%s: unsupported channel in: %s",
1488 __func__, kcontrol->id.name);
1489 channel = -EINVAL;
1490 }
1491
1492 return channel;
1493}
1494
1495static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
1496 struct tdm_port *port)
1497{
1498 if (port) {
1499 port->mode = tdm_get_mode(kcontrol);
1500 if (port->mode < 0)
1501 return port->mode;
1502
1503 port->channel = tdm_get_channel(kcontrol);
1504 if (port->channel < 0)
1505 return port->channel;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]1506 } else
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1507 return -EINVAL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1508 return 0;
1509}
1510
1511static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1512 struct snd_ctl_elem_value *ucontrol)
1513{
1514 struct tdm_port port;
1515 int ret = tdm_get_port_idx(kcontrol, &port);
1516
1517 if (ret) {
1518 pr_err("%s: unsupported control: %s\n",
1519 __func__, kcontrol->id.name);
1520 } else {
1521 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1522 tdm_rx_cfg[port.mode][port.channel].sample_rate);
1523
1524 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1525 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1526 ucontrol->value.enumerated.item[0]);
1527 }
1528 return ret;
1529}
1530
1531static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1532 struct snd_ctl_elem_value *ucontrol)
1533{
1534 struct tdm_port port;
1535 int ret = tdm_get_port_idx(kcontrol, &port);
1536
1537 if (ret) {
1538 pr_err("%s: unsupported control: %s\n",
1539 __func__, kcontrol->id.name);
1540 } else {
1541 tdm_rx_cfg[port.mode][port.channel].sample_rate =
1542 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1543
1544 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1545 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1546 ucontrol->value.enumerated.item[0]);
1547 }
1548 return ret;
1549}
1550
1551static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
1552 struct snd_ctl_elem_value *ucontrol)
1553{
1554 struct tdm_port port;
1555 int ret = tdm_get_port_idx(kcontrol, &port);
1556
1557 if (ret) {
1558 pr_err("%s: unsupported control: %s",
1559 __func__, kcontrol->id.name);
1560 } else {
1561 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1562 tdm_tx_cfg[port.mode][port.channel].sample_rate);
1563
1564 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1565 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1566 ucontrol->value.enumerated.item[0]);
1567 }
1568 return ret;
1569}
1570
1571static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1572 struct snd_ctl_elem_value *ucontrol)
1573{
1574 struct tdm_port port;
1575 int ret = tdm_get_port_idx(kcontrol, &port);
1576
1577 if (ret) {
1578 pr_err("%s: unsupported control: %s\n",
1579 __func__, kcontrol->id.name);
1580 } else {
1581 tdm_tx_cfg[port.mode][port.channel].sample_rate =
1582 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1583
1584 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1585 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1586 ucontrol->value.enumerated.item[0]);
1587 }
1588 return ret;
1589}
1590
1591static int tdm_get_format(int value)
1592{
1593 int format = 0;
1594
1595 switch (value) {
1596 case 0:
1597 format = SNDRV_PCM_FORMAT_S16_LE;
1598 break;
1599 case 1:
1600 format = SNDRV_PCM_FORMAT_S24_LE;
1601 break;
1602 case 2:
1603 format = SNDRV_PCM_FORMAT_S32_LE;
1604 break;
1605 default:
1606 format = SNDRV_PCM_FORMAT_S16_LE;
1607 break;
1608 }
1609 return format;
1610}
1611
1612static int tdm_get_format_val(int format)
1613{
1614 int value = 0;
1615
1616 switch (format) {
1617 case SNDRV_PCM_FORMAT_S16_LE:
1618 value = 0;
1619 break;
1620 case SNDRV_PCM_FORMAT_S24_LE:
1621 value = 1;
1622 break;
1623 case SNDRV_PCM_FORMAT_S32_LE:
1624 value = 2;
1625 break;
1626 default:
1627 value = 0;
1628 break;
1629 }
1630 return value;
1631}
1632
1633static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
1634 struct snd_ctl_elem_value *ucontrol)
1635{
1636 struct tdm_port port;
1637 int ret = tdm_get_port_idx(kcontrol, &port);
1638
1639 if (ret) {
1640 pr_err("%s: unsupported control: %s\n",
1641 __func__, kcontrol->id.name);
1642 } else {
1643 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1644 tdm_rx_cfg[port.mode][port.channel].bit_format);
1645
1646 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1647 tdm_rx_cfg[port.mode][port.channel].bit_format,
1648 ucontrol->value.enumerated.item[0]);
1649 }
1650 return ret;
1651}
1652
1653static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
1654 struct snd_ctl_elem_value *ucontrol)
1655{
1656 struct tdm_port port;
1657 int ret = tdm_get_port_idx(kcontrol, &port);
1658
1659 if (ret) {
1660 pr_err("%s: unsupported control: %s\n",
1661 __func__, kcontrol->id.name);
1662 } else {
1663 tdm_rx_cfg[port.mode][port.channel].bit_format =
1664 tdm_get_format(ucontrol->value.enumerated.item[0]);
1665
1666 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1667 tdm_rx_cfg[port.mode][port.channel].bit_format,
1668 ucontrol->value.enumerated.item[0]);
1669 }
1670 return ret;
1671}
1672
1673static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
1674 struct snd_ctl_elem_value *ucontrol)
1675{
1676 struct tdm_port port;
1677 int ret = tdm_get_port_idx(kcontrol, &port);
1678
1679 if (ret) {
1680 pr_err("%s: unsupported control: %s\n",
1681 __func__, kcontrol->id.name);
1682 } else {
1683 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1684 tdm_tx_cfg[port.mode][port.channel].bit_format);
1685
1686 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1687 tdm_tx_cfg[port.mode][port.channel].bit_format,
1688 ucontrol->value.enumerated.item[0]);
1689 }
1690 return ret;
1691}
1692
1693static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
1694 struct snd_ctl_elem_value *ucontrol)
1695{
1696 struct tdm_port port;
1697 int ret = tdm_get_port_idx(kcontrol, &port);
1698
1699 if (ret) {
1700 pr_err("%s: unsupported control: %s\n",
1701 __func__, kcontrol->id.name);
1702 } else {
1703 tdm_tx_cfg[port.mode][port.channel].bit_format =
1704 tdm_get_format(ucontrol->value.enumerated.item[0]);
1705
1706 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1707 tdm_tx_cfg[port.mode][port.channel].bit_format,
1708 ucontrol->value.enumerated.item[0]);
1709 }
1710 return ret;
1711}
1712
1713static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
1714 struct snd_ctl_elem_value *ucontrol)
1715{
1716 struct tdm_port port;
1717 int ret = tdm_get_port_idx(kcontrol, &port);
1718
1719 if (ret) {
1720 pr_err("%s: unsupported control: %s\n",
1721 __func__, kcontrol->id.name);
1722 } else {
1723
1724 ucontrol->value.enumerated.item[0] =
1725 tdm_rx_cfg[port.mode][port.channel].channels - 1;
1726
1727 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1728 tdm_rx_cfg[port.mode][port.channel].channels - 1,
1729 ucontrol->value.enumerated.item[0]);
1730 }
1731 return ret;
1732}
1733
1734static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
1735 struct snd_ctl_elem_value *ucontrol)
1736{
1737 struct tdm_port port;
1738 int ret = tdm_get_port_idx(kcontrol, &port);
1739
1740 if (ret) {
1741 pr_err("%s: unsupported control: %s\n",
1742 __func__, kcontrol->id.name);
1743 } else {
1744 tdm_rx_cfg[port.mode][port.channel].channels =
1745 ucontrol->value.enumerated.item[0] + 1;
1746
1747 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1748 tdm_rx_cfg[port.mode][port.channel].channels,
1749 ucontrol->value.enumerated.item[0] + 1);
1750 }
1751 return ret;
1752}
1753
1754static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
1755 struct snd_ctl_elem_value *ucontrol)
1756{
1757 struct tdm_port port;
1758 int ret = tdm_get_port_idx(kcontrol, &port);
1759
1760 if (ret) {
1761 pr_err("%s: unsupported control: %s\n",
1762 __func__, kcontrol->id.name);
1763 } else {
1764 ucontrol->value.enumerated.item[0] =
1765 tdm_tx_cfg[port.mode][port.channel].channels - 1;
1766
1767 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1768 tdm_tx_cfg[port.mode][port.channel].channels - 1,
1769 ucontrol->value.enumerated.item[0]);
1770 }
1771 return ret;
1772}
1773
1774static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
1775 struct snd_ctl_elem_value *ucontrol)
1776{
1777 struct tdm_port port;
1778 int ret = tdm_get_port_idx(kcontrol, &port);
1779
1780 if (ret) {
1781 pr_err("%s: unsupported control: %s\n",
1782 __func__, kcontrol->id.name);
1783 } else {
1784 tdm_tx_cfg[port.mode][port.channel].channels =
1785 ucontrol->value.enumerated.item[0] + 1;
1786
1787 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1788 tdm_tx_cfg[port.mode][port.channel].channels,
1789 ucontrol->value.enumerated.item[0] + 1);
1790 }
1791 return ret;
1792}
1793
1794static int tdm_get_slot_num_val(int slot_num)
1795{
1796 int slot_num_val = 0;
1797
1798 switch (slot_num) {
1799 case 1:
1800 slot_num_val = 0;
1801 break;
1802 case 2:
1803 slot_num_val = 1;
1804 break;
1805 case 4:
1806 slot_num_val = 2;
1807 break;
1808 case 8:
1809 slot_num_val = 3;
1810 break;
1811 case 16:
1812 slot_num_val = 4;
1813 break;
1814 case 32:
1815 slot_num_val = 5;
1816 break;
1817 default:
1818 slot_num_val = 5;
1819 break;
1820 }
1821 return slot_num_val;
1822}
1823
1824static int tdm_slot_num_get(struct snd_kcontrol *kcontrol,
1825 struct snd_ctl_elem_value *ucontrol)
1826{
1827 int mode = tdm_get_mode(kcontrol);
1828
1829 if (mode < 0) {
1830 pr_err("%s: unsupported control: %s\n",
1831 __func__, kcontrol->id.name);
1832 return mode;
1833 }
1834
1835 ucontrol->value.enumerated.item[0] =
1836 tdm_get_slot_num_val(tdm_slot[mode].num);
1837
1838 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1839 mode, tdm_slot[mode].num,
1840 ucontrol->value.enumerated.item[0]);
1841
1842 return 0;
1843}
1844
1845static int tdm_get_slot_num(int value)
1846{
1847 int slot_num = 0;
1848
1849 switch (value) {
1850 case 0:
1851 slot_num = 1;
1852 break;
1853 case 1:
1854 slot_num = 2;
1855 break;
1856 case 2:
1857 slot_num = 4;
1858 break;
1859 case 3:
1860 slot_num = 8;
1861 break;
1862 case 4:
1863 slot_num = 16;
1864 break;
1865 case 5:
1866 slot_num = 32;
1867 break;
1868 default:
1869 slot_num = 8;
1870 break;
1871 }
1872 return slot_num;
1873}
1874
1875static int tdm_slot_num_put(struct snd_kcontrol *kcontrol,
1876 struct snd_ctl_elem_value *ucontrol)
1877{
1878 int mode = tdm_get_mode(kcontrol);
1879
1880 if (mode < 0) {
1881 pr_err("%s: unsupported control: %s\n",
1882 __func__, kcontrol->id.name);
1883 return mode;
1884 }
1885
1886 tdm_slot[mode].num =
1887 tdm_get_slot_num(ucontrol->value.enumerated.item[0]);
1888
1889 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1890 mode, tdm_slot[mode].num,
1891 ucontrol->value.enumerated.item[0]);
1892
1893 return 0;
1894}
1895
1896static int tdm_get_slot_width_val(int slot_width)
1897{
1898 int slot_width_val = 2;
1899
1900 switch (slot_width) {
1901 case 16:
1902 slot_width_val = 0;
1903 break;
1904 case 24:
1905 slot_width_val = 1;
1906 break;
1907 case 32:
1908 slot_width_val = 2;
1909 break;
1910 default:
1911 slot_width_val = 2;
1912 break;
1913 }
1914 return slot_width_val;
1915}
1916
1917static int tdm_slot_width_get(struct snd_kcontrol *kcontrol,
1918 struct snd_ctl_elem_value *ucontrol)
1919{
1920 int mode = tdm_get_mode(kcontrol);
1921
1922 if (mode < 0) {
1923 pr_err("%s: unsupported control: %s\n",
1924 __func__, kcontrol->id.name);
1925 return mode;
1926 }
1927
1928 ucontrol->value.enumerated.item[0] =
1929 tdm_get_slot_width_val(tdm_slot[mode].width);
1930
1931 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1932 mode, tdm_slot[mode].width,
1933 ucontrol->value.enumerated.item[0]);
1934
1935 return 0;
1936}
1937
1938static int tdm_get_slot_width(int value)
1939{
1940 int slot_width = 32;
1941
1942 switch (value) {
1943 case 0:
1944 slot_width = 16;
1945 break;
1946 case 1:
1947 slot_width = 24;
1948 break;
1949 case 2:
1950 slot_width = 32;
1951 break;
1952 default:
1953 slot_width = 32;
1954 break;
1955 }
1956 return slot_width;
1957}
1958
1959static int tdm_slot_width_put(struct snd_kcontrol *kcontrol,
1960 struct snd_ctl_elem_value *ucontrol)
1961{
1962 int mode = tdm_get_mode(kcontrol);
1963
1964 if (mode < 0) {
1965 pr_err("%s: unsupported control: %s\n",
1966 __func__, kcontrol->id.name);
1967 return mode;
1968 }
1969
1970 tdm_slot[mode].width =
1971 tdm_get_slot_width(ucontrol->value.enumerated.item[0]);
1972
1973 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1974 mode, tdm_slot[mode].width,
1975 ucontrol->value.enumerated.item[0]);
1976
1977 return 0;
1978}
1979
1980static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol,
1981 struct snd_ctl_elem_value *ucontrol)
1982{
1983 unsigned int *slot_offset;
1984 int i;
1985 struct tdm_port port;
1986 int ret = tdm_get_port_idx(kcontrol, &port);
1987
1988 if (ret) {
1989 pr_err("%s: unsupported control: %s\n",
1990 __func__, kcontrol->id.name);
1991 } else {
1992 slot_offset = tdm_rx_slot_offset[port.mode][port.channel];
1993 pr_debug("%s: mode = %d, channel = %d\n",
1994 __func__, port.mode, port.channel);
1995 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1996 ucontrol->value.integer.value[i] = slot_offset[i];
1997 pr_debug("%s: offset %d, value %d\n",
1998 __func__, i, slot_offset[i]);
1999 }
2000 }
2001 return ret;
2002}
2003
2004static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol,
2005 struct snd_ctl_elem_value *ucontrol)
2006{
2007 unsigned int *slot_offset;
2008 int i;
2009 struct tdm_port port;
2010 int ret = tdm_get_port_idx(kcontrol, &port);
2011
2012 if (ret) {
2013 pr_err("%s: unsupported control: %s\n",
2014 __func__, kcontrol->id.name);
2015 } else {
2016 slot_offset = tdm_rx_slot_offset[port.mode][port.channel];
2017 pr_debug("%s: mode = %d, channel = %d\n",
2018 __func__, port.mode, port.channel);
2019 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2020 slot_offset[i] = ucontrol->value.integer.value[i];
2021 pr_debug("%s: offset %d, value %d\n",
2022 __func__, i, slot_offset[i]);
2023 }
2024 }
2025 return ret;
2026}
2027
2028static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol,
2029 struct snd_ctl_elem_value *ucontrol)
2030{
2031 unsigned int *slot_offset;
2032 int i;
2033 struct tdm_port port;
2034 int ret = tdm_get_port_idx(kcontrol, &port);
2035
2036 if (ret) {
2037 pr_err("%s: unsupported control: %s\n",
2038 __func__, kcontrol->id.name);
2039 } else {
2040 slot_offset = tdm_tx_slot_offset[port.mode][port.channel];
2041 pr_debug("%s: mode = %d, channel = %d\n",
2042 __func__, port.mode, port.channel);
2043 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2044 ucontrol->value.integer.value[i] = slot_offset[i];
2045 pr_debug("%s: offset %d, value %d\n",
2046 __func__, i, slot_offset[i]);
2047 }
2048 }
2049 return ret;
2050}
2051
2052static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol,
2053 struct snd_ctl_elem_value *ucontrol)
2054{
2055 unsigned int *slot_offset;
2056 int i;
2057 struct tdm_port port;
2058 int ret = tdm_get_port_idx(kcontrol, &port);
2059
2060 if (ret) {
2061 pr_err("%s: unsupported control: %s\n",
2062 __func__, kcontrol->id.name);
2063 } else {
2064 slot_offset = tdm_tx_slot_offset[port.mode][port.channel];
2065 pr_debug("%s: mode = %d, channel = %d\n",
2066 __func__, port.mode, port.channel);
2067 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2068 slot_offset[i] = ucontrol->value.integer.value[i];
2069 pr_debug("%s: offset %d, value %d\n",
2070 __func__, i, slot_offset[i]);
2071 }
2072 }
2073 return ret;
2074}
2075
2076static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
2077{
2078 int idx;
2079
2080 if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
2081 sizeof("PRIM_AUX_PCM")))
2082 idx = PRIM_AUX_PCM;
2083 else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
2084 sizeof("SEC_AUX_PCM")))
2085 idx = SEC_AUX_PCM;
2086 else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
2087 sizeof("TERT_AUX_PCM")))
2088 idx = TERT_AUX_PCM;
2089 else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
2090 sizeof("QUAT_AUX_PCM")))
2091 idx = QUAT_AUX_PCM;
2092 else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
2093 sizeof("QUIN_AUX_PCM")))
2094 idx = QUIN_AUX_PCM;
2095 else {
2096 pr_err("%s: unsupported port: %s\n",
2097 __func__, kcontrol->id.name);
2098 idx = -EINVAL;
2099 }
2100
2101 return idx;
2102}
2103
2104static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2105 struct snd_ctl_elem_value *ucontrol)
2106{
2107 int idx = aux_pcm_get_port_idx(kcontrol);
2108
2109 if (idx < 0)
2110 return idx;
2111
2112 aux_pcm_rx_cfg[idx].sample_rate =
2113 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2114
2115 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2116 idx, aux_pcm_rx_cfg[idx].sample_rate,
2117 ucontrol->value.enumerated.item[0]);
2118
2119 return 0;
2120}
2121
2122static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2123 struct snd_ctl_elem_value *ucontrol)
2124{
2125 int idx = aux_pcm_get_port_idx(kcontrol);
2126
2127 if (idx < 0)
2128 return idx;
2129
2130 ucontrol->value.enumerated.item[0] =
2131 aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
2132
2133 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2134 idx, aux_pcm_rx_cfg[idx].sample_rate,
2135 ucontrol->value.enumerated.item[0]);
2136
2137 return 0;
2138}
2139
2140static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2141 struct snd_ctl_elem_value *ucontrol)
2142{
2143 int idx = aux_pcm_get_port_idx(kcontrol);
2144
2145 if (idx < 0)
2146 return idx;
2147
2148 aux_pcm_tx_cfg[idx].sample_rate =
2149 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2150
2151 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2152 idx, aux_pcm_tx_cfg[idx].sample_rate,
2153 ucontrol->value.enumerated.item[0]);
2154
2155 return 0;
2156}
2157
2158static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2159 struct snd_ctl_elem_value *ucontrol)
2160{
2161 int idx = aux_pcm_get_port_idx(kcontrol);
2162
2163 if (idx < 0)
2164 return idx;
2165
2166 ucontrol->value.enumerated.item[0] =
2167 aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
2168
2169 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2170 idx, aux_pcm_tx_cfg[idx].sample_rate,
2171 ucontrol->value.enumerated.item[0]);
2172
2173 return 0;
2174}
2175
2176static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
2177{
2178 int idx;
2179
2180 if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
2181 sizeof("PRIM_MI2S_RX")))
2182 idx = PRIM_MI2S;
2183 else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
2184 sizeof("SEC_MI2S_RX")))
2185 idx = SEC_MI2S;
2186 else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
2187 sizeof("TERT_MI2S_RX")))
2188 idx = TERT_MI2S;
2189 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
2190 sizeof("QUAT_MI2S_RX")))
2191 idx = QUAT_MI2S;
2192 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
2193 sizeof("QUIN_MI2S_RX")))
2194 idx = QUIN_MI2S;
2195 else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
2196 sizeof("PRIM_MI2S_TX")))
2197 idx = PRIM_MI2S;
2198 else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
2199 sizeof("SEC_MI2S_TX")))
2200 idx = SEC_MI2S;
2201 else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
2202 sizeof("TERT_MI2S_TX")))
2203 idx = TERT_MI2S;
2204 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
2205 sizeof("QUAT_MI2S_TX")))
2206 idx = QUAT_MI2S;
2207 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
2208 sizeof("QUIN_MI2S_TX")))
2209 idx = QUIN_MI2S;
2210 else {
2211 pr_err("%s: unsupported channel: %s\n",
2212 __func__, kcontrol->id.name);
2213 idx = -EINVAL;
2214 }
2215
2216 return idx;
2217}
2218
2219static int mi2s_get_sample_rate_val(int sample_rate)
2220{
2221 int sample_rate_val;
2222
2223 switch (sample_rate) {
2224 case SAMPLING_RATE_8KHZ:
2225 sample_rate_val = 0;
2226 break;
2227 case SAMPLING_RATE_11P025KHZ:
2228 sample_rate_val = 1;
2229 break;
2230 case SAMPLING_RATE_16KHZ:
2231 sample_rate_val = 2;
2232 break;
2233 case SAMPLING_RATE_22P05KHZ:
2234 sample_rate_val = 3;
2235 break;
2236 case SAMPLING_RATE_32KHZ:
2237 sample_rate_val = 4;
2238 break;
2239 case SAMPLING_RATE_44P1KHZ:
2240 sample_rate_val = 5;
2241 break;
2242 case SAMPLING_RATE_48KHZ:
2243 sample_rate_val = 6;
2244 break;
2245 case SAMPLING_RATE_96KHZ:
2246 sample_rate_val = 7;
2247 break;
2248 case SAMPLING_RATE_192KHZ:
2249 sample_rate_val = 8;
2250 break;
2251 default:
2252 sample_rate_val = 6;
2253 break;
2254 }
2255 return sample_rate_val;
2256}
2257
2258static int mi2s_get_sample_rate(int value)
2259{
2260 int sample_rate;
2261
2262 switch (value) {
2263 case 0:
2264 sample_rate = SAMPLING_RATE_8KHZ;
2265 break;
2266 case 1:
2267 sample_rate = SAMPLING_RATE_11P025KHZ;
2268 break;
2269 case 2:
2270 sample_rate = SAMPLING_RATE_16KHZ;
2271 break;
2272 case 3:
2273 sample_rate = SAMPLING_RATE_22P05KHZ;
2274 break;
2275 case 4:
2276 sample_rate = SAMPLING_RATE_32KHZ;
2277 break;
2278 case 5:
2279 sample_rate = SAMPLING_RATE_44P1KHZ;
2280 break;
2281 case 6:
2282 sample_rate = SAMPLING_RATE_48KHZ;
2283 break;
2284 case 7:
2285 sample_rate = SAMPLING_RATE_96KHZ;
2286 break;
2287 case 8:
2288 sample_rate = SAMPLING_RATE_192KHZ;
2289 break;
2290 default:
2291 sample_rate = SAMPLING_RATE_48KHZ;
2292 break;
2293 }
2294 return sample_rate;
2295}
2296
2297static int mi2s_auxpcm_get_format(int value)
2298{
2299 int format;
2300
2301 switch (value) {
2302 case 0:
2303 format = SNDRV_PCM_FORMAT_S16_LE;
2304 break;
2305 case 1:
2306 format = SNDRV_PCM_FORMAT_S24_LE;
2307 break;
2308 case 2:
2309 format = SNDRV_PCM_FORMAT_S24_3LE;
2310 break;
2311 case 3:
2312 format = SNDRV_PCM_FORMAT_S32_LE;
2313 break;
2314 default:
2315 format = SNDRV_PCM_FORMAT_S16_LE;
2316 break;
2317 }
2318 return format;
2319}
2320
2321static int mi2s_auxpcm_get_format_value(int format)
2322{
2323 int value;
2324
2325 switch (format) {
2326 case SNDRV_PCM_FORMAT_S16_LE:
2327 value = 0;
2328 break;
2329 case SNDRV_PCM_FORMAT_S24_LE:
2330 value = 1;
2331 break;
2332 case SNDRV_PCM_FORMAT_S24_3LE:
2333 value = 2;
2334 break;
2335 case SNDRV_PCM_FORMAT_S32_LE:
2336 value = 3;
2337 break;
2338 default:
2339 value = 0;
2340 break;
2341 }
2342 return value;
2343}
2344
2345static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2346 struct snd_ctl_elem_value *ucontrol)
2347{
2348 int idx = mi2s_get_port_idx(kcontrol);
2349
2350 if (idx < 0)
2351 return idx;
2352
2353 mi2s_rx_cfg[idx].sample_rate =
2354 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2355
2356 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2357 idx, mi2s_rx_cfg[idx].sample_rate,
2358 ucontrol->value.enumerated.item[0]);
2359
2360 return 0;
2361}
2362
2363static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2364 struct snd_ctl_elem_value *ucontrol)
2365{
2366 int idx = mi2s_get_port_idx(kcontrol);
2367
2368 if (idx < 0)
2369 return idx;
2370
2371 ucontrol->value.enumerated.item[0] =
2372 mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
2373
2374 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2375 idx, mi2s_rx_cfg[idx].sample_rate,
2376 ucontrol->value.enumerated.item[0]);
2377
2378 return 0;
2379}
2380
2381static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2382 struct snd_ctl_elem_value *ucontrol)
2383{
2384 int idx = mi2s_get_port_idx(kcontrol);
2385
2386 if (idx < 0)
2387 return idx;
2388
2389 mi2s_tx_cfg[idx].sample_rate =
2390 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2391
2392 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2393 idx, mi2s_tx_cfg[idx].sample_rate,
2394 ucontrol->value.enumerated.item[0]);
2395
2396 return 0;
2397}
2398
2399static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2400 struct snd_ctl_elem_value *ucontrol)
2401{
2402 int idx = mi2s_get_port_idx(kcontrol);
2403
2404 if (idx < 0)
2405 return idx;
2406
2407 ucontrol->value.enumerated.item[0] =
2408 mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
2409
2410 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2411 idx, mi2s_tx_cfg[idx].sample_rate,
2412 ucontrol->value.enumerated.item[0]);
2413
2414 return 0;
2415}
2416
2417static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
2418 struct snd_ctl_elem_value *ucontrol)
2419{
2420 int idx = mi2s_get_port_idx(kcontrol);
2421
2422 if (idx < 0)
2423 return idx;
2424
2425 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2426 idx, mi2s_rx_cfg[idx].channels);
2427 ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
2428
2429 return 0;
2430}
2431
2432static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
2433 struct snd_ctl_elem_value *ucontrol)
2434{
2435 int idx = mi2s_get_port_idx(kcontrol);
2436
2437 if (idx < 0)
2438 return idx;
2439
2440 mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2441 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2442 idx, mi2s_rx_cfg[idx].channels);
2443
2444 return 1;
2445}
2446
2447static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
2448 struct snd_ctl_elem_value *ucontrol)
2449{
2450 int idx = mi2s_get_port_idx(kcontrol);
2451
2452 if (idx < 0)
2453 return idx;
2454
2455 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2456 idx, mi2s_tx_cfg[idx].channels);
2457 ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
2458
2459 return 0;
2460}
2461
2462static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
2463 struct snd_ctl_elem_value *ucontrol)
2464{
2465 int idx = mi2s_get_port_idx(kcontrol);
2466
2467 if (idx < 0)
2468 return idx;
2469
2470 mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2471 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2472 idx, mi2s_tx_cfg[idx].channels);
2473
2474 return 1;
2475}
2476
2477static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
2478 struct snd_ctl_elem_value *ucontrol)
2479{
2480 int idx = mi2s_get_port_idx(kcontrol);
2481
2482 if (idx < 0)
2483 return idx;
2484
2485 ucontrol->value.enumerated.item[0] =
2486 mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
2487
2488 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2489 idx, mi2s_rx_cfg[idx].bit_format,
2490 ucontrol->value.enumerated.item[0]);
2491
2492 return 0;
2493}
2494
2495static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
2496 struct snd_ctl_elem_value *ucontrol)
2497{
2498 int idx = mi2s_get_port_idx(kcontrol);
2499
2500 if (idx < 0)
2501 return idx;
2502
2503 mi2s_rx_cfg[idx].bit_format =
2504 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2505
2506 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2507 idx, mi2s_rx_cfg[idx].bit_format,
2508 ucontrol->value.enumerated.item[0]);
2509
2510 return 0;
2511}
2512
2513static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
2514 struct snd_ctl_elem_value *ucontrol)
2515{
2516 int idx = mi2s_get_port_idx(kcontrol);
2517
2518 if (idx < 0)
2519 return idx;
2520
2521 ucontrol->value.enumerated.item[0] =
2522 mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
2523
2524 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2525 idx, mi2s_tx_cfg[idx].bit_format,
2526 ucontrol->value.enumerated.item[0]);
2527
2528 return 0;
2529}
2530
2531static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
2532 struct snd_ctl_elem_value *ucontrol)
2533{
2534 int idx = mi2s_get_port_idx(kcontrol);
2535
2536 if (idx < 0)
2537 return idx;
2538
2539 mi2s_tx_cfg[idx].bit_format =
2540 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2541
2542 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2543 idx, mi2s_tx_cfg[idx].bit_format,
2544 ucontrol->value.enumerated.item[0]);
2545
2546 return 0;
2547}
2548
2549static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
2550 struct snd_ctl_elem_value *ucontrol)
2551{
2552 int idx = aux_pcm_get_port_idx(kcontrol);
2553
2554 if (idx < 0)
2555 return idx;
2556
2557 ucontrol->value.enumerated.item[0] =
2558 mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
2559
2560 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2561 idx, aux_pcm_rx_cfg[idx].bit_format,
2562 ucontrol->value.enumerated.item[0]);
2563
2564 return 0;
2565}
2566
2567static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
2568 struct snd_ctl_elem_value *ucontrol)
2569{
2570 int idx = aux_pcm_get_port_idx(kcontrol);
2571
2572 if (idx < 0)
2573 return idx;
2574
2575 aux_pcm_rx_cfg[idx].bit_format =
2576 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2577
2578 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2579 idx, aux_pcm_rx_cfg[idx].bit_format,
2580 ucontrol->value.enumerated.item[0]);
2581
2582 return 0;
2583}
2584
2585static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
2586 struct snd_ctl_elem_value *ucontrol)
2587{
2588 int idx = aux_pcm_get_port_idx(kcontrol);
2589
2590 if (idx < 0)
2591 return idx;
2592
2593 ucontrol->value.enumerated.item[0] =
2594 mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
2595
2596 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2597 idx, aux_pcm_tx_cfg[idx].bit_format,
2598 ucontrol->value.enumerated.item[0]);
2599
2600 return 0;
2601}
2602
2603static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
2604 struct snd_ctl_elem_value *ucontrol)
2605{
2606 int idx = aux_pcm_get_port_idx(kcontrol);
2607
2608 if (idx < 0)
2609 return idx;
2610
2611 aux_pcm_tx_cfg[idx].bit_format =
2612 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2613
2614 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2615 idx, aux_pcm_tx_cfg[idx].bit_format,
2616 ucontrol->value.enumerated.item[0]);
2617
2618 return 0;
2619}
2620
2621static const struct snd_kcontrol_new msm_snd_controls[] = {
2622 SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
2623 usb_audio_rx_ch_get, usb_audio_rx_ch_put),
2624 SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
2625 usb_audio_tx_ch_get, usb_audio_tx_ch_put),
2626 SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
2627 ext_disp_rx_ch_get, ext_disp_rx_ch_put),
2628 SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
2629 proxy_rx_ch_get, proxy_rx_ch_put),
2630 SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
2631 usb_audio_rx_format_get, usb_audio_rx_format_put),
2632 SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
2633 usb_audio_tx_format_get, usb_audio_tx_format_put),
2634 SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
2635 ext_disp_rx_format_get, ext_disp_rx_format_put),
2636 SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
2637 usb_audio_rx_sample_rate_get,
2638 usb_audio_rx_sample_rate_put),
2639 SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
2640 usb_audio_tx_sample_rate_get,
2641 usb_audio_tx_sample_rate_put),
2642 SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
2643 ext_disp_rx_sample_rate_get,
2644 ext_disp_rx_sample_rate_put),
2645 SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2646 tdm_rx_sample_rate_get,
2647 tdm_rx_sample_rate_put),
2648 SOC_ENUM_EXT("PRI_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2649 tdm_rx_sample_rate_get,
2650 tdm_rx_sample_rate_put),
2651 SOC_ENUM_EXT("PRI_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2652 tdm_rx_sample_rate_get,
2653 tdm_rx_sample_rate_put),
2654 SOC_ENUM_EXT("PRI_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2655 tdm_rx_sample_rate_get,
2656 tdm_rx_sample_rate_put),
2657 SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2658 tdm_tx_sample_rate_get,
2659 tdm_tx_sample_rate_put),
2660 SOC_ENUM_EXT("PRI_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2661 tdm_tx_sample_rate_get,
2662 tdm_tx_sample_rate_put),
2663 SOC_ENUM_EXT("PRI_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2664 tdm_tx_sample_rate_get,
2665 tdm_tx_sample_rate_put),
2666 SOC_ENUM_EXT("PRI_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2667 tdm_tx_sample_rate_get,
2668 tdm_tx_sample_rate_put),
2669 SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
2670 tdm_rx_format_get,
2671 tdm_rx_format_put),
2672 SOC_ENUM_EXT("PRI_TDM_RX_1 Format", tdm_rx_format,
2673 tdm_rx_format_get,
2674 tdm_rx_format_put),
2675 SOC_ENUM_EXT("PRI_TDM_RX_2 Format", tdm_rx_format,
2676 tdm_rx_format_get,
2677 tdm_rx_format_put),
2678 SOC_ENUM_EXT("PRI_TDM_RX_3 Format", tdm_rx_format,
2679 tdm_rx_format_get,
2680 tdm_rx_format_put),
2681 SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
2682 tdm_tx_format_get,
2683 tdm_tx_format_put),
2684 SOC_ENUM_EXT("PRI_TDM_TX_1 Format", tdm_tx_format,
2685 tdm_tx_format_get,
2686 tdm_tx_format_put),
2687 SOC_ENUM_EXT("PRI_TDM_TX_2 Format", tdm_tx_format,
2688 tdm_tx_format_get,
2689 tdm_tx_format_put),
2690 SOC_ENUM_EXT("PRI_TDM_TX_3 Format", tdm_tx_format,
2691 tdm_tx_format_get,
2692 tdm_tx_format_put),
2693 SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
2694 tdm_rx_ch_get,
2695 tdm_rx_ch_put),
2696 SOC_ENUM_EXT("PRI_TDM_RX_1 Channels", tdm_rx_chs,
2697 tdm_rx_ch_get,
2698 tdm_rx_ch_put),
2699 SOC_ENUM_EXT("PRI_TDM_RX_2 Channels", tdm_rx_chs,
2700 tdm_rx_ch_get,
2701 tdm_rx_ch_put),
2702 SOC_ENUM_EXT("PRI_TDM_RX_3 Channels", tdm_rx_chs,
2703 tdm_rx_ch_get,
2704 tdm_rx_ch_put),
2705 SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
2706 tdm_tx_ch_get,
2707 tdm_tx_ch_put),
2708 SOC_ENUM_EXT("PRI_TDM_TX_1 Channels", tdm_tx_chs,
2709 tdm_tx_ch_get,
2710 tdm_tx_ch_put),
2711 SOC_ENUM_EXT("PRI_TDM_TX_2 Channels", tdm_tx_chs,
2712 tdm_tx_ch_get,
2713 tdm_tx_ch_put),
2714 SOC_ENUM_EXT("PRI_TDM_TX_3 Channels", tdm_tx_chs,
2715 tdm_tx_ch_get,
2716 tdm_tx_ch_put),
2717 SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2718 tdm_rx_sample_rate_get,
2719 tdm_rx_sample_rate_put),
2720 SOC_ENUM_EXT("SEC_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2721 tdm_rx_sample_rate_get,
2722 tdm_rx_sample_rate_put),
2723 SOC_ENUM_EXT("SEC_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2724 tdm_rx_sample_rate_get,
2725 tdm_rx_sample_rate_put),
2726 SOC_ENUM_EXT("SEC_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2727 tdm_rx_sample_rate_get,
2728 tdm_rx_sample_rate_put),
2729 SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2730 tdm_tx_sample_rate_get,
2731 tdm_tx_sample_rate_put),
2732 SOC_ENUM_EXT("SEC_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2733 tdm_tx_sample_rate_get,
2734 tdm_tx_sample_rate_put),
2735 SOC_ENUM_EXT("SEC_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2736 tdm_tx_sample_rate_get,
2737 tdm_tx_sample_rate_put),
2738 SOC_ENUM_EXT("SEC_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2739 tdm_tx_sample_rate_get,
2740 tdm_tx_sample_rate_put),
2741 SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
2742 tdm_rx_format_get,
2743 tdm_rx_format_put),
2744 SOC_ENUM_EXT("SEC_TDM_RX_1 Format", tdm_rx_format,
2745 tdm_rx_format_get,
2746 tdm_rx_format_put),
2747 SOC_ENUM_EXT("SEC_TDM_RX_2 Format", tdm_rx_format,
2748 tdm_rx_format_get,
2749 tdm_rx_format_put),
2750 SOC_ENUM_EXT("SEC_TDM_RX_3 Format", tdm_rx_format,
2751 tdm_rx_format_get,
2752 tdm_rx_format_put),
2753 SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
2754 tdm_tx_format_get,
2755 tdm_tx_format_put),
2756 SOC_ENUM_EXT("SEC_TDM_TX_1 Format", tdm_tx_format,
2757 tdm_tx_format_get,
2758 tdm_tx_format_put),
2759 SOC_ENUM_EXT("SEC_TDM_TX_2 Format", tdm_tx_format,
2760 tdm_tx_format_get,
2761 tdm_tx_format_put),
2762 SOC_ENUM_EXT("SEC_TDM_TX_3 Format", tdm_tx_format,
2763 tdm_tx_format_get,
2764 tdm_tx_format_put),
2765 SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
2766 tdm_rx_ch_get,
2767 tdm_rx_ch_put),
2768 SOC_ENUM_EXT("SEC_TDM_RX_1 Channels", tdm_rx_chs,
2769 tdm_rx_ch_get,
2770 tdm_rx_ch_put),
2771 SOC_ENUM_EXT("SEC_TDM_RX_2 Channels", tdm_rx_chs,
2772 tdm_rx_ch_get,
2773 tdm_rx_ch_put),
2774 SOC_ENUM_EXT("SEC_TDM_RX_3 Channels", tdm_rx_chs,
2775 tdm_rx_ch_get,
2776 tdm_rx_ch_put),
2777 SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
2778 tdm_tx_ch_get,
2779 tdm_tx_ch_put),
2780 SOC_ENUM_EXT("SEC_TDM_TX_1 Channels", tdm_tx_chs,
2781 tdm_tx_ch_get,
2782 tdm_tx_ch_put),
2783 SOC_ENUM_EXT("SEC_TDM_TX_2 Channels", tdm_tx_chs,
2784 tdm_tx_ch_get,
2785 tdm_tx_ch_put),
2786 SOC_ENUM_EXT("SEC_TDM_TX_3 Channels", tdm_tx_chs,
2787 tdm_tx_ch_get,
2788 tdm_tx_ch_put),
2789 SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2790 tdm_rx_sample_rate_get,
2791 tdm_rx_sample_rate_put),
2792 SOC_ENUM_EXT("TERT_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2793 tdm_rx_sample_rate_get,
2794 tdm_rx_sample_rate_put),
2795 SOC_ENUM_EXT("TERT_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2796 tdm_rx_sample_rate_get,
2797 tdm_rx_sample_rate_put),
2798 SOC_ENUM_EXT("TERT_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2799 tdm_rx_sample_rate_get,
2800 tdm_rx_sample_rate_put),
2801 SOC_ENUM_EXT("TERT_TDM_RX_4 SampleRate", tdm_rx_sample_rate,
2802 tdm_rx_sample_rate_get,
2803 tdm_rx_sample_rate_put),
2804 SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2805 tdm_tx_sample_rate_get,
2806 tdm_tx_sample_rate_put),
2807 SOC_ENUM_EXT("TERT_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2808 tdm_tx_sample_rate_get,
2809 tdm_tx_sample_rate_put),
2810 SOC_ENUM_EXT("TERT_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2811 tdm_tx_sample_rate_get,
2812 tdm_tx_sample_rate_put),
2813 SOC_ENUM_EXT("TERT_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2814 tdm_tx_sample_rate_get,
2815 tdm_tx_sample_rate_put),
2816 SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
2817 tdm_rx_format_get,
2818 tdm_rx_format_put),
2819 SOC_ENUM_EXT("TERT_TDM_RX_1 Format", tdm_rx_format,
2820 tdm_rx_format_get,
2821 tdm_rx_format_put),
2822 SOC_ENUM_EXT("TERT_TDM_RX_2 Format", tdm_rx_format,
2823 tdm_rx_format_get,
2824 tdm_rx_format_put),
2825 SOC_ENUM_EXT("TERT_TDM_RX_3 Format", tdm_rx_format,
2826 tdm_rx_format_get,
2827 tdm_rx_format_put),
2828 SOC_ENUM_EXT("TERT_TDM_RX_4 Format", tdm_rx_format,
2829 tdm_rx_format_get,
2830 tdm_rx_format_put),
2831 SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
2832 tdm_tx_format_get,
2833 tdm_tx_format_put),
2834 SOC_ENUM_EXT("TERT_TDM_TX_1 Format", tdm_tx_format,
2835 tdm_tx_format_get,
2836 tdm_tx_format_put),
2837 SOC_ENUM_EXT("TERT_TDM_TX_2 Format", tdm_tx_format,
2838 tdm_tx_format_get,
2839 tdm_tx_format_put),
2840 SOC_ENUM_EXT("TERT_TDM_TX_3 Format", tdm_tx_format,
2841 tdm_tx_format_get,
2842 tdm_tx_format_put),
2843 SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
2844 tdm_rx_ch_get,
2845 tdm_rx_ch_put),
2846 SOC_ENUM_EXT("TERT_TDM_RX_1 Channels", tdm_rx_chs,
2847 tdm_rx_ch_get,
2848 tdm_rx_ch_put),
2849 SOC_ENUM_EXT("TERT_TDM_RX_2 Channels", tdm_rx_chs,
2850 tdm_rx_ch_get,
2851 tdm_rx_ch_put),
2852 SOC_ENUM_EXT("TERT_TDM_RX_3 Channels", tdm_rx_chs,
2853 tdm_rx_ch_get,
2854 tdm_rx_ch_put),
2855 SOC_ENUM_EXT("TERT_TDM_RX_4 Channels", tdm_rx_chs,
2856 tdm_rx_ch_get,
2857 tdm_rx_ch_put),
2858 SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
2859 tdm_tx_ch_get,
2860 tdm_tx_ch_put),
2861 SOC_ENUM_EXT("TERT_TDM_TX_1 Channels", tdm_tx_chs,
2862 tdm_tx_ch_get,
2863 tdm_tx_ch_put),
2864 SOC_ENUM_EXT("TERT_TDM_TX_2 Channels", tdm_tx_chs,
2865 tdm_tx_ch_get,
2866 tdm_tx_ch_put),
2867 SOC_ENUM_EXT("TERT_TDM_TX_3 Channels", tdm_tx_chs,
2868 tdm_tx_ch_get,
2869 tdm_tx_ch_put),
2870 SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2871 tdm_rx_sample_rate_get,
2872 tdm_rx_sample_rate_put),
2873 SOC_ENUM_EXT("QUAT_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2874 tdm_rx_sample_rate_get,
2875 tdm_rx_sample_rate_put),
2876 SOC_ENUM_EXT("QUAT_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2877 tdm_rx_sample_rate_get,
2878 tdm_rx_sample_rate_put),
2879 SOC_ENUM_EXT("QUAT_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2880 tdm_rx_sample_rate_get,
2881 tdm_rx_sample_rate_put),
2882 SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2883 tdm_tx_sample_rate_get,
2884 tdm_tx_sample_rate_put),
2885 SOC_ENUM_EXT("QUAT_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2886 tdm_tx_sample_rate_get,
2887 tdm_tx_sample_rate_put),
2888 SOC_ENUM_EXT("QUAT_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2889 tdm_tx_sample_rate_get,
2890 tdm_tx_sample_rate_put),
2891 SOC_ENUM_EXT("QUAT_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2892 tdm_tx_sample_rate_get,
2893 tdm_tx_sample_rate_put),
2894 SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
2895 tdm_rx_format_get,
2896 tdm_rx_format_put),
2897 SOC_ENUM_EXT("QUAT_TDM_RX_1 Format", tdm_rx_format,
2898 tdm_rx_format_get,
2899 tdm_rx_format_put),
2900 SOC_ENUM_EXT("QUAT_TDM_RX_2 Format", tdm_rx_format,
2901 tdm_rx_format_get,
2902 tdm_rx_format_put),
2903 SOC_ENUM_EXT("QUAT_TDM_RX_3 Format", tdm_rx_format,
2904 tdm_rx_format_get,
2905 tdm_rx_format_put),
2906 SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
2907 tdm_tx_format_get,
2908 tdm_tx_format_put),
2909 SOC_ENUM_EXT("QUAT_TDM_TX_1 Format", tdm_tx_format,
2910 tdm_tx_format_get,
2911 tdm_tx_format_put),
2912 SOC_ENUM_EXT("QUAT_TDM_TX_2 Format", tdm_tx_format,
2913 tdm_tx_format_get,
2914 tdm_tx_format_put),
2915 SOC_ENUM_EXT("QUAT_TDM_TX_3 Format", tdm_tx_format,
2916 tdm_tx_format_get,
2917 tdm_tx_format_put),
2918 SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
2919 tdm_rx_ch_get,
2920 tdm_rx_ch_put),
2921 SOC_ENUM_EXT("QUAT_TDM_RX_1 Channels", tdm_rx_chs,
2922 tdm_rx_ch_get,
2923 tdm_rx_ch_put),
2924 SOC_ENUM_EXT("QUAT_TDM_RX_2 Channels", tdm_rx_chs,
2925 tdm_rx_ch_get,
2926 tdm_rx_ch_put),
2927 SOC_ENUM_EXT("QUAT_TDM_RX_3 Channels", tdm_rx_chs,
2928 tdm_rx_ch_get,
2929 tdm_rx_ch_put),
2930 SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
2931 tdm_tx_ch_get,
2932 tdm_tx_ch_put),
2933 SOC_ENUM_EXT("QUAT_TDM_TX_1 Channels", tdm_tx_chs,
2934 tdm_tx_ch_get,
2935 tdm_tx_ch_put),
2936 SOC_ENUM_EXT("QUAT_TDM_TX_2 Channels", tdm_tx_chs,
2937 tdm_tx_ch_get,
2938 tdm_tx_ch_put),
2939 SOC_ENUM_EXT("QUAT_TDM_TX_3 Channels", tdm_tx_chs,
2940 tdm_tx_ch_get,
2941 tdm_tx_ch_put),
2942 SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2943 tdm_rx_sample_rate_get,
2944 tdm_rx_sample_rate_put),
2945 SOC_ENUM_EXT("QUIN_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2946 tdm_rx_sample_rate_get,
2947 tdm_rx_sample_rate_put),
2948 SOC_ENUM_EXT("QUIN_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2949 tdm_rx_sample_rate_get,
2950 tdm_rx_sample_rate_put),
2951 SOC_ENUM_EXT("QUIN_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2952 tdm_rx_sample_rate_get,
2953 tdm_rx_sample_rate_put),
2954 SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2955 tdm_tx_sample_rate_get,
2956 tdm_tx_sample_rate_put),
2957 SOC_ENUM_EXT("QUIN_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2958 tdm_tx_sample_rate_get,
2959 tdm_tx_sample_rate_put),
2960 SOC_ENUM_EXT("QUIN_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2961 tdm_tx_sample_rate_get,
2962 tdm_tx_sample_rate_put),
2963 SOC_ENUM_EXT("QUIN_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2964 tdm_tx_sample_rate_get,
2965 tdm_tx_sample_rate_put),
2966 SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
2967 tdm_rx_format_get,
2968 tdm_rx_format_put),
2969 SOC_ENUM_EXT("QUIN_TDM_RX_1 Format", tdm_rx_format,
2970 tdm_rx_format_get,
2971 tdm_rx_format_put),
2972 SOC_ENUM_EXT("QUIN_TDM_RX_2 Format", tdm_rx_format,
2973 tdm_rx_format_get,
2974 tdm_rx_format_put),
2975 SOC_ENUM_EXT("QUIN_TDM_RX_3 Format", tdm_rx_format,
2976 tdm_rx_format_get,
2977 tdm_rx_format_put),
2978 SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
2979 tdm_tx_format_get,
2980 tdm_tx_format_put),
2981 SOC_ENUM_EXT("QUIN_TDM_TX_1 Format", tdm_tx_format,
2982 tdm_tx_format_get,
2983 tdm_tx_format_put),
2984 SOC_ENUM_EXT("QUIN_TDM_TX_2 Format", tdm_tx_format,
2985 tdm_tx_format_get,
2986 tdm_tx_format_put),
2987 SOC_ENUM_EXT("QUIN_TDM_TX_3 Format", tdm_tx_format,
2988 tdm_tx_format_get,
2989 tdm_tx_format_put),
2990 SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
2991 tdm_rx_ch_get,
2992 tdm_rx_ch_put),
2993 SOC_ENUM_EXT("QUIN_TDM_RX_1 Channels", tdm_rx_chs,
2994 tdm_rx_ch_get,
2995 tdm_rx_ch_put),
2996 SOC_ENUM_EXT("QUIN_TDM_RX_2 Channels", tdm_rx_chs,
2997 tdm_rx_ch_get,
2998 tdm_rx_ch_put),
2999 SOC_ENUM_EXT("QUIN_TDM_RX_3 Channels", tdm_rx_chs,
3000 tdm_rx_ch_get,
3001 tdm_rx_ch_put),
3002 SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
3003 tdm_tx_ch_get,
3004 tdm_tx_ch_put),
3005 SOC_ENUM_EXT("QUIN_TDM_TX_1 Channels", tdm_tx_chs,
3006 tdm_tx_ch_get,
3007 tdm_tx_ch_put),
3008 SOC_ENUM_EXT("QUIN_TDM_TX_2 Channels", tdm_tx_chs,
3009 tdm_tx_ch_get,
3010 tdm_tx_ch_put),
3011 SOC_ENUM_EXT("QUIN_TDM_TX_3 Channels", tdm_tx_chs,
3012 tdm_tx_ch_get,
3013 tdm_tx_ch_put),
3014 SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num,
3015 tdm_slot_num_get, tdm_slot_num_put),
3016 SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width,
3017 tdm_slot_width_get, tdm_slot_width_put),
3018 SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num,
3019 tdm_slot_num_get, tdm_slot_num_put),
3020 SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width,
3021 tdm_slot_width_get, tdm_slot_width_put),
3022 SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num,
3023 tdm_slot_num_get, tdm_slot_num_put),
3024 SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width,
3025 tdm_slot_width_get, tdm_slot_width_put),
3026 SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num,
3027 tdm_slot_num_get, tdm_slot_num_put),
3028 SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width,
3029 tdm_slot_width_get, tdm_slot_width_put),
3030 SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num,
3031 tdm_slot_num_get, tdm_slot_num_put),
3032 SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width,
3033 tdm_slot_width_get, tdm_slot_width_put),
3034 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_0 SlotMapping",
3035 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3036 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3037 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_1 SlotMapping",
3038 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3039 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3040 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_2 SlotMapping",
3041 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3042 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3043 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_3 SlotMapping",
3044 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3045 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3046 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_0 SlotMapping",
3047 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3048 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3049 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_1 SlotMapping",
3050 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3051 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3052 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_2 SlotMapping",
3053 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3054 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3055 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_3 SlotMapping",
3056 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3057 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3058 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_0 SlotMapping",
3059 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3060 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3061 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_1 SlotMapping",
3062 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3063 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3064 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_2 SlotMapping",
3065 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3066 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3067 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_3 SlotMapping",
3068 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3069 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3070 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_0 SlotMapping",
3071 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3072 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3073 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_1 SlotMapping",
3074 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3075 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3076 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_2 SlotMapping",
3077 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3078 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3079 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_3 SlotMapping",
3080 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3081 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3082 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_0 SlotMapping",
3083 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3084 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3085 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_1 SlotMapping",
3086 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3087 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3088 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_2 SlotMapping",
3089 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3090 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3091 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_3 SlotMapping",
3092 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3093 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3094 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_4 SlotMapping",
3095 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3096 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3097 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_0 SlotMapping",
3098 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3099 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3100 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_1 SlotMapping",
3101 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3102 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3103 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_2 SlotMapping",
3104 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3105 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3106 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_3 SlotMapping",
3107 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3108 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3109 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_0 SlotMapping",
3110 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3111 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3112 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_1 SlotMapping",
3113 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3114 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3115 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_2 SlotMapping",
3116 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3117 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3118 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_3 SlotMapping",
3119 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3120 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3121 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_0 SlotMapping",
3122 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3123 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3124 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_1 SlotMapping",
3125 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3126 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3127 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_2 SlotMapping",
3128 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3129 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3130 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_3 SlotMapping",
3131 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3132 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3133 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_0 SlotMapping",
3134 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3135 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3136 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_1 SlotMapping",
3137 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3138 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3139 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_2 SlotMapping",
3140 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3141 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3142 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_3 SlotMapping",
3143 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3144 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3145 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_0 SlotMapping",
3146 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3147 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3148 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_1 SlotMapping",
3149 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3150 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3151 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_2 SlotMapping",
3152 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3153 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3154 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_3 SlotMapping",
3155 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3156 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3157 SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
3158 aux_pcm_rx_sample_rate_get,
3159 aux_pcm_rx_sample_rate_put),
3160 SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
3161 aux_pcm_rx_sample_rate_get,
3162 aux_pcm_rx_sample_rate_put),
3163 SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
3164 aux_pcm_rx_sample_rate_get,
3165 aux_pcm_rx_sample_rate_put),
3166 SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
3167 aux_pcm_rx_sample_rate_get,
3168 aux_pcm_rx_sample_rate_put),
3169 SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
3170 aux_pcm_rx_sample_rate_get,
3171 aux_pcm_rx_sample_rate_put),
3172 SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
3173 aux_pcm_tx_sample_rate_get,
3174 aux_pcm_tx_sample_rate_put),
3175 SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
3176 aux_pcm_tx_sample_rate_get,
3177 aux_pcm_tx_sample_rate_put),
3178 SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
3179 aux_pcm_tx_sample_rate_get,
3180 aux_pcm_tx_sample_rate_put),
3181 SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
3182 aux_pcm_tx_sample_rate_get,
3183 aux_pcm_tx_sample_rate_put),
3184 SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
3185 aux_pcm_tx_sample_rate_get,
3186 aux_pcm_tx_sample_rate_put),
3187 SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
3188 mi2s_rx_sample_rate_get,
3189 mi2s_rx_sample_rate_put),
3190 SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
3191 mi2s_rx_sample_rate_get,
3192 mi2s_rx_sample_rate_put),
3193 SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
3194 mi2s_rx_sample_rate_get,
3195 mi2s_rx_sample_rate_put),
3196 SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
3197 mi2s_rx_sample_rate_get,
3198 mi2s_rx_sample_rate_put),
3199 SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
3200 mi2s_rx_sample_rate_get,
3201 mi2s_rx_sample_rate_put),
3202 SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
3203 mi2s_tx_sample_rate_get,
3204 mi2s_tx_sample_rate_put),
3205 SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
3206 mi2s_tx_sample_rate_get,
3207 mi2s_tx_sample_rate_put),
3208 SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
3209 mi2s_tx_sample_rate_get,
3210 mi2s_tx_sample_rate_put),
3211 SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
3212 mi2s_tx_sample_rate_get,
3213 mi2s_tx_sample_rate_put),
3214 SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
3215 mi2s_tx_sample_rate_get,
3216 mi2s_tx_sample_rate_put),
3217 SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
3218 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3219 SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
3220 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3221 SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
3222 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3223 SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
3224 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3225 SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
3226 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3227 SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
3228 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3229 SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
3230 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3231 SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
3232 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3233 SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
3234 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3235 SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
3236 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3237 SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
3238 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3239 SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
3240 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3241 SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
3242 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3243 SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
3244 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3245 SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
3246 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3247 SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
3248 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3249 SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
3250 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3251 SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
3252 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3253 SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
3254 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3255 SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
3256 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3257 SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
3258 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3259 SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
3260 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3261 SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
3262 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3263 SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
3264 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3265 SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
3266 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3267 SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
3268 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3269 SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
3270 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3271 SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
3272 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3273 SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
3274 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3275 SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
3276 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3277};
3278
3279static inline int param_is_mask(int p)
3280{
3281 return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
3282 (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
3283}
3284
3285static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
3286 int n)
3287{
3288 return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
3289}
3290
3291static void param_set_mask(struct snd_pcm_hw_params *p, int n,
3292 unsigned int bit)
3293{
3294 if (bit >= SNDRV_MASK_MAX)
3295 return;
3296 if (param_is_mask(n)) {
3297 struct snd_mask *m = param_to_mask(p, n);
3298
3299 m->bits[0] = 0;
3300 m->bits[1] = 0;
3301 m->bits[bit >> 5] |= (1 << (bit & 31));
3302 }
3303}
3304
3305static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
3306{
3307 int idx;
3308
3309 switch (be_id) {
3310 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
3311 idx = DP_RX_IDX;
3312 break;
3313 default:
3314 pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
3315 idx = -EINVAL;
3316 break;
3317 }
3318
3319 return idx;
3320}
3321
3322static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
3323 struct snd_pcm_hw_params *params)
3324{
3325 struct snd_soc_dai_link *dai_link = rtd->dai_link;
3326 struct snd_interval *rate = hw_param_interval(params,
3327 SNDRV_PCM_HW_PARAM_RATE);
3328 struct snd_interval *channels = hw_param_interval(params,
3329 SNDRV_PCM_HW_PARAM_CHANNELS);
3330 int rc = 0;
3331 int idx;
3332
3333 pr_debug("%s: format = %d, rate = %d\n",
3334 __func__, params_format(params), params_rate(params));
3335
3336 switch (dai_link->id) {
3337 case MSM_BACKEND_DAI_USB_RX:
3338 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3339 usb_rx_cfg.bit_format);
3340 rate->min = rate->max = usb_rx_cfg.sample_rate;
3341 channels->min = channels->max = usb_rx_cfg.channels;
3342 break;
3343
3344 case MSM_BACKEND_DAI_USB_TX:
3345 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3346 usb_tx_cfg.bit_format);
3347 rate->min = rate->max = usb_tx_cfg.sample_rate;
3348 channels->min = channels->max = usb_tx_cfg.channels;
3349 break;
3350
3351 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
3352 idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
3353 if (idx < 0) {
3354 pr_err("%s: Incorrect ext disp idx %d\n",
3355 __func__, idx);
3356 rc = idx;
3357 goto done;
3358 }
3359
3360 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3361 ext_disp_rx_cfg[idx].bit_format);
3362 rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
3363 channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
3364 break;
3365
3366 case MSM_BACKEND_DAI_AFE_PCM_RX:
3367 channels->min = channels->max = proxy_rx_cfg.channels;
3368 rate->min = rate->max = SAMPLING_RATE_48KHZ;
3369 break;
3370
3371 case MSM_BACKEND_DAI_PRI_TDM_RX_0:
3372 channels->min = channels->max =
3373 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
3374 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3375 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
3376 rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
3377 break;
3378
3379 case MSM_BACKEND_DAI_PRI_TDM_TX_0:
3380 channels->min = channels->max =
3381 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
3382 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3383 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
3384 rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
3385 break;
3386
3387 case MSM_BACKEND_DAI_SEC_TDM_RX_0:
3388 channels->min = channels->max =
3389 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
3390 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3391 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
3392 rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
3393 break;
3394
3395 case MSM_BACKEND_DAI_SEC_TDM_TX_0:
3396 channels->min = channels->max =
3397 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
3398 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3399 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
3400 rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
3401 break;
3402
3403 case MSM_BACKEND_DAI_TERT_TDM_RX_0:
3404 channels->min = channels->max =
3405 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
3406 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3407 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
3408 rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
3409 break;
3410
3411 case MSM_BACKEND_DAI_TERT_TDM_TX_0:
3412 channels->min = channels->max =
3413 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
3414 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3415 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
3416 rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
3417 break;
3418
3419 case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
3420 channels->min = channels->max =
3421 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
3422 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3423 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
3424 rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
3425 break;
3426
3427 case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
3428 channels->min = channels->max =
3429 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
3430 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3431 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
3432 rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
3433 break;
3434
3435 case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
3436 channels->min = channels->max =
3437 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
3438 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3439 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
3440 rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
3441 break;
3442
3443 case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
3444 channels->min = channels->max =
3445 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
3446 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3447 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
3448 rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
3449 break;
3450
3451
3452 case MSM_BACKEND_DAI_AUXPCM_RX:
3453 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3454 aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
3455 rate->min = rate->max =
3456 aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
3457 channels->min = channels->max =
3458 aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
3459 break;
3460
3461 case MSM_BACKEND_DAI_AUXPCM_TX:
3462 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3463 aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
3464 rate->min = rate->max =
3465 aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
3466 channels->min = channels->max =
3467 aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
3468 break;
3469
3470 case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
3471 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3472 aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
3473 rate->min = rate->max =
3474 aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
3475 channels->min = channels->max =
3476 aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
3477 break;
3478
3479 case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
3480 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3481 aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
3482 rate->min = rate->max =
3483 aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
3484 channels->min = channels->max =
3485 aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
3486 break;
3487
3488 case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
3489 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3490 aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
3491 rate->min = rate->max =
3492 aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
3493 channels->min = channels->max =
3494 aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
3495 break;
3496
3497 case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
3498 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3499 aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
3500 rate->min = rate->max =
3501 aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
3502 channels->min = channels->max =
3503 aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
3504 break;
3505
3506 case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
3507 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3508 aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
3509 rate->min = rate->max =
3510 aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
3511 channels->min = channels->max =
3512 aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
3513 break;
3514
3515 case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
3516 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3517 aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
3518 rate->min = rate->max =
3519 aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
3520 channels->min = channels->max =
3521 aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
3522 break;
3523
3524 case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
3525 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3526 aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
3527 rate->min = rate->max =
3528 aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
3529 channels->min = channels->max =
3530 aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
3531 break;
3532
3533 case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
3534 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3535 aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
3536 rate->min = rate->max =
3537 aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
3538 channels->min = channels->max =
3539 aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
3540 break;
3541
3542 case MSM_BACKEND_DAI_PRI_MI2S_RX:
3543 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3544 mi2s_rx_cfg[PRIM_MI2S].bit_format);
3545 rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
3546 channels->min = channels->max =
3547 mi2s_rx_cfg[PRIM_MI2S].channels;
3548 break;
3549
3550 case MSM_BACKEND_DAI_PRI_MI2S_TX:
3551 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3552 mi2s_tx_cfg[PRIM_MI2S].bit_format);
3553 rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
3554 channels->min = channels->max =
3555 mi2s_tx_cfg[PRIM_MI2S].channels;
3556 break;
3557
3558 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
3559 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3560 mi2s_rx_cfg[SEC_MI2S].bit_format);
3561 rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
3562 channels->min = channels->max =
3563 mi2s_rx_cfg[SEC_MI2S].channels;
3564 break;
3565
3566 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
3567 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3568 mi2s_tx_cfg[SEC_MI2S].bit_format);
3569 rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
3570 channels->min = channels->max =
3571 mi2s_tx_cfg[SEC_MI2S].channels;
3572 break;
3573
3574 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
3575 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3576 mi2s_rx_cfg[TERT_MI2S].bit_format);
3577 rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
3578 channels->min = channels->max =
3579 mi2s_rx_cfg[TERT_MI2S].channels;
3580 break;
3581
3582 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
3583 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3584 mi2s_tx_cfg[TERT_MI2S].bit_format);
3585 rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
3586 channels->min = channels->max =
3587 mi2s_tx_cfg[TERT_MI2S].channels;
3588 break;
3589
3590 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
3591 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3592 mi2s_rx_cfg[QUAT_MI2S].bit_format);
3593 rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
3594 channels->min = channels->max =
3595 mi2s_rx_cfg[QUAT_MI2S].channels;
3596 break;
3597
3598 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
3599 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3600 mi2s_tx_cfg[QUAT_MI2S].bit_format);
3601 rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
3602 channels->min = channels->max =
3603 mi2s_tx_cfg[QUAT_MI2S].channels;
3604 break;
3605
3606 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
3607 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3608 mi2s_rx_cfg[QUIN_MI2S].bit_format);
3609 rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
3610 channels->min = channels->max =
3611 mi2s_rx_cfg[QUIN_MI2S].channels;
3612 break;
3613
3614 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
3615 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3616 mi2s_tx_cfg[QUIN_MI2S].bit_format);
3617 rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
3618 channels->min = channels->max =
3619 mi2s_tx_cfg[QUIN_MI2S].channels;
3620 break;
3621
3622 default:
3623 rate->min = rate->max = SAMPLING_RATE_48KHZ;
3624 break;
3625 }
3626
3627done:
3628 return rc;
3629}
3630
3631static int msm_get_port_id(int be_id)
3632{
3633 int afe_port_id;
3634
3635 switch (be_id) {
3636 case MSM_BACKEND_DAI_PRI_MI2S_RX:
3637 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
3638 break;
3639 case MSM_BACKEND_DAI_PRI_MI2S_TX:
3640 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
3641 break;
3642 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
3643 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
3644 break;
3645 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
3646 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
3647 break;
3648 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
3649 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
3650 break;
3651 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
3652 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
3653 break;
3654 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
3655 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
3656 break;
3657 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
3658 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
3659 break;
3660 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
3661 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
3662 break;
3663 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
3664 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
3665 break;
3666 default:
3667 pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
3668 afe_port_id = -EINVAL;
3669 }
3670
3671 return afe_port_id;
3672}
3673
3674static u32 get_mi2s_bits_per_sample(u32 bit_format)
3675{
3676 u32 bit_per_sample;
3677
3678 switch (bit_format) {
3679 case SNDRV_PCM_FORMAT_S32_LE:
3680 case SNDRV_PCM_FORMAT_S24_3LE:
3681 case SNDRV_PCM_FORMAT_S24_LE:
3682 bit_per_sample = 32;
3683 break;
3684 case SNDRV_PCM_FORMAT_S16_LE:
3685 default:
3686 bit_per_sample = 16;
3687 break;
3688 }
3689
3690 return bit_per_sample;
3691}
3692
3693static void update_mi2s_clk_val(int dai_id, int stream)
3694{
3695 u32 bit_per_sample;
3696
3697 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
3698 bit_per_sample =
3699 get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
3700 mi2s_clk[dai_id].clk_freq_in_hz =
3701 mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
3702 } else {
3703 bit_per_sample =
3704 get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
3705 mi2s_clk[dai_id].clk_freq_in_hz =
3706 mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
3707 }
3708}
3709
3710static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
3711{
3712 int ret = 0;
3713 struct snd_soc_pcm_runtime *rtd = substream->private_data;
3714 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
3715 int port_id = 0;
3716 int index = cpu_dai->id;
3717
3718 port_id = msm_get_port_id(rtd->dai_link->id);
3719 if (port_id < 0) {
3720 dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
3721 ret = port_id;
3722 goto err;
3723 }
3724
3725 if (enable) {
3726 update_mi2s_clk_val(index, substream->stream);
3727 dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
3728 mi2s_clk[index].clk_freq_in_hz);
3729 }
3730
3731 mi2s_clk[index].enable = enable;
3732 ret = afe_set_lpass_clock_v2(port_id,
3733 &mi2s_clk[index]);
3734 if (ret < 0) {
3735 dev_err(rtd->card->dev,
3736 "%s: afe lpass clock failed for port 0x%x , err:%d\n",
3737 __func__, port_id, ret);
3738 goto err;
3739 }
3740
3741err:
3742 return ret;
3743}
3744
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3745static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
3746 enum pinctrl_pin_state new_state)
3747{
3748 int ret = 0;
3749 int curr_state = 0;
3750
3751 if (pinctrl_info == NULL) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3752 pr_err("%s: pinctrl info is NULL\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3753 ret = -EINVAL;
3754 goto err;
3755 }
3756
3757 if (pinctrl_info->pinctrl == NULL) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3758 pr_err("%s: pinctrl handle is NULL\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3759 ret = -EINVAL;
3760 goto err;
3761 }
3762
3763 curr_state = pinctrl_info->curr_state;
3764 pinctrl_info->curr_state = new_state;
3765 pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
3766 pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
3767
3768 if (curr_state == pinctrl_info->curr_state) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3769 pr_debug("%s: pin already in same state\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3770 goto err;
3771 }
3772
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3773 if (curr_state != STATE_SLEEP &&
3774 pinctrl_info->curr_state != STATE_SLEEP) {
3775 pr_debug("%s: pin state is already active, cannot switch\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3776 ret = -EIO;
3777 goto err;
3778 }
3779
3780 switch (pinctrl_info->curr_state) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3781 case STATE_ACTIVE:
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3782 ret = pinctrl_select_state(pinctrl_info->pinctrl,
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3783 pinctrl_info->active);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3784 if (ret) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3785 pr_err("%s: state select to active failed with %d\n",
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3786 __func__, ret);
3787 ret = -EIO;
3788 goto err;
3789 }
3790 break;
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3791 case STATE_SLEEP:
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3792 ret = pinctrl_select_state(pinctrl_info->pinctrl,
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3793 pinctrl_info->sleep);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3794 if (ret) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3795 pr_err("%s: state select to sleep failed with %d\n",
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3796 __func__, ret);
3797 ret = -EIO;
3798 goto err;
3799 }
3800 break;
3801 default:
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3802 pr_err("%s: pin state is invalid\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3803 return -EINVAL;
3804 }
3805
3806err:
3807 return ret;
3808}
3809
3810static void msm_release_pinctrl(struct platform_device *pdev)
3811{
3812 struct snd_soc_card *card = platform_get_drvdata(pdev);
3813 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3814 struct msm_pinctrl_info *pinctrl_info = NULL;
3815 int i;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3816
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3817 for (i = TDM_PRI; i < TDM_INTERFACE_MAX; i++) {
3818 pinctrl_info = &pdata->pinctrl_info[i];
3819 if (pinctrl_info == NULL)
3820 continue;
3821 if (pinctrl_info->pinctrl) {
3822 devm_pinctrl_put(pinctrl_info->pinctrl);
3823 pinctrl_info->pinctrl = NULL;
3824 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3825 }
3826}
3827
3828static int msm_get_pinctrl(struct platform_device *pdev)
3829{
3830 struct snd_soc_card *card = platform_get_drvdata(pdev);
3831 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
3832 struct msm_pinctrl_info *pinctrl_info = NULL;
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3833 struct pinctrl *pinctrl = NULL;
3834 int i, j;
3835 struct device_node *np = NULL;
3836 struct platform_device *pdev_np = NULL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3837 int ret = 0;
3838
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3839 for (i = TDM_PRI; i < TDM_INTERFACE_MAX; i++) {
3840 np = of_parse_phandle(pdev->dev.of_node,
3841 tdm_gpio_phandle[i], 0);
3842 if (!np) {
3843 pr_debug("%s: device node %s is null\n",
3844 __func__, tdm_gpio_phandle[i]);
3845 continue;
3846 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3847
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3848 pdev_np = of_find_device_by_node(np);
3849 if (!pdev_np) {
3850 pr_err("%s: platform device not found\n", __func__);
3851 continue;
3852 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3853
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3854 pinctrl_info = &pdata->pinctrl_info[i];
3855 if (pinctrl_info == NULL) {
3856 pr_err("%s: pinctrl info is null\n", __func__);
3857 continue;
3858 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3859
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3860 pinctrl = devm_pinctrl_get(&pdev_np->dev);
3861 if (IS_ERR_OR_NULL(pinctrl)) {
3862 pr_err("%s: fail to get pinctrl handle\n", __func__);
3863 goto err;
3864 }
3865 pinctrl_info->pinctrl = pinctrl;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3866
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3867 /* get all the states handles from Device Tree */
3868 pinctrl_info->sleep = pinctrl_lookup_state(pinctrl,
3869 "sleep");
3870 if (IS_ERR(pinctrl_info->sleep)) {
3871 pr_err("%s: could not get sleep pin state\n", __func__);
3872 goto err;
3873 }
3874 pinctrl_info->active = pinctrl_lookup_state(pinctrl,
3875 "default");
3876 if (IS_ERR(pinctrl_info->active)) {
3877 pr_err("%s: could not get active pin state\n",
3878 __func__);
3879 goto err;
3880 }
3881
3882 /* Reset the TLMM pins to a sleep state */
3883 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3884 pinctrl_info->sleep);
3885 if (ret != 0) {
3886 pr_err("%s: set pin state to sleep failed with %d\n",
3887 __func__, ret);
3888 ret = -EIO;
3889 goto err;
3890 }
3891 pinctrl_info->curr_state = STATE_SLEEP;
3892 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3893 return 0;
3894
3895err:
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3896 for (j = i; j >= 0; j--) {
3897 pinctrl_info = &pdata->pinctrl_info[j];
3898 if (pinctrl_info == NULL)
3899 continue;
3900 if (pinctrl_info->pinctrl) {
3901 devm_pinctrl_put(pinctrl_info->pinctrl);
3902 pinctrl_info->pinctrl = NULL;
3903 }
3904 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3905 return -EINVAL;
3906}
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3907
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3908static int msm_tdm_get_intf_idx(u16 id)
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3909{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3910 switch (id) {
3911 case AFE_PORT_ID_PRIMARY_TDM_RX:
3912 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
3913 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
3914 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
3915 case AFE_PORT_ID_PRIMARY_TDM_RX_4:
3916 case AFE_PORT_ID_PRIMARY_TDM_RX_5:
3917 case AFE_PORT_ID_PRIMARY_TDM_RX_6:
3918 case AFE_PORT_ID_PRIMARY_TDM_RX_7:
3919 case AFE_PORT_ID_PRIMARY_TDM_TX:
3920 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
3921 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
3922 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
3923 case AFE_PORT_ID_PRIMARY_TDM_TX_4:
3924 case AFE_PORT_ID_PRIMARY_TDM_TX_5:
3925 case AFE_PORT_ID_PRIMARY_TDM_TX_6:
3926 case AFE_PORT_ID_PRIMARY_TDM_TX_7:
3927 return TDM_PRI;
3928 case AFE_PORT_ID_SECONDARY_TDM_RX:
3929 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
3930 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
3931 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
3932 case AFE_PORT_ID_SECONDARY_TDM_RX_4:
3933 case AFE_PORT_ID_SECONDARY_TDM_RX_5:
3934 case AFE_PORT_ID_SECONDARY_TDM_RX_6:
3935 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
3936 case AFE_PORT_ID_SECONDARY_TDM_TX:
3937 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
3938 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
3939 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
3940 case AFE_PORT_ID_SECONDARY_TDM_TX_4:
3941 case AFE_PORT_ID_SECONDARY_TDM_TX_5:
3942 case AFE_PORT_ID_SECONDARY_TDM_TX_6:
3943 case AFE_PORT_ID_SECONDARY_TDM_TX_7:
3944 return TDM_SEC;
3945 case AFE_PORT_ID_TERTIARY_TDM_RX:
3946 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
3947 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
3948 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
3949 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
3950 case AFE_PORT_ID_TERTIARY_TDM_RX_5:
3951 case AFE_PORT_ID_TERTIARY_TDM_RX_6:
3952 case AFE_PORT_ID_TERTIARY_TDM_RX_7:
3953 case AFE_PORT_ID_TERTIARY_TDM_TX:
3954 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
3955 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
3956 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
3957 case AFE_PORT_ID_TERTIARY_TDM_TX_4:
3958 case AFE_PORT_ID_TERTIARY_TDM_TX_5:
3959 case AFE_PORT_ID_TERTIARY_TDM_TX_6:
3960 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
3961 return TDM_TERT;
3962 case AFE_PORT_ID_QUATERNARY_TDM_RX:
3963 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
3964 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
3965 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
3966 case AFE_PORT_ID_QUATERNARY_TDM_RX_4:
3967 case AFE_PORT_ID_QUATERNARY_TDM_RX_5:
3968 case AFE_PORT_ID_QUATERNARY_TDM_RX_6:
3969 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
3970 case AFE_PORT_ID_QUATERNARY_TDM_TX:
3971 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
3972 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
3973 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
3974 case AFE_PORT_ID_QUATERNARY_TDM_TX_4:
3975 case AFE_PORT_ID_QUATERNARY_TDM_TX_5:
3976 case AFE_PORT_ID_QUATERNARY_TDM_TX_6:
3977 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
3978 return TDM_QUAT;
3979 case AFE_PORT_ID_QUINARY_TDM_RX:
3980 case AFE_PORT_ID_QUINARY_TDM_RX_1:
3981 case AFE_PORT_ID_QUINARY_TDM_RX_2:
3982 case AFE_PORT_ID_QUINARY_TDM_RX_3:
3983 case AFE_PORT_ID_QUINARY_TDM_RX_4:
3984 case AFE_PORT_ID_QUINARY_TDM_RX_5:
3985 case AFE_PORT_ID_QUINARY_TDM_RX_6:
3986 case AFE_PORT_ID_QUINARY_TDM_RX_7:
3987 case AFE_PORT_ID_QUINARY_TDM_TX:
3988 case AFE_PORT_ID_QUINARY_TDM_TX_1:
3989 case AFE_PORT_ID_QUINARY_TDM_TX_2:
3990 case AFE_PORT_ID_QUINARY_TDM_TX_3:
3991 case AFE_PORT_ID_QUINARY_TDM_TX_4:
3992 case AFE_PORT_ID_QUINARY_TDM_TX_5:
3993 case AFE_PORT_ID_QUINARY_TDM_TX_6:
3994 case AFE_PORT_ID_QUINARY_TDM_TX_7:
3995 return TDM_QUIN;
3996 default: return -EINVAL;
3997 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3998}
3999
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4000static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
4001 struct snd_pcm_hw_params *params)
4002{
4003 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4004 struct snd_interval *rate = hw_param_interval(params,
4005 SNDRV_PCM_HW_PARAM_RATE);
4006 struct snd_interval *channels = hw_param_interval(params,
4007 SNDRV_PCM_HW_PARAM_CHANNELS);
4008
4009 switch (cpu_dai->id) {
4010 case AFE_PORT_ID_PRIMARY_TDM_RX:
4011 channels->min = channels->max =
4012 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
4013 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4014 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
4015 rate->min = rate->max =
4016 tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
4017 break;
4018 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
4019 channels->min = channels->max =
4020 tdm_rx_cfg[TDM_PRI][TDM_1].channels;
4021 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4022 tdm_rx_cfg[TDM_PRI][TDM_1].bit_format);
4023 rate->min = rate->max =
4024 tdm_rx_cfg[TDM_PRI][TDM_1].sample_rate;
4025 break;
4026 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
4027 channels->min = channels->max =
4028 tdm_rx_cfg[TDM_PRI][TDM_2].channels;
4029 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4030 tdm_rx_cfg[TDM_PRI][TDM_2].bit_format);
4031 rate->min = rate->max =
4032 tdm_rx_cfg[TDM_PRI][TDM_2].sample_rate;
4033 break;
4034 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
4035 channels->min = channels->max =
4036 tdm_rx_cfg[TDM_PRI][TDM_3].channels;
4037 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4038 tdm_rx_cfg[TDM_PRI][TDM_3].bit_format);
4039 rate->min = rate->max =
4040 tdm_rx_cfg[TDM_PRI][TDM_3].sample_rate;
4041 break;
4042 case AFE_PORT_ID_PRIMARY_TDM_TX:
4043 channels->min = channels->max =
4044 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
4045 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4046 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
4047 rate->min = rate->max =
4048 tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
4049 break;
4050 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
4051 channels->min = channels->max =
4052 tdm_tx_cfg[TDM_PRI][TDM_1].channels;
4053 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4054 tdm_tx_cfg[TDM_PRI][TDM_1].bit_format);
4055 rate->min = rate->max =
4056 tdm_tx_cfg[TDM_PRI][TDM_1].sample_rate;
4057 break;
4058 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
4059 channels->min = channels->max =
4060 tdm_tx_cfg[TDM_PRI][TDM_2].channels;
4061 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4062 tdm_tx_cfg[TDM_PRI][TDM_2].bit_format);
4063 rate->min = rate->max =
4064 tdm_tx_cfg[TDM_PRI][TDM_2].sample_rate;
4065 break;
4066 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
4067 channels->min = channels->max =
4068 tdm_tx_cfg[TDM_PRI][TDM_3].channels;
4069 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4070 tdm_tx_cfg[TDM_PRI][TDM_3].bit_format);
4071 rate->min = rate->max =
4072 tdm_tx_cfg[TDM_PRI][TDM_3].sample_rate;
4073 break;
4074 case AFE_PORT_ID_SECONDARY_TDM_RX:
4075 channels->min = channels->max =
4076 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
4077 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4078 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
4079 rate->min = rate->max =
4080 tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
4081 break;
4082 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
4083 channels->min = channels->max =
4084 tdm_rx_cfg[TDM_SEC][TDM_1].channels;
4085 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4086 tdm_rx_cfg[TDM_SEC][TDM_1].bit_format);
4087 rate->min = rate->max =
4088 tdm_rx_cfg[TDM_SEC][TDM_1].sample_rate;
4089 break;
4090 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
4091 channels->min = channels->max =
4092 tdm_rx_cfg[TDM_SEC][TDM_2].channels;
4093 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4094 tdm_rx_cfg[TDM_SEC][TDM_2].bit_format);
4095 rate->min = rate->max =
4096 tdm_rx_cfg[TDM_SEC][TDM_2].sample_rate;
4097 break;
4098 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
4099 channels->min = channels->max =
4100 tdm_rx_cfg[TDM_SEC][TDM_3].channels;
4101 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4102 tdm_rx_cfg[TDM_SEC][TDM_3].bit_format);
4103 rate->min = rate->max =
4104 tdm_rx_cfg[TDM_SEC][TDM_3].sample_rate;
4105 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4106 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
4107 channels->min = channels->max =
4108 tdm_rx_cfg[TDM_SEC][TDM_7].channels;
4109 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4110 tdm_rx_cfg[TDM_SEC][TDM_7].bit_format);
4111 rate->min = rate->max =
4112 tdm_rx_cfg[TDM_SEC][TDM_7].sample_rate;
4113 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4114 case AFE_PORT_ID_SECONDARY_TDM_TX:
4115 channels->min = channels->max =
4116 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
4117 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4118 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
4119 rate->min = rate->max =
4120 tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
4121 break;
4122 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
4123 channels->min = channels->max =
4124 tdm_tx_cfg[TDM_SEC][TDM_1].channels;
4125 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4126 tdm_tx_cfg[TDM_SEC][TDM_1].bit_format);
4127 rate->min = rate->max =
4128 tdm_tx_cfg[TDM_SEC][TDM_1].sample_rate;
4129 break;
4130 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
4131 channels->min = channels->max =
4132 tdm_tx_cfg[TDM_SEC][TDM_2].channels;
4133 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4134 tdm_tx_cfg[TDM_SEC][TDM_2].bit_format);
4135 rate->min = rate->max =
4136 tdm_tx_cfg[TDM_SEC][TDM_2].sample_rate;
4137 break;
4138 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
4139 channels->min = channels->max =
4140 tdm_tx_cfg[TDM_SEC][TDM_3].channels;
4141 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4142 tdm_tx_cfg[TDM_SEC][TDM_3].bit_format);
4143 rate->min = rate->max =
4144 tdm_tx_cfg[TDM_SEC][TDM_3].sample_rate;
4145 break;
4146 case AFE_PORT_ID_TERTIARY_TDM_RX:
4147 channels->min = channels->max =
4148 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
4149 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4150 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
4151 rate->min = rate->max =
4152 tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
4153 break;
4154 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
4155 channels->min = channels->max =
4156 tdm_rx_cfg[TDM_TERT][TDM_1].channels;
4157 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4158 tdm_rx_cfg[TDM_TERT][TDM_1].bit_format);
4159 rate->min = rate->max =
4160 tdm_rx_cfg[TDM_TERT][TDM_1].sample_rate;
4161 break;
4162 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
4163 channels->min = channels->max =
4164 tdm_rx_cfg[TDM_TERT][TDM_2].channels;
4165 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4166 tdm_rx_cfg[TDM_TERT][TDM_2].bit_format);
4167 rate->min = rate->max =
4168 tdm_rx_cfg[TDM_TERT][TDM_2].sample_rate;
4169 break;
4170 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
4171 channels->min = channels->max =
4172 tdm_rx_cfg[TDM_TERT][TDM_3].channels;
4173 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4174 tdm_rx_cfg[TDM_TERT][TDM_3].bit_format);
4175 rate->min = rate->max =
4176 tdm_rx_cfg[TDM_TERT][TDM_3].sample_rate;
4177 break;
4178 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
4179 channels->min = channels->max =
4180 tdm_rx_cfg[TDM_TERT][TDM_4].channels;
4181 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4182 tdm_rx_cfg[TDM_TERT][TDM_4].bit_format);
4183 rate->min = rate->max =
4184 tdm_rx_cfg[TDM_TERT][TDM_4].sample_rate;
4185 break;
4186 case AFE_PORT_ID_TERTIARY_TDM_TX:
4187 channels->min = channels->max =
4188 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
4189 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4190 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
4191 rate->min = rate->max =
4192 tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
4193 break;
4194 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4195 channels->min = channels->max =
4196 tdm_tx_cfg[TDM_TERT][TDM_1].channels;
4197 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4198 tdm_tx_cfg[TDM_TERT][TDM_1].bit_format);
4199 rate->min = rate->max =
4200 tdm_tx_cfg[TDM_TERT][TDM_1].sample_rate;
4201 break;
4202 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4203 channels->min = channels->max =
4204 tdm_tx_cfg[TDM_TERT][TDM_2].channels;
4205 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4206 tdm_tx_cfg[TDM_TERT][TDM_2].bit_format);
4207 rate->min = rate->max =
4208 tdm_tx_cfg[TDM_TERT][TDM_2].sample_rate;
4209 break;
4210 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4211 channels->min = channels->max =
4212 tdm_tx_cfg[TDM_TERT][TDM_3].channels;
4213 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4214 tdm_tx_cfg[TDM_TERT][TDM_3].bit_format);
4215 rate->min = rate->max =
4216 tdm_tx_cfg[TDM_TERT][TDM_3].sample_rate;
4217 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4218 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
4219 channels->min = channels->max =
4220 tdm_tx_cfg[TDM_TERT][TDM_7].channels;
4221 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4222 tdm_tx_cfg[TDM_TERT][TDM_7].bit_format);
4223 rate->min = rate->max =
4224 tdm_tx_cfg[TDM_TERT][TDM_7].sample_rate;
4225 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4226 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4227 channels->min = channels->max =
4228 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
4229 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4230 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
4231 rate->min = rate->max =
4232 tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
4233 break;
4234 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4235 channels->min = channels->max =
4236 tdm_rx_cfg[TDM_QUAT][TDM_1].channels;
4237 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4238 tdm_rx_cfg[TDM_QUAT][TDM_1].bit_format);
4239 rate->min = rate->max =
4240 tdm_rx_cfg[TDM_QUAT][TDM_1].sample_rate;
4241 break;
4242 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4243 channels->min = channels->max =
4244 tdm_rx_cfg[TDM_QUAT][TDM_2].channels;
4245 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4246 tdm_rx_cfg[TDM_QUAT][TDM_2].bit_format);
4247 rate->min = rate->max =
4248 tdm_rx_cfg[TDM_QUAT][TDM_2].sample_rate;
4249 break;
4250 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4251 channels->min = channels->max =
4252 tdm_rx_cfg[TDM_QUAT][TDM_3].channels;
4253 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4254 tdm_rx_cfg[TDM_QUAT][TDM_3].bit_format);
4255 rate->min = rate->max =
4256 tdm_rx_cfg[TDM_QUAT][TDM_3].sample_rate;
4257 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4258 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
4259 channels->min = channels->max =
4260 tdm_rx_cfg[TDM_QUAT][TDM_7].channels;
4261 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4262 tdm_rx_cfg[TDM_QUAT][TDM_7].bit_format);
4263 rate->min = rate->max =
4264 tdm_rx_cfg[TDM_QUAT][TDM_7].sample_rate;
4265 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4266 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4267 channels->min = channels->max =
4268 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
4269 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4270 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
4271 rate->min = rate->max =
4272 tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
4273 break;
4274 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4275 channels->min = channels->max =
4276 tdm_tx_cfg[TDM_QUAT][TDM_1].channels;
4277 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4278 tdm_tx_cfg[TDM_QUAT][TDM_1].bit_format);
4279 rate->min = rate->max =
4280 tdm_tx_cfg[TDM_QUAT][TDM_1].sample_rate;
4281 break;
4282 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4283 channels->min = channels->max =
4284 tdm_tx_cfg[TDM_QUAT][TDM_2].channels;
4285 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4286 tdm_tx_cfg[TDM_QUAT][TDM_2].bit_format);
4287 rate->min = rate->max =
4288 tdm_tx_cfg[TDM_QUAT][TDM_2].sample_rate;
4289 break;
4290 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4291 channels->min = channels->max =
4292 tdm_tx_cfg[TDM_QUAT][TDM_3].channels;
4293 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4294 tdm_tx_cfg[TDM_QUAT][TDM_3].bit_format);
4295 rate->min = rate->max =
4296 tdm_tx_cfg[TDM_QUAT][TDM_3].sample_rate;
4297 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4298 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
4299 channels->min = channels->max =
4300 tdm_tx_cfg[TDM_QUAT][TDM_7].channels;
4301 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4302 tdm_tx_cfg[TDM_QUAT][TDM_7].bit_format);
4303 rate->min = rate->max =
4304 tdm_tx_cfg[TDM_QUAT][TDM_7].sample_rate;
4305 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4306 case AFE_PORT_ID_QUINARY_TDM_RX:
4307 channels->min = channels->max =
4308 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4309 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4310 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4311 rate->min = rate->max =
4312 tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4313 break;
4314 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4315 channels->min = channels->max =
4316 tdm_rx_cfg[TDM_QUIN][TDM_1].channels;
4317 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4318 tdm_rx_cfg[TDM_QUIN][TDM_1].bit_format);
4319 rate->min = rate->max =
4320 tdm_rx_cfg[TDM_QUIN][TDM_1].sample_rate;
4321 break;
4322 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4323 channels->min = channels->max =
4324 tdm_rx_cfg[TDM_QUIN][TDM_2].channels;
4325 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4326 tdm_rx_cfg[TDM_QUIN][TDM_2].bit_format);
4327 rate->min = rate->max =
4328 tdm_rx_cfg[TDM_QUIN][TDM_2].sample_rate;
4329 break;
4330 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4331 channels->min = channels->max =
4332 tdm_rx_cfg[TDM_QUIN][TDM_3].channels;
4333 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4334 tdm_rx_cfg[TDM_QUIN][TDM_3].bit_format);
4335 rate->min = rate->max =
4336 tdm_rx_cfg[TDM_QUIN][TDM_3].sample_rate;
4337 break;
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4338 case AFE_PORT_ID_QUINARY_TDM_RX_7:
4339 channels->min = channels->max =
4340 tdm_rx_cfg[TDM_QUIN][TDM_7].channels;
4341 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4342 tdm_rx_cfg[TDM_QUIN][TDM_7].bit_format);
4343 rate->min = rate->max =
4344 tdm_rx_cfg[TDM_QUIN][TDM_7].sample_rate;
4345 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4346 case AFE_PORT_ID_QUINARY_TDM_TX:
4347 channels->min = channels->max =
4348 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4349 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4350 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4351 rate->min = rate->max =
4352 tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4353 break;
4354 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4355 channels->min = channels->max =
4356 tdm_tx_cfg[TDM_QUIN][TDM_1].channels;
4357 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4358 tdm_tx_cfg[TDM_QUIN][TDM_1].bit_format);
4359 rate->min = rate->max =
4360 tdm_tx_cfg[TDM_QUIN][TDM_1].sample_rate;
4361 break;
4362 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4363 channels->min = channels->max =
4364 tdm_tx_cfg[TDM_QUIN][TDM_2].channels;
4365 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4366 tdm_tx_cfg[TDM_QUIN][TDM_2].bit_format);
4367 rate->min = rate->max =
4368 tdm_tx_cfg[TDM_QUIN][TDM_2].sample_rate;
4369 break;
4370 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4371 channels->min = channels->max =
4372 tdm_tx_cfg[TDM_QUIN][TDM_3].channels;
4373 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4374 tdm_tx_cfg[TDM_QUIN][TDM_3].bit_format);
4375 rate->min = rate->max =
4376 tdm_tx_cfg[TDM_QUIN][TDM_3].sample_rate;
4377 break;
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4378 case AFE_PORT_ID_QUINARY_TDM_TX_7:
4379 channels->min = channels->max =
4380 tdm_tx_cfg[TDM_QUIN][TDM_7].channels;
4381 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4382 tdm_tx_cfg[TDM_QUIN][TDM_7].bit_format);
4383 rate->min = rate->max =
4384 tdm_tx_cfg[TDM_QUIN][TDM_7].sample_rate;
4385 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4386 default:
4387 pr_err("%s: dai id 0x%x not supported\n",
4388 __func__, cpu_dai->id);
4389 return -EINVAL;
4390 }
4391
4392 pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
4393 __func__, cpu_dai->id, channels->max, rate->max,
4394 params_format(params));
4395
4396 return 0;
4397}
4398
4399static unsigned int tdm_param_set_slot_mask(int slots)
4400{
4401 unsigned int slot_mask = 0;
4402 int i = 0;
4403
4404 if ((slots <= 0) || (slots > 32)) {
4405 pr_err("%s: invalid slot number %d\n", __func__, slots);
4406 return -EINVAL;
4407 }
4408
4409 for (i = 0; i < slots ; i++)
4410 slot_mask |= 1 << i;
4411 return slot_mask;
4412}
4413
4414static int sa6155_tdm_snd_hw_params(struct snd_pcm_substream *substream,
4415 struct snd_pcm_hw_params *params)
4416{
4417 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4418 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4419 int ret = 0;
4420 int channels, slot_width, slots, rate, format;
4421 unsigned int slot_mask;
4422 unsigned int *slot_offset;
4423 int offset_channels = 0;
4424 int i;
4425 int clk_freq;
4426
4427 pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
4428
4429 channels = params_channels(params);
4430 if (channels < 1 || channels > 32) {
4431 pr_err("%s: invalid param channels %d\n",
4432 __func__, channels);
4433 return -EINVAL;
4434 }
4435
4436 format = params_format(params);
4437 if (format != SNDRV_PCM_FORMAT_S32_LE &&
4438 format != SNDRV_PCM_FORMAT_S24_LE &&
4439 format != SNDRV_PCM_FORMAT_S16_LE) {
4440 /*
4441 * Up to 8 channel HW configuration should
4442 * use 32 bit slot width for max support of
4443 * stream bit width. (slot_width > bit_width)
4444 */
4445 pr_err("%s: invalid param format 0x%x\n",
4446 __func__, format);
4447 return -EINVAL;
4448 }
4449
4450 switch (cpu_dai->id) {
4451 case AFE_PORT_ID_PRIMARY_TDM_RX:
4452 slots = tdm_slot[TDM_PRI].num;
4453 slot_width = tdm_slot[TDM_PRI].width;
4454 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_0];
4455 break;
4456 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
4457 slots = tdm_slot[TDM_PRI].num;
4458 slot_width = tdm_slot[TDM_PRI].width;
4459 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_1];
4460 break;
4461 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
4462 slots = tdm_slot[TDM_PRI].num;
4463 slot_width = tdm_slot[TDM_PRI].width;
4464 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_2];
4465 break;
4466 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
4467 slots = tdm_slot[TDM_PRI].num;
4468 slot_width = tdm_slot[TDM_PRI].width;
4469 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_3];
4470 break;
4471 case AFE_PORT_ID_PRIMARY_TDM_TX:
4472 slots = tdm_slot[TDM_PRI].num;
4473 slot_width = tdm_slot[TDM_PRI].width;
4474 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_0];
4475 break;
4476 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
4477 slots = tdm_slot[TDM_PRI].num;
4478 slot_width = tdm_slot[TDM_PRI].width;
4479 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_1];
4480 break;
4481 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
4482 slots = tdm_slot[TDM_PRI].num;
4483 slot_width = tdm_slot[TDM_PRI].width;
4484 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_2];
4485 break;
4486 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
4487 slots = tdm_slot[TDM_PRI].num;
4488 slot_width = tdm_slot[TDM_PRI].width;
4489 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_3];
4490 break;
4491 case AFE_PORT_ID_SECONDARY_TDM_RX:
4492 slots = tdm_slot[TDM_SEC].num;
4493 slot_width = tdm_slot[TDM_SEC].width;
4494 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_0];
4495 break;
4496 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
4497 slots = tdm_slot[TDM_SEC].num;
4498 slot_width = tdm_slot[TDM_SEC].width;
4499 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_1];
4500 break;
4501 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
4502 slots = tdm_slot[TDM_SEC].num;
4503 slot_width = tdm_slot[TDM_SEC].width;
4504 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_2];
4505 break;
4506 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
4507 slots = tdm_slot[TDM_SEC].num;
4508 slot_width = tdm_slot[TDM_SEC].width;
4509 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_3];
4510 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4511 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
4512 slots = tdm_slot[TDM_SEC].num;
4513 slot_width = tdm_slot[TDM_SEC].width;
4514 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_7];
4515 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4516 case AFE_PORT_ID_SECONDARY_TDM_TX:
4517 slots = tdm_slot[TDM_SEC].num;
4518 slot_width = tdm_slot[TDM_SEC].width;
4519 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_0];
4520 break;
4521 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
4522 slots = tdm_slot[TDM_SEC].num;
4523 slot_width = tdm_slot[TDM_SEC].width;
4524 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_1];
4525 break;
4526 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
4527 slots = tdm_slot[TDM_SEC].num;
4528 slot_width = tdm_slot[TDM_SEC].width;
4529 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_2];
4530 break;
4531 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
4532 slots = tdm_slot[TDM_SEC].num;
4533 slot_width = tdm_slot[TDM_SEC].width;
4534 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_3];
4535 break;
4536 case AFE_PORT_ID_TERTIARY_TDM_RX:
4537 slots = tdm_slot[TDM_TERT].num;
4538 slot_width = tdm_slot[TDM_TERT].width;
4539 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_0];
4540 break;
4541 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
4542 slots = tdm_slot[TDM_TERT].num;
4543 slot_width = tdm_slot[TDM_TERT].width;
4544 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_1];
4545 break;
4546 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
4547 slots = tdm_slot[TDM_TERT].num;
4548 slot_width = tdm_slot[TDM_TERT].width;
4549 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_2];
4550 break;
4551 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
4552 slots = tdm_slot[TDM_TERT].num;
4553 slot_width = tdm_slot[TDM_TERT].width;
4554 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_3];
4555 break;
4556 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
4557 slots = tdm_slot[TDM_TERT].num;
4558 slot_width = tdm_slot[TDM_TERT].width;
4559 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_4];
4560 break;
4561 case AFE_PORT_ID_TERTIARY_TDM_TX:
4562 slots = tdm_slot[TDM_TERT].num;
4563 slot_width = tdm_slot[TDM_TERT].width;
4564 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_0];
4565 break;
4566 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4567 slots = tdm_slot[TDM_TERT].num;
4568 slot_width = tdm_slot[TDM_TERT].width;
4569 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_1];
4570 break;
4571 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4572 slots = tdm_slot[TDM_TERT].num;
4573 slot_width = tdm_slot[TDM_TERT].width;
4574 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_2];
4575 break;
4576 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4577 slots = tdm_slot[TDM_TERT].num;
4578 slot_width = tdm_slot[TDM_TERT].width;
4579 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_3];
4580 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4581 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
4582 slots = tdm_slot[TDM_TERT].num;
4583 slot_width = tdm_slot[TDM_TERT].width;
4584 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_7];
4585 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4586 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4587 slots = tdm_slot[TDM_QUAT].num;
4588 slot_width = tdm_slot[TDM_QUAT].width;
4589 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_0];
4590 break;
4591 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4592 slots = tdm_slot[TDM_QUAT].num;
4593 slot_width = tdm_slot[TDM_QUAT].width;
4594 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_1];
4595 break;
4596 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4597 slots = tdm_slot[TDM_QUAT].num;
4598 slot_width = tdm_slot[TDM_QUAT].width;
4599 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_2];
4600 break;
4601 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4602 slots = tdm_slot[TDM_QUAT].num;
4603 slot_width = tdm_slot[TDM_QUAT].width;
4604 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_3];
4605 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4606 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
4607 slots = tdm_slot[TDM_QUAT].num;
4608 slot_width = tdm_slot[TDM_QUAT].width;
4609 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_7];
4610 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4611 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4612 slots = tdm_slot[TDM_QUAT].num;
4613 slot_width = tdm_slot[TDM_QUAT].width;
4614 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_0];
4615 break;
4616 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4617 slots = tdm_slot[TDM_QUAT].num;
4618 slot_width = tdm_slot[TDM_QUAT].width;
4619 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_1];
4620 break;
4621 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4622 slots = tdm_slot[TDM_QUAT].num;
4623 slot_width = tdm_slot[TDM_QUAT].width;
4624 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_2];
4625 break;
4626 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4627 slots = tdm_slot[TDM_QUAT].num;
4628 slot_width = tdm_slot[TDM_QUAT].width;
4629 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_3];
4630 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4631 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
4632 slots = tdm_slot[TDM_QUAT].num;
4633 slot_width = tdm_slot[TDM_QUAT].width;
4634 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_7];
4635 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4636 case AFE_PORT_ID_QUINARY_TDM_RX:
4637 slots = tdm_slot[TDM_QUIN].num;
4638 slot_width = tdm_slot[TDM_QUIN].width;
4639 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_0];
4640 break;
4641 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4642 slots = tdm_slot[TDM_QUIN].num;
4643 slot_width = tdm_slot[TDM_QUIN].width;
4644 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_1];
4645 break;
4646 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4647 slots = tdm_slot[TDM_QUIN].num;
4648 slot_width = tdm_slot[TDM_QUIN].width;
4649 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_2];
4650 break;
4651 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4652 slots = tdm_slot[TDM_QUIN].num;
4653 slot_width = tdm_slot[TDM_QUIN].width;
4654 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_3];
4655 break;
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4656 case AFE_PORT_ID_QUINARY_TDM_RX_7:
4657 slots = tdm_slot[TDM_QUIN].num;
4658 slot_width = tdm_slot[TDM_QUIN].width;
4659 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_7];
4660 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4661 case AFE_PORT_ID_QUINARY_TDM_TX:
4662 slots = tdm_slot[TDM_QUIN].num;
4663 slot_width = tdm_slot[TDM_QUIN].width;
4664 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_0];
4665 break;
4666 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4667 slots = tdm_slot[TDM_QUIN].num;
4668 slot_width = tdm_slot[TDM_QUIN].width;
4669 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_1];
4670 break;
4671 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4672 slots = tdm_slot[TDM_QUIN].num;
4673 slot_width = tdm_slot[TDM_QUIN].width;
4674 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_2];
4675 break;
4676 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4677 slots = tdm_slot[TDM_QUIN].num;
4678 slot_width = tdm_slot[TDM_QUIN].width;
4679 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_3];
4680 break;
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4681 case AFE_PORT_ID_QUINARY_TDM_TX_7:
4682 slots = tdm_slot[TDM_QUIN].num;
4683 slot_width = tdm_slot[TDM_QUIN].width;
4684 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_7];
4685 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4686 default:
4687 pr_err("%s: dai id 0x%x not supported\n",
4688 __func__, cpu_dai->id);
4689 return -EINVAL;
4690 }
4691
4692 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
4693 if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID)
4694 offset_channels++;
4695 else
4696 break;
4697 }
4698
4699 if (offset_channels == 0) {
4700 pr_err("%s: invalid offset_channels %d\n",
4701 __func__, offset_channels);
4702 return -EINVAL;
4703 }
4704
4705 if (channels > offset_channels) {
4706 pr_err("%s: channels %d exceed offset_channels %d\n",
4707 __func__, channels, offset_channels);
4708 return -EINVAL;
4709 }
4710
4711 slot_mask = tdm_param_set_slot_mask(slots);
4712 if (!slot_mask) {
4713 pr_err("%s: invalid slot_mask 0x%x\n",
4714 __func__, slot_mask);
4715 return -EINVAL;
4716 }
4717
4718 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4719 ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
4720 slots, slot_width);
4721 if (ret < 0) {
4722 pr_err("%s: failed to set tdm slot, err:%d\n",
4723 __func__, ret);
4724 goto end;
4725 }
4726
4727 ret = snd_soc_dai_set_channel_map(cpu_dai,
4728 0, NULL, channels, slot_offset);
4729 if (ret < 0) {
4730 pr_err("%s: failed to set channel map, err:%d\n",
4731 __func__, ret);
4732 goto end;
4733 }
4734 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
4735 ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
4736 slots, slot_width);
4737 if (ret < 0) {
4738 pr_err("%s: failed to set tdm slot, err:%d\n",
4739 __func__, ret);
4740 goto end;
4741 }
4742
4743 ret = snd_soc_dai_set_channel_map(cpu_dai,
4744 channels, slot_offset, 0, NULL);
4745 if (ret < 0) {
4746 pr_err("%s: failed to set channel map, err:%d\n",
4747 __func__, ret);
4748 goto end;
4749 }
4750 } else {
4751 ret = -EINVAL;
4752 pr_err("%s: invalid use case, err:%d\n",
4753 __func__, ret);
4754 goto end;
4755 }
4756
4757 rate = params_rate(params);
4758 clk_freq = rate * slot_width * slots;
4759 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
4760 if (ret < 0)
4761 pr_err("%s: failed to set tdm clk, err:%d\n",
4762 __func__, ret);
4763
4764end:
4765 return ret;
4766}
4767
4768static int sa6155_tdm_snd_startup(struct snd_pcm_substream *substream)
4769{
4770 int ret = 0;
4771 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4772 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4773 struct snd_soc_card *card = rtd->card;
4774 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4775 struct msm_pinctrl_info *pinctrl_info = NULL;
4776 struct tdm_conf *intf_conf = NULL;
4777 int ret_pinctrl = 0;
4778 int index;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4779
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4780 pr_debug("%s: substream = %s, stream = %d, dai name = %s, dai id = %d\n",
4781 __func__, substream->name, substream->stream,
4782 cpu_dai->name, cpu_dai->id);
4783
4784 index = msm_tdm_get_intf_idx(cpu_dai->id);
4785 if (index < 0) {
4786 ret = -EINVAL;
4787 pr_err("%s: CPU DAI id (%d) out of range\n",
4788 __func__, cpu_dai->id);
4789 goto err;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4790 }
4791
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4792 /*
4793 * Mutex protection in case the same TDM
4794 * interface using for both TX and RX so
4795 * that the same clock won't be enable twice.
4796 */
4797 intf_conf = &pdata->tdm_intf_conf[index];
4798 mutex_lock(&intf_conf->lock);
4799 if (++intf_conf->ref_cnt == 1) {
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4800 if (index == TDM_TERT || index == TDM_QUAT ||
4801 index == TDM_QUIN) {
4802 pinctrl_info = &pdata->pinctrl_info[index];
Derek Chenbbce3832019-11-27 15:21:56 -0800[diff] [blame]4803 if (pinctrl_info->pinctrl) {
4804 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4805 STATE_ACTIVE);
4806 if (ret_pinctrl)
4807 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
4808 __func__, ret_pinctrl);
4809 }
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4810 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4811 }
4812 mutex_unlock(&intf_conf->lock);
4813
4814err:
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4815 return ret;
4816}
4817
4818static void sa6155_tdm_snd_shutdown(struct snd_pcm_substream *substream)
4819{
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4820 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4821 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4822 struct snd_soc_card *card = rtd->card;
4823 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4824 struct msm_pinctrl_info *pinctrl_info = NULL;
4825 struct tdm_conf *intf_conf = NULL;
4826 int ret_pinctrl = 0;
4827 int index;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4828
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4829 pr_debug("%s: substream = %s, stream = %d\n", __func__,
4830 substream->name, substream->stream);
4831
4832 index = msm_tdm_get_intf_idx(cpu_dai->id);
4833 if (index < 0) {
4834 pr_err("%s: CPU DAI id (%d) out of range\n",
4835 __func__, cpu_dai->id);
4836 return;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4837 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4838
4839 intf_conf = &pdata->tdm_intf_conf[index];
4840 mutex_lock(&intf_conf->lock);
4841 if (--intf_conf->ref_cnt == 0) {
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4842 if (index == TDM_TERT || index == TDM_QUAT ||
4843 index == TDM_QUIN) {
4844 pinctrl_info = &pdata->pinctrl_info[index];
Derek Chenbbce3832019-11-27 15:21:56 -0800[diff] [blame]4845 if (pinctrl_info->pinctrl) {
4846 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4847 STATE_SLEEP);
4848 if (ret_pinctrl)
4849 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
4850 __func__, ret_pinctrl);
4851 }
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4852 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4853 }
4854 mutex_unlock(&intf_conf->lock);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4855}
4856
4857static struct snd_soc_ops sa6155_tdm_be_ops = {
4858 .hw_params = sa6155_tdm_snd_hw_params,
4859 .startup = sa6155_tdm_snd_startup,
4860 .shutdown = sa6155_tdm_snd_shutdown
4861};
4862
4863static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
4864{
4865 cpumask_t mask;
4866
4867 if (pm_qos_request_active(&substream->latency_pm_qos_req))
4868 pm_qos_remove_request(&substream->latency_pm_qos_req);
4869
4870 cpumask_clear(&mask);
4871 cpumask_set_cpu(1, &mask); /* affine to core 1 */
4872 cpumask_set_cpu(2, &mask); /* affine to core 2 */
4873 cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
4874
4875 substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
4876
4877 pm_qos_add_request(&substream->latency_pm_qos_req,
4878 PM_QOS_CPU_DMA_LATENCY,
4879 MSM_LL_QOS_VALUE);
4880 return 0;
4881}
4882
4883static struct snd_soc_ops msm_fe_qos_ops = {
4884 .prepare = msm_fe_qos_prepare,
4885};
4886
4887static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
4888{
4889 int ret = 0;
4890 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4891 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4892 int index = cpu_dai->id;
4893 unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
4894 struct snd_soc_card *card = rtd->card;
4895 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4896 struct msm_pinctrl_info *pinctrl_info = NULL;
4897 struct mi2s_conf *intf_conf = NULL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4898 int ret_pinctrl = 0;
4899
4900 dev_dbg(rtd->card->dev,
4901 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4902 __func__, substream->name, substream->stream,
4903 cpu_dai->name, cpu_dai->id);
4904
4905 if (index < PRIM_MI2S || index >= MI2S_MAX) {
4906 ret = -EINVAL;
4907 dev_err(rtd->card->dev,
4908 "%s: CPU DAI id (%d) out of range\n",
4909 __func__, cpu_dai->id);
4910 goto err;
4911 }
4912 /*
4913 * Mutex protection in case the same MI2S
4914 * interface using for both TX and RX so
4915 * that the same clock won't be enable twice.
4916 */
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4917 intf_conf = &pdata->mi2s_intf_conf[index];
4918 mutex_lock(&intf_conf->lock);
4919 if (++intf_conf->ref_cnt == 1) {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4920 /* Check if msm needs to provide the clock to the interface */
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4921 if (!intf_conf->msm_is_mi2s_master) {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4922 mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
4923 fmt = SND_SOC_DAIFMT_CBM_CFM;
4924 }
4925 ret = msm_mi2s_set_sclk(substream, true);
4926 if (ret < 0) {
4927 dev_err(rtd->card->dev,
4928 "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
4929 __func__, ret);
4930 goto clean_up;
4931 }
4932
4933 ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
4934 if (ret < 0) {
4935 pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
4936 __func__, index, ret);
4937 goto clk_off;
4938 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4939
4940 pinctrl_info = &pdata->pinctrl_info[index];
Derek Chenbbce3832019-11-27 15:21:56 -0800[diff] [blame]4941 if (pinctrl_info->pinctrl) {
4942 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4943 STATE_ACTIVE);
4944 if (ret_pinctrl)
4945 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
4946 __func__, ret_pinctrl);
4947 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4948 }
4949clk_off:
4950 if (ret < 0)
4951 msm_mi2s_set_sclk(substream, false);
4952clean_up:
4953 if (ret < 0)
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4954 intf_conf->ref_cnt--;
4955 mutex_unlock(&intf_conf->lock);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4956err:
4957 return ret;
4958}
4959
4960static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
4961{
4962 int ret;
4963 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4964 int index = rtd->cpu_dai->id;
4965 struct snd_soc_card *card = rtd->card;
4966 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4967 struct msm_pinctrl_info *pinctrl_info = NULL;
4968 struct mi2s_conf *intf_conf = NULL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4969 int ret_pinctrl = 0;
4970
4971 pr_debug("%s(): substream = %s stream = %d\n", __func__,
4972 substream->name, substream->stream);
4973 if (index < PRIM_MI2S || index >= MI2S_MAX) {
4974 pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
4975 return;
4976 }
4977
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4978 intf_conf = &pdata->mi2s_intf_conf[index];
4979 mutex_lock(&intf_conf->lock);
4980 if (--intf_conf->ref_cnt == 0) {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4981 ret = msm_mi2s_set_sclk(substream, false);
4982 if (ret < 0)
4983 pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
4984 __func__, index, ret);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4985
4986 pinctrl_info = &pdata->pinctrl_info[index];
Derek Chenbbce3832019-11-27 15:21:56 -0800[diff] [blame]4987 if (pinctrl_info->pinctrl) {
4988 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4989 STATE_SLEEP);
4990 if (ret_pinctrl)
4991 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
4992 __func__, ret_pinctrl);
4993 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4994 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4995 mutex_unlock(&intf_conf->lock);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4996}
4997
4998static struct snd_soc_ops msm_mi2s_be_ops = {
4999 .startup = msm_mi2s_snd_startup,
5000 .shutdown = msm_mi2s_snd_shutdown,
5001};
5002
5003
5004/* Digital audio interface glue - connects codec <---> CPU */
5005static struct snd_soc_dai_link msm_common_dai_links[] = {
5006 /* FrontEnd DAI Links */
5007 {
5008 .name = MSM_DAILINK_NAME(Media1),
5009 .stream_name = "MultiMedia1",
5010 .cpu_dai_name = "MultiMedia1",
5011 .platform_name = "msm-pcm-dsp.0",
5012 .dynamic = 1,
5013 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5014 .dpcm_playback = 1,
5015 .dpcm_capture = 1,
5016 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5017 SND_SOC_DPCM_TRIGGER_POST},
5018 .codec_dai_name = "snd-soc-dummy-dai",
5019 .codec_name = "snd-soc-dummy",
5020 .ignore_suspend = 1,
5021 /* this dainlink has playback support */
5022 .ignore_pmdown_time = 1,
5023 .id = MSM_FRONTEND_DAI_MULTIMEDIA1
5024 },
5025 {
5026 .name = MSM_DAILINK_NAME(Media2),
5027 .stream_name = "MultiMedia2",
5028 .cpu_dai_name = "MultiMedia2",
5029 .platform_name = "msm-pcm-dsp.0",
5030 .dynamic = 1,
5031 .dpcm_playback = 1,
5032 .dpcm_capture = 1,
5033 .codec_dai_name = "snd-soc-dummy-dai",
5034 .codec_name = "snd-soc-dummy",
5035 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5036 SND_SOC_DPCM_TRIGGER_POST},
5037 .ignore_suspend = 1,
5038 /* this dainlink has playback support */
5039 .ignore_pmdown_time = 1,
5040 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
5041 },
5042 {
5043 .name = "VoiceMMode1",
5044 .stream_name = "VoiceMMode1",
5045 .cpu_dai_name = "VoiceMMode1",
5046 .platform_name = "msm-pcm-voice",
5047 .dynamic = 1,
5048 .dpcm_playback = 1,
5049 .dpcm_capture = 1,
5050 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5051 SND_SOC_DPCM_TRIGGER_POST},
5052 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5053 .ignore_suspend = 1,
5054 .ignore_pmdown_time = 1,
5055 .codec_dai_name = "snd-soc-dummy-dai",
5056 .codec_name = "snd-soc-dummy",
5057 .id = MSM_FRONTEND_DAI_VOICEMMODE1,
5058 },
5059 {
5060 .name = "MSM VoIP",
5061 .stream_name = "VoIP",
5062 .cpu_dai_name = "VoIP",
5063 .platform_name = "msm-voip-dsp",
5064 .dynamic = 1,
5065 .dpcm_playback = 1,
5066 .dpcm_capture = 1,
5067 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5068 SND_SOC_DPCM_TRIGGER_POST},
5069 .codec_dai_name = "snd-soc-dummy-dai",
5070 .codec_name = "snd-soc-dummy",
5071 .ignore_suspend = 1,
5072 /* this dainlink has playback support */
5073 .ignore_pmdown_time = 1,
5074 .id = MSM_FRONTEND_DAI_VOIP,
5075 },
5076 {
5077 .name = MSM_DAILINK_NAME(ULL),
5078 .stream_name = "MultiMedia3",
5079 .cpu_dai_name = "MultiMedia3",
5080 .platform_name = "msm-pcm-dsp.2",
5081 .dynamic = 1,
5082 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5083 .dpcm_playback = 1,
5084 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5085 SND_SOC_DPCM_TRIGGER_POST},
5086 .codec_dai_name = "snd-soc-dummy-dai",
5087 .codec_name = "snd-soc-dummy",
5088 .ignore_suspend = 1,
5089 /* this dainlink has playback support */
5090 .ignore_pmdown_time = 1,
5091 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
5092 },
5093 /* - SLIMBUS_0 Hostless */
5094 {
5095 .name = "MSM AFE-PCM RX",
5096 .stream_name = "AFE-PROXY RX",
5097 .cpu_dai_name = "msm-dai-q6-dev.241",
5098 .codec_name = "msm-stub-codec.1",
5099 .codec_dai_name = "msm-stub-rx",
5100 .platform_name = "msm-pcm-afe",
5101 .dpcm_playback = 1,
5102 .ignore_suspend = 1,
5103 /* this dainlink has playback support */
5104 .ignore_pmdown_time = 1,
5105 },
5106 {
5107 .name = "MSM AFE-PCM TX",
5108 .stream_name = "AFE-PROXY TX",
5109 .cpu_dai_name = "msm-dai-q6-dev.240",
5110 .codec_name = "msm-stub-codec.1",
5111 .codec_dai_name = "msm-stub-tx",
5112 .platform_name = "msm-pcm-afe",
5113 .dpcm_capture = 1,
5114 .ignore_suspend = 1,
5115 },
5116 {
5117 .name = MSM_DAILINK_NAME(Compress1),
5118 .stream_name = "Compress1",
5119 .cpu_dai_name = "MultiMedia4",
5120 .platform_name = "msm-compress-dsp",
5121 .dynamic = 1,
5122 .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
5123 .dpcm_playback = 1,
5124 .dpcm_capture = 1,
5125 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5126 SND_SOC_DPCM_TRIGGER_POST},
5127 .codec_dai_name = "snd-soc-dummy-dai",
5128 .codec_name = "snd-soc-dummy",
5129 .ignore_suspend = 1,
5130 .ignore_pmdown_time = 1,
5131 /* this dainlink has playback support */
5132 .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
5133 },
5134 /* Hostless PCM purpose */
5135 {
5136 .name = "AUXPCM Hostless",
5137 .stream_name = "AUXPCM Hostless",
5138 .cpu_dai_name = "AUXPCM_HOSTLESS",
5139 .platform_name = "msm-pcm-hostless",
5140 .dynamic = 1,
5141 .dpcm_playback = 1,
5142 .dpcm_capture = 1,
5143 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5144 SND_SOC_DPCM_TRIGGER_POST},
5145 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5146 .ignore_suspend = 1,
5147 /* this dainlink has playback support */
5148 .ignore_pmdown_time = 1,
5149 .codec_dai_name = "snd-soc-dummy-dai",
5150 .codec_name = "snd-soc-dummy",
5151 },
5152 /* - SLIMBUS_1 Hostless */
5153 /* - SLIMBUS_3 Hostless */
5154 /* - SLIMBUS_4 Hostless */
5155 {
5156 .name = MSM_DAILINK_NAME(LowLatency),
5157 .stream_name = "MultiMedia5",
5158 .cpu_dai_name = "MultiMedia5",
5159 .platform_name = "msm-pcm-dsp.1",
5160 .dynamic = 1,
5161 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5162 .dpcm_playback = 1,
5163 .dpcm_capture = 1,
5164 .codec_dai_name = "snd-soc-dummy-dai",
5165 .codec_name = "snd-soc-dummy",
5166 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5167 SND_SOC_DPCM_TRIGGER_POST},
5168 .ignore_suspend = 1,
5169 /* this dainlink has playback support */
5170 .ignore_pmdown_time = 1,
5171 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
5172 .ops = &msm_fe_qos_ops,
5173 },
5174 {
5175 .name = "Listen 1 Audio Service",
5176 .stream_name = "Listen 1 Audio Service",
5177 .cpu_dai_name = "LSM1",
5178 .platform_name = "msm-lsm-client",
5179 .dynamic = 1,
5180 .dpcm_capture = 1,
5181 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5182 SND_SOC_DPCM_TRIGGER_POST },
5183 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5184 .ignore_suspend = 1,
5185 .codec_dai_name = "snd-soc-dummy-dai",
5186 .codec_name = "snd-soc-dummy",
5187 .id = MSM_FRONTEND_DAI_LSM1,
5188 },
5189 /* Multiple Tunnel instances */
5190 {
5191 .name = MSM_DAILINK_NAME(Compress2),
5192 .stream_name = "Compress2",
5193 .cpu_dai_name = "MultiMedia7",
5194 .platform_name = "msm-compress-dsp",
5195 .dynamic = 1,
5196 .dpcm_playback = 1,
5197 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5198 SND_SOC_DPCM_TRIGGER_POST},
5199 .codec_dai_name = "snd-soc-dummy-dai",
5200 .codec_name = "snd-soc-dummy",
5201 .ignore_suspend = 1,
5202 .ignore_pmdown_time = 1,
5203 /* this dainlink has playback support */
5204 .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
5205 },
5206 {
5207 .name = MSM_DAILINK_NAME(MultiMedia10),
5208 .stream_name = "MultiMedia10",
5209 .cpu_dai_name = "MultiMedia10",
5210 .platform_name = "msm-pcm-dsp.1",
5211 .dynamic = 1,
5212 .dpcm_playback = 1,
5213 .dpcm_capture = 1,
5214 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5215 SND_SOC_DPCM_TRIGGER_POST},
5216 .codec_dai_name = "snd-soc-dummy-dai",
5217 .codec_name = "snd-soc-dummy",
5218 .ignore_suspend = 1,
5219 .ignore_pmdown_time = 1,
5220 /* this dainlink has playback support */
5221 .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
5222 },
5223 {
5224 .name = MSM_DAILINK_NAME(ULL_NOIRQ),
5225 .stream_name = "MM_NOIRQ",
5226 .cpu_dai_name = "MultiMedia8",
5227 .platform_name = "msm-pcm-dsp-noirq",
5228 .dynamic = 1,
5229 .dpcm_playback = 1,
5230 .dpcm_capture = 1,
5231 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5232 SND_SOC_DPCM_TRIGGER_POST},
5233 .codec_dai_name = "snd-soc-dummy-dai",
5234 .codec_name = "snd-soc-dummy",
5235 .ignore_suspend = 1,
5236 .ignore_pmdown_time = 1,
5237 /* this dainlink has playback support */
5238 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
5239 .ops = &msm_fe_qos_ops,
5240 },
5241 /* HDMI Hostless */
5242 {
5243 .name = "HDMI_RX_HOSTLESS",
5244 .stream_name = "HDMI_RX_HOSTLESS",
5245 .cpu_dai_name = "HDMI_HOSTLESS",
5246 .platform_name = "msm-pcm-hostless",
5247 .dynamic = 1,
5248 .dpcm_playback = 1,
5249 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5250 SND_SOC_DPCM_TRIGGER_POST},
5251 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5252 .ignore_suspend = 1,
5253 .ignore_pmdown_time = 1,
5254 .codec_dai_name = "snd-soc-dummy-dai",
5255 .codec_name = "snd-soc-dummy",
5256 },
5257 {
5258 .name = "VoiceMMode2",
5259 .stream_name = "VoiceMMode2",
5260 .cpu_dai_name = "VoiceMMode2",
5261 .platform_name = "msm-pcm-voice",
5262 .dynamic = 1,
5263 .dpcm_playback = 1,
5264 .dpcm_capture = 1,
5265 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5266 SND_SOC_DPCM_TRIGGER_POST},
5267 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5268 .ignore_suspend = 1,
5269 .ignore_pmdown_time = 1,
5270 .codec_dai_name = "snd-soc-dummy-dai",
5271 .codec_name = "snd-soc-dummy",
5272 .id = MSM_FRONTEND_DAI_VOICEMMODE2,
5273 },
5274 /* LSM FE */
5275 {
5276 .name = "Listen 2 Audio Service",
5277 .stream_name = "Listen 2 Audio Service",
5278 .cpu_dai_name = "LSM2",
5279 .platform_name = "msm-lsm-client",
5280 .dynamic = 1,
5281 .dpcm_capture = 1,
5282 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5283 SND_SOC_DPCM_TRIGGER_POST },
5284 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5285 .ignore_suspend = 1,
5286 .codec_dai_name = "snd-soc-dummy-dai",
5287 .codec_name = "snd-soc-dummy",
5288 .id = MSM_FRONTEND_DAI_LSM2,
5289 },
5290 {
5291 .name = "Listen 3 Audio Service",
5292 .stream_name = "Listen 3 Audio Service",
5293 .cpu_dai_name = "LSM3",
5294 .platform_name = "msm-lsm-client",
5295 .dynamic = 1,
5296 .dpcm_capture = 1,
5297 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5298 SND_SOC_DPCM_TRIGGER_POST },
5299 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5300 .ignore_suspend = 1,
5301 .codec_dai_name = "snd-soc-dummy-dai",
5302 .codec_name = "snd-soc-dummy",
5303 .id = MSM_FRONTEND_DAI_LSM3,
5304 },
5305 {
5306 .name = "Listen 4 Audio Service",
5307 .stream_name = "Listen 4 Audio Service",
5308 .cpu_dai_name = "LSM4",
5309 .platform_name = "msm-lsm-client",
5310 .dynamic = 1,
5311 .dpcm_capture = 1,
5312 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5313 SND_SOC_DPCM_TRIGGER_POST },
5314 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5315 .ignore_suspend = 1,
5316 .codec_dai_name = "snd-soc-dummy-dai",
5317 .codec_name = "snd-soc-dummy",
5318 .id = MSM_FRONTEND_DAI_LSM4,
5319 },
5320 {
5321 .name = "Listen 5 Audio Service",
5322 .stream_name = "Listen 5 Audio Service",
5323 .cpu_dai_name = "LSM5",
5324 .platform_name = "msm-lsm-client",
5325 .dynamic = 1,
5326 .dpcm_capture = 1,
5327 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5328 SND_SOC_DPCM_TRIGGER_POST },
5329 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5330 .ignore_suspend = 1,
5331 .codec_dai_name = "snd-soc-dummy-dai",
5332 .codec_name = "snd-soc-dummy",
5333 .id = MSM_FRONTEND_DAI_LSM5,
5334 },
5335 {
5336 .name = "Listen 6 Audio Service",
5337 .stream_name = "Listen 6 Audio Service",
5338 .cpu_dai_name = "LSM6",
5339 .platform_name = "msm-lsm-client",
5340 .dynamic = 1,
5341 .dpcm_capture = 1,
5342 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5343 SND_SOC_DPCM_TRIGGER_POST },
5344 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5345 .ignore_suspend = 1,
5346 .codec_dai_name = "snd-soc-dummy-dai",
5347 .codec_name = "snd-soc-dummy",
5348 .id = MSM_FRONTEND_DAI_LSM6,
5349 },
5350 {
5351 .name = "Listen 7 Audio Service",
5352 .stream_name = "Listen 7 Audio Service",
5353 .cpu_dai_name = "LSM7",
5354 .platform_name = "msm-lsm-client",
5355 .dynamic = 1,
5356 .dpcm_capture = 1,
5357 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5358 SND_SOC_DPCM_TRIGGER_POST },
5359 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5360 .ignore_suspend = 1,
5361 .codec_dai_name = "snd-soc-dummy-dai",
5362 .codec_name = "snd-soc-dummy",
5363 .id = MSM_FRONTEND_DAI_LSM7,
5364 },
5365 {
5366 .name = "Listen 8 Audio Service",
5367 .stream_name = "Listen 8 Audio Service",
5368 .cpu_dai_name = "LSM8",
5369 .platform_name = "msm-lsm-client",
5370 .dynamic = 1,
5371 .dpcm_capture = 1,
5372 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5373 SND_SOC_DPCM_TRIGGER_POST },
5374 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5375 .ignore_suspend = 1,
5376 .codec_dai_name = "snd-soc-dummy-dai",
5377 .codec_name = "snd-soc-dummy",
5378 .id = MSM_FRONTEND_DAI_LSM8,
5379 },
5380 /* - Multimedia9 */
5381 {
5382 .name = MSM_DAILINK_NAME(Compress4),
5383 .stream_name = "Compress4",
5384 .cpu_dai_name = "MultiMedia11",
5385 .platform_name = "msm-compress-dsp",
5386 .dynamic = 1,
5387 .dpcm_playback = 1,
5388 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5389 SND_SOC_DPCM_TRIGGER_POST},
5390 .codec_dai_name = "snd-soc-dummy-dai",
5391 .codec_name = "snd-soc-dummy",
5392 .ignore_suspend = 1,
5393 .ignore_pmdown_time = 1,
5394 /* this dainlink has playback support */
5395 .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
5396 },
5397 {
5398 .name = MSM_DAILINK_NAME(Compress5),
5399 .stream_name = "Compress5",
5400 .cpu_dai_name = "MultiMedia12",
5401 .platform_name = "msm-compress-dsp",
5402 .dynamic = 1,
5403 .dpcm_playback = 1,
5404 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5405 SND_SOC_DPCM_TRIGGER_POST},
5406 .codec_dai_name = "snd-soc-dummy-dai",
5407 .codec_name = "snd-soc-dummy",
5408 .ignore_suspend = 1,
5409 .ignore_pmdown_time = 1,
5410 /* this dainlink has playback support */
5411 .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
5412 },
5413 {
5414 .name = MSM_DAILINK_NAME(Compress6),
5415 .stream_name = "Compress6",
5416 .cpu_dai_name = "MultiMedia13",
5417 .platform_name = "msm-compress-dsp",
5418 .dynamic = 1,
5419 .dpcm_playback = 1,
5420 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5421 SND_SOC_DPCM_TRIGGER_POST},
5422 .codec_dai_name = "snd-soc-dummy-dai",
5423 .codec_name = "snd-soc-dummy",
5424 .ignore_suspend = 1,
5425 .ignore_pmdown_time = 1,
5426 /* this dainlink has playback support */
5427 .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
5428 },
5429 {
5430 .name = MSM_DAILINK_NAME(Compress7),
5431 .stream_name = "Compress7",
5432 .cpu_dai_name = "MultiMedia14",
5433 .platform_name = "msm-compress-dsp",
5434 .dynamic = 1,
5435 .dpcm_playback = 1,
5436 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5437 SND_SOC_DPCM_TRIGGER_POST},
5438 .codec_dai_name = "snd-soc-dummy-dai",
5439 .codec_name = "snd-soc-dummy",
5440 .ignore_suspend = 1,
5441 .ignore_pmdown_time = 1,
5442 /* this dainlink has playback support */
5443 .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
5444 },
5445 {
5446 .name = MSM_DAILINK_NAME(Compress8),
5447 .stream_name = "Compress8",
5448 .cpu_dai_name = "MultiMedia15",
5449 .platform_name = "msm-compress-dsp",
5450 .dynamic = 1,
5451 .dpcm_playback = 1,
5452 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5453 SND_SOC_DPCM_TRIGGER_POST},
5454 .codec_dai_name = "snd-soc-dummy-dai",
5455 .codec_name = "snd-soc-dummy",
5456 .ignore_suspend = 1,
5457 .ignore_pmdown_time = 1,
5458 /* this dainlink has playback support */
5459 .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
5460 },
5461 {
5462 .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
5463 .stream_name = "MM_NOIRQ_2",
5464 .cpu_dai_name = "MultiMedia16",
5465 .platform_name = "msm-pcm-dsp-noirq",
5466 .dynamic = 1,
5467 .dpcm_playback = 1,
5468 .dpcm_capture = 1,
5469 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5470 SND_SOC_DPCM_TRIGGER_POST},
5471 .codec_dai_name = "snd-soc-dummy-dai",
5472 .codec_name = "snd-soc-dummy",
5473 .ignore_suspend = 1,
5474 .ignore_pmdown_time = 1,
5475 /* this dainlink has playback support */
5476 .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
5477 },
5478 /* - SLIMBUS_8 Hostless */
5479 /* - Slimbus4 Capture */
5480 /* - SLIMBUS_2 Hostless Playback */
5481 /* - SLIMBUS_2 Hostless Capture */
5482 /* HFP TX */
5483 {
5484 .name = MSM_DAILINK_NAME(ASM Loopback),
5485 .stream_name = "MultiMedia6",
5486 .cpu_dai_name = "MultiMedia6",
5487 .platform_name = "msm-pcm-loopback",
5488 .dynamic = 1,
5489 .dpcm_playback = 1,
5490 .dpcm_capture = 1,
5491 .codec_dai_name = "snd-soc-dummy-dai",
5492 .codec_name = "snd-soc-dummy",
5493 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5494 SND_SOC_DPCM_TRIGGER_POST},
5495 .ignore_suspend = 1,
5496 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5497 .ignore_pmdown_time = 1,
5498 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
5499 },
5500 {
5501 .name = "USB Audio Hostless",
5502 .stream_name = "USB Audio Hostless",
5503 .cpu_dai_name = "USBAUDIO_HOSTLESS",
5504 .platform_name = "msm-pcm-hostless",
5505 .dynamic = 1,
5506 .dpcm_playback = 1,
5507 .dpcm_capture = 1,
5508 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5509 SND_SOC_DPCM_TRIGGER_POST},
5510 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5511 .ignore_suspend = 1,
5512 .ignore_pmdown_time = 1,
5513 .codec_dai_name = "snd-soc-dummy-dai",
5514 .codec_name = "snd-soc-dummy",
5515 },
5516 /* - SLIMBUS_7 Hostless */
5517 {
5518 .name = "Compress Capture",
5519 .stream_name = "Compress9",
5520 .cpu_dai_name = "MultiMedia17",
5521 .platform_name = "msm-compress-dsp",
5522 .dynamic = 1,
5523 .dpcm_capture = 1,
5524 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5525 SND_SOC_DPCM_TRIGGER_POST},
5526 .codec_dai_name = "snd-soc-dummy-dai",
5527 .codec_name = "snd-soc-dummy",
5528 .ignore_suspend = 1,
5529 .ignore_pmdown_time = 1,
5530 .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
5531 },
5532};
5533
5534static struct snd_soc_dai_link msm_auto_fe_dai_links[] = {
5535 {
5536 .name = "INT_HFP_BT Hostless",
5537 .stream_name = "INT_HFP_BT Hostless",
5538 .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
5539 .platform_name = "msm-pcm-hostless",
5540 .dynamic = 1,
5541 .dpcm_playback = 1,
5542 .dpcm_capture = 1,
5543 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5544 SND_SOC_DPCM_TRIGGER_POST},
5545 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5546 .ignore_suspend = 1,
5547 /* this dainlink has playback support */
5548 .ignore_pmdown_time = 1,
5549 .codec_dai_name = "snd-soc-dummy-dai",
5550 .codec_name = "snd-soc-dummy",
5551 },
5552 /* Low latency ASM loopback for ICC */
5553 {
5554 .name = MSM_DAILINK_NAME(LowLatency Loopback),
5555 .stream_name = "MultiMedia9",
5556 .cpu_dai_name = "MultiMedia9",
5557 .platform_name = "msm-pcm-loopback.1",
5558 .dynamic = 1,
5559 .dpcm_playback = 1,
5560 .dpcm_capture = 1,
5561 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5562 SND_SOC_DPCM_TRIGGER_POST},
5563 .codec_dai_name = "snd-soc-dummy-dai",
5564 .codec_name = "snd-soc-dummy",
5565 .ignore_suspend = 1,
5566 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5567 /* this dainlink has playback support */
5568 .ignore_pmdown_time = 1,
5569 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
5570 },
5571 {
5572 .name = "Tertiary MI2S TX_Hostless",
5573 .stream_name = "Tertiary MI2S_TX Hostless Capture",
5574 .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
5575 .platform_name = "msm-pcm-hostless",
5576 .dynamic = 1,
5577 .dpcm_capture = 1,
5578 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5579 SND_SOC_DPCM_TRIGGER_POST},
5580 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5581 .ignore_suspend = 1,
5582 .ignore_pmdown_time = 1,
5583 .codec_dai_name = "snd-soc-dummy-dai",
5584 .codec_name = "snd-soc-dummy",
5585 },
5586 {
5587 .name = MSM_DAILINK_NAME(Media20),
5588 .stream_name = "MultiMedia20",
5589 .cpu_dai_name = "MultiMedia20",
5590 .platform_name = "msm-pcm-loopback",
5591 .dynamic = 1,
5592 .dpcm_playback = 1,
5593 .dpcm_capture = 1,
5594 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5595 SND_SOC_DPCM_TRIGGER_POST},
5596 .codec_dai_name = "snd-soc-dummy-dai",
5597 .codec_name = "snd-soc-dummy",
5598 .ignore_suspend = 1,
5599 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5600 /* this dainlink has playback support */
5601 .ignore_pmdown_time = 1,
5602 .id = MSM_FRONTEND_DAI_MULTIMEDIA20,
5603 },
5604 {
5605 .name = MSM_DAILINK_NAME(HFP RX),
5606 .stream_name = "MultiMedia21",
5607 .cpu_dai_name = "MultiMedia21",
5608 .platform_name = "msm-pcm-loopback",
5609 .dynamic = 1,
5610 .dpcm_playback = 1,
5611 .dpcm_capture = 1,
5612 .codec_dai_name = "snd-soc-dummy-dai",
5613 .codec_name = "snd-soc-dummy",
5614 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5615 SND_SOC_DPCM_TRIGGER_POST},
5616 .ignore_suspend = 1,
5617 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5618 .ignore_pmdown_time = 1,
5619 .id = MSM_FRONTEND_DAI_MULTIMEDIA21,
5620 },
5621 /* TDM Hostless */
5622 {
5623 .name = "Primary TDM RX 0 Hostless",
5624 .stream_name = "Primary TDM RX 0 Hostless",
5625 .cpu_dai_name = "PRI_TDM_RX_0_HOSTLESS",
5626 .platform_name = "msm-pcm-hostless",
5627 .dynamic = 1,
5628 .dpcm_playback = 1,
5629 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5630 SND_SOC_DPCM_TRIGGER_POST},
5631 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5632 .ignore_suspend = 1,
5633 .ignore_pmdown_time = 1,
5634 .codec_dai_name = "snd-soc-dummy-dai",
5635 .codec_name = "snd-soc-dummy",
5636 },
5637 {
5638 .name = "Primary TDM TX 0 Hostless",
5639 .stream_name = "Primary TDM TX 0 Hostless",
5640 .cpu_dai_name = "PRI_TDM_TX_0_HOSTLESS",
5641 .platform_name = "msm-pcm-hostless",
5642 .dynamic = 1,
5643 .dpcm_capture = 1,
5644 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5645 SND_SOC_DPCM_TRIGGER_POST},
5646 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5647 .ignore_suspend = 1,
5648 .ignore_pmdown_time = 1,
5649 .codec_dai_name = "snd-soc-dummy-dai",
5650 .codec_name = "snd-soc-dummy",
5651 },
5652 {
5653 .name = "Secondary TDM RX 0 Hostless",
5654 .stream_name = "Secondary TDM RX 0 Hostless",
5655 .cpu_dai_name = "SEC_TDM_RX_0_HOSTLESS",
5656 .platform_name = "msm-pcm-hostless",
5657 .dynamic = 1,
5658 .dpcm_playback = 1,
5659 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5660 SND_SOC_DPCM_TRIGGER_POST},
5661 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5662 .ignore_suspend = 1,
5663 .ignore_pmdown_time = 1,
5664 .codec_dai_name = "snd-soc-dummy-dai",
5665 .codec_name = "snd-soc-dummy",
5666 },
5667 {
5668 .name = "Secondary TDM TX 0 Hostless",
5669 .stream_name = "Secondary TDM TX 0 Hostless",
5670 .cpu_dai_name = "SEC_TDM_TX_0_HOSTLESS",
5671 .platform_name = "msm-pcm-hostless",
5672 .dynamic = 1,
5673 .dpcm_capture = 1,
5674 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5675 SND_SOC_DPCM_TRIGGER_POST},
5676 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5677 .ignore_suspend = 1,
5678 .ignore_pmdown_time = 1,
5679 .codec_dai_name = "snd-soc-dummy-dai",
5680 .codec_name = "snd-soc-dummy",
5681 },
5682 {
5683 .name = "Tertiary TDM RX 0 Hostless",
5684 .stream_name = "Tertiary TDM RX 0 Hostless",
5685 .cpu_dai_name = "TERT_TDM_RX_0_HOSTLESS",
5686 .platform_name = "msm-pcm-hostless",
5687 .dynamic = 1,
5688 .dpcm_playback = 1,
5689 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5690 SND_SOC_DPCM_TRIGGER_POST},
5691 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5692 .ignore_suspend = 1,
5693 .ignore_pmdown_time = 1,
5694 .codec_dai_name = "snd-soc-dummy-dai",
5695 .codec_name = "snd-soc-dummy",
5696 },
5697 {
5698 .name = "Tertiary TDM TX 0 Hostless",
5699 .stream_name = "Tertiary TDM TX 0 Hostless",
5700 .cpu_dai_name = "TERT_TDM_TX_0_HOSTLESS",
5701 .platform_name = "msm-pcm-hostless",
5702 .dynamic = 1,
5703 .dpcm_capture = 1,
5704 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5705 SND_SOC_DPCM_TRIGGER_POST},
5706 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5707 .ignore_suspend = 1,
5708 .ignore_pmdown_time = 1,
5709 .codec_dai_name = "snd-soc-dummy-dai",
5710 .codec_name = "snd-soc-dummy",
5711 },
5712 {
5713 .name = "Quaternary TDM RX 0 Hostless",
5714 .stream_name = "Quaternary TDM RX 0 Hostless",
5715 .cpu_dai_name = "QUAT_TDM_RX_0_HOSTLESS",
5716 .platform_name = "msm-pcm-hostless",
5717 .dynamic = 1,
5718 .dpcm_playback = 1,
5719 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5720 SND_SOC_DPCM_TRIGGER_POST},
5721 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5722 .ignore_suspend = 1,
5723 .ignore_pmdown_time = 1,
5724 .codec_dai_name = "snd-soc-dummy-dai",
5725 .codec_name = "snd-soc-dummy",
5726 },
5727 {
5728 .name = "Quaternary TDM TX 0 Hostless",
5729 .stream_name = "Quaternary TDM TX 0 Hostless",
5730 .cpu_dai_name = "QUAT_TDM_TX_0_HOSTLESS",
5731 .platform_name = "msm-pcm-hostless",
5732 .dynamic = 1,
5733 .dpcm_capture = 1,
5734 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5735 SND_SOC_DPCM_TRIGGER_POST},
5736 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5737 .ignore_suspend = 1,
5738 .ignore_pmdown_time = 1,
5739 .codec_dai_name = "snd-soc-dummy-dai",
5740 .codec_name = "snd-soc-dummy",
5741 },
5742 {
5743 .name = "Quaternary MI2S_RX Hostless Playback",
5744 .stream_name = "Quaternary MI2S_RX Hostless Playback",
5745 .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS",
5746 .platform_name = "msm-pcm-hostless",
5747 .dynamic = 1,
5748 .dpcm_playback = 1,
5749 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5750 SND_SOC_DPCM_TRIGGER_POST},
5751 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5752 .ignore_suspend = 1,
5753 .ignore_pmdown_time = 1,
5754 .codec_dai_name = "snd-soc-dummy-dai",
5755 .codec_name = "snd-soc-dummy",
5756 },
5757 {
5758 .name = "Secondary MI2S_TX Hostless Capture",
5759 .stream_name = "Secondary MI2S_TX Hostless Capture",
5760 .cpu_dai_name = "SEC_MI2S_TX_HOSTLESS",
5761 .platform_name = "msm-pcm-hostless",
5762 .dynamic = 1,
5763 .dpcm_capture = 1,
5764 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5765 SND_SOC_DPCM_TRIGGER_POST},
5766 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5767 .ignore_suspend = 1,
5768 .ignore_pmdown_time = 1,
5769 .codec_dai_name = "snd-soc-dummy-dai",
5770 .codec_name = "snd-soc-dummy",
5771 },
5772 {
5773 .name = "DTMF RX Hostless",
5774 .stream_name = "DTMF RX Hostless",
5775 .cpu_dai_name = "DTMF_RX_HOSTLESS",
5776 .platform_name = "msm-pcm-dtmf",
5777 .dynamic = 1,
5778 .dpcm_playback = 1,
5779 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5780 SND_SOC_DPCM_TRIGGER_POST},
5781 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5782 .ignore_suspend = 1,
5783 .ignore_pmdown_time = 1,
5784 .codec_dai_name = "snd-soc-dummy-dai",
5785 .codec_name = "snd-soc-dummy",
5786 .id = MSM_FRONTEND_DAI_DTMF_RX,
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]5787 },
5788 {
5789 .name = "Secondary TDM RX 7 Hostless",
5790 .stream_name = "Secondary TDM RX 7 Hostless",
5791 .cpu_dai_name = "SEC_TDM_RX_7_HOSTLESS",
5792 .platform_name = "msm-pcm-hostless",
5793 .dynamic = 1,
5794 .dpcm_playback = 1,
5795 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5796 SND_SOC_DPCM_TRIGGER_POST},
5797 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5798 .ignore_suspend = 1,
5799 .ignore_pmdown_time = 1,
5800 .codec_dai_name = "snd-soc-dummy-dai",
5801 .codec_name = "snd-soc-dummy",
5802 },
5803 {
5804 .name = "Tertiary TDM TX 7 Hostless",
5805 .stream_name = "Tertiary TDM TX 7 Hostless",
5806 .cpu_dai_name = "TERT_TDM_TX_7_HOSTLESS",
5807 .platform_name = "msm-pcm-hostless",
5808 .dynamic = 1,
5809 .dpcm_capture = 1,
5810 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5811 SND_SOC_DPCM_TRIGGER_POST},
5812 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5813 .ignore_suspend = 1,
5814 .ignore_pmdown_time = 1,
5815 .codec_dai_name = "snd-soc-dummy-dai",
5816 .codec_name = "snd-soc-dummy",
5817 },
5818 {
5819 .name = "Quaternary TDM RX 7 Hostless",
5820 .stream_name = "Quaternary TDM RX 7 Hostless",
5821 .cpu_dai_name = "QUAT_TDM_RX_7_HOSTLESS",
5822 .platform_name = "msm-pcm-hostless",
5823 .dynamic = 1,
5824 .dpcm_playback = 1,
5825 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5826 SND_SOC_DPCM_TRIGGER_POST},
5827 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5828 .ignore_suspend = 1,
5829 .ignore_pmdown_time = 1,
5830 .codec_dai_name = "snd-soc-dummy-dai",
5831 .codec_name = "snd-soc-dummy",
5832 },
5833 {
5834 .name = "Quaternary TDM TX 7 Hostless",
5835 .stream_name = "Quaternary TDM TX 7 Hostless",
5836 .cpu_dai_name = "QUAT_TDM_TX_7_HOSTLESS",
5837 .platform_name = "msm-pcm-hostless",
5838 .dynamic = 1,
5839 .dpcm_capture = 1,
5840 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5841 SND_SOC_DPCM_TRIGGER_POST},
5842 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5843 .ignore_suspend = 1,
5844 .ignore_pmdown_time = 1,
5845 .codec_dai_name = "snd-soc-dummy-dai",
5846 .codec_name = "snd-soc-dummy",
5847 },
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]5848 {
5849 .name = "Quinary TDM RX 7 Hostless",
5850 .stream_name = "Quinary TDM RX 7 Hostless",
5851 .cpu_dai_name = "QUIN_TDM_RX_7_HOSTLESS",
5852 .platform_name = "msm-pcm-hostless",
5853 .dynamic = 1,
5854 .dpcm_playback = 1,
5855 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5856 SND_SOC_DPCM_TRIGGER_POST},
5857 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5858 .ignore_suspend = 1,
5859 .ignore_pmdown_time = 1,
5860 .codec_dai_name = "snd-soc-dummy-dai",
5861 .codec_name = "snd-soc-dummy",
5862 },
5863 {
5864 .name = "Quinary TDM TX 7 Hostless",
5865 .stream_name = "Quinary TDM TX 7 Hostless",
5866 .cpu_dai_name = "QUIN_TDM_TX_7_HOSTLESS",
5867 .platform_name = "msm-pcm-hostless",
5868 .dynamic = 1,
5869 .dpcm_capture = 1,
5870 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5871 SND_SOC_DPCM_TRIGGER_POST},
5872 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5873 .ignore_suspend = 1,
5874 .ignore_pmdown_time = 1,
5875 .codec_dai_name = "snd-soc-dummy-dai",
5876 .codec_name = "snd-soc-dummy",
5877 },
Derek Chen6c052da2019-07-31 17:30:46 -0700[diff] [blame]5878 {
5879 .name = MSM_DAILINK_NAME(Media22),
5880 .stream_name = "MultiMedia22",
5881 .cpu_dai_name = "MultiMedia22",
5882 .platform_name = "msm-pcm-dsp.0",
5883 .dynamic = 1,
5884 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5885 .dpcm_playback = 1,
5886 .dpcm_capture = 1,
5887 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5888 SND_SOC_DPCM_TRIGGER_POST},
5889 .codec_dai_name = "snd-soc-dummy-dai",
5890 .codec_name = "snd-soc-dummy",
5891 .ignore_suspend = 1,
5892 .ignore_pmdown_time = 1,
5893 .id = MSM_FRONTEND_DAI_MULTIMEDIA22
5894 },
Viraja Kommarajud3478b22019-11-04 20:38:23 +0530[diff] [blame]5895 {
5896 .name = MSM_DAILINK_NAME(Media23),
5897 .stream_name = "MultiMedia23",
5898 .cpu_dai_name = "MultiMedia23",
5899 .platform_name = "msm-pcm-dsp.1",
5900 .dynamic = 1,
5901 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5902 .dpcm_playback = 1,
5903 .dpcm_capture = 1,
5904 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5905 SND_SOC_DPCM_TRIGGER_POST},
5906 .codec_dai_name = "snd-soc-dummy-dai",
5907 .codec_name = "snd-soc-dummy",
5908 .ignore_suspend = 1,
5909 .ignore_pmdown_time = 1,
5910 .id = MSM_FRONTEND_DAI_MULTIMEDIA23
5911 },
Deru Wang5ab8cbd2020-03-25 13:20:06 +0800[diff] [blame]5912 {
5913 .name = MSM_DAILINK_NAME(Media24),
5914 .stream_name = "MultiMedia24",
5915 .cpu_dai_name = "MultiMedia24",
5916 .platform_name = "msm-pcm-loopback",
5917 .dynamic = 1,
5918 .dpcm_playback = 1,
5919 .dpcm_capture = 1,
5920 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5921 SND_SOC_DPCM_TRIGGER_POST},
5922 .codec_dai_name = "snd-soc-dummy-dai",
5923 .codec_name = "snd-soc-dummy",
5924 .ignore_suspend = 1,
5925 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5926 .ignore_pmdown_time = 1,
5927 .id = MSM_FRONTEND_DAI_MULTIMEDIA24
5928 },
5929 {
5930 .name = MSM_DAILINK_NAME(Media25),
5931 .stream_name = "MultiMedia25",
5932 .cpu_dai_name = "MultiMedia25",
5933 .platform_name = "msm-pcm-loopback",
5934 .dynamic = 1,
5935 .dpcm_playback = 1,
5936 .dpcm_capture = 1,
5937 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5938 SND_SOC_DPCM_TRIGGER_POST},
5939 .codec_dai_name = "snd-soc-dummy-dai",
5940 .codec_name = "snd-soc-dummy",
5941 .ignore_suspend = 1,
5942 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5943 .ignore_pmdown_time = 1,
5944 .id = MSM_FRONTEND_DAI_MULTIMEDIA25
5945 },
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]5946};
5947
5948static struct snd_soc_dai_link msm_custom_fe_dai_links[] = {
5949 /* FrontEnd DAI Links */
5950 {
5951 .name = MSM_DAILINK_NAME(Media1),
5952 .stream_name = "MultiMedia1",
5953 .cpu_dai_name = "MultiMedia1",
5954 .platform_name = "msm-pcm-dsp.1",
5955 .dynamic = 1,
5956 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5957 .dpcm_playback = 1,
5958 .dpcm_capture = 1,
5959 .codec_dai_name = "snd-soc-dummy-dai",
5960 .codec_name = "snd-soc-dummy",
5961 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5962 SND_SOC_DPCM_TRIGGER_POST},
5963 .ignore_suspend = 1,
5964 /* this dainlink has playback support */
5965 .ignore_pmdown_time = 1,
5966 .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
5967 .ops = &msm_fe_qos_ops,
5968 },
5969 {
5970 .name = MSM_DAILINK_NAME(Media2),
5971 .stream_name = "MultiMedia2",
5972 .cpu_dai_name = "MultiMedia2",
5973 .platform_name = "msm-pcm-dsp.1",
5974 .dynamic = 1,
5975 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5976 .dpcm_playback = 1,
5977 .dpcm_capture = 1,
5978 .codec_dai_name = "snd-soc-dummy-dai",
5979 .codec_name = "snd-soc-dummy",
5980 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5981 SND_SOC_DPCM_TRIGGER_POST},
5982 .ignore_suspend = 1,
5983 /* this dainlink has playback support */
5984 .ignore_pmdown_time = 1,
5985 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
5986 .ops = &msm_fe_qos_ops,
5987 },
5988 {
5989 .name = MSM_DAILINK_NAME(Media3),
5990 .stream_name = "MultiMedia3",
5991 .cpu_dai_name = "MultiMedia3",
5992 .platform_name = "msm-pcm-dsp.1",
5993 .dynamic = 1,
5994 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5995 .dpcm_playback = 1,
5996 .dpcm_capture = 1,
5997 .codec_dai_name = "snd-soc-dummy-dai",
5998 .codec_name = "snd-soc-dummy",
5999 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6000 SND_SOC_DPCM_TRIGGER_POST},
6001 .ignore_suspend = 1,
6002 /* this dainlink has playback support */
6003 .ignore_pmdown_time = 1,
6004 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
6005 .ops = &msm_fe_qos_ops,
6006 },
6007 {
6008 .name = MSM_DAILINK_NAME(Media5),
6009 .stream_name = "MultiMedia5",
6010 .cpu_dai_name = "MultiMedia5",
6011 .platform_name = "msm-pcm-dsp.1",
6012 .dynamic = 1,
6013 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
6014 .dpcm_playback = 1,
6015 .dpcm_capture = 1,
6016 .codec_dai_name = "snd-soc-dummy-dai",
6017 .codec_name = "snd-soc-dummy",
6018 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6019 SND_SOC_DPCM_TRIGGER_POST},
6020 .ignore_suspend = 1,
6021 /* this dainlink has playback support */
6022 .ignore_pmdown_time = 1,
6023 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
6024 .ops = &msm_fe_qos_ops,
6025 },
6026 {
6027 .name = MSM_DAILINK_NAME(Media6),
6028 .stream_name = "MultiMedia6",
6029 .cpu_dai_name = "MultiMedia6",
6030 .platform_name = "msm-pcm-dsp.1",
6031 .dynamic = 1,
6032 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
6033 .dpcm_playback = 1,
6034 .dpcm_capture = 1,
6035 .codec_dai_name = "snd-soc-dummy-dai",
6036 .codec_name = "snd-soc-dummy",
6037 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6038 SND_SOC_DPCM_TRIGGER_POST},
6039 .ignore_suspend = 1,
6040 /* this dainlink has playback support */
6041 .ignore_pmdown_time = 1,
6042 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
6043 .ops = &msm_fe_qos_ops,
6044 },
6045 {
6046 .name = MSM_DAILINK_NAME(Media8),
6047 .stream_name = "MultiMedia8",
6048 .cpu_dai_name = "MultiMedia8",
6049 .platform_name = "msm-pcm-dsp.1",
6050 .dynamic = 1,
6051 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
6052 .dpcm_playback = 1,
6053 .dpcm_capture = 1,
6054 .codec_dai_name = "snd-soc-dummy-dai",
6055 .codec_name = "snd-soc-dummy",
6056 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6057 SND_SOC_DPCM_TRIGGER_POST},
6058 .ignore_suspend = 1,
6059 /* this dainlink has playback support */
6060 .ignore_pmdown_time = 1,
6061 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
6062 .ops = &msm_fe_qos_ops,
6063 },
6064 {
6065 .name = MSM_DAILINK_NAME(Media9),
6066 .stream_name = "MultiMedia9",
6067 .cpu_dai_name = "MultiMedia9",
6068 .platform_name = "msm-pcm-dsp.1",
6069 .dynamic = 1,
6070 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
6071 .dpcm_playback = 1,
6072 .dpcm_capture = 1,
6073 .codec_dai_name = "snd-soc-dummy-dai",
6074 .codec_name = "snd-soc-dummy",
6075 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6076 SND_SOC_DPCM_TRIGGER_POST},
6077 .ignore_suspend = 1,
6078 /* this dainlink has playback support */
6079 .ignore_pmdown_time = 1,
6080 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
6081 .ops = &msm_fe_qos_ops,
6082 },
6083 {
6084 .name = "INT_HFP_BT Hostless",
6085 .stream_name = "INT_HFP_BT Hostless",
6086 .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
6087 .platform_name = "msm-pcm-hostless",
6088 .dynamic = 1,
6089 .dpcm_playback = 1,
6090 .dpcm_capture = 1,
6091 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6092 SND_SOC_DPCM_TRIGGER_POST},
6093 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6094 .ignore_suspend = 1,
6095 /* this dainlink has playback support */
6096 .ignore_pmdown_time = 1,
6097 .codec_dai_name = "snd-soc-dummy-dai",
6098 .codec_name = "snd-soc-dummy",
6099 },
6100 {
6101 .name = "AUXPCM Hostless",
6102 .stream_name = "AUXPCM Hostless",
6103 .cpu_dai_name = "AUXPCM_HOSTLESS",
6104 .platform_name = "msm-pcm-hostless",
6105 .dynamic = 1,
6106 .dpcm_playback = 1,
6107 .dpcm_capture = 1,
6108 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6109 SND_SOC_DPCM_TRIGGER_POST},
6110 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6111 .ignore_suspend = 1,
6112 /* this dainlink has playback support */
6113 .ignore_pmdown_time = 1,
6114 .codec_dai_name = "snd-soc-dummy-dai",
6115 .codec_name = "snd-soc-dummy",
6116 },
6117 {
6118 .name = MSM_DAILINK_NAME(Media20),
6119 .stream_name = "MultiMedia20",
6120 .cpu_dai_name = "MultiMedia20",
6121 .platform_name = "msm-pcm-loopback",
6122 .dynamic = 1,
6123 .dpcm_playback = 1,
6124 .dpcm_capture = 1,
6125 .codec_dai_name = "snd-soc-dummy-dai",
6126 .codec_name = "snd-soc-dummy",
6127 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6128 SND_SOC_DPCM_TRIGGER_POST},
6129 .ignore_suspend = 1,
6130 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6131 /* this dainlink has playback support */
6132 .ignore_pmdown_time = 1,
6133 .id = MSM_FRONTEND_DAI_MULTIMEDIA20,
6134 },
6135};
6136
6137static struct snd_soc_dai_link msm_common_be_dai_links[] = {
6138 /* Backend AFE DAI Links */
6139 {
6140 .name = LPASS_BE_AFE_PCM_RX,
6141 .stream_name = "AFE Playback",
6142 .cpu_dai_name = "msm-dai-q6-dev.224",
6143 .platform_name = "msm-pcm-routing",
6144 .codec_name = "msm-stub-codec.1",
6145 .codec_dai_name = "msm-stub-rx",
6146 .no_pcm = 1,
6147 .dpcm_playback = 1,
6148 .id = MSM_BACKEND_DAI_AFE_PCM_RX,
6149 .be_hw_params_fixup = msm_be_hw_params_fixup,
6150 /* this dainlink has playback support */
6151 .ignore_pmdown_time = 1,
6152 .ignore_suspend = 1,
6153 },
6154 {
6155 .name = LPASS_BE_AFE_PCM_TX,
6156 .stream_name = "AFE Capture",
6157 .cpu_dai_name = "msm-dai-q6-dev.225",
6158 .platform_name = "msm-pcm-routing",
6159 .codec_name = "msm-stub-codec.1",
6160 .codec_dai_name = "msm-stub-tx",
6161 .no_pcm = 1,
6162 .dpcm_capture = 1,
6163 .id = MSM_BACKEND_DAI_AFE_PCM_TX,
6164 .be_hw_params_fixup = msm_be_hw_params_fixup,
6165 .ignore_suspend = 1,
6166 },
6167 /* Incall Record Uplink BACK END DAI Link */
6168 {
6169 .name = LPASS_BE_INCALL_RECORD_TX,
6170 .stream_name = "Voice Uplink Capture",
6171 .cpu_dai_name = "msm-dai-q6-dev.32772",
6172 .platform_name = "msm-pcm-routing",
6173 .codec_name = "msm-stub-codec.1",
6174 .codec_dai_name = "msm-stub-tx",
6175 .no_pcm = 1,
6176 .dpcm_capture = 1,
6177 .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
6178 .be_hw_params_fixup = msm_be_hw_params_fixup,
6179 .ignore_suspend = 1,
6180 },
6181 /* Incall Record Downlink BACK END DAI Link */
6182 {
6183 .name = LPASS_BE_INCALL_RECORD_RX,
6184 .stream_name = "Voice Downlink Capture",
6185 .cpu_dai_name = "msm-dai-q6-dev.32771",
6186 .platform_name = "msm-pcm-routing",
6187 .codec_name = "msm-stub-codec.1",
6188 .codec_dai_name = "msm-stub-tx",
6189 .no_pcm = 1,
6190 .dpcm_capture = 1,
6191 .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
6192 .be_hw_params_fixup = msm_be_hw_params_fixup,
6193 .ignore_suspend = 1,
6194 },
6195 /* Incall Music BACK END DAI Link */
6196 {
6197 .name = LPASS_BE_VOICE_PLAYBACK_TX,
6198 .stream_name = "Voice Farend Playback",
6199 .cpu_dai_name = "msm-dai-q6-dev.32773",
6200 .platform_name = "msm-pcm-routing",
6201 .codec_name = "msm-stub-codec.1",
6202 .codec_dai_name = "msm-stub-rx",
6203 .no_pcm = 1,
6204 .dpcm_playback = 1,
6205 .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
6206 .be_hw_params_fixup = msm_be_hw_params_fixup,
6207 .ignore_suspend = 1,
6208 .ignore_pmdown_time = 1,
6209 },
6210 /* Incall Music 2 BACK END DAI Link */
6211 {
6212 .name = LPASS_BE_VOICE2_PLAYBACK_TX,
6213 .stream_name = "Voice2 Farend Playback",
6214 .cpu_dai_name = "msm-dai-q6-dev.32770",
6215 .platform_name = "msm-pcm-routing",
6216 .codec_name = "msm-stub-codec.1",
6217 .codec_dai_name = "msm-stub-rx",
6218 .no_pcm = 1,
6219 .dpcm_playback = 1,
6220 .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
6221 .be_hw_params_fixup = msm_be_hw_params_fixup,
6222 .ignore_suspend = 1,
6223 .ignore_pmdown_time = 1,
6224 },
6225 {
6226 .name = LPASS_BE_USB_AUDIO_RX,
6227 .stream_name = "USB Audio Playback",
6228 .cpu_dai_name = "msm-dai-q6-dev.28672",
6229 .platform_name = "msm-pcm-routing",
6230 .codec_name = "msm-stub-codec.1",
6231 .codec_dai_name = "msm-stub-rx",
6232 .no_pcm = 1,
6233 .dpcm_playback = 1,
6234 .id = MSM_BACKEND_DAI_USB_RX,
6235 .be_hw_params_fixup = msm_be_hw_params_fixup,
6236 .ignore_pmdown_time = 1,
6237 .ignore_suspend = 1,
6238 },
6239 {
6240 .name = LPASS_BE_USB_AUDIO_TX,
6241 .stream_name = "USB Audio Capture",
6242 .cpu_dai_name = "msm-dai-q6-dev.28673",
6243 .platform_name = "msm-pcm-routing",
6244 .codec_name = "msm-stub-codec.1",
6245 .codec_dai_name = "msm-stub-tx",
6246 .no_pcm = 1,
6247 .dpcm_capture = 1,
6248 .id = MSM_BACKEND_DAI_USB_TX,
6249 .be_hw_params_fixup = msm_be_hw_params_fixup,
6250 .ignore_suspend = 1,
6251 },
6252 {
6253 .name = LPASS_BE_PRI_TDM_RX_0,
6254 .stream_name = "Primary TDM0 Playback",
6255 .cpu_dai_name = "msm-dai-q6-tdm.36864",
6256 .platform_name = "msm-pcm-routing",
6257 .codec_name = "msm-stub-codec.1",
6258 .codec_dai_name = "msm-stub-rx",
6259 .no_pcm = 1,
6260 .dpcm_playback = 1,
6261 .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
6262 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6263 .ops = &sa6155_tdm_be_ops,
6264 .ignore_suspend = 1,
6265 .ignore_pmdown_time = 1,
6266 },
6267 {
6268 .name = LPASS_BE_PRI_TDM_TX_0,
6269 .stream_name = "Primary TDM0 Capture",
6270 .cpu_dai_name = "msm-dai-q6-tdm.36865",
6271 .platform_name = "msm-pcm-routing",
6272 .codec_name = "msm-stub-codec.1",
6273 .codec_dai_name = "msm-stub-tx",
6274 .no_pcm = 1,
6275 .dpcm_capture = 1,
6276 .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
6277 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6278 .ops = &sa6155_tdm_be_ops,
6279 .ignore_suspend = 1,
6280 },
6281 {
6282 .name = LPASS_BE_SEC_TDM_RX_0,
6283 .stream_name = "Secondary TDM0 Playback",
6284 .cpu_dai_name = "msm-dai-q6-tdm.36880",
6285 .platform_name = "msm-pcm-routing",
6286 .codec_name = "msm-stub-codec.1",
6287 .codec_dai_name = "msm-stub-rx",
6288 .no_pcm = 1,
6289 .dpcm_playback = 1,
6290 .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
6291 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6292 .ops = &sa6155_tdm_be_ops,
6293 .ignore_suspend = 1,
6294 .ignore_pmdown_time = 1,
6295 },
6296 {
6297 .name = LPASS_BE_SEC_TDM_TX_0,
6298 .stream_name = "Secondary TDM0 Capture",
6299 .cpu_dai_name = "msm-dai-q6-tdm.36881",
6300 .platform_name = "msm-pcm-routing",
6301 .codec_name = "msm-stub-codec.1",
6302 .codec_dai_name = "msm-stub-tx",
6303 .no_pcm = 1,
6304 .dpcm_capture = 1,
6305 .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
6306 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6307 .ops = &sa6155_tdm_be_ops,
6308 .ignore_suspend = 1,
6309 },
6310 {
6311 .name = LPASS_BE_TERT_TDM_RX_0,
6312 .stream_name = "Tertiary TDM0 Playback",
6313 .cpu_dai_name = "msm-dai-q6-tdm.36896",
6314 .platform_name = "msm-pcm-routing",
6315 .codec_name = "msm-stub-codec.1",
6316 .codec_dai_name = "msm-stub-rx",
6317 .no_pcm = 1,
6318 .dpcm_playback = 1,
6319 .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
6320 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6321 .ops = &sa6155_tdm_be_ops,
6322 .ignore_suspend = 1,
6323 .ignore_pmdown_time = 1,
6324 },
6325 {
6326 .name = LPASS_BE_TERT_TDM_TX_0,
6327 .stream_name = "Tertiary TDM0 Capture",
6328 .cpu_dai_name = "msm-dai-q6-tdm.36897",
6329 .platform_name = "msm-pcm-routing",
6330 .codec_name = "msm-stub-codec.1",
6331 .codec_dai_name = "msm-stub-tx",
6332 .no_pcm = 1,
6333 .dpcm_capture = 1,
6334 .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
6335 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6336 .ops = &sa6155_tdm_be_ops,
6337 .ignore_suspend = 1,
6338 },
6339 {
6340 .name = LPASS_BE_QUAT_TDM_RX_0,
6341 .stream_name = "Quaternary TDM0 Playback",
6342 .cpu_dai_name = "msm-dai-q6-tdm.36912",
6343 .platform_name = "msm-pcm-routing",
6344 .codec_name = "msm-stub-codec.1",
6345 .codec_dai_name = "msm-stub-rx",
6346 .no_pcm = 1,
6347 .dpcm_playback = 1,
6348 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
6349 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6350 .ops = &sa6155_tdm_be_ops,
6351 .ignore_suspend = 1,
6352 .ignore_pmdown_time = 1,
6353 },
6354 {
6355 .name = LPASS_BE_QUAT_TDM_TX_0,
6356 .stream_name = "Quaternary TDM0 Capture",
6357 .cpu_dai_name = "msm-dai-q6-tdm.36913",
6358 .platform_name = "msm-pcm-routing",
6359 .codec_name = "msm-stub-codec.1",
6360 .codec_dai_name = "msm-stub-tx",
6361 .no_pcm = 1,
6362 .dpcm_capture = 1,
6363 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
6364 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6365 .ops = &sa6155_tdm_be_ops,
6366 .ignore_suspend = 1,
6367 },
Rahul Sharma51181d02019-04-12 17:03:01 +0530[diff] [blame]6368 {
6369 .name = LPASS_BE_QUIN_TDM_RX_0,
6370 .stream_name = "Quinary TDM0 Playback",
6371 .cpu_dai_name = "msm-dai-q6-tdm.36928",
6372 .platform_name = "msm-pcm-routing",
6373 .codec_name = "msm-stub-codec.1",
6374 .codec_dai_name = "msm-stub-rx",
6375 .no_pcm = 1,
6376 .dpcm_playback = 1,
6377 .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
6378 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6379 .ops = &sa6155_tdm_be_ops,
6380 .ignore_suspend = 1,
6381 .ignore_pmdown_time = 1,
6382 },
6383 {
6384 .name = LPASS_BE_QUIN_TDM_TX_0,
6385 .stream_name = "Quinary TDM0 Capture",
6386 .cpu_dai_name = "msm-dai-q6-tdm.36929",
6387 .platform_name = "msm-pcm-routing",
6388 .codec_name = "msm-stub-codec.1",
6389 .codec_dai_name = "msm-stub-tx",
6390 .no_pcm = 1,
6391 .dpcm_capture = 1,
6392 .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
6393 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6394 .ops = &sa6155_tdm_be_ops,
6395 .ignore_suspend = 1,
6396 },
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6397};
6398
6399static struct snd_soc_dai_link msm_auto_be_dai_links[] = {
6400 /* Backend DAI Links */
6401 {
6402 .name = LPASS_BE_PRI_TDM_RX_1,
6403 .stream_name = "Primary TDM1 Playback",
6404 .cpu_dai_name = "msm-dai-q6-tdm.36866",
6405 .platform_name = "msm-pcm-routing",
6406 .codec_name = "msm-stub-codec.1",
6407 .codec_dai_name = "msm-stub-rx",
6408 .no_pcm = 1,
6409 .dpcm_playback = 1,
6410 .id = MSM_BACKEND_DAI_PRI_TDM_RX_1,
6411 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6412 .ops = &sa6155_tdm_be_ops,
6413 .ignore_suspend = 1,
6414 },
6415 {
6416 .name = LPASS_BE_PRI_TDM_RX_2,
6417 .stream_name = "Primary TDM2 Playback",
6418 .cpu_dai_name = "msm-dai-q6-tdm.36868",
6419 .platform_name = "msm-pcm-routing",
6420 .codec_name = "msm-stub-codec.1",
6421 .codec_dai_name = "msm-stub-rx",
6422 .no_pcm = 1,
6423 .dpcm_playback = 1,
6424 .id = MSM_BACKEND_DAI_PRI_TDM_RX_2,
6425 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6426 .ops = &sa6155_tdm_be_ops,
6427 .ignore_suspend = 1,
6428 },
6429 {
6430 .name = LPASS_BE_PRI_TDM_RX_3,
6431 .stream_name = "Primary TDM3 Playback",
6432 .cpu_dai_name = "msm-dai-q6-tdm.36870",
6433 .platform_name = "msm-pcm-routing",
6434 .codec_name = "msm-stub-codec.1",
6435 .codec_dai_name = "msm-stub-rx",
6436 .no_pcm = 1,
6437 .dpcm_playback = 1,
6438 .id = MSM_BACKEND_DAI_PRI_TDM_RX_3,
6439 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6440 .ops = &sa6155_tdm_be_ops,
6441 .ignore_suspend = 1,
6442 },
6443 {
6444 .name = LPASS_BE_PRI_TDM_TX_1,
6445 .stream_name = "Primary TDM1 Capture",
6446 .cpu_dai_name = "msm-dai-q6-tdm.36867",
6447 .platform_name = "msm-pcm-routing",
6448 .codec_name = "msm-stub-codec.1",
6449 .codec_dai_name = "msm-stub-rx",
6450 .no_pcm = 1,
6451 .dpcm_capture = 1,
6452 .id = MSM_BACKEND_DAI_PRI_TDM_TX_1,
6453 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6454 .ops = &sa6155_tdm_be_ops,
6455 .ignore_suspend = 1,
6456 },
6457 {
6458 .name = LPASS_BE_PRI_TDM_TX_2,
6459 .stream_name = "Primary TDM2 Capture",
6460 .cpu_dai_name = "msm-dai-q6-tdm.36869",
6461 .platform_name = "msm-pcm-routing",
6462 .codec_name = "msm-stub-codec.1",
6463 .codec_dai_name = "msm-stub-rx",
6464 .no_pcm = 1,
6465 .dpcm_capture = 1,
6466 .id = MSM_BACKEND_DAI_PRI_TDM_TX_2,
6467 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6468 .ops = &sa6155_tdm_be_ops,
6469 .ignore_suspend = 1,
6470 },
6471 {
6472 .name = LPASS_BE_PRI_TDM_TX_3,
6473 .stream_name = "Primary TDM3 Capture",
6474 .cpu_dai_name = "msm-dai-q6-tdm.36871",
6475 .platform_name = "msm-pcm-routing",
6476 .codec_name = "msm-stub-codec.1",
6477 .codec_dai_name = "msm-stub-rx",
6478 .no_pcm = 1,
6479 .dpcm_capture = 1,
6480 .id = MSM_BACKEND_DAI_PRI_TDM_TX_3,
6481 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6482 .ops = &sa6155_tdm_be_ops,
6483 .ignore_suspend = 1,
6484 },
6485 {
6486 .name = LPASS_BE_SEC_TDM_RX_1,
6487 .stream_name = "Secondary TDM1 Playback",
6488 .cpu_dai_name = "msm-dai-q6-tdm.36882",
6489 .platform_name = "msm-pcm-routing",
6490 .codec_name = "msm-stub-codec.1",
6491 .codec_dai_name = "msm-stub-rx",
6492 .no_pcm = 1,
6493 .dpcm_playback = 1,
6494 .id = MSM_BACKEND_DAI_SEC_TDM_RX_1,
6495 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6496 .ops = &sa6155_tdm_be_ops,
6497 .ignore_suspend = 1,
6498 },
6499 {
6500 .name = LPASS_BE_SEC_TDM_RX_2,
6501 .stream_name = "Secondary TDM2 Playback",
6502 .cpu_dai_name = "msm-dai-q6-tdm.36884",
6503 .platform_name = "msm-pcm-routing",
6504 .codec_name = "msm-stub-codec.1",
6505 .codec_dai_name = "msm-stub-rx",
6506 .no_pcm = 1,
6507 .dpcm_playback = 1,
6508 .id = MSM_BACKEND_DAI_SEC_TDM_RX_2,
6509 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6510 .ops = &sa6155_tdm_be_ops,
6511 .ignore_suspend = 1,
6512 },
6513 {
6514 .name = LPASS_BE_SEC_TDM_RX_3,
6515 .stream_name = "Secondary TDM3 Playback",
6516 .cpu_dai_name = "msm-dai-q6-tdm.36886",
6517 .platform_name = "msm-pcm-routing",
6518 .codec_name = "msm-stub-codec.1",
6519 .codec_dai_name = "msm-stub-rx",
6520 .no_pcm = 1,
6521 .dpcm_playback = 1,
6522 .id = MSM_BACKEND_DAI_SEC_TDM_RX_3,
6523 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6524 .ops = &sa6155_tdm_be_ops,
6525 .ignore_suspend = 1,
6526 },
6527 {
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]6528 .name = LPASS_BE_SEC_TDM_RX_7,
6529 .stream_name = "Secondary TDM7 Playback",
6530 .cpu_dai_name = "msm-dai-q6-tdm.36894",
6531 .platform_name = "msm-pcm-routing",
6532 .codec_name = "msm-stub-codec.1",
6533 .codec_dai_name = "msm-stub-rx",
6534 .no_pcm = 1,
6535 .dpcm_playback = 1,
6536 .id = MSM_BACKEND_DAI_SEC_TDM_RX_7,
6537 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6538 .ops = &sa6155_tdm_be_ops,
6539 .ignore_suspend = 1,
6540 },
6541 {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6542 .name = LPASS_BE_SEC_TDM_TX_1,
6543 .stream_name = "Secondary TDM1 Capture",
6544 .cpu_dai_name = "msm-dai-q6-tdm.36883",
6545 .platform_name = "msm-pcm-routing",
6546 .codec_name = "msm-stub-codec.1",
6547 .codec_dai_name = "msm-stub-rx",
6548 .no_pcm = 1,
6549 .dpcm_capture = 1,
6550 .id = MSM_BACKEND_DAI_SEC_TDM_TX_1,
6551 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6552 .ops = &sa6155_tdm_be_ops,
6553 .ignore_suspend = 1,
6554 },
6555 {
6556 .name = LPASS_BE_SEC_TDM_TX_2,
6557 .stream_name = "Secondary TDM2 Capture",
6558 .cpu_dai_name = "msm-dai-q6-tdm.36885",
6559 .platform_name = "msm-pcm-routing",
6560 .codec_name = "msm-stub-codec.1",
6561 .codec_dai_name = "msm-stub-rx",
6562 .no_pcm = 1,
6563 .dpcm_capture = 1,
6564 .id = MSM_BACKEND_DAI_SEC_TDM_TX_2,
6565 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6566 .ops = &sa6155_tdm_be_ops,
6567 .ignore_suspend = 1,
6568 },
6569 {
6570 .name = LPASS_BE_SEC_TDM_TX_3,
6571 .stream_name = "Secondary TDM3 Capture",
6572 .cpu_dai_name = "msm-dai-q6-tdm.36887",
6573 .platform_name = "msm-pcm-routing",
6574 .codec_name = "msm-stub-codec.1",
6575 .codec_dai_name = "msm-stub-rx",
6576 .no_pcm = 1,
6577 .dpcm_capture = 1,
6578 .id = MSM_BACKEND_DAI_SEC_TDM_TX_3,
6579 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6580 .ops = &sa6155_tdm_be_ops,
6581 .ignore_suspend = 1,
6582 },
6583 {
6584 .name = LPASS_BE_TERT_TDM_RX_1,
6585 .stream_name = "Tertiary TDM1 Playback",
6586 .cpu_dai_name = "msm-dai-q6-tdm.36898",
6587 .platform_name = "msm-pcm-routing",
6588 .codec_name = "msm-stub-codec.1",
6589 .codec_dai_name = "msm-stub-rx",
6590 .no_pcm = 1,
6591 .dpcm_playback = 1,
6592 .id = MSM_BACKEND_DAI_TERT_TDM_RX_1,
6593 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6594 .ops = &sa6155_tdm_be_ops,
6595 .ignore_suspend = 1,
6596 },
6597 {
6598 .name = LPASS_BE_TERT_TDM_RX_2,
6599 .stream_name = "Tertiary TDM2 Playback",
6600 .cpu_dai_name = "msm-dai-q6-tdm.36900",
6601 .platform_name = "msm-pcm-routing",
6602 .codec_name = "msm-stub-codec.1",
6603 .codec_dai_name = "msm-stub-rx",
6604 .no_pcm = 1,
6605 .dpcm_playback = 1,
6606 .id = MSM_BACKEND_DAI_TERT_TDM_RX_2,
6607 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6608 .ops = &sa6155_tdm_be_ops,
6609 .ignore_suspend = 1,
6610 },
6611 {
6612 .name = LPASS_BE_TERT_TDM_RX_3,
6613 .stream_name = "Tertiary TDM3 Playback",
6614 .cpu_dai_name = "msm-dai-q6-tdm.36902",
6615 .platform_name = "msm-pcm-routing",
6616 .codec_name = "msm-stub-codec.1",
6617 .codec_dai_name = "msm-stub-rx",
6618 .no_pcm = 1,
6619 .dpcm_playback = 1,
6620 .id = MSM_BACKEND_DAI_TERT_TDM_RX_3,
6621 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6622 .ops = &sa6155_tdm_be_ops,
6623 .ignore_suspend = 1,
6624 },
6625 {
6626 .name = LPASS_BE_TERT_TDM_RX_4,
6627 .stream_name = "Tertiary TDM4 Playback",
6628 .cpu_dai_name = "msm-dai-q6-tdm.36904",
6629 .platform_name = "msm-pcm-routing",
6630 .codec_name = "msm-stub-codec.1",
6631 .codec_dai_name = "msm-stub-rx",
6632 .no_pcm = 1,
6633 .dpcm_playback = 1,
6634 .id = MSM_BACKEND_DAI_TERT_TDM_RX_4,
6635 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6636 .ops = &sa6155_tdm_be_ops,
6637 .ignore_suspend = 1,
6638 },
6639 {
6640 .name = LPASS_BE_TERT_TDM_TX_1,
6641 .stream_name = "Tertiary TDM1 Capture",
6642 .cpu_dai_name = "msm-dai-q6-tdm.36899",
6643 .platform_name = "msm-pcm-routing",
6644 .codec_name = "msm-stub-codec.1",
6645 .codec_dai_name = "msm-stub-rx",
6646 .no_pcm = 1,
6647 .dpcm_capture = 1,
6648 .id = MSM_BACKEND_DAI_TERT_TDM_TX_1,
6649 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6650 .ops = &sa6155_tdm_be_ops,
6651 .ignore_suspend = 1,
6652 },
6653 {
6654 .name = LPASS_BE_TERT_TDM_TX_2,
6655 .stream_name = "Tertiary TDM2 Capture",
6656 .cpu_dai_name = "msm-dai-q6-tdm.36901",
6657 .platform_name = "msm-pcm-routing",
6658 .codec_name = "msm-stub-codec.1",
6659 .codec_dai_name = "msm-stub-rx",
6660 .no_pcm = 1,
6661 .dpcm_capture = 1,
6662 .id = MSM_BACKEND_DAI_TERT_TDM_TX_2,
6663 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6664 .ops = &sa6155_tdm_be_ops,
6665 .ignore_suspend = 1,
6666 },
6667 {
6668 .name = LPASS_BE_TERT_TDM_TX_3,
6669 .stream_name = "Tertiary TDM3 Capture",
6670 .cpu_dai_name = "msm-dai-q6-tdm.36903",
6671 .platform_name = "msm-pcm-routing",
6672 .codec_name = "msm-stub-codec.1",
6673 .codec_dai_name = "msm-stub-rx",
6674 .no_pcm = 1,
6675 .dpcm_capture = 1,
6676 .id = MSM_BACKEND_DAI_TERT_TDM_TX_3,
6677 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6678 .ops = &sa6155_tdm_be_ops,
6679 .ignore_suspend = 1,
6680 },
6681 {
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]6682 .name = LPASS_BE_TERT_TDM_TX_7,
6683 .stream_name = "Tertiary TDM7 Capture",
6684 .cpu_dai_name = "msm-dai-q6-tdm.36911",
6685 .platform_name = "msm-pcm-routing",
6686 .codec_name = "msm-stub-codec.1",
6687 .codec_dai_name = "msm-stub-rx",
6688 .no_pcm = 1,
6689 .dpcm_capture = 1,
6690 .id = MSM_BACKEND_DAI_TERT_TDM_TX_7,
6691 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6692 .ops = &sa6155_tdm_be_ops,
6693 .ignore_suspend = 1,
6694 },
6695 {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6696 .name = LPASS_BE_QUAT_TDM_RX_1,
6697 .stream_name = "Quaternary TDM1 Playback",
6698 .cpu_dai_name = "msm-dai-q6-tdm.36914",
6699 .platform_name = "msm-pcm-routing",
6700 .codec_name = "msm-stub-codec.1",
6701 .codec_dai_name = "msm-stub-rx",
6702 .no_pcm = 1,
6703 .dpcm_playback = 1,
6704 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_1,
6705 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6706 .ops = &sa6155_tdm_be_ops,
6707 .ignore_suspend = 1,
6708 },
6709 {
6710 .name = LPASS_BE_QUAT_TDM_RX_2,
6711 .stream_name = "Quaternary TDM2 Playback",
6712 .cpu_dai_name = "msm-dai-q6-tdm.36916",
6713 .platform_name = "msm-pcm-routing",
6714 .codec_name = "msm-stub-codec.1",
6715 .codec_dai_name = "msm-stub-rx",
6716 .no_pcm = 1,
6717 .dpcm_playback = 1,
6718 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_2,
6719 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6720 .ops = &sa6155_tdm_be_ops,
6721 .ignore_suspend = 1,
6722 },
6723 {
6724 .name = LPASS_BE_QUAT_TDM_RX_3,
6725 .stream_name = "Quaternary TDM3 Playback",
6726 .cpu_dai_name = "msm-dai-q6-tdm.36918",
6727 .platform_name = "msm-pcm-routing",
6728 .codec_name = "msm-stub-codec.1",
6729 .codec_dai_name = "msm-stub-rx",
6730 .no_pcm = 1,
6731 .dpcm_playback = 1,
6732 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_3,
6733 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6734 .ops = &sa6155_tdm_be_ops,
6735 .ignore_suspend = 1,
6736 },
6737 {
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]6738 .name = LPASS_BE_QUAT_TDM_RX_7,
6739 .stream_name = "Quaternary TDM7 Playback",
6740 .cpu_dai_name = "msm-dai-q6-tdm.36926",
6741 .platform_name = "msm-pcm-routing",
6742 .codec_name = "msm-stub-codec.1",
6743 .codec_dai_name = "msm-stub-rx",
6744 .no_pcm = 1,
6745 .dpcm_playback = 1,
6746 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_7,
6747 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6748 .ops = &sa6155_tdm_be_ops,
6749 .ignore_suspend = 1,
6750 },
6751 {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6752 .name = LPASS_BE_QUAT_TDM_TX_1,
6753 .stream_name = "Quaternary TDM1 Capture",
6754 .cpu_dai_name = "msm-dai-q6-tdm.36915",
6755 .platform_name = "msm-pcm-routing",
6756 .codec_name = "msm-stub-codec.1",
6757 .codec_dai_name = "msm-stub-rx",
6758 .no_pcm = 1,
6759 .dpcm_capture = 1,
6760 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_1,
6761 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6762 .ops = &sa6155_tdm_be_ops,
6763 .ignore_suspend = 1,
6764 },
6765 {
6766 .name = LPASS_BE_QUAT_TDM_TX_2,
6767 .stream_name = "Quaternary TDM2 Capture",
6768 .cpu_dai_name = "msm-dai-q6-tdm.36917",
6769 .platform_name = "msm-pcm-routing",
6770 .codec_name = "msm-stub-codec.1",
6771 .codec_dai_name = "msm-stub-rx",
6772 .no_pcm = 1,
6773 .dpcm_capture = 1,
6774 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_2,
6775 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6776 .ops = &sa6155_tdm_be_ops,
6777 .ignore_suspend = 1,
6778 },
6779 {
6780 .name = LPASS_BE_QUAT_TDM_TX_3,
6781 .stream_name = "Quaternary TDM3 Capture",
6782 .cpu_dai_name = "msm-dai-q6-tdm.36919",
6783 .platform_name = "msm-pcm-routing",
6784 .codec_name = "msm-stub-codec.1",
6785 .codec_dai_name = "msm-stub-rx",
6786 .no_pcm = 1,
6787 .dpcm_capture = 1,
6788 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_3,
6789 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6790 .ops = &sa6155_tdm_be_ops,
6791 .ignore_suspend = 1,
6792 },
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]6793 {
6794 .name = LPASS_BE_QUAT_TDM_TX_7,
6795 .stream_name = "Quaternary TDM7 Capture",
6796 .cpu_dai_name = "msm-dai-q6-tdm.36927",
6797 .platform_name = "msm-pcm-routing",
6798 .codec_name = "msm-stub-codec.1",
6799 .codec_dai_name = "msm-stub-rx",
6800 .no_pcm = 1,
6801 .dpcm_capture = 1,
6802 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_7,
6803 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6804 .ops = &sa6155_tdm_be_ops,
6805 .ignore_suspend = 1,
6806 },
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]6807 {
6808 .name = LPASS_BE_QUIN_TDM_RX_7,
6809 .stream_name = "Quinary TDM7 Playback",
6810 .cpu_dai_name = "msm-dai-q6-tdm.36942",
6811 .platform_name = "msm-pcm-routing",
6812 .codec_name = "msm-stub-codec.1",
6813 .codec_dai_name = "msm-stub-rx",
6814 .no_pcm = 1,
6815 .dpcm_playback = 1,
6816 .id = MSM_BACKEND_DAI_QUIN_TDM_RX_7,
6817 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6818 .ops = &sa6155_tdm_be_ops,
6819 .ignore_suspend = 1,
6820 },
6821 {
6822 .name = LPASS_BE_QUIN_TDM_TX_7,
6823 .stream_name = "Quinary TDM7 Capture",
6824 .cpu_dai_name = "msm-dai-q6-tdm.36943",
6825 .platform_name = "msm-pcm-routing",
6826 .codec_name = "msm-stub-codec.1",
6827 .codec_dai_name = "msm-stub-rx",
6828 .no_pcm = 1,
6829 .dpcm_capture = 1,
6830 .id = MSM_BACKEND_DAI_QUIN_TDM_TX_7,
6831 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6832 .ops = &sa6155_tdm_be_ops,
6833 .ignore_suspend = 1,
6834 },
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6835};
6836
6837static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
6838 /* DISP PORT BACK END DAI Link */
6839 {
6840 .name = LPASS_BE_DISPLAY_PORT,
6841 .stream_name = "Display Port Playback",
6842 .cpu_dai_name = "msm-dai-q6-dp.24608",
6843 .platform_name = "msm-pcm-routing",
6844 .codec_name = "msm-ext-disp-audio-codec-rx",
6845 .codec_dai_name = "msm_dp_audio_codec_rx_dai",
6846 .no_pcm = 1,
6847 .dpcm_playback = 1,
6848 .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
6849 .be_hw_params_fixup = msm_be_hw_params_fixup,
6850 .ignore_pmdown_time = 1,
6851 .ignore_suspend = 1,
6852 },
6853};
6854
6855static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
6856 {
6857 .name = LPASS_BE_PRI_MI2S_RX,
6858 .stream_name = "Primary MI2S Playback",
6859 .cpu_dai_name = "msm-dai-q6-mi2s.0",
6860 .platform_name = "msm-pcm-routing",
6861 .codec_name = "msm-stub-codec.1",
6862 .codec_dai_name = "msm-stub-rx",
6863 .no_pcm = 1,
6864 .dpcm_playback = 1,
6865 .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
6866 .be_hw_params_fixup = msm_be_hw_params_fixup,
6867 .ops = &msm_mi2s_be_ops,
6868 .ignore_suspend = 1,
6869 .ignore_pmdown_time = 1,
6870 },
6871 {
6872 .name = LPASS_BE_PRI_MI2S_TX,
6873 .stream_name = "Primary MI2S Capture",
6874 .cpu_dai_name = "msm-dai-q6-mi2s.0",
6875 .platform_name = "msm-pcm-routing",
6876 .codec_name = "msm-stub-codec.1",
6877 .codec_dai_name = "msm-stub-tx",
6878 .no_pcm = 1,
6879 .dpcm_capture = 1,
6880 .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
6881 .be_hw_params_fixup = msm_be_hw_params_fixup,
6882 .ops = &msm_mi2s_be_ops,
6883 .ignore_suspend = 1,
6884 },
6885 {
6886 .name = LPASS_BE_SEC_MI2S_RX,
6887 .stream_name = "Secondary MI2S Playback",
6888 .cpu_dai_name = "msm-dai-q6-mi2s.1",
6889 .platform_name = "msm-pcm-routing",
6890 .codec_name = "msm-stub-codec.1",
6891 .codec_dai_name = "msm-stub-rx",
6892 .no_pcm = 1,
6893 .dpcm_playback = 1,
6894 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
6895 .be_hw_params_fixup = msm_be_hw_params_fixup,
6896 .ops = &msm_mi2s_be_ops,
6897 .ignore_suspend = 1,
6898 .ignore_pmdown_time = 1,
6899 },
6900 {
6901 .name = LPASS_BE_SEC_MI2S_TX,
6902 .stream_name = "Secondary MI2S Capture",
6903 .cpu_dai_name = "msm-dai-q6-mi2s.1",
6904 .platform_name = "msm-pcm-routing",
6905 .codec_name = "msm-stub-codec.1",
6906 .codec_dai_name = "msm-stub-tx",
6907 .no_pcm = 1,
6908 .dpcm_capture = 1,
6909 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
6910 .be_hw_params_fixup = msm_be_hw_params_fixup,
6911 .ops = &msm_mi2s_be_ops,
6912 .ignore_suspend = 1,
6913 },
6914 {
6915 .name = LPASS_BE_TERT_MI2S_RX,
6916 .stream_name = "Tertiary MI2S Playback",
6917 .cpu_dai_name = "msm-dai-q6-mi2s.2",
6918 .platform_name = "msm-pcm-routing",
6919 .codec_name = "msm-stub-codec.1",
6920 .codec_dai_name = "msm-stub-rx",
6921 .no_pcm = 1,
6922 .dpcm_playback = 1,
6923 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
6924 .be_hw_params_fixup = msm_be_hw_params_fixup,
6925 .ops = &msm_mi2s_be_ops,
6926 .ignore_suspend = 1,
6927 .ignore_pmdown_time = 1,
6928 },
6929 {
6930 .name = LPASS_BE_TERT_MI2S_TX,
6931 .stream_name = "Tertiary MI2S Capture",
6932 .cpu_dai_name = "msm-dai-q6-mi2s.2",
6933 .platform_name = "msm-pcm-routing",
6934 .codec_name = "msm-stub-codec.1",
6935 .codec_dai_name = "msm-stub-tx",
6936 .no_pcm = 1,
6937 .dpcm_capture = 1,
6938 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
6939 .be_hw_params_fixup = msm_be_hw_params_fixup,
6940 .ops = &msm_mi2s_be_ops,
6941 .ignore_suspend = 1,
6942 },
6943 {
6944 .name = LPASS_BE_QUAT_MI2S_RX,
6945 .stream_name = "Quaternary MI2S Playback",
6946 .cpu_dai_name = "msm-dai-q6-mi2s.3",
6947 .platform_name = "msm-pcm-routing",
6948 .codec_name = "msm-stub-codec.1",
6949 .codec_dai_name = "msm-stub-rx",
6950 .no_pcm = 1,
6951 .dpcm_playback = 1,
6952 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
6953 .be_hw_params_fixup = msm_be_hw_params_fixup,
6954 .ops = &msm_mi2s_be_ops,
6955 .ignore_suspend = 1,
6956 .ignore_pmdown_time = 1,
6957 },
6958 {
6959 .name = LPASS_BE_QUAT_MI2S_TX,
6960 .stream_name = "Quaternary MI2S Capture",
6961 .cpu_dai_name = "msm-dai-q6-mi2s.3",
6962 .platform_name = "msm-pcm-routing",
6963 .codec_name = "msm-stub-codec.1",
6964 .codec_dai_name = "msm-stub-tx",
6965 .no_pcm = 1,
6966 .dpcm_capture = 1,
6967 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
6968 .be_hw_params_fixup = msm_be_hw_params_fixup,
6969 .ops = &msm_mi2s_be_ops,
6970 .ignore_suspend = 1,
6971 },
6972 {
6973 .name = LPASS_BE_QUIN_MI2S_RX,
6974 .stream_name = "Quinary MI2S Playback",
6975 .cpu_dai_name = "msm-dai-q6-mi2s.4",
6976 .platform_name = "msm-pcm-routing",
6977 .codec_name = "msm-stub-codec.1",
6978 .codec_dai_name = "msm-stub-rx",
6979 .no_pcm = 1,
6980 .dpcm_playback = 1,
6981 .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
6982 .be_hw_params_fixup = msm_be_hw_params_fixup,
6983 .ops = &msm_mi2s_be_ops,
6984 .ignore_suspend = 1,
6985 .ignore_pmdown_time = 1,
6986 },
6987 {
6988 .name = LPASS_BE_QUIN_MI2S_TX,
6989 .stream_name = "Quinary MI2S Capture",
6990 .cpu_dai_name = "msm-dai-q6-mi2s.4",
6991 .platform_name = "msm-pcm-routing",
6992 .codec_name = "msm-stub-codec.1",
6993 .codec_dai_name = "msm-stub-tx",
6994 .no_pcm = 1,
6995 .dpcm_capture = 1,
6996 .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
6997 .be_hw_params_fixup = msm_be_hw_params_fixup,
6998 .ops = &msm_mi2s_be_ops,
6999 .ignore_suspend = 1,
7000 },
7001};
7002
7003static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
7004 /* Primary AUX PCM Backend DAI Links */
7005 {
7006 .name = LPASS_BE_AUXPCM_RX,
7007 .stream_name = "AUX PCM Playback",
7008 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
7009 .platform_name = "msm-pcm-routing",
7010 .codec_name = "msm-stub-codec.1",
7011 .codec_dai_name = "msm-stub-rx",
7012 .no_pcm = 1,
7013 .dpcm_playback = 1,
7014 .id = MSM_BACKEND_DAI_AUXPCM_RX,
7015 .be_hw_params_fixup = msm_be_hw_params_fixup,
7016 .ignore_pmdown_time = 1,
7017 .ignore_suspend = 1,
7018 },
7019 {
7020 .name = LPASS_BE_AUXPCM_TX,
7021 .stream_name = "AUX PCM Capture",
7022 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
7023 .platform_name = "msm-pcm-routing",
7024 .codec_name = "msm-stub-codec.1",
7025 .codec_dai_name = "msm-stub-tx",
7026 .no_pcm = 1,
7027 .dpcm_capture = 1,
7028 .id = MSM_BACKEND_DAI_AUXPCM_TX,
7029 .be_hw_params_fixup = msm_be_hw_params_fixup,
7030 .ignore_suspend = 1,
7031 },
7032 /* Secondary AUX PCM Backend DAI Links */
7033 {
7034 .name = LPASS_BE_SEC_AUXPCM_RX,
7035 .stream_name = "Sec AUX PCM Playback",
7036 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
7037 .platform_name = "msm-pcm-routing",
7038 .codec_name = "msm-stub-codec.1",
7039 .codec_dai_name = "msm-stub-rx",
7040 .no_pcm = 1,
7041 .dpcm_playback = 1,
7042 .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
7043 .be_hw_params_fixup = msm_be_hw_params_fixup,
7044 .ignore_pmdown_time = 1,
7045 .ignore_suspend = 1,
7046 },
7047 {
7048 .name = LPASS_BE_SEC_AUXPCM_TX,
7049 .stream_name = "Sec AUX PCM Capture",
7050 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
7051 .platform_name = "msm-pcm-routing",
7052 .codec_name = "msm-stub-codec.1",
7053 .codec_dai_name = "msm-stub-tx",
7054 .no_pcm = 1,
7055 .dpcm_capture = 1,
7056 .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
7057 .be_hw_params_fixup = msm_be_hw_params_fixup,
7058 .ignore_suspend = 1,
7059 },
7060 /* Tertiary AUX PCM Backend DAI Links */
7061 {
7062 .name = LPASS_BE_TERT_AUXPCM_RX,
7063 .stream_name = "Tert AUX PCM Playback",
7064 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
7065 .platform_name = "msm-pcm-routing",
7066 .codec_name = "msm-stub-codec.1",
7067 .codec_dai_name = "msm-stub-rx",
7068 .no_pcm = 1,
7069 .dpcm_playback = 1,
7070 .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
7071 .be_hw_params_fixup = msm_be_hw_params_fixup,
7072 .ignore_suspend = 1,
7073 },
7074 {
7075 .name = LPASS_BE_TERT_AUXPCM_TX,
7076 .stream_name = "Tert AUX PCM Capture",
7077 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
7078 .platform_name = "msm-pcm-routing",
7079 .codec_name = "msm-stub-codec.1",
7080 .codec_dai_name = "msm-stub-tx",
7081 .no_pcm = 1,
7082 .dpcm_capture = 1,
7083 .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
7084 .be_hw_params_fixup = msm_be_hw_params_fixup,
7085 .ignore_suspend = 1,
7086 },
7087 /* Quaternary AUX PCM Backend DAI Links */
7088 {
7089 .name = LPASS_BE_QUAT_AUXPCM_RX,
7090 .stream_name = "Quat AUX PCM Playback",
7091 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
7092 .platform_name = "msm-pcm-routing",
7093 .codec_name = "msm-stub-codec.1",
7094 .codec_dai_name = "msm-stub-rx",
7095 .no_pcm = 1,
7096 .dpcm_playback = 1,
7097 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
7098 .be_hw_params_fixup = msm_be_hw_params_fixup,
7099 .ignore_pmdown_time = 1,
7100 .ignore_suspend = 1,
7101 },
7102 {
7103 .name = LPASS_BE_QUAT_AUXPCM_TX,
7104 .stream_name = "Quat AUX PCM Capture",
7105 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
7106 .platform_name = "msm-pcm-routing",
7107 .codec_name = "msm-stub-codec.1",
7108 .codec_dai_name = "msm-stub-tx",
7109 .no_pcm = 1,
7110 .dpcm_capture = 1,
7111 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
7112 .be_hw_params_fixup = msm_be_hw_params_fixup,
7113 .ignore_suspend = 1,
7114 },
7115 /* Quinary AUX PCM Backend DAI Links */
7116 {
7117 .name = LPASS_BE_QUIN_AUXPCM_RX,
7118 .stream_name = "Quin AUX PCM Playback",
7119 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
7120 .platform_name = "msm-pcm-routing",
7121 .codec_name = "msm-stub-codec.1",
7122 .codec_dai_name = "msm-stub-rx",
7123 .no_pcm = 1,
7124 .dpcm_playback = 1,
7125 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
7126 .be_hw_params_fixup = msm_be_hw_params_fixup,
7127 .ignore_pmdown_time = 1,
7128 .ignore_suspend = 1,
7129 },
7130 {
7131 .name = LPASS_BE_QUIN_AUXPCM_TX,
7132 .stream_name = "Quin AUX PCM Capture",
7133 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
7134 .platform_name = "msm-pcm-routing",
7135 .codec_name = "msm-stub-codec.1",
7136 .codec_dai_name = "msm-stub-tx",
7137 .no_pcm = 1,
7138 .dpcm_capture = 1,
7139 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
7140 .be_hw_params_fixup = msm_be_hw_params_fixup,
7141 .ignore_suspend = 1,
7142 },
7143};
7144
7145static struct snd_soc_dai_link msm_auto_dai_links[
7146 ARRAY_SIZE(msm_common_dai_links) +
7147 ARRAY_SIZE(msm_auto_fe_dai_links) +
7148 ARRAY_SIZE(msm_common_be_dai_links) +
7149 ARRAY_SIZE(msm_auto_be_dai_links) +
7150 ARRAY_SIZE(ext_disp_be_dai_link) +
7151 ARRAY_SIZE(msm_mi2s_be_dai_links) +
7152 ARRAY_SIZE(msm_auxpcm_be_dai_links)];
7153
7154static struct snd_soc_dai_link msm_auto_custom_dai_links[
7155 ARRAY_SIZE(msm_custom_fe_dai_links) +
7156 ARRAY_SIZE(msm_auto_fe_dai_links) +
7157 ARRAY_SIZE(msm_common_be_dai_links) +
7158 ARRAY_SIZE(msm_auto_be_dai_links) +
7159 ARRAY_SIZE(ext_disp_be_dai_link) +
7160 ARRAY_SIZE(msm_mi2s_be_dai_links) +
7161 ARRAY_SIZE(msm_auxpcm_be_dai_links)];
7162
7163struct snd_soc_card snd_soc_card_auto_msm = {
7164 .name = "sa6155-adp-star-snd-card",
7165};
7166
7167struct snd_soc_card snd_soc_card_auto_custom_msm = {
7168 .name = "sa6155-custom-snd-card",
7169};
7170
7171static int msm_populate_dai_link_component_of_node(
7172 struct snd_soc_card *card)
7173{
7174 int i, index, ret = 0;
7175 struct device *cdev = card->dev;
7176 struct snd_soc_dai_link *dai_link = card->dai_link;
7177 struct device_node *np;
7178
7179 if (!cdev) {
7180 pr_err("%s: Sound card device memory NULL\n", __func__);
7181 return -ENODEV;
7182 }
7183
7184 for (i = 0; i < card->num_links; i++) {
7185 if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
7186 continue;
7187
7188 /* populate platform_of_node for snd card dai links */
7189 if (dai_link[i].platform_name &&
7190 !dai_link[i].platform_of_node) {
7191 index = of_property_match_string(cdev->of_node,
7192 "asoc-platform-names",
7193 dai_link[i].platform_name);
7194 if (index < 0) {
7195 pr_err("%s: No match found for platform name: %s\n",
7196 __func__, dai_link[i].platform_name);
7197 ret = index;
7198 goto err;
7199 }
7200 np = of_parse_phandle(cdev->of_node, "asoc-platform",
7201 index);
7202 if (!np) {
7203 pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
7204 __func__, dai_link[i].platform_name,
7205 index);
7206 ret = -ENODEV;
7207 goto err;
7208 }
7209 dai_link[i].platform_of_node = np;
7210 dai_link[i].platform_name = NULL;
7211 }
7212
7213 /* populate cpu_of_node for snd card dai links */
7214 if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
7215 index = of_property_match_string(cdev->of_node,
7216 "asoc-cpu-names",
7217 dai_link[i].cpu_dai_name);
7218 if (index >= 0) {
7219 np = of_parse_phandle(cdev->of_node, "asoc-cpu",
7220 index);
7221 if (!np) {
7222 pr_err("%s: retrieving phandle for cpu dai %s failed\n",
7223 __func__,
7224 dai_link[i].cpu_dai_name);
7225 ret = -ENODEV;
7226 goto err;
7227 }
7228 dai_link[i].cpu_of_node = np;
7229 dai_link[i].cpu_dai_name = NULL;
7230 }
7231 }
7232
7233 /* populate codec_of_node for snd card dai links */
7234 if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
7235 index = of_property_match_string(cdev->of_node,
7236 "asoc-codec-names",
7237 dai_link[i].codec_name);
7238 if (index < 0)
7239 continue;
7240 np = of_parse_phandle(cdev->of_node, "asoc-codec",
7241 index);
7242 if (!np) {
7243 pr_err("%s: retrieving phandle for codec %s failed\n",
7244 __func__, dai_link[i].codec_name);
7245 ret = -ENODEV;
7246 goto err;
7247 }
7248 dai_link[i].codec_of_node = np;
7249 dai_link[i].codec_name = NULL;
7250 }
7251 }
7252
7253err:
7254 return ret;
7255}
7256
7257static const struct of_device_id sa6155_asoc_machine_of_match[] = {
7258 { .compatible = "qcom,sa6155-asoc-snd-adp-star",
7259 .data = "adp_star_codec"},
7260 { .compatible = "qcom,sa6155-asoc-snd-custom",
7261 .data = "custom_codec"},
7262 {},
7263};
7264
7265static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
7266{
7267 struct snd_soc_card *card = NULL;
7268 struct snd_soc_dai_link *dailink;
7269 int len_1, len_2, len_3;
7270 int total_links;
7271 const struct of_device_id *match;
7272
7273 match = of_match_node(sa6155_asoc_machine_of_match, dev->of_node);
7274 if (!match) {
7275 dev_err(dev, "%s: No DT match found for sound card\n",
7276 __func__);
7277 return NULL;
7278 }
7279
7280 if (!strcmp(match->data, "adp_star_codec")) {
7281 card = &snd_soc_card_auto_msm;
7282 len_1 = ARRAY_SIZE(msm_common_dai_links);
7283 len_2 = len_1 + ARRAY_SIZE(msm_auto_fe_dai_links);
7284 len_3 = len_2 + ARRAY_SIZE(msm_common_be_dai_links);
7285 total_links = len_3 + ARRAY_SIZE(msm_auto_be_dai_links);
7286 memcpy(msm_auto_dai_links,
7287 msm_common_dai_links,
7288 sizeof(msm_common_dai_links));
7289 memcpy(msm_auto_dai_links + len_1,
7290 msm_auto_fe_dai_links,
7291 sizeof(msm_auto_fe_dai_links));
7292 memcpy(msm_auto_dai_links + len_2,
7293 msm_common_be_dai_links,
7294 sizeof(msm_common_be_dai_links));
7295 memcpy(msm_auto_dai_links + len_3,
7296 msm_auto_be_dai_links,
7297 sizeof(msm_auto_be_dai_links));
7298
7299 if (of_property_read_bool(dev->of_node,
7300 "qcom,ext-disp-audio-rx")) {
7301 dev_dbg(dev, "%s(): ext disp audio support present\n",
7302 __func__);
7303 memcpy(msm_auto_dai_links + total_links,
7304 ext_disp_be_dai_link,
7305 sizeof(ext_disp_be_dai_link));
7306 total_links += ARRAY_SIZE(ext_disp_be_dai_link);
7307 }
7308 if (of_property_read_bool(dev->of_node,
7309 "qcom,mi2s-audio-intf")) {
7310 memcpy(msm_auto_dai_links + total_links,
7311 msm_mi2s_be_dai_links,
7312 sizeof(msm_mi2s_be_dai_links));
7313 total_links += ARRAY_SIZE(msm_mi2s_be_dai_links);
7314 }
7315 if (of_property_read_bool(dev->of_node,
7316 "qcom,auxpcm-audio-intf")) {
7317 memcpy(msm_auto_dai_links + total_links,
7318 msm_auxpcm_be_dai_links,
7319 sizeof(msm_auxpcm_be_dai_links));
7320 total_links += ARRAY_SIZE(msm_auxpcm_be_dai_links);
7321 }
7322
7323 dailink = msm_auto_dai_links;
7324 } else if (!strcmp(match->data, "custom_codec")) {
7325 card = &snd_soc_card_auto_custom_msm;
7326 len_1 = ARRAY_SIZE(msm_custom_fe_dai_links);
7327 len_2 = len_1 + ARRAY_SIZE(msm_auto_fe_dai_links);
7328 len_3 = len_2 + ARRAY_SIZE(msm_common_be_dai_links);
7329 total_links = len_3 + ARRAY_SIZE(msm_auto_be_dai_links);
7330 memcpy(msm_auto_custom_dai_links,
7331 msm_custom_fe_dai_links,
7332 sizeof(msm_custom_fe_dai_links));
7333 memcpy(msm_auto_custom_dai_links + len_1,
7334 msm_auto_fe_dai_links,
7335 sizeof(msm_auto_fe_dai_links));
7336 memcpy(msm_auto_custom_dai_links + len_2,
7337 msm_common_be_dai_links,
7338 sizeof(msm_common_be_dai_links));
7339 memcpy(msm_auto_custom_dai_links + len_3,
7340 msm_auto_be_dai_links,
7341 sizeof(msm_auto_be_dai_links));
7342
7343 if (of_property_read_bool(dev->of_node,
7344 "qcom,ext-disp-audio-rx")) {
7345 dev_dbg(dev, "%s(): ext disp audio support present\n",
7346 __func__);
7347 memcpy(msm_auto_custom_dai_links + total_links,
7348 ext_disp_be_dai_link,
7349 sizeof(ext_disp_be_dai_link));
7350 total_links += ARRAY_SIZE(ext_disp_be_dai_link);
7351 }
7352 if (of_property_read_bool(dev->of_node,
7353 "qcom,mi2s-audio-intf")) {
7354 memcpy(msm_auto_custom_dai_links + total_links,
7355 msm_mi2s_be_dai_links,
7356 sizeof(msm_mi2s_be_dai_links));
7357 total_links += ARRAY_SIZE(msm_mi2s_be_dai_links);
7358 }
7359 if (of_property_read_bool(dev->of_node,
7360 "qcom,auxpcm-audio-intf")) {
7361 memcpy(msm_auto_custom_dai_links + total_links,
7362 msm_auxpcm_be_dai_links,
7363 sizeof(msm_auxpcm_be_dai_links));
7364 total_links += ARRAY_SIZE(msm_auxpcm_be_dai_links);
7365 }
7366 dailink = msm_auto_custom_dai_links;
7367 } else {
7368 dev_err(dev, "%s: Codec not supported\n",
7369 __func__);
7370 return NULL;
7371 }
7372
7373 if (card) {
7374 card->dai_link = dailink;
7375 card->num_links = total_links;
7376 }
7377
7378 return card;
7379}
7380
7381/*****************************************************************************
7382* TO BE UPDATED: Codec/Platform specific tdm slot and offset table selection
7383*****************************************************************************/
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7384static int msm_tdm_init(struct platform_device *pdev)
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7385{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7386 struct snd_soc_card *card = platform_get_drvdata(pdev);
7387 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7388 const struct of_device_id *match;
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7389 int count;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7390
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7391 match = of_match_node(sa6155_asoc_machine_of_match, pdev->dev.of_node);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7392 if (!match) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7393 dev_err(&pdev->dev, "%s: No DT match found for sound card\n",
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7394 __func__);
7395 return -EINVAL;
7396 }
7397
7398 if (!strcmp(match->data, "custom_codec")) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7399 dev_dbg(&pdev->dev, "%s: custom tdm configuration\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7400
7401 memcpy(tdm_rx_slot_offset,
7402 tdm_rx_slot_offset_custom,
7403 sizeof(tdm_rx_slot_offset_custom));
7404 memcpy(tdm_tx_slot_offset,
7405 tdm_tx_slot_offset_custom,
7406 sizeof(tdm_tx_slot_offset_custom));
7407 memcpy(tdm_slot,
7408 tdm_slot_custom,
7409 sizeof(tdm_slot_custom));
7410 } else {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7411 dev_dbg(&pdev->dev, "%s: default tdm configuration\n", __func__);
7412 }
7413
7414 for (count = 0; count < TDM_INTERFACE_MAX; count++) {
7415 mutex_init(&pdata->tdm_intf_conf[count].lock);
7416 pdata->tdm_intf_conf[count].ref_cnt = 0;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7417 }
7418
7419 return 0;
7420}
7421
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7422static void msm_tdm_deinit(struct platform_device *pdev)
7423{
7424 struct snd_soc_card *card = platform_get_drvdata(pdev);
7425 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
7426 int count;
7427
7428 for (count = 0; count < TDM_INTERFACE_MAX; count++) {
7429 mutex_destroy(&pdata->tdm_intf_conf[count].lock);
7430 pdata->tdm_intf_conf[count].ref_cnt = 0;
7431 }
7432}
7433
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7434static void msm_i2s_auxpcm_init(struct platform_device *pdev)
7435{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7436 struct snd_soc_card *card = platform_get_drvdata(pdev);
7437 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7438 int count;
7439 u32 mi2s_master_slave[MI2S_MAX];
7440 int ret;
7441
7442 for (count = 0; count < MI2S_MAX; count++) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7443 mutex_init(&pdata->mi2s_intf_conf[count].lock);
7444 pdata->mi2s_intf_conf[count].ref_cnt = 0;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7445 }
7446
7447 ret = of_property_read_u32_array(pdev->dev.of_node,
7448 "qcom,msm-mi2s-master",
7449 mi2s_master_slave, MI2S_MAX);
7450 if (ret) {
7451 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
7452 __func__);
7453 } else {
7454 for (count = 0; count < MI2S_MAX; count++) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7455 pdata->mi2s_intf_conf[count].msm_is_mi2s_master =
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7456 mi2s_master_slave[count];
7457 }
7458 }
7459}
7460
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7461static void msm_i2s_auxpcm_deinit(struct platform_device *pdev)
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7462{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7463 struct snd_soc_card *card = platform_get_drvdata(pdev);
7464 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7465 int count;
7466
7467 for (count = 0; count < MI2S_MAX; count++) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7468 mutex_destroy(&pdata->mi2s_intf_conf[count].lock);
7469 pdata->mi2s_intf_conf[count].ref_cnt = 0;
7470 pdata->mi2s_intf_conf[count].msm_is_mi2s_master = 0;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7471 }
7472}
Erin Yan300664f2019-05-14 10:42:31 +0800[diff] [blame]7473
7474static int sa6155_ssr_enable(struct device *dev, void *data)
7475{
7476 struct platform_device *pdev = to_platform_device(dev);
7477 struct snd_soc_card *card = platform_get_drvdata(pdev);
7478 int ret = 0;
7479
7480 if (!card) {
7481 dev_err(dev, "%s: card is NULL\n", __func__);
7482 ret = -EINVAL;
7483 goto err;
7484 }
7485
7486 dev_info(dev, "%s: setting snd_card to ONLINE\n", __func__);
7487 snd_soc_card_change_online_state(card, 1);
7488
7489err:
7490 return ret;
7491}
7492
7493static void sa6155_ssr_disable(struct device *dev, void *data)
7494{
7495 struct platform_device *pdev = to_platform_device(dev);
7496 struct snd_soc_card *card = platform_get_drvdata(pdev);
7497
7498 if (!card) {
7499 dev_err(dev, "%s: card is NULL\n", __func__);
7500 return;
7501 }
7502
7503 dev_info(dev, "%s: setting snd_card to OFFLINE\n", __func__);
7504 snd_soc_card_change_online_state(card, 0);
7505}
7506
7507static const struct snd_event_ops sa6155_ssr_ops = {
7508 .enable = sa6155_ssr_enable,
7509 .disable = sa6155_ssr_disable,
7510};
7511
7512static int msm_audio_ssr_compare(struct device *dev, void *data)
7513{
7514 struct device_node *node = data;
7515
7516 dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
7517 __func__, dev->of_node, node);
7518 return (dev->of_node && dev->of_node == node);
7519}
7520
7521static int msm_audio_ssr_register(struct device *dev)
7522{
7523 struct device_node *np = dev->of_node;
7524 struct snd_event_clients *ssr_clients = NULL;
7525 struct device_node *node;
7526 int ret;
7527 int i;
7528
7529 for (i = 0; ; i++) {
7530 node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
7531 if (!node)
7532 break;
7533 snd_event_mstr_add_client(&ssr_clients,
7534 msm_audio_ssr_compare, node);
7535 }
7536
7537 ret = snd_event_master_register(dev, &sa6155_ssr_ops,
7538 ssr_clients, NULL);
7539 if (!ret)
7540 snd_event_notify(dev, SND_EVENT_UP);
7541
7542 return ret;
7543}
7544
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7545static int msm_asoc_machine_probe(struct platform_device *pdev)
7546{
7547 struct snd_soc_card *card;
7548 struct msm_asoc_mach_data *pdata;
7549 int ret;
7550 enum apr_subsys_state q6_state;
Derek Chen628c9952019-05-03 17:14:09 +0530[diff] [blame]7551 static int first_probe = 1;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7552
Derek Chen628c9952019-05-03 17:14:09 +0530[diff] [blame]7553 if (first_probe) {
7554 place_marker("M - DRIVER Audio Init");
7555 first_probe = 0;
7556 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7557 if (!pdev->dev.of_node) {
7558 dev_err(&pdev->dev, "No platform supplied from device tree\n");
7559 return -EINVAL;
7560 }
7561
7562 q6_state = apr_get_q6_state();
7563 if (q6_state == APR_SUBSYS_DOWN) {
7564 dev_dbg(&pdev->dev, "deferring %s, adsp_state %d\n",
7565 __func__, q6_state);
7566 return -EPROBE_DEFER;
7567 }
7568
7569 pdata = devm_kzalloc(&pdev->dev,
7570 sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
7571 if (!pdata)
7572 return -ENOMEM;
7573
7574 card = populate_snd_card_dailinks(&pdev->dev);
7575 if (!card) {
7576 dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
7577 ret = -EINVAL;
7578 goto err;
7579 }
7580 card->dev = &pdev->dev;
7581 platform_set_drvdata(pdev, card);
7582 snd_soc_card_set_drvdata(card, pdata);
7583
7584 ret = snd_soc_of_parse_card_name(card, "qcom,model");
7585 if (ret) {
7586 dev_err(&pdev->dev, "parse card name failed, err:%d\n",
7587 ret);
7588 goto err;
7589 }
7590
7591 ret = msm_populate_dai_link_component_of_node(card);
7592 if (ret) {
7593 ret = -EPROBE_DEFER;
7594 goto err;
7595 }
7596
7597 /* Populate controls of snd card */
7598 card->controls = msm_snd_controls;
7599 card->num_controls = ARRAY_SIZE(msm_snd_controls);
7600
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7601 ret = msm_tdm_init(pdev);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7602 if (ret) {
7603 ret = -EPROBE_DEFER;
7604 goto err;
7605 }
7606
7607 ret = devm_snd_soc_register_card(&pdev->dev, card);
7608 if (ret == -EPROBE_DEFER) {
7609 goto err;
7610 } else if (ret) {
7611 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
7612 ret);
7613 goto err;
7614 }
7615 dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
7616
7617 /* Parse pinctrl info from devicetree */
7618 ret = msm_get_pinctrl(pdev);
7619 if (!ret) {
7620 pr_debug("%s: pinctrl parsing successful\n", __func__);
7621 } else {
7622 dev_dbg(&pdev->dev,
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7623 "%s: pinctrl parsing failed with %d\n",
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7624 __func__, ret);
7625 ret = 0;
7626 }
7627
7628 msm_i2s_auxpcm_init(pdev);
7629
Erin Yan300664f2019-05-14 10:42:31 +0800[diff] [blame]7630 ret = msm_audio_ssr_register(&pdev->dev);
7631 if (ret)
7632 pr_err("%s: Registration with SND event FWK failed ret = %d\n",
7633 __func__, ret);
7634
Derek Chen628c9952019-05-03 17:14:09 +0530[diff] [blame]7635 place_marker("M - DRIVER Audio Ready");
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7636 return 0;
7637err:
7638 msm_release_pinctrl(pdev);
7639 devm_kfree(&pdev->dev, pdata);
7640 return ret;
7641}
7642
7643static int msm_asoc_machine_remove(struct platform_device *pdev)
7644{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7645 msm_i2s_auxpcm_deinit(pdev);
7646 msm_tdm_deinit(pdev);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7647
7648 msm_release_pinctrl(pdev);
7649 return 0;
7650}
7651
7652static struct platform_driver sa6155_asoc_machine_driver = {
7653 .driver = {
7654 .name = DRV_NAME,
7655 .owner = THIS_MODULE,
7656 .pm = &snd_soc_pm_ops,
7657 .of_match_table = sa6155_asoc_machine_of_match,
7658 },
7659 .probe = msm_asoc_machine_probe,
7660 .remove = msm_asoc_machine_remove,
7661};
7662
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7663int __init sa6155_init(void)
7664{
7665 pr_debug("%s\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7666 return platform_driver_register(&sa6155_asoc_machine_driver);
7667}
7668
7669void sa6155_exit(void)
7670{
7671 pr_debug("%s\n", __func__);
7672 platform_driver_unregister(&sa6155_asoc_machine_driver);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7673}
7674
Rahul Sharmaf53de7f2019-03-03 22:30:47 +0530[diff] [blame]7675module_init(sa6155_init);
7676module_exit(sa6155_exit);
7677
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7678MODULE_DESCRIPTION("ALSA SoC msm");
7679MODULE_LICENSE("GPL v2");
7680MODULE_ALIAS("platform:" DRV_NAME);
7681MODULE_DEVICE_TABLE(of, sa6155_asoc_machine_of_match);