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Vivek126db5d2018-07-25 22:05:04 +05301/*
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -08002 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
Vivek126db5d2018-07-25 22:05:04 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all
7 * copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16 * PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/**
20 * DOC: This file contains definitions of Data Path configuration.
21 */
22
23#ifndef _CFG_DP_H_
24#define _CFG_DP_H_
25
26#include "cfg_define.h"
27
28#define WLAN_CFG_MAX_CLIENTS 64
Pratik Gandhi4cce3e02018-09-05 19:43:11 +053029#define WLAN_CFG_MAX_CLIENTS_MIN 8
Vivek126db5d2018-07-25 22:05:04 +053030#define WLAN_CFG_MAX_CLIENTS_MAX 64
31
32/* Change this to a lower value to enforce scattered idle list mode */
33#define WLAN_CFG_MAX_ALLOC_SIZE 0x200000
sumedh baikady3c05f972019-04-18 15:30:30 -070034#define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000
Vivek126db5d2018-07-25 22:05:04 +053035#define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000
36
37#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
38#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
39#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
40
hangtian04f0ad42019-06-07 11:04:02 +080041#if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \
42 defined(QCA_LL_PDEV_TX_FLOW_CONTROL)
jitiphil60ac9aa2018-10-05 19:54:04 +053043#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10
44#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15
Vivek126db5d2018-07-25 22:05:04 +053045#else
jitiphil60ac9aa2018-10-05 19:54:04 +053046#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
47#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
Vivek126db5d2018-07-25 22:05:04 +053048#endif
Vivek126db5d2018-07-25 22:05:04 +053049
50#define WLAN_CFG_PER_PDEV_TX_RING_MIN 0
51#define WLAN_CFG_PER_PDEV_TX_RING_MAX 1
52
Vevek Venkatesan4a6c3e82019-06-24 14:29:19 +053053#if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
Vivek126db5d2018-07-25 22:05:04 +053054#define WLAN_CFG_PER_PDEV_RX_RING 0
55#define WLAN_CFG_PER_PDEV_LMAC_RING 0
jitiphil60ac9aa2018-10-05 19:54:04 +053056#define WLAN_LRO_ENABLE 0
Venkata Sharath Chandra Manchala8d583a82019-04-21 12:32:24 -070057#define WLAN_CFG_MAC_PER_TARGET 2
Vivek126db5d2018-07-25 22:05:04 +053058#ifdef IPA_OFFLOAD
Mohit Khanna81179cb2018-08-16 20:50:43 -070059/* Size of TCL TX Ring */
60#define WLAN_CFG_TX_RING_SIZE 1024
jitiphil60ac9aa2018-10-05 19:54:04 +053061#define WLAN_CFG_PER_PDEV_TX_RING 0
62#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048
63#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000
64#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024
Vivek126db5d2018-07-25 22:05:04 +053065#else
66#define WLAN_CFG_TX_RING_SIZE 512
jitiphil60ac9aa2018-10-05 19:54:04 +053067#define WLAN_CFG_PER_PDEV_TX_RING 1
68#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
69#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
70#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
Vivek126db5d2018-07-25 22:05:04 +053071#endif
72#define WLAN_CFG_TX_COMP_RING_SIZE 1024
73
74/* Tx Descriptor and Tx Extension Descriptor pool sizes */
75#define WLAN_CFG_NUM_TX_DESC 1024
76#define WLAN_CFG_NUM_TX_EXT_DESC 1024
77
78/* Interrupt Mitigation - Batch threshold in terms of number of frames */
79#define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1
80#define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1
81#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1
82
83/* Interrupt Mitigation - Timer threshold in us */
84#define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8
85#define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8
86#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8
Vivek126db5d2018-07-25 22:05:04 +053087#endif
88
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -070089#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256
90#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 256
91
Vivek126db5d2018-07-25 22:05:04 +053092#define WLAN_CFG_PER_PDEV_RX_RING_MIN 0
93#define WLAN_CFG_PER_PDEV_RX_RING_MAX 0
94
95#define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0
96#define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1
97
98#define WLAN_CFG_TX_RING_SIZE_MIN 512
99#define WLAN_CFG_TX_RING_SIZE_MAX 2048
100
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530101#define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512
Vivek126db5d2018-07-25 22:05:04 +0530102#define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000
103
104#define WLAN_CFG_NUM_TX_DESC_MIN 1024
Shashikala Prabhu550e69c2019-03-13 17:41:17 +0530105#define WLAN_CFG_NUM_TX_DESC_MAX 32768
Vivek126db5d2018-07-25 22:05:04 +0530106
107#define WLAN_CFG_NUM_TX_EXT_DESC_MIN 1024
108#define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000
109
110#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1
111#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256
112
113#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1
114#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128
115
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700116#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1
117#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128
118
119#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1
120#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128
121
Vivek126db5d2018-07-25 22:05:04 +0530122#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1
123#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1
124
125#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8
126#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 100
127
128#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8
129#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500
130
131#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8
132#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000
133
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700134#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8
135#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 500
136
137#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8
138#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500
139
Aniruddha Paul7d991b32018-09-03 17:40:00 +0530140#define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000
141#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000
Aniruddha Paul1b267242019-03-15 12:01:06 +0530142#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000
Vivek126db5d2018-07-25 22:05:04 +0530143
144#ifdef QCA_LL_TX_FLOW_CONTROL_V2
145
146/* Per vdev pools */
147#define WLAN_CFG_NUM_TX_DESC_POOL 3
148#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
149
150#else /* QCA_LL_TX_FLOW_CONTROL_V2 */
151
152#ifdef TX_PER_PDEV_DESC_POOL
153#define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT
154#define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT
155
156#else /* TX_PER_PDEV_DESC_POOL */
157
158#define WLAN_CFG_NUM_TX_DESC_POOL 3
159#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
160
161#endif /* TX_PER_PDEV_DESC_POOL */
162#endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
163
164#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1
165#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4
166
167#define WLAN_CFG_HTT_PKT_TYPE 2
168#define WLAN_CFG_HTT_PKT_TYPE_MIN 2
169#define WLAN_CFG_HTT_PKT_TYPE_MAX 2
170
171#define WLAN_CFG_MAX_PEER_ID 64
172#define WLAN_CFG_MAX_PEER_ID_MIN 64
173#define WLAN_CFG_MAX_PEER_ID_MAX 64
174
175#define WLAN_CFG_RX_DEFRAG_TIMEOUT 100
176#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100
177#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100
178
179#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
180#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
181#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
182
183#define WLAN_CFG_NUM_REO_DEST_RING 4
184#define WLAN_CFG_NUM_REO_DEST_RING_MIN 4
185#define WLAN_CFG_NUM_REO_DEST_RING_MAX 4
186
187#define WLAN_CFG_WBM_RELEASE_RING_SIZE 64
188#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64
189#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 64
190
191#define WLAN_CFG_TCL_CMD_RING_SIZE 32
192#define WLAN_CFG_TCL_CMD_RING_SIZE_MIN 32
193#define WLAN_CFG_TCL_CMD_RING_SIZE_MAX 32
194
195#define WLAN_CFG_TCL_STATUS_RING_SIZE 32
196#define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32
197#define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32
198
199#if defined(QCA_WIFI_QCA6290)
200#define WLAN_CFG_REO_DST_RING_SIZE 1024
201#else
202#define WLAN_CFG_REO_DST_RING_SIZE 2048
203#endif
204
205#define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024
206#define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048
207
208#define WLAN_CFG_REO_REINJECT_RING_SIZE 32
209#define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32
210#define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32
211
212#define WLAN_CFG_RX_RELEASE_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530213#define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530214#if defined(QCA_WIFI_QCA6390)
Vivek126db5d2018-07-25 22:05:04 +0530215#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530216#else
217#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192
218#endif
Vivek126db5d2018-07-25 22:05:04 +0530219
220#define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128
221#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128
222#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128
223
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700224#define WLAN_CFG_REO_CMD_RING_SIZE 128
Vivek126db5d2018-07-25 22:05:04 +0530225#define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700226#define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128
Vivek126db5d2018-07-25 22:05:04 +0530227
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700228#define WLAN_CFG_REO_STATUS_RING_SIZE 256
Vivek126db5d2018-07-25 22:05:04 +0530229#define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -0800230#define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048
Vivek126db5d2018-07-25 22:05:04 +0530231
232#define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024
233#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024
234#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024
235
236#define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530237#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16
Vivek126db5d2018-07-25 22:05:04 +0530238#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096
239
240#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530241#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800242#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530243
244#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530245#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48
Kai Chen692850b2018-12-05 15:06:07 -0800246#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530247
248#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530249#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800250#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530251
252#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096
253#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096
Kai Chen692850b2018-12-05 15:06:07 -0800254#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384
Vivek126db5d2018-07-25 22:05:04 +0530255
256#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024
257#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024
Karunakar Dasineni79768452018-09-07 11:32:34 -0700258#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530259
260/* DP INI Declerations */
261#define CFG_DP_HTT_PACKET_TYPE \
262 CFG_INI_UINT("dp_htt_packet_type", \
263 WLAN_CFG_HTT_PKT_TYPE_MIN, \
264 WLAN_CFG_HTT_PKT_TYPE_MAX, \
265 WLAN_CFG_HTT_PKT_TYPE, \
266 CFG_VALUE_OR_DEFAULT, "DP HTT packet type")
267
268#define CFG_DP_INT_BATCH_THRESHOLD_OTHER \
269 CFG_INI_UINT("dp_int_batch_threshold_other", \
Karunakar Dasineni2b7628c2018-10-23 22:59:37 -0700270 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \
271 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \
272 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700273 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other")
Vivek126db5d2018-07-25 22:05:04 +0530274
275#define CFG_DP_INT_BATCH_THRESHOLD_RX \
276 CFG_INI_UINT("dp_int_batch_threshold_rx", \
277 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \
278 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \
279 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700280 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx")
Vivek126db5d2018-07-25 22:05:04 +0530281
282#define CFG_DP_INT_BATCH_THRESHOLD_TX \
283 CFG_INI_UINT("dp_int_batch_threshold_tx", \
284 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \
285 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \
286 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \
287 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx")
288
289#define CFG_DP_INT_TIMER_THRESHOLD_OTHER \
290 CFG_INI_UINT("dp_int_timer_threshold_other", \
291 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \
292 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \
293 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \
294 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other")
295
296#define CFG_DP_INT_TIMER_THRESHOLD_RX \
297 CFG_INI_UINT("dp_int_timer_threshold_rx", \
298 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \
299 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \
300 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \
301 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx")
302
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700303#define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \
304 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \
305 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \
306 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \
307 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \
308 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring")
309
310#define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \
311 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \
312 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \
313 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \
314 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \
315 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring")
316
Vivek126db5d2018-07-25 22:05:04 +0530317#define CFG_DP_INT_TIMER_THRESHOLD_TX \
318 CFG_INI_UINT("dp_int_timer_threshold_tx", \
319 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \
320 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \
321 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \
322 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx")
323
324#define CFG_DP_MAX_ALLOC_SIZE \
325 CFG_INI_UINT("dp_max_alloc_size", \
326 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \
327 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \
328 WLAN_CFG_MAX_ALLOC_SIZE, \
329 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size")
330
331#define CFG_DP_MAX_CLIENTS \
332 CFG_INI_UINT("dp_max_clients", \
333 WLAN_CFG_MAX_CLIENTS_MIN, \
334 WLAN_CFG_MAX_CLIENTS_MAX, \
335 WLAN_CFG_MAX_CLIENTS, \
336 CFG_VALUE_OR_DEFAULT, "DP Max Clients")
337
338#define CFG_DP_MAX_PEER_ID \
339 CFG_INI_UINT("dp_max_peer_id", \
340 WLAN_CFG_MAX_PEER_ID_MIN, \
341 WLAN_CFG_MAX_PEER_ID_MAX, \
342 WLAN_CFG_MAX_PEER_ID, \
343 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID")
344
345#define CFG_DP_REO_DEST_RINGS \
346 CFG_INI_UINT("dp_reo_dest_rings", \
347 WLAN_CFG_NUM_REO_DEST_RING_MIN, \
348 WLAN_CFG_NUM_REO_DEST_RING_MAX, \
349 WLAN_CFG_NUM_REO_DEST_RING, \
350 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings")
351
352#define CFG_DP_TCL_DATA_RINGS \
353 CFG_INI_UINT("dp_tcl_data_rings", \
354 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \
355 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \
356 WLAN_CFG_NUM_TCL_DATA_RINGS, \
357 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings")
358
359#define CFG_DP_TX_DESC \
360 CFG_INI_UINT("dp_tx_desc", \
361 WLAN_CFG_NUM_TX_DESC_MIN, \
362 WLAN_CFG_NUM_TX_DESC_MAX, \
363 WLAN_CFG_NUM_TX_DESC, \
364 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors")
365
366#define CFG_DP_TX_EXT_DESC \
367 CFG_INI_UINT("dp_tx_ext_desc", \
368 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \
369 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \
370 WLAN_CFG_NUM_TX_EXT_DESC, \
371 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors")
372
373#define CFG_DP_TX_EXT_DESC_POOLS \
374 CFG_INI_UINT("dp_tx_ext_desc_pool", \
375 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \
376 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \
377 WLAN_CFG_NUM_TXEXT_DESC_POOL, \
378 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool")
379
380#define CFG_DP_PDEV_RX_RING \
381 CFG_INI_UINT("dp_pdev_rx_ring", \
382 WLAN_CFG_PER_PDEV_RX_RING_MIN, \
383 WLAN_CFG_PER_PDEV_RX_RING_MAX, \
384 WLAN_CFG_PER_PDEV_RX_RING, \
385 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring")
386
387#define CFG_DP_PDEV_TX_RING \
388 CFG_INI_UINT("dp_pdev_tx_ring", \
389 WLAN_CFG_PER_PDEV_TX_RING_MIN, \
390 WLAN_CFG_PER_PDEV_TX_RING_MAX, \
391 WLAN_CFG_PER_PDEV_TX_RING, \
392 CFG_VALUE_OR_DEFAULT, \
393 "DP PDEV Tx Ring")
394
395#define CFG_DP_RX_DEFRAG_TIMEOUT \
396 CFG_INI_UINT("dp_rx_defrag_timeout", \
397 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \
398 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \
399 WLAN_CFG_RX_DEFRAG_TIMEOUT, \
400 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout")
401
402#define CFG_DP_TX_COMPL_RING_SIZE \
403 CFG_INI_UINT("dp_tx_compl_ring_size", \
404 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \
405 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \
406 WLAN_CFG_TX_COMP_RING_SIZE, \
407 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size")
408
409#define CFG_DP_TX_RING_SIZE \
410 CFG_INI_UINT("dp_tx_ring_size", \
411 WLAN_CFG_TX_RING_SIZE_MIN,\
412 WLAN_CFG_TX_RING_SIZE_MAX,\
413 WLAN_CFG_TX_RING_SIZE,\
414 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size")
415
416#define CFG_DP_NSS_COMP_RING_SIZE \
417 CFG_INI_UINT("dp_nss_comp_ring_size", \
418 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \
419 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \
420 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \
421 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size")
422
423#define CFG_DP_PDEV_LMAC_RING \
424 CFG_INI_UINT("dp_pdev_lmac_ring", \
425 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \
426 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \
427 WLAN_CFG_PER_PDEV_LMAC_RING, \
428 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring")
429
430#define CFG_DP_BASE_HW_MAC_ID \
431 CFG_INI_UINT("dp_base_hw_macid", \
432 0, 1, 1, \
433 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID")
434
Vivek126db5d2018-07-25 22:05:04 +0530435#define CFG_DP_RX_HASH \
436 CFG_INI_BOOL("dp_rx_hash", true, \
437 "DP Rx Hash")
438
439#define CFG_DP_TSO \
440 CFG_INI_BOOL("TSOEnable", false, \
441 "DP TSO Enabled")
442
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530443#define CFG_DP_LRO \
444 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \
445 "DP LRO Enable")
446
447#define CFG_DP_SG \
448 CFG_INI_BOOL("dp_sg_support", false, \
449 "DP SG Enable")
450
451#define CFG_DP_GRO \
452 CFG_INI_BOOL("GROEnable", false, \
453 "DP GRO Enable")
454
455#define CFG_DP_OL_TX_CSUM \
456 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \
457 "DP tx csum Enable")
458
459#define CFG_DP_OL_RX_CSUM \
460 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \
461 "DP rx csum Enable")
462
463#define CFG_DP_RAWMODE \
464 CFG_INI_BOOL("dp_rawmode_support", false, \
465 "DP rawmode Enable")
466
467#define CFG_DP_PEER_FLOW_CTRL \
468 CFG_INI_BOOL("dp_peer_flow_control_support", false, \
469 "DP peer flow ctrl Enable")
470
Vivek126db5d2018-07-25 22:05:04 +0530471#define CFG_DP_NAPI \
472 CFG_INI_BOOL("dp_napi_enabled", MCL_OR_WIN_VALUE(true, false), \
473 "DP Napi Enabled")
474
475#define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \
jitiphil60ac9aa2018-10-05 19:54:04 +0530476 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \
Vivek126db5d2018-07-25 22:05:04 +0530477 "DP TCP UDP Checksum Offload")
478
479#define CFG_DP_DEFRAG_TIMEOUT_CHECK \
480 CFG_INI_BOOL("dp_defrag_timeout_check", true, \
481 "DP Defrag Timeout Check")
482
483#define CFG_DP_WBM_RELEASE_RING \
484 CFG_INI_UINT("dp_wbm_release_ring", \
485 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \
486 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \
487 WLAN_CFG_WBM_RELEASE_RING_SIZE, \
488 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring")
489
490#define CFG_DP_TCL_CMD_RING \
491 CFG_INI_UINT("dp_tcl_cmd_ring", \
492 WLAN_CFG_TCL_CMD_RING_SIZE_MIN, \
493 WLAN_CFG_TCL_CMD_RING_SIZE_MAX, \
494 WLAN_CFG_TCL_CMD_RING_SIZE, \
495 CFG_VALUE_OR_DEFAULT, "DP TCL command ring")
496
497#define CFG_DP_TCL_STATUS_RING \
498 CFG_INI_UINT("dp_tcl_status_ring",\
499 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \
500 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \
501 WLAN_CFG_TCL_STATUS_RING_SIZE, \
502 CFG_VALUE_OR_DEFAULT, "DP TCL status ring")
503
504#define CFG_DP_REO_REINJECT_RING \
505 CFG_INI_UINT("dp_reo_reinject_ring", \
506 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \
507 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \
508 WLAN_CFG_REO_REINJECT_RING_SIZE, \
509 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring")
510
511#define CFG_DP_RX_RELEASE_RING \
512 CFG_INI_UINT("dp_rx_release_ring", \
513 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \
514 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \
515 WLAN_CFG_RX_RELEASE_RING_SIZE, \
516 CFG_VALUE_OR_DEFAULT, "DP Rx release ring")
517
518#define CFG_DP_REO_EXCEPTION_RING \
519 CFG_INI_UINT("dp_reo_exception_ring", \
520 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \
521 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \
522 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \
523 CFG_VALUE_OR_DEFAULT, "DP REO exception ring")
524
525#define CFG_DP_REO_CMD_RING \
526 CFG_INI_UINT("dp_reo_cmd_ring", \
527 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \
528 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \
529 WLAN_CFG_REO_CMD_RING_SIZE, \
530 CFG_VALUE_OR_DEFAULT, "DP REO command ring")
531
532#define CFG_DP_REO_STATUS_RING \
533 CFG_INI_UINT("dp_reo_status_ring", \
534 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \
535 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \
536 WLAN_CFG_REO_STATUS_RING_SIZE, \
537 CFG_VALUE_OR_DEFAULT, "DP REO status ring")
538
539#define CFG_DP_RXDMA_BUF_RING \
540 CFG_INI_UINT("dp_rxdma_buf_ring", \
541 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \
542 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \
543 WLAN_CFG_RXDMA_BUF_RING_SIZE, \
544 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring")
545
546#define CFG_DP_RXDMA_REFILL_RING \
547 CFG_INI_UINT("dp_rxdma_refill_ring", \
548 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \
549 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \
550 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \
551 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring")
552
553#define CFG_DP_RXDMA_MONITOR_BUF_RING \
554 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \
555 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \
556 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \
557 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \
558 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring")
559
560#define CFG_DP_RXDMA_MONITOR_DST_RING \
561 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \
562 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \
563 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \
564 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \
565 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
566
567#define CFG_DP_RXDMA_MONITOR_STATUS_RING \
568 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \
569 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \
570 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \
571 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \
572 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring")
573
574#define CFG_DP_RXDMA_MONITOR_DESC_RING \
575 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \
576 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \
577 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \
578 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \
579 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
580
581#define CFG_DP_RXDMA_ERR_DST_RING \
582 CFG_INI_UINT("dp_rxdma_err_dst_ring", \
583 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \
584 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \
585 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \
586 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring")
587
Krunal Soni03ba0f52019-02-12 11:44:46 -0800588#define CFG_DP_PER_PKT_LOGGING \
589 CFG_INI_UINT("enable_verbose_debug", \
590 0, 0xffff, 0, \
591 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging")
592
jitiphil60ac9aa2018-10-05 19:54:04 +0530593#define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \
594 CFG_INI_UINT("TxFlowStartQueueOffset", \
595 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \
596 CFG_VALUE_OR_DEFAULT, "Start queue offset")
597
598#define CFG_DP_TX_FLOW_STOP_QUEUE_TH \
599 CFG_INI_UINT("TxFlowStopQueueThreshold", \
600 0, 50, 15, \
601 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold")
602
603#define CFG_DP_IPA_UC_TX_BUF_SIZE \
604 CFG_INI_UINT("IpaUcTxBufSize", \
605 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \
606 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size")
607
608#define CFG_DP_IPA_UC_TX_PARTITION_BASE \
609 CFG_INI_UINT("IpaUcTxPartitionBase", \
610 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \
611 CFG_VALUE_OR_DEFAULT, "IPA tx partition base")
612
613#define CFG_DP_IPA_UC_RX_IND_RING_COUNT \
614 CFG_INI_UINT("IpaUcRxIndRingCount", \
615 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \
616 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count")
617
618#define CFG_DP_REORDER_OFFLOAD_SUPPORT \
619 CFG_INI_UINT("gReorderOffloadSupported", \
620 0, 1, 1, \
621 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware")
622
623#define CFG_DP_AP_STA_SECURITY_SEPERATION \
624 CFG_INI_BOOL("gDisableIntraBssFwd", \
625 false, "Disable intrs BSS Rx packets")
626
627#define CFG_DP_ENABLE_DATA_STALL_DETECTION \
628 CFG_INI_BOOL("gEnableDataStallDetection", \
629 true, "Enable/Disable Data stall detection")
630
Vivek126db5d2018-07-25 22:05:04 +0530631#define CFG_DP \
632 CFG(CFG_DP_HTT_PACKET_TYPE) \
633 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \
634 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \
635 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \
636 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \
637 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \
638 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \
639 CFG(CFG_DP_MAX_ALLOC_SIZE) \
640 CFG(CFG_DP_MAX_CLIENTS) \
641 CFG(CFG_DP_MAX_PEER_ID) \
642 CFG(CFG_DP_REO_DEST_RINGS) \
643 CFG(CFG_DP_TCL_DATA_RINGS) \
644 CFG(CFG_DP_TX_DESC) \
645 CFG(CFG_DP_TX_EXT_DESC) \
646 CFG(CFG_DP_TX_EXT_DESC_POOLS) \
647 CFG(CFG_DP_PDEV_RX_RING) \
648 CFG(CFG_DP_PDEV_TX_RING) \
649 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \
650 CFG(CFG_DP_TX_COMPL_RING_SIZE) \
651 CFG(CFG_DP_TX_RING_SIZE) \
652 CFG(CFG_DP_NSS_COMP_RING_SIZE) \
653 CFG(CFG_DP_PDEV_LMAC_RING) \
654 CFG(CFG_DP_BASE_HW_MAC_ID) \
Vivek126db5d2018-07-25 22:05:04 +0530655 CFG(CFG_DP_RX_HASH) \
656 CFG(CFG_DP_TSO) \
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530657 CFG(CFG_DP_LRO) \
658 CFG(CFG_DP_SG) \
659 CFG(CFG_DP_GRO) \
660 CFG(CFG_DP_OL_TX_CSUM) \
661 CFG(CFG_DP_OL_RX_CSUM) \
662 CFG(CFG_DP_RAWMODE) \
663 CFG(CFG_DP_PEER_FLOW_CTRL) \
Vivek126db5d2018-07-25 22:05:04 +0530664 CFG(CFG_DP_NAPI) \
665 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \
666 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \
667 CFG(CFG_DP_WBM_RELEASE_RING) \
668 CFG(CFG_DP_TCL_CMD_RING) \
669 CFG(CFG_DP_TCL_STATUS_RING) \
670 CFG(CFG_DP_REO_REINJECT_RING) \
671 CFG(CFG_DP_RX_RELEASE_RING) \
672 CFG(CFG_DP_REO_EXCEPTION_RING) \
673 CFG(CFG_DP_REO_CMD_RING) \
674 CFG(CFG_DP_REO_STATUS_RING) \
675 CFG(CFG_DP_RXDMA_BUF_RING) \
676 CFG(CFG_DP_RXDMA_REFILL_RING) \
677 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \
678 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \
679 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \
680 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530681 CFG(CFG_DP_RXDMA_ERR_DST_RING) \
Krunal Soni03ba0f52019-02-12 11:44:46 -0800682 CFG(CFG_DP_PER_PKT_LOGGING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530683 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \
684 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \
685 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \
686 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \
687 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \
688 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \
689 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \
690 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION)
Vivek126db5d2018-07-25 22:05:04 +0530691
692#endif /* _CFG_DP_H_ */