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Vivek126db5d2018-07-25 22:05:04 +05301/*
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -08002 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
Vivek126db5d2018-07-25 22:05:04 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all
7 * copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16 * PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/**
20 * DOC: This file contains definitions of Data Path configuration.
21 */
22
23#ifndef _CFG_DP_H_
24#define _CFG_DP_H_
25
26#include "cfg_define.h"
27
28#define WLAN_CFG_MAX_CLIENTS 64
Pratik Gandhi4cce3e02018-09-05 19:43:11 +053029#define WLAN_CFG_MAX_CLIENTS_MIN 8
Vivek126db5d2018-07-25 22:05:04 +053030#define WLAN_CFG_MAX_CLIENTS_MAX 64
31
32/* Change this to a lower value to enforce scattered idle list mode */
33#define WLAN_CFG_MAX_ALLOC_SIZE 0x200000
sumedh baikady3c05f972019-04-18 15:30:30 -070034#define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000
Vivek126db5d2018-07-25 22:05:04 +053035#define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000
36
37#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
38#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
39#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
40
41#ifdef CONFIG_MCL
hangtian04f0ad42019-06-07 11:04:02 +080042#if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \
43 defined(QCA_LL_PDEV_TX_FLOW_CONTROL)
jitiphil60ac9aa2018-10-05 19:54:04 +053044#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10
45#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15
Vivek126db5d2018-07-25 22:05:04 +053046#else
jitiphil60ac9aa2018-10-05 19:54:04 +053047#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
48#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
Vivek126db5d2018-07-25 22:05:04 +053049#endif
Vivek126db5d2018-07-25 22:05:04 +053050#endif
51
52#define WLAN_CFG_PER_PDEV_TX_RING_MIN 0
53#define WLAN_CFG_PER_PDEV_TX_RING_MAX 1
54
55#ifdef CONFIG_MCL
56#define WLAN_CFG_PER_PDEV_RX_RING 0
57#define WLAN_CFG_PER_PDEV_LMAC_RING 0
jitiphil60ac9aa2018-10-05 19:54:04 +053058#define WLAN_LRO_ENABLE 0
Venkata Sharath Chandra Manchala8d583a82019-04-21 12:32:24 -070059#define WLAN_CFG_MAC_PER_TARGET 2
Vivek126db5d2018-07-25 22:05:04 +053060#ifdef IPA_OFFLOAD
Mohit Khanna81179cb2018-08-16 20:50:43 -070061/* Size of TCL TX Ring */
62#define WLAN_CFG_TX_RING_SIZE 1024
jitiphil60ac9aa2018-10-05 19:54:04 +053063#define WLAN_CFG_PER_PDEV_TX_RING 0
64#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048
65#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000
66#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024
Vivek126db5d2018-07-25 22:05:04 +053067#else
68#define WLAN_CFG_TX_RING_SIZE 512
jitiphil60ac9aa2018-10-05 19:54:04 +053069#define WLAN_CFG_PER_PDEV_TX_RING 1
70#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
71#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
72#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
Vivek126db5d2018-07-25 22:05:04 +053073#endif
74#define WLAN_CFG_TX_COMP_RING_SIZE 1024
75
76/* Tx Descriptor and Tx Extension Descriptor pool sizes */
77#define WLAN_CFG_NUM_TX_DESC 1024
78#define WLAN_CFG_NUM_TX_EXT_DESC 1024
79
80/* Interrupt Mitigation - Batch threshold in terms of number of frames */
81#define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1
82#define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1
83#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1
84
85/* Interrupt Mitigation - Timer threshold in us */
86#define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8
87#define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8
88#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8
Vivek126db5d2018-07-25 22:05:04 +053089#endif
90
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -070091#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256
92#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 256
93
Vivek126db5d2018-07-25 22:05:04 +053094#define WLAN_CFG_PER_PDEV_RX_RING_MIN 0
95#define WLAN_CFG_PER_PDEV_RX_RING_MAX 0
96
97#define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0
98#define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1
99
100#define WLAN_CFG_TX_RING_SIZE_MIN 512
101#define WLAN_CFG_TX_RING_SIZE_MAX 2048
102
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530103#define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512
Vivek126db5d2018-07-25 22:05:04 +0530104#define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000
105
106#define WLAN_CFG_NUM_TX_DESC_MIN 1024
Shashikala Prabhu550e69c2019-03-13 17:41:17 +0530107#define WLAN_CFG_NUM_TX_DESC_MAX 32768
Vivek126db5d2018-07-25 22:05:04 +0530108
109#define WLAN_CFG_NUM_TX_EXT_DESC_MIN 1024
110#define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000
111
112#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1
113#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256
114
115#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1
116#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128
117
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700118#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1
119#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128
120
121#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1
122#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128
123
Vivek126db5d2018-07-25 22:05:04 +0530124#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1
125#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1
126
127#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8
128#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 100
129
130#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8
131#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500
132
133#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8
134#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000
135
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700136#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8
137#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 500
138
139#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8
140#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500
141
Aniruddha Paul7d991b32018-09-03 17:40:00 +0530142#define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000
143#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000
Aniruddha Paul1b267242019-03-15 12:01:06 +0530144#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000
Vivek126db5d2018-07-25 22:05:04 +0530145
146#ifdef QCA_LL_TX_FLOW_CONTROL_V2
147
148/* Per vdev pools */
149#define WLAN_CFG_NUM_TX_DESC_POOL 3
150#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
151
152#else /* QCA_LL_TX_FLOW_CONTROL_V2 */
153
154#ifdef TX_PER_PDEV_DESC_POOL
155#define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT
156#define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT
157
158#else /* TX_PER_PDEV_DESC_POOL */
159
160#define WLAN_CFG_NUM_TX_DESC_POOL 3
161#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
162
163#endif /* TX_PER_PDEV_DESC_POOL */
164#endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
165
166#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1
167#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4
168
169#define WLAN_CFG_HTT_PKT_TYPE 2
170#define WLAN_CFG_HTT_PKT_TYPE_MIN 2
171#define WLAN_CFG_HTT_PKT_TYPE_MAX 2
172
173#define WLAN_CFG_MAX_PEER_ID 64
174#define WLAN_CFG_MAX_PEER_ID_MIN 64
175#define WLAN_CFG_MAX_PEER_ID_MAX 64
176
177#define WLAN_CFG_RX_DEFRAG_TIMEOUT 100
178#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100
179#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100
180
181#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
182#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
183#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
184
185#define WLAN_CFG_NUM_REO_DEST_RING 4
186#define WLAN_CFG_NUM_REO_DEST_RING_MIN 4
187#define WLAN_CFG_NUM_REO_DEST_RING_MAX 4
188
189#define WLAN_CFG_WBM_RELEASE_RING_SIZE 64
190#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64
191#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 64
192
193#define WLAN_CFG_TCL_CMD_RING_SIZE 32
194#define WLAN_CFG_TCL_CMD_RING_SIZE_MIN 32
195#define WLAN_CFG_TCL_CMD_RING_SIZE_MAX 32
196
197#define WLAN_CFG_TCL_STATUS_RING_SIZE 32
198#define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32
199#define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32
200
201#if defined(QCA_WIFI_QCA6290)
202#define WLAN_CFG_REO_DST_RING_SIZE 1024
203#else
204#define WLAN_CFG_REO_DST_RING_SIZE 2048
205#endif
206
207#define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024
208#define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048
209
210#define WLAN_CFG_REO_REINJECT_RING_SIZE 32
211#define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32
212#define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32
213
214#define WLAN_CFG_RX_RELEASE_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530215#define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530216#if defined(QCA_WIFI_QCA6390)
Vivek126db5d2018-07-25 22:05:04 +0530217#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530218#else
219#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192
220#endif
Vivek126db5d2018-07-25 22:05:04 +0530221
222#define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128
223#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128
224#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128
225
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700226#define WLAN_CFG_REO_CMD_RING_SIZE 128
Vivek126db5d2018-07-25 22:05:04 +0530227#define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700228#define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128
Vivek126db5d2018-07-25 22:05:04 +0530229
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700230#define WLAN_CFG_REO_STATUS_RING_SIZE 256
Vivek126db5d2018-07-25 22:05:04 +0530231#define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -0800232#define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048
Vivek126db5d2018-07-25 22:05:04 +0530233
234#define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024
235#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024
236#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024
237
238#define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530239#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16
Vivek126db5d2018-07-25 22:05:04 +0530240#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096
241
242#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530243#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800244#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530245
246#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530247#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48
Kai Chen692850b2018-12-05 15:06:07 -0800248#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530249
250#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530251#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800252#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530253
254#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096
255#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096
Kai Chen692850b2018-12-05 15:06:07 -0800256#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384
Vivek126db5d2018-07-25 22:05:04 +0530257
258#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024
259#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024
Karunakar Dasineni79768452018-09-07 11:32:34 -0700260#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530261
262/* DP INI Declerations */
263#define CFG_DP_HTT_PACKET_TYPE \
264 CFG_INI_UINT("dp_htt_packet_type", \
265 WLAN_CFG_HTT_PKT_TYPE_MIN, \
266 WLAN_CFG_HTT_PKT_TYPE_MAX, \
267 WLAN_CFG_HTT_PKT_TYPE, \
268 CFG_VALUE_OR_DEFAULT, "DP HTT packet type")
269
270#define CFG_DP_INT_BATCH_THRESHOLD_OTHER \
271 CFG_INI_UINT("dp_int_batch_threshold_other", \
Karunakar Dasineni2b7628c2018-10-23 22:59:37 -0700272 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \
273 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \
274 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700275 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other")
Vivek126db5d2018-07-25 22:05:04 +0530276
277#define CFG_DP_INT_BATCH_THRESHOLD_RX \
278 CFG_INI_UINT("dp_int_batch_threshold_rx", \
279 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \
280 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \
281 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700282 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx")
Vivek126db5d2018-07-25 22:05:04 +0530283
284#define CFG_DP_INT_BATCH_THRESHOLD_TX \
285 CFG_INI_UINT("dp_int_batch_threshold_tx", \
286 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \
287 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \
288 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \
289 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx")
290
291#define CFG_DP_INT_TIMER_THRESHOLD_OTHER \
292 CFG_INI_UINT("dp_int_timer_threshold_other", \
293 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \
294 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \
295 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \
296 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other")
297
298#define CFG_DP_INT_TIMER_THRESHOLD_RX \
299 CFG_INI_UINT("dp_int_timer_threshold_rx", \
300 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \
301 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \
302 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \
303 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx")
304
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700305#define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \
306 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \
307 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \
308 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \
309 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \
310 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring")
311
312#define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \
313 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \
314 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \
315 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \
316 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \
317 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring")
318
Vivek126db5d2018-07-25 22:05:04 +0530319#define CFG_DP_INT_TIMER_THRESHOLD_TX \
320 CFG_INI_UINT("dp_int_timer_threshold_tx", \
321 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \
322 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \
323 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \
324 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx")
325
326#define CFG_DP_MAX_ALLOC_SIZE \
327 CFG_INI_UINT("dp_max_alloc_size", \
328 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \
329 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \
330 WLAN_CFG_MAX_ALLOC_SIZE, \
331 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size")
332
333#define CFG_DP_MAX_CLIENTS \
334 CFG_INI_UINT("dp_max_clients", \
335 WLAN_CFG_MAX_CLIENTS_MIN, \
336 WLAN_CFG_MAX_CLIENTS_MAX, \
337 WLAN_CFG_MAX_CLIENTS, \
338 CFG_VALUE_OR_DEFAULT, "DP Max Clients")
339
340#define CFG_DP_MAX_PEER_ID \
341 CFG_INI_UINT("dp_max_peer_id", \
342 WLAN_CFG_MAX_PEER_ID_MIN, \
343 WLAN_CFG_MAX_PEER_ID_MAX, \
344 WLAN_CFG_MAX_PEER_ID, \
345 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID")
346
347#define CFG_DP_REO_DEST_RINGS \
348 CFG_INI_UINT("dp_reo_dest_rings", \
349 WLAN_CFG_NUM_REO_DEST_RING_MIN, \
350 WLAN_CFG_NUM_REO_DEST_RING_MAX, \
351 WLAN_CFG_NUM_REO_DEST_RING, \
352 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings")
353
354#define CFG_DP_TCL_DATA_RINGS \
355 CFG_INI_UINT("dp_tcl_data_rings", \
356 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \
357 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \
358 WLAN_CFG_NUM_TCL_DATA_RINGS, \
359 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings")
360
361#define CFG_DP_TX_DESC \
362 CFG_INI_UINT("dp_tx_desc", \
363 WLAN_CFG_NUM_TX_DESC_MIN, \
364 WLAN_CFG_NUM_TX_DESC_MAX, \
365 WLAN_CFG_NUM_TX_DESC, \
366 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors")
367
368#define CFG_DP_TX_EXT_DESC \
369 CFG_INI_UINT("dp_tx_ext_desc", \
370 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \
371 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \
372 WLAN_CFG_NUM_TX_EXT_DESC, \
373 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors")
374
375#define CFG_DP_TX_EXT_DESC_POOLS \
376 CFG_INI_UINT("dp_tx_ext_desc_pool", \
377 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \
378 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \
379 WLAN_CFG_NUM_TXEXT_DESC_POOL, \
380 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool")
381
382#define CFG_DP_PDEV_RX_RING \
383 CFG_INI_UINT("dp_pdev_rx_ring", \
384 WLAN_CFG_PER_PDEV_RX_RING_MIN, \
385 WLAN_CFG_PER_PDEV_RX_RING_MAX, \
386 WLAN_CFG_PER_PDEV_RX_RING, \
387 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring")
388
389#define CFG_DP_PDEV_TX_RING \
390 CFG_INI_UINT("dp_pdev_tx_ring", \
391 WLAN_CFG_PER_PDEV_TX_RING_MIN, \
392 WLAN_CFG_PER_PDEV_TX_RING_MAX, \
393 WLAN_CFG_PER_PDEV_TX_RING, \
394 CFG_VALUE_OR_DEFAULT, \
395 "DP PDEV Tx Ring")
396
397#define CFG_DP_RX_DEFRAG_TIMEOUT \
398 CFG_INI_UINT("dp_rx_defrag_timeout", \
399 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \
400 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \
401 WLAN_CFG_RX_DEFRAG_TIMEOUT, \
402 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout")
403
404#define CFG_DP_TX_COMPL_RING_SIZE \
405 CFG_INI_UINT("dp_tx_compl_ring_size", \
406 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \
407 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \
408 WLAN_CFG_TX_COMP_RING_SIZE, \
409 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size")
410
411#define CFG_DP_TX_RING_SIZE \
412 CFG_INI_UINT("dp_tx_ring_size", \
413 WLAN_CFG_TX_RING_SIZE_MIN,\
414 WLAN_CFG_TX_RING_SIZE_MAX,\
415 WLAN_CFG_TX_RING_SIZE,\
416 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size")
417
418#define CFG_DP_NSS_COMP_RING_SIZE \
419 CFG_INI_UINT("dp_nss_comp_ring_size", \
420 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \
421 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \
422 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \
423 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size")
424
425#define CFG_DP_PDEV_LMAC_RING \
426 CFG_INI_UINT("dp_pdev_lmac_ring", \
427 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \
428 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \
429 WLAN_CFG_PER_PDEV_LMAC_RING, \
430 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring")
431
432#define CFG_DP_BASE_HW_MAC_ID \
433 CFG_INI_UINT("dp_base_hw_macid", \
434 0, 1, 1, \
435 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID")
436
Vivek126db5d2018-07-25 22:05:04 +0530437#define CFG_DP_RX_HASH \
438 CFG_INI_BOOL("dp_rx_hash", true, \
439 "DP Rx Hash")
440
441#define CFG_DP_TSO \
442 CFG_INI_BOOL("TSOEnable", false, \
443 "DP TSO Enabled")
444
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530445#define CFG_DP_LRO \
446 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \
447 "DP LRO Enable")
448
449#define CFG_DP_SG \
450 CFG_INI_BOOL("dp_sg_support", false, \
451 "DP SG Enable")
452
453#define CFG_DP_GRO \
454 CFG_INI_BOOL("GROEnable", false, \
455 "DP GRO Enable")
456
457#define CFG_DP_OL_TX_CSUM \
458 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \
459 "DP tx csum Enable")
460
461#define CFG_DP_OL_RX_CSUM \
462 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \
463 "DP rx csum Enable")
464
465#define CFG_DP_RAWMODE \
466 CFG_INI_BOOL("dp_rawmode_support", false, \
467 "DP rawmode Enable")
468
469#define CFG_DP_PEER_FLOW_CTRL \
470 CFG_INI_BOOL("dp_peer_flow_control_support", false, \
471 "DP peer flow ctrl Enable")
472
Vivek126db5d2018-07-25 22:05:04 +0530473#define CFG_DP_NAPI \
474 CFG_INI_BOOL("dp_napi_enabled", MCL_OR_WIN_VALUE(true, false), \
475 "DP Napi Enabled")
476
477#define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \
jitiphil60ac9aa2018-10-05 19:54:04 +0530478 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \
Vivek126db5d2018-07-25 22:05:04 +0530479 "DP TCP UDP Checksum Offload")
480
481#define CFG_DP_DEFRAG_TIMEOUT_CHECK \
482 CFG_INI_BOOL("dp_defrag_timeout_check", true, \
483 "DP Defrag Timeout Check")
484
485#define CFG_DP_WBM_RELEASE_RING \
486 CFG_INI_UINT("dp_wbm_release_ring", \
487 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \
488 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \
489 WLAN_CFG_WBM_RELEASE_RING_SIZE, \
490 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring")
491
492#define CFG_DP_TCL_CMD_RING \
493 CFG_INI_UINT("dp_tcl_cmd_ring", \
494 WLAN_CFG_TCL_CMD_RING_SIZE_MIN, \
495 WLAN_CFG_TCL_CMD_RING_SIZE_MAX, \
496 WLAN_CFG_TCL_CMD_RING_SIZE, \
497 CFG_VALUE_OR_DEFAULT, "DP TCL command ring")
498
499#define CFG_DP_TCL_STATUS_RING \
500 CFG_INI_UINT("dp_tcl_status_ring",\
501 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \
502 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \
503 WLAN_CFG_TCL_STATUS_RING_SIZE, \
504 CFG_VALUE_OR_DEFAULT, "DP TCL status ring")
505
506#define CFG_DP_REO_REINJECT_RING \
507 CFG_INI_UINT("dp_reo_reinject_ring", \
508 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \
509 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \
510 WLAN_CFG_REO_REINJECT_RING_SIZE, \
511 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring")
512
513#define CFG_DP_RX_RELEASE_RING \
514 CFG_INI_UINT("dp_rx_release_ring", \
515 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \
516 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \
517 WLAN_CFG_RX_RELEASE_RING_SIZE, \
518 CFG_VALUE_OR_DEFAULT, "DP Rx release ring")
519
520#define CFG_DP_REO_EXCEPTION_RING \
521 CFG_INI_UINT("dp_reo_exception_ring", \
522 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \
523 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \
524 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \
525 CFG_VALUE_OR_DEFAULT, "DP REO exception ring")
526
527#define CFG_DP_REO_CMD_RING \
528 CFG_INI_UINT("dp_reo_cmd_ring", \
529 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \
530 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \
531 WLAN_CFG_REO_CMD_RING_SIZE, \
532 CFG_VALUE_OR_DEFAULT, "DP REO command ring")
533
534#define CFG_DP_REO_STATUS_RING \
535 CFG_INI_UINT("dp_reo_status_ring", \
536 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \
537 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \
538 WLAN_CFG_REO_STATUS_RING_SIZE, \
539 CFG_VALUE_OR_DEFAULT, "DP REO status ring")
540
541#define CFG_DP_RXDMA_BUF_RING \
542 CFG_INI_UINT("dp_rxdma_buf_ring", \
543 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \
544 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \
545 WLAN_CFG_RXDMA_BUF_RING_SIZE, \
546 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring")
547
548#define CFG_DP_RXDMA_REFILL_RING \
549 CFG_INI_UINT("dp_rxdma_refill_ring", \
550 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \
551 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \
552 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \
553 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring")
554
555#define CFG_DP_RXDMA_MONITOR_BUF_RING \
556 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \
557 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \
558 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \
559 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \
560 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring")
561
562#define CFG_DP_RXDMA_MONITOR_DST_RING \
563 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \
564 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \
565 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \
566 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \
567 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
568
569#define CFG_DP_RXDMA_MONITOR_STATUS_RING \
570 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \
571 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \
572 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \
573 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \
574 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring")
575
576#define CFG_DP_RXDMA_MONITOR_DESC_RING \
577 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \
578 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \
579 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \
580 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \
581 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
582
583#define CFG_DP_RXDMA_ERR_DST_RING \
584 CFG_INI_UINT("dp_rxdma_err_dst_ring", \
585 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \
586 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \
587 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \
588 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring")
589
Krunal Soni03ba0f52019-02-12 11:44:46 -0800590#define CFG_DP_PER_PKT_LOGGING \
591 CFG_INI_UINT("enable_verbose_debug", \
592 0, 0xffff, 0, \
593 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging")
594
jitiphil60ac9aa2018-10-05 19:54:04 +0530595#define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \
596 CFG_INI_UINT("TxFlowStartQueueOffset", \
597 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \
598 CFG_VALUE_OR_DEFAULT, "Start queue offset")
599
600#define CFG_DP_TX_FLOW_STOP_QUEUE_TH \
601 CFG_INI_UINT("TxFlowStopQueueThreshold", \
602 0, 50, 15, \
603 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold")
604
605#define CFG_DP_IPA_UC_TX_BUF_SIZE \
606 CFG_INI_UINT("IpaUcTxBufSize", \
607 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \
608 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size")
609
610#define CFG_DP_IPA_UC_TX_PARTITION_BASE \
611 CFG_INI_UINT("IpaUcTxPartitionBase", \
612 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \
613 CFG_VALUE_OR_DEFAULT, "IPA tx partition base")
614
615#define CFG_DP_IPA_UC_RX_IND_RING_COUNT \
616 CFG_INI_UINT("IpaUcRxIndRingCount", \
617 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \
618 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count")
619
620#define CFG_DP_REORDER_OFFLOAD_SUPPORT \
621 CFG_INI_UINT("gReorderOffloadSupported", \
622 0, 1, 1, \
623 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware")
624
625#define CFG_DP_AP_STA_SECURITY_SEPERATION \
626 CFG_INI_BOOL("gDisableIntraBssFwd", \
627 false, "Disable intrs BSS Rx packets")
628
629#define CFG_DP_ENABLE_DATA_STALL_DETECTION \
630 CFG_INI_BOOL("gEnableDataStallDetection", \
631 true, "Enable/Disable Data stall detection")
632
Vivek126db5d2018-07-25 22:05:04 +0530633#define CFG_DP \
634 CFG(CFG_DP_HTT_PACKET_TYPE) \
635 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \
636 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \
637 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \
638 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \
639 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \
640 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \
641 CFG(CFG_DP_MAX_ALLOC_SIZE) \
642 CFG(CFG_DP_MAX_CLIENTS) \
643 CFG(CFG_DP_MAX_PEER_ID) \
644 CFG(CFG_DP_REO_DEST_RINGS) \
645 CFG(CFG_DP_TCL_DATA_RINGS) \
646 CFG(CFG_DP_TX_DESC) \
647 CFG(CFG_DP_TX_EXT_DESC) \
648 CFG(CFG_DP_TX_EXT_DESC_POOLS) \
649 CFG(CFG_DP_PDEV_RX_RING) \
650 CFG(CFG_DP_PDEV_TX_RING) \
651 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \
652 CFG(CFG_DP_TX_COMPL_RING_SIZE) \
653 CFG(CFG_DP_TX_RING_SIZE) \
654 CFG(CFG_DP_NSS_COMP_RING_SIZE) \
655 CFG(CFG_DP_PDEV_LMAC_RING) \
656 CFG(CFG_DP_BASE_HW_MAC_ID) \
Vivek126db5d2018-07-25 22:05:04 +0530657 CFG(CFG_DP_RX_HASH) \
658 CFG(CFG_DP_TSO) \
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530659 CFG(CFG_DP_LRO) \
660 CFG(CFG_DP_SG) \
661 CFG(CFG_DP_GRO) \
662 CFG(CFG_DP_OL_TX_CSUM) \
663 CFG(CFG_DP_OL_RX_CSUM) \
664 CFG(CFG_DP_RAWMODE) \
665 CFG(CFG_DP_PEER_FLOW_CTRL) \
Vivek126db5d2018-07-25 22:05:04 +0530666 CFG(CFG_DP_NAPI) \
667 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \
668 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \
669 CFG(CFG_DP_WBM_RELEASE_RING) \
670 CFG(CFG_DP_TCL_CMD_RING) \
671 CFG(CFG_DP_TCL_STATUS_RING) \
672 CFG(CFG_DP_REO_REINJECT_RING) \
673 CFG(CFG_DP_RX_RELEASE_RING) \
674 CFG(CFG_DP_REO_EXCEPTION_RING) \
675 CFG(CFG_DP_REO_CMD_RING) \
676 CFG(CFG_DP_REO_STATUS_RING) \
677 CFG(CFG_DP_RXDMA_BUF_RING) \
678 CFG(CFG_DP_RXDMA_REFILL_RING) \
679 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \
680 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \
681 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \
682 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530683 CFG(CFG_DP_RXDMA_ERR_DST_RING) \
Krunal Soni03ba0f52019-02-12 11:44:46 -0800684 CFG(CFG_DP_PER_PKT_LOGGING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530685 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \
686 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \
687 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \
688 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \
689 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \
690 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \
691 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \
692 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION)
Vivek126db5d2018-07-25 22:05:04 +0530693
694#endif /* _CFG_DP_H_ */