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gerrit-public.fairphone.software / toolchain / llvm-project / 199c8235551c37b8a51a44c080f7fae1b7ab8884 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 1ac563010fd59be58248d49c545d2e70311fdb70 [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]394def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
398
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]399multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
409}
410
411defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
413 VEX_W;
414
415def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
417
418def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
420
421def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
424 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]425def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
426 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]427
428multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
429 X86MemOperand x86memop, PatFrag ld_frag,
430 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
431 RegisterClass KRC> {
432 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
434 [(set DstRC:$dst,
435 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
436 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
437 VR128X:$src),
438 !strconcat(OpcodeStr,
439 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
440 [(set DstRC:$dst,
441 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
442 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]443 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]444 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
445 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
446 [(set DstRC:$dst,
447 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
448 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
449 x86memop:$src),
450 !strconcat(OpcodeStr,
451 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
452 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
453 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]454 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]455}
456
457defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
458 loadi32, VR512, v16i32, v4i32, VK16WM>,
459 EVEX_V512, EVEX_CD8<32, CD8VT1>;
460defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
461 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
462 EVEX_CD8<64, CD8VT1>;
463
464def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
465 (VBROADCASTSSZrr VR128X:$src)>;
466def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
467 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]468
469def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
470 (VBROADCASTSSZrr VR128X:$src)>;
471def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
472 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]473
474// Provide fallback in case the load node that is used in the patterns above
475// is used by additional users, which prevents the pattern selection.
476def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
477 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
478def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
479 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
480
481
482let Predicates = [HasAVX512] in {
483def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
484 (EXTRACT_SUBREG
485 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
486 addr:$src)), sub_ymm)>;
487}
488//===----------------------------------------------------------------------===//
489// AVX-512 BROADCAST MASK TO VECTOR REGISTER
490//---
491
492multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
493 RegisterClass DstRC, RegisterClass KRC,
494 ValueType OpVT, ValueType SrcVT> {
495def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
496 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
497 []>, EVEX;
498}
499
500defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
501 VK16, v16i32, v16i1>, EVEX_V512;
502defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
503 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
504
505//===----------------------------------------------------------------------===//
506// AVX-512 - VPERM
507//
508// -- immediate form --
509multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
510 SDNode OpNode, PatFrag mem_frag,
511 X86MemOperand x86memop, ValueType OpVT> {
512 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
513 (ins RC:$src1, i8imm:$src2),
514 !strconcat(OpcodeStr,
515 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
516 [(set RC:$dst,
517 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
518 EVEX;
519 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
520 (ins x86memop:$src1, i8imm:$src2),
521 !strconcat(OpcodeStr,
522 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
523 [(set RC:$dst,
524 (OpVT (OpNode (mem_frag addr:$src1),
525 (i8 imm:$src2))))]>, EVEX;
526}
527
528defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
529 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
530let ExeDomain = SSEPackedDouble in
531defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
532 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
533
534// -- VPERM - register form --
535multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
536 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
537
538 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
539 (ins RC:$src1, RC:$src2),
540 !strconcat(OpcodeStr,
541 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
542 [(set RC:$dst,
543 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
544
545 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
546 (ins RC:$src1, x86memop:$src2),
547 !strconcat(OpcodeStr,
548 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
549 [(set RC:$dst,
550 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
551 EVEX_4V;
552}
553
554defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
555 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
556defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
557 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
558let ExeDomain = SSEPackedSingle in
559defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
560 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
561let ExeDomain = SSEPackedDouble in
562defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
563 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
564
565// -- VPERM2I - 3 source operands form --
566multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
567 PatFrag mem_frag, X86MemOperand x86memop,
568 ValueType OpVT> {
569let Constraints = "$src1 = $dst" in {
570 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
571 (ins RC:$src1, RC:$src2, RC:$src3),
572 !strconcat(OpcodeStr,
573 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
574 [(set RC:$dst,
575 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
576 EVEX_4V;
577
578 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
579 (ins RC:$src1, RC:$src2, x86memop:$src3),
580 !strconcat(OpcodeStr,
581 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
582 [(set RC:$dst,
583 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
584 (mem_frag addr:$src3))))]>, EVEX_4V;
585 }
586}
587defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
588 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
589defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
590 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
591defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
592 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
593defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
594 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
595
596//===----------------------------------------------------------------------===//
597// AVX-512 - BLEND using mask
598//
599multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
600 RegisterClass KRC, RegisterClass RC,
601 X86MemOperand x86memop, PatFrag mem_frag,
602 SDNode OpNode, ValueType vt> {
603 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
604 (ins KRC:$mask, RC:$src1, RC:$src2),
605 !strconcat(OpcodeStr,
606 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
607 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
608 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
609
610 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
611 (ins KRC:$mask, RC:$src1, x86memop:$src2),
612 !strconcat(OpcodeStr,
613 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
614 []>,
615 EVEX_4V, EVEX_K;
616}
617
618let ExeDomain = SSEPackedSingle in
619defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
620 memopv16f32, vselect, v16f32>,
621 EVEX_CD8<32, CD8VF>, EVEX_V512;
622let ExeDomain = SSEPackedDouble in
623defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
624 memopv8f64, vselect, v8f64>,
625 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
626
627defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
628 memopv8i64, vselect, v16i32>,
629 EVEX_CD8<32, CD8VF>, EVEX_V512;
630
631defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
632 memopv8i64, vselect, v8i64>, VEX_W,
633 EVEX_CD8<64, CD8VF>, EVEX_V512;
634
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]635let Predicates = [HasAVX512] in {
636def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
637 (v8f32 VR256X:$src2))),
638 (EXTRACT_SUBREG
639 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
640 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
641 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
642
643def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
644 (v8i32 VR256X:$src2))),
645 (EXTRACT_SUBREG
646 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
647 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
648 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
649}
650
651multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
652 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
653 SDNode OpNode, ValueType vt> {
654 def rr : AVX512BI<opc, MRMSrcReg,
655 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
656 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
657 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
658 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
659 def rm : AVX512BI<opc, MRMSrcMem,
660 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
661 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
662 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
663 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
664}
665
666defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
667 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
668defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
669 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
670
671defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
672 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
673defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
674 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
675
676def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
677 (COPY_TO_REGCLASS (VPCMPGTDZrr
678 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
679 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
680
681def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
682 (COPY_TO_REGCLASS (VPCMPEQDZrr
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
685
686multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
687 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
688 SDNode OpNode, ValueType vt, Operand CC, string asm,
689 string asm_alt> {
690 def rri : AVX512AIi8<opc, MRMSrcReg,
691 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
692 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
693 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
694 def rmi : AVX512AIi8<opc, MRMSrcMem,
695 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
696 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
697 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
698 // Accept explicit immediate argument form instead of comparison code.
699 let neverHasSideEffects = 1 in {
700 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
701 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
702 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
703 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
704 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
705 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
706 }
707}
708
709defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
710 X86cmpm, v16i32, AVXCC,
711 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
712 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
713 EVEX_V512, EVEX_CD8<32, CD8VF>;
714defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
715 X86cmpmu, v16i32, AVXCC,
716 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
717 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
718 EVEX_V512, EVEX_CD8<32, CD8VF>;
719
720defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
721 X86cmpm, v8i64, AVXCC,
722 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
723 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
724 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
725defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
726 X86cmpmu, v8i64, AVXCC,
727 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
728 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
729 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
730
731// avx512_cmp_packed - sse 1 & 2 compare packed instructions
732multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
733 X86MemOperand x86memop, Operand CC,
734 SDNode OpNode, ValueType vt, string asm,
735 string asm_alt, Domain d> {
736 def rri : AVX512PIi8<0xC2, MRMSrcReg,
737 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
738 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
739 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
740 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
741 [(set KRC:$dst,
742 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
743
744 // Accept explicit immediate argument form instead of comparison code.
745 let neverHasSideEffects = 1 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]746 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]747 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]748 asm_alt, [], d>;
749 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]750 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]751 asm_alt, [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]752 }
753}
754
755defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
756 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
757 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]758 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]759defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
760 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
761 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]762 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]763 EVEX_CD8<64, CD8VF>;
764
765def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
766 (COPY_TO_REGCLASS (VCMPPSZrri
767 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
768 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
769 imm:$cc), VK8)>;
770def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
771 (COPY_TO_REGCLASS (VPCMPDZrri
772 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
773 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
774 imm:$cc), VK8)>;
775def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
776 (COPY_TO_REGCLASS (VPCMPUDZrri
777 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
778 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
779 imm:$cc), VK8)>;
780
781// Mask register copy, including
782// - copy between mask registers
783// - load/store mask registers
784// - copy from GPR to mask register and vice versa
785//
786multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
787 string OpcodeStr, RegisterClass KRC,
788 ValueType vt, X86MemOperand x86memop> {
789 let neverHasSideEffects = 1 in {
790 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
791 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
792 let mayLoad = 1 in
793 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
794 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
795 [(set KRC:$dst, (vt (load addr:$src)))]>;
796 let mayStore = 1 in
797 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
799 }
800}
801
802multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
803 string OpcodeStr,
804 RegisterClass KRC, RegisterClass GRC> {
805 let neverHasSideEffects = 1 in {
806 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
808 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
809 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
810 }
811}
812
813let Predicates = [HasAVX512] in {
814 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
815 VEX, TB;
816 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
817 VEX, TB;
818}
819
820let Predicates = [HasAVX512] in {
821 // GR16 from/to 16-bit mask
822 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
823 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
824 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
825 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
826
827 // Store kreg in memory
828 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
829 (KMOVWmk addr:$dst, VK16:$src)>;
830
831 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
832 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
833}
834// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
835let Predicates = [HasAVX512] in {
836 // GR from/to 8-bit mask without native support
837 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
838 (COPY_TO_REGCLASS
839 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
840 VK8)>;
841 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
842 (EXTRACT_SUBREG
843 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
844 sub_8bit)>;
845}
846
847// Mask unary operation
848// - KNOT
849multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
850 RegisterClass KRC, SDPatternOperator OpNode> {
851 let Predicates = [HasAVX512] in
852 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
854 [(set KRC:$dst, (OpNode KRC:$src))]>;
855}
856
857multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
858 SDPatternOperator OpNode> {
859 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
860 VEX, TB;
861}
862
863defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
864
865def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
866def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
867 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
868
869// With AVX-512, 8-bit mask is promoted to 16-bit mask.
870def : Pat<(not VK8:$src),
871 (COPY_TO_REGCLASS
872 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
873
874// Mask binary operation
875// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
876multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
877 RegisterClass KRC, SDPatternOperator OpNode> {
878 let Predicates = [HasAVX512] in
879 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
880 !strconcat(OpcodeStr,
881 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
882 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
883}
884
885multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
886 SDPatternOperator OpNode> {
887 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
888 VEX_4V, VEX_L, TB;
889}
890
891def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
892def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
893
894let isCommutable = 1 in {
895 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
896 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
897 let isCommutable = 0 in
898 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
899 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
900 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
901 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
902}
903
904multiclass avx512_mask_binop_int<string IntName, string InstName> {
905 let Predicates = [HasAVX512] in
906 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
907 VK16:$src1, VK16:$src2),
908 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
909}
910
911defm : avx512_mask_binop_int<"kadd", "KADD">;
912defm : avx512_mask_binop_int<"kand", "KAND">;
913defm : avx512_mask_binop_int<"kandn", "KANDN">;
914defm : avx512_mask_binop_int<"kor", "KOR">;
915defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
916defm : avx512_mask_binop_int<"kxor", "KXOR">;
917// With AVX-512, 8-bit mask is promoted to 16-bit mask.
918multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
919 let Predicates = [HasAVX512] in
920 def : Pat<(OpNode VK8:$src1, VK8:$src2),
921 (COPY_TO_REGCLASS
922 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
923 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
924}
925
926defm : avx512_binop_pat<and, KANDWrr>;
927defm : avx512_binop_pat<andn, KANDNWrr>;
928defm : avx512_binop_pat<or, KORWrr>;
929defm : avx512_binop_pat<xnor, KXNORWrr>;
930defm : avx512_binop_pat<xor, KXORWrr>;
931
932// Mask unpacking
933multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
934 RegisterClass KRC1, RegisterClass KRC2> {
935 let Predicates = [HasAVX512] in
936 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
937 !strconcat(OpcodeStr,
938 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
939}
940
941multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
942 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
943 VEX_4V, VEX_L, OpSize, TB;
944}
945
946defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
947
948multiclass avx512_mask_unpck_int<string IntName, string InstName> {
949 let Predicates = [HasAVX512] in
950 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
951 VK8:$src1, VK8:$src2),
952 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
953}
954
955defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
956// Mask bit testing
957multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
958 SDNode OpNode> {
959 let Predicates = [HasAVX512], Defs = [EFLAGS] in
960 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
961 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
962 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
963}
964
965multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
966 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
967 VEX, TB;
968}
969
970defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
971defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
972
973// Mask shift
974multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
975 SDNode OpNode> {
976 let Predicates = [HasAVX512] in
977 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
978 !strconcat(OpcodeStr,
979 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
980 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
981}
982
983multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
984 SDNode OpNode> {
985 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
986 VEX, OpSize, TA, VEX_W;
987}
988
989defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
990defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
991
992// Mask setting all 0s or 1s
993multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
994 let Predicates = [HasAVX512] in
995 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
996 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
997 [(set KRC:$dst, (VT Val))]>;
998}
999
1000multiclass avx512_mask_setop_w<PatFrag Val> {
1001 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1002 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1003}
1004
1005defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1006defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1007
1008// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1009let Predicates = [HasAVX512] in {
1010 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1011 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1012}
1013def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1014 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1015
1016def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1017 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1018
1019def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1020 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1021
1022//===----------------------------------------------------------------------===//
1023// AVX-512 - Aligned and unaligned load and store
1024//
1025
1026multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1027 X86MemOperand x86memop, PatFrag ld_frag,
1028 string asm, Domain d> {
1029let neverHasSideEffects = 1 in
1030 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1031 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1032 EVEX;
1033let canFoldAsLoad = 1 in
1034 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1035 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1036 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1037let Constraints = "$src1 = $dst" in {
1038 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1039 (ins RC:$src1, KRC:$mask, RC:$src2),
1040 !strconcat(asm,
1041 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1042 EVEX, EVEX_K;
1043 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1044 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1045 !strconcat(asm,
1046 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1047 [], d>, EVEX, EVEX_K;
1048}
1049}
1050
1051defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1052 "vmovaps", SSEPackedSingle>,
1053 EVEX_V512, EVEX_CD8<32, CD8VF>;
1054defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1055 "vmovapd", SSEPackedDouble>,
1056 OpSize, EVEX_V512, VEX_W,
1057 EVEX_CD8<64, CD8VF>;
1058defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1059 "vmovups", SSEPackedSingle>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1060 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1061defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1062 "vmovupd", SSEPackedDouble>,
1063 OpSize, EVEX_V512, VEX_W,
1064 EVEX_CD8<64, CD8VF>;
1065def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1066 "vmovaps\t{$src, $dst|$dst, $src}",
1067 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1068 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1069def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1070 "vmovapd\t{$src, $dst|$dst, $src}",
1071 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1072 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1073 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1074def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1075 "vmovups\t{$src, $dst|$dst, $src}",
1076 [(store (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1077 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1078def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1079 "vmovupd\t{$src, $dst|$dst, $src}",
1080 [(store (v8f64 VR512:$src), addr:$dst)],
1081 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1082 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1083
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1084let neverHasSideEffects = 1 in {
1085 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1086 (ins VR512:$src),
1087 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1088 EVEX, EVEX_V512;
1089 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1090 (ins VR512:$src),
1091 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1092 EVEX, EVEX_V512, VEX_W;
1093let mayStore = 1 in {
1094 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1095 (ins i512mem:$dst, VR512:$src),
1096 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1097 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1098 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1099 (ins i512mem:$dst, VR512:$src),
1100 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1101 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1102}
1103let mayLoad = 1 in {
1104def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1105 (ins i512mem:$src),
1106 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1107 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1108def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1109 (ins i512mem:$src),
1110 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1111 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1112}
1113}
1114
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1115// 512-bit aligned load/store
1116def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1117def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1118
1119def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1120 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1121def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1122 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1123
1124multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1125 RegisterClass RC, RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1126 PatFrag ld_frag, X86MemOperand x86memop> {
1127let neverHasSideEffects = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1128 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1129 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1130let canFoldAsLoad = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1131 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1132 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1133 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1134let mayStore = 1 in
1135 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1136 (ins x86memop:$dst, VR512:$src),
1137 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1138let Constraints = "$src1 = $dst" in {
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1139 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1140 (ins RC:$src1, KRC:$mask, RC:$src2),
1141 !strconcat(asm,
1142 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1143 EVEX, EVEX_K;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1144 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1145 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1146 !strconcat(asm,
1147 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1148 []>, EVEX, EVEX_K;
1149}
1150}
1151
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1152defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1153 memopv16i32, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1154 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1155defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1156 memopv8i64, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1157 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1158
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1159// 512-bit unaligned load/store
1160def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1161def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1162
1163def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1164 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1165def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1166 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1167
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1168let AddedComplexity = 20 in {
1169def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1170 (v16f32 VR512:$src2))),
1171 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1172def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1173 (v8f64 VR512:$src2))),
1174 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1175def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1176 (v16i32 VR512:$src2))),
1177 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1178def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1179 (v8i64 VR512:$src2))),
1180 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1181}
1182// Move Int Doubleword to Packed Double Int
1183//
1184def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1185 "vmovd{z}\t{$src, $dst|$dst, $src}",
1186 [(set VR128X:$dst,
1187 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1188 EVEX, VEX_LIG;
1189def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1190 "vmovd{z}\t{$src, $dst|$dst, $src}",
1191 [(set VR128X:$dst,
1192 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1193 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1194def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1195 "vmovq{z}\t{$src, $dst|$dst, $src}",
1196 [(set VR128X:$dst,
1197 (v2i64 (scalar_to_vector GR64:$src)))],
1198 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1199let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1200def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1201 "vmovq{z}\t{$src, $dst|$dst, $src}",
1202 [(set FR64:$dst, (bitconvert GR64:$src))],
1203 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1204def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1205 "vmovq{z}\t{$src, $dst|$dst, $src}",
1206 [(set GR64:$dst, (bitconvert FR64:$src))],
1207 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1208}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1209def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1210 "vmovq{z}\t{$src, $dst|$dst, $src}",
1211 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1212 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1213 EVEX_CD8<64, CD8VT1>;
1214
1215// Move Int Doubleword to Single Scalar
1216//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1217let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1218def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1219 "vmovd{z}\t{$src, $dst|$dst, $src}",
1220 [(set FR32X:$dst, (bitconvert GR32:$src))],
1221 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1222
1223def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1224 "vmovd{z}\t{$src, $dst|$dst, $src}",
1225 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1226 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1227}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1228
1229// Move Packed Doubleword Int to Packed Double Int
1230//
1231def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1232 "vmovd{z}\t{$src, $dst|$dst, $src}",
1233 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1234 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1235 EVEX, VEX_LIG;
1236def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1237 (ins i32mem:$dst, VR128X:$src),
1238 "vmovd{z}\t{$src, $dst|$dst, $src}",
1239 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1240 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1241 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1242
1243// Move Packed Doubleword Int first element to Doubleword Int
1244//
1245def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1246 "vmovq{z}\t{$src, $dst|$dst, $src}",
1247 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1248 (iPTR 0)))],
1249 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1250 Requires<[HasAVX512, In64BitMode]>;
1251
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1252def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1253 (ins i64mem:$dst, VR128X:$src),
1254 "vmovq{z}\t{$src, $dst|$dst, $src}",
1255 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1256 addr:$dst)], IIC_SSE_MOVDQ>,
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1257 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1258 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1259
1260// Move Scalar Single to Double Int
1261//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1262let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1263def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1264 (ins FR32X:$src),
1265 "vmovd{z}\t{$src, $dst|$dst, $src}",
1266 [(set GR32:$dst, (bitconvert FR32X:$src))],
1267 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1268def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1269 (ins i32mem:$dst, FR32X:$src),
1270 "vmovd{z}\t{$src, $dst|$dst, $src}",
1271 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1272 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1273}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1274
1275// Move Quadword Int to Packed Quadword Int
1276//
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1277def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1278 (ins i64mem:$src),
1279 "vmovq{z}\t{$src, $dst|$dst, $src}",
1280 [(set VR128X:$dst,
1281 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1282 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1283
1284//===----------------------------------------------------------------------===//
1285// AVX-512 MOVSS, MOVSD
1286//===----------------------------------------------------------------------===//
1287
1288multiclass avx512_move_scalar <string asm, RegisterClass RC,
1289 SDNode OpNode, ValueType vt,
1290 X86MemOperand x86memop, PatFrag mem_pat> {
1291 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1292 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1293 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1294 (scalar_to_vector RC:$src2))))],
1295 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1296 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1297 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1298 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1299 EVEX, VEX_LIG;
1300 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1301 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1302 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1303 EVEX, VEX_LIG;
1304}
1305
1306let ExeDomain = SSEPackedSingle in
1307defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1308 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1309
1310let ExeDomain = SSEPackedDouble in
1311defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1312 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1313
1314
1315// For the disassembler
1316let isCodeGenOnly = 1 in {
1317 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1318 (ins VR128X:$src1, FR32X:$src2),
1319 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1320 IIC_SSE_MOV_S_RR>,
1321 XS, EVEX_4V, VEX_LIG;
1322 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1323 (ins VR128X:$src1, FR64X:$src2),
1324 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1325 IIC_SSE_MOV_S_RR>,
1326 XD, EVEX_4V, VEX_LIG, VEX_W;
1327}
1328
1329let Predicates = [HasAVX512] in {
1330 let AddedComplexity = 15 in {
1331 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1332 // MOVS{S,D} to the lower bits.
1333 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1334 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1335 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1336 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1337 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1338 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1339 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1340 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1341
1342 // Move low f32 and clear high bits.
1343 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1344 (SUBREG_TO_REG (i32 0),
1345 (VMOVSSZrr (v4f32 (V_SET0)),
1346 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1347 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1348 (SUBREG_TO_REG (i32 0),
1349 (VMOVSSZrr (v4i32 (V_SET0)),
1350 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1351 }
1352
1353 let AddedComplexity = 20 in {
1354 // MOVSSrm zeros the high parts of the register; represent this
1355 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1356 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1357 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1358 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1359 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1360 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1361 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1362
1363 // MOVSDrm zeros the high parts of the register; represent this
1364 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1365 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1366 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1367 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1368 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1369 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1370 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1371 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1372 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1373 def : Pat<(v2f64 (X86vzload addr:$src)),
1374 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1375
1376 // Represent the same patterns above but in the form they appear for
1377 // 256-bit types
1378 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1379 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1380 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1381 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1382 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1383 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1384 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1385 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1386 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1387 }
1388 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1389 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1390 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1391 FR32X:$src)), sub_xmm)>;
1392 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1393 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1394 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1395 FR64X:$src)), sub_xmm)>;
1396 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1397 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1398 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1399
1400 // Move low f64 and clear high bits.
1401 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1402 (SUBREG_TO_REG (i32 0),
1403 (VMOVSDZrr (v2f64 (V_SET0)),
1404 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1405
1406 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1407 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1408 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1409
1410 // Extract and store.
1411 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1412 addr:$dst),
1413 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1414 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1415 addr:$dst),
1416 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1417
1418 // Shuffle with VMOVSS
1419 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1420 (VMOVSSZrr (v4i32 VR128X:$src1),
1421 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1422 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1423 (VMOVSSZrr (v4f32 VR128X:$src1),
1424 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1425
1426 // 256-bit variants
1427 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1428 (SUBREG_TO_REG (i32 0),
1429 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1430 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1431 sub_xmm)>;
1432 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1433 (SUBREG_TO_REG (i32 0),
1434 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1435 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1436 sub_xmm)>;
1437
1438 // Shuffle with VMOVSD
1439 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1440 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1441 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1442 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1443 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1444 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1445 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1446 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1447
1448 // 256-bit variants
1449 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1450 (SUBREG_TO_REG (i32 0),
1451 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1452 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1453 sub_xmm)>;
1454 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1455 (SUBREG_TO_REG (i32 0),
1456 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1457 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1458 sub_xmm)>;
1459
1460 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1461 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1462 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1463 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1464 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1465 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1466 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1467 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1468}
1469
1470let AddedComplexity = 15 in
1471def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1472 (ins VR128X:$src),
1473 "vmovq{z}\t{$src, $dst|$dst, $src}",
1474 [(set VR128X:$dst, (v2i64 (X86vzmovl
1475 (v2i64 VR128X:$src))))],
1476 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1477
1478let AddedComplexity = 20 in
1479def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1480 (ins i128mem:$src),
1481 "vmovq{z}\t{$src, $dst|$dst, $src}",
1482 [(set VR128X:$dst, (v2i64 (X86vzmovl
1483 (loadv2i64 addr:$src))))],
1484 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1485 EVEX_CD8<8, CD8VT8>;
1486
1487let Predicates = [HasAVX512] in {
1488 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1489 let AddedComplexity = 20 in {
1490 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1491 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1492 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1493 (VMOV64toPQIZrr GR64:$src)>;
1494 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1495 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1496
1497 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1498 (VMOVDI2PDIZrm addr:$src)>;
1499 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1500 (VMOVDI2PDIZrm addr:$src)>;
1501 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1502 (VMOVZPQILo2PQIZrm addr:$src)>;
1503 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1504 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1505 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1506
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1507 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1508 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1509 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1510 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1511 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1512 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1513 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1514}
1515
1516def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1517 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1518
1519def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1520 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1521
1522def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1523 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1524
1525def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1526 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1527
1528//===----------------------------------------------------------------------===//
1529// AVX-512 - Integer arithmetic
1530//
1531multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1532 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1533 X86MemOperand x86memop, PatFrag scalar_mfrag,
1534 X86MemOperand x86scalar_mop, string BrdcstStr,
1535 OpndItins itins, bit IsCommutable = 0> {
1536 let isCommutable = IsCommutable in
1537 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1538 (ins RC:$src1, RC:$src2),
1539 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1540 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1541 itins.rr>, EVEX_4V;
1542 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1543 (ins RC:$src1, x86memop:$src2),
1544 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1545 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1546 itins.rm>, EVEX_4V;
1547 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1548 (ins RC:$src1, x86scalar_mop:$src2),
1549 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1550 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1551 [(set RC:$dst, (OpNode RC:$src1,
1552 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1553 itins.rm>, EVEX_4V, EVEX_B;
1554}
1555multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1556 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1557 PatFrag memop_frag, X86MemOperand x86memop,
1558 OpndItins itins,
1559 bit IsCommutable = 0> {
1560 let isCommutable = IsCommutable in
1561 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1562 (ins RC:$src1, RC:$src2),
1563 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1564 []>, EVEX_4V, VEX_W;
1565 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1566 (ins RC:$src1, x86memop:$src2),
1567 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1568 []>, EVEX_4V, VEX_W;
1569}
1570
1571defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1572 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1573 EVEX_V512, EVEX_CD8<32, CD8VF>;
1574
1575defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1576 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1577 EVEX_V512, EVEX_CD8<32, CD8VF>;
1578
1579defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1580 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1581 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1582
1583defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1584 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1585 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1586
1587defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1588 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1589 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1590
1591defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1592 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1593 EVEX_V512, EVEX_CD8<64, CD8VF>;
1594
1595defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1596 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1597 EVEX_CD8<64, CD8VF>;
1598
1599def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1600 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1601
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame^]1602defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1603 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1604 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1605defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1606 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1607 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1608
1609defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1610 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1611 EVEX_V512, EVEX_CD8<32, CD8VF>;
1612defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1613 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1614 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1615
1616defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1617 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1618 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1619defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1620 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1621 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1622
1623defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1624 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1625 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1626defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1627 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1628 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1629
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1630//===----------------------------------------------------------------------===//
1631// AVX-512 - Unpack Instructions
1632//===----------------------------------------------------------------------===//
1633
1634multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1635 PatFrag mem_frag, RegisterClass RC,
1636 X86MemOperand x86memop, string asm,
1637 Domain d> {
1638 def rr : AVX512PI<opc, MRMSrcReg,
1639 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1640 asm, [(set RC:$dst,
1641 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1642 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1643 def rm : AVX512PI<opc, MRMSrcMem,
1644 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1645 asm, [(set RC:$dst,
1646 (vt (OpNode RC:$src1,
1647 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1648 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1649}
1650
1651defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1652 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1653 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1654defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1655 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1656 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1657defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1658 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1659 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1660defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1661 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1662 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1663
1664multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1665 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1666 X86MemOperand x86memop> {
1667 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1668 (ins RC:$src1, RC:$src2),
1669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1670 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1671 IIC_SSE_UNPCK>, EVEX_4V;
1672 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1673 (ins RC:$src1, x86memop:$src2),
1674 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1675 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1676 (bitconvert (memop_frag addr:$src2)))))],
1677 IIC_SSE_UNPCK>, EVEX_4V;
1678}
1679defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1680 VR512, memopv16i32, i512mem>, EVEX_V512,
1681 EVEX_CD8<32, CD8VF>;
1682defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1683 VR512, memopv8i64, i512mem>, EVEX_V512,
1684 VEX_W, EVEX_CD8<64, CD8VF>;
1685defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1686 VR512, memopv16i32, i512mem>, EVEX_V512,
1687 EVEX_CD8<32, CD8VF>;
1688defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1689 VR512, memopv8i64, i512mem>, EVEX_V512,
1690 VEX_W, EVEX_CD8<64, CD8VF>;
1691//===----------------------------------------------------------------------===//
1692// AVX-512 - PSHUFD
1693//
1694
1695multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1696 SDNode OpNode, PatFrag mem_frag,
1697 X86MemOperand x86memop, ValueType OpVT> {
1698 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1699 (ins RC:$src1, i8imm:$src2),
1700 !strconcat(OpcodeStr,
1701 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1702 [(set RC:$dst,
1703 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1704 EVEX;
1705 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1706 (ins x86memop:$src1, i8imm:$src2),
1707 !strconcat(OpcodeStr,
1708 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1709 [(set RC:$dst,
1710 (OpVT (OpNode (mem_frag addr:$src1),
1711 (i8 imm:$src2))))]>, EVEX;
1712}
1713
1714defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1715 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1716
1717let ExeDomain = SSEPackedSingle in
1718defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1719 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1720 EVEX_CD8<32, CD8VF>;
1721let ExeDomain = SSEPackedDouble in
1722defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1723 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1724 VEX_W, EVEX_CD8<32, CD8VF>;
1725
1726def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1727 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1728def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1729 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1730
1731//===----------------------------------------------------------------------===//
1732// AVX-512 Logical Instructions
1733//===----------------------------------------------------------------------===//
1734
1735defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1736 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1737 EVEX_V512, EVEX_CD8<32, CD8VF>;
1738defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1739 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1740 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1741defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1742 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1743 EVEX_V512, EVEX_CD8<32, CD8VF>;
1744defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1745 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1746 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1747defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1748 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1749 EVEX_V512, EVEX_CD8<32, CD8VF>;
1750defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1751 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1752 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1753defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1754 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1755 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1756defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1757 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1758 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1759
1760//===----------------------------------------------------------------------===//
1761// AVX-512 FP arithmetic
1762//===----------------------------------------------------------------------===//
1763
1764multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1765 SizeItins itins> {
1766 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1767 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1768 EVEX_CD8<32, CD8VT1>;
1769 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1770 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1771 EVEX_CD8<64, CD8VT1>;
1772}
1773
1774let isCommutable = 1 in {
1775defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1776defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1777defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1778defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1779}
1780let isCommutable = 0 in {
1781defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1782defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1783}
1784
1785multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1786 RegisterClass RC, ValueType vt,
1787 X86MemOperand x86memop, PatFrag mem_frag,
1788 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1789 string BrdcstStr,
1790 Domain d, OpndItins itins, bit commutable> {
1791 let isCommutable = commutable in
1792 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1793 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1794 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1795 EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1796 let mayLoad = 1 in {
1797 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1798 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1799 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1800 itins.rm, d>, EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1801 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1802 (ins RC:$src1, x86scalar_mop:$src2),
1803 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1804 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1805 [(set RC:$dst, (OpNode RC:$src1,
1806 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1807 itins.rm, d>, EVEX_4V, EVEX_B, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1808 }
1809}
1810
1811defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1812 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1813 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1814
1815defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1816 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1817 SSE_ALU_ITINS_P.d, 1>,
1818 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1819
1820defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1821 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1822 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1823defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1824 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1825 SSE_ALU_ITINS_P.d, 1>,
1826 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1827
1828defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1829 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1830 SSE_ALU_ITINS_P.s, 1>,
1831 EVEX_V512, EVEX_CD8<32, CD8VF>;
1832defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1833 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1834 SSE_ALU_ITINS_P.s, 1>,
1835 EVEX_V512, EVEX_CD8<32, CD8VF>;
1836
1837defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1838 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1839 SSE_ALU_ITINS_P.d, 1>,
1840 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1841defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1842 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1843 SSE_ALU_ITINS_P.d, 1>,
1844 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1845
1846defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1847 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1848 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1849defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1850 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1851 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1852
1853defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1854 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1855 SSE_ALU_ITINS_P.d, 0>,
1856 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1857defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1858 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1859 SSE_ALU_ITINS_P.d, 0>,
1860 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1861
1862//===----------------------------------------------------------------------===//
1863// AVX-512 VPTESTM instructions
1864//===----------------------------------------------------------------------===//
1865
1866multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1867 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1868 SDNode OpNode, ValueType vt> {
1869 def rr : AVX5128I<opc, MRMSrcReg,
1870 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1871 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1872 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1873 def rm : AVX5128I<opc, MRMSrcMem,
1874 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1875 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1876 [(set KRC:$dst, (OpNode (vt RC:$src1),
1877 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1878}
1879
1880defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1881 memopv16i32, X86testm, v16i32>, EVEX_V512,
1882 EVEX_CD8<32, CD8VF>;
1883defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1884 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1885 EVEX_CD8<64, CD8VF>;
1886
1887//===----------------------------------------------------------------------===//
1888// AVX-512 Shift instructions
1889//===----------------------------------------------------------------------===//
1890multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1891 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1892 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1893 RegisterClass KRC> {
1894 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1895 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1896 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1897 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1898 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1899 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1900 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1901 !strconcat(OpcodeStr,
1902 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1903 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1904 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1905 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1906 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1907 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1908 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1909 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1910 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1911 !strconcat(OpcodeStr,
1912 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1913 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1914}
1915
1916multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1917 RegisterClass RC, ValueType vt, ValueType SrcVT,
1918 PatFrag bc_frag, RegisterClass KRC> {
1919 // src2 is always 128-bit
1920 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1921 (ins RC:$src1, VR128X:$src2),
1922 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1923 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1924 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1925 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1926 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1927 !strconcat(OpcodeStr,
1928 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1929 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1930 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1931 (ins RC:$src1, i128mem:$src2),
1932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1933 [(set RC:$dst, (vt (OpNode RC:$src1,
1934 (bc_frag (memopv2i64 addr:$src2)))))],
1935 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1936 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1937 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1938 !strconcat(OpcodeStr,
1939 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1940 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1941}
1942
1943defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1944 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1945 EVEX_V512, EVEX_CD8<32, CD8VF>;
1946defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1947 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1948 EVEX_CD8<32, CD8VQ>;
1949
1950defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1951 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1952 EVEX_CD8<64, CD8VF>, VEX_W;
1953defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1954 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1955 EVEX_CD8<64, CD8VQ>, VEX_W;
1956
1957defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1958 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1959 EVEX_CD8<32, CD8VF>;
1960defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1961 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1962 EVEX_CD8<32, CD8VQ>;
1963
1964defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1965 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1966 EVEX_CD8<64, CD8VF>, VEX_W;
1967defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1968 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1969 EVEX_CD8<64, CD8VQ>, VEX_W;
1970
1971defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1972 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1973 EVEX_V512, EVEX_CD8<32, CD8VF>;
1974defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1975 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1976 EVEX_CD8<32, CD8VQ>;
1977
1978defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1979 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1980 EVEX_CD8<64, CD8VF>, VEX_W;
1981defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1982 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1983 EVEX_CD8<64, CD8VQ>, VEX_W;
1984
1985//===-------------------------------------------------------------------===//
1986// Variable Bit Shifts
1987//===-------------------------------------------------------------------===//
1988multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1989 RegisterClass RC, ValueType vt,
1990 X86MemOperand x86memop, PatFrag mem_frag> {
1991 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1992 (ins RC:$src1, RC:$src2),
1993 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1994 [(set RC:$dst,
1995 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1996 EVEX_4V;
1997 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1998 (ins RC:$src1, x86memop:$src2),
1999 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2000 [(set RC:$dst,
2001 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2002 EVEX_4V;
2003}
2004
2005defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2006 i512mem, memopv16i32>, EVEX_V512,
2007 EVEX_CD8<32, CD8VF>;
2008defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2009 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2010 EVEX_CD8<64, CD8VF>;
2011defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2012 i512mem, memopv16i32>, EVEX_V512,
2013 EVEX_CD8<32, CD8VF>;
2014defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2015 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2016 EVEX_CD8<64, CD8VF>;
2017defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2018 i512mem, memopv16i32>, EVEX_V512,
2019 EVEX_CD8<32, CD8VF>;
2020defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2021 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2022 EVEX_CD8<64, CD8VF>;
2023
2024//===----------------------------------------------------------------------===//
2025// AVX-512 - MOVDDUP
2026//===----------------------------------------------------------------------===//
2027
2028multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2029 X86MemOperand x86memop, PatFrag memop_frag> {
2030def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2031 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2032 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2033def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2034 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2035 [(set RC:$dst,
2036 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2037}
2038
2039defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2040 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2041def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2042 (VMOVDDUPZrm addr:$src)>;
2043
2044def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2045 (ins VR128X:$src1, VR128X:$src2),
2046 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2047 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2048 IIC_SSE_MOV_LH>, EVEX_4V;
2049def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2050 (ins VR128X:$src1, VR128X:$src2),
2051 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2052 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2053 IIC_SSE_MOV_LH>, EVEX_4V;
2054
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2055let Predicates = [HasAVX512] in {
2056 // MOVLHPS patterns
2057 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2058 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2059 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2060 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2061
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2062 // MOVHLPS patterns
2063 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2064 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2065}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2066
2067//===----------------------------------------------------------------------===//
2068// FMA - Fused Multiply Operations
2069//
2070let Constraints = "$src1 = $dst" in {
2071multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2072 RegisterClass RC, X86MemOperand x86memop,
2073 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2074 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2075 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2076 (ins RC:$src1, RC:$src2, RC:$src3),
2077 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2078 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2079
2080 let mayLoad = 1 in
2081 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2082 (ins RC:$src1, RC:$src2, x86memop:$src3),
2083 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2084 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2085 (mem_frag addr:$src3))))]>;
2086 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2087 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2088 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2089 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2090 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2091 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2092}
2093} // Constraints = "$src1 = $dst"
2094
2095let ExeDomain = SSEPackedSingle in {
2096 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2097 memopv16f32, f32mem, loadf32, "{1to16}",
2098 X86Fmadd, v16f32>, EVEX_V512,
2099 EVEX_CD8<32, CD8VF>;
2100 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2101 memopv16f32, f32mem, loadf32, "{1to16}",
2102 X86Fmsub, v16f32>, EVEX_V512,
2103 EVEX_CD8<32, CD8VF>;
2104 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2105 memopv16f32, f32mem, loadf32, "{1to16}",
2106 X86Fmaddsub, v16f32>,
2107 EVEX_V512, EVEX_CD8<32, CD8VF>;
2108 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2109 memopv16f32, f32mem, loadf32, "{1to16}",
2110 X86Fmsubadd, v16f32>,
2111 EVEX_V512, EVEX_CD8<32, CD8VF>;
2112 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2113 memopv16f32, f32mem, loadf32, "{1to16}",
2114 X86Fnmadd, v16f32>, EVEX_V512,
2115 EVEX_CD8<32, CD8VF>;
2116 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2117 memopv16f32, f32mem, loadf32, "{1to16}",
2118 X86Fnmsub, v16f32>, EVEX_V512,
2119 EVEX_CD8<32, CD8VF>;
2120}
2121let ExeDomain = SSEPackedDouble in {
2122 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2123 memopv8f64, f64mem, loadf64, "{1to8}",
2124 X86Fmadd, v8f64>, EVEX_V512,
2125 VEX_W, EVEX_CD8<64, CD8VF>;
2126 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2127 memopv8f64, f64mem, loadf64, "{1to8}",
2128 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2129 EVEX_CD8<64, CD8VF>;
2130 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2131 memopv8f64, f64mem, loadf64, "{1to8}",
2132 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2133 EVEX_CD8<64, CD8VF>;
2134 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2135 memopv8f64, f64mem, loadf64, "{1to8}",
2136 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2137 EVEX_CD8<64, CD8VF>;
2138 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2139 memopv8f64, f64mem, loadf64, "{1to8}",
2140 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2141 EVEX_CD8<64, CD8VF>;
2142 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2143 memopv8f64, f64mem, loadf64, "{1to8}",
2144 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2145 EVEX_CD8<64, CD8VF>;
2146}
2147
2148let Constraints = "$src1 = $dst" in {
2149multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2150 RegisterClass RC, X86MemOperand x86memop,
2151 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2152 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2153 let mayLoad = 1 in
2154 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2155 (ins RC:$src1, RC:$src3, x86memop:$src2),
2156 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2157 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2158 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2159 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2160 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2161 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2162 [(set RC:$dst, (OpNode RC:$src1,
2163 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2164}
2165} // Constraints = "$src1 = $dst"
2166
2167
2168let ExeDomain = SSEPackedSingle in {
2169 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2170 memopv16f32, f32mem, loadf32, "{1to16}",
2171 X86Fmadd, v16f32>, EVEX_V512,
2172 EVEX_CD8<32, CD8VF>;
2173 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2174 memopv16f32, f32mem, loadf32, "{1to16}",
2175 X86Fmsub, v16f32>, EVEX_V512,
2176 EVEX_CD8<32, CD8VF>;
2177 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2178 memopv16f32, f32mem, loadf32, "{1to16}",
2179 X86Fmaddsub, v16f32>,
2180 EVEX_V512, EVEX_CD8<32, CD8VF>;
2181 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2182 memopv16f32, f32mem, loadf32, "{1to16}",
2183 X86Fmsubadd, v16f32>,
2184 EVEX_V512, EVEX_CD8<32, CD8VF>;
2185 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2186 memopv16f32, f32mem, loadf32, "{1to16}",
2187 X86Fnmadd, v16f32>, EVEX_V512,
2188 EVEX_CD8<32, CD8VF>;
2189 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2190 memopv16f32, f32mem, loadf32, "{1to16}",
2191 X86Fnmsub, v16f32>, EVEX_V512,
2192 EVEX_CD8<32, CD8VF>;
2193}
2194let ExeDomain = SSEPackedDouble in {
2195 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2196 memopv8f64, f64mem, loadf64, "{1to8}",
2197 X86Fmadd, v8f64>, EVEX_V512,
2198 VEX_W, EVEX_CD8<64, CD8VF>;
2199 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2200 memopv8f64, f64mem, loadf64, "{1to8}",
2201 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2202 EVEX_CD8<64, CD8VF>;
2203 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2204 memopv8f64, f64mem, loadf64, "{1to8}",
2205 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2206 EVEX_CD8<64, CD8VF>;
2207 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2208 memopv8f64, f64mem, loadf64, "{1to8}",
2209 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2210 EVEX_CD8<64, CD8VF>;
2211 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2212 memopv8f64, f64mem, loadf64, "{1to8}",
2213 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2214 EVEX_CD8<64, CD8VF>;
2215 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2216 memopv8f64, f64mem, loadf64, "{1to8}",
2217 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2218 EVEX_CD8<64, CD8VF>;
2219}
2220
2221// Scalar FMA
2222let Constraints = "$src1 = $dst" in {
2223multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2224 RegisterClass RC, ValueType OpVT,
2225 X86MemOperand x86memop, Operand memop,
2226 PatFrag mem_frag> {
2227 let isCommutable = 1 in
2228 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2229 (ins RC:$src1, RC:$src2, RC:$src3),
2230 !strconcat(OpcodeStr,
2231 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2232 [(set RC:$dst,
2233 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2234 let mayLoad = 1 in
2235 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2236 (ins RC:$src1, RC:$src2, f128mem:$src3),
2237 !strconcat(OpcodeStr,
2238 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2239 [(set RC:$dst,
2240 (OpVT (OpNode RC:$src2, RC:$src1,
2241 (mem_frag addr:$src3))))]>;
2242}
2243
2244} // Constraints = "$src1 = $dst"
2245
2246defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2247 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2248defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2249 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2250defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2251 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2252defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2253 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2254defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2255 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2256defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2257 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2258defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2259 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2260defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2261 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2262
2263//===----------------------------------------------------------------------===//
2264// AVX-512 Scalar convert from sign integer to float/double
2265//===----------------------------------------------------------------------===//
2266
2267multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2268 X86MemOperand x86memop, string asm> {
2269let neverHasSideEffects = 1 in {
2270 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2271 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2272 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2273 let mayLoad = 1 in
2274 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2275 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2276 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2277 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2278} // neverHasSideEffects = 1
2279}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2280let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2281defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2282 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2283defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2284 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2285defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2286 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2287defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2288 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2289
2290def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2291 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2292def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2293 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2294def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2295 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2296def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2297 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2298
2299def : Pat<(f32 (sint_to_fp GR32:$src)),
2300 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2301def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2302 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2303def : Pat<(f64 (sint_to_fp GR32:$src)),
2304 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2305def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2306 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2307
2308defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2309 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2310defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2311 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2312defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2313 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2314defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2315 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2316
2317def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2318 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2319def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2320 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2321def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2322 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2323def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2324 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2325
2326def : Pat<(f32 (uint_to_fp GR32:$src)),
2327 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2328def : Pat<(f32 (uint_to_fp GR64:$src)),
2329 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2330def : Pat<(f64 (uint_to_fp GR32:$src)),
2331 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2332def : Pat<(f64 (uint_to_fp GR64:$src)),
2333 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2334}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2335
2336//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2337// AVX-512 Scalar convert from float/double to integer
2338//===----------------------------------------------------------------------===//
2339multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2340 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2341 string asm> {
2342let neverHasSideEffects = 1 in {
2343 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2344 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2345 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2346 let mayLoad = 1 in
2347 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2348 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2349} // neverHasSideEffects = 1
2350}
2351let Predicates = [HasAVX512] in {
2352// Convert float/double to signed/unsigned int 32/64
2353defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2354 ssmem, sse_load_f32, "cvtss2si{z}">,
2355 XS, EVEX_CD8<32, CD8VT1>;
2356defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2357 ssmem, sse_load_f32, "cvtss2si{z}">,
2358 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2359defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2360 ssmem, sse_load_f32, "cvtss2usi{z}">,
2361 XS, EVEX_CD8<32, CD8VT1>;
2362defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2363 int_x86_avx512_cvtss2usi64, ssmem,
2364 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2365 EVEX_CD8<32, CD8VT1>;
2366defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2367 sdmem, sse_load_f64, "cvtsd2si{z}">,
2368 XD, EVEX_CD8<64, CD8VT1>;
2369defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2370 sdmem, sse_load_f64, "cvtsd2si{z}">,
2371 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2372defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2373 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2374 XD, EVEX_CD8<64, CD8VT1>;
2375defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2376 int_x86_avx512_cvtsd2usi64, sdmem,
2377 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2378 EVEX_CD8<64, CD8VT1>;
2379
2380defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2381 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2382 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2383defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2384 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2385 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2386defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2387 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2388 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2389defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2390 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2391 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2392
2393defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2394 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2395 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2396defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2397 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2398 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2399defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2400 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2401 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2402defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2403 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2404 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2405
2406// Convert float/double to signed/unsigned int 32/64 with truncation
2407defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2408 ssmem, sse_load_f32, "cvttss2si{z}">,
2409 XS, EVEX_CD8<32, CD8VT1>;
2410defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2411 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2412 "cvttss2si{z}">, XS, VEX_W,
2413 EVEX_CD8<32, CD8VT1>;
2414defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2415 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2416 EVEX_CD8<64, CD8VT1>;
2417defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2418 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2419 "cvttsd2si{z}">, XD, VEX_W,
2420 EVEX_CD8<64, CD8VT1>;
2421defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2422 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2423 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2424defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2425 int_x86_avx512_cvttss2usi64, ssmem,
2426 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2427 EVEX_CD8<32, CD8VT1>;
2428defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2429 int_x86_avx512_cvttsd2usi,
2430 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2431 EVEX_CD8<64, CD8VT1>;
2432defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2433 int_x86_avx512_cvttsd2usi64, sdmem,
2434 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2435 EVEX_CD8<64, CD8VT1>;
2436}
2437
2438multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2439 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2440 string asm> {
2441 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2442 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2443 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2444 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2445 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2446 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2447}
2448
2449defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2450 loadf32, "cvttss2si{z}">, XS,
2451 EVEX_CD8<32, CD8VT1>;
2452defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2453 loadf32, "cvttss2usi{z}">, XS,
2454 EVEX_CD8<32, CD8VT1>;
2455defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2456 loadf32, "cvttss2si{z}">, XS, VEX_W,
2457 EVEX_CD8<32, CD8VT1>;
2458defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2459 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2460 EVEX_CD8<32, CD8VT1>;
2461defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2462 loadf64, "cvttsd2si{z}">, XD,
2463 EVEX_CD8<64, CD8VT1>;
2464defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2465 loadf64, "cvttsd2usi{z}">, XD,
2466 EVEX_CD8<64, CD8VT1>;
2467defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2468 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2469 EVEX_CD8<64, CD8VT1>;
2470defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2471 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2472 EVEX_CD8<64, CD8VT1>;
2473//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2474// AVX-512 Convert form float to double and back
2475//===----------------------------------------------------------------------===//
2476let neverHasSideEffects = 1 in {
2477def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2478 (ins FR32X:$src1, FR32X:$src2),
2479 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2480 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2481let mayLoad = 1 in
2482def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2483 (ins FR32X:$src1, f32mem:$src2),
2484 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2485 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2486 EVEX_CD8<32, CD8VT1>;
2487
2488// Convert scalar double to scalar single
2489def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2490 (ins FR64X:$src1, FR64X:$src2),
2491 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2492 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2493let mayLoad = 1 in
2494def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2495 (ins FR64X:$src1, f64mem:$src2),
2496 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2497 []>, EVEX_4V, VEX_LIG, VEX_W,
2498 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2499}
2500
2501def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2502 Requires<[HasAVX512]>;
2503def : Pat<(fextend (loadf32 addr:$src)),
2504 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2505
2506def : Pat<(extloadf32 addr:$src),
2507 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2508 Requires<[HasAVX512, OptForSize]>;
2509
2510def : Pat<(extloadf32 addr:$src),
2511 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2512 Requires<[HasAVX512, OptForSpeed]>;
2513
2514def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2515 Requires<[HasAVX512]>;
2516
2517multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2518 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2519 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2520 Domain d> {
2521let neverHasSideEffects = 1 in {
2522 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2523 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2524 [(set DstRC:$dst,
2525 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2526 let mayLoad = 1 in
2527 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2528 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2529 [(set DstRC:$dst,
2530 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2531} // neverHasSideEffects = 1
2532}
2533
2534defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2535 memopv8f64, f512mem, v8f32, v8f64,
2536 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2537 EVEX_CD8<64, CD8VF>;
2538
2539defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2540 memopv4f64, f256mem, v8f64, v8f32,
2541 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2542def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2543 (VCVTPS2PDZrm addr:$src)>;
2544
2545//===----------------------------------------------------------------------===//
2546// AVX-512 Vector convert from sign integer to float/double
2547//===----------------------------------------------------------------------===//
2548
2549defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2550 memopv8i64, i512mem, v16f32, v16i32,
2551 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2552
2553defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2554 memopv4i64, i256mem, v8f64, v8i32,
2555 SSEPackedDouble>, EVEX_V512, XS,
2556 EVEX_CD8<32, CD8VH>;
2557
2558defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2559 memopv16f32, f512mem, v16i32, v16f32,
2560 SSEPackedSingle>, EVEX_V512, XS,
2561 EVEX_CD8<32, CD8VF>;
2562
2563defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2564 memopv8f64, f512mem, v8i32, v8f64,
2565 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2566 EVEX_CD8<64, CD8VF>;
2567
2568defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2569 memopv16f32, f512mem, v16i32, v16f32,
2570 SSEPackedSingle>, EVEX_V512,
2571 EVEX_CD8<32, CD8VF>;
2572
2573defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2574 memopv8f64, f512mem, v8i32, v8f64,
2575 SSEPackedDouble>, EVEX_V512, VEX_W,
2576 EVEX_CD8<64, CD8VF>;
2577
2578defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2579 memopv4i64, f256mem, v8f64, v8i32,
2580 SSEPackedDouble>, EVEX_V512, XS,
2581 EVEX_CD8<32, CD8VH>;
2582
2583defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2584 memopv16i32, f512mem, v16f32, v16i32,
2585 SSEPackedSingle>, EVEX_V512, XD,
2586 EVEX_CD8<32, CD8VF>;
2587
2588def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2589 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2590 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2591
2592
2593def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2594 (VCVTDQ2PSZrr VR512:$src)>;
2595def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2596 (VCVTDQ2PSZrm addr:$src)>;
2597
2598def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2599 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2600 [(set VR512:$dst,
2601 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2602 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2603def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2604 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2605 [(set VR512:$dst,
2606 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2607 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2608
2609
2610let Predicates = [HasAVX512] in {
2611 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2612 (VCVTPD2PSZrm addr:$src)>;
2613 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2614 (VCVTPS2PDZrm addr:$src)>;
2615}
2616
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]2617//===----------------------------------------------------------------------===//
2618// Half precision conversion instructions
2619//===----------------------------------------------------------------------===//
2620multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2621 X86MemOperand x86memop, Intrinsic Int> {
2622 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2623 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2624 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2625 let neverHasSideEffects = 1, mayLoad = 1 in
2626 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2627 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2628}
2629
2630multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2631 X86MemOperand x86memop, Intrinsic Int> {
2632 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2633 (ins srcRC:$src1, i32i8imm:$src2),
2634 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2635 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2636 let neverHasSideEffects = 1, mayStore = 1 in
2637 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2638 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2639 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2640}
2641
2642defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2643 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2644 EVEX_CD8<32, CD8VH>;
2645defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2646 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2647 EVEX_CD8<32, CD8VH>;
2648
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2649let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2650 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2651 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2652 EVEX_CD8<32, CD8VT1>;
2653 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2654 "ucomisd{z}">, TB, OpSize, EVEX,
2655 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2656 let Pattern = []<dag> in {
2657 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2658 "comiss{z}">, TB, EVEX, VEX_LIG,
2659 EVEX_CD8<32, CD8VT1>;
2660 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2661 "comisd{z}">, TB, OpSize, EVEX,
2662 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2663 }
2664 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2665 load, "ucomiss">, TB, EVEX, VEX_LIG,
2666 EVEX_CD8<32, CD8VT1>;
2667 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2668 load, "ucomisd">, TB, OpSize, EVEX,
2669 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2670
2671 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2672 load, "comiss">, TB, EVEX, VEX_LIG,
2673 EVEX_CD8<32, CD8VT1>;
2674 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2675 load, "comisd">, TB, OpSize, EVEX,
2676 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2677}
2678
2679/// avx512_unop_p - AVX-512 unops in packed form.
2680multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2681 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2682 !strconcat(OpcodeStr,
2683 "ps\t{$src, $dst|$dst, $src}"),
2684 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2685 EVEX, EVEX_V512;
2686 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2687 !strconcat(OpcodeStr,
2688 "ps\t{$src, $dst|$dst, $src}"),
2689 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2690 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2691 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2692 !strconcat(OpcodeStr,
2693 "pd\t{$src, $dst|$dst, $src}"),
2694 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2695 EVEX, EVEX_V512, VEX_W;
2696 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2697 !strconcat(OpcodeStr,
2698 "pd\t{$src, $dst|$dst, $src}"),
2699 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2700 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2701}
2702
2703/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2704multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2705 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2706 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2707 !strconcat(OpcodeStr,
2708 "ps\t{$src, $dst|$dst, $src}"),
2709 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2710 EVEX, EVEX_V512;
2711 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2712 !strconcat(OpcodeStr,
2713 "ps\t{$src, $dst|$dst, $src}"),
2714 [(set VR512:$dst,
2715 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2716 EVEX_V512, EVEX_CD8<32, CD8VF>;
2717 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2718 !strconcat(OpcodeStr,
2719 "pd\t{$src, $dst|$dst, $src}"),
2720 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2721 EVEX, EVEX_V512, VEX_W;
2722 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2723 !strconcat(OpcodeStr,
2724 "pd\t{$src, $dst|$dst, $src}"),
2725 [(set VR512:$dst,
2726 (V8F64Int (memopv8f64 addr:$src)))]>,
2727 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2728}
2729
2730/// avx512_fp_unop_s - AVX-512 unops in scalar form.
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2731multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2732 let hasSideEffects = 0 in {
2733 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2734 (ins FR32X:$src1, FR32X:$src2),
2735 !strconcat(OpcodeStr,
2736 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2737 []>, EVEX_4V;
2738 let mayLoad = 1 in {
2739 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2740 (ins FR32X:$src1, f32mem:$src2),
2741 !strconcat(OpcodeStr,
2742 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2743 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2744 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2745 (ins VR128X:$src1, ssmem:$src2),
2746 !strconcat(OpcodeStr,
2747 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2748 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2749 }
2750 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2751 (ins FR64X:$src1, FR64X:$src2),
2752 !strconcat(OpcodeStr,
2753 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2754 EVEX_4V, VEX_W;
2755 let mayLoad = 1 in {
2756 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2757 (ins FR64X:$src1, f64mem:$src2),
2758 !strconcat(OpcodeStr,
2759 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2760 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2761 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2762 (ins VR128X:$src1, sdmem:$src2),
2763 !strconcat(OpcodeStr,
2764 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2765 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2766 }
2767}
2768}
2769
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2770defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2771 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2772 avx512_fp_unop_p_int<0x4C, "vrcp14",
2773 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2774
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2775defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2776 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2777 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2778 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2779
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2780def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2781 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2782 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2783 VR128X)>;
2784def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2785 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2786
2787def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2788 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2789 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2790 VR128X)>;
2791def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2792 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2793
2794let AddedComplexity = 20, Predicates = [HasERI] in {
2795defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2796 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2797 avx512_fp_unop_p_int<0xCA, "vrcp28",
2798 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2799
2800defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2801 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2802 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2803 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2804}
2805
2806let Predicates = [HasERI] in {
2807 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2808 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2809 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2810 VR128X)>;
2811 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2812 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2813
2814 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2815 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2816 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2817 VR128X)>;
2818 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2819 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2820}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2821multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2822 Intrinsic V16F32Int, Intrinsic V8F64Int,
2823 OpndItins itins_s, OpndItins itins_d> {
2824 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2825 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2826 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2827 EVEX, EVEX_V512;
2828
2829 let mayLoad = 1 in
2830 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2831 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2832 [(set VR512:$dst,
2833 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2834 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2835
2836 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2837 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2838 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2839 EVEX, EVEX_V512;
2840
2841 let mayLoad = 1 in
2842 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2844 [(set VR512:$dst, (OpNode
2845 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2846 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2847
2848 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2849 !strconcat(OpcodeStr,
2850 "ps\t{$src, $dst|$dst, $src}"),
2851 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2852 EVEX, EVEX_V512;
2853 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2854 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2855 [(set VR512:$dst,
2856 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2857 EVEX_V512, EVEX_CD8<32, CD8VF>;
2858 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2859 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2860 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2861 EVEX, EVEX_V512, VEX_W;
2862 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2863 !strconcat(OpcodeStr,
2864 "pd\t{$src, $dst|$dst, $src}"),
2865 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2866 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2867}
2868
2869multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2870 Intrinsic F32Int, Intrinsic F64Int,
2871 OpndItins itins_s, OpndItins itins_d> {
2872 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2873 (ins FR32X:$src1, FR32X:$src2),
2874 !strconcat(OpcodeStr,
2875 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2876 [], itins_s.rr>, XS, EVEX_4V;
2877 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2878 (ins VR128X:$src1, VR128X:$src2),
2879 !strconcat(OpcodeStr,
2880 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2881 [(set VR128X:$dst,
2882 (F32Int VR128X:$src1, VR128X:$src2))],
2883 itins_s.rr>, XS, EVEX_4V;
2884 let mayLoad = 1 in {
2885 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2886 (ins FR32X:$src1, f32mem:$src2),
2887 !strconcat(OpcodeStr,
2888 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2889 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2890 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2891 (ins VR128X:$src1, ssmem:$src2),
2892 !strconcat(OpcodeStr,
2893 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2894 [(set VR128X:$dst,
2895 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2896 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2897 }
2898 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2899 (ins FR64X:$src1, FR64X:$src2),
2900 !strconcat(OpcodeStr,
2901 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2902 XD, EVEX_4V, VEX_W;
2903 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2904 (ins VR128X:$src1, VR128X:$src2),
2905 !strconcat(OpcodeStr,
2906 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2907 [(set VR128X:$dst,
2908 (F64Int VR128X:$src1, VR128X:$src2))],
2909 itins_s.rr>, XD, EVEX_4V, VEX_W;
2910 let mayLoad = 1 in {
2911 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2912 (ins FR64X:$src1, f64mem:$src2),
2913 !strconcat(OpcodeStr,
2914 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2915 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2916 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2917 (ins VR128X:$src1, sdmem:$src2),
2918 !strconcat(OpcodeStr,
2919 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2920 [(set VR128X:$dst,
2921 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2922 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2923 }
2924}
2925
2926
2927defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2928 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2929 SSE_SQRTSS, SSE_SQRTSD>,
2930 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2931 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2932 SSE_SQRTPS, SSE_SQRTPD>;
2933
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2934let Predicates = [HasAVX512] in {
2935 def : Pat<(f32 (fsqrt FR32X:$src)),
2936 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2937 def : Pat<(f32 (fsqrt (load addr:$src))),
2938 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2939 Requires<[OptForSize]>;
2940 def : Pat<(f64 (fsqrt FR64X:$src)),
2941 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2942 def : Pat<(f64 (fsqrt (load addr:$src))),
2943 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2944 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2945
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2946 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2947 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2948 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2949 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2950 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2951
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2952 def : Pat<(f32 (X86frcp FR32X:$src)),
2953 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2954 def : Pat<(f32 (X86frcp (load addr:$src))),
2955 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2956 Requires<[OptForSize]>;
2957
2958 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
2959 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
2960 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2961 VR128X)>;
2962 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2963 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2964
2965 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
2966 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
2967 (COPY_TO_REGCLASS VR128X:$src, FR64)),
2968 VR128X)>;
2969 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2970 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2971}
2972
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2973
2974multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2975 X86MemOperand x86memop, RegisterClass RC,
2976 PatFrag mem_frag32, PatFrag mem_frag64,
2977 Intrinsic V4F32Int, Intrinsic V2F64Int,
2978 CD8VForm VForm> {
2979let ExeDomain = SSEPackedSingle in {
2980 // Intrinsic operation, reg.
2981 // Vector intrinsic operation, reg
2982 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2983 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2984 !strconcat(OpcodeStr,
2985 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2986 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2987
2988 // Vector intrinsic operation, mem
2989 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2990 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2991 !strconcat(OpcodeStr,
2992 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2993 [(set RC:$dst,
2994 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2995 EVEX_CD8<32, VForm>;
2996} // ExeDomain = SSEPackedSingle
2997
2998let ExeDomain = SSEPackedDouble in {
2999 // Vector intrinsic operation, reg
3000 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3001 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3002 !strconcat(OpcodeStr,
3003 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3004 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3005
3006 // Vector intrinsic operation, mem
3007 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3008 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3009 !strconcat(OpcodeStr,
3010 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3011 [(set RC:$dst,
3012 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3013 EVEX_CD8<64, VForm>;
3014} // ExeDomain = SSEPackedDouble
3015}
3016
3017multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3018 string OpcodeStr,
3019 Intrinsic F32Int,
3020 Intrinsic F64Int> {
3021let ExeDomain = GenericDomain in {
3022 // Operation, reg.
3023 let hasSideEffects = 0 in
3024 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3025 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3026 !strconcat(OpcodeStr,
3027 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3028 []>;
3029
3030 // Intrinsic operation, reg.
3031 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3032 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3033 !strconcat(OpcodeStr,
3034 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3035 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3036
3037 // Intrinsic operation, mem.
3038 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3039 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3040 !strconcat(OpcodeStr,
3041 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3042 [(set VR128X:$dst, (F32Int VR128X:$src1,
3043 sse_load_f32:$src2, imm:$src3))]>,
3044 EVEX_CD8<32, CD8VT1>;
3045
3046 // Operation, reg.
3047 let hasSideEffects = 0 in
3048 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3049 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3050 !strconcat(OpcodeStr,
3051 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3052 []>, VEX_W;
3053
3054 // Intrinsic operation, reg.
3055 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3056 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3057 !strconcat(OpcodeStr,
3058 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3059 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3060 VEX_W;
3061
3062 // Intrinsic operation, mem.
3063 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3064 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3065 !strconcat(OpcodeStr,
3066 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3067 [(set VR128X:$dst,
3068 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3069 VEX_W, EVEX_CD8<64, CD8VT1>;
3070} // ExeDomain = GenericDomain
3071}
3072
3073let Predicates = [HasAVX512] in {
3074 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3075 int_x86_avx512_rndscale_ss,
3076 int_x86_avx512_rndscale_sd>, EVEX_4V;
3077
3078 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3079 memopv16f32, memopv8f64,
3080 int_x86_avx512_rndscale_ps_512,
3081 int_x86_avx512_rndscale_pd_512, CD8VF>,
3082 EVEX, EVEX_V512;
3083}
3084
3085def : Pat<(ffloor FR32X:$src),
3086 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3087def : Pat<(f64 (ffloor FR64X:$src)),
3088 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3089def : Pat<(f32 (fnearbyint FR32X:$src)),
3090 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3091def : Pat<(f64 (fnearbyint FR64X:$src)),
3092 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3093def : Pat<(f32 (fceil FR32X:$src)),
3094 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3095def : Pat<(f64 (fceil FR64X:$src)),
3096 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3097def : Pat<(f32 (frint FR32X:$src)),
3098 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3099def : Pat<(f64 (frint FR64X:$src)),
3100 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3101def : Pat<(f32 (ftrunc FR32X:$src)),
3102 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3103def : Pat<(f64 (ftrunc FR64X:$src)),
3104 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3105
3106def : Pat<(v16f32 (ffloor VR512:$src)),
3107 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3108def : Pat<(v16f32 (fnearbyint VR512:$src)),
3109 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3110def : Pat<(v16f32 (fceil VR512:$src)),
3111 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3112def : Pat<(v16f32 (frint VR512:$src)),
3113 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3114def : Pat<(v16f32 (ftrunc VR512:$src)),
3115 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3116
3117def : Pat<(v8f64 (ffloor VR512:$src)),
3118 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3119def : Pat<(v8f64 (fnearbyint VR512:$src)),
3120 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3121def : Pat<(v8f64 (fceil VR512:$src)),
3122 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3123def : Pat<(v8f64 (frint VR512:$src)),
3124 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3125def : Pat<(v8f64 (ftrunc VR512:$src)),
3126 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3127
3128//-------------------------------------------------
3129// Integer truncate and extend operations
3130//-------------------------------------------------
3131
3132multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3133 RegisterClass dstRC, RegisterClass srcRC,
3134 RegisterClass KRC, X86MemOperand x86memop> {
3135 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3136 (ins srcRC:$src),
3137 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3138 []>, EVEX;
3139
3140 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3141 (ins KRC:$mask, srcRC:$src),
3142 !strconcat(OpcodeStr,
3143 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3144 []>, EVEX, EVEX_KZ;
3145
3146 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3147 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3148 []>, EVEX;
3149}
3150defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3151 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3152defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3153 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3154defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3155 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3156defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3157 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3158defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3159 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3160defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3161 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3162defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3163 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3164defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3165 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3166defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3167 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3168defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3169 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3170defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3171 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3172defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3173 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3174defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3175 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3176defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3177 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3178defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3179 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3180
3181def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3182def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3183def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3184def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3185def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3186
3187def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3188 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3189def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3190 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3191def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3192 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3193def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3194 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3195
3196
3197multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3198 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3199 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3200
3201 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3202 (ins SrcRC:$src),
3203 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3204 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3205 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3206 (ins x86memop:$src),
3207 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3208 [(set DstRC:$dst,
3209 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3210 EVEX;
3211}
3212
3213defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3214 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3215 EVEX_CD8<8, CD8VQ>;
3216defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3217 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3218 EVEX_CD8<8, CD8VO>;
3219defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3220 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3221 EVEX_CD8<16, CD8VH>;
3222defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3223 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3224 EVEX_CD8<16, CD8VQ>;
3225defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3226 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3227 EVEX_CD8<32, CD8VH>;
3228
3229defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3230 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3231 EVEX_CD8<8, CD8VQ>;
3232defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3233 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3234 EVEX_CD8<8, CD8VO>;
3235defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3236 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3237 EVEX_CD8<16, CD8VH>;
3238defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3239 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3240 EVEX_CD8<16, CD8VQ>;
3241defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3242 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3243 EVEX_CD8<32, CD8VH>;
3244
3245//===----------------------------------------------------------------------===//
3246// GATHER - SCATTER Operations
3247
3248multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3249 RegisterClass RC, X86MemOperand memop> {
3250let mayLoad = 1,
3251 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3252 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3253 (ins RC:$src1, KRC:$mask, memop:$src2),
3254 !strconcat(OpcodeStr,
3255 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3256 []>, EVEX, EVEX_K;
3257}
3258defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3259 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3260defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3261 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3262
3263defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3264 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3265defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3266 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3267
3268defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3269 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3270defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3271 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3272
3273defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3274 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3275defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3276 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3277
3278multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3279 RegisterClass RC, X86MemOperand memop> {
3280let mayStore = 1, Constraints = "$mask = $mask_wb" in
3281 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3282 (ins memop:$dst, KRC:$mask, RC:$src2),
3283 !strconcat(OpcodeStr,
3284 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3285 []>, EVEX, EVEX_K;
3286}
3287
3288defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3289 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3290defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3291 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3292
3293defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3294 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3295defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3296 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3297
3298defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3299 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3300defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3301 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3302
3303defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3304 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3305defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3306 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3307
3308//===----------------------------------------------------------------------===//
3309// VSHUFPS - VSHUFPD Operations
3310
3311multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3312 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3313 Domain d> {
3314 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3315 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3316 !strconcat(OpcodeStr,
3317 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3318 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3319 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3320 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3321 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3322 (ins RC:$src1, RC:$src2, i8imm:$src3),
3323 !strconcat(OpcodeStr,
3324 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3325 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3326 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3327 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3328}
3329
3330defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3331 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3332defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3333 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3334
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]3335def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3336 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3337def : Pat<(v16i32 (X86Shufp VR512:$src1,
3338 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3339 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3340
3341def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3342 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3343def : Pat<(v8i64 (X86Shufp VR512:$src1,
3344 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3345 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3346
3347multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3348 X86MemOperand x86memop> {
3349 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3350 (ins RC:$src1, RC:$src2, i8imm:$src3),
3351 !strconcat(OpcodeStr,
3352 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3353 []>, EVEX_4V;
3354 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3355 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3356 !strconcat(OpcodeStr,
3357 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3358 []>, EVEX_4V;
3359}
3360defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3361 EVEX_V512, EVEX_CD8<32, CD8VF>;
3362defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3363 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3364
3365def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3366 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3367def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3368 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3369def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3370 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3371def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3372 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3373
3374multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3375 X86MemOperand x86memop> {
3376 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3377 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3378 EVEX;
3379 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3380 (ins x86memop:$src),
3381 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3382 EVEX;
3383}
3384
3385defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3386 EVEX_CD8<32, CD8VF>;
3387defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3388 EVEX_CD8<64, CD8VF>;
3389