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Tom Stellardcb97e3a2013-04-15 17:51:35 +00001//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
Tom Stellardb6550522015-01-12 19:33:18 +000011#include "llvm/MC/MCInstrDesc.h"
12
Matt Arsenault6b6a2c32016-03-11 08:00:27 +000013#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
Tom Stellardcb97e3a2013-04-15 17:51:35 +000015
Tom Stellard16a9a202013-08-14 23:24:17 +000016namespace SIInstrFlags {
Matt Arsenaulte2fabd32014-07-29 18:51:56 +000017// This needs to be kept in sync with the field bits in InstSI.
Tom Stellard16a9a202013-08-14 23:24:17 +000018enum {
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000019 SALU = 1 << 3,
20 VALU = 1 << 4,
21
22 SOP1 = 1 << 5,
23 SOP2 = 1 << 6,
24 SOPC = 1 << 7,
25 SOPK = 1 << 8,
26 SOPP = 1 << 9,
27
28 VOP1 = 1 << 10,
29 VOP2 = 1 << 11,
30 VOP3 = 1 << 12,
31 VOPC = 1 << 13,
Sam Kolton3025e7f2016-04-26 13:33:56 +000032 SDWA = 1 << 14,
33 DPP = 1 << 15,
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000034
Sam Kolton3025e7f2016-04-26 13:33:56 +000035 MUBUF = 1 << 16,
36 MTBUF = 1 << 17,
37 SMRD = 1 << 18,
38 DS = 1 << 19,
39 MIMG = 1 << 20,
40 FLAT = 1 << 21,
41 WQM = 1 << 22,
42 VGPRSpill = 1 << 23,
Matt Arsenault3354f422016-09-10 01:20:33 +000043 SGPRSpill = 1 << 24,
44 VOPAsmPrefer32Bit = 1 << 25,
45 Gather4 = 1 << 26,
Matt Arsenault7ccf6cd2016-09-16 21:41:16 +000046 DisableWQM = 1 << 27,
47 SOPK_ZEXT = 1 << 28
Tom Stellard16a9a202013-08-14 23:24:17 +000048};
Alexander Kornienkof00654e2015-06-23 09:49:53 +000049}
Tom Stellard16a9a202013-08-14 23:24:17 +000050
Tom Stellardb6550522015-01-12 19:33:18 +000051namespace llvm {
52namespace AMDGPU {
53 enum OperandType {
Sam Kolton1eeb11b2016-09-09 14:44:04 +000054 /// Operands with register or 32-bit immediate
55 OPERAND_REG_IMM32_INT = MCOI::OPERAND_FIRST_TARGET,
56 OPERAND_REG_IMM32_FP,
57 /// Operands with register or inline constant
58 OPERAND_REG_INLINE_C_INT,
59 OPERAND_REG_INLINE_C_FP,
Matt Arsenaultffc82752016-07-05 17:09:01 +000060
Sam Kolton1eeb11b2016-09-09 14:44:04 +000061 // Operand for source modifiers for VOP instructions
62 OPERAND_INPUT_MODS,
63
64 /// Operand with 32-bit immediate that uses the constant bus.
Matt Arsenaultffc82752016-07-05 17:09:01 +000065 OPERAND_KIMM32
Tom Stellardb6550522015-01-12 19:33:18 +000066 };
67}
68}
69
Matt Arsenault9783e002014-09-29 15:50:26 +000070namespace SIInstrFlags {
71 enum Flags {
72 // First 4 bits are the instruction encoding
73 VM_CNT = 1 << 0,
74 EXP_CNT = 1 << 1,
75 LGKM_CNT = 1 << 2
76 };
Matt Arsenault4831ce52015-01-06 23:00:37 +000077
78 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
79 // The result is true if any of these tests are true.
80 enum ClassFlags {
81 S_NAN = 1 << 0, // Signaling NaN
82 Q_NAN = 1 << 1, // Quiet NaN
83 N_INFINITY = 1 << 2, // Negative infinity
84 N_NORMAL = 1 << 3, // Negative normal
85 N_SUBNORMAL = 1 << 4, // Negative subnormal
86 N_ZERO = 1 << 5, // Negative zero
87 P_ZERO = 1 << 6, // Positive zero
88 P_SUBNORMAL = 1 << 7, // Positive subnormal
89 P_NORMAL = 1 << 8, // Positive normal
90 P_INFINITY = 1 << 9 // Positive infinity
91 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +000092}
Matt Arsenault9783e002014-09-29 15:50:26 +000093
Sam Kolton945231a2016-06-10 09:57:59 +000094// Input operand modifiers bit-masks
95// NEG and SEXT share same bit-mask because they can't be set simultaneously.
Matt Arsenault9783e002014-09-29 15:50:26 +000096namespace SISrcMods {
97 enum {
Sam Kolton945231a2016-06-10 09:57:59 +000098 NEG = 1 << 0, // Floating-point negate modifier
99 ABS = 1 << 1, // Floating-point absolute modifier
100 SEXT = 1 << 0 // Integer sign-extend modifier
Matt Arsenault9783e002014-09-29 15:50:26 +0000101 };
102}
103
Matt Arsenault97069782014-09-30 19:49:48 +0000104namespace SIOutMods {
105 enum {
106 NONE = 0,
107 MUL2 = 1,
108 MUL4 = 2,
109 DIV2 = 3
110 };
111}
112
Sam Koltond63d8a72016-09-09 09:37:51 +0000113namespace AMDGPUAsmVariants {
114 enum {
115 DEFAULT = 0,
116 VOP3 = 1,
117 SDWA = 2,
118 DPP = 3
119 };
120}
121
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000122namespace llvm {
123namespace AMDGPU {
Artem Tamazov212a2512016-05-24 12:05:16 +0000124namespace EncValues { // Encoding values of enum9/8/7 operands
125
126enum {
127 SGPR_MIN = 0,
128 SGPR_MAX = 101,
129 TTMP_MIN = 112,
130 TTMP_MAX = 123,
131 INLINE_INTEGER_C_MIN = 128,
132 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
133 INLINE_INTEGER_C_MAX = 208,
134 INLINE_FLOATING_C_MIN = 240,
135 INLINE_FLOATING_C_MAX = 248,
136 LITERAL_CONST = 255,
137 VGPR_MIN = 256,
138 VGPR_MAX = 511
139};
140
141} // namespace EncValues
142} // namespace AMDGPU
143} // namespace llvm
144
145namespace llvm {
146namespace AMDGPU {
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000147namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
148
Artem Tamazov6edc1352016-05-26 17:00:33 +0000149enum Id { // Message ID, width(4) [3:0].
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000150 ID_UNKNOWN_ = -1,
151 ID_INTERRUPT = 1,
152 ID_GS,
153 ID_GS_DONE,
154 ID_SYSMSG = 15,
155 ID_GAPS_LAST_, // Indicate that sequence has gaps.
156 ID_GAPS_FIRST_ = ID_INTERRUPT,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000157 ID_SHIFT_ = 0,
158 ID_WIDTH_ = 4,
159 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000160};
161
162enum Op { // Both GS and SYS operation IDs.
163 OP_UNKNOWN_ = -1,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000164 OP_SHIFT_ = 4,
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000165 // width(2) [5:4]
166 OP_GS_NOP = 0,
167 OP_GS_CUT,
168 OP_GS_EMIT,
169 OP_GS_EMIT_CUT,
170 OP_GS_LAST_,
171 OP_GS_FIRST_ = OP_GS_NOP,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000172 OP_GS_WIDTH_ = 2,
173 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000174 // width(3) [6:4]
175 OP_SYS_ECC_ERR_INTERRUPT = 1,
176 OP_SYS_REG_RD,
177 OP_SYS_HOST_TRAP_ACK,
178 OP_SYS_TTRACE_PC,
179 OP_SYS_LAST_,
180 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000181 OP_SYS_WIDTH_ = 3,
182 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000183};
184
185enum StreamId { // Stream ID, (2) [9:8].
Artem Tamazov6edc1352016-05-26 17:00:33 +0000186 STREAM_ID_DEFAULT_ = 0,
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000187 STREAM_ID_LAST_ = 4,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000188 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
189 STREAM_ID_SHIFT_ = 8,
190 STREAM_ID_WIDTH_= 2,
191 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000192};
193
194} // namespace SendMsg
Artem Tamazov6edc1352016-05-26 17:00:33 +0000195
196namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
197
198enum Id { // HwRegCode, (6) [5:0]
199 ID_UNKNOWN_ = -1,
200 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
201 ID_SYMBOLIC_LAST_ = 8,
202 ID_SHIFT_ = 0,
203 ID_WIDTH_ = 6,
204 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
205};
206
207enum Offset { // Offset, (5) [10:6]
208 OFFSET_DEFAULT_ = 0,
209 OFFSET_SHIFT_ = 6,
210 OFFSET_WIDTH_ = 5,
211 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_)
212};
213
214enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
215 WIDTH_M1_DEFAULT_ = 31,
216 WIDTH_M1_SHIFT_ = 11,
217 WIDTH_M1_WIDTH_ = 5,
218 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_)
219};
220
221} // namespace Hwreg
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000222} // namespace AMDGPU
223} // namespace llvm
224
Tom Stellardcb97e3a2013-04-15 17:51:35 +0000225#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
Michel Danzer49812b52013-07-10 16:37:07 +0000226#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
227#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
Tom Stellardcb97e3a2013-04-15 17:51:35 +0000228#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
229#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
230#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
231#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
232#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
Tom Stellardff7416b2015-06-26 21:58:31 +0000233
Michel Danzer49812b52013-07-10 16:37:07 +0000234#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
Tom Stellard4df465b2014-12-02 21:28:53 +0000235#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
Tom Stellardff7416b2015-06-26 21:58:31 +0000236#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
237#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
Tom Stellard4df465b2014-12-02 21:28:53 +0000238#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
Tom Stellardff7416b2015-06-26 21:58:31 +0000239#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
240#define C_00B84C_USER_SGPR 0xFFFFFFC1
Tom Stellard4df465b2014-12-02 21:28:53 +0000241#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
Tom Stellardff7416b2015-06-26 21:58:31 +0000242#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
243#define C_00B84C_TGID_X_EN 0xFFFFFF7F
Tom Stellard4df465b2014-12-02 21:28:53 +0000244#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
Tom Stellardff7416b2015-06-26 21:58:31 +0000245#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
246#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
Tom Stellard4df465b2014-12-02 21:28:53 +0000247#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
Tom Stellardff7416b2015-06-26 21:58:31 +0000248#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
249#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
Tom Stellard4df465b2014-12-02 21:28:53 +0000250#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
Tom Stellardff7416b2015-06-26 21:58:31 +0000251#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
252#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
Tom Stellard4df465b2014-12-02 21:28:53 +0000253#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
Tom Stellardff7416b2015-06-26 21:58:31 +0000254#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
255#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
256/* CIK */
257#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
258#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
259#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
260/* */
Michel Danzer49812b52013-07-10 16:37:07 +0000261#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
Tom Stellardff7416b2015-06-26 21:58:31 +0000262#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
263#define C_00B84C_LDS_SIZE 0xFF007FFF
264#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
265#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
Matt Arsenault37fefd62016-06-10 02:18:02 +0000266#define C_00B84C_EXCP_EN
Tom Stellardff7416b2015-06-26 21:58:31 +0000267
Tom Stellardcb97e3a2013-04-15 17:51:35 +0000268#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
Marek Olsakfccabaf2016-01-13 11:45:36 +0000269#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
Matt Arsenault0989d512014-06-26 17:22:30 +0000270
271#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
272#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
273#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
274#define C_00B848_VGPRS 0xFFFFFFC0
275#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
276#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
277#define C_00B848_SGPRS 0xFFFFFC3F
278#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
279#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
280#define C_00B848_PRIORITY 0xFFFFF3FF
281#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
282#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
283#define C_00B848_FLOAT_MODE 0xFFF00FFF
284#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
285#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
286#define C_00B848_PRIV 0xFFEFFFFF
287#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
288#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
289#define C_00B848_DX10_CLAMP 0xFFDFFFFF
290#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
291#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
292#define C_00B848_DEBUG_MODE 0xFFBFFFFF
293#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
294#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
295#define C_00B848_IEEE_MODE 0xFF7FFFFF
296
297
298// Helpers for setting FLOAT_MODE
299#define FP_ROUND_ROUND_TO_NEAREST 0
300#define FP_ROUND_ROUND_TO_INF 1
301#define FP_ROUND_ROUND_TO_NEGINF 2
302#define FP_ROUND_ROUND_TO_ZERO 3
303
304// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
305// precision.
306#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
307#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
308
309#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
310#define FP_DENORM_FLUSH_OUT 1
311#define FP_DENORM_FLUSH_IN 2
312#define FP_DENORM_FLUSH_NONE 3
313
314
315// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
316// precision.
317#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
318#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
319
Tom Stellardb02094e2014-07-21 15:45:01 +0000320#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
321#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
322
Tom Stellarde99fb652015-01-20 19:33:04 +0000323#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
324#define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
325
Marek Olsak0532c192016-07-13 17:35:15 +0000326#define R_SPILLED_SGPRS 0x4
327#define R_SPILLED_VGPRS 0x8
Tom Stellard95292bb2015-01-20 17:49:47 +0000328
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000329#endif