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gerrit-public.fairphone.software / toolchain / llvm-project / 15ee408a91abb9b53f532672e9fc7c0864cfdf3a / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
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Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]22#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]23#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]25#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]26#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]27#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]28#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]29#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]31#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]32#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]33#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]34#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]35#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]38#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]39#include <limits>
40
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]41using namespace llvm;
42
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]43#define DEBUG_TYPE "x86-instr-info"
44
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]45#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]46#include "X86GenInstrInfo.inc"
47
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]48static cl::opt<bool>
49NoFusing("disable-spill-fusing",
50 cl::desc("Disable fusing of spill code into instructions"));
51static cl::opt<bool>
52PrintFailedFusing("print-failed-fuse-candidates",
53 cl::desc("Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
55 cl::Hidden);
56static cl::opt<bool>
57ReMatPICStubLoad("remat-pic-stub-load",
58 cl::desc("Re-materialize load from stub in PIC mode"),
59 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]60
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]61enum {
62 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]63 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]64 TB_INDEX_0 = 0,
65 TB_INDEX_1 = 1,
66 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]67 TB_INDEX_3 = 3,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]68 TB_INDEX_MASK = 0xf,
69
70 // Do not insert the reverse map (MemOp -> RegOp) into the table.
71 // This may be needed because there is a many -> one mapping.
72 TB_NO_REVERSE = 1 << 4,
73
74 // Do not insert the forward map (RegOp -> MemOp) into the table.
75 // This is needed for Native Client, which prohibits branch
76 // instructions from using a memory operand.
77 TB_NO_FORWARD = 1 << 5,
78
79 TB_FOLDED_LOAD = 1 << 6,
80 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]81
82 // Minimum alignment required for load/store.
83 // Used for RegOp->MemOp conversion.
84 // (stored in bits 8 - 15)
85 TB_ALIGN_SHIFT = 8,
86 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
87 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
88 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]89 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]90 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]91};
92
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]93struct X86OpTblEntry {
94 uint16_t RegOp;
95 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]96 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]97};
98
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]99// Pin the vtable to this file.
100void X86InstrInfo::anchor() {}
101
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]102X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
103 : X86GenInstrInfo(
Pavel Chupinbe9f1212014-09-22 13:11:35 +0000[diff] [blame]104 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]106 Subtarget(STI), RI(STI) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]107
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]108 static const X86OpTblEntry OpTbl2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]109 { X86::ADC32ri, X86::ADC32mi, 0 },
110 { X86::ADC32ri8, X86::ADC32mi8, 0 },
111 { X86::ADC32rr, X86::ADC32mr, 0 },
112 { X86::ADC64ri32, X86::ADC64mi32, 0 },
113 { X86::ADC64ri8, X86::ADC64mi8, 0 },
114 { X86::ADC64rr, X86::ADC64mr, 0 },
115 { X86::ADD16ri, X86::ADD16mi, 0 },
116 { X86::ADD16ri8, X86::ADD16mi8, 0 },
117 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
118 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
119 { X86::ADD16rr, X86::ADD16mr, 0 },
120 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
121 { X86::ADD32ri, X86::ADD32mi, 0 },
122 { X86::ADD32ri8, X86::ADD32mi8, 0 },
123 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
124 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
125 { X86::ADD32rr, X86::ADD32mr, 0 },
126 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
127 { X86::ADD64ri32, X86::ADD64mi32, 0 },
128 { X86::ADD64ri8, X86::ADD64mi8, 0 },
129 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
130 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
131 { X86::ADD64rr, X86::ADD64mr, 0 },
132 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
133 { X86::ADD8ri, X86::ADD8mi, 0 },
134 { X86::ADD8rr, X86::ADD8mr, 0 },
135 { X86::AND16ri, X86::AND16mi, 0 },
136 { X86::AND16ri8, X86::AND16mi8, 0 },
137 { X86::AND16rr, X86::AND16mr, 0 },
138 { X86::AND32ri, X86::AND32mi, 0 },
139 { X86::AND32ri8, X86::AND32mi8, 0 },
140 { X86::AND32rr, X86::AND32mr, 0 },
141 { X86::AND64ri32, X86::AND64mi32, 0 },
142 { X86::AND64ri8, X86::AND64mi8, 0 },
143 { X86::AND64rr, X86::AND64mr, 0 },
144 { X86::AND8ri, X86::AND8mi, 0 },
145 { X86::AND8rr, X86::AND8mr, 0 },
146 { X86::DEC16r, X86::DEC16m, 0 },
147 { X86::DEC32r, X86::DEC32m, 0 },
148 { X86::DEC64_16r, X86::DEC64_16m, 0 },
149 { X86::DEC64_32r, X86::DEC64_32m, 0 },
150 { X86::DEC64r, X86::DEC64m, 0 },
151 { X86::DEC8r, X86::DEC8m, 0 },
152 { X86::INC16r, X86::INC16m, 0 },
153 { X86::INC32r, X86::INC32m, 0 },
154 { X86::INC64_16r, X86::INC64_16m, 0 },
155 { X86::INC64_32r, X86::INC64_32m, 0 },
156 { X86::INC64r, X86::INC64m, 0 },
157 { X86::INC8r, X86::INC8m, 0 },
158 { X86::NEG16r, X86::NEG16m, 0 },
159 { X86::NEG32r, X86::NEG32m, 0 },
160 { X86::NEG64r, X86::NEG64m, 0 },
161 { X86::NEG8r, X86::NEG8m, 0 },
162 { X86::NOT16r, X86::NOT16m, 0 },
163 { X86::NOT32r, X86::NOT32m, 0 },
164 { X86::NOT64r, X86::NOT64m, 0 },
165 { X86::NOT8r, X86::NOT8m, 0 },
166 { X86::OR16ri, X86::OR16mi, 0 },
167 { X86::OR16ri8, X86::OR16mi8, 0 },
168 { X86::OR16rr, X86::OR16mr, 0 },
169 { X86::OR32ri, X86::OR32mi, 0 },
170 { X86::OR32ri8, X86::OR32mi8, 0 },
171 { X86::OR32rr, X86::OR32mr, 0 },
172 { X86::OR64ri32, X86::OR64mi32, 0 },
173 { X86::OR64ri8, X86::OR64mi8, 0 },
174 { X86::OR64rr, X86::OR64mr, 0 },
175 { X86::OR8ri, X86::OR8mi, 0 },
176 { X86::OR8rr, X86::OR8mr, 0 },
177 { X86::ROL16r1, X86::ROL16m1, 0 },
178 { X86::ROL16rCL, X86::ROL16mCL, 0 },
179 { X86::ROL16ri, X86::ROL16mi, 0 },
180 { X86::ROL32r1, X86::ROL32m1, 0 },
181 { X86::ROL32rCL, X86::ROL32mCL, 0 },
182 { X86::ROL32ri, X86::ROL32mi, 0 },
183 { X86::ROL64r1, X86::ROL64m1, 0 },
184 { X86::ROL64rCL, X86::ROL64mCL, 0 },
185 { X86::ROL64ri, X86::ROL64mi, 0 },
186 { X86::ROL8r1, X86::ROL8m1, 0 },
187 { X86::ROL8rCL, X86::ROL8mCL, 0 },
188 { X86::ROL8ri, X86::ROL8mi, 0 },
189 { X86::ROR16r1, X86::ROR16m1, 0 },
190 { X86::ROR16rCL, X86::ROR16mCL, 0 },
191 { X86::ROR16ri, X86::ROR16mi, 0 },
192 { X86::ROR32r1, X86::ROR32m1, 0 },
193 { X86::ROR32rCL, X86::ROR32mCL, 0 },
194 { X86::ROR32ri, X86::ROR32mi, 0 },
195 { X86::ROR64r1, X86::ROR64m1, 0 },
196 { X86::ROR64rCL, X86::ROR64mCL, 0 },
197 { X86::ROR64ri, X86::ROR64mi, 0 },
198 { X86::ROR8r1, X86::ROR8m1, 0 },
199 { X86::ROR8rCL, X86::ROR8mCL, 0 },
200 { X86::ROR8ri, X86::ROR8mi, 0 },
201 { X86::SAR16r1, X86::SAR16m1, 0 },
202 { X86::SAR16rCL, X86::SAR16mCL, 0 },
203 { X86::SAR16ri, X86::SAR16mi, 0 },
204 { X86::SAR32r1, X86::SAR32m1, 0 },
205 { X86::SAR32rCL, X86::SAR32mCL, 0 },
206 { X86::SAR32ri, X86::SAR32mi, 0 },
207 { X86::SAR64r1, X86::SAR64m1, 0 },
208 { X86::SAR64rCL, X86::SAR64mCL, 0 },
209 { X86::SAR64ri, X86::SAR64mi, 0 },
210 { X86::SAR8r1, X86::SAR8m1, 0 },
211 { X86::SAR8rCL, X86::SAR8mCL, 0 },
212 { X86::SAR8ri, X86::SAR8mi, 0 },
213 { X86::SBB32ri, X86::SBB32mi, 0 },
214 { X86::SBB32ri8, X86::SBB32mi8, 0 },
215 { X86::SBB32rr, X86::SBB32mr, 0 },
216 { X86::SBB64ri32, X86::SBB64mi32, 0 },
217 { X86::SBB64ri8, X86::SBB64mi8, 0 },
218 { X86::SBB64rr, X86::SBB64mr, 0 },
219 { X86::SHL16rCL, X86::SHL16mCL, 0 },
220 { X86::SHL16ri, X86::SHL16mi, 0 },
221 { X86::SHL32rCL, X86::SHL32mCL, 0 },
222 { X86::SHL32ri, X86::SHL32mi, 0 },
223 { X86::SHL64rCL, X86::SHL64mCL, 0 },
224 { X86::SHL64ri, X86::SHL64mi, 0 },
225 { X86::SHL8rCL, X86::SHL8mCL, 0 },
226 { X86::SHL8ri, X86::SHL8mi, 0 },
227 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
228 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
229 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
230 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
231 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
232 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
233 { X86::SHR16r1, X86::SHR16m1, 0 },
234 { X86::SHR16rCL, X86::SHR16mCL, 0 },
235 { X86::SHR16ri, X86::SHR16mi, 0 },
236 { X86::SHR32r1, X86::SHR32m1, 0 },
237 { X86::SHR32rCL, X86::SHR32mCL, 0 },
238 { X86::SHR32ri, X86::SHR32mi, 0 },
239 { X86::SHR64r1, X86::SHR64m1, 0 },
240 { X86::SHR64rCL, X86::SHR64mCL, 0 },
241 { X86::SHR64ri, X86::SHR64mi, 0 },
242 { X86::SHR8r1, X86::SHR8m1, 0 },
243 { X86::SHR8rCL, X86::SHR8mCL, 0 },
244 { X86::SHR8ri, X86::SHR8mi, 0 },
245 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
246 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
247 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
248 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
249 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
250 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
251 { X86::SUB16ri, X86::SUB16mi, 0 },
252 { X86::SUB16ri8, X86::SUB16mi8, 0 },
253 { X86::SUB16rr, X86::SUB16mr, 0 },
254 { X86::SUB32ri, X86::SUB32mi, 0 },
255 { X86::SUB32ri8, X86::SUB32mi8, 0 },
256 { X86::SUB32rr, X86::SUB32mr, 0 },
257 { X86::SUB64ri32, X86::SUB64mi32, 0 },
258 { X86::SUB64ri8, X86::SUB64mi8, 0 },
259 { X86::SUB64rr, X86::SUB64mr, 0 },
260 { X86::SUB8ri, X86::SUB8mi, 0 },
261 { X86::SUB8rr, X86::SUB8mr, 0 },
262 { X86::XOR16ri, X86::XOR16mi, 0 },
263 { X86::XOR16ri8, X86::XOR16mi8, 0 },
264 { X86::XOR16rr, X86::XOR16mr, 0 },
265 { X86::XOR32ri, X86::XOR32mi, 0 },
266 { X86::XOR32ri8, X86::XOR32mi8, 0 },
267 { X86::XOR32rr, X86::XOR32mr, 0 },
268 { X86::XOR64ri32, X86::XOR64mi32, 0 },
269 { X86::XOR64ri8, X86::XOR64mi8, 0 },
270 { X86::XOR64rr, X86::XOR64mr, 0 },
271 { X86::XOR8ri, X86::XOR8mi, 0 },
272 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]273 };
274
275 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]276 unsigned RegOp = OpTbl2Addr[i].RegOp;
277 unsigned MemOp = OpTbl2Addr[i].MemOp;
278 unsigned Flags = OpTbl2Addr[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]279 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
280 RegOp, MemOp,
281 // Index 0, folded load and store, no alignment requirement.
282 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]283 }
284
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]285 static const X86OpTblEntry OpTbl0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]286 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
287 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
288 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
289 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
290 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]291 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
292 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
293 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
294 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
295 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
296 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
297 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
298 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
299 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
300 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
301 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
302 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
303 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
304 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
305 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]306 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]307 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
308 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
309 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
310 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
311 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
312 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
313 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
314 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
315 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
316 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
317 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
318 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
319 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
320 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
321 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
322 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
323 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
324 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
325 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
326 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
327 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
328 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]329 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
330 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
331 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
332 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
333 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
334 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]335 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
336 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
337 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
338 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
339 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
340 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
341 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
342 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
343 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
344 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
345 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
346 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
347 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
348 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
349 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
350 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
351 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
352 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
353 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
354 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
355 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
356 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
357 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
358 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
359 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]360 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
361 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]362 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]363 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]364 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
368 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
369 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
370 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
371 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
372 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
373 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]374 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]375 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
376 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
377 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
378 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]379 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
380 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]381 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
382 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
383 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
384 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
385 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
386 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
387 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]388 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
389 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]390 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]391 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
392 // AVX-512 foldable instructions (256-bit versions)
393 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
394 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
398 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
399 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
400 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
401 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
402 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
403 // AVX-512 foldable instructions (128-bit versions)
404 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
405 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
406 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
407 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
408 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
409 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
410 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
411 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
412 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
413 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]414 };
415
416 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]417 unsigned RegOp = OpTbl0[i].RegOp;
418 unsigned MemOp = OpTbl0[i].MemOp;
419 unsigned Flags = OpTbl0[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]420 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
421 RegOp, MemOp, TB_INDEX_0 | Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]422 }
423
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]424 static const X86OpTblEntry OpTbl1[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]425 { X86::CMP16rr, X86::CMP16rm, 0 },
426 { X86::CMP32rr, X86::CMP32rm, 0 },
427 { X86::CMP64rr, X86::CMP64rm, 0 },
428 { X86::CMP8rr, X86::CMP8rm, 0 },
429 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
430 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
431 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
432 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
433 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
434 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
435 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
436 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
437 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
438 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]439 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
440 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
441 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
442 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
443 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
444 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
445 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
446 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]447 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
448 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]449 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
450 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]451 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
452 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
453 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
454 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
455 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
456 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
457 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
458 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]459 { X86::MOV16rr, X86::MOV16rm, 0 },
460 { X86::MOV32rr, X86::MOV32rm, 0 },
461 { X86::MOV64rr, X86::MOV64rm, 0 },
462 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
463 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
464 { X86::MOV8rr, X86::MOV8rm, 0 },
465 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
466 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]467 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
468 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
469 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
470 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]471 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
472 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
473 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
474 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
475 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
476 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
477 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
478 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
479 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
480 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]481 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
482 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
483 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
484 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
485 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
486 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]487 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
488 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
489 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]490 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
491 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
492 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
493 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
494 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
495 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
496 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
497 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
498 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
499 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]500 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]501 { X86::SQRTSDr, X86::SQRTSDm, 0 },
502 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
503 { X86::SQRTSSr, X86::SQRTSSm, 0 },
504 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
505 { X86::TEST16rr, X86::TEST16rm, 0 },
506 { X86::TEST32rr, X86::TEST32rm, 0 },
507 { X86::TEST64rr, X86::TEST64rm, 0 },
508 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]509 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]510 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
511 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]512 // AVX 128-bit versions of foldable instructions
513 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
514 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]515 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
516 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]517 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
518 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]519 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]520 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
521 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
522 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
523 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
524 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
525 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
526 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
527 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
528 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]529 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
530 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
531 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
532 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
533 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
534 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
535 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
536 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
537 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
538 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]539 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]540 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]541 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
542 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]543 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
544 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
545 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
546 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
547 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
548 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
549 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
550 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
551 { X86::VRCPPSr, X86::VRCPPSm, 0 },
552 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
553 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
554 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
555 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]556 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]557 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]558 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]559 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
560
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]561 // AVX 256-bit foldable instructions
562 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
563 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]564 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]565 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]566 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]567 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
568 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]569 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
570 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
571 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
572 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
573 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
574 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
575 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]576
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]577 // AVX2 foldable instructions
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]578 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
579 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
580 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
581 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
582 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
583 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]584
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]585 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]586 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
587 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]588 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
589 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
590 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
591 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
592 { X86::BLCI32rr, X86::BLCI32rm, 0 },
593 { X86::BLCI64rr, X86::BLCI64rm, 0 },
594 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
595 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
596 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
597 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
598 { X86::BLCS32rr, X86::BLCS32rm, 0 },
599 { X86::BLCS64rr, X86::BLCS64rm, 0 },
600 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
601 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]602 { X86::BLSI32rr, X86::BLSI32rm, 0 },
603 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]604 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
605 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]606 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
607 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
608 { X86::BLSR32rr, X86::BLSR32rm, 0 },
609 { X86::BLSR64rr, X86::BLSR64rm, 0 },
610 { X86::BZHI32rr, X86::BZHI32rm, 0 },
611 { X86::BZHI64rr, X86::BZHI64rm, 0 },
612 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
613 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
614 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
615 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
616 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
617 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]618 { X86::RORX32ri, X86::RORX32mi, 0 },
619 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]620 { X86::SARX32rr, X86::SARX32rm, 0 },
621 { X86::SARX64rr, X86::SARX64rm, 0 },
622 { X86::SHRX32rr, X86::SHRX32rm, 0 },
623 { X86::SHRX64rr, X86::SHRX64rm, 0 },
624 { X86::SHLX32rr, X86::SHLX32rm, 0 },
625 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]626 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
627 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]628 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
629 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
630 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]631 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
632 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]633
634 // AVX-512 foldable instructions
635 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
636 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]637 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
638 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]639 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
640 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]641 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
642 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]643 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
644 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]645 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
646 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]647 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
648 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]649 // AVX-512 foldable instructions (256-bit versions)
650 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
651 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
652 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
653 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
654 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
655 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
656 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
657 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
658 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
659 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
660 // AVX-512 foldable instructions (256-bit versions)
661 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
662 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
663 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
664 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
665 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
666 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
667 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
668 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
669 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
670 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]671
672 // AES foldable instructions
673 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
674 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
675 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]676 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]677 };
678
679 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]680 unsigned RegOp = OpTbl1[i].RegOp;
681 unsigned MemOp = OpTbl1[i].MemOp;
682 unsigned Flags = OpTbl1[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]683 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
684 RegOp, MemOp,
685 // Index 1, folded load
686 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]687 }
688
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]689 static const X86OpTblEntry OpTbl2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]690 { X86::ADC32rr, X86::ADC32rm, 0 },
691 { X86::ADC64rr, X86::ADC64rm, 0 },
692 { X86::ADD16rr, X86::ADD16rm, 0 },
693 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
694 { X86::ADD32rr, X86::ADD32rm, 0 },
695 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
696 { X86::ADD64rr, X86::ADD64rm, 0 },
697 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
698 { X86::ADD8rr, X86::ADD8rm, 0 },
699 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
700 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
701 { X86::ADDSDrr, X86::ADDSDrm, 0 },
702 { X86::ADDSSrr, X86::ADDSSrm, 0 },
703 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
704 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
705 { X86::AND16rr, X86::AND16rm, 0 },
706 { X86::AND32rr, X86::AND32rm, 0 },
707 { X86::AND64rr, X86::AND64rm, 0 },
708 { X86::AND8rr, X86::AND8rm, 0 },
709 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
710 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
711 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
712 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]713 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
714 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
715 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
716 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]717 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
718 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
719 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
720 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
721 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
722 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
723 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
724 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
725 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
726 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
727 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
728 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
729 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
730 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
731 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
732 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
733 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
734 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
735 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
736 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
737 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
738 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
739 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
740 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
741 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
742 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
743 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
744 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
745 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
746 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
747 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
748 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
749 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
750 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
751 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
752 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
753 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
754 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
755 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
756 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
757 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
758 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
759 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
760 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
761 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
762 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
763 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
764 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
765 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
766 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
767 { X86::CMPSDrr, X86::CMPSDrm, 0 },
768 { X86::CMPSSrr, X86::CMPSSrm, 0 },
769 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
770 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
771 { X86::DIVSDrr, X86::DIVSDrm, 0 },
772 { X86::DIVSSrr, X86::DIVSSrm, 0 },
773 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
774 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
775 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
776 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
777 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
778 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
779 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
780 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
781 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
782 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
783 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
784 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
785 { X86::IMUL16rr, X86::IMUL16rm, 0 },
786 { X86::IMUL32rr, X86::IMUL32rm, 0 },
787 { X86::IMUL64rr, X86::IMUL64rm, 0 },
788 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
789 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]790 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
791 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
792 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
793 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
794 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
795 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]796 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]797 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]798 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]799 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]800 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]801 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]802 { X86::MINSDrr, X86::MINSDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]803 { X86::MINSSrr, X86::MINSSrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]804 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]805 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
806 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
807 { X86::MULSDrr, X86::MULSDrm, 0 },
808 { X86::MULSSrr, X86::MULSSrm, 0 },
809 { X86::OR16rr, X86::OR16rm, 0 },
810 { X86::OR32rr, X86::OR32rm, 0 },
811 { X86::OR64rr, X86::OR64rm, 0 },
812 { X86::OR8rr, X86::OR8rm, 0 },
813 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
814 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
815 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
816 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]817 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]818 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
819 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
820 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
821 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
822 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
823 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]824 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
825 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]826 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]827 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]828 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
829 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
830 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
831 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]832 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]833 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
834 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]835 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]836 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
837 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
838 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]839 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]840 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]841 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
842 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]843 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]844 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]845 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]846 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]847 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]848 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]849 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
850 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
851 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
852 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
853 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]854 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
855 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
856 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
857 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
858 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
859 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
860 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
861 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]862 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]863 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]864 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
865 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
866 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
867 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
868 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
869 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
870 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]871 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
872 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
873 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
874 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]875 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
876 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
877 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
878 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
879 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
880 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
881 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
882 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
883 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
884 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
885 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
886 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
887 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
888 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
889 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
890 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
891 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
892 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
893 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
894 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
895 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
896 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
897 { X86::SBB32rr, X86::SBB32rm, 0 },
898 { X86::SBB64rr, X86::SBB64rm, 0 },
899 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
900 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
901 { X86::SUB16rr, X86::SUB16rm, 0 },
902 { X86::SUB32rr, X86::SUB32rm, 0 },
903 { X86::SUB64rr, X86::SUB64rm, 0 },
904 { X86::SUB8rr, X86::SUB8rm, 0 },
905 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
906 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
907 { X86::SUBSDrr, X86::SUBSDrm, 0 },
908 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]909 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]910 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
911 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
912 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
913 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
914 { X86::XOR16rr, X86::XOR16rm, 0 },
915 { X86::XOR32rr, X86::XOR32rm, 0 },
916 { X86::XOR64rr, X86::XOR64rm, 0 },
917 { X86::XOR8rr, X86::XOR8rm, 0 },
918 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]919 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
920 // AVX 128-bit versions of foldable instructions
921 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
922 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
923 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
924 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
925 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
926 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
927 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
928 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
929 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
930 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]931 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
932 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]933 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
934 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]935 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
936 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
937 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]938 { X86::VADDPDrr, X86::VADDPDrm, 0 },
939 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]940 { X86::VADDSDrr, X86::VADDSDrm, 0 },
941 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]942 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
943 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
944 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
945 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
946 { X86::VANDPDrr, X86::VANDPDrm, 0 },
947 { X86::VANDPSrr, X86::VANDPSrm, 0 },
948 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
949 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
950 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
951 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
952 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
953 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]954 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
955 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]956 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
957 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]958 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
959 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
960 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
961 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
962 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
963 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
964 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
965 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
966 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
967 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]968 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
969 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
970 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
971 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]972 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
973 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]974 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]975 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]976 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]977 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]978 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]979 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]980 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]981 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]982 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
983 { X86::VMULPDrr, X86::VMULPDrm, 0 },
984 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]985 { X86::VMULSDrr, X86::VMULSDrm, 0 },
986 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]987 { X86::VORPDrr, X86::VORPDrm, 0 },
988 { X86::VORPSrr, X86::VORPSrm, 0 },
989 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
990 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
991 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
992 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
993 { X86::VPADDBrr, X86::VPADDBrm, 0 },
994 { X86::VPADDDrr, X86::VPADDDrm, 0 },
995 { X86::VPADDQrr, X86::VPADDQrm, 0 },
996 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
997 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
998 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
999 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1000 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1001 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1002 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1003 { X86::VPANDrr, X86::VPANDrm, 0 },
1004 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1005 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
1006 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
1007 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1008 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1009 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1010 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1011 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1012 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1013 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1014 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1015 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1016 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1017 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1018 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1019 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1020 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1021 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1022 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
1023 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1024 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1025 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1026 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1027 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1028 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1029 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1030 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1031 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1032 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1033 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1034 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1035 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1036 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1037 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1038 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1039 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1040 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1041 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1042 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1043 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1044 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1045 { X86::VPORrr, X86::VPORrm, 0 },
1046 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1047 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1048 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1049 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1050 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1051 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1052 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1053 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1054 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1055 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1056 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1057 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1058 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1059 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1060 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1061 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1062 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1063 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1064 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1065 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1066 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1067 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1068 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1069 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1070 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1071 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1072 { X86::VPXORrr, X86::VPXORrm, 0 },
1073 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1074 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1075 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1076 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1077 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1078 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1079 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1080 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1081 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1082 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1083 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1084 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1085 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1086 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1087 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1088 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1089 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1090 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1091 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1092 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1093 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1094 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1095 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1096 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1097 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1098 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1099 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1100 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1101 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1102 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1103 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1104 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1105 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1106 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1107 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1108 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1109 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1110 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1111 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1112 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1113 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1114 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1115 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1116 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1117 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1118 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1119 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1120 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1121 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1122 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1123 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1124 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1125 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1126 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1127 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1128 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1129 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1130 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1131 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1132 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1133 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1134 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1135 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1136 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1137 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1138 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1139 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1140 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1141 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1142 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1143 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1144 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1145 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1146 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1147 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1148 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1149 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1150 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1151 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1152 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1153 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1154 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1155 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1156 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1157 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1158 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1159 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1160 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
1161 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1162 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
1163 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1164 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1165 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1166 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1167 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1168 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1169 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1170 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1171 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1172 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1173 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1174 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1175 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1176 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1177 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1178 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1179 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1180 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1181 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1182 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1183 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1184 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1185 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1186 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1187 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1188 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1189 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1190 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1191 { X86::VPORYrr, X86::VPORYrm, 0 },
1192 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1193 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1194 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1195 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1196 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1197 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1198 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1199 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1200 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1201 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1202 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1203 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1204 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1205 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1206 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1207 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1208 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1209 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1210 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1211 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1212 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1213 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1214 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1215 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1216 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1217 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1218 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1219 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1220 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1221 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1222 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1223 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1224 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1225 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1226 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1227 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1228 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1229 // FIXME: add AVX 256-bit foldable instructions
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1230
1231 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1232 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1233 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1234 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
1235 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
1236 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
1237 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1238 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1239 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1240 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
1241 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
1242 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
1243 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1244 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1245 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1246 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
1247 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
1248 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
1249 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1250 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1251 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1252 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
1253 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
1254 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 },
1255 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
1256 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
1257 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
1258 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
1259 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
1260 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
1261 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
1262 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
1263 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1264
1265 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1266 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1267 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1268 { X86::MULX32rr, X86::MULX32rm, 0 },
1269 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1270 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1271 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1272 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1273 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1274
1275 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1276 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1277 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1278 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1279 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1280 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1281 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1282 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1283 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1284 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1285 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1286 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1287 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1288 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1289 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1290 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1291 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1292 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1293 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1294 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1295 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1296 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1297 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1298 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1299 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1300 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1301 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1302 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1303 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1304 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1305 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1306 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1307 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1308 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1309 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1310 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1311 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1312 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1313
1314 // AES foldable instructions
1315 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1316 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1317 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1318 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1319 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 },
1320 { X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 },
1321 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 },
1322 { X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 },
1323
1324 // SHA foldable instructions
1325 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1326 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1327 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1328 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1329 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1330 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1331 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1332 };
1333
1334 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]1335 unsigned RegOp = OpTbl2[i].RegOp;
1336 unsigned MemOp = OpTbl2[i].MemOp;
1337 unsigned Flags = OpTbl2[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1338 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1339 RegOp, MemOp,
1340 // Index 2, folded load
1341 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1342 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1343
1344 static const X86OpTblEntry OpTbl3[] = {
1345 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1346 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1347 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1348 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1349 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1350 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1351 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1352
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1353 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1354 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1355 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1356 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1357 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1358 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1359 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1360 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1361 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1362 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1363 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1364 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1365
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1366 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1367 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1368 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1369 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1370 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1371 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1372
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1373 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1374 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1375 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1376 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1377 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1378 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1379 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1380 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1381 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1382 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1383 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1384 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1385
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1386 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1387 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1388 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1389 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1390 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1391 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1392
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1393 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1394 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1395 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1396 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1397 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1398 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1399 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1400 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1401 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1402 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1403 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1404 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1405
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1406 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1407 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1408 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1409 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1410 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1411 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1412
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1413 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1414 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1415 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1416 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1417 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1418 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1419 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1420 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1421 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1422 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1423 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1424 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1425
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1426 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1427 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1428 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1429 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1430 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1431 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1432 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1433 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1434 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1435 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1436 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1437 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1438
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1439 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1440 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1441 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1442 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1443 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1444 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1445 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1446 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1447 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1448 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1449 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1450 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1451
1452 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1453 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1454 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1455 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1456 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1457 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1458 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1459 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1460 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1461 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1462 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1463 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1464 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1465 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1466 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1467 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1468 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1469 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1470 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1471 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1472 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1473 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1474 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1475 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1476 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1477 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1478 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1479 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1480 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1481 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1482 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1483 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1484 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1485 // AVX-512 VPERMI instructions with 3 source operands.
1486 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1487 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1488 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1489 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1490 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1491 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1492 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1493 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1494 };
1495
1496 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1497 unsigned RegOp = OpTbl3[i].RegOp;
1498 unsigned MemOp = OpTbl3[i].MemOp;
1499 unsigned Flags = OpTbl3[i].Flags;
1500 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1501 RegOp, MemOp,
1502 // Index 3, folded load
1503 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1504 }
1505
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]1506}
1507
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1508void
1509X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1510 MemOp2RegOpTableType &M2RTable,
1511 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1512 if ((Flags & TB_NO_FORWARD) == 0) {
1513 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1514 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1515 }
1516 if ((Flags & TB_NO_REVERSE) == 0) {
1517 assert(!M2RTable.count(MemOp) &&
1518 "Duplicated entries in unfolding maps?");
1519 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1520 }
1521}
1522
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1523bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1524X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1525 unsigned &SrcReg, unsigned &DstReg,
1526 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1527 switch (MI.getOpcode()) {
1528 default: break;
1529 case X86::MOVSX16rr8:
1530 case X86::MOVZX16rr8:
1531 case X86::MOVSX32rr8:
1532 case X86::MOVZX32rr8:
1533 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]1534 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]1535 // It's not always legal to reference the low 8-bit of the larger
1536 // register in 32-bit mode.
1537 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1538 case X86::MOVSX32rr16:
1539 case X86::MOVZX32rr16:
1540 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]1541 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1542 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1543 // Be conservative.
1544 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1545 SrcReg = MI.getOperand(1).getReg();
1546 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1547 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1548 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1549 case X86::MOVSX16rr8:
1550 case X86::MOVZX16rr8:
1551 case X86::MOVSX32rr8:
1552 case X86::MOVZX32rr8:
1553 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1554 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1555 break;
1556 case X86::MOVSX32rr16:
1557 case X86::MOVZX32rr16:
1558 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1559 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1560 break;
1561 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1562 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1563 break;
1564 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1565 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1566 }
1567 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1568 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1569}
1570
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1571/// isFrameOperand - Return true and the FrameIndex if the specified
1572/// operand and follow operands form a reference to the stack frame.
1573bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1574 int &FrameIndex) const {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1575 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1576 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1577 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1578 MI->getOperand(Op+X86::AddrDisp).isImm() &&
1579 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1580 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1581 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1582 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1583 return true;
1584 }
1585 return false;
1586}
1587
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1588static bool isFrameLoadOpcode(int Opcode) {
1589 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]1590 default:
1591 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1592 case X86::MOV8rm:
1593 case X86::MOV16rm:
1594 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]1595 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]1596 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1597 case X86::MOVSSrm:
1598 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]1599 case X86::MOVAPSrm:
1600 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]1601 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1602 case X86::VMOVSSrm:
1603 case X86::VMOVSDrm:
1604 case X86::VMOVAPSrm:
1605 case X86::VMOVAPDrm:
1606 case X86::VMOVDQArm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1607 case X86::VMOVAPSYrm:
1608 case X86::VMOVAPDYrm:
1609 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]1610 case X86::MMX_MOVD64rm:
1611 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1612 case X86::VMOVAPSZrm:
1613 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1614 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1615 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1616}
1617
1618static bool isFrameStoreOpcode(int Opcode) {
1619 switch (Opcode) {
1620 default: break;
1621 case X86::MOV8mr:
1622 case X86::MOV16mr:
1623 case X86::MOV32mr:
1624 case X86::MOV64mr:
1625 case X86::ST_FpP64m:
1626 case X86::MOVSSmr:
1627 case X86::MOVSDmr:
1628 case X86::MOVAPSmr:
1629 case X86::MOVAPDmr:
1630 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1631 case X86::VMOVSSmr:
1632 case X86::VMOVSDmr:
1633 case X86::VMOVAPSmr:
1634 case X86::VMOVAPDmr:
1635 case X86::VMOVDQAmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1636 case X86::VMOVAPSYmr:
1637 case X86::VMOVAPDYmr:
1638 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1639 case X86::VMOVUPSZmr:
1640 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1641 case X86::MMX_MOVD64mr:
1642 case X86::MMX_MOVQ64mr:
1643 case X86::MMX_MOVNTQmr:
1644 return true;
1645 }
1646 return false;
1647}
1648
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1649unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1650 int &FrameIndex) const {
1651 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1652 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1653 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1654 return 0;
1655}
1656
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1657unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1658 int &FrameIndex) const {
1659 if (isFrameLoadOpcode(MI->getOpcode())) {
1660 unsigned Reg;
1661 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1662 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1663 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1664 const MachineMemOperand *Dummy;
1665 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1666 }
1667 return 0;
1668}
1669
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]1670unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1671 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1672 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1673 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1674 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]1675 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1676 return 0;
1677}
1678
1679unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1680 int &FrameIndex) const {
1681 if (isFrameStoreOpcode(MI->getOpcode())) {
1682 unsigned Reg;
1683 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1684 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1685 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1686 const MachineMemOperand *Dummy;
1687 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1688 }
1689 return 0;
1690}
1691
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1692/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1693/// X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1694static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]1695 // Don't waste compile time scanning use-def chains of physregs.
1696 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1697 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1698 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]1699 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1700 E = MRI.def_instr_end(); I != E; ++I) {
1701 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1702 if (DefMI->getOpcode() != X86::MOVPC32r)
1703 return false;
1704 assert(!isPICBase && "More than one PIC base?");
1705 isPICBase = true;
1706 }
1707 return isPICBase;
1708}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]1709
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]1710bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]1711X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1712 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1713 switch (MI->getOpcode()) {
1714 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1715 case X86::MOV8rm:
1716 case X86::MOV16rm:
1717 case X86::MOV32rm:
1718 case X86::MOV64rm:
1719 case X86::LD_Fp64m:
1720 case X86::MOVSSrm:
1721 case X86::MOVSDrm:
1722 case X86::MOVAPSrm:
1723 case X86::MOVUPSrm:
1724 case X86::MOVAPDrm:
1725 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1726 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1727 case X86::VMOVSSrm:
1728 case X86::VMOVSDrm:
1729 case X86::VMOVAPSrm:
1730 case X86::VMOVUPSrm:
1731 case X86::VMOVAPDrm:
1732 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1733 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1734 case X86::VMOVAPSYrm:
1735 case X86::VMOVUPSYrm:
1736 case X86::VMOVAPDYrm:
1737 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1738 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1739 case X86::MMX_MOVD64rm:
1740 case X86::MMX_MOVQ64rm:
1741 case X86::FsVMOVAPSrm:
1742 case X86::FsVMOVAPDrm:
1743 case X86::FsMOVAPSrm:
1744 case X86::FsMOVAPDrm: {
1745 // Loads from constant pools are trivially rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1746 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1747 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1748 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1749 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1750 MI->isInvariantLoad(AA)) {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1751 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1752 if (BaseReg == 0 || BaseReg == X86::RIP)
1753 return true;
1754 // Allow re-materialization of PIC load.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1755 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1756 return false;
1757 const MachineFunction &MF = *MI->getParent()->getParent();
1758 const MachineRegisterInfo &MRI = MF.getRegInfo();
1759 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]1760 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1761 return false;
1762 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1763
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1764 case X86::LEA32r:
1765 case X86::LEA64r: {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1766 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1767 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1768 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1769 !MI->getOperand(1+X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1770 // lea fi#, lea GV, etc. are all rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1771 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1772 return true;
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1773 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1774 if (BaseReg == 0)
1775 return true;
1776 // Allow re-materialization of lea PICBase + x.
1777 const MachineFunction &MF = *MI->getParent()->getParent();
1778 const MachineRegisterInfo &MRI = MF.getRegInfo();
1779 return regIsPICBase(BaseReg, MRI);
1780 }
1781 return false;
1782 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1783 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1784
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]1785 // All other instructions marked M_REMATERIALIZABLE are always trivially
1786 // rematerializable.
1787 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1788}
1789
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]1790bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1791 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1792 MachineBasicBlock::iterator E = MBB.end();
1793
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1794 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1795 // safety after visiting 4 instructions in each direction, we will assume
1796 // it's not safe.
1797 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1798 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1799 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1800 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1801 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]1802 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1803 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1804 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1805 continue;
1806 if (MO.getReg() == X86::EFLAGS) {
1807 if (MO.isUse())
1808 return false;
1809 SeenDef = true;
1810 }
1811 }
1812
1813 if (SeenDef)
1814 // This instruction defines EFLAGS, no need to look any further.
1815 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1816 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1817 // Skip over DBG_VALUE.
1818 while (Iter != E && Iter->isDebugValue())
1819 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1820 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]1821
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1822 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1823 // live in.
1824 if (Iter == E) {
1825 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1826 SE = MBB.succ_end(); SI != SE; ++SI)
1827 if ((*SI)->isLiveIn(X86::EFLAGS))
1828 return false;
1829 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1830 }
1831
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1832 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1833 Iter = I;
1834 for (unsigned i = 0; i < 4; ++i) {
1835 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]1836 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1837 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1838 return !MBB.isLiveIn(X86::EFLAGS);
1839
1840 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1841 // Skip over DBG_VALUE.
1842 while (Iter != B && Iter->isDebugValue())
1843 --Iter;
1844
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1845 bool SawKill = false;
1846 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1847 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]1848 // A register mask may clobber EFLAGS, but we should still look for a
1849 // live EFLAGS def.
1850 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1851 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1852 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1853 if (MO.isDef()) return MO.isDead();
1854 if (MO.isKill()) SawKill = true;
1855 }
1856 }
1857
1858 if (SawKill)
1859 // This instruction kills EFLAGS and doesn't redefine it, so
1860 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]1861 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1862 }
1863
1864 // Conservative answer.
1865 return false;
1866}
1867
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1868void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1869 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1870 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]1871 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1872 const TargetRegisterInfo &TRI) const {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]1873 // MOV32r0 is implemented with a xor which clobbers condition code.
1874 // Re-materialize it as movri instructions to avoid side effects.
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1875 unsigned Opc = Orig->getOpcode();
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]1876 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1877 DebugLoc DL = Orig->getDebugLoc();
1878 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1879 .addImm(0);
1880 } else {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1881 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1882 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1883 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]1884
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]1885 MachineInstr *NewMI = std::prev(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1886 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1887}
1888
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1889/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1890/// is not marked dead.
1891static bool hasLiveCondCodeDef(MachineInstr *MI) {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1892 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1893 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1894 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1895 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1896 return true;
1897 }
1898 }
1899 return false;
1900}
1901
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]1902/// getTruncatedShiftCount - check whether the shift count for a machine operand
1903/// is non-zero.
1904inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1905 unsigned ShiftAmtOperandIdx) {
1906 // The shift count is six bits with the REX.W prefix and five bits without.
1907 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1908 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1909 return Imm & ShiftCountMask;
1910}
1911
1912/// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1913/// can be represented by a LEA instruction.
1914inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1915 // Left shift instructions can be transformed into load-effective-address
1916 // instructions if we can encode them appropriately.
1917 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1918 // The SIB.scale field is two bits wide which means that we can encode any
1919 // shift amount less than 4.
1920 return ShAmt < 4 && ShAmt > 0;
1921}
1922
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]1923bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1924 unsigned Opc, bool AllowSP,
1925 unsigned &NewSrc, bool &isKill, bool &isUndef,
1926 MachineOperand &ImplicitOp) const {
1927 MachineFunction &MF = *MI->getParent()->getParent();
1928 const TargetRegisterClass *RC;
1929 if (AllowSP) {
1930 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1931 } else {
1932 RC = Opc != X86::LEA32r ?
1933 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1934 }
1935 unsigned SrcReg = Src.getReg();
1936
1937 // For both LEA64 and LEA32 the register already has essentially the right
1938 // type (32-bit or 64-bit) we may just need to forbid SP.
1939 if (Opc != X86::LEA64_32r) {
1940 NewSrc = SrcReg;
1941 isKill = Src.isKill();
1942 isUndef = Src.isUndef();
1943
1944 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1945 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1946 return false;
1947
1948 return true;
1949 }
1950
1951 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1952 // another we need to add 64-bit registers to the final MI.
1953 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1954 ImplicitOp = Src;
1955 ImplicitOp.setImplicit();
1956
1957 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1958 MachineBasicBlock::LivenessQueryResult LQR =
1959 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1960
1961 switch (LQR) {
1962 case MachineBasicBlock::LQR_Unknown:
1963 // We can't give sane liveness flags to the instruction, abandon LEA
1964 // formation.
1965 return false;
1966 case MachineBasicBlock::LQR_Live:
1967 isKill = MI->killsRegister(SrcReg);
1968 isUndef = false;
1969 break;
1970 default:
1971 // The physreg itself is dead, so we have to use it as an <undef>.
1972 isKill = false;
1973 isUndef = true;
1974 break;
1975 }
1976 } else {
1977 // Virtual register of the wrong class, we have to create a temporary 64-bit
1978 // vreg to feed into the LEA.
1979 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1980 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1981 get(TargetOpcode::COPY))
1982 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1983 .addOperand(Src);
1984
1985 // Which is obviously going to be dead after we're done with it.
1986 isKill = true;
1987 isUndef = false;
1988 }
1989
1990 // We've set all the parameters without issue.
1991 return true;
1992}
1993
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1994/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1995/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1996/// to a 32-bit superregister and then truncating back down to a 16-bit
1997/// subregister.
1998MachineInstr *
1999X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2000 MachineFunction::iterator &MFI,
2001 MachineBasicBlock::iterator &MBBI,
2002 LiveVariables *LV) const {
2003 MachineInstr *MI = MBBI;
2004 unsigned Dest = MI->getOperand(0).getReg();
2005 unsigned Src = MI->getOperand(1).getReg();
2006 bool isDead = MI->getOperand(0).isDead();
2007 bool isKill = MI->getOperand(1).isKill();
2008
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2009 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2010 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2011 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2012 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2013 Opc = X86::LEA64_32r;
2014 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2015 } else {
2016 Opc = X86::LEA32r;
2017 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2018 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2019
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2020 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2021 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2022 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2023 // movw (%rbp,%rcx,2), %dx
2024 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2025 // But testing has shown this *does* help performance in 64-bit mode (at
2026 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2027 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2028 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2029 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2030 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2031 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2032
2033 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2034 get(Opc), leaOutReg);
2035 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2036 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2037 case X86::SHL16ri: {
2038 unsigned ShAmt = MI->getOperand(2).getImm();
2039 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2040 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2041 break;
2042 }
2043 case X86::INC16r:
2044 case X86::INC64_16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2045 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2046 break;
2047 case X86::DEC16r:
2048 case X86::DEC64_16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2049 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2050 break;
2051 case X86::ADD16ri:
2052 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2053 case X86::ADD16ri_DB:
2054 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2055 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2056 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2057 case X86::ADD16rr:
2058 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2059 unsigned Src2 = MI->getOperand(2).getReg();
2060 bool isKill2 = MI->getOperand(2).isKill();
2061 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2062 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2063 if (Src == Src2) {
2064 // ADD16rr %reg1028<kill>, %reg1028
2065 // just a single insert_subreg.
2066 addRegReg(MIB, leaInReg, true, leaInReg, false);
2067 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2068 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2069 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2070 else
2071 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2072 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2073 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2074 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2075 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2076 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2077 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2078 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2079 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2080 }
2081 if (LV && isKill2 && InsMI2)
2082 LV->replaceKillInstruction(Src2, MI, InsMI2);
2083 break;
2084 }
2085 }
2086
2087 MachineInstr *NewMI = MIB;
2088 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2089 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2090 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2091 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2092
2093 if (LV) {
2094 // Update live variables
2095 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2096 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2097 if (isKill)
2098 LV->replaceKillInstruction(Src, MI, InsMI);
2099 if (isDead)
2100 LV->replaceKillInstruction(Dest, MI, ExtMI);
2101 }
2102
2103 return ExtMI;
2104}
2105
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2106/// convertToThreeAddress - This method must be implemented by targets that
2107/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2108/// may be able to convert a two-address instruction into a true
2109/// three-address instruction on demand. This allows the X86 target (for
2110/// example) to convert ADD and SHL instructions into LEA instructions if they
2111/// would require register copies due to two-addressness.
2112///
2113/// This method returns a null pointer if the transformation cannot be
2114/// performed, otherwise it returns the new instruction.
2115///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2116MachineInstr *
2117X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2118 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]2119 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2120 MachineInstr *MI = MBBI;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2121
2122 // The following opcodes also sets the condition code register(s). Only
2123 // convert them to equivalent lea if the condition code register def's
2124 // are dead!
2125 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2126 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2127
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2128 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2129 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2130 const MachineOperand &Dest = MI->getOperand(0);
2131 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2132
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2133 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2134 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2135 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2136 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2137 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2138 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2139
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2140 unsigned MIOpc = MI->getOpcode();
2141 switch (MIOpc) {
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2142 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2143 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2144 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2145 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2146
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2147 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2148 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2149 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2150 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2151 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2152
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2153 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2154 .addOperand(Dest)
2155 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2156 break;
2157 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2158 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2159 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2160 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2161 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2162
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2163 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2164
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2165 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2166 bool isKill, isUndef;
2167 unsigned SrcReg;
2168 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2169 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2170 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2171 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2172
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2173 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2174 .addOperand(Dest)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2175 .addReg(0).addImm(1 << ShAmt)
2176 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2177 .addImm(0).addReg(0);
2178 if (ImplicitOp.getReg() != 0)
2179 MIB.addOperand(ImplicitOp);
2180 NewMI = MIB;
2181
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2182 break;
2183 }
2184 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2185 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2186 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2187 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2188
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2189 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2190 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2191 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2192 .addOperand(Dest)
2193 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2194 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2195 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2196 default: {
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2197
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2198 switch (MIOpc) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2199 default: return nullptr;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2200 case X86::INC64r:
Dan Gohmanbeac19e2009-01-06 23:34:46 +0000[diff] [blame]2201 case X86::INC32r:
2202 case X86::INC64_32r: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2203 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Evan Cheng82bc90a2007-10-09 07:14:53 +0000[diff] [blame]2204 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2205 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2206 bool isKill, isUndef;
2207 unsigned SrcReg;
2208 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2209 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2210 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2211 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2212
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2213 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2214 .addOperand(Dest)
2215 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2216 if (ImplicitOp.getReg() != 0)
2217 MIB.addOperand(ImplicitOp);
2218
2219 NewMI = addOffset(MIB, 1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2220 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2221 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2222 case X86::INC16r:
2223 case X86::INC64_16r:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2224 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2225 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2226 : nullptr;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2227 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2228 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2229 .addOperand(Dest).addOperand(Src), 1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2230 break;
2231 case X86::DEC64r:
Dan Gohmanbeac19e2009-01-06 23:34:46 +0000[diff] [blame]2232 case X86::DEC32r:
2233 case X86::DEC64_32r: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2234 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Evan Cheng82bc90a2007-10-09 07:14:53 +0000[diff] [blame]2235 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2236 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2237
2238 bool isKill, isUndef;
2239 unsigned SrcReg;
2240 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2241 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2242 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2243 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2244
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2245 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2246 .addOperand(Dest)
2247 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2248 if (ImplicitOp.getReg() != 0)
2249 MIB.addOperand(ImplicitOp);
2250
2251 NewMI = addOffset(MIB, -1);
2252
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2253 break;
2254 }
2255 case X86::DEC16r:
2256 case X86::DEC64_16r:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2257 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2258 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2259 : nullptr;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2260 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2261 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2262 .addOperand(Dest).addOperand(Src), -1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2263 break;
2264 case X86::ADD64rr:
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2265 case X86::ADD64rr_DB:
2266 case X86::ADD32rr:
2267 case X86::ADD32rr_DB: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2268 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2269 unsigned Opc;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2270 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2271 Opc = X86::LEA64r;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2272 else
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2273 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2274
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2275 bool isKill, isUndef;
2276 unsigned SrcReg;
2277 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2278 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2279 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2280 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2281
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2282 const MachineOperand &Src2 = MI->getOperand(2);
2283 bool isKill2, isUndef2;
2284 unsigned SrcReg2;
2285 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2286 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2287 SrcReg2, isKill2, isUndef2, ImplicitOp2))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2288 return nullptr;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2289
2290 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2291 .addOperand(Dest);
2292 if (ImplicitOp.getReg() != 0)
2293 MIB.addOperand(ImplicitOp);
2294 if (ImplicitOp2.getReg() != 0)
2295 MIB.addOperand(ImplicitOp2);
2296
2297 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
Nadav Rotem4968e452012-07-16 10:52:25 +0000[diff] [blame]2298
2299 // Preserve undefness of the operands.
Tim Northover339bf152013-06-01 10:23:46 +0000[diff] [blame]2300 NewMI->getOperand(1).setIsUndef(isUndef);
2301 NewMI->getOperand(3).setIsUndef(isUndef2);
Nadav Rotem4968e452012-07-16 10:52:25 +0000[diff] [blame]2302
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2303 if (LV && Src2.isKill())
2304 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2305 break;
2306 }
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2307 case X86::ADD16rr:
2308 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2309 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2310 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2311 : nullptr;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2312 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2313 unsigned Src2 = MI->getOperand(2).getReg();
2314 bool isKill2 = MI->getOperand(2).isKill();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2315 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2316 .addOperand(Dest),
2317 Src.getReg(), Src.isKill(), Src2, isKill2);
2318
2319 // Preserve undefness of the operands.
2320 bool isUndef = MI->getOperand(1).isUndef();
2321 bool isUndef2 = MI->getOperand(2).isUndef();
2322 NewMI->getOperand(1).setIsUndef(isUndef);
2323 NewMI->getOperand(3).setIsUndef(isUndef2);
2324
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2325 if (LV && isKill2)
2326 LV->replaceKillInstruction(Src2, MI, NewMI);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2327 break;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2328 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2329 case X86::ADD64ri32:
2330 case X86::ADD64ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2331 case X86::ADD64ri32_DB:
2332 case X86::ADD64ri8_DB:
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2333 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2334 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2335 .addOperand(Dest).addOperand(Src),
2336 MI->getOperand(2).getImm());
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2337 break;
2338 case X86::ADD32ri:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2339 case X86::ADD32ri8:
2340 case X86::ADD32ri_DB:
2341 case X86::ADD32ri8_DB: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2342 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Tim Northover339bf152013-06-01 10:23:46 +0000[diff] [blame]2343 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2344
2345 bool isKill, isUndef;
2346 unsigned SrcReg;
2347 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2348 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2349 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2350 return nullptr;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2351
2352 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2353 .addOperand(Dest)
2354 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2355 if (ImplicitOp.getReg() != 0)
2356 MIB.addOperand(ImplicitOp);
2357
2358 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2359 break;
2360 }
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2361 case X86::ADD16ri:
2362 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2363 case X86::ADD16ri_DB:
2364 case X86::ADD16ri8_DB:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2365 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2366 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2367 : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2368 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2369 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2370 .addOperand(Dest).addOperand(Src),
2371 MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2372 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2373 }
2374 }
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2375 }
2376
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2377 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2378
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2379 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2380 if (Src.isKill())
2381 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2382 if (Dest.isDead())
2383 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2384 }
2385
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2386 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2387 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2388}
2389
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2390/// commuteInstruction - We have a few instructions that must be hacked on to
2391/// commute them.
2392///
Evan Cheng03553bb2008-06-16 07:33:11 +0000[diff] [blame]2393MachineInstr *
2394X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2395 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2396 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2397 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2398 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2399 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2400 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2401 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2402 unsigned Opc;
2403 unsigned Size;
2404 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2405 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2406 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2407 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2408 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2409 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2410 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2411 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2412 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]2413 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2414 if (NewMI) {
2415 MachineFunction &MF = *MI->getParent()->getParent();
2416 MI = MF.CloneMachineInstr(MI);
2417 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]2418 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2419 MI->setDesc(get(Opc));
2420 MI->getOperand(3).setImm(Size-Amt);
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2421 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2422 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2423 case X86::BLENDPDrri:
2424 case X86::BLENDPSrri:
2425 case X86::PBLENDWrri:
2426 case X86::VBLENDPDrri:
2427 case X86::VBLENDPSrri:
2428 case X86::VBLENDPDYrri:
2429 case X86::VBLENDPSYrri:
2430 case X86::VPBLENDDrri:
2431 case X86::VPBLENDWrri:
2432 case X86::VPBLENDDYrri:
2433 case X86::VPBLENDWYrri:{
2434 unsigned Mask;
2435 switch (MI->getOpcode()) {
2436 default: llvm_unreachable("Unreachable!");
2437 case X86::BLENDPDrri: Mask = 0x03; break;
2438 case X86::BLENDPSrri: Mask = 0x0F; break;
2439 case X86::PBLENDWrri: Mask = 0xFF; break;
2440 case X86::VBLENDPDrri: Mask = 0x03; break;
2441 case X86::VBLENDPSrri: Mask = 0x0F; break;
2442 case X86::VBLENDPDYrri: Mask = 0x0F; break;
2443 case X86::VBLENDPSYrri: Mask = 0xFF; break;
2444 case X86::VPBLENDDrri: Mask = 0x0F; break;
2445 case X86::VPBLENDWrri: Mask = 0xFF; break;
2446 case X86::VPBLENDDYrri: Mask = 0xFF; break;
2447 case X86::VPBLENDWYrri: Mask = 0xFF; break;
2448 }
2449 unsigned Imm = MI->getOperand(3).getImm();
2450 if (NewMI) {
2451 MachineFunction &MF = *MI->getParent()->getParent();
2452 MI = MF.CloneMachineInstr(MI);
2453 NewMI = false;
2454 }
2455 MI->getOperand(3).setImm(Mask ^ Imm);
2456 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2457 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2458 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2459 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2460 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2461 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2462 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2463 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2464 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2465 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2466 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2467 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2468 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2469 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2470 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2471 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2472 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2473 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2474 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2475 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2476 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2477 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2478 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2479 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2480 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2481 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2482 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2483 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2484 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2485 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2486 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2487 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2488 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]2489 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2490 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2491 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2492 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2493 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2494 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2495 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2496 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2497 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2498 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2499 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2500 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2501 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2502 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2503 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2504 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2505 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2506 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2507 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2508 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2509 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2510 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2511 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2512 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2513 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2514 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2515 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2516 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2517 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2518 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2519 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2520 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2521 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2522 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2523 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2524 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2525 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2526 if (NewMI) {
2527 MachineFunction &MF = *MI->getParent()->getParent();
2528 MI = MF.CloneMachineInstr(MI);
2529 NewMI = false;
2530 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]2531 MI->setDesc(get(Opc));
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2532 // Fallthrough intended.
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2533 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2534 default:
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2535 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2536 }
2537}
2538
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2539bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2540 unsigned &SrcOpIdx2) const {
2541 switch (MI->getOpcode()) {
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2542 case X86::BLENDPDrri:
2543 case X86::BLENDPSrri:
2544 case X86::PBLENDWrri:
2545 case X86::VBLENDPDrri:
2546 case X86::VBLENDPSrri:
2547 case X86::VBLENDPDYrri:
2548 case X86::VBLENDPSYrri:
2549 case X86::VPBLENDDrri:
2550 case X86::VPBLENDDYrri:
2551 case X86::VPBLENDWrri:
2552 case X86::VPBLENDWYrri:
2553 SrcOpIdx1 = 1;
2554 SrcOpIdx2 = 2;
2555 return true;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2556 case X86::VFMADDPDr231r:
2557 case X86::VFMADDPSr231r:
2558 case X86::VFMADDSDr231r:
2559 case X86::VFMADDSSr231r:
2560 case X86::VFMSUBPDr231r:
2561 case X86::VFMSUBPSr231r:
2562 case X86::VFMSUBSDr231r:
2563 case X86::VFMSUBSSr231r:
2564 case X86::VFNMADDPDr231r:
2565 case X86::VFNMADDPSr231r:
2566 case X86::VFNMADDSDr231r:
2567 case X86::VFNMADDSSr231r:
2568 case X86::VFNMSUBPDr231r:
2569 case X86::VFNMSUBPSr231r:
2570 case X86::VFNMSUBSDr231r:
2571 case X86::VFNMSUBSSr231r:
2572 case X86::VFMADDPDr231rY:
2573 case X86::VFMADDPSr231rY:
2574 case X86::VFMSUBPDr231rY:
2575 case X86::VFMSUBPSr231rY:
2576 case X86::VFNMADDPDr231rY:
2577 case X86::VFNMADDPSr231rY:
2578 case X86::VFNMSUBPDr231rY:
2579 case X86::VFNMSUBPSr231rY:
2580 SrcOpIdx1 = 2;
2581 SrcOpIdx2 = 3;
2582 return true;
2583 default:
2584 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2585 }
2586}
2587
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2588static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2589 switch (BrOpc) {
2590 default: return X86::COND_INVALID;
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2591 case X86::JE_4: return X86::COND_E;
2592 case X86::JNE_4: return X86::COND_NE;
2593 case X86::JL_4: return X86::COND_L;
2594 case X86::JLE_4: return X86::COND_LE;
2595 case X86::JG_4: return X86::COND_G;
2596 case X86::JGE_4: return X86::COND_GE;
2597 case X86::JB_4: return X86::COND_B;
2598 case X86::JBE_4: return X86::COND_BE;
2599 case X86::JA_4: return X86::COND_A;
2600 case X86::JAE_4: return X86::COND_AE;
2601 case X86::JS_4: return X86::COND_S;
2602 case X86::JNS_4: return X86::COND_NS;
2603 case X86::JP_4: return X86::COND_P;
2604 case X86::JNP_4: return X86::COND_NP;
2605 case X86::JO_4: return X86::COND_O;
2606 case X86::JNO_4: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2607 }
2608}
2609
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2610/// getCondFromSETOpc - return condition code of a SET opcode.
2611static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2612 switch (Opc) {
2613 default: return X86::COND_INVALID;
2614 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2615 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2616 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2617 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2618 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2619 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2620 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2621 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2622 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2623 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2624 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2625 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2626 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2627 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2628 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2629 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2630 }
2631}
2632
2633/// getCondFromCmovOpc - return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]2634X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2635 switch (Opc) {
2636 default: return X86::COND_INVALID;
2637 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2638 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2639 return X86::COND_A;
2640 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2641 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2642 return X86::COND_AE;
2643 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2644 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2645 return X86::COND_B;
2646 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2647 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2648 return X86::COND_BE;
2649 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2650 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2651 return X86::COND_E;
2652 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2653 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2654 return X86::COND_G;
2655 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2656 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2657 return X86::COND_GE;
2658 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2659 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2660 return X86::COND_L;
2661 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2662 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2663 return X86::COND_LE;
2664 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2665 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2666 return X86::COND_NE;
2667 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2668 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2669 return X86::COND_NO;
2670 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2671 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2672 return X86::COND_NP;
2673 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2674 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2675 return X86::COND_NS;
2676 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2677 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2678 return X86::COND_O;
2679 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2680 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2681 return X86::COND_P;
2682 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2683 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2684 return X86::COND_S;
2685 }
2686}
2687
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2688unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2689 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2690 default: llvm_unreachable("Illegal condition code!");
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2691 case X86::COND_E: return X86::JE_4;
2692 case X86::COND_NE: return X86::JNE_4;
2693 case X86::COND_L: return X86::JL_4;
2694 case X86::COND_LE: return X86::JLE_4;
2695 case X86::COND_G: return X86::JG_4;
2696 case X86::COND_GE: return X86::JGE_4;
2697 case X86::COND_B: return X86::JB_4;
2698 case X86::COND_BE: return X86::JBE_4;
2699 case X86::COND_A: return X86::JA_4;
2700 case X86::COND_AE: return X86::JAE_4;
2701 case X86::COND_S: return X86::JS_4;
2702 case X86::COND_NS: return X86::JNS_4;
2703 case X86::COND_P: return X86::JP_4;
2704 case X86::COND_NP: return X86::JNP_4;
2705 case X86::COND_O: return X86::JO_4;
2706 case X86::COND_NO: return X86::JNO_4;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2707 }
2708}
2709
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2710/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2711/// e.g. turning COND_E to COND_NE.
2712X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2713 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2714 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2715 case X86::COND_E: return X86::COND_NE;
2716 case X86::COND_NE: return X86::COND_E;
2717 case X86::COND_L: return X86::COND_GE;
2718 case X86::COND_LE: return X86::COND_G;
2719 case X86::COND_G: return X86::COND_LE;
2720 case X86::COND_GE: return X86::COND_L;
2721 case X86::COND_B: return X86::COND_AE;
2722 case X86::COND_BE: return X86::COND_A;
2723 case X86::COND_A: return X86::COND_BE;
2724 case X86::COND_AE: return X86::COND_B;
2725 case X86::COND_S: return X86::COND_NS;
2726 case X86::COND_NS: return X86::COND_S;
2727 case X86::COND_P: return X86::COND_NP;
2728 case X86::COND_NP: return X86::COND_P;
2729 case X86::COND_O: return X86::COND_NO;
2730 case X86::COND_NO: return X86::COND_O;
2731 }
2732}
2733
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2734/// getSwappedCondition - assume the flags are set by MI(a,b), return
2735/// the condition code if we modify the instructions such that flags are
2736/// set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]2737static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2738 switch (CC) {
2739 default: return X86::COND_INVALID;
2740 case X86::COND_E: return X86::COND_E;
2741 case X86::COND_NE: return X86::COND_NE;
2742 case X86::COND_L: return X86::COND_G;
2743 case X86::COND_LE: return X86::COND_GE;
2744 case X86::COND_G: return X86::COND_L;
2745 case X86::COND_GE: return X86::COND_LE;
2746 case X86::COND_B: return X86::COND_A;
2747 case X86::COND_BE: return X86::COND_AE;
2748 case X86::COND_A: return X86::COND_B;
2749 case X86::COND_AE: return X86::COND_BE;
2750 }
2751}
2752
2753/// getSETFromCond - Return a set opcode for the given condition and
2754/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]2755unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]2756 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2757 { X86::SETAr, X86::SETAm },
2758 { X86::SETAEr, X86::SETAEm },
2759 { X86::SETBr, X86::SETBm },
2760 { X86::SETBEr, X86::SETBEm },
2761 { X86::SETEr, X86::SETEm },
2762 { X86::SETGr, X86::SETGm },
2763 { X86::SETGEr, X86::SETGEm },
2764 { X86::SETLr, X86::SETLm },
2765 { X86::SETLEr, X86::SETLEm },
2766 { X86::SETNEr, X86::SETNEm },
2767 { X86::SETNOr, X86::SETNOm },
2768 { X86::SETNPr, X86::SETNPm },
2769 { X86::SETNSr, X86::SETNSm },
2770 { X86::SETOr, X86::SETOm },
2771 { X86::SETPr, X86::SETPm },
2772 { X86::SETSr, X86::SETSm }
2773 };
2774
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]2775 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2776 return Opc[CC][HasMemoryOperand ? 1 : 0];
2777}
2778
2779/// getCMovFromCond - Return a cmov opcode for the given condition,
2780/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]2781unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2782 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]2783 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2784 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2785 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2786 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2787 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2788 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2789 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2790 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2791 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2792 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2793 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2794 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2795 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2796 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2797 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2798 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2799 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2800 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2801 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2802 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2803 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2804 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2805 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2806 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2807 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2808 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2809 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2810 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2811 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2812 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2813 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2814 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2815 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2816 };
2817
2818 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2819 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2820 switch(RegBytes) {
2821 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2822 case 2: return Opc[Idx][0];
2823 case 4: return Opc[Idx][1];
2824 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2825 }
2826}
2827
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]2828bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2829 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2830
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2831 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2832 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2833 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2834 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2835 return true;
2836 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]2837}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2838
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2839bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2840 MachineBasicBlock *&TBB,
2841 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2842 SmallVectorImpl<MachineOperand> &Cond,
2843 bool AllowModify) const {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2844 // Start from the bottom of the block and work up, examining the
2845 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2846 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2847 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2848 while (I != MBB.begin()) {
2849 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]2850 if (I->isDebugValue())
2851 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2852
2853 // Working from the bottom, when we see a non-terminator instruction, we're
2854 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]2855 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2856 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2857
2858 // A terminator that isn't a branch can't easily be handled by this
2859 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2860 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2861 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2862
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2863 // Handle unconditional branches.
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2864 if (I->getOpcode() == X86::JMP_4) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2865 UnCondBrIter = I;
2866
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2867 if (!AllowModify) {
2868 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]2869 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2870 }
2871
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2872 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2873 while (std::next(I) != MBB.end())
2874 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2875
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2876 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2877 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2878
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2879 // Delete the JMP if it's equivalent to a fall-through.
2880 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2881 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2882 I->eraseFromParent();
2883 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2884 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2885 continue;
2886 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2887
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2888 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2889 TBB = I->getOperand(0).getMBB();
2890 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2891 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2892
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2893 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2894 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2895 if (BranchCode == X86::COND_INVALID)
2896 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2897
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2898 // Working from the bottom, handle the first conditional branch.
2899 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2900 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2901 if (AllowModify && UnCondBrIter != MBB.end() &&
2902 MBB.isLayoutSuccessor(TargetBB)) {
2903 // If we can modify the code and it ends in something like:
2904 //
2905 // jCC L1
2906 // jmp L2
2907 // L1:
2908 // ...
2909 // L2:
2910 //
2911 // Then we can change this to:
2912 //
2913 // jnCC L2
2914 // L1:
2915 // ...
2916 // L2:
2917 //
2918 // Which is a bit more efficient.
2919 // We conditionally jump to the fall-through block.
2920 BranchCode = GetOppositeBranchCondition(BranchCode);
2921 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2922 MachineBasicBlock::iterator OldInst = I;
2923
2924 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2925 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2926 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2927 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2928
2929 OldInst->eraseFromParent();
2930 UnCondBrIter->eraseFromParent();
2931
2932 // Restart the analysis.
2933 UnCondBrIter = MBB.end();
2934 I = MBB.end();
2935 continue;
2936 }
2937
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2938 FBB = TBB;
2939 TBB = I->getOperand(0).getMBB();
2940 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2941 continue;
2942 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2943
2944 // Handle subsequent conditional branches. Only handle the case where all
2945 // conditional branches branch to the same destination and their condition
2946 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2947 assert(Cond.size() == 1);
2948 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2949
2950 // Only handle the case where all conditional branches branch to the same
2951 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2952 if (TBB != I->getOperand(0).getMBB())
2953 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2954
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2955 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2956 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2957 if (OldBranchCode == BranchCode)
2958 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2959
2960 // If they differ, see if they fit one of the known patterns. Theoretically,
2961 // we could handle more patterns here, but we shouldn't expect to see them
2962 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2963 if ((OldBranchCode == X86::COND_NP &&
2964 BranchCode == X86::COND_E) ||
2965 (OldBranchCode == X86::COND_E &&
2966 BranchCode == X86::COND_NP))
2967 BranchCode = X86::COND_NP_OR_E;
2968 else if ((OldBranchCode == X86::COND_P &&
2969 BranchCode == X86::COND_NE) ||
2970 (OldBranchCode == X86::COND_NE &&
2971 BranchCode == X86::COND_P))
2972 BranchCode = X86::COND_NE_OR_P;
2973 else
2974 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2975
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2976 // Update the MachineOperand.
2977 Cond[0].setImm(BranchCode);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]2978 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2979
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2980 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2981}
2982
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2983unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2984 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2985 unsigned Count = 0;
2986
2987 while (I != MBB.begin()) {
2988 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]2989 if (I->isDebugValue())
2990 continue;
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2991 if (I->getOpcode() != X86::JMP_4 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2992 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2993 break;
2994 // Remove the branch.
2995 I->eraseFromParent();
2996 I = MBB.end();
2997 ++Count;
2998 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2999
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3000 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3001}
3002
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3003unsigned
3004X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3005 MachineBasicBlock *FBB,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3006 const SmallVectorImpl<MachineOperand> &Cond,
3007 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3008 // Shouldn't be a fall through.
3009 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]3010 assert((Cond.size() == 1 || Cond.size() == 0) &&
3011 "X86 branch conditions have one component!");
3012
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3013 if (Cond.empty()) {
3014 // Unconditional branch?
3015 assert(!FBB && "Unconditional branch with multiple successors!");
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3016 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3017 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3018 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3019
3020 // Conditional branch.
3021 unsigned Count = 0;
3022 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3023 switch (CC) {
3024 case X86::COND_NP_OR_E:
3025 // Synthesize NP_OR_E with two branches.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3026 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3027 ++Count;
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3028 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3029 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3030 break;
3031 case X86::COND_NE_OR_P:
3032 // Synthesize NE_OR_P with two branches.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3033 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3034 ++Count;
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3035 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3036 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3037 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3038 default: {
3039 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3040 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3041 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3042 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3043 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3044 if (FBB) {
3045 // Two-way Conditional branch. Insert the second branch.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3046 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3047 ++Count;
3048 }
3049 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3050}
3051
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3052bool X86InstrInfo::
3053canInsertSelect(const MachineBasicBlock &MBB,
3054 const SmallVectorImpl<MachineOperand> &Cond,
3055 unsigned TrueReg, unsigned FalseReg,
3056 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3057 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3058 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3059 return false;
3060 if (Cond.size() != 1)
3061 return false;
3062 // We cannot do the composite conditions, at least not in SSA form.
3063 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3064 return false;
3065
3066 // Check register classes.
3067 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3068 const TargetRegisterClass *RC =
3069 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3070 if (!RC)
3071 return false;
3072
3073 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3074 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3075 X86::GR32RegClass.hasSubClassEq(RC) ||
3076 X86::GR64RegClass.hasSubClassEq(RC)) {
3077 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3078 // Bridge. Probably Ivy Bridge as well.
3079 CondCycles = 2;
3080 TrueCycles = 2;
3081 FalseCycles = 2;
3082 return true;
3083 }
3084
3085 // Can't do vectors.
3086 return false;
3087}
3088
3089void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3090 MachineBasicBlock::iterator I, DebugLoc DL,
3091 unsigned DstReg,
3092 const SmallVectorImpl<MachineOperand> &Cond,
3093 unsigned TrueReg, unsigned FalseReg) const {
3094 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3095 assert(Cond.size() == 1 && "Invalid Cond array");
3096 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3097 MRI.getRegClass(DstReg)->getSize(),
3098 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3099 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3100}
3101
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3102/// isHReg - Test if the given register is a physical h register.
3103static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3104 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3105}
3106
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3107// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3108static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3109 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3110
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3111 // SrcReg(VR128) -> DestReg(GR64)
3112 // SrcReg(VR64) -> DestReg(GR64)
3113 // SrcReg(GR64) -> DestReg(VR128)
3114 // SrcReg(GR64) -> DestReg(VR64)
3115
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3116 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3117 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3118 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3119 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3120 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3121 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3122 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3123 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3124 // Copy from a VR64 register to a GR64 register.
3125 return X86::MOVSDto64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3126 } else if (X86::GR64RegClass.contains(SrcReg)) {
3127 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3128 if (X86::VR128XRegClass.contains(DestReg))
3129 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3130 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3131 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3132 if (X86::VR64RegClass.contains(DestReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3133 return X86::MOV64toSDrr;
3134 }
3135
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3136 // SrcReg(FR32) -> DestReg(GR32)
3137 // SrcReg(GR32) -> DestReg(FR32)
3138
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3139 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3140 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3141 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3142
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3143 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3144 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3145 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3146 return 0;
3147}
3148
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3149inline static bool MaskRegClassContains(unsigned Reg) {
3150 return X86::VK8RegClass.contains(Reg) ||
3151 X86::VK16RegClass.contains(Reg) ||
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]3152 X86::VK32RegClass.contains(Reg) ||
3153 X86::VK64RegClass.contains(Reg) ||
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3154 X86::VK1RegClass.contains(Reg);
3155}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3156static
3157unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3158 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3159 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3160 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3161 DestReg = get512BitSuperRegister(DestReg);
3162 SrcReg = get512BitSuperRegister(SrcReg);
3163 return X86::VMOVAPSZrr;
3164 }
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3165 if (MaskRegClassContains(DestReg) &&
3166 MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3167 return X86::KMOVWkk;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3168 if (MaskRegClassContains(DestReg) &&
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3169 (X86::GR32RegClass.contains(SrcReg) ||
3170 X86::GR16RegClass.contains(SrcReg) ||
3171 X86::GR8RegClass.contains(SrcReg))) {
3172 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3173 return X86::KMOVWkr;
3174 }
3175 if ((X86::GR32RegClass.contains(DestReg) ||
3176 X86::GR16RegClass.contains(DestReg) ||
3177 X86::GR8RegClass.contains(DestReg)) &&
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3178 MaskRegClassContains(SrcReg)) {
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3179 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3180 return X86::KMOVWrk;
3181 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3182 return 0;
3183}
3184
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3185void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3186 MachineBasicBlock::iterator MI, DebugLoc DL,
3187 unsigned DestReg, unsigned SrcReg,
3188 bool KillSrc) const {
3189 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3190 bool HasAVX = Subtarget.hasAVX();
3191 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3192 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3193 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3194 Opc = X86::MOV64rr;
3195 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3196 Opc = X86::MOV32rr;
3197 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3198 Opc = X86::MOV16rr;
3199 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3200 // Copying to or from a physical H register on x86-64 requires a NOREX
3201 // move. Otherwise use a normal move.
3202 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3203 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3204 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]3205 // Both operands must be encodable without an REX prefix.
3206 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3207 "8-bit H register can not be copied outside GR8_NOREX");
3208 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3209 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3210 }
3211 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3212 Opc = X86::MMX_MOVQ64rr;
3213 else if (HasAVX512)
3214 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3215 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3216 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3217 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3218 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3219 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3220 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3221
3222 if (Opc) {
3223 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3224 .addReg(SrcReg, getKillRegState(KillSrc));
3225 return;
3226 }
3227
3228 // Moving EFLAGS to / from another register requires a push and a pop.
Nadav Rotemd5aae982012-12-21 23:48:49 +0000[diff] [blame]3229 // Notice that we have to adjust the stack if we don't want to clobber the
JF Bastienac8b66b2014-08-05 23:27:34 +0000[diff] [blame]3230 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3231 if (SrcReg == X86::EFLAGS) {
3232 if (X86::GR64RegClass.contains(DestReg)) {
3233 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3234 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3235 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3236 }
3237 if (X86::GR32RegClass.contains(DestReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3238 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3239 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3240 return;
3241 }
3242 }
3243 if (DestReg == X86::EFLAGS) {
3244 if (X86::GR64RegClass.contains(SrcReg)) {
3245 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3246 .addReg(SrcReg, getKillRegState(KillSrc));
3247 BuildMI(MBB, MI, DL, get(X86::POPF64));
3248 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3249 }
3250 if (X86::GR32RegClass.contains(SrcReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3251 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3252 .addReg(SrcReg, getKillRegState(KillSrc));
3253 BuildMI(MBB, MI, DL, get(X86::POPF32));
3254 return;
3255 }
3256 }
3257
3258 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3259 << " to " << RI.getName(DestReg) << '\n');
3260 llvm_unreachable("Cannot emit physreg copy instruction");
3261}
3262
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3263static unsigned getLoadStoreRegOpcode(unsigned Reg,
3264 const TargetRegisterClass *RC,
3265 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3266 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3267 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3268 if (STI.hasAVX512()) {
Andrew Trick8460a3b2013-10-14 22:18:56 +0000[diff] [blame]3269 if (X86::VK8RegClass.hasSubClassEq(RC) ||
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3270 X86::VK16RegClass.hasSubClassEq(RC))
3271 return load ? X86::KMOVWkm : X86::KMOVWmk;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3272 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3273 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3274 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3275 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3276 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3277 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3278 }
3279
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3280 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3281 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]3282 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3283 llvm_unreachable("Unknown spill size");
3284 case 1:
3285 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3286 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3287 // Copying to or from a physical H register on x86-64 requires a NOREX
3288 // move. Otherwise use a normal move.
3289 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3290 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3291 return load ? X86::MOV8rm : X86::MOV8mr;
3292 case 2:
3293 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3294 return load ? X86::MOV16rm : X86::MOV16mr;
3295 case 4:
3296 if (X86::GR32RegClass.hasSubClassEq(RC))
3297 return load ? X86::MOV32rm : X86::MOV32mr;
3298 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3299 return load ?
3300 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3301 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3302 if (X86::RFP32RegClass.hasSubClassEq(RC))
3303 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3304 llvm_unreachable("Unknown 4-byte regclass");
3305 case 8:
3306 if (X86::GR64RegClass.hasSubClassEq(RC))
3307 return load ? X86::MOV64rm : X86::MOV64mr;
3308 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3309 return load ?
3310 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3311 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3312 if (X86::VR64RegClass.hasSubClassEq(RC))
3313 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3314 if (X86::RFP64RegClass.hasSubClassEq(RC))
3315 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3316 llvm_unreachable("Unknown 8-byte regclass");
3317 case 10:
3318 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3319 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3320 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3321 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3322 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3323 // If stack is realigned we can use aligned stores.
3324 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3325 return load ?
3326 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3327 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3328 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3329 return load ?
3330 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3331 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3332 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3333 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3334 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3335 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3336 // If stack is realigned we can use aligned stores.
3337 if (isStackAligned)
3338 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3339 else
3340 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3341 case 64:
3342 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3343 if (isStackAligned)
3344 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3345 else
3346 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3347 }
3348}
3349
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3350static unsigned getStoreRegOpcode(unsigned SrcReg,
3351 const TargetRegisterClass *RC,
3352 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3353 const X86Subtarget &STI) {
3354 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3355}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3356
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3357
3358static unsigned getLoadRegOpcode(unsigned DestReg,
3359 const TargetRegisterClass *RC,
3360 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3361 const X86Subtarget &STI) {
3362 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3363}
3364
3365void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3366 MachineBasicBlock::iterator MI,
3367 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3368 const TargetRegisterClass *RC,
3369 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3370 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]3371 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3372 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3373 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]3374 bool isAligned = (MF.getTarget()
3375 .getSubtargetImpl()
3376 ->getFrameLowering()
3377 ->getStackAlignment() >= Alignment) ||
3378 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3379 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3380 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3381 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3382 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3383}
3384
3385void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3386 bool isKill,
3387 SmallVectorImpl<MachineOperand> &Addr,
3388 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3389 MachineInstr::mmo_iterator MMOBegin,
3390 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3391 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3392 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3393 bool isAligned = MMOBegin != MMOEnd &&
3394 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3395 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3396 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3397 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3398 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3399 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3400 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3401 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3402 NewMIs.push_back(MIB);
3403}
3404
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3405
3406void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3407 MachineBasicBlock::iterator MI,
3408 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3409 const TargetRegisterClass *RC,
3410 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3411 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3412 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]3413 bool isAligned = (MF.getTarget()
3414 .getSubtargetImpl()
3415 ->getFrameLowering()
3416 ->getStackAlignment() >= Alignment) ||
3417 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3418 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3419 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3420 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3421}
3422
3423void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3424 SmallVectorImpl<MachineOperand> &Addr,
3425 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3426 MachineInstr::mmo_iterator MMOBegin,
3427 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3428 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3429 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3430 bool isAligned = MMOBegin != MMOEnd &&
3431 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3432 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3433 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3434 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3435 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3436 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3437 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3438 NewMIs.push_back(MIB);
3439}
3440
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3441bool X86InstrInfo::
3442analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3443 int &CmpMask, int &CmpValue) const {
3444 switch (MI->getOpcode()) {
3445 default: break;
3446 case X86::CMP64ri32:
3447 case X86::CMP64ri8:
3448 case X86::CMP32ri:
3449 case X86::CMP32ri8:
3450 case X86::CMP16ri:
3451 case X86::CMP16ri8:
3452 case X86::CMP8ri:
3453 SrcReg = MI->getOperand(0).getReg();
3454 SrcReg2 = 0;
3455 CmpMask = ~0;
3456 CmpValue = MI->getOperand(1).getImm();
3457 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3458 // A SUB can be used to perform comparison.
3459 case X86::SUB64rm:
3460 case X86::SUB32rm:
3461 case X86::SUB16rm:
3462 case X86::SUB8rm:
3463 SrcReg = MI->getOperand(1).getReg();
3464 SrcReg2 = 0;
3465 CmpMask = ~0;
3466 CmpValue = 0;
3467 return true;
3468 case X86::SUB64rr:
3469 case X86::SUB32rr:
3470 case X86::SUB16rr:
3471 case X86::SUB8rr:
3472 SrcReg = MI->getOperand(1).getReg();
3473 SrcReg2 = MI->getOperand(2).getReg();
3474 CmpMask = ~0;
3475 CmpValue = 0;
3476 return true;
3477 case X86::SUB64ri32:
3478 case X86::SUB64ri8:
3479 case X86::SUB32ri:
3480 case X86::SUB32ri8:
3481 case X86::SUB16ri:
3482 case X86::SUB16ri8:
3483 case X86::SUB8ri:
3484 SrcReg = MI->getOperand(1).getReg();
3485 SrcReg2 = 0;
3486 CmpMask = ~0;
3487 CmpValue = MI->getOperand(2).getImm();
3488 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3489 case X86::CMP64rr:
3490 case X86::CMP32rr:
3491 case X86::CMP16rr:
3492 case X86::CMP8rr:
3493 SrcReg = MI->getOperand(0).getReg();
3494 SrcReg2 = MI->getOperand(1).getReg();
3495 CmpMask = ~0;
3496 CmpValue = 0;
3497 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3498 case X86::TEST8rr:
3499 case X86::TEST16rr:
3500 case X86::TEST32rr:
3501 case X86::TEST64rr:
3502 SrcReg = MI->getOperand(0).getReg();
3503 if (MI->getOperand(1).getReg() != SrcReg) return false;
3504 // Compare against zero.
3505 SrcReg2 = 0;
3506 CmpMask = ~0;
3507 CmpValue = 0;
3508 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3509 }
3510 return false;
3511}
3512
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3513/// isRedundantFlagInstr - check whether the first instruction, whose only
3514/// purpose is to update flags, can be made redundant.
3515/// CMPrr can be made redundant by SUBrr if the operands are the same.
3516/// This function can be extended later on.
3517/// SrcReg, SrcRegs: register operands for FlagI.
3518/// ImmValue: immediate for FlagI if it takes an immediate.
3519inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3520 unsigned SrcReg2, int ImmValue,
3521 MachineInstr *OI) {
3522 if (((FlagI->getOpcode() == X86::CMP64rr &&
3523 OI->getOpcode() == X86::SUB64rr) ||
3524 (FlagI->getOpcode() == X86::CMP32rr &&
3525 OI->getOpcode() == X86::SUB32rr)||
3526 (FlagI->getOpcode() == X86::CMP16rr &&
3527 OI->getOpcode() == X86::SUB16rr)||
3528 (FlagI->getOpcode() == X86::CMP8rr &&
3529 OI->getOpcode() == X86::SUB8rr)) &&
3530 ((OI->getOperand(1).getReg() == SrcReg &&
3531 OI->getOperand(2).getReg() == SrcReg2) ||
3532 (OI->getOperand(1).getReg() == SrcReg2 &&
3533 OI->getOperand(2).getReg() == SrcReg)))
3534 return true;
3535
3536 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3537 OI->getOpcode() == X86::SUB64ri32) ||
3538 (FlagI->getOpcode() == X86::CMP64ri8 &&
3539 OI->getOpcode() == X86::SUB64ri8) ||
3540 (FlagI->getOpcode() == X86::CMP32ri &&
3541 OI->getOpcode() == X86::SUB32ri) ||
3542 (FlagI->getOpcode() == X86::CMP32ri8 &&
3543 OI->getOpcode() == X86::SUB32ri8) ||
3544 (FlagI->getOpcode() == X86::CMP16ri &&
3545 OI->getOpcode() == X86::SUB16ri) ||
3546 (FlagI->getOpcode() == X86::CMP16ri8 &&
3547 OI->getOpcode() == X86::SUB16ri8) ||
3548 (FlagI->getOpcode() == X86::CMP8ri &&
3549 OI->getOpcode() == X86::SUB8ri)) &&
3550 OI->getOperand(1).getReg() == SrcReg &&
3551 OI->getOperand(2).getImm() == ImmValue)
3552 return true;
3553 return false;
3554}
3555
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3556/// isDefConvertible - check whether the definition can be converted
3557/// to remove a comparison against zero.
3558inline static bool isDefConvertible(MachineInstr *MI) {
3559 switch (MI->getOpcode()) {
3560 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3561
3562 // The shift instructions only modify ZF if their shift count is non-zero.
3563 // N.B.: The processor truncates the shift count depending on the encoding.
3564 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3565 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3566 return getTruncatedShiftCount(MI, 2) != 0;
3567
3568 // Some left shift instructions can be turned into LEA instructions but only
3569 // if their flags aren't used. Avoid transforming such instructions.
3570 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3571 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3572 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3573 return ShAmt != 0;
3574 }
3575
3576 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3577 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3578 return getTruncatedShiftCount(MI, 3) != 0;
3579
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3580 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3581 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3582 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3583 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3584 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]3585 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3586 case X86::DEC64_32r: case X86::DEC64_16r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3587 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3588 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3589 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3590 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3591 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]3592 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3593 case X86::INC64_32r: case X86::INC64_16r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3594 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3595 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3596 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3597 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3598 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3599 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3600 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3601 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3602 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3603 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3604 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3605 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3606 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3607 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3608 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]3609 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3610 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3611 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3612 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3613 case X86::ADC32ri: case X86::ADC32ri8:
3614 case X86::ADC32rr: case X86::ADC64ri32:
3615 case X86::ADC64ri8: case X86::ADC64rr:
3616 case X86::SBB32ri: case X86::SBB32ri8:
3617 case X86::SBB32rr: case X86::SBB64ri32:
3618 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]3619 case X86::ANDN32rr: case X86::ANDN32rm:
3620 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]3621 case X86::BEXTR32rr: case X86::BEXTR64rr:
3622 case X86::BEXTR32rm: case X86::BEXTR64rm:
3623 case X86::BLSI32rr: case X86::BLSI32rm:
3624 case X86::BLSI64rr: case X86::BLSI64rm:
3625 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3626 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3627 case X86::BLSR32rr: case X86::BLSR32rm:
3628 case X86::BLSR64rr: case X86::BLSR64rm:
3629 case X86::BZHI32rr: case X86::BZHI32rm:
3630 case X86::BZHI64rr: case X86::BZHI64rm:
3631 case X86::LZCNT16rr: case X86::LZCNT16rm:
3632 case X86::LZCNT32rr: case X86::LZCNT32rm:
3633 case X86::LZCNT64rr: case X86::LZCNT64rm:
3634 case X86::POPCNT16rr:case X86::POPCNT16rm:
3635 case X86::POPCNT32rr:case X86::POPCNT32rm:
3636 case X86::POPCNT64rr:case X86::POPCNT64rm:
3637 case X86::TZCNT16rr: case X86::TZCNT16rm:
3638 case X86::TZCNT32rr: case X86::TZCNT32rm:
3639 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3640 return true;
3641 }
3642}
3643
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3644/// isUseDefConvertible - check whether the use can be converted
3645/// to remove a comparison against zero.
3646static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3647 switch (MI->getOpcode()) {
3648 default: return X86::COND_INVALID;
3649 case X86::LZCNT16rr: case X86::LZCNT16rm:
3650 case X86::LZCNT32rr: case X86::LZCNT32rm:
3651 case X86::LZCNT64rr: case X86::LZCNT64rm:
3652 return X86::COND_B;
3653 case X86::POPCNT16rr:case X86::POPCNT16rm:
3654 case X86::POPCNT32rr:case X86::POPCNT32rm:
3655 case X86::POPCNT64rr:case X86::POPCNT64rm:
3656 return X86::COND_E;
3657 case X86::TZCNT16rr: case X86::TZCNT16rm:
3658 case X86::TZCNT32rr: case X86::TZCNT32rm:
3659 case X86::TZCNT64rr: case X86::TZCNT64rm:
3660 return X86::COND_B;
3661 }
3662}
3663
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3664/// optimizeCompareInstr - Check if there exists an earlier instruction that
3665/// operates on the same source operands and sets flags in the same way as
3666/// Compare; remove Compare if possible.
3667bool X86InstrInfo::
3668optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3669 int CmpMask, int CmpValue,
3670 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3671 // Check whether we can replace SUB with CMP.
3672 unsigned NewOpcode = 0;
3673 switch (CmpInstr->getOpcode()) {
3674 default: break;
3675 case X86::SUB64ri32:
3676 case X86::SUB64ri8:
3677 case X86::SUB32ri:
3678 case X86::SUB32ri8:
3679 case X86::SUB16ri:
3680 case X86::SUB16ri8:
3681 case X86::SUB8ri:
3682 case X86::SUB64rm:
3683 case X86::SUB32rm:
3684 case X86::SUB16rm:
3685 case X86::SUB8rm:
3686 case X86::SUB64rr:
3687 case X86::SUB32rr:
3688 case X86::SUB16rr:
3689 case X86::SUB8rr: {
3690 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3691 return false;
3692 // There is no use of the destination register, we can replace SUB with CMP.
3693 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]3694 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3695 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3696 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3697 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3698 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3699 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3700 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3701 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3702 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3703 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3704 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3705 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3706 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3707 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3708 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3709 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3710 }
3711 CmpInstr->setDesc(get(NewOpcode));
3712 CmpInstr->RemoveOperand(0);
3713 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3714 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3715 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3716 return false;
3717 }
3718 }
3719
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3720 // Get the unique definition of SrcReg.
3721 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3722 if (!MI) return false;
3723
3724 // CmpInstr is the first instruction of the BB.
3725 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3726
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3727 // If we are comparing against zero, check whether we can use MI to update
3728 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3729 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3730 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3731 return false;
3732
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3733 // If we have a use of the source register between the def and our compare
3734 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3735 // right way.
3736 bool ShouldUpdateCC = false;
3737 X86::CondCode NewCC = X86::COND_INVALID;
3738 if (IsCmpZero && !isDefConvertible(MI)) {
3739 // Scan forward from the use until we hit the use we're looking for or the
3740 // compare instruction.
3741 for (MachineBasicBlock::iterator J = MI;; ++J) {
3742 // Do we have a convertible instruction?
3743 NewCC = isUseDefConvertible(J);
3744 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3745 J->getOperand(1).getReg() == SrcReg) {
3746 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3747 ShouldUpdateCC = true; // Update CC later on.
3748 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3749 // with the new def.
3750 MI = Def = J;
3751 break;
3752 }
3753
3754 if (J == I)
3755 return false;
3756 }
3757 }
3758
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3759 // We are searching for an earlier instruction that can make CmpInstr
3760 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3761 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3762 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3763
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3764 // We iterate backward, starting from the instruction before CmpInstr and
3765 // stop when reaching the definition of a source register or done with the BB.
3766 // RI points to the instruction before CmpInstr.
3767 // If the definition is in this basic block, RE points to the definition;
3768 // otherwise, RE is the rend of the basic block.
3769 MachineBasicBlock::reverse_iterator
3770 RI = MachineBasicBlock::reverse_iterator(I),
3771 RE = CmpInstr->getParent() == MI->getParent() ?
3772 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3773 CmpInstr->getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3774 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3775 for (; RI != RE; ++RI) {
3776 MachineInstr *Instr = &*RI;
3777 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3778 if (!IsCmpZero &&
3779 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3780 Sub = Instr;
3781 break;
3782 }
3783
3784 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3785 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3786 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3787
3788 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3789 // They are safe to move up, if the definition to EFLAGS is dead and
3790 // earlier instructions do not read or write EFLAGS.
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]3791 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3792 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3793 Movr0Inst = Instr;
3794 continue;
3795 }
3796
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3797 // We can't remove CmpInstr.
3798 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3799 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3800 }
3801
3802 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3803 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3804 return false;
3805
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3806 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3807 Sub->getOperand(2).getReg() == SrcReg);
3808
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3809 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3810 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3811 // If we are done with the basic block, we need to check whether EFLAGS is
3812 // live-out.
3813 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3814 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3815 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3816 for (++I; I != E; ++I) {
3817 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3818 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3819 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3820 // We should check the usage if this instruction uses and updates EFLAGS.
3821 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3822 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3823 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3824 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3825 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3826 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3827 continue;
3828
3829 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]3830 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3831 bool OpcIsSET = false;
3832 if (IsCmpZero || IsSwapped) {
3833 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3834 if (Instr.isBranch())
3835 OldCC = getCondFromBranchOpc(Instr.getOpcode());
3836 else {
3837 OldCC = getCondFromSETOpc(Instr.getOpcode());
3838 if (OldCC != X86::COND_INVALID)
3839 OpcIsSET = true;
3840 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3841 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3842 }
3843 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3844 }
3845 if (IsCmpZero) {
3846 switch (OldCC) {
3847 default: break;
3848 case X86::COND_A: case X86::COND_AE:
3849 case X86::COND_B: case X86::COND_BE:
3850 case X86::COND_G: case X86::COND_GE:
3851 case X86::COND_L: case X86::COND_LE:
3852 case X86::COND_O: case X86::COND_NO:
3853 // CF and OF are used, we can't perform this optimization.
3854 return false;
3855 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3856
3857 // If we're updating the condition code check if we have to reverse the
3858 // condition.
3859 if (ShouldUpdateCC)
3860 switch (OldCC) {
3861 default:
3862 return false;
3863 case X86::COND_E:
3864 break;
3865 case X86::COND_NE:
3866 NewCC = GetOppositeBranchCondition(NewCC);
3867 break;
3868 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3869 } else if (IsSwapped) {
3870 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3871 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3872 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3873 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3874 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3875 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3876
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3877 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3878 // Synthesize the new opcode.
3879 bool HasMemoryOperand = Instr.hasOneMemOperand();
3880 unsigned NewOpc;
3881 if (Instr.isBranch())
3882 NewOpc = GetCondBranchFromCond(NewCC);
3883 else if(OpcIsSET)
3884 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3885 else {
3886 unsigned DstReg = Instr.getOperand(0).getReg();
3887 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3888 HasMemoryOperand);
3889 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3890
3891 // Push the MachineInstr to OpsToUpdate.
3892 // If it is safe to remove CmpInstr, the condition code of these
3893 // instructions will be modified.
3894 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3895 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3896 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3897 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3898 IsSafe = true;
3899 break;
3900 }
3901 }
3902
3903 // If EFLAGS is not killed nor re-defined, we should check whether it is
3904 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3905 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3906 MachineBasicBlock *MBB = CmpInstr->getParent();
3907 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3908 SE = MBB->succ_end(); SI != SE; ++SI)
3909 if ((*SI)->isLiveIn(X86::EFLAGS))
3910 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3911 }
3912
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3913 // The instruction to be updated is either Sub or MI.
3914 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]3915 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3916 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]3917 // Look backwards until we find a def that doesn't use the current EFLAGS.
3918 Def = Sub;
3919 MachineBasicBlock::reverse_iterator
3920 InsertI = MachineBasicBlock::reverse_iterator(++Def),
3921 InsertE = Sub->getParent()->rend();
3922 for (; InsertI != InsertE; ++InsertI) {
3923 MachineInstr *Instr = &*InsertI;
3924 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3925 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3926 Sub->getParent()->remove(Movr0Inst);
3927 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3928 Movr0Inst);
3929 break;
3930 }
3931 }
3932 if (InsertI == InsertE)
3933 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3934 }
3935
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3936 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]3937 unsigned i = 0, e = Sub->getNumOperands();
3938 for (; i != e; ++i) {
3939 MachineOperand &MO = Sub->getOperand(i);
3940 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3941 MO.setIsDead(false);
3942 break;
3943 }
3944 }
3945 assert(i != e && "Unable to locate a def EFLAGS operand");
3946
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3947 CmpInstr->eraseFromParent();
3948
3949 // Modify the condition code of instructions in OpsToUpdate.
3950 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3951 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3952 return true;
3953}
3954
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3955/// optimizeLoadInstr - Try to remove the load by folding it to a register
3956/// operand at the use. We fold the load instructions if load defines a virtual
3957/// register, the virtual register is used once in the same BB, and the
3958/// instructions in-between do not load or store, and have no side effects.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]3959MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
3960 const MachineRegisterInfo *MRI,
3961 unsigned &FoldAsLoadDefReg,
3962 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3963 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3964 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3965 // To be conservative, if there exists another load, clear the load candidate.
3966 if (MI->mayLoad()) {
3967 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3968 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3969 }
3970
3971 // Check whether we can move DefMI here.
3972 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3973 assert(DefMI);
3974 bool SawStore = false;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3975 if (!DefMI->isSafeToMove(this, nullptr, SawStore))
3976 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3977
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]3978 // Collect information about virtual register operands of MI.
3979 unsigned SrcOperandId = 0;
3980 bool FoundSrcOperand = false;
3981 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3982 MachineOperand &MO = MI->getOperand(i);
3983 if (!MO.isReg())
3984 continue;
3985 unsigned Reg = MO.getReg();
3986 if (Reg != FoldAsLoadDefReg)
3987 continue;
3988 // Do not fold if we have a subreg use or a def or multiple uses.
3989 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3990 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3991
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]3992 SrcOperandId = i;
3993 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3994 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]3995 if (!FoundSrcOperand)
3996 return nullptr;
3997
3998 // Check whether we can fold the def into SrcOperandId.
3999 SmallVector<unsigned, 8> Ops;
4000 Ops.push_back(SrcOperandId);
4001 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4002 if (FoldMI) {
4003 FoldAsLoadDefReg = 0;
4004 return FoldMI;
4005 }
4006
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4007 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4008}
4009
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4010/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
4011/// instruction with two undef reads of the register being defined. This is
4012/// used for mapping:
4013/// %xmm4 = V_SET0
4014/// to:
4015/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4016///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4017static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4018 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4019 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4020 unsigned Reg = MIB->getOperand(0).getReg();
4021 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4022
4023 // MachineInstr::addOperand() will insert explicit operands before any
4024 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4025 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4026 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4027 assert(MIB->getOperand(1).getReg() == Reg &&
4028 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4029 return true;
4030}
4031
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4032// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4033// code sequence is needed for other targets.
4034static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4035 const TargetInstrInfo &TII) {
4036 MachineBasicBlock &MBB = *MIB->getParent();
4037 DebugLoc DL = MIB->getDebugLoc();
4038 unsigned Reg = MIB->getOperand(0).getReg();
4039 const GlobalValue *GV =
4040 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4041 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4042 MachineMemOperand *MMO = MBB.getParent()->
4043 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]4044 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4045
4046 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4047 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4048 .addMemOperand(MMO);
4049 MIB->setDebugLoc(DL);
4050 MIB->setDesc(TII.get(X86::MOV64rm));
4051 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4052}
4053
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4054bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4055 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4056 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4057 switch (MI->getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]4058 case X86::MOV32r0:
4059 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4060 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4061 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4062 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4063 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4064 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4065 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4066 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4067 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4068 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4069 case X86::FsFLD0SS:
4070 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4071 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4072 case X86::AVX_SET0:
4073 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4074 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4075 case X86::AVX512_512_SET0:
4076 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4077 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4078 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4079 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4080 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]4081 case X86::TEST8ri_NOREX:
4082 MI->setDesc(get(X86::TEST8ri));
4083 return true;
Elena Demikhovsky8fae5652014-03-06 08:15:35 +0000[diff] [blame]4084 case X86::KSET0B:
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4085 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4086 case X86::KSET1B:
4087 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4088 case TargetOpcode::LOAD_STACK_GUARD:
4089 expandLoadStackGuard(MIB, *this);
4090 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4091 }
4092 return false;
4093}
4094
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4095static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4096 const SmallVectorImpl<MachineOperand> &MOs,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4097 MachineInstr *MI,
4098 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4099 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4100 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4101 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4102 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4103 MachineInstrBuilder MIB(MF, NewMI);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4104 unsigned NumAddrOps = MOs.size();
4105 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4106 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4107 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4108 addOffset(MIB, 0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4109
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4110 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4111 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4112 for (unsigned i = 0; i != NumOps; ++i) {
4113 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4114 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4115 }
4116 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4117 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4118 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4119 }
4120 return MIB;
4121}
4122
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4123static MachineInstr *FuseInst(MachineFunction &MF,
4124 unsigned Opcode, unsigned OpNo,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4125 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4126 MachineInstr *MI, const TargetInstrInfo &TII) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4127 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4128 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4129 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4130 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4131
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4132 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4133 MachineOperand &MO = MI->getOperand(i);
4134 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4135 assert(MO.isReg() && "Expected to fold into reg operand!");
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4136 unsigned NumAddrOps = MOs.size();
4137 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4138 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4139 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4140 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4141 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4142 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4143 }
4144 }
4145 return MIB;
4146}
4147
4148static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4149 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4150 MachineInstr *MI) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4151 MachineFunction &MF = *MI->getParent()->getParent();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4152 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4153
4154 unsigned NumAddrOps = MOs.size();
4155 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4156 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4157 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4158 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4159 return MIB.addImm(0);
4160}
4161
4162MachineInstr*
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4163X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4164 MachineInstr *MI, unsigned i,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4165 const SmallVectorImpl<MachineOperand> &MOs,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4166 unsigned Size, unsigned Align,
4167 bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4168 const DenseMap<unsigned,
4169 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4170 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4171 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4172
4173 // Atom favors register form of call. So, we do not fold loads into calls
4174 // when X86Subtarget is Atom.
4175 if (isCallRegIndirect &&
4176 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4177 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4178 }
4179
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4180 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4181 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4182 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4183
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4184 // FIXME: AsmPrinter doesn't know how to handle
4185 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4186 if (MI->getOpcode() == X86::ADD32ri &&
4187 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4188 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4189
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4190 MachineInstr *NewMI = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4191 // Folding a memory location into the two-address part of a two-address
4192 // instruction is different than folding it other places. It requires
4193 // replacing the *two* registers with the memory location.
4194 if (isTwoAddr && NumOps >= 2 && i < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4195 MI->getOperand(0).isReg() &&
4196 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4197 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4198 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4199 isTwoAddrFold = true;
4200 } else if (i == 0) { // If operand 0
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4201 if (MI->getOpcode() == X86::MOV32r0) {
4202 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4203 if (NewMI)
4204 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]4205 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4206
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4207 OpcodeTablePtr = &RegOp2MemOpTable0;
4208 } else if (i == 1) {
4209 OpcodeTablePtr = &RegOp2MemOpTable1;
4210 } else if (i == 2) {
4211 OpcodeTablePtr = &RegOp2MemOpTable2;
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]4212 } else if (i == 3) {
4213 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4214 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4215
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4216 // If table selected...
4217 if (OpcodeTablePtr) {
4218 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4219 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4220 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4221 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4222 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4223 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4224 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4225 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4226 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4227 if (Size) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4228 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4229 if (Size < RCSize) {
4230 // Check if it's safe to fold the load. If the size of the object is
4231 // narrower than the load width, then it's not.
4232 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4233 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4234 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4235 // a 32-bit load which is implicitly zero-extended. This likely is
4236 // due to live interval analysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4237 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4238 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4239 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4240 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4241 }
4242 }
4243
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4244 if (isTwoAddrFold)
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4245 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4246 else
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4247 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4248
4249 if (NarrowToMOV32rm) {
4250 // If this is the special case where we use a MOV32rm to load a 32-bit
4251 // value and zero-extend the top bits. Change the destination register
4252 // to a 32-bit one.
4253 unsigned DstReg = NewMI->getOperand(0).getReg();
4254 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4255 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4256 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]4257 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4258 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4259 return NewMI;
4260 }
4261 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4262
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4263 // If the instruction and target operand are commutable, commute the
4264 // instruction and try again.
4265 if (AllowCommute) {
4266 unsigned OriginalOpIdx = i, CommuteOpIdx1, CommuteOpIdx2;
4267 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4268 bool HasDef = MI->getDesc().getNumDefs();
4269 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4270 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4271 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4272 bool Tied0 =
4273 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4274 bool Tied1 =
4275 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4276
4277 // If either of the commutable operands are tied to the destination
4278 // then we can not commute + fold.
4279 if ((HasDef && Reg0 == Reg1 && Tied0) ||
4280 (HasDef && Reg0 == Reg2 && Tied1))
4281 return nullptr;
4282
4283 if ((CommuteOpIdx1 == OriginalOpIdx) ||
4284 (CommuteOpIdx2 == OriginalOpIdx)) {
4285 MachineInstr *CommutedMI = commuteInstruction(MI, false);
4286 if (!CommutedMI) {
4287 // Unable to commute.
4288 return nullptr;
4289 }
4290 if (CommutedMI != MI) {
4291 // New instruction. We can't fold from this.
4292 CommutedMI->eraseFromParent();
4293 return nullptr;
4294 }
4295
4296 // Attempt to fold with the commuted version of the instruction.
4297 unsigned CommuteOp =
4298 (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4299 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4300 /*AllowCommute=*/false);
4301 if (NewMI)
4302 return NewMI;
4303
4304 // Folding failed again - undo the commute before returning.
4305 MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4306 if (!UncommutedMI) {
4307 // Unable to commute.
4308 return nullptr;
4309 }
4310 if (UncommutedMI != MI) {
4311 // New instruction. It doesn't need to be kept.
4312 UncommutedMI->eraseFromParent();
4313 return nullptr;
4314 }
4315
4316 // Return here to prevent duplicate fuse failure report.
4317 return nullptr;
4318 }
4319 }
4320 }
4321
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4322 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]4323 if (PrintFailedFusing && !MI->isCopy())
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]4324 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4325 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4326}
4327
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4328/// hasPartialRegUpdate - Return true for all instructions that only update
4329/// the first 32 or 64-bits of the destination register and leave the rest
4330/// unmodified. This can be used to avoid folding loads if the instructions
4331/// only update part of the destination register, and the non-updated part is
4332/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4333/// instructions breaks the partial register dependency and it can improve
4334/// performance. e.g.:
4335///
4336/// movss (%rdi), %xmm0
4337/// cvtss2sd %xmm0, %xmm0
4338///
4339/// Instead of
4340/// cvtss2sd (%rdi), %xmm0
4341///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]4342/// FIXME: This should be turned into a TSFlags.
4343///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4344static bool hasPartialRegUpdate(unsigned Opcode) {
4345 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4346 case X86::CVTSI2SSrr:
4347 case X86::CVTSI2SS64rr:
4348 case X86::CVTSI2SDrr:
4349 case X86::CVTSI2SD64rr:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4350 case X86::CVTSD2SSrr:
4351 case X86::Int_CVTSD2SSrr:
4352 case X86::CVTSS2SDrr:
4353 case X86::Int_CVTSS2SDrr:
4354 case X86::RCPSSr:
4355 case X86::RCPSSr_Int:
4356 case X86::ROUNDSDr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4357 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4358 case X86::ROUNDSSr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4359 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4360 case X86::RSQRTSSr:
4361 case X86::RSQRTSSr_Int:
4362 case X86::SQRTSSr:
4363 case X86::SQRTSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4364 return true;
4365 }
4366
4367 return false;
4368}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4369
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4370/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4371/// instructions we would like before a partial register update.
4372unsigned X86InstrInfo::
4373getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4374 const TargetRegisterInfo *TRI) const {
4375 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4376 return 0;
4377
4378 // If MI is marked as reading Reg, the partial register update is wanted.
4379 const MachineOperand &MO = MI->getOperand(0);
4380 unsigned Reg = MO.getReg();
4381 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4382 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4383 return 0;
4384 } else {
4385 if (MI->readsRegister(Reg, TRI))
4386 return 0;
4387 }
4388
4389 // If any of the preceding 16 instructions are reading Reg, insert a
4390 // dependency breaking instruction. The magic number is based on a few
4391 // Nehalem experiments.
4392 return 16;
4393}
4394
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4395// Return true for any instruction the copies the high bits of the first source
4396// operand into the unused high bits of the destination operand.
4397static bool hasUndefRegUpdate(unsigned Opcode) {
4398 switch (Opcode) {
4399 case X86::VCVTSI2SSrr:
4400 case X86::Int_VCVTSI2SSrr:
4401 case X86::VCVTSI2SS64rr:
4402 case X86::Int_VCVTSI2SS64rr:
4403 case X86::VCVTSI2SDrr:
4404 case X86::Int_VCVTSI2SDrr:
4405 case X86::VCVTSI2SD64rr:
4406 case X86::Int_VCVTSI2SD64rr:
4407 case X86::VCVTSD2SSrr:
4408 case X86::Int_VCVTSD2SSrr:
4409 case X86::VCVTSS2SDrr:
4410 case X86::Int_VCVTSS2SDrr:
4411 case X86::VRCPSSr:
4412 case X86::VROUNDSDr:
4413 case X86::VROUNDSDr_Int:
4414 case X86::VROUNDSSr:
4415 case X86::VROUNDSSr_Int:
4416 case X86::VRSQRTSSr:
4417 case X86::VSQRTSSr:
4418
4419 // AVX-512
4420 case X86::VCVTSD2SSZrr:
4421 case X86::VCVTSS2SDZrr:
4422 return true;
4423 }
4424
4425 return false;
4426}
4427
4428/// Inform the ExeDepsFix pass how many idle instructions we would like before
4429/// certain undef register reads.
4430///
4431/// This catches the VCVTSI2SD family of instructions:
4432///
4433/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4434///
4435/// We should to be careful *not* to catch VXOR idioms which are presumably
4436/// handled specially in the pipeline:
4437///
4438/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4439///
4440/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4441/// high bits that are passed-through are not live.
4442unsigned X86InstrInfo::
4443getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4444 const TargetRegisterInfo *TRI) const {
4445 if (!hasUndefRegUpdate(MI->getOpcode()))
4446 return 0;
4447
4448 // Set the OpNum parameter to the first source operand.
4449 OpNum = 1;
4450
4451 const MachineOperand &MO = MI->getOperand(OpNum);
4452 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4453 // Use the same magic number as getPartialRegUpdateClearance.
4454 return 16;
4455 }
4456 return 0;
4457}
4458
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4459void X86InstrInfo::
4460breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4461 const TargetRegisterInfo *TRI) const {
4462 unsigned Reg = MI->getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4463 // If MI kills this register, the false dependence is already broken.
4464 if (MI->killsRegister(Reg, TRI))
4465 return;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4466 if (X86::VR128RegClass.contains(Reg)) {
4467 // These instructions are all floating point domain, so xorps is the best
4468 // choice.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4469 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4470 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4471 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4472 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4473 } else if (X86::VR256RegClass.contains(Reg)) {
4474 // Use vxorps to clear the full ymm register.
4475 // It wants to read and write the xmm sub-register.
4476 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4477 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4478 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4479 .addReg(Reg, RegState::ImplicitDefine);
4480 } else
4481 return;
4482 MI->addRegisterKilled(Reg, TRI, true);
4483}
4484
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]4485MachineInstr*
4486X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4487 const SmallVectorImpl<unsigned> &Ops,
4488 int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4489 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4490 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4491
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4492 // Unless optimizing for size, don't fold to avoid partial
4493 // register update stalls
Bill Wendling698e84f2012-12-30 10:32:01 +0000[diff] [blame]4494 if (!MF.getFunction()->getAttributes().
4495 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4496 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4497 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]4498
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4499 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4500 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4501 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]4502 // If the function stack isn't realigned we don't want to fold instructions
4503 // that need increased alignment.
4504 if (!RI.needsStackRealignment(MF))
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]4505 Alignment = std::min(Alignment, MF.getTarget()
4506 .getSubtargetImpl()
4507 ->getFrameLowering()
4508 ->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4509 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4510 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4511 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4512 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4513 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4514 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]4515 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4516 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4517 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4518 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4519 // Check if it's safe to fold the load. If the size of the object is
4520 // narrower than the load width, then it's not.
4521 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4522 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4523 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4524 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4525 MI->getOperand(1).ChangeToImmediate(0);
4526 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4527 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4528
4529 SmallVector<MachineOperand,4> MOs;
4530 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4531 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4532 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4533}
4534
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]4535static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
4536 const MachineFunction &MF) {
4537 unsigned Opc = LoadMI.getOpcode();
4538 unsigned RegSize =
4539 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
4540
4541 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
4542 // These instructions only load 32 bits, we can't fold them if the
4543 // destination register is wider than 32 bits (4 bytes).
4544 return true;
4545
4546 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
4547 // These instructions only load 64 bits, we can't fold them if the
4548 // destination register is wider than 64 bits (8 bytes).
4549 return true;
4550
4551 return false;
4552}
4553
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4554MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4555 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4556 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4557 MachineInstr *LoadMI) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]4558 // If loading from a FrameIndex, fold directly from the FrameIndex.
4559 unsigned NumOps = LoadMI->getDesc().getNumOperands();
4560 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]4561 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
4562 if (isPartialRegisterLoad(*LoadMI, MF))
4563 return nullptr;
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]4564 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]4565 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]4566
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4567 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4568 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4569
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4570 // Unless optimizing for size, don't fold to avoid partial
4571 // register update stalls
Bill Wendling698e84f2012-12-30 10:32:01 +0000[diff] [blame]4572 if (!MF.getFunction()->getAttributes().
4573 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4574 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4575 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]4576
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]4577 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4578 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]4579 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]4580 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4581 else
4582 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]4583 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4584 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]4585 Alignment = 32;
4586 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4587 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4588 case X86::V_SETALLONES:
4589 Alignment = 16;
4590 break;
4591 case X86::FsFLD0SD:
4592 Alignment = 8;
4593 break;
4594 case X86::FsFLD0SS:
4595 Alignment = 4;
4596 break;
4597 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4598 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4599 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4600 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4601 unsigned NewOpc = 0;
4602 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4603 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4604 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4605 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4606 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4607 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4608 }
4609 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4610 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4611 MI->getOperand(1).ChangeToImmediate(0);
4612 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4613 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4614
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]4615 // Make sure the subregisters match.
4616 // Otherwise we risk changing the size of the load.
4617 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4618 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]4619
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4620 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4621 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4622 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4623 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]4624 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4625 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4626 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4627 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4628 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4629 // Create a constant-pool entry and operands to load from it.
4630
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]4631 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4632 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
4633 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4634 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]4635
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4636 // x86-32 PIC requires a PIC base register for constant pools.
4637 unsigned PICBase = 0;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4638 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
4639 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]4640 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]4641 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4642 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]4643 // This doesn't work for several reasons.
4644 // 1. GlobalBaseReg may have been spilled.
4645 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4646 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]4647 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4648
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4649 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4650 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]4651 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]4652 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4653 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4654 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4655 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4656 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4657 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]4658 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4659 else
4660 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]4661
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4662 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]4663 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4664 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4665 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4666
4667 // Create operands to load from the constant pool entry.
4668 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4669 MOs.push_back(MachineOperand::CreateImm(1));
4670 MOs.push_back(MachineOperand::CreateReg(0, false));
4671 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4672 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4673 break;
4674 }
4675 default: {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]4676 if (isPartialRegisterLoad(*LoadMI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4677 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]4678
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4679 // Folding a normal load. Just copy the load's address operands.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4680 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4681 MOs.push_back(LoadMI->getOperand(i));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4682 break;
4683 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4684 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4685 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4686 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4687}
4688
4689
Dan Gohman33332bc2008-10-16 01:49:15 +0000[diff] [blame]4690bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4691 const SmallVectorImpl<unsigned> &Ops) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4692 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4693 if (NoFusing) return 0;
4694
4695 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4696 switch (MI->getOpcode()) {
4697 default: return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4698 case X86::TEST8rr:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4699 case X86::TEST16rr:
4700 case X86::TEST32rr:
4701 case X86::TEST64rr:
4702 return true;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4703 case X86::ADD32ri:
4704 // FIXME: AsmPrinter doesn't know how to handle
4705 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4706 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4707 return false;
4708 break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4709 }
4710 }
4711
4712 if (Ops.size() != 1)
4713 return false;
4714
4715 unsigned OpNum = Ops[0];
4716 unsigned Opc = MI->getOpcode();
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4717 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4718 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4719 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4720
4721 // Folding a memory location into the two-address part of a two-address
4722 // instruction is different than folding it other places. It requires
4723 // replacing the *two* registers with the memory location.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4724 const DenseMap<unsigned,
4725 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4726 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4727 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4728 } else if (OpNum == 0) { // If operand 0
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4729 if (Opc == X86::MOV32r0)
4730 return true;
4731
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4732 OpcodeTablePtr = &RegOp2MemOpTable0;
4733 } else if (OpNum == 1) {
4734 OpcodeTablePtr = &RegOp2MemOpTable1;
4735 } else if (OpNum == 2) {
4736 OpcodeTablePtr = &RegOp2MemOpTable2;
Craig Topper7573c8f2012-08-31 22:12:16 +0000[diff] [blame]4737 } else if (OpNum == 3) {
4738 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4739 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4740
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]4741 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4742 return true;
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]4743 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4744}
4745
4746bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4747 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4748 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4749 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4750 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4751 if (I == MemOp2RegOpTable.end())
4752 return false;
4753 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4754 unsigned Index = I->second.second & TB_INDEX_MASK;
4755 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4756 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4757 if (UnfoldLoad && !FoldedLoad)
4758 return false;
4759 UnfoldLoad &= FoldedLoad;
4760 if (UnfoldStore && !FoldedStore)
4761 return false;
4762 UnfoldStore &= FoldedStore;
4763
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4764 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4765 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4766 if (!MI->hasOneMemOperand() &&
4767 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4768 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4769 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4770 // conservatively assume the address is unaligned. That's bad for
4771 // performance.
4772 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4773 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4774 SmallVector<MachineOperand,2> BeforeOps;
4775 SmallVector<MachineOperand,2> AfterOps;
4776 SmallVector<MachineOperand,4> ImpOps;
4777 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4778 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4779 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4780 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4781 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4782 ImpOps.push_back(Op);
4783 else if (i < Index)
4784 BeforeOps.push_back(Op);
4785 else if (i > Index)
4786 AfterOps.push_back(Op);
4787 }
4788
4789 // Emit the load instruction.
4790 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4791 std::pair<MachineInstr::mmo_iterator,
4792 MachineInstr::mmo_iterator> MMOs =
4793 MF.extractLoadMemRefs(MI->memoperands_begin(),
4794 MI->memoperands_end());
4795 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4796 if (UnfoldStore) {
4797 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4798 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4799 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4800 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4801 MO.setIsKill(false);
4802 }
4803 }
4804 }
4805
4806 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4807 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4808 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4809
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4810 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4811 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4812 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4813 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4814 if (FoldedLoad)
4815 MIB.addReg(Reg);
4816 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4817 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4818 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4819 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4820 MIB.addReg(MO.getReg(),
4821 getDefRegState(MO.isDef()) |
4822 RegState::Implicit |
4823 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]4824 getDeadRegState(MO.isDead()) |
4825 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4826 }
4827 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4828 switch (DataMI->getOpcode()) {
4829 default: break;
4830 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4831 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4832 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4833 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4834 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4835 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4836 case X86::CMP8ri: {
4837 MachineOperand &MO0 = DataMI->getOperand(0);
4838 MachineOperand &MO1 = DataMI->getOperand(1);
4839 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4840 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4841 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4842 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4843 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4844 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4845 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4846 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4847 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4848 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
4849 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
4850 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4851 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4852 MO1.ChangeToRegister(MO0.getReg(), false);
4853 }
4854 }
4855 }
4856 NewMIs.push_back(DataMI);
4857
4858 // Emit the store instruction.
4859 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4860 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4861 std::pair<MachineInstr::mmo_iterator,
4862 MachineInstr::mmo_iterator> MMOs =
4863 MF.extractStoreMemRefs(MI->memoperands_begin(),
4864 MI->memoperands_end());
4865 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4866 }
4867
4868 return true;
4869}
4870
4871bool
4872X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4873 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]4874 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4875 return false;
4876
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4877 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4878 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4879 if (I == MemOp2RegOpTable.end())
4880 return false;
4881 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4882 unsigned Index = I->second.second & TB_INDEX_MASK;
4883 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4884 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4885 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4886 MachineFunction &MF = DAG.getMachineFunction();
4887 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4888 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4889 std::vector<SDValue> AddrOps;
4890 std::vector<SDValue> BeforeOps;
4891 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]4892 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4893 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]4894 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4895 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4896 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4897 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]4898 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4899 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]4900 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4901 AfterOps.push_back(Op);
4902 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4903 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4904 AddrOps.push_back(Chain);
4905
4906 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4907 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4908 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4909 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]4910 std::pair<MachineInstr::mmo_iterator,
4911 MachineInstr::mmo_iterator> MMOs =
4912 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4913 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4914 if (!(*MMOs.first) &&
4915 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4916 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4917 // Do not introduce a slow unaligned load.
4918 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4919 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4920 bool isAligned = (*MMOs.first) &&
4921 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4922 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]4923 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4924 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4925
4926 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4927 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4928 }
4929
4930 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4931 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4932 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4933 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4934 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4935 VTs.push_back(*DstRC->vt_begin());
4936 }
4937 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4938 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4939 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4940 VTs.push_back(VT);
4941 }
4942 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4943 BeforeOps.push_back(SDValue(Load, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4944 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]4945 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4946 NewNodes.push_back(NewNode);
4947
4948 // Emit the store instruction.
4949 if (FoldedStore) {
4950 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4951 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4952 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]4953 std::pair<MachineInstr::mmo_iterator,
4954 MachineInstr::mmo_iterator> MMOs =
4955 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4956 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4957 if (!(*MMOs.first) &&
4958 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4959 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4960 // Do not introduce a slow unaligned store.
4961 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4962 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4963 bool isAligned = (*MMOs.first) &&
4964 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4965 SDNode *Store =
4966 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
4967 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4968 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4969
4970 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4971 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4972 }
4973
4974 return true;
4975}
4976
4977unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]4978 bool UnfoldLoad, bool UnfoldStore,
4979 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4980 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4981 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4982 if (I == MemOp2RegOpTable.end())
4983 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4984 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4985 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4986 if (UnfoldLoad && !FoldedLoad)
4987 return 0;
4988 if (UnfoldStore && !FoldedStore)
4989 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]4990 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4991 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4992 return I->second.first;
4993}
4994
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4995bool
4996X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4997 int64_t &Offset1, int64_t &Offset2) const {
4998 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4999 return false;
5000 unsigned Opc1 = Load1->getMachineOpcode();
5001 unsigned Opc2 = Load2->getMachineOpcode();
5002 switch (Opc1) {
5003 default: return false;
5004 case X86::MOV8rm:
5005 case X86::MOV16rm:
5006 case X86::MOV32rm:
5007 case X86::MOV64rm:
5008 case X86::LD_Fp32m:
5009 case X86::LD_Fp64m:
5010 case X86::LD_Fp80m:
5011 case X86::MOVSSrm:
5012 case X86::MOVSDrm:
5013 case X86::MMX_MOVD64rm:
5014 case X86::MMX_MOVQ64rm:
5015 case X86::FsMOVAPSrm:
5016 case X86::FsMOVAPDrm:
5017 case X86::MOVAPSrm:
5018 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5019 case X86::MOVAPDrm:
5020 case X86::MOVDQArm:
5021 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5022 // AVX load instructions
5023 case X86::VMOVSSrm:
5024 case X86::VMOVSDrm:
5025 case X86::FsVMOVAPSrm:
5026 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5027 case X86::VMOVAPSrm:
5028 case X86::VMOVUPSrm:
5029 case X86::VMOVAPDrm:
5030 case X86::VMOVDQArm:
5031 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5032 case X86::VMOVAPSYrm:
5033 case X86::VMOVUPSYrm:
5034 case X86::VMOVAPDYrm:
5035 case X86::VMOVDQAYrm:
5036 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5037 break;
5038 }
5039 switch (Opc2) {
5040 default: return false;
5041 case X86::MOV8rm:
5042 case X86::MOV16rm:
5043 case X86::MOV32rm:
5044 case X86::MOV64rm:
5045 case X86::LD_Fp32m:
5046 case X86::LD_Fp64m:
5047 case X86::LD_Fp80m:
5048 case X86::MOVSSrm:
5049 case X86::MOVSDrm:
5050 case X86::MMX_MOVD64rm:
5051 case X86::MMX_MOVQ64rm:
5052 case X86::FsMOVAPSrm:
5053 case X86::FsMOVAPDrm:
5054 case X86::MOVAPSrm:
5055 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5056 case X86::MOVAPDrm:
5057 case X86::MOVDQArm:
5058 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5059 // AVX load instructions
5060 case X86::VMOVSSrm:
5061 case X86::VMOVSDrm:
5062 case X86::FsVMOVAPSrm:
5063 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5064 case X86::VMOVAPSrm:
5065 case X86::VMOVUPSrm:
5066 case X86::VMOVAPDrm:
5067 case X86::VMOVDQArm:
5068 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5069 case X86::VMOVAPSYrm:
5070 case X86::VMOVUPSYrm:
5071 case X86::VMOVAPDYrm:
5072 case X86::VMOVDQAYrm:
5073 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5074 break;
5075 }
5076
5077 // Check if chain operands and base addresses match.
5078 if (Load1->getOperand(0) != Load2->getOperand(0) ||
5079 Load1->getOperand(5) != Load2->getOperand(5))
5080 return false;
5081 // Segment operands should match as well.
5082 if (Load1->getOperand(4) != Load2->getOperand(4))
5083 return false;
5084 // Scale should be 1, Index should be Reg0.
5085 if (Load1->getOperand(1) == Load2->getOperand(1) &&
5086 Load1->getOperand(2) == Load2->getOperand(2)) {
5087 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5088 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5089
5090 // Now let's examine the displacements.
5091 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5092 isa<ConstantSDNode>(Load2->getOperand(3))) {
5093 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5094 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5095 return true;
5096 }
5097 }
5098 return false;
5099}
5100
5101bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5102 int64_t Offset1, int64_t Offset2,
5103 unsigned NumLoads) const {
5104 assert(Offset2 > Offset1);
5105 if ((Offset2 - Offset1) / 8 > 64)
5106 return false;
5107
5108 unsigned Opc1 = Load1->getMachineOpcode();
5109 unsigned Opc2 = Load2->getMachineOpcode();
5110 if (Opc1 != Opc2)
5111 return false; // FIXME: overly conservative?
5112
5113 switch (Opc1) {
5114 default: break;
5115 case X86::LD_Fp32m:
5116 case X86::LD_Fp64m:
5117 case X86::LD_Fp80m:
5118 case X86::MMX_MOVD64rm:
5119 case X86::MMX_MOVQ64rm:
5120 return false;
5121 }
5122
5123 EVT VT = Load1->getValueType(0);
5124 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5125 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5126 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5127 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5128 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5129 if (NumLoads >= 3)
5130 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5131 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5132 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5133 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5134 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5135 case MVT::i8:
5136 case MVT::i16:
5137 case MVT::i32:
5138 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]5139 case MVT::f32:
5140 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5141 if (NumLoads)
5142 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5143 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5144 }
5145
5146 return true;
5147}
5148
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5149bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5150 MachineInstr *Second) const {
5151 // Check if this processor supports macro-fusion. Since this is a minor
5152 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5153 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5154 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5155 return false;
5156
5157 enum {
5158 FuseTest,
5159 FuseCmp,
5160 FuseInc
5161 } FuseKind;
5162
5163 switch(Second->getOpcode()) {
5164 default:
5165 return false;
5166 case X86::JE_4:
5167 case X86::JNE_4:
5168 case X86::JL_4:
5169 case X86::JLE_4:
5170 case X86::JG_4:
5171 case X86::JGE_4:
5172 FuseKind = FuseInc;
5173 break;
5174 case X86::JB_4:
5175 case X86::JBE_4:
5176 case X86::JA_4:
5177 case X86::JAE_4:
5178 FuseKind = FuseCmp;
5179 break;
5180 case X86::JS_4:
5181 case X86::JNS_4:
5182 case X86::JP_4:
5183 case X86::JNP_4:
5184 case X86::JO_4:
5185 case X86::JNO_4:
5186 FuseKind = FuseTest;
5187 break;
5188 }
5189 switch (First->getOpcode()) {
5190 default:
5191 return false;
5192 case X86::TEST8rr:
5193 case X86::TEST16rr:
5194 case X86::TEST32rr:
5195 case X86::TEST64rr:
5196 case X86::TEST8ri:
5197 case X86::TEST16ri:
5198 case X86::TEST32ri:
5199 case X86::TEST32i32:
5200 case X86::TEST64i32:
5201 case X86::TEST64ri32:
5202 case X86::TEST8rm:
5203 case X86::TEST16rm:
5204 case X86::TEST32rm:
5205 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]5206 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5207 case X86::AND16i16:
5208 case X86::AND16ri:
5209 case X86::AND16ri8:
5210 case X86::AND16rm:
5211 case X86::AND16rr:
5212 case X86::AND32i32:
5213 case X86::AND32ri:
5214 case X86::AND32ri8:
5215 case X86::AND32rm:
5216 case X86::AND32rr:
5217 case X86::AND64i32:
5218 case X86::AND64ri32:
5219 case X86::AND64ri8:
5220 case X86::AND64rm:
5221 case X86::AND64rr:
5222 case X86::AND8i8:
5223 case X86::AND8ri:
5224 case X86::AND8rm:
5225 case X86::AND8rr:
5226 return true;
5227 case X86::CMP16i16:
5228 case X86::CMP16ri:
5229 case X86::CMP16ri8:
5230 case X86::CMP16rm:
5231 case X86::CMP16rr:
5232 case X86::CMP32i32:
5233 case X86::CMP32ri:
5234 case X86::CMP32ri8:
5235 case X86::CMP32rm:
5236 case X86::CMP32rr:
5237 case X86::CMP64i32:
5238 case X86::CMP64ri32:
5239 case X86::CMP64ri8:
5240 case X86::CMP64rm:
5241 case X86::CMP64rr:
5242 case X86::CMP8i8:
5243 case X86::CMP8ri:
5244 case X86::CMP8rm:
5245 case X86::CMP8rr:
5246 case X86::ADD16i16:
5247 case X86::ADD16ri:
5248 case X86::ADD16ri8:
5249 case X86::ADD16ri8_DB:
5250 case X86::ADD16ri_DB:
5251 case X86::ADD16rm:
5252 case X86::ADD16rr:
5253 case X86::ADD16rr_DB:
5254 case X86::ADD32i32:
5255 case X86::ADD32ri:
5256 case X86::ADD32ri8:
5257 case X86::ADD32ri8_DB:
5258 case X86::ADD32ri_DB:
5259 case X86::ADD32rm:
5260 case X86::ADD32rr:
5261 case X86::ADD32rr_DB:
5262 case X86::ADD64i32:
5263 case X86::ADD64ri32:
5264 case X86::ADD64ri32_DB:
5265 case X86::ADD64ri8:
5266 case X86::ADD64ri8_DB:
5267 case X86::ADD64rm:
5268 case X86::ADD64rr:
5269 case X86::ADD64rr_DB:
5270 case X86::ADD8i8:
5271 case X86::ADD8mi:
5272 case X86::ADD8mr:
5273 case X86::ADD8ri:
5274 case X86::ADD8rm:
5275 case X86::ADD8rr:
5276 case X86::SUB16i16:
5277 case X86::SUB16ri:
5278 case X86::SUB16ri8:
5279 case X86::SUB16rm:
5280 case X86::SUB16rr:
5281 case X86::SUB32i32:
5282 case X86::SUB32ri:
5283 case X86::SUB32ri8:
5284 case X86::SUB32rm:
5285 case X86::SUB32rr:
5286 case X86::SUB64i32:
5287 case X86::SUB64ri32:
5288 case X86::SUB64ri8:
5289 case X86::SUB64rm:
5290 case X86::SUB64rr:
5291 case X86::SUB8i8:
5292 case X86::SUB8ri:
5293 case X86::SUB8rm:
5294 case X86::SUB8rr:
5295 return FuseKind == FuseCmp || FuseKind == FuseInc;
5296 case X86::INC16r:
5297 case X86::INC32r:
5298 case X86::INC64_16r:
5299 case X86::INC64_32r:
5300 case X86::INC64r:
5301 case X86::INC8r:
5302 case X86::DEC16r:
5303 case X86::DEC32r:
5304 case X86::DEC64_16r:
5305 case X86::DEC64_32r:
5306 case X86::DEC64r:
5307 case X86::DEC8r:
5308 return FuseKind == FuseInc;
5309 }
5310}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5311
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5312bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]5313ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5314 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5315 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]5316 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5317 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5318 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5319 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5320}
5321
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5322bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5323isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5324 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5325 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5326 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5327 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5328}
5329
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5330/// getGlobalBaseReg - Return a virtual register initialized with the
5331/// the global base register value. Output instructions required to
5332/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5333///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5334/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5335///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5336unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5337 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5338 "X86-64 PIC uses RIP relative addressing");
5339
5340 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5341 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5342 if (GlobalBaseReg != 0)
5343 return GlobalBaseReg;
5344
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5345 // Create the register. The code to initialize it is inserted
5346 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5347 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]5348 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5349 X86FI->setGlobalBaseReg(GlobalBaseReg);
5350 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5351}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5352
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5353// These are the replaceable SSE instructions. Some of these have Int variants
5354// that we don't include here. We don't want to replace instructions selected
5355// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5356static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]5357 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]5358 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5359 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5360 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5361 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5362 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5363 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5364 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5365 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5366 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5367 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5368 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5369 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5370 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5371 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5372 // AVX 128-bit support
5373 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5374 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5375 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5376 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5377 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5378 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5379 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5380 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5381 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5382 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5383 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5384 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5385 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5386 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5387 // AVX 256-bit support
5388 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5389 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5390 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5391 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5392 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5393 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
5394};
5395
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5396static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5397 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]5398 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5399 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5400 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5401 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5402 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5403 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5404 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]5405 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5406 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5407 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5408 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5409 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5410 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]5411 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5412 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5413 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5414 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5415 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5416 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5417 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5418};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5419
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5420// FIXME: Some shuffle and unpack instructions have equivalents in different
5421// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5422
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5423static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5424 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5425 if (ReplaceableInstrs[i][domain-1] == opcode)
5426 return ReplaceableInstrs[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5427 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5428}
5429
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5430static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5431 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5432 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5433 return ReplaceableInstrsAVX2[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5434 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5435}
5436
5437std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5438X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5439 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5440 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5441 uint16_t validDomains = 0;
5442 if (domain && lookup(MI->getOpcode(), domain))
5443 validDomains = 0xe;
5444 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5445 validDomains = hasAVX2 ? 0xe : 0x6;
5446 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5447}
5448
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5449void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5450 assert(Domain>0 && Domain<4 && "Invalid execution domain");
5451 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5452 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5453 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5454 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5455 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5456 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5457 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5458 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5459 assert(table && "Cannot change domain");
5460 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5461}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]5462
5463/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5464void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5465 NopInst.setOpcode(X86::NOOP);
5466}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5467
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]5468void X86InstrInfo::getUnconditionalBranch(
5469 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
5470 Branch.setOpcode(X86::JMP_4);
5471 Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
5472}
5473
5474void X86InstrInfo::getTrap(MCInst &MI) const {
5475 MI.setOpcode(X86::TRAP);
5476}
5477
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]5478bool X86InstrInfo::isHighLatencyDef(int opc) const {
5479 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5480 default: return false;
5481 case X86::DIVSDrm:
5482 case X86::DIVSDrm_Int:
5483 case X86::DIVSDrr:
5484 case X86::DIVSDrr_Int:
5485 case X86::DIVSSrm:
5486 case X86::DIVSSrm_Int:
5487 case X86::DIVSSrr:
5488 case X86::DIVSSrr_Int:
5489 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5490 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5491 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5492 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5493 case X86::SQRTSDm:
5494 case X86::SQRTSDm_Int:
5495 case X86::SQRTSDr:
5496 case X86::SQRTSDr_Int:
5497 case X86::SQRTSSm:
5498 case X86::SQRTSSm_Int:
5499 case X86::SQRTSSr:
5500 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5501 // AVX instructions with high latency
5502 case X86::VDIVSDrm:
5503 case X86::VDIVSDrm_Int:
5504 case X86::VDIVSDrr:
5505 case X86::VDIVSDrr_Int:
5506 case X86::VDIVSSrm:
5507 case X86::VDIVSSrm_Int:
5508 case X86::VDIVSSrr:
5509 case X86::VDIVSSrr_Int:
5510 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5511 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5512 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5513 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5514 case X86::VSQRTSDm:
5515 case X86::VSQRTSDm_Int:
5516 case X86::VSQRTSDr:
5517 case X86::VSQRTSSm:
5518 case X86::VSQRTSSm_Int:
5519 case X86::VSQRTSSr:
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]5520 case X86::VSQRTPDZm:
5521 case X86::VSQRTPDZr:
5522 case X86::VSQRTPSZm:
5523 case X86::VSQRTPSZr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]5524 case X86::VSQRTSDZm:
5525 case X86::VSQRTSDZm_Int:
5526 case X86::VSQRTSDZr:
5527 case X86::VSQRTSSZm_Int:
5528 case X86::VSQRTSSZr:
5529 case X86::VSQRTSSZm:
5530 case X86::VDIVSDZrm:
5531 case X86::VDIVSDZrr:
5532 case X86::VDIVSSZrm:
5533 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]5534
5535 case X86::VGATHERQPSZrm:
5536 case X86::VGATHERQPDZrm:
5537 case X86::VGATHERDPDZrm:
5538 case X86::VGATHERDPSZrm:
5539 case X86::VPGATHERQDZrm:
5540 case X86::VPGATHERQQZrm:
5541 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]5542 case X86::VPGATHERDQZrm:
5543 case X86::VSCATTERQPDZmr:
5544 case X86::VSCATTERQPSZmr:
5545 case X86::VSCATTERDPDZmr:
5546 case X86::VSCATTERDPSZmr:
5547 case X86::VPSCATTERQDZmr:
5548 case X86::VPSCATTERQQZmr:
5549 case X86::VPSCATTERDDZmr:
5550 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5551 return true;
5552 }
5553}
5554
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]5555bool X86InstrInfo::
5556hasHighOperandLatency(const InstrItineraryData *ItinData,
5557 const MachineRegisterInfo *MRI,
5558 const MachineInstr *DefMI, unsigned DefIdx,
5559 const MachineInstr *UseMI, unsigned UseIdx) const {
5560 return isHighLatencyDef(DefMI->getOpcode());
5561}
5562
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5563namespace {
5564 /// CGBR - Create Global Base Reg pass. This initializes the PIC
5565 /// global base register for x86-32.
5566 struct CGBR : public MachineFunctionPass {
5567 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]5568 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5569
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5570 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5571 const X86TargetMachine *TM =
5572 static_cast<const X86TargetMachine *>(&MF.getTarget());
5573
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]5574 // Don't do anything if this is 64-bit as 64-bit PIC
5575 // uses RIP relative addressing.
5576 if (TM->getSubtarget<X86Subtarget>().is64Bit())
5577 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5578
5579 // Only emit a global base reg in PIC mode.
5580 if (TM->getRelocationModel() != Reloc::PIC_)
5581 return false;
5582
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]5583 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5584 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5585
5586 // If we didn't need a GlobalBaseReg, don't insert code.
5587 if (GlobalBaseReg == 0)
5588 return false;
5589
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5590 // Insert the set of GlobalBaseReg into the first MBB of the function
5591 MachineBasicBlock &FirstMBB = MF.front();
5592 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5593 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5594 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]5595 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5596
5597 unsigned PC;
5598 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]5599 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5600 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]5601 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5602
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5603 // Operand of MovePCtoStack is completely ignored by asm printer. It's
5604 // only used in JIT code emission as displacement to pc.
5605 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5606
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5607 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5608 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5609 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5610 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5611 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5612 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5613 X86II::MO_GOT_ABSOLUTE_ADDRESS);
5614 }
5615
5616 return true;
5617 }
5618
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5619 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5620 return "X86 PIC Global Base Reg Initialization";
5621 }
5622
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5623 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5624 AU.setPreservesCFG();
5625 MachineFunctionPass::getAnalysisUsage(AU);
5626 }
5627 };
5628}
5629
5630char CGBR::ID = 0;
5631FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]5632llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5633
5634namespace {
5635 struct LDTLSCleanup : public MachineFunctionPass {
5636 static char ID;
5637 LDTLSCleanup() : MachineFunctionPass(ID) {}
5638
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5639 bool runOnMachineFunction(MachineFunction &MF) override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5640 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5641 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5642 // No point folding accesses if there isn't at least two.
5643 return false;
5644 }
5645
5646 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5647 return VisitNode(DT->getRootNode(), 0);
5648 }
5649
5650 // Visit the dominator subtree rooted at Node in pre-order.
5651 // If TLSBaseAddrReg is non-null, then use that to replace any
5652 // TLS_base_addr instructions. Otherwise, create the register
5653 // when the first such instruction is seen, and then use it
5654 // as we encounter more instructions.
5655 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5656 MachineBasicBlock *BB = Node->getBlock();
5657 bool Changed = false;
5658
5659 // Traverse the current block.
5660 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5661 ++I) {
5662 switch (I->getOpcode()) {
5663 case X86::TLS_base_addr32:
5664 case X86::TLS_base_addr64:
5665 if (TLSBaseAddrReg)
5666 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5667 else
5668 I = SetRegister(I, &TLSBaseAddrReg);
5669 Changed = true;
5670 break;
5671 default:
5672 break;
5673 }
5674 }
5675
5676 // Visit the children of this block in the dominator tree.
5677 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5678 I != E; ++I) {
5679 Changed |= VisitNode(*I, TLSBaseAddrReg);
5680 }
5681
5682 return Changed;
5683 }
5684
5685 // Replace the TLS_base_addr instruction I with a copy from
5686 // TLSBaseAddrReg, returning the new instruction.
5687 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5688 unsigned TLSBaseAddrReg) {
5689 MachineFunction *MF = I->getParent()->getParent();
5690 const X86TargetMachine *TM =
5691 static_cast<const X86TargetMachine *>(&MF->getTarget());
5692 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]5693 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5694
5695 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5696 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5697 TII->get(TargetOpcode::COPY),
5698 is64Bit ? X86::RAX : X86::EAX)
5699 .addReg(TLSBaseAddrReg);
5700
5701 // Erase the TLS_base_addr instruction.
5702 I->eraseFromParent();
5703
5704 return Copy;
5705 }
5706
5707 // Create a virtal register in *TLSBaseAddrReg, and populate it by
5708 // inserting a copy instruction after I. Returns the new instruction.
5709 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5710 MachineFunction *MF = I->getParent()->getParent();
5711 const X86TargetMachine *TM =
5712 static_cast<const X86TargetMachine *>(&MF->getTarget());
5713 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]5714 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5715
5716 // Create a virtual register for the TLS base address.
5717 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5718 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5719 ? &X86::GR64RegClass
5720 : &X86::GR32RegClass);
5721
5722 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5723 MachineInstr *Next = I->getNextNode();
5724 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5725 TII->get(TargetOpcode::COPY),
5726 *TLSBaseAddrReg)
5727 .addReg(is64Bit ? X86::RAX : X86::EAX);
5728
5729 return Copy;
5730 }
5731
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5732 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5733 return "Local Dynamic TLS Access Clean-up";
5734 }
5735
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5736 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5737 AU.setPreservesCFG();
5738 AU.addRequired<MachineDominatorTree>();
5739 MachineFunctionPass::getAnalysisUsage(AU);
5740 }
5741 };
5742}
5743
5744char LDTLSCleanup::ID = 0;
5745FunctionPass*
5746llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }