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gerrit-public.fairphone.software / toolchain / llvm-project / 41a24b7b139a63225c03b8dd8c25c335d611dec3 / . / llvm / lib / Target / Hexagon / HexagonPatternsHVX.td
blob: 9c313abee8b81a433b99b7c7c5c47e1c6d92680e [file] [log] [blame]
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]1def SDTVecLeaf:
2 SDTypeProfile<1, 0, [SDTCisVec<0>]>;
3def SDTVecBinOp:
4 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>]>;
5
6def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2,
7 [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>;
8def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>;
9
10def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,
11 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]12def HexagonVINSERTW0: SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
13
14def SDTHexagonVSPLATW: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
15def HexagonVSPLATW: SDNode<"HexagonISD::VSPLATW", SDTHexagonVSPLATW>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]16
17def HwLen2: SDNodeXForm<imm, [{
18 const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget());
19 return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);
20}]>;
21
22def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (A2_tfrsi -1))>;
23
24def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt),
25 (REG_SEQUENCE HvxWR, $Vs, vsub_hi, $Vt, vsub_lo)>;
26
27def Combineq: OutPatFrag<(ops node:$Qs, node:$Qt),
28 (V6_vandvrt
29 (V6_vor
30 (V6_vror (V6_vpackeb (V6_vd0), (Q2V $Qs)),
31 (A2_tfrsi (HwLen2 (i32 0)))), // Half the vector length
32 (V6_vpackeb (V6_vd0), (Q2V $Qt))),
33 (A2_tfrsi -1))>;
34
35def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
36def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
37
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]38def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
39def HexagonQCAT: SDNode<"HexagonISD::QCAT", SDTVecBinOp>;
40def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>;
41def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>;
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]42
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]43def vzero: PatFrag<(ops), (HexagonVZERO)>;
44def qtrue: PatFrag<(ops), (HexagonQTRUE)>;
45def qfalse: PatFrag<(ops), (HexagonQFALSE)>;
46def qcat: PatFrag<(ops node:$Qs, node:$Qt),
47 (HexagonQCAT node:$Qs, node:$Qt)>;
48
49def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>;
50
51def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>;
52def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>;
53def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>;
54def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>;
55
56def SplatB: SDNodeXForm<imm, [{
57 uint32_t V = N->getZExtValue();
58 assert(isUInt<8>(V));
59 uint32_t S = V << 24 | V << 16 | V << 8 | V;
60 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32);
61}]>;
62
63def SplatH: SDNodeXForm<imm, [{
64 uint32_t V = N->getZExtValue();
65 assert(isUInt<16>(V));
66 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32);
67}]>;
68
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]69def IsVecOff : PatLeaf<(i32 imm), [{
70 int32_t V = N->getSExtValue();
71 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
72 assert(isPowerOf2_32(VecSize));
73 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
74 return false;
75 int32_t L = Log2_32(VecSize);
76 return isInt<4>(V >> L);
77}]>;
78
79
80def alignedload: PatFrag<(ops node:$a), (load $a), [{
81 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
82}]>;
83
84def unalignedload: PatFrag<(ops node:$a), (load $a), [{
85 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
86}]>;
87
88def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
89 return isAlignedMemNode(dyn_cast<MemSDNode>(N));
90}]>;
91
92def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
93 return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
94}]>;
95
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]96
97// HVX loads
98
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]99multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]100 PatFrag ImmPred> {
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]101 def: Pat<(ResType (Load I32:$Rt)),
102 (MI I32:$Rt, 0)>;
103 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
104 (MI I32:$Rt, imm:$s)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]105 // The HVX selection code for shuffles can generate vector constants.
106 // Calling "Select" on the resulting loads from CP fails without these
107 // patterns.
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]108 def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
109 (MI (A2_tfrsi imm:$A), 0)>;
110 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]111 (MI (C4_addipc imm:$A), 0)>;
112}
113
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]114multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
115 PatFrag ImmPred> {
116 let AddedComplexity = 50 in {
117 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
118 (MI I32:$Rt, 0)>;
119 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
120 (MI I32:$Rt, imm:$Off)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]121 }
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]122 defm: HvxLd_pat<MI, Load, ResType, ImmPred>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]123}
124
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]125let Predicates = [UseHVX] in {
126 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI8, IsVecOff>;
127 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI16, IsVecOff>;
128 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI32, IsVecOff>;
129
130 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>;
131 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;
132 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;
133
134 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>;
135 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>;
136 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>;
137}
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]138
139// HVX stores
140
141multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
142 PatFrag Value> {
143 def: Pat<(Store Value:$Vs, I32:$Rt),
144 (MI I32:$Rt, 0, Value:$Vs)>;
145 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
146 (MI I32:$Rt, imm:$s, Value:$Vs)>;
147}
148
149let Predicates = [UseHVX] in {
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]150 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI8>;
151 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI16>;
152 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI32>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]153
Krzysztof Parzyszekad83ce42018-02-14 20:46:06 +0000[diff] [blame]154 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI8>;
155 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI16>;
156 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI32>;
157
158 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI8>;
159 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI16>;
160 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI32>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]161}
162
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]163// Bitcasts between same-size vector types are no-ops, except for the
164// actual type change.
165class Bitcast<ValueType ResTy, ValueType InpTy, RegisterClass RC>
166 : Pat<(ResTy (bitconvert (InpTy RC:$Val))), (ResTy RC:$Val)>;
167
168let Predicates = [UseHVX] in {
169 def: Bitcast<VecI8, VecI16, HvxVR>;
170 def: Bitcast<VecI8, VecI32, HvxVR>;
171 def: Bitcast<VecI16, VecI8, HvxVR>;
172 def: Bitcast<VecI16, VecI32, HvxVR>;
173 def: Bitcast<VecI32, VecI8, HvxVR>;
174 def: Bitcast<VecI32, VecI16, HvxVR>;
175
176 def: Bitcast<VecPI8, VecPI16, HvxWR>;
177 def: Bitcast<VecPI8, VecPI32, HvxWR>;
178 def: Bitcast<VecPI16, VecPI8, HvxWR>;
179 def: Bitcast<VecPI16, VecPI32, HvxWR>;
180 def: Bitcast<VecPI32, VecPI8, HvxWR>;
181 def: Bitcast<VecPI32, VecPI16, HvxWR>;
182}
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]183
184let Predicates = [UseHVX] in {
185 def: Pat<(VecI8 vzero), (V6_vd0)>;
186 def: Pat<(VecI16 vzero), (V6_vd0)>;
187 def: Pat<(VecI32 vzero), (V6_vd0)>;
188 // Use V6_vsubw_dv instead.
189 def: Pat<(VecPI8 vzero), (Combinev (V6_vd0), (V6_vd0))>;
190 def: Pat<(VecPI16 vzero), (Combinev (V6_vd0), (V6_vd0))>;
191 def: Pat<(VecPI32 vzero), (Combinev (V6_vd0), (V6_vd0))>;
192
193 def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
194 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
195 def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
196 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
197 def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),
198 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
199
200 def: Pat<(VecQ8 (qcat HQ16:$Qs, HQ16:$Qt)), (Combineq $Qs, $Qt)>;
201 def: Pat<(VecQ16 (qcat HQ32:$Qs, HQ32:$Qt)), (Combineq $Qs, $Qt)>;
202
203 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
204 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
205 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
206 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
207 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
208 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
209
210 def: Pat<(HexagonVINSERTW0 HVI8:$Vu, I32:$Rt),
211 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
212 def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt),
213 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
214 def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt),
215 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]216}
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]217
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]218def Vsplatib: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatB $V)))>;
219def Vsplatih: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatH $V)))>;
220def Vsplatiw: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 $V))>;
221
222def Vsplatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>;
223def Vsplatrh: OutPatFrag<(ops node:$Rs),
224 (V6_lvsplatw (A2_combine_ll $Rs, $Rs))>;
225def Vsplatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
226
227def Rep: OutPatFrag<(ops node:$N), (Combinev $N, $N)>;
228
229let Predicates = [UseHVX] in {
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]230 let AddedComplexity = 10 in {
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]231 def: Pat<(VecI8 (HexagonVSPLAT u8_0ImmPred:$V)), (Vsplatib $V)>;
232 def: Pat<(VecI16 (HexagonVSPLAT u16_0ImmPred:$V)), (Vsplatih $V)>;
233 def: Pat<(VecI32 (HexagonVSPLAT anyimm:$V)), (Vsplatiw $V)>;
234 def: Pat<(VecPI8 (HexagonVSPLAT u8_0ImmPred:$V)), (Rep (Vsplatib $V))>;
235 def: Pat<(VecPI16 (HexagonVSPLAT u16_0ImmPred:$V)), (Rep (Vsplatih $V))>;
236 def: Pat<(VecPI32 (HexagonVSPLAT anyimm:$V)), (Rep (Vsplatiw $V))>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]237 }
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]238 def: Pat<(VecI8 (HexagonVSPLAT I32:$Rs)), (Vsplatrb $Rs)>;
239 def: Pat<(VecI16 (HexagonVSPLAT I32:$Rs)), (Vsplatrh $Rs)>;
240 def: Pat<(VecI32 (HexagonVSPLAT I32:$Rs)), (Vsplatrw $Rs)>;
241 def: Pat<(VecPI8 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrb $Rs))>;
242 def: Pat<(VecPI16 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrh $Rs))>;
243 def: Pat<(VecPI32 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrw $Rs))>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]244
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]245 def: Pat<(VecI8 (HexagonVSPLATW I32:$Rs)), (V6_lvsplatw I32:$Rs)>;
246 def: Pat<(VecI16 (HexagonVSPLATW I32:$Rs)), (V6_lvsplatw I32:$Rs)>;
247 def: Pat<(VecI32 (HexagonVSPLATW I32:$Rs)), (V6_lvsplatw I32:$Rs)>;
248 def: Pat<(VecPI8 (HexagonVSPLATW I32:$Rs)), (Rep (V6_lvsplatw I32:$Rs))>;
249 def: Pat<(VecPI16 (HexagonVSPLATW I32:$Rs)), (Rep (V6_lvsplatw I32:$Rs))>;
250 def: Pat<(VecPI32 (HexagonVSPLATW I32:$Rs)), (Rep (V6_lvsplatw I32:$Rs))>;
251}
252
253let Predicates = [UseHVX] in {
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]254 def: Pat<(add HVI8:$Vs, HVI8:$Vt), (V6_vaddb HvxVR:$Vs, HvxVR:$Vt)>;
255 def: Pat<(add HVI16:$Vs, HVI16:$Vt), (V6_vaddh HvxVR:$Vs, HvxVR:$Vt)>;
256 def: Pat<(add HVI32:$Vs, HVI32:$Vt), (V6_vaddw HvxVR:$Vs, HvxVR:$Vt)>;
257 def: Pat<(add HWI8:$Vs, HWI8:$Vt), (V6_vaddb_dv HvxWR:$Vs, HvxWR:$Vt)>;
258 def: Pat<(add HWI16:$Vs, HWI16:$Vt), (V6_vaddh_dv HvxWR:$Vs, HvxWR:$Vt)>;
259 def: Pat<(add HWI32:$Vs, HWI32:$Vt), (V6_vaddw_dv HvxWR:$Vs, HvxWR:$Vt)>;
260
261 def: Pat<(sub HVI8:$Vs, HVI8:$Vt), (V6_vsubb HvxVR:$Vs, HvxVR:$Vt)>;
262 def: Pat<(sub HVI16:$Vs, HVI16:$Vt), (V6_vsubh HvxVR:$Vs, HvxVR:$Vt)>;
263 def: Pat<(sub HVI32:$Vs, HVI32:$Vt), (V6_vsubw HvxVR:$Vs, HvxVR:$Vt)>;
264 def: Pat<(sub HWI8:$Vs, HWI8:$Vt), (V6_vsubb_dv HvxWR:$Vs, HvxWR:$Vt)>;
265 def: Pat<(sub HWI16:$Vs, HWI16:$Vt), (V6_vsubh_dv HvxWR:$Vs, HvxWR:$Vt)>;
266 def: Pat<(sub HWI32:$Vs, HWI32:$Vt), (V6_vsubw_dv HvxWR:$Vs, HvxWR:$Vt)>;
267
268 def: Pat<(and HVI8:$Vs, HVI8:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]269 def: Pat<(and HVI16:$Vs, HVI16:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
270 def: Pat<(and HVI32:$Vs, HVI32:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]271 def: Pat<(or HVI8:$Vs, HVI8:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]272 def: Pat<(or HVI16:$Vs, HVI16:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
273 def: Pat<(or HVI32:$Vs, HVI32:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]274 def: Pat<(xor HVI8:$Vs, HVI8:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
Krzysztof Parzyszek41a24b72018-04-20 19:38:37 +0000[diff] [blame^]275 def: Pat<(xor HVI16:$Vs, HVI16:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
276 def: Pat<(xor HVI32:$Vs, HVI32:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]277
278 def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
279 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
280 def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),
281 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
282 def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
283 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
284
285 def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt),
286 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
287 def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt),
288 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
289 def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt),
290 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
291
292 def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>;
293 def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;
294 def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>;
295 def: Pat<(VecPI32 (zext HVI16:$Vs)), (VZxth $Vs)>;
296
297 def: Pat<(VecI16 (sext_invec HVI8:$Vs)), (LoVec (VSxtb $Vs))>;
298 def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (VSxth $Vs))>;
299 def: Pat<(VecI32 (sext_invec HVI8:$Vs)),
300 (LoVec (VSxth (LoVec (VSxtb $Vs))))>;
301 def: Pat<(VecPI16 (sext_invec HWI8:$Vss)), (VSxtb (LoVec $Vss))>;
302 def: Pat<(VecPI32 (sext_invec HWI16:$Vss)), (VSxth (LoVec $Vss))>;
303 def: Pat<(VecPI32 (sext_invec HWI8:$Vss)),
304 (VSxth (LoVec (VSxtb (LoVec $Vss))))>;
305
306 def: Pat<(VecI16 (zext_invec HVI8:$Vs)), (LoVec (VZxtb $Vs))>;
307 def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (VZxth $Vs))>;
308 def: Pat<(VecI32 (zext_invec HVI8:$Vs)),
309 (LoVec (VZxth (LoVec (VZxtb $Vs))))>;
310 def: Pat<(VecPI16 (zext_invec HWI8:$Vss)), (VZxtb (LoVec $Vss))>;
311 def: Pat<(VecPI32 (zext_invec HWI16:$Vss)), (VZxth (LoVec $Vss))>;
312 def: Pat<(VecPI32 (zext_invec HWI8:$Vss)),
313 (VZxth (LoVec (VZxtb (LoVec $Vss))))>;
314
315 // The "source" types are not legal, and there are no parameterized
316 // definitions for them, but they are length-specific.
317 let Predicates = [UseHVX,UseHVX64B] in {
318 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)),
319 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
320 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i8)),
321 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
322 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),
323 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
324 }
325 let Predicates = [UseHVX,UseHVX128B] in {
326 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),
327 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
328 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)),
329 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
330 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),
331 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
332 }
333
334 def: Pat<(HexagonVASL HVI8:$Vs, I32:$Rt),
335 (V6_vpackeb (V6_vaslh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
336 (V6_vaslh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
337 def: Pat<(HexagonVASR HVI8:$Vs, I32:$Rt),
338 (V6_vpackeb (V6_vasrh (HiVec (VSxtb HvxVR:$Vs)), I32:$Rt),
339 (V6_vasrh (LoVec (VSxtb HvxVR:$Vs)), I32:$Rt))>;
340 def: Pat<(HexagonVLSR HVI8:$Vs, I32:$Rt),
341 (V6_vpackeb (V6_vlsrh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
342 (V6_vlsrh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
343
344 def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>;
345 def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>;
346 def: Pat<(HexagonVASR HVI16:$Vs, I32:$Rt), (V6_vasrh HvxVR:$Vs, I32:$Rt)>;
347 def: Pat<(HexagonVASR HVI32:$Vs, I32:$Rt), (V6_vasrw HvxVR:$Vs, I32:$Rt)>;
348 def: Pat<(HexagonVLSR HVI16:$Vs, I32:$Rt), (V6_vlsrh HvxVR:$Vs, I32:$Rt)>;
349 def: Pat<(HexagonVLSR HVI32:$Vs, I32:$Rt), (V6_vlsrw HvxVR:$Vs, I32:$Rt)>;
350
351 def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;
352 def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;
353 def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
354 def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;
355 def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
356 def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
357
Krzysztof Parzyszek9b48e8d2018-02-09 19:10:46 +0000[diff] [blame]358 def: Pat<(VecQ8 (qtrue)), (PS_qtrue)>;
359 def: Pat<(VecQ16 (qtrue)), (PS_qtrue)>;
360 def: Pat<(VecQ32 (qtrue)), (PS_qtrue)>;
361 def: Pat<(VecQ8 (qfalse)), (PS_qfalse)>;
362 def: Pat<(VecQ16 (qfalse)), (PS_qfalse)>;
363 def: Pat<(VecQ32 (qfalse)), (PS_qfalse)>;
364
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]365 def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
366 def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
367 def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
368 def: Pat<(qnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
369 def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
370 def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
371
372 def: Pat<(VecQ8 (seteq HVI8:$Vs, HVI8:$Vt)),
373 (V6_veqb HvxVR:$Vs, HvxVR:$Vt)>;
374 def: Pat<(VecQ8 (setgt HVI8:$Vs, HVI8:$Vt)),
375 (V6_vgtb HvxVR:$Vs, HvxVR:$Vt)>;
376 def: Pat<(VecQ8 (setugt HVI8:$Vs, HVI8:$Vt)),
377 (V6_vgtub HvxVR:$Vs, HvxVR:$Vt)>;
378 def: Pat<(VecQ16 (seteq HVI16:$Vs, HVI16:$Vt)),
379 (V6_veqh HvxVR:$Vs, HvxVR:$Vt)>;
380 def: Pat<(VecQ16 (setgt HVI16:$Vs, HVI16:$Vt)),
381 (V6_vgth HvxVR:$Vs, HvxVR:$Vt)>;
382 def: Pat<(VecQ16 (setugt HVI16:$Vs, HVI16:$Vt)),
383 (V6_vgtuh HvxVR:$Vs, HvxVR:$Vt)>;
384 def: Pat<(VecQ32 (seteq HVI32:$Vs, HVI32:$Vt)),
385 (V6_veqw HvxVR:$Vs, HvxVR:$Vt)>;
386 def: Pat<(VecQ32 (setgt HVI32:$Vs, HVI32:$Vt)),
387 (V6_vgtw HvxVR:$Vs, HvxVR:$Vt)>;
388 def: Pat<(VecQ32 (setugt HVI32:$Vs, HVI32:$Vt)),
389 (V6_vgtuw HvxVR:$Vs, HvxVR:$Vt)>;
390
391 def: Pat<(VecI8 (trunc HWI16:$Vss)),
392 (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
393 def: Pat<(VecI16 (trunc HWI32:$Vss)),
394 (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
Krzysztof Parzyszekd92c37e2018-04-19 14:46:44 +0000[diff] [blame]395
396 def: Pat<(VecI16 (bswap HVI16:$Vs)),
397 (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
398 def: Pat<(VecI32 (bswap HVI32:$Vs)),
399 (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame]400}
401
402class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
403 : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
404 (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
405
406let Predicates = [HasV60T,UseHVX] in {
407 def: HvxSel_pat<PS_vselect, HVI8>;
408 def: HvxSel_pat<PS_vselect, HVI16>;
409 def: HvxSel_pat<PS_vselect, HVI32>;
410 def: HvxSel_pat<PS_wselect, HWI8>;
411 def: HvxSel_pat<PS_wselect, HWI16>;
412 def: HvxSel_pat<PS_wselect, HWI32>;
413}
414