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gerrit-public.fairphone.software / toolchain / llvm-project / 50e5ed3d0877da178ac224012d8cf1c3687859b1 / . / llvm / test / CodeGen / Mips / msa / arithmetic.ll
blob: 512a1c1824b0f0eec6662fd737134bd70aeb9a86 [file] [log] [blame]
Daniel Sanders1b1e25b2013-09-27 10:08:31 +0000[diff] [blame]1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]2
3define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
4 ; CHECK: add_v16i8:
5
6 %1 = load <16 x i8>* %a
7 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
8 %2 = load <16 x i8>* %b
9 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
10 %3 = add <16 x i8> %1, %2
11 ; CHECK-DAG: addv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
12 store <16 x i8> %3, <16 x i8>* %c
13 ; CHECK-DAG: st.b [[R3]], 0($4)
14
15 ret void
16 ; CHECK: .size add_v16i8
17}
18
19define void @add_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
20 ; CHECK: add_v8i16:
21
22 %1 = load <8 x i16>* %a
23 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
24 %2 = load <8 x i16>* %b
25 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
26 %3 = add <8 x i16> %1, %2
27 ; CHECK-DAG: addv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
28 store <8 x i16> %3, <8 x i16>* %c
29 ; CHECK-DAG: st.h [[R3]], 0($4)
30
31 ret void
32 ; CHECK: .size add_v8i16
33}
34
35define void @add_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
36 ; CHECK: add_v4i32:
37
38 %1 = load <4 x i32>* %a
39 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
40 %2 = load <4 x i32>* %b
41 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
42 %3 = add <4 x i32> %1, %2
43 ; CHECK-DAG: addv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
44 store <4 x i32> %3, <4 x i32>* %c
45 ; CHECK-DAG: st.w [[R3]], 0($4)
46
47 ret void
48 ; CHECK: .size add_v4i32
49}
50
51define void @add_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
52 ; CHECK: add_v2i64:
53
54 %1 = load <2 x i64>* %a
55 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
56 %2 = load <2 x i64>* %b
57 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
58 %3 = add <2 x i64> %1, %2
59 ; CHECK-DAG: addv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
60 store <2 x i64> %3, <2 x i64>* %c
61 ; CHECK-DAG: st.d [[R3]], 0($4)
62
63 ret void
64 ; CHECK: .size add_v2i64
65}
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]66
67define void @add_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
68 ; CHECK: add_v16i8_i:
69
70 %1 = load <16 x i8>* %a
71 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]72 %2 = add <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
73 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]74 ; CHECK-DAG: addvi.b [[R3:\$w[0-9]+]], [[R1]], 1
75 store <16 x i8> %2, <16 x i8>* %c
76 ; CHECK-DAG: st.b [[R3]], 0($4)
77
78 ret void
79 ; CHECK: .size add_v16i8_i
80}
81
82define void @add_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
83 ; CHECK: add_v8i16_i:
84
85 %1 = load <8 x i16>* %a
86 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]87 %2 = add <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,
88 i16 1, i16 1, i16 1, i16 1>
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]89 ; CHECK-DAG: addvi.h [[R3:\$w[0-9]+]], [[R1]], 1
90 store <8 x i16> %2, <8 x i16>* %c
91 ; CHECK-DAG: st.h [[R3]], 0($4)
92
93 ret void
94 ; CHECK: .size add_v8i16_i
95}
96
97define void @add_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
98 ; CHECK: add_v4i32_i:
99
100 %1 = load <4 x i32>* %a
101 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
102 %2 = add <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
103 ; CHECK-DAG: addvi.w [[R3:\$w[0-9]+]], [[R1]], 1
104 store <4 x i32> %2, <4 x i32>* %c
105 ; CHECK-DAG: st.w [[R3]], 0($4)
106
107 ret void
108 ; CHECK: .size add_v4i32_i
109}
110
111define void @add_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
112 ; CHECK: add_v2i64_i:
113
114 %1 = load <2 x i64>* %a
115 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
116 %2 = add <2 x i64> %1, <i64 1, i64 1>
117 ; CHECK-DAG: addvi.d [[R3:\$w[0-9]+]], [[R1]], 1
118 store <2 x i64> %2, <2 x i64>* %c
119 ; CHECK-DAG: st.d [[R3]], 0($4)
120
121 ret void
122 ; CHECK: .size add_v2i64_i
123}
124
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]125define void @sub_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
126 ; CHECK: sub_v16i8:
127
128 %1 = load <16 x i8>* %a
129 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
130 %2 = load <16 x i8>* %b
131 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
132 %3 = sub <16 x i8> %1, %2
133 ; CHECK-DAG: subv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
134 store <16 x i8> %3, <16 x i8>* %c
135 ; CHECK-DAG: st.b [[R3]], 0($4)
136
137 ret void
138 ; CHECK: .size sub_v16i8
139}
140
141define void @sub_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
142 ; CHECK: sub_v8i16:
143
144 %1 = load <8 x i16>* %a
145 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
146 %2 = load <8 x i16>* %b
147 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
148 %3 = sub <8 x i16> %1, %2
149 ; CHECK-DAG: subv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
150 store <8 x i16> %3, <8 x i16>* %c
151 ; CHECK-DAG: st.h [[R3]], 0($4)
152
153 ret void
154 ; CHECK: .size sub_v8i16
155}
156
157define void @sub_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
158 ; CHECK: sub_v4i32:
159
160 %1 = load <4 x i32>* %a
161 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
162 %2 = load <4 x i32>* %b
163 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
164 %3 = sub <4 x i32> %1, %2
165 ; CHECK-DAG: subv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
166 store <4 x i32> %3, <4 x i32>* %c
167 ; CHECK-DAG: st.w [[R3]], 0($4)
168
169 ret void
170 ; CHECK: .size sub_v4i32
171}
172
173define void @sub_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
174 ; CHECK: sub_v2i64:
175
176 %1 = load <2 x i64>* %a
177 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
178 %2 = load <2 x i64>* %b
179 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
180 %3 = sub <2 x i64> %1, %2
181 ; CHECK-DAG: subv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
182 store <2 x i64> %3, <2 x i64>* %c
183 ; CHECK-DAG: st.d [[R3]], 0($4)
184
185 ret void
186 ; CHECK: .size sub_v2i64
187}
188
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]189define void @sub_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
190 ; CHECK: sub_v16i8_i:
191
192 %1 = load <16 x i8>* %a
193 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]194 %2 = sub <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
195 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]196 ; CHECK-DAG: subvi.b [[R3:\$w[0-9]+]], [[R1]], 1
197 store <16 x i8> %2, <16 x i8>* %c
198 ; CHECK-DAG: st.b [[R3]], 0($4)
199
200 ret void
201 ; CHECK: .size sub_v16i8_i
202}
203
204define void @sub_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
205 ; CHECK: sub_v8i16_i:
206
207 %1 = load <8 x i16>* %a
208 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]209 %2 = sub <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,
210 i16 1, i16 1, i16 1, i16 1>
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]211 ; CHECK-DAG: subvi.h [[R3:\$w[0-9]+]], [[R1]], 1
212 store <8 x i16> %2, <8 x i16>* %c
213 ; CHECK-DAG: st.h [[R3]], 0($4)
214
215 ret void
216 ; CHECK: .size sub_v8i16_i
217}
218
219define void @sub_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
220 ; CHECK: sub_v4i32_i:
221
222 %1 = load <4 x i32>* %a
223 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
224 %2 = sub <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
225 ; CHECK-DAG: subvi.w [[R3:\$w[0-9]+]], [[R1]], 1
226 store <4 x i32> %2, <4 x i32>* %c
227 ; CHECK-DAG: st.w [[R3]], 0($4)
228
229 ret void
230 ; CHECK: .size sub_v4i32_i
231}
232
233define void @sub_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
234 ; CHECK: sub_v2i64_i:
235
236 %1 = load <2 x i64>* %a
237 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
238 %2 = sub <2 x i64> %1, <i64 1, i64 1>
239 ; CHECK-DAG: subvi.d [[R3:\$w[0-9]+]], [[R1]], 1
240 store <2 x i64> %2, <2 x i64>* %c
241 ; CHECK-DAG: st.d [[R3]], 0($4)
242
243 ret void
244 ; CHECK: .size sub_v2i64_i
245}
246
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]247define void @mul_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
248 ; CHECK: mul_v16i8:
249
250 %1 = load <16 x i8>* %a
251 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
252 %2 = load <16 x i8>* %b
253 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
254 %3 = mul <16 x i8> %1, %2
255 ; CHECK-DAG: mulv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
256 store <16 x i8> %3, <16 x i8>* %c
257 ; CHECK-DAG: st.b [[R3]], 0($4)
258
259 ret void
260 ; CHECK: .size mul_v16i8
261}
262
263define void @mul_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
264 ; CHECK: mul_v8i16:
265
266 %1 = load <8 x i16>* %a
267 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
268 %2 = load <8 x i16>* %b
269 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
270 %3 = mul <8 x i16> %1, %2
271 ; CHECK-DAG: mulv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
272 store <8 x i16> %3, <8 x i16>* %c
273 ; CHECK-DAG: st.h [[R3]], 0($4)
274
275 ret void
276 ; CHECK: .size mul_v8i16
277}
278
279define void @mul_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
280 ; CHECK: mul_v4i32:
281
282 %1 = load <4 x i32>* %a
283 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
284 %2 = load <4 x i32>* %b
285 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
286 %3 = mul <4 x i32> %1, %2
287 ; CHECK-DAG: mulv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
288 store <4 x i32> %3, <4 x i32>* %c
289 ; CHECK-DAG: st.w [[R3]], 0($4)
290
291 ret void
292 ; CHECK: .size mul_v4i32
293}
294
295define void @mul_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
296 ; CHECK: mul_v2i64:
297
298 %1 = load <2 x i64>* %a
299 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
300 %2 = load <2 x i64>* %b
301 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
302 %3 = mul <2 x i64> %1, %2
303 ; CHECK-DAG: mulv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
304 store <2 x i64> %3, <2 x i64>* %c
305 ; CHECK-DAG: st.d [[R3]], 0($4)
306
307 ret void
308 ; CHECK: .size mul_v2i64
309}
310
Daniel Sanders50e5ed32013-10-11 10:50:42 +0000[diff] [blame^]311define void @maddv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
312 <16 x i8>* %c) nounwind {
313 ; CHECK: maddv_v16i8:
314
315 %1 = load <16 x i8>* %a
316 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
317 %2 = load <16 x i8>* %b
318 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
319 %3 = load <16 x i8>* %c
320 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
321 %4 = mul <16 x i8> %2, %3
322 %5 = add <16 x i8> %4, %1
323 ; CHECK-DAG: maddv.b [[R1]], [[R2]], [[R3]]
324 store <16 x i8> %5, <16 x i8>* %d
325 ; CHECK-DAG: st.b [[R1]], 0($4)
326
327 ret void
328 ; CHECK: .size maddv_v16i8
329}
330
331define void @maddv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
332 <8 x i16>* %c) nounwind {
333 ; CHECK: maddv_v8i16:
334
335 %1 = load <8 x i16>* %a
336 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
337 %2 = load <8 x i16>* %b
338 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
339 %3 = load <8 x i16>* %c
340 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
341 %4 = mul <8 x i16> %2, %3
342 %5 = add <8 x i16> %4, %1
343 ; CHECK-DAG: maddv.h [[R1]], [[R2]], [[R3]]
344 store <8 x i16> %5, <8 x i16>* %d
345 ; CHECK-DAG: st.h [[R1]], 0($4)
346
347 ret void
348 ; CHECK: .size maddv_v8i16
349}
350
351define void @maddv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
352 <4 x i32>* %c) nounwind {
353 ; CHECK: maddv_v4i32:
354
355 %1 = load <4 x i32>* %a
356 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
357 %2 = load <4 x i32>* %b
358 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
359 %3 = load <4 x i32>* %c
360 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
361 %4 = mul <4 x i32> %2, %3
362 %5 = add <4 x i32> %4, %1
363 ; CHECK-DAG: maddv.w [[R1]], [[R2]], [[R3]]
364 store <4 x i32> %5, <4 x i32>* %d
365 ; CHECK-DAG: st.w [[R1]], 0($4)
366
367 ret void
368 ; CHECK: .size maddv_v4i32
369}
370
371define void @maddv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
372 <2 x i64>* %c) nounwind {
373 ; CHECK: maddv_v2i64:
374
375 %1 = load <2 x i64>* %a
376 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
377 %2 = load <2 x i64>* %b
378 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
379 %3 = load <2 x i64>* %c
380 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
381 %4 = mul <2 x i64> %2, %3
382 %5 = add <2 x i64> %4, %1
383 ; CHECK-DAG: maddv.d [[R1]], [[R2]], [[R3]]
384 store <2 x i64> %5, <2 x i64>* %d
385 ; CHECK-DAG: st.d [[R1]], 0($4)
386
387 ret void
388 ; CHECK: .size maddv_v2i64
389}
390
391define void @msubv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
392 <16 x i8>* %c) nounwind {
393 ; CHECK: msubv_v16i8:
394
395 %1 = load <16 x i8>* %a
396 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
397 %2 = load <16 x i8>* %b
398 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
399 %3 = load <16 x i8>* %c
400 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
401 %4 = mul <16 x i8> %2, %3
402 %5 = sub <16 x i8> %1, %4
403 ; CHECK-DAG: msubv.b [[R1]], [[R2]], [[R3]]
404 store <16 x i8> %5, <16 x i8>* %d
405 ; CHECK-DAG: st.b [[R1]], 0($4)
406
407 ret void
408 ; CHECK: .size msubv_v16i8
409}
410
411define void @msubv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
412 <8 x i16>* %c) nounwind {
413 ; CHECK: msubv_v8i16:
414
415 %1 = load <8 x i16>* %a
416 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
417 %2 = load <8 x i16>* %b
418 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
419 %3 = load <8 x i16>* %c
420 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
421 %4 = mul <8 x i16> %2, %3
422 %5 = sub <8 x i16> %1, %4
423 ; CHECK-DAG: msubv.h [[R1]], [[R2]], [[R3]]
424 store <8 x i16> %5, <8 x i16>* %d
425 ; CHECK-DAG: st.h [[R1]], 0($4)
426
427 ret void
428 ; CHECK: .size msubv_v8i16
429}
430
431define void @msubv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
432 <4 x i32>* %c) nounwind {
433 ; CHECK: msubv_v4i32:
434
435 %1 = load <4 x i32>* %a
436 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
437 %2 = load <4 x i32>* %b
438 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
439 %3 = load <4 x i32>* %c
440 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
441 %4 = mul <4 x i32> %2, %3
442 %5 = sub <4 x i32> %1, %4
443 ; CHECK-DAG: msubv.w [[R1]], [[R2]], [[R3]]
444 store <4 x i32> %5, <4 x i32>* %d
445 ; CHECK-DAG: st.w [[R1]], 0($4)
446
447 ret void
448 ; CHECK: .size msubv_v4i32
449}
450
451define void @msubv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
452 <2 x i64>* %c) nounwind {
453 ; CHECK: msubv_v2i64:
454
455 %1 = load <2 x i64>* %a
456 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
457 %2 = load <2 x i64>* %b
458 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
459 %3 = load <2 x i64>* %c
460 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
461 %4 = mul <2 x i64> %2, %3
462 %5 = sub <2 x i64> %1, %4
463 ; CHECK-DAG: msubv.d [[R1]], [[R2]], [[R3]]
464 store <2 x i64> %5, <2 x i64>* %d
465 ; CHECK-DAG: st.d [[R1]], 0($4)
466
467 ret void
468 ; CHECK: .size msubv_v2i64
469}
470
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]471define void @div_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
472 ; CHECK: div_s_v16i8:
473
474 %1 = load <16 x i8>* %a
475 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
476 %2 = load <16 x i8>* %b
477 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
478 %3 = sdiv <16 x i8> %1, %2
479 ; CHECK-DAG: div_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
480 store <16 x i8> %3, <16 x i8>* %c
481 ; CHECK-DAG: st.b [[R3]], 0($4)
482
483 ret void
484 ; CHECK: .size div_s_v16i8
485}
486
487define void @div_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
488 ; CHECK: div_s_v8i16:
489
490 %1 = load <8 x i16>* %a
491 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
492 %2 = load <8 x i16>* %b
493 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
494 %3 = sdiv <8 x i16> %1, %2
495 ; CHECK-DAG: div_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
496 store <8 x i16> %3, <8 x i16>* %c
497 ; CHECK-DAG: st.h [[R3]], 0($4)
498
499 ret void
500 ; CHECK: .size div_s_v8i16
501}
502
503define void @div_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
504 ; CHECK: div_s_v4i32:
505
506 %1 = load <4 x i32>* %a
507 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
508 %2 = load <4 x i32>* %b
509 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
510 %3 = sdiv <4 x i32> %1, %2
511 ; CHECK-DAG: div_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
512 store <4 x i32> %3, <4 x i32>* %c
513 ; CHECK-DAG: st.w [[R3]], 0($4)
514
515 ret void
516 ; CHECK: .size div_s_v4i32
517}
518
519define void @div_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
520 ; CHECK: div_s_v2i64:
521
522 %1 = load <2 x i64>* %a
523 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
524 %2 = load <2 x i64>* %b
525 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
526 %3 = sdiv <2 x i64> %1, %2
527 ; CHECK-DAG: div_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
528 store <2 x i64> %3, <2 x i64>* %c
529 ; CHECK-DAG: st.d [[R3]], 0($4)
530
531 ret void
532 ; CHECK: .size div_s_v2i64
533}
534
535define void @div_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
536 ; CHECK: div_u_v16i8:
537
538 %1 = load <16 x i8>* %a
539 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
540 %2 = load <16 x i8>* %b
541 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
542 %3 = udiv <16 x i8> %1, %2
543 ; CHECK-DAG: div_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
544 store <16 x i8> %3, <16 x i8>* %c
545 ; CHECK-DAG: st.b [[R3]], 0($4)
546
547 ret void
548 ; CHECK: .size div_u_v16i8
549}
550
551define void @div_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
552 ; CHECK: div_u_v8i16:
553
554 %1 = load <8 x i16>* %a
555 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
556 %2 = load <8 x i16>* %b
557 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
558 %3 = udiv <8 x i16> %1, %2
559 ; CHECK-DAG: div_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
560 store <8 x i16> %3, <8 x i16>* %c
561 ; CHECK-DAG: st.h [[R3]], 0($4)
562
563 ret void
564 ; CHECK: .size div_u_v8i16
565}
566
567define void @div_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
568 ; CHECK: div_u_v4i32:
569
570 %1 = load <4 x i32>* %a
571 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
572 %2 = load <4 x i32>* %b
573 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
574 %3 = udiv <4 x i32> %1, %2
575 ; CHECK-DAG: div_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
576 store <4 x i32> %3, <4 x i32>* %c
577 ; CHECK-DAG: st.w [[R3]], 0($4)
578
579 ret void
580 ; CHECK: .size div_u_v4i32
581}
582
583define void @div_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
584 ; CHECK: div_u_v2i64:
585
586 %1 = load <2 x i64>* %a
587 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
588 %2 = load <2 x i64>* %b
589 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
590 %3 = udiv <2 x i64> %1, %2
591 ; CHECK-DAG: div_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
592 store <2 x i64> %3, <2 x i64>* %c
593 ; CHECK-DAG: st.d [[R3]], 0($4)
594
595 ret void
596 ; CHECK: .size div_u_v2i64
597}
Daniel Sanders0210dd42013-10-01 10:22:35 +0000[diff] [blame]598
599define void @mod_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
600 ; CHECK: mod_s_v16i8:
601
602 %1 = load <16 x i8>* %a
603 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
604 %2 = load <16 x i8>* %b
605 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
606 %3 = srem <16 x i8> %1, %2
607 ; CHECK-DAG: mod_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
608 store <16 x i8> %3, <16 x i8>* %c
609 ; CHECK-DAG: st.b [[R3]], 0($4)
610
611 ret void
612 ; CHECK: .size mod_s_v16i8
613}
614
615define void @mod_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
616 ; CHECK: mod_s_v8i16:
617
618 %1 = load <8 x i16>* %a
619 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
620 %2 = load <8 x i16>* %b
621 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
622 %3 = srem <8 x i16> %1, %2
623 ; CHECK-DAG: mod_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
624 store <8 x i16> %3, <8 x i16>* %c
625 ; CHECK-DAG: st.h [[R3]], 0($4)
626
627 ret void
628 ; CHECK: .size mod_s_v8i16
629}
630
631define void @mod_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
632 ; CHECK: mod_s_v4i32:
633
634 %1 = load <4 x i32>* %a
635 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
636 %2 = load <4 x i32>* %b
637 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
638 %3 = srem <4 x i32> %1, %2
639 ; CHECK-DAG: mod_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
640 store <4 x i32> %3, <4 x i32>* %c
641 ; CHECK-DAG: st.w [[R3]], 0($4)
642
643 ret void
644 ; CHECK: .size mod_s_v4i32
645}
646
647define void @mod_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
648 ; CHECK: mod_s_v2i64:
649
650 %1 = load <2 x i64>* %a
651 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
652 %2 = load <2 x i64>* %b
653 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
654 %3 = srem <2 x i64> %1, %2
655 ; CHECK-DAG: mod_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
656 store <2 x i64> %3, <2 x i64>* %c
657 ; CHECK-DAG: st.d [[R3]], 0($4)
658
659 ret void
660 ; CHECK: .size mod_s_v2i64
661}
662
663define void @mod_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
664 ; CHECK: mod_u_v16i8:
665
666 %1 = load <16 x i8>* %a
667 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
668 %2 = load <16 x i8>* %b
669 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
670 %3 = urem <16 x i8> %1, %2
671 ; CHECK-DAG: mod_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
672 store <16 x i8> %3, <16 x i8>* %c
673 ; CHECK-DAG: st.b [[R3]], 0($4)
674
675 ret void
676 ; CHECK: .size mod_u_v16i8
677}
678
679define void @mod_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
680 ; CHECK: mod_u_v8i16:
681
682 %1 = load <8 x i16>* %a
683 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
684 %2 = load <8 x i16>* %b
685 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
686 %3 = urem <8 x i16> %1, %2
687 ; CHECK-DAG: mod_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
688 store <8 x i16> %3, <8 x i16>* %c
689 ; CHECK-DAG: st.h [[R3]], 0($4)
690
691 ret void
692 ; CHECK: .size mod_u_v8i16
693}
694
695define void @mod_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
696 ; CHECK: mod_u_v4i32:
697
698 %1 = load <4 x i32>* %a
699 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
700 %2 = load <4 x i32>* %b
701 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
702 %3 = urem <4 x i32> %1, %2
703 ; CHECK-DAG: mod_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
704 store <4 x i32> %3, <4 x i32>* %c
705 ; CHECK-DAG: st.w [[R3]], 0($4)
706
707 ret void
708 ; CHECK: .size mod_u_v4i32
709}
710
711define void @mod_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
712 ; CHECK: mod_u_v2i64:
713
714 %1 = load <2 x i64>* %a
715 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
716 %2 = load <2 x i64>* %b
717 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
718 %3 = urem <2 x i64> %1, %2
719 ; CHECK-DAG: mod_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
720 store <2 x i64> %3, <2 x i64>* %c
721 ; CHECK-DAG: st.d [[R3]], 0($4)
722
723 ret void
724 ; CHECK: .size mod_u_v2i64
725}