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gerrit-public.fairphone.software / toolchain / llvm-project / 54e22f33d9bf2e1225e58d8cb69dad0c64886fcc / . / llvm / lib / Target / ARM / ARMISelLowering.h
blob: b1a954c581320dea0c81e681efb3d6b5f81db279 [file] [log] [blame]
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000[diff] [blame]15#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]17
Craig Toppera9253262014-03-22 23:51:00 +0000[diff] [blame]18#include "MCTargetDesc/ARMBaseInfo.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]19#include "llvm/ADT/SmallVector.h"
20#include "llvm/ADT/StringRef.h"
Chandler Carruth802d7552012-12-04 07:12:27 +0000[diff] [blame]21#include "llvm/CodeGen/CallingConvLower.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineValueType.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]24#include "llvm/CodeGen/SelectionDAG.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]25#include "llvm/CodeGen/SelectionDAGNodes.h"
26#include "llvm/CodeGen/ValueTypes.h"
27#include "llvm/IR/CallingConv.h"
28#include "llvm/IR/IRBuilder.h"
29#include "llvm/IR/InlineAsm.h"
30#include "llvm/Support/CodeGen.h"
Chandler Carruth802d7552012-12-04 07:12:27 +0000[diff] [blame]31#include "llvm/Target/TargetLowering.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]32#include <utility>
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]33
34namespace llvm {
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]35
36class ARMSubtarget;
37class InstrItineraryData;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]38
39 namespace ARMISD {
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]40
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]41 // ARM Specific DAG Nodes
Matthias Braund04893f2015-05-07 21:33:59 +0000[diff] [blame]42 enum NodeType : unsigned {
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]43 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohmaned1cf1a2008-09-23 18:42:32 +0000[diff] [blame]44 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]45
46 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
47 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Chengdfce83c2011-01-17 08:03:18 +0000[diff] [blame]48 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
49 // PIC mode.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]50 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]51
Manman Ren9f911162012-06-01 02:44:42 +0000[diff] [blame]52 // Add pseudo op to model memcpy for struct byval.
53 COPY_STRUCT_BYVAL,
54
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]55 CALL, // Function call.
Evan Chengc3c949b42007-06-19 21:05:09 +0000[diff] [blame]56 CALL_PRED, // Function call that's predicable.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]57 CALL_NOLINK, // Function call with branch not branch-and-link.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]58 BRCOND, // Conditional branch.
59 BR_JT, // Jumptable branch.
Evan Chengc6d70ae2009-07-29 02:18:14 +0000[diff] [blame]60 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]61 RET_FLAG, // Return with a flag operand.
Tim Northoverd8407452013-10-01 14:33:28 +0000[diff] [blame]62 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]63
64 PIC_ADD, // Add with a PC operand and a PIC label.
65
66 CMP, // ARM compare instructions.
Bill Wendling4b796472012-06-11 08:07:26 +0000[diff] [blame]67 CMN, // ARM CMN instructions.
David Goodwindbf11ba2009-06-29 15:33:01 +0000[diff] [blame]68 CMPZ, // ARM compare that sets only Z flag.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]69 CMPFP, // ARM VFP compare instruction, sets FPSCR.
70 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
71 FMSTAT, // ARM fmstat instruction.
Evan Chenge87681c2012-02-23 01:19:06 +0000[diff] [blame]72
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]73 CMOV, // ARM conditional move instructions.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]74
Pablo Barrio7a643462016-06-23 16:53:49 +0000[diff] [blame]75 SSAT, // Signed saturation
76
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]77 BCC_i64,
78
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]79 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
80 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
81 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]82
Evan Chenge8916542011-08-30 01:34:54 +0000[diff] [blame]83 ADDC, // Add with carry
84 ADDE, // Add using carry
85 SUBC, // Sub with carry
86 SUBE, // Sub using carry
87
Jim Grosbachd7cf55c2009-11-09 00:11:35 +0000[diff] [blame]88 VMOVRRD, // double to two gprs.
89 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +0000[diff] [blame]90
Jim Grosbachbbdc5d22010-10-19 23:27:08 +0000[diff] [blame]91 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
92 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Matthias Braun3cd00c12015-07-16 22:34:16 +0000[diff] [blame]93 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
Jim Grosbachaeca45d2009-05-12 23:59:14 +0000[diff] [blame]94
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]95 TC_RETURN, // Tail call return pseudo.
96
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]97 THREAD_POINTER,
98
Evan Chengb972e562009-08-07 00:34:42 +0000[diff] [blame]99 DYN_ALLOC, // Dynamic allocation on the stack.
100
Bob Wilson7ed59712010-10-30 00:54:37 +0000[diff] [blame]101 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]102
103 PRELOAD, // Preload
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]104
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]105 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000[diff] [blame]106 WIN__DBZCHK, // Windows' divide by zero check
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]107
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]108 VCEQ, // Vector compare equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]109 VCEQZ, // Vector compare equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]110 VCGE, // Vector compare greater than or equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]111 VCGEZ, // Vector compare greater than or equal to zero.
112 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]113 VCGEU, // Vector compare unsigned greater than or equal.
114 VCGT, // Vector compare greater than.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]115 VCGTZ, // Vector compare greater than zero.
116 VCLTZ, // Vector compare less than zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]117 VCGTU, // Vector compare unsigned greater than.
118 VTST, // Vector test bits.
119
120 // Vector shift by immediate:
121 VSHL, // ...left
122 VSHRs, // ...right (signed)
123 VSHRu, // ...right (unsigned)
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]124
125 // Vector rounding shift by immediate:
126 VRSHRs, // ...right (signed)
127 VRSHRu, // ...right (unsigned)
128 VRSHRN, // ...right narrow
129
130 // Vector saturating shift by immediate:
131 VQSHLs, // ...left (signed)
132 VQSHLu, // ...left (unsigned)
133 VQSHLsu, // ...left (signed to unsigned)
134 VQSHRNs, // ...right narrow (signed)
135 VQSHRNu, // ...right narrow (unsigned)
136 VQSHRNsu, // ...right narrow (signed to unsigned)
137
138 // Vector saturating rounding shift by immediate:
139 VQRSHRNs, // ...right narrow (signed)
140 VQRSHRNu, // ...right narrow (unsigned)
141 VQRSHRNsu, // ...right narrow (signed to unsigned)
142
143 // Vector shift and insert:
144 VSLI, // ...left
145 VSRI, // ...right
146
147 // Vector get lane (VMOV scalar to ARM core register)
148 // (These are used for 8- and 16-bit element types only.)
149 VGETLANEu, // zero-extend vector extract element
150 VGETLANEs, // sign-extend vector extract element
151
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]152 // Vector move immediate and move negated immediate:
Bob Wilsona3f19012010-07-13 21:16:48 +0000[diff] [blame]153 VMOVIMM,
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]154 VMVNIMM,
155
Evan Cheng7ca4b6e2011-11-15 02:12:34 +0000[diff] [blame]156 // Vector move f32 immediate:
157 VMOVFPIMM,
158
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]159 // Vector duplicate:
Bob Wilsoneb54d512009-08-14 05:13:08 +0000[diff] [blame]160 VDUP,
Bob Wilsoncce31f62009-08-14 05:08:32 +0000[diff] [blame]161 VDUPLANE,
Bob Wilsonf45dee32009-08-04 00:36:16 +0000[diff] [blame]162
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]163 // Vector shuffles:
Bob Wilson32cd8552009-08-19 17:03:43 +0000[diff] [blame]164 VEXT, // extract
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]165 VREV64, // reverse elements within 64-bit doublewords
166 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov9a232f42009-08-21 12:41:24 +0000[diff] [blame]167 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsona7062312009-08-21 20:54:19 +0000[diff] [blame]168 VZIP, // zip (interleave)
169 VUZP, // unzip (deinterleave)
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]170 VTRN, // transpose
Bill Wendlinge1fd78f2011-03-14 23:02:38 +0000[diff] [blame]171 VTBL1, // 1-register shuffle with mask
172 VTBL2, // 2-register shuffle with mask
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]173
Bob Wilson38ab35a2010-09-01 23:50:19 +0000[diff] [blame]174 // Vector multiply long:
175 VMULLs, // ...signed
176 VMULLu, // ...unsigned
177
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000[diff] [blame]178 UMLAL, // 64bit Unsigned Accumulate Multiply
179 SMLAL, // 64bit Signed Accumulate Multiply
Sam Parkerd616cf02016-06-20 16:47:09 +0000[diff] [blame]180 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000[diff] [blame]181
Bob Wilsond8a9a042010-06-04 00:04:02 +0000[diff] [blame]182 // Operands of the standard BUILD_VECTOR node are not legalized, which
183 // is fine if BUILD_VECTORs are always lowered to shuffles or other
184 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
185 // operands need to be legalized. Define an ARM-specific version of
186 // BUILD_VECTOR for this purpose.
187 BUILD_VECTOR,
188
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]189 // Bit-field insert
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]190 BFI,
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]191
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]192 // Vector OR with immediate
Owen Anderson30c48922010-11-05 19:27:46 +0000[diff] [blame]193 VORRIMM,
194 // Vector AND with NOT of immediate
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]195 VBICIMM,
196
Cameron Zwarich53dd03d2011-03-30 23:01:21 +0000[diff] [blame]197 // Vector bitwise select
198 VBSL,
199
Scott Douglass953f9082015-10-05 14:49:54 +0000[diff] [blame]200 // Pseudo-instruction representing a memory copy using ldm/stm
201 // instructions.
202 MEMCPY,
203
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]204 // Vector load N-element structure to all lanes:
Eli Friedmanf624ec22016-12-16 18:44:08 +0000[diff] [blame]205 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
206 VLD2DUP,
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]207 VLD3DUP,
Bob Wilson06fce872011-02-07 17:43:21 +0000[diff] [blame]208 VLD4DUP,
209
210 // NEON loads with post-increment base updates:
211 VLD1_UPD,
212 VLD2_UPD,
213 VLD3_UPD,
214 VLD4_UPD,
215 VLD2LN_UPD,
216 VLD3LN_UPD,
217 VLD4LN_UPD,
Eli Friedmanf624ec22016-12-16 18:44:08 +0000[diff] [blame]218 VLD1DUP_UPD,
Bob Wilson06fce872011-02-07 17:43:21 +0000[diff] [blame]219 VLD2DUP_UPD,
220 VLD3DUP_UPD,
221 VLD4DUP_UPD,
222
223 // NEON stores with post-increment base updates:
224 VST1_UPD,
225 VST2_UPD,
226 VST3_UPD,
227 VST4_UPD,
228 VST2LN_UPD,
229 VST3LN_UPD,
Amara Emersonb4ad2f32013-09-26 12:22:36 +0000[diff] [blame]230 VST4LN_UPD
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]231 };
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]232
233 } // end namespace ARMISD
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]234
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]235 /// Define some predicates that are used for node matching.
236 namespace ARM {
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]237
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]238 bool isBitFieldInvertedMask(unsigned v);
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]239
240 } // end namespace ARM
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]241
Bob Wilsondd0e2362009-05-20 16:30:25 +0000[diff] [blame]242 //===--------------------------------------------------------------------===//
Dale Johannesen8447d342007-03-20 00:30:56 +0000[diff] [blame]243 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]244
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]245 class ARMTargetLowering : public TargetLowering {
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]246 public:
Eric Christopher1889fdc2015-01-29 00:19:39 +0000[diff] [blame]247 explicit ARMTargetLowering(const TargetMachine &TM,
248 const ARMSubtarget &STI);
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]249
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]250 unsigned getJumpTableEncoding() const override;
Eric Christopher824f42f2015-05-12 01:26:05 +0000[diff] [blame]251 bool useSoftFloat() const override;
Jim Grosbach8d3ba732010-07-19 17:20:38 +0000[diff] [blame]252
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]253 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]254
255 /// ReplaceNodeResults - Replace the results of node with an illegal result
256 /// type with new values built out of custom code.
257 ///
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]258 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
259 SelectionDAG &DAG) const override;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]260
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]261 const char *getTargetNodeName(unsigned Opcode) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]262
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]263 bool isSelectSupported(SelectSupportKind Kind) const override {
Nadav Rotem9d832022012-09-02 12:10:19 +0000[diff] [blame]264 // ARM does not support scalar condition selects on vectors.
265 return (Kind != ScalarCondVectorVal);
266 }
267
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]268 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]269 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
270 EVT VT) const override;
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]271
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]272 MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]273 EmitInstrWithCustomInserter(MachineInstr &MI,
274 MachineBasicBlock *MBB) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]275
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]276 void AdjustInstrPostInstrSelection(MachineInstr &MI,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]277 SDNode *Node) const override;
Evan Chenge6fba772011-08-30 19:09:48 +0000[diff] [blame]278
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]279 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Peter Collingbourne86b9fbe2016-03-21 18:00:02 +0000[diff] [blame]280 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
James Molloy9d55f192015-11-10 14:22:05 +0000[diff] [blame]281 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]282 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
Evan Chengd42641c2011-02-02 01:06:55 +0000[diff] [blame]283
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]284 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
Evan Chengd42641c2011-02-02 01:06:55 +0000[diff] [blame]285
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000[diff] [blame]286 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
Evan Cheng79e2ca92012-12-10 23:21:26 +0000[diff] [blame]287 /// unaligned memory accesses of the specified type. Returns whether it
288 /// is "fast" by reference in the second argument.
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000[diff] [blame]289 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
290 unsigned Align,
291 bool *Fast) const override;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]292
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]293 EVT getOptimalMemOpType(uint64_t Size,
294 unsigned DstAlign, unsigned SrcAlign,
295 bool IsMemset, bool ZeroMemset,
296 bool MemcpyStrSrc,
297 MachineFunction &MF) const override;
Lang Hames9929c422011-11-02 22:52:45 +0000[diff] [blame]298
Matt Beaumont-Gay4a04c922012-12-06 23:15:36 +0000[diff] [blame]299 using TargetLowering::isZExtFree;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]300 bool isZExtFree(SDValue Val, EVT VT2) const override;
Evan Cheng9ec512d2012-12-06 19:13:27 +0000[diff] [blame]301
Ahmed Bougacha4200cc92015-03-05 19:37:53 +0000[diff] [blame]302 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
303
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]304 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
Tim Northovercc2e9032013-08-06 13:58:03 +0000[diff] [blame]305
306
Chris Lattner1eb94d92007-03-30 23:15:24 +0000[diff] [blame]307 /// isLegalAddressingMode - Return true if the addressing mode represented
308 /// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]309 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
310 Type *Ty, unsigned AS) const override;
Javed Absar85874a92016-10-13 14:57:43 +0000[diff] [blame]311
312 /// getScalingFactorCost - Return the cost of the scaling used in
313 /// addressing mode represented by AM.
314 /// If the AM is supported, the return value must be >= 0.
315 /// If the AM is not supported, the return value must be negative.
316 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
317 unsigned AS) const override;
318
Evan Chengdc49a8d2009-08-14 20:09:37 +0000[diff] [blame]319 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]320
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]321 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]322 /// icmp immediate, that is the target has icmp instructions which can
323 /// compare a register against the immediate without having to materialize
324 /// the immediate into a register.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]325 bool isLegalICmpImmediate(int64_t Imm) const override;
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]326
Dan Gohman6136e942011-05-03 00:46:49 +0000[diff] [blame]327 /// isLegalAddImmediate - Return true if the specified immediate is legal
328 /// add immediate, that is the target has add instructions which can
329 /// add a register and the immediate without having to materialize
330 /// the immediate into a register.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]331 bool isLegalAddImmediate(int64_t Imm) const override;
Dan Gohman6136e942011-05-03 00:46:49 +0000[diff] [blame]332
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]333 /// getPreIndexedAddressParts - returns true by value, base pointer and
334 /// offset pointer and addressing mode by reference if the node's address
335 /// can be legally represented as pre-indexed load / store address.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]336 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
337 ISD::MemIndexedMode &AM,
338 SelectionDAG &DAG) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]339
340 /// getPostIndexedAddressParts - returns true by value, base pointer and
341 /// offset pointer and addressing mode by reference if this node can be
342 /// combined with a load / store to form a post-indexed load / store.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]343 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
344 SDValue &Offset, ISD::MemIndexedMode &AM,
345 SelectionDAG &DAG) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]346
Jay Foada0653a32014-05-14 21:14:37 +0000[diff] [blame]347 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
348 APInt &KnownOne,
349 const SelectionDAG &DAG,
350 unsigned Depth) const override;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]351
352
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]353 bool ExpandInlineAsm(CallInst *CI) const override;
Evan Cheng078b0b02011-01-08 01:24:27 +0000[diff] [blame]354
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]355 ConstraintType getConstraintType(StringRef Constraint) const override;
John Thompsone8360b72010-10-29 17:29:13 +0000[diff] [blame]356
357 /// Examine constraint string and operand type and determine a weight value.
358 /// The operand object must already have been set up with the operand type.
359 ConstraintWeight getSingleConstraintMatchWeight(
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]360 AsmOperandInfo &info, const char *constraint) const override;
John Thompsone8360b72010-10-29 17:29:13 +0000[diff] [blame]361
Eric Christopher11e4df72015-02-26 22:38:43 +0000[diff] [blame]362 std::pair<unsigned, const TargetRegisterClass *>
363 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]364 StringRef Constraint, MVT VT) const override;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]365
Silviu Baranga82d04262016-04-25 14:29:18 +0000[diff] [blame]366 const char *LowerXConstraint(EVT ConstraintVT) const override;
367
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +0000[diff] [blame]368 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
369 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
370 /// true it means one of the asm constraint of the inline asm instruction
371 /// being processed is 'm'.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]372 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
373 std::vector<SDValue> &Ops,
374 SelectionDAG &DAG) const override;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]375
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]376 unsigned
377 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
Daniel Sanders1f58ef72015-06-03 12:33:56 +0000[diff] [blame]378 if (ConstraintCode == "Q")
379 return InlineAsm::Constraint_Q;
James Molloy72222f52015-10-26 10:04:52 +0000[diff] [blame]380 else if (ConstraintCode == "o")
381 return InlineAsm::Constraint_o;
Daniel Sanders1f58ef72015-06-03 12:33:56 +0000[diff] [blame]382 else if (ConstraintCode.size() == 2) {
383 if (ConstraintCode[0] == 'U') {
384 switch(ConstraintCode[1]) {
385 default:
386 break;
387 case 'm':
388 return InlineAsm::Constraint_Um;
389 case 'n':
390 return InlineAsm::Constraint_Un;
391 case 'q':
392 return InlineAsm::Constraint_Uq;
393 case 's':
394 return InlineAsm::Constraint_Us;
395 case 't':
396 return InlineAsm::Constraint_Ut;
397 case 'v':
398 return InlineAsm::Constraint_Uv;
399 case 'y':
400 return InlineAsm::Constraint_Uy;
401 }
402 }
403 }
404 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
Daniel Sandersbf5b80f2015-03-16 13:13:41 +0000[diff] [blame]405 }
406
Dan Gohman4df9d9c2010-05-11 16:21:03 +0000[diff] [blame]407 const ARMSubtarget* getSubtarget() const {
Dan Gohman544ab2c2008-04-12 04:36:06 +0000[diff] [blame]408 return Subtarget;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]409 }
410
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]411 /// getRegClassFor - Return the register class that should be used for the
412 /// specified value type.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]413 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]414
James Molloy8a259922013-12-03 11:23:11 +0000[diff] [blame]415 /// Returns true if a cast between SrcAS and DestAS is a noop.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]416 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
James Molloy8a259922013-12-03 11:23:11 +0000[diff] [blame]417 // Addrspacecasts are always noops.
418 return true;
419 }
420
John Brawn0dbcd652015-03-18 12:01:59 +0000[diff] [blame]421 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
422 unsigned &PrefAlign) const override;
423
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]424 /// createFastISel - This method returns a target specific FastISel object,
425 /// or null if the target does not support "fast" ISel.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]426 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
427 const TargetLibraryInfo *libInfo) const override;
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]428
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]429 Sched::Preference getSchedulingPreference(SDNode *N) const override;
Evan Cheng4401f882010-05-20 23:26:43 +0000[diff] [blame]430
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]431 bool
432 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
433 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000[diff] [blame]434
435 /// isFPImmLegal - Returns true if the target can instruction select the
436 /// specified FP immediate natively. If false, the legalizer will
437 /// materialize the FP immediate as a load from a constant pool.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]438 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000[diff] [blame]439
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]440 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
441 const CallInst &I,
442 unsigned Intrinsic) const override;
Juergen Ributzka659ce002014-01-28 01:20:14 +0000[diff] [blame]443
444 /// \brief Returns true if it is beneficial to convert a load of a constant
445 /// to just the constant itself.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]446 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
447 Type *Ty) const override;
Juergen Ributzka659ce002014-01-28 01:20:14 +0000[diff] [blame]448
Eli Friedmand03df812016-12-20 20:05:07 +0000[diff] [blame]449 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
450 /// with this index.
451 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
452
Oliver Stannardc24f2172014-05-09 14:01:47 +0000[diff] [blame]453 /// \brief Returns true if an argument of type Ty needs to be passed in a
454 /// contiguous block of registers in calling convention CallConv.
455 bool functionArgumentNeedsConsecutiveRegisters(
456 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
457
Joseph Tremouletf748c892015-11-07 01:11:31 +0000[diff] [blame]458 /// If a physical register, this returns the register that receives the
459 /// exception address on entry to an EH pad.
460 unsigned
461 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
462
463 /// If a physical register, this returns the register that receives the
464 /// exception typeid on entry to a landing pad.
465 unsigned
466 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
467
Robin Morisset5349e8e2014-09-18 18:56:04 +0000[diff] [blame]468 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
Tim Northover037f26f22014-04-17 18:22:47 +0000[diff] [blame]469 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
470 AtomicOrdering Ord) const override;
471 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
472 Value *Addr, AtomicOrdering Ord) const override;
473
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]474 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
475
Robin Morissetdedef332014-09-23 20:31:14 +0000[diff] [blame]476 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
Robin Morisseta47cb412014-09-03 21:01:03 +0000[diff] [blame]477 bool IsStore, bool IsLoad) const override;
Robin Morissetdedef332014-09-23 20:31:14 +0000[diff] [blame]478 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
Robin Morisseta47cb412014-09-03 21:01:03 +0000[diff] [blame]479 bool IsStore, bool IsLoad) const override;
480
Hao Liu2cd34bb2015-06-26 02:45:36 +0000[diff] [blame]481 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
482
483 bool lowerInterleavedLoad(LoadInst *LI,
484 ArrayRef<ShuffleVectorInst *> Shuffles,
485 ArrayRef<unsigned> Indices,
486 unsigned Factor) const override;
487 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
488 unsigned Factor) const override;
489
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]490 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
Ahmed Bougacha52468672015-09-11 17:08:28 +0000[diff] [blame]491 TargetLoweringBase::AtomicExpansionKind
492 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
Robin Morisseted3d48f2014-09-03 21:29:59 +0000[diff] [blame]493 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
Ahmed Bougacha9d677132015-09-11 17:08:17 +0000[diff] [blame]494 TargetLoweringBase::AtomicExpansionKind
JF Bastienf14889e2015-03-04 15:47:57 +0000[diff] [blame]495 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
Ahmed Bougacha52468672015-09-11 17:08:28 +0000[diff] [blame]496 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
Tim Northover037f26f22014-04-17 18:22:47 +0000[diff] [blame]497
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]498 bool useLoadStackGuardNode() const override;
499
Quentin Colombetc32615d2014-10-31 17:52:53 +0000[diff] [blame]500 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
501 unsigned &Cost) const override;
502
Nirav Dave54e22f32017-03-14 00:34:14 +0000[diff] [blame^]503 bool canMergeStoresTo(EVT MemVT) const override {
504 // Do not merge to larger than i32.
505 return (MemVT.getSizeInBits() <= 32);
506 }
507
Sanjay Patelaf1b48b2015-11-10 19:24:31 +0000[diff] [blame]508 bool isCheapToSpeculateCttz() const override;
509 bool isCheapToSpeculateCtlz() const override;
510
Manman Ren57518142016-04-11 21:08:06 +0000[diff] [blame]511 bool supportSwiftError() const override {
512 return true;
513 }
514
Diana Picus774d1572016-07-18 06:48:25 +0000[diff] [blame]515 bool hasStandaloneRem(EVT VT) const override {
516 return HasStandaloneRem;
517 }
518
Diana Picus2af9c382016-12-16 10:35:20 +0000[diff] [blame]519 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
520 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
521
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]522 protected:
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]523 std::pair<const TargetRegisterClass *, uint8_t>
524 findRepresentativeClass(const TargetRegisterInfo *TRI,
525 MVT VT) const override;
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]526
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]527 private:
528 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
529 /// make the right decision when generating code for different targets.
530 const ARMSubtarget *Subtarget;
531
Evan Chengdf907f42010-07-23 22:39:59 +0000[diff] [blame]532 const TargetRegisterInfo *RegInfo;
533
Evan Chengbf407072010-09-10 01:29:16 +0000[diff] [blame]534 const InstrItineraryData *Itins;
535
Bob Wilson844d6c82009-07-13 18:11:36 +0000[diff] [blame]536 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]537 ///
538 unsigned ARMPCLabelIndex;
539
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]540 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
541 // check.
542 bool InsertFencesForAtomic;
543
Diana Picus774d1572016-07-18 06:48:25 +0000[diff] [blame]544 bool HasStandaloneRem = true;
545
Craig Topper4fa625f2012-08-12 03:16:37 +0000[diff] [blame]546 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
547 void addDRTypeForNEON(MVT VT);
548 void addQRTypeForNEON(MVT VT);
Louis Gerbarg3342bf12014-05-09 17:02:49 +0000[diff] [blame]549 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]550
551 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]552
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]553 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
554 SDValue &Arg, RegsToPassVector &RegsToPass,
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]555 CCValAssign &VA, CCValAssign &NextVA,
556 SDValue &StackPtr,
Craig Topperb94011f2013-07-14 04:42:23 +0000[diff] [blame]557 SmallVectorImpl<SDValue> &MemOpChains,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]558 ISD::ArgFlagsTy Flags) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]559 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]560 SDValue &Root, SelectionDAG &DAG,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]561 const SDLoc &dl) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]562
Oliver Stannardc24f2172014-05-09 14:01:47 +0000[diff] [blame]563 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
564 bool isVarArg) const;
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]565 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
566 bool isVarArg) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]567 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]568 const SDLoc &dl, SelectionDAG &DAG,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]569 const CCValAssign &VA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]570 ISD::ArgFlagsTy Flags) const;
Jim Grosbachc98892f2010-05-26 20:22:18 +0000[diff] [blame]571 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbachbd9485d2010-05-22 01:06:18 +0000[diff] [blame]572 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Matthias Braun3cd00c12015-07-16 22:34:16 +0000[diff] [blame]573 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha570d052010-02-08 23:22:00 +0000[diff] [blame]574 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]575 const ARMSubtarget *Subtarget) const;
576 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
577 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
578 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +0000[diff] [blame]579 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]580 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]581 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]582 SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]583 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgaea41202012-05-04 09:40:39 +0000[diff] [blame]584 SelectionDAG &DAG,
585 TLSModel::Model model) const;
Tim Northoverbd41cf82016-01-07 09:03:03 +0000[diff] [blame]586 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
Saleem Abdulrasoolf36005a2016-02-03 18:21:59 +0000[diff] [blame]587 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
Tim Northoverbd41cf82016-01-07 09:03:03 +0000[diff] [blame]588 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]589 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Louis Gerbarg3342bf12014-05-09 17:02:49 +0000[diff] [blame]590 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
Bill Wendling6a981312010-08-11 08:43:16 +0000[diff] [blame]591 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]592 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
593 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng25f93642010-07-08 02:08:50 +0000[diff] [blame]594 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng168ced92010-05-22 01:47:14 +0000[diff] [blame]595 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]596 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]597 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
598 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemanb69b1822010-08-03 21:31:55 +0000[diff] [blame]599 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hamesc35ee8b2012-03-15 18:49:02 +0000[diff] [blame]600 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
601 const ARMSubtarget *ST) const;
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]602 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]603 const ARMSubtarget *ST) const;
Bob Wilsone7dde0c2013-11-03 06:14:38 +0000[diff] [blame]604 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
Renato Golin87610692013-07-16 09:32:17 +0000[diff] [blame]605 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
Martell Maloned1229242015-11-26 15:34:03 +0000[diff] [blame]606 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
607 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000[diff] [blame]608 SmallVectorImpl<SDValue> &Results) const;
Martell Maloned1229242015-11-26 15:34:03 +0000[diff] [blame]609 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000[diff] [blame]610 SDValue &Chain) const;
Scott Douglassbdef6042015-08-24 09:17:18 +0000[diff] [blame]611 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]612 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
Oliver Stannard51b1d462014-08-21 12:50:31 +0000[diff] [blame]613 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
614 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
615 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
616 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]617
Pat Gavlina717f252015-07-09 17:40:29 +0000[diff] [blame]618 unsigned getRegisterByName(const char* RegName, EVT VT,
619 SelectionDAG &DAG) const override;
Renato Golinc7aea402014-05-06 16:51:25 +0000[diff] [blame]620
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]621 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
622 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
623 /// expanded to FMAs when this method returns true, otherwise fmuladd is
624 /// expanded to fmul + fadd.
625 ///
626 /// ARM supports both fused and unfused multiply-add operations; we already
Stephen Lin2a644732013-07-10 01:57:39 +0000[diff] [blame]627 /// lower a pair of fmul and fadd to the latter so it's not clear that there
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]628 /// would be a gain or that the gain would be worthwhile enough to risk
629 /// correctness bugs.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]630 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]631
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]632 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola18a831d2007-10-19 14:35:17 +0000[diff] [blame]633
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]634 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]635 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]636 const SmallVectorImpl<ISD::InputArg> &Ins,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]637 const SDLoc &dl, SelectionDAG &DAG,
638 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
639 SDValue ThisVal) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]640
Manman Ren5e9e65e2016-01-12 00:47:18 +0000[diff] [blame]641 bool supportSplitCSR(MachineFunction *MF) const override {
642 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
643 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
644 }
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]645
Manman Ren5e9e65e2016-01-12 00:47:18 +0000[diff] [blame]646 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
647 void insertCopiesSplitCSR(
648 MachineBasicBlock *Entry,
649 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
650
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]651 SDValue
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]652 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
653 const SmallVectorImpl<ISD::InputArg> &Ins,
654 const SDLoc &dl, SelectionDAG &DAG,
655 SmallVectorImpl<SDValue> &InVals) const override;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]656
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]657 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
658 SDValue &Chain, const Value *OrigArg,
659 unsigned InRegsParamRecordIdx, int ArgOffset,
Tim Northover8cda34f2015-03-11 18:54:22 +0000[diff] [blame]660 unsigned ArgSize) const;
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]661
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]662 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]663 const SDLoc &dl, SDValue &Chain,
664 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]665 bool ForceMutable = false) const;
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]666
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]667 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
668 SmallVectorImpl<SDValue> &InVals) const override;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]669
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]670 /// HandleByVal - Target-specific cleanup for ByVal support.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]671 void HandleByVal(CCState *, unsigned &, unsigned) const override;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]672
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]673 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
674 /// for tail call optimization. Targets which want to do tail call
675 /// optimization should implement this function.
676 bool IsEligibleForTailCallOptimization(SDValue Callee,
677 CallingConv::ID CalleeCC,
678 bool isVarArg,
679 bool isCalleeStructRet,
680 bool isCallerStructRet,
681 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]682 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]683 const SmallVectorImpl<ISD::InputArg> &Ins,
684 SelectionDAG& DAG) const;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000[diff] [blame]685
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]686 bool CanLowerReturn(CallingConv::ID CallConv,
687 MachineFunction &MF, bool isVarArg,
688 const SmallVectorImpl<ISD::OutputArg> &Outs,
689 LLVMContext &Context) const override;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000[diff] [blame]690
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]691 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
692 const SmallVectorImpl<ISD::OutputArg> &Outs,
693 const SmallVectorImpl<SDValue> &OutVals,
694 const SDLoc &dl, SelectionDAG &DAG) const override;
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]695
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]696 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
Evan Chengd4b08732010-11-30 23:55:39 +0000[diff] [blame]697
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]698 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
Evan Cheng0663f232011-03-21 01:19:09 +0000[diff] [blame]699
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]700 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
Oliver Stannard51b1d462014-08-21 12:50:31 +0000[diff] [blame]701 SDValue ARMcc, SDValue CCR, SDValue Cmp,
702 SelectionDAG &DAG) const;
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]703 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]704 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
705 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
James Molloyd5087892017-02-13 12:32:47 +0000[diff] [blame]706 const SDLoc &dl, bool InvalidOnQNaN) const;
Bob Wilson45acbd02011-03-08 01:17:20 +0000[diff] [blame]707 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]708
709 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000[diff] [blame]710
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]711 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
Bill Wendling030b58e2011-10-06 22:18:16 +0000[diff] [blame]712 MachineBasicBlock *DispatchBB, int FI) const;
713
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]714 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
Bill Wendling374ee192011-10-03 21:25:38 +0000[diff] [blame]715
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]716 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
Manman Rene8735522012-06-01 19:33:18 +0000[diff] [blame]717
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]718 MachineBasicBlock *EmitStructByval(MachineInstr &MI,
Manman Rene8735522012-06-01 19:33:18 +0000[diff] [blame]719 MachineBasicBlock *MBB) const;
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]720
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]721 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]722 MachineBasicBlock *MBB) const;
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]723 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000[diff] [blame]724 MachineBasicBlock *MBB) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]725 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]726
Owen Andersona4076922010-11-05 21:57:54 +0000[diff] [blame]727 enum NEONModImmType {
728 VMOVModImm,
729 VMVNModImm,
730 OtherModImm
731 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]732
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]733 namespace ARM {
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]734
Bob Wilson3e6fa462012-08-03 04:06:28 +0000[diff] [blame]735 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
736 const TargetLibraryInfo *libInfo);
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]737
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000[diff] [blame]738 } // end namespace ARM
739
740} // end namespace llvm
741
742#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H