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gerrit-public.fairphone.software / toolchain / llvm-project / 307e782cbceee321817bd3adc0a2679348dff6cc / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: 3a96ab6c6cbbacc672ba7211b35e5ebe62baea08 [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
15#include "AArch64Subtarget.h"
16#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]17#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]19#include "llvm-c/Disassembler.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]22#include "llvm/MC/MCInst.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]27#include <algorithm>
28#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-disassembler"
33
34// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]35using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36
37// Forward declare these because the autogenerated code will reference them.
38// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]39static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 unsigned RegNo, uint64_t Address,
41 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]42static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43 unsigned RegNo,
44 uint64_t Address,
45 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]46static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47 uint64_t Address,
48 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]49static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50 uint64_t Address,
51 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]52static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53 uint64_t Address,
54 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]55static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56 uint64_t Address,
57 const void *Decoder);
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]58static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
59 uint64_t Address,
60 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]61static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]62 uint64_t Address,
63 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]64static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]65 unsigned RegNo, uint64_t Address,
66 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]67static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]68 uint64_t Address,
69 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]70static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]71 unsigned RegNo, uint64_t Address,
72 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]73static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]74 uint64_t Address,
75 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]76static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]77 uint64_t Address,
78 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]79static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80 uint64_t Address,
81 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]82static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]83 uint64_t Address,
84 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]85static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 uint64_t Address,
87 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]88static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]89 uint64_t Address,
90 const void *Decoder);
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]91static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
92 uint64_t Address,
93 const void *Decode);
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]94static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
95 uint64_t Address,
96 const void *Decode);
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]97static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
98 uint64_t Address,
99 const void *Decode);
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]100static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
101 uint64_t Address,
102 const void *Decode);
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]103static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
104 uint64_t Address,
105 const void *Decode);
Sander de Smalen906a5de2018-01-09 17:01:27 +0000[diff] [blame]106static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
107 uint64_t Address,
108 const void *Decode);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]109
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]110static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]111 uint64_t Address,
112 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]113static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]114 uint64_t Address,
115 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]116static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]118static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]120static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]122static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]123 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]124static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]125 uint64_t Address,
126 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]127static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]128 uint64_t Address,
129 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]130static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]131 uint64_t Address,
132 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]133static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
134 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]135 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]136static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]137 uint64_t Address,
138 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]139static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]140 uint64_t Address,
141 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]142static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
143 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]144 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]145static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
146 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]147 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]148static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]149 uint64_t Address,
150 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]151static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
152 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]153 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]154static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]156static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]158static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]159 uint64_t Address,
160 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]161static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]162 uint64_t Address,
163 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]164static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 uint64_t Address, const void *Decoder);
166
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]167static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]168 uint64_t Address,
169 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]170static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]171 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]172static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]173 uint64_t Addr,
174 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]175static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]176 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]177static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]178 uint64_t Addr,
179 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]180static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]181 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]182static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]183 uint64_t Addr,
184 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]185static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]186 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]187static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]188 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]189static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]190 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]191static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]192 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]193static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]194 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]195static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
196 unsigned RegNo,
197 uint64_t Addr,
198 const void *Decoder);
199static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
200 unsigned RegNo,
201 uint64_t Addr,
202 const void *Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]203static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
204 uint32_t insn,
205 uint64_t Address,
206 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]207template<int Bits>
208static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
209 uint64_t Address, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]210
211static bool Check(DecodeStatus &Out, DecodeStatus In) {
212 switch (In) {
213 case MCDisassembler::Success:
214 // Out stays the same.
215 return true;
216 case MCDisassembler::SoftFail:
217 Out = In;
218 return true;
219 case MCDisassembler::Fail:
220 Out = In;
221 return false;
222 }
223 llvm_unreachable("Invalid DecodeStatus!");
224}
225
226#include "AArch64GenDisassemblerTables.inc"
227#include "AArch64GenInstrInfo.inc"
228
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]229#define Success MCDisassembler::Success
230#define Fail MCDisassembler::Fail
231#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]232
233static MCDisassembler *createAArch64Disassembler(const Target &T,
234 const MCSubtargetInfo &STI,
235 MCContext &Ctx) {
236 return new AArch64Disassembler(STI, Ctx);
237}
238
239DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]240 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]241 uint64_t Address,
242 raw_ostream &OS,
243 raw_ostream &CS) const {
244 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]245
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]246 Size = 0;
247 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]248 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]249 return Fail;
250 Size = 4;
251
252 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]253 uint32_t Insn =
254 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]255
256 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]257 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]258}
259
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]260static MCSymbolizer *
261createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
262 LLVMSymbolLookupCallback SymbolLookUp,
263 void *DisInfo, MCContext *Ctx,
264 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]265 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
266 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]267}
268
269extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]270 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]271 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]272 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]273 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]274 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]275 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]276 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]277 createAArch64ExternalSymbolizer);
278
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]279 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]280 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]281 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]282 createAArch64ExternalSymbolizer);
283}
284
285static const unsigned FPR128DecoderTable[] = {
286 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
287 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
288 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
289 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
290 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
291 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
292 AArch64::Q30, AArch64::Q31
293};
294
295static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
296 uint64_t Addr,
297 const void *Decoder) {
298 if (RegNo > 31)
299 return Fail;
300
301 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]302 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]303 return Success;
304}
305
306static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
307 uint64_t Addr,
308 const void *Decoder) {
309 if (RegNo > 15)
310 return Fail;
311 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
312}
313
314static const unsigned FPR64DecoderTable[] = {
315 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
316 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
317 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
318 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
319 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
320 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
321 AArch64::D30, AArch64::D31
322};
323
324static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
325 uint64_t Addr,
326 const void *Decoder) {
327 if (RegNo > 31)
328 return Fail;
329
330 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]331 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]332 return Success;
333}
334
335static const unsigned FPR32DecoderTable[] = {
336 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
337 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
338 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
339 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
340 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
341 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
342 AArch64::S30, AArch64::S31
343};
344
345static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
346 uint64_t Addr,
347 const void *Decoder) {
348 if (RegNo > 31)
349 return Fail;
350
351 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]352 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]353 return Success;
354}
355
356static const unsigned FPR16DecoderTable[] = {
357 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
358 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
359 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
360 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
361 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
362 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
363 AArch64::H30, AArch64::H31
364};
365
366static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
367 uint64_t Addr,
368 const void *Decoder) {
369 if (RegNo > 31)
370 return Fail;
371
372 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]373 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]374 return Success;
375}
376
377static const unsigned FPR8DecoderTable[] = {
378 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
379 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
380 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
381 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
382 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
383 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
384 AArch64::B30, AArch64::B31
385};
386
387static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
388 uint64_t Addr,
389 const void *Decoder) {
390 if (RegNo > 31)
391 return Fail;
392
393 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]394 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]395 return Success;
396}
397
398static const unsigned GPR64DecoderTable[] = {
399 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
400 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
401 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
402 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
403 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
404 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
405 AArch64::LR, AArch64::XZR
406};
407
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]408static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
409 uint64_t Addr,
410 const void *Decoder) {
411 if (RegNo > 30)
412 return Fail;
413
414 unsigned Register = GPR64DecoderTable[RegNo];
415 Inst.addOperand(MCOperand::createReg(Register));
416 return Success;
417}
418
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]419static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
420 uint64_t Addr,
421 const void *Decoder) {
422 if (RegNo > 31)
423 return Fail;
424
425 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]426 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]427 return Success;
428}
429
430static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
431 uint64_t Addr,
432 const void *Decoder) {
433 if (RegNo > 31)
434 return Fail;
435 unsigned Register = GPR64DecoderTable[RegNo];
436 if (Register == AArch64::XZR)
437 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]438 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]439 return Success;
440}
441
442static const unsigned GPR32DecoderTable[] = {
443 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
444 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
445 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
446 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
447 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
448 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
449 AArch64::W30, AArch64::WZR
450};
451
452static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
453 uint64_t Addr,
454 const void *Decoder) {
455 if (RegNo > 31)
456 return Fail;
457
458 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]459 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]460 return Success;
461}
462
463static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
464 uint64_t Addr,
465 const void *Decoder) {
466 if (RegNo > 31)
467 return Fail;
468
469 unsigned Register = GPR32DecoderTable[RegNo];
470 if (Register == AArch64::WZR)
471 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]472 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]473 return Success;
474}
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]475static const unsigned ZPRDecoderTable[] = {
476 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
477 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
478 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
479 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
480 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
481 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
482 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
483 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
484};
485
486static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
487 uint64_t Address,
488 const void* Decoder) {
489 if (RegNo > 31)
490 return Fail;
491
492 unsigned Register = ZPRDecoderTable[RegNo];
493 Inst.addOperand(MCOperand::createReg(Register));
494 return Success;
495}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]496
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]497static const unsigned ZZDecoderTable[] = {
498 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
499 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
500 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
501 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
502 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
503 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
504 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
505 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
506};
507
508static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
509 uint64_t Address,
510 const void* Decoder) {
511 if (RegNo > 31)
512 return Fail;
513 unsigned Register = ZZDecoderTable[RegNo];
514 Inst.addOperand(MCOperand::createReg(Register));
515 return Success;
516}
517
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]518static const unsigned ZZZDecoderTable[] = {
519 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
520 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
521 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
522 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
523 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
524 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
525 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
526 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
527 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
528 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
529 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
530};
531
532static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
533 uint64_t Address,
534 const void* Decoder) {
535 if (RegNo > 31)
536 return Fail;
537 unsigned Register = ZZZDecoderTable[RegNo];
538 Inst.addOperand(MCOperand::createReg(Register));
539 return Success;
540}
541
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]542static const unsigned ZZZZDecoderTable[] = {
543 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
544 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
545 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
546 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
547 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
548 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
549 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
550 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
551 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
552 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
553 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
554};
555
556static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
557 uint64_t Address,
558 const void* Decoder) {
559 if (RegNo > 31)
560 return Fail;
561 unsigned Register = ZZZZDecoderTable[RegNo];
562 Inst.addOperand(MCOperand::createReg(Register));
563 return Success;
564}
565
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]566static const unsigned PPRDecoderTable[] = {
567 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
568 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
569 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
570 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
571};
572
573static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
574 uint64_t Addr, const void *Decoder) {
575 if (RegNo > 15)
576 return Fail;
577
578 unsigned Register = PPRDecoderTable[RegNo];
579 Inst.addOperand(MCOperand::createReg(Register));
580 return Success;
581}
582
Sander de Smalendc5e0812018-01-03 10:15:46 +0000[diff] [blame]583static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
584 uint64_t Addr,
585 const void* Decoder) {
586 if (RegNo > 7)
587 return Fail;
588
589 // Just reuse the PPR decode table
590 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
591}
592
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]593static const unsigned VectorDecoderTable[] = {
594 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
595 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
596 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
597 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
598 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
599 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
600 AArch64::Q30, AArch64::Q31
601};
602
603static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
604 uint64_t Addr,
605 const void *Decoder) {
606 if (RegNo > 31)
607 return Fail;
608
609 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]610 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]611 return Success;
612}
613
614static const unsigned QQDecoderTable[] = {
615 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
616 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
617 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
618 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
619 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
620 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
621 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
622 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
623};
624
625static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
626 uint64_t Addr, const void *Decoder) {
627 if (RegNo > 31)
628 return Fail;
629 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]630 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]631 return Success;
632}
633
634static const unsigned QQQDecoderTable[] = {
635 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
636 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
637 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
638 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
639 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
640 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
641 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
642 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
643 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
644 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
645 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
646};
647
648static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
649 uint64_t Addr, const void *Decoder) {
650 if (RegNo > 31)
651 return Fail;
652 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]653 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]654 return Success;
655}
656
657static const unsigned QQQQDecoderTable[] = {
658 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
659 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
660 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
661 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
662 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
663 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
664 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
665 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
666 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
667 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
668 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
669};
670
671static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
672 uint64_t Addr,
673 const void *Decoder) {
674 if (RegNo > 31)
675 return Fail;
676 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]677 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]678 return Success;
679}
680
681static const unsigned DDDecoderTable[] = {
682 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
683 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
684 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
685 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
686 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
687 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
688 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
689 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
690};
691
692static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
693 uint64_t Addr, const void *Decoder) {
694 if (RegNo > 31)
695 return Fail;
696 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]697 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]698 return Success;
699}
700
701static const unsigned DDDDecoderTable[] = {
702 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
703 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
704 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
705 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
706 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
707 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
708 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
709 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
710 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
711 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
712 AArch64::D30_D31_D0, AArch64::D31_D0_D1
713};
714
715static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
716 uint64_t Addr, const void *Decoder) {
717 if (RegNo > 31)
718 return Fail;
719 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]720 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]721 return Success;
722}
723
724static const unsigned DDDDDecoderTable[] = {
725 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
726 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
727 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
728 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
729 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
730 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
731 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
732 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
733 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
734 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
735 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
736};
737
738static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
739 uint64_t Addr,
740 const void *Decoder) {
741 if (RegNo > 31)
742 return Fail;
743 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]744 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]745 return Success;
746}
747
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]748static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]749 uint64_t Addr,
750 const void *Decoder) {
751 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]752 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]753 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]754 return Success;
755}
756
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]757static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]758 uint64_t Addr,
759 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]760 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]761 return Success;
762}
763
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]764static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]765 uint64_t Addr, const void *Decoder) {
766 int64_t ImmVal = Imm;
767 const AArch64Disassembler *Dis =
768 static_cast<const AArch64Disassembler *>(Decoder);
769
770 // Sign-extend 19-bit immediate.
771 if (ImmVal & (1 << (19 - 1)))
772 ImmVal |= ~((1LL << 19) - 1);
773
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]774 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]775 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]776 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]777 return Success;
778}
779
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]780static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]781 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]782 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
783 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]784 return Success;
785}
786
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]787static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]788 uint64_t Address,
789 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]790 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]791
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]792 // Every system register in the encoding space is valid with the syntax
793 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
794 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]795}
796
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]797static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]798 uint64_t Address,
799 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]800 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]801
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]802 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]803}
804
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]805static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]806 uint64_t Address,
807 const void *Decoder) {
808 // This decoder exists to add the dummy Lane operand to the MCInst, which must
809 // be 1 in assembly but has no other real manifestation.
810 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
811 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
812 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
813
814 if (IsToVec) {
815 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
816 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
817 } else {
818 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
819 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
820 }
821
822 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]823 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]824
825 return Success;
826}
827
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]828static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]829 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]830 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]831 return Success;
832}
833
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]834static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]835 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]836 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]837 return Success;
838}
839
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]840static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]841 uint64_t Addr, const void *Decoder) {
842 return DecodeVecShiftRImm(Inst, Imm, 64);
843}
844
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]845static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]846 uint64_t Addr,
847 const void *Decoder) {
848 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
849}
850
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]851static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]852 uint64_t Addr, const void *Decoder) {
853 return DecodeVecShiftRImm(Inst, Imm, 32);
854}
855
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]856static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]857 uint64_t Addr,
858 const void *Decoder) {
859 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
860}
861
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]862static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]863 uint64_t Addr, const void *Decoder) {
864 return DecodeVecShiftRImm(Inst, Imm, 16);
865}
866
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]867static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]868 uint64_t Addr,
869 const void *Decoder) {
870 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
871}
872
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]873static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]874 uint64_t Addr, const void *Decoder) {
875 return DecodeVecShiftRImm(Inst, Imm, 8);
876}
877
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]878static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]879 uint64_t Addr, const void *Decoder) {
880 return DecodeVecShiftLImm(Inst, Imm, 64);
881}
882
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]883static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]884 uint64_t Addr, const void *Decoder) {
885 return DecodeVecShiftLImm(Inst, Imm, 32);
886}
887
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]888static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]889 uint64_t Addr, const void *Decoder) {
890 return DecodeVecShiftLImm(Inst, Imm, 16);
891}
892
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]893static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]894 uint64_t Addr, const void *Decoder) {
895 return DecodeVecShiftLImm(Inst, Imm, 8);
896}
897
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]898static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
899 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]900 const void *Decoder) {
901 unsigned Rd = fieldFromInstruction(insn, 0, 5);
902 unsigned Rn = fieldFromInstruction(insn, 5, 5);
903 unsigned Rm = fieldFromInstruction(insn, 16, 5);
904 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
905 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
906 unsigned shift = (shiftHi << 6) | shiftLo;
907 switch (Inst.getOpcode()) {
908 default:
909 return Fail;
910 case AArch64::ADDWrs:
911 case AArch64::ADDSWrs:
912 case AArch64::SUBWrs:
913 case AArch64::SUBSWrs:
914 // if shift == '11' then ReservedValue()
915 if (shiftHi == 0x3)
916 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]917 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]918 case AArch64::ANDWrs:
919 case AArch64::ANDSWrs:
920 case AArch64::BICWrs:
921 case AArch64::BICSWrs:
922 case AArch64::ORRWrs:
923 case AArch64::ORNWrs:
924 case AArch64::EORWrs:
925 case AArch64::EONWrs: {
926 // if sf == '0' and imm6<5> == '1' then ReservedValue()
927 if (shiftLo >> 5 == 1)
928 return Fail;
929 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
930 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
931 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
932 break;
933 }
934 case AArch64::ADDXrs:
935 case AArch64::ADDSXrs:
936 case AArch64::SUBXrs:
937 case AArch64::SUBSXrs:
938 // if shift == '11' then ReservedValue()
939 if (shiftHi == 0x3)
940 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]941 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]942 case AArch64::ANDXrs:
943 case AArch64::ANDSXrs:
944 case AArch64::BICXrs:
945 case AArch64::BICSXrs:
946 case AArch64::ORRXrs:
947 case AArch64::ORNXrs:
948 case AArch64::EORXrs:
949 case AArch64::EONXrs:
950 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
951 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
952 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
953 break;
954 }
955
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]956 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]957 return Success;
958}
959
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]960static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]961 uint64_t Addr,
962 const void *Decoder) {
963 unsigned Rd = fieldFromInstruction(insn, 0, 5);
964 unsigned imm = fieldFromInstruction(insn, 5, 16);
965 unsigned shift = fieldFromInstruction(insn, 21, 2);
966 shift <<= 4;
967 switch (Inst.getOpcode()) {
968 default:
969 return Fail;
970 case AArch64::MOVZWi:
971 case AArch64::MOVNWi:
972 case AArch64::MOVKWi:
973 if (shift & (1U << 5))
974 return Fail;
975 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
976 break;
977 case AArch64::MOVZXi:
978 case AArch64::MOVNXi:
979 case AArch64::MOVKXi:
980 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
981 break;
982 }
983
984 if (Inst.getOpcode() == AArch64::MOVKWi ||
985 Inst.getOpcode() == AArch64::MOVKXi)
986 Inst.addOperand(Inst.getOperand(0));
987
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]988 Inst.addOperand(MCOperand::createImm(imm));
989 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]990 return Success;
991}
992
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]993static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
994 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]995 const void *Decoder) {
996 unsigned Rt = fieldFromInstruction(insn, 0, 5);
997 unsigned Rn = fieldFromInstruction(insn, 5, 5);
998 unsigned offset = fieldFromInstruction(insn, 10, 12);
999 const AArch64Disassembler *Dis =
1000 static_cast<const AArch64Disassembler *>(Decoder);
1001
1002 switch (Inst.getOpcode()) {
1003 default:
1004 return Fail;
1005 case AArch64::PRFMui:
1006 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1007 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1008 break;
1009 case AArch64::STRBBui:
1010 case AArch64::LDRBBui:
1011 case AArch64::LDRSBWui:
1012 case AArch64::STRHHui:
1013 case AArch64::LDRHHui:
1014 case AArch64::LDRSHWui:
1015 case AArch64::STRWui:
1016 case AArch64::LDRWui:
1017 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1018 break;
1019 case AArch64::LDRSBXui:
1020 case AArch64::LDRSHXui:
1021 case AArch64::LDRSWui:
1022 case AArch64::STRXui:
1023 case AArch64::LDRXui:
1024 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1025 break;
1026 case AArch64::LDRQui:
1027 case AArch64::STRQui:
1028 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1029 break;
1030 case AArch64::LDRDui:
1031 case AArch64::STRDui:
1032 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1033 break;
1034 case AArch64::LDRSui:
1035 case AArch64::STRSui:
1036 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1037 break;
1038 case AArch64::LDRHui:
1039 case AArch64::STRHui:
1040 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1041 break;
1042 case AArch64::LDRBui:
1043 case AArch64::STRBui:
1044 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1045 break;
1046 }
1047
1048 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1049 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1050 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1051 return Success;
1052}
1053
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1054static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1055 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1056 const void *Decoder) {
1057 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1058 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1059 int64_t offset = fieldFromInstruction(insn, 12, 9);
1060
1061 // offset is a 9-bit signed immediate, so sign extend it to
1062 // fill the unsigned.
1063 if (offset & (1 << (9 - 1)))
1064 offset |= ~((1LL << 9) - 1);
1065
1066 // First operand is always the writeback to the address register, if needed.
1067 switch (Inst.getOpcode()) {
1068 default:
1069 break;
1070 case AArch64::LDRSBWpre:
1071 case AArch64::LDRSHWpre:
1072 case AArch64::STRBBpre:
1073 case AArch64::LDRBBpre:
1074 case AArch64::STRHHpre:
1075 case AArch64::LDRHHpre:
1076 case AArch64::STRWpre:
1077 case AArch64::LDRWpre:
1078 case AArch64::LDRSBWpost:
1079 case AArch64::LDRSHWpost:
1080 case AArch64::STRBBpost:
1081 case AArch64::LDRBBpost:
1082 case AArch64::STRHHpost:
1083 case AArch64::LDRHHpost:
1084 case AArch64::STRWpost:
1085 case AArch64::LDRWpost:
1086 case AArch64::LDRSBXpre:
1087 case AArch64::LDRSHXpre:
1088 case AArch64::STRXpre:
1089 case AArch64::LDRSWpre:
1090 case AArch64::LDRXpre:
1091 case AArch64::LDRSBXpost:
1092 case AArch64::LDRSHXpost:
1093 case AArch64::STRXpost:
1094 case AArch64::LDRSWpost:
1095 case AArch64::LDRXpost:
1096 case AArch64::LDRQpre:
1097 case AArch64::STRQpre:
1098 case AArch64::LDRQpost:
1099 case AArch64::STRQpost:
1100 case AArch64::LDRDpre:
1101 case AArch64::STRDpre:
1102 case AArch64::LDRDpost:
1103 case AArch64::STRDpost:
1104 case AArch64::LDRSpre:
1105 case AArch64::STRSpre:
1106 case AArch64::LDRSpost:
1107 case AArch64::STRSpost:
1108 case AArch64::LDRHpre:
1109 case AArch64::STRHpre:
1110 case AArch64::LDRHpost:
1111 case AArch64::STRHpost:
1112 case AArch64::LDRBpre:
1113 case AArch64::STRBpre:
1114 case AArch64::LDRBpost:
1115 case AArch64::STRBpost:
1116 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1117 break;
1118 }
1119
1120 switch (Inst.getOpcode()) {
1121 default:
1122 return Fail;
1123 case AArch64::PRFUMi:
1124 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1125 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1126 break;
1127 case AArch64::STURBBi:
1128 case AArch64::LDURBBi:
1129 case AArch64::LDURSBWi:
1130 case AArch64::STURHHi:
1131 case AArch64::LDURHHi:
1132 case AArch64::LDURSHWi:
1133 case AArch64::STURWi:
1134 case AArch64::LDURWi:
1135 case AArch64::LDTRSBWi:
1136 case AArch64::LDTRSHWi:
1137 case AArch64::STTRWi:
1138 case AArch64::LDTRWi:
1139 case AArch64::STTRHi:
1140 case AArch64::LDTRHi:
1141 case AArch64::LDTRBi:
1142 case AArch64::STTRBi:
1143 case AArch64::LDRSBWpre:
1144 case AArch64::LDRSHWpre:
1145 case AArch64::STRBBpre:
1146 case AArch64::LDRBBpre:
1147 case AArch64::STRHHpre:
1148 case AArch64::LDRHHpre:
1149 case AArch64::STRWpre:
1150 case AArch64::LDRWpre:
1151 case AArch64::LDRSBWpost:
1152 case AArch64::LDRSHWpost:
1153 case AArch64::STRBBpost:
1154 case AArch64::LDRBBpost:
1155 case AArch64::STRHHpost:
1156 case AArch64::LDRHHpost:
1157 case AArch64::STRWpost:
1158 case AArch64::LDRWpost:
1159 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1160 break;
1161 case AArch64::LDURSBXi:
1162 case AArch64::LDURSHXi:
1163 case AArch64::LDURSWi:
1164 case AArch64::STURXi:
1165 case AArch64::LDURXi:
1166 case AArch64::LDTRSBXi:
1167 case AArch64::LDTRSHXi:
1168 case AArch64::LDTRSWi:
1169 case AArch64::STTRXi:
1170 case AArch64::LDTRXi:
1171 case AArch64::LDRSBXpre:
1172 case AArch64::LDRSHXpre:
1173 case AArch64::STRXpre:
1174 case AArch64::LDRSWpre:
1175 case AArch64::LDRXpre:
1176 case AArch64::LDRSBXpost:
1177 case AArch64::LDRSHXpost:
1178 case AArch64::STRXpost:
1179 case AArch64::LDRSWpost:
1180 case AArch64::LDRXpost:
1181 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1182 break;
1183 case AArch64::LDURQi:
1184 case AArch64::STURQi:
1185 case AArch64::LDRQpre:
1186 case AArch64::STRQpre:
1187 case AArch64::LDRQpost:
1188 case AArch64::STRQpost:
1189 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1190 break;
1191 case AArch64::LDURDi:
1192 case AArch64::STURDi:
1193 case AArch64::LDRDpre:
1194 case AArch64::STRDpre:
1195 case AArch64::LDRDpost:
1196 case AArch64::STRDpost:
1197 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1198 break;
1199 case AArch64::LDURSi:
1200 case AArch64::STURSi:
1201 case AArch64::LDRSpre:
1202 case AArch64::STRSpre:
1203 case AArch64::LDRSpost:
1204 case AArch64::STRSpost:
1205 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1206 break;
1207 case AArch64::LDURHi:
1208 case AArch64::STURHi:
1209 case AArch64::LDRHpre:
1210 case AArch64::STRHpre:
1211 case AArch64::LDRHpost:
1212 case AArch64::STRHpost:
1213 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1214 break;
1215 case AArch64::LDURBi:
1216 case AArch64::STURBi:
1217 case AArch64::LDRBpre:
1218 case AArch64::STRBpre:
1219 case AArch64::LDRBpost:
1220 case AArch64::STRBpost:
1221 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1222 break;
1223 }
1224
1225 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1226 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1227
1228 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1229 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1230 bool IsFP = fieldFromInstruction(insn, 26, 1);
1231
1232 // Cannot write back to a transfer register (but xzr != sp).
1233 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1234 return SoftFail;
1235
1236 return Success;
1237}
1238
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1239static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1240 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1241 const void *Decoder) {
1242 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1243 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1244 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1245 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1246
1247 unsigned Opcode = Inst.getOpcode();
1248 switch (Opcode) {
1249 default:
1250 return Fail;
1251 case AArch64::STLXRW:
1252 case AArch64::STLXRB:
1253 case AArch64::STLXRH:
1254 case AArch64::STXRW:
1255 case AArch64::STXRB:
1256 case AArch64::STXRH:
1257 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1258 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1259 case AArch64::LDARW:
1260 case AArch64::LDARB:
1261 case AArch64::LDARH:
1262 case AArch64::LDAXRW:
1263 case AArch64::LDAXRB:
1264 case AArch64::LDAXRH:
1265 case AArch64::LDXRW:
1266 case AArch64::LDXRB:
1267 case AArch64::LDXRH:
1268 case AArch64::STLRW:
1269 case AArch64::STLRB:
1270 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1271 case AArch64::STLLRW:
1272 case AArch64::STLLRB:
1273 case AArch64::STLLRH:
1274 case AArch64::LDLARW:
1275 case AArch64::LDLARB:
1276 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1277 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1278 break;
1279 case AArch64::STLXRX:
1280 case AArch64::STXRX:
1281 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1282 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1283 case AArch64::LDARX:
1284 case AArch64::LDAXRX:
1285 case AArch64::LDXRX:
1286 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1287 case AArch64::LDLARX:
1288 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1289 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1290 break;
1291 case AArch64::STLXPW:
1292 case AArch64::STXPW:
1293 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1294 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1295 case AArch64::LDAXPW:
1296 case AArch64::LDXPW:
1297 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1298 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1299 break;
1300 case AArch64::STLXPX:
1301 case AArch64::STXPX:
1302 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1303 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1304 case AArch64::LDAXPX:
1305 case AArch64::LDXPX:
1306 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1307 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1308 break;
1309 }
1310
1311 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1312
1313 // You shouldn't load to the same register twice in an instruction...
1314 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1315 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1316 Rt == Rt2)
1317 return SoftFail;
1318
1319 return Success;
1320}
1321
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1322static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1323 uint64_t Addr,
1324 const void *Decoder) {
1325 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1326 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1327 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1328 int64_t offset = fieldFromInstruction(insn, 15, 7);
1329 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1330
1331 // offset is a 7-bit signed immediate, so sign extend it to
1332 // fill the unsigned.
1333 if (offset & (1 << (7 - 1)))
1334 offset |= ~((1LL << 7) - 1);
1335
1336 unsigned Opcode = Inst.getOpcode();
1337 bool NeedsDisjointWritebackTransfer = false;
1338
1339 // First operand is always writeback of base register.
1340 switch (Opcode) {
1341 default:
1342 break;
1343 case AArch64::LDPXpost:
1344 case AArch64::STPXpost:
1345 case AArch64::LDPSWpost:
1346 case AArch64::LDPXpre:
1347 case AArch64::STPXpre:
1348 case AArch64::LDPSWpre:
1349 case AArch64::LDPWpost:
1350 case AArch64::STPWpost:
1351 case AArch64::LDPWpre:
1352 case AArch64::STPWpre:
1353 case AArch64::LDPQpost:
1354 case AArch64::STPQpost:
1355 case AArch64::LDPQpre:
1356 case AArch64::STPQpre:
1357 case AArch64::LDPDpost:
1358 case AArch64::STPDpost:
1359 case AArch64::LDPDpre:
1360 case AArch64::STPDpre:
1361 case AArch64::LDPSpost:
1362 case AArch64::STPSpost:
1363 case AArch64::LDPSpre:
1364 case AArch64::STPSpre:
1365 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1366 break;
1367 }
1368
1369 switch (Opcode) {
1370 default:
1371 return Fail;
1372 case AArch64::LDPXpost:
1373 case AArch64::STPXpost:
1374 case AArch64::LDPSWpost:
1375 case AArch64::LDPXpre:
1376 case AArch64::STPXpre:
1377 case AArch64::LDPSWpre:
1378 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1379 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1380 case AArch64::LDNPXi:
1381 case AArch64::STNPXi:
1382 case AArch64::LDPXi:
1383 case AArch64::STPXi:
1384 case AArch64::LDPSWi:
1385 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1386 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1387 break;
1388 case AArch64::LDPWpost:
1389 case AArch64::STPWpost:
1390 case AArch64::LDPWpre:
1391 case AArch64::STPWpre:
1392 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1393 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1394 case AArch64::LDNPWi:
1395 case AArch64::STNPWi:
1396 case AArch64::LDPWi:
1397 case AArch64::STPWi:
1398 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1399 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1400 break;
1401 case AArch64::LDNPQi:
1402 case AArch64::STNPQi:
1403 case AArch64::LDPQpost:
1404 case AArch64::STPQpost:
1405 case AArch64::LDPQi:
1406 case AArch64::STPQi:
1407 case AArch64::LDPQpre:
1408 case AArch64::STPQpre:
1409 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1410 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1411 break;
1412 case AArch64::LDNPDi:
1413 case AArch64::STNPDi:
1414 case AArch64::LDPDpost:
1415 case AArch64::STPDpost:
1416 case AArch64::LDPDi:
1417 case AArch64::STPDi:
1418 case AArch64::LDPDpre:
1419 case AArch64::STPDpre:
1420 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1421 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1422 break;
1423 case AArch64::LDNPSi:
1424 case AArch64::STNPSi:
1425 case AArch64::LDPSpost:
1426 case AArch64::STPSpost:
1427 case AArch64::LDPSi:
1428 case AArch64::STPSi:
1429 case AArch64::LDPSpre:
1430 case AArch64::STPSpre:
1431 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1432 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1433 break;
1434 }
1435
1436 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1437 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1438
1439 // You shouldn't load to the same register twice in an instruction...
1440 if (IsLoad && Rt == Rt2)
1441 return SoftFail;
1442
1443 // ... or do any operation that writes-back to a transfer register. But note
1444 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1445 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1446 return SoftFail;
1447
1448 return Success;
1449}
1450
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1451static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1452 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1453 const void *Decoder) {
1454 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1455 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1456 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1457 unsigned extend = fieldFromInstruction(insn, 10, 6);
1458
1459 unsigned shift = extend & 0x7;
1460 if (shift > 4)
1461 return Fail;
1462
1463 switch (Inst.getOpcode()) {
1464 default:
1465 return Fail;
1466 case AArch64::ADDWrx:
1467 case AArch64::SUBWrx:
1468 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1469 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1470 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1471 break;
1472 case AArch64::ADDSWrx:
1473 case AArch64::SUBSWrx:
1474 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1475 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1476 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1477 break;
1478 case AArch64::ADDXrx:
1479 case AArch64::SUBXrx:
1480 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1481 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1482 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1483 break;
1484 case AArch64::ADDSXrx:
1485 case AArch64::SUBSXrx:
1486 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1487 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1488 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1489 break;
1490 case AArch64::ADDXrx64:
1491 case AArch64::SUBXrx64:
1492 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1493 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1494 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1495 break;
1496 case AArch64::SUBSXrx64:
1497 case AArch64::ADDSXrx64:
1498 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1499 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1500 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1501 break;
1502 }
1503
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1504 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1505 return Success;
1506}
1507
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1508static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1509 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1510 const void *Decoder) {
1511 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1512 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1513 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1514 unsigned imm;
1515
1516 if (Datasize) {
1517 if (Inst.getOpcode() == AArch64::ANDSXri)
1518 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1519 else
1520 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1521 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1522 imm = fieldFromInstruction(insn, 10, 13);
1523 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1524 return Fail;
1525 } else {
1526 if (Inst.getOpcode() == AArch64::ANDSWri)
1527 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1528 else
1529 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1530 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1531 imm = fieldFromInstruction(insn, 10, 12);
1532 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1533 return Fail;
1534 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1535 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1536 return Success;
1537}
1538
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1539static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1540 uint64_t Addr,
1541 const void *Decoder) {
1542 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1543 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1544 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1545 imm |= fieldFromInstruction(insn, 5, 5);
1546
1547 if (Inst.getOpcode() == AArch64::MOVID)
1548 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1549 else
1550 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1551
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1552 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1553
1554 switch (Inst.getOpcode()) {
1555 default:
1556 break;
1557 case AArch64::MOVIv4i16:
1558 case AArch64::MOVIv8i16:
1559 case AArch64::MVNIv4i16:
1560 case AArch64::MVNIv8i16:
1561 case AArch64::MOVIv2i32:
1562 case AArch64::MOVIv4i32:
1563 case AArch64::MVNIv2i32:
1564 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1565 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1566 break;
1567 case AArch64::MOVIv2s_msl:
1568 case AArch64::MOVIv4s_msl:
1569 case AArch64::MVNIv2s_msl:
1570 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1571 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1572 break;
1573 }
1574
1575 return Success;
1576}
1577
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1578static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1579 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1580 const void *Decoder) {
1581 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1582 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1583 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1584 imm |= fieldFromInstruction(insn, 5, 5);
1585
1586 // Tied operands added twice.
1587 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1588 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1589
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1590 Inst.addOperand(MCOperand::createImm(imm));
1591 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1592
1593 return Success;
1594}
1595
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1596static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1597 uint64_t Addr, const void *Decoder) {
1598 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1599 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1600 imm |= fieldFromInstruction(insn, 29, 2);
1601 const AArch64Disassembler *Dis =
1602 static_cast<const AArch64Disassembler *>(Decoder);
1603
1604 // Sign-extend the 21-bit immediate.
1605 if (imm & (1 << (21 - 1)))
1606 imm |= ~((1LL << 21) - 1);
1607
1608 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1609 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1610 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1611
1612 return Success;
1613}
1614
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1615static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1616 uint64_t Addr, const void *Decoder) {
1617 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1618 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1619 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1620 unsigned S = fieldFromInstruction(insn, 29, 1);
1621 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1622
1623 unsigned ShifterVal = (Imm >> 12) & 3;
1624 unsigned ImmVal = Imm & 0xFFF;
1625 const AArch64Disassembler *Dis =
1626 static_cast<const AArch64Disassembler *>(Decoder);
1627
1628 if (ShifterVal != 0 && ShifterVal != 1)
1629 return Fail;
1630
1631 if (Datasize) {
1632 if (Rd == 31 && !S)
1633 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1634 else
1635 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1636 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1637 } else {
1638 if (Rd == 31 && !S)
1639 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1640 else
1641 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1642 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1643 }
1644
1645 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1646 Inst.addOperand(MCOperand::createImm(ImmVal));
1647 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1648 return Success;
1649}
1650
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1651static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1652 uint64_t Addr,
1653 const void *Decoder) {
1654 int64_t imm = fieldFromInstruction(insn, 0, 26);
1655 const AArch64Disassembler *Dis =
1656 static_cast<const AArch64Disassembler *>(Decoder);
1657
1658 // Sign-extend the 26-bit immediate.
1659 if (imm & (1 << (26 - 1)))
1660 imm |= ~((1LL << 26) - 1);
1661
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1662 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1663 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1664
1665 return Success;
1666}
1667
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1668static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1669 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1670 const void *Decoder) {
1671 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1672 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1673 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1674
1675 uint64_t pstate_field = (op1 << 3) | op2;
1676
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1677 if ((pstate_field == AArch64PState::PAN ||
1678 pstate_field == AArch64PState::UAO) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1679 return Fail;
1680
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1681 Inst.addOperand(MCOperand::createImm(pstate_field));
1682 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1683
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1684 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1685 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1686 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1687 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1688 return Success;
1689 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1690}
1691
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1692static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1693 uint64_t Addr, const void *Decoder) {
1694 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1695 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1696 bit |= fieldFromInstruction(insn, 19, 5);
1697 int64_t dst = fieldFromInstruction(insn, 5, 14);
1698 const AArch64Disassembler *Dis =
1699 static_cast<const AArch64Disassembler *>(Decoder);
1700
1701 // Sign-extend 14-bit immediate.
1702 if (dst & (1 << (14 - 1)))
1703 dst |= ~((1LL << 14) - 1);
1704
1705 if (fieldFromInstruction(insn, 31, 1) == 0)
1706 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1707 else
1708 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1709 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1710 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1711 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1712
1713 return Success;
1714}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1715
1716static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1717 unsigned RegClassID,
1718 unsigned RegNo,
1719 uint64_t Addr,
1720 const void *Decoder) {
1721 // Register number must be even (see CASP instruction)
1722 if (RegNo & 0x1)
1723 return Fail;
1724
1725 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1726 Inst.addOperand(MCOperand::createReg(Register));
1727 return Success;
1728}
1729
1730static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1731 unsigned RegNo,
1732 uint64_t Addr,
1733 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1734 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1735 AArch64::WSeqPairsClassRegClassID,
1736 RegNo, Addr, Decoder);
1737}
1738
1739static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1740 unsigned RegNo,
1741 uint64_t Addr,
1742 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1743 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1744 AArch64::XSeqPairsClassRegClassID,
1745 RegNo, Addr, Decoder);
1746}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1747
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1748static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1749 uint32_t insn,
1750 uint64_t Addr,
1751 const void *Decoder) {
1752 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1753 unsigned imm = fieldFromInstruction(insn, 5, 13);
1754 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1755 return Fail;
1756
1757 // The same (tied) operand is added twice to the instruction.
1758 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1759 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1760 Inst.addOperand(MCOperand::createImm(imm));
1761 return Success;
1762}
1763
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1764template<int Bits>
1765static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1766 uint64_t Address, const void *Decoder) {
1767 if (Imm & ~((1LL << Bits) - 1))
1768 return Fail;
1769
1770 // Imm is a signed immediate, so sign extend it.
1771 if (Imm & (1 << (Bits - 1)))
1772 Imm |= ~((1LL << Bits) - 1);
1773
1774 Inst.addOperand(MCOperand::createImm(Imm));
1775 return Success;
1776}
1777