Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / d239eb3ce375b238ac2793152417754795b371ba / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: ff1904cec78d95c1dab400cd368ff6e3feb2733f [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
15#include "AArch64Subtarget.h"
16#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]17#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]19#include "llvm-c/Disassembler.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]22#include "llvm/MC/MCInst.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]27#include <algorithm>
28#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-disassembler"
33
34// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]35using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36
37// Forward declare these because the autogenerated code will reference them.
38// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]39static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 unsigned RegNo, uint64_t Address,
41 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]42static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43 unsigned RegNo,
44 uint64_t Address,
45 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]46static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47 uint64_t Address,
48 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]49static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50 uint64_t Address,
51 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]52static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53 uint64_t Address,
54 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]55static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56 uint64_t Address,
57 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]58static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]59 uint64_t Address,
60 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]61static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]62 unsigned RegNo, uint64_t Address,
63 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]64static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]65 uint64_t Address,
66 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]67static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]68 unsigned RegNo, uint64_t Address,
69 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]70static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]71 uint64_t Address,
72 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]73static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]74 uint64_t Address,
75 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]76static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]77 uint64_t Address,
78 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]79static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80 uint64_t Address,
81 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]82static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]83 uint64_t Address,
84 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]85static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 uint64_t Address,
87 const void *Decoder);
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]88static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
89 uint64_t Address,
90 const void *Decode);
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]91static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
92 uint64_t Address,
93 const void *Decode);
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame^]94static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
95 uint64_t Address,
96 const void *Decode);
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]97static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
98 uint64_t Address,
99 const void *Decode);
Sander de Smalen906a5de2018-01-09 17:01:27 +0000[diff] [blame]100static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
101 uint64_t Address,
102 const void *Decode);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]103
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]104static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]105 uint64_t Address,
106 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]107static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]108 uint64_t Address,
109 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]110static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]112static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]114static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]116static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]118static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]119 uint64_t Address,
120 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]121static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]122 uint64_t Address,
123 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]124static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]125 uint64_t Address,
126 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]127static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
128 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]129 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]130static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]131 uint64_t Address,
132 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]133static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]134 uint64_t Address,
135 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]136static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
137 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]138 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]139static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
140 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]141 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]142static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]143 uint64_t Address,
144 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]145static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
146 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]147 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]148static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]149 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]150static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]152static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]153 uint64_t Address,
154 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]155static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]156 uint64_t Address,
157 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]158static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]159 uint64_t Address, const void *Decoder);
160
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]161static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]162 uint64_t Address,
163 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]164static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]166static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]167 uint64_t Addr,
168 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]169static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]170 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]171static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]172 uint64_t Addr,
173 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]174static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]175 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]176static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]177 uint64_t Addr,
178 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]179static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]180 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]181static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]182 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]183static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]184 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]185static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]186 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]187static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]188 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]189static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
190 unsigned RegNo,
191 uint64_t Addr,
192 const void *Decoder);
193static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
194 unsigned RegNo,
195 uint64_t Addr,
196 const void *Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]197static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
198 uint32_t insn,
199 uint64_t Address,
200 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]201template<int Bits>
202static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
203 uint64_t Address, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]204
205static bool Check(DecodeStatus &Out, DecodeStatus In) {
206 switch (In) {
207 case MCDisassembler::Success:
208 // Out stays the same.
209 return true;
210 case MCDisassembler::SoftFail:
211 Out = In;
212 return true;
213 case MCDisassembler::Fail:
214 Out = In;
215 return false;
216 }
217 llvm_unreachable("Invalid DecodeStatus!");
218}
219
220#include "AArch64GenDisassemblerTables.inc"
221#include "AArch64GenInstrInfo.inc"
222
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]223#define Success MCDisassembler::Success
224#define Fail MCDisassembler::Fail
225#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]226
227static MCDisassembler *createAArch64Disassembler(const Target &T,
228 const MCSubtargetInfo &STI,
229 MCContext &Ctx) {
230 return new AArch64Disassembler(STI, Ctx);
231}
232
233DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]234 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]235 uint64_t Address,
236 raw_ostream &OS,
237 raw_ostream &CS) const {
238 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]239
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]240 Size = 0;
241 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]242 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]243 return Fail;
244 Size = 4;
245
246 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]247 uint32_t Insn =
248 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]249
250 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]251 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]252}
253
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]254static MCSymbolizer *
255createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
256 LLVMSymbolLookupCallback SymbolLookUp,
257 void *DisInfo, MCContext *Ctx,
258 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]259 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
260 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]261}
262
263extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]264 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]265 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]266 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]267 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]268 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]269 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]270 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]271 createAArch64ExternalSymbolizer);
272
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]273 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]274 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]275 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]276 createAArch64ExternalSymbolizer);
277}
278
279static const unsigned FPR128DecoderTable[] = {
280 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
281 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
282 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
283 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
284 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
285 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
286 AArch64::Q30, AArch64::Q31
287};
288
289static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
290 uint64_t Addr,
291 const void *Decoder) {
292 if (RegNo > 31)
293 return Fail;
294
295 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]296 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]297 return Success;
298}
299
300static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
301 uint64_t Addr,
302 const void *Decoder) {
303 if (RegNo > 15)
304 return Fail;
305 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
306}
307
308static const unsigned FPR64DecoderTable[] = {
309 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
310 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
311 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
312 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
313 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
314 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
315 AArch64::D30, AArch64::D31
316};
317
318static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
319 uint64_t Addr,
320 const void *Decoder) {
321 if (RegNo > 31)
322 return Fail;
323
324 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]325 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]326 return Success;
327}
328
329static const unsigned FPR32DecoderTable[] = {
330 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
331 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
332 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
333 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
334 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
335 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
336 AArch64::S30, AArch64::S31
337};
338
339static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
340 uint64_t Addr,
341 const void *Decoder) {
342 if (RegNo > 31)
343 return Fail;
344
345 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]346 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]347 return Success;
348}
349
350static const unsigned FPR16DecoderTable[] = {
351 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
352 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
353 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
354 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
355 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
356 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
357 AArch64::H30, AArch64::H31
358};
359
360static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
361 uint64_t Addr,
362 const void *Decoder) {
363 if (RegNo > 31)
364 return Fail;
365
366 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]367 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]368 return Success;
369}
370
371static const unsigned FPR8DecoderTable[] = {
372 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
373 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
374 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
375 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
376 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
377 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
378 AArch64::B30, AArch64::B31
379};
380
381static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
382 uint64_t Addr,
383 const void *Decoder) {
384 if (RegNo > 31)
385 return Fail;
386
387 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]388 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]389 return Success;
390}
391
392static const unsigned GPR64DecoderTable[] = {
393 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
394 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
395 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
396 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
397 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
398 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
399 AArch64::LR, AArch64::XZR
400};
401
402static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
403 uint64_t Addr,
404 const void *Decoder) {
405 if (RegNo > 31)
406 return Fail;
407
408 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]409 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]410 return Success;
411}
412
413static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
414 uint64_t Addr,
415 const void *Decoder) {
416 if (RegNo > 31)
417 return Fail;
418 unsigned Register = GPR64DecoderTable[RegNo];
419 if (Register == AArch64::XZR)
420 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]421 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]422 return Success;
423}
424
425static const unsigned GPR32DecoderTable[] = {
426 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
427 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
428 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
429 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
430 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
431 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
432 AArch64::W30, AArch64::WZR
433};
434
435static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
436 uint64_t Addr,
437 const void *Decoder) {
438 if (RegNo > 31)
439 return Fail;
440
441 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]442 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]443 return Success;
444}
445
446static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
447 uint64_t Addr,
448 const void *Decoder) {
449 if (RegNo > 31)
450 return Fail;
451
452 unsigned Register = GPR32DecoderTable[RegNo];
453 if (Register == AArch64::WZR)
454 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]455 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]456 return Success;
457}
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]458static const unsigned ZPRDecoderTable[] = {
459 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
460 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
461 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
462 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
463 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
464 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
465 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
466 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
467};
468
469static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
470 uint64_t Address,
471 const void* Decoder) {
472 if (RegNo > 31)
473 return Fail;
474
475 unsigned Register = ZPRDecoderTable[RegNo];
476 Inst.addOperand(MCOperand::createReg(Register));
477 return Success;
478}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]479
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]480static const unsigned ZZDecoderTable[] = {
481 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
482 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
483 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
484 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
485 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
486 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
487 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
488 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
489};
490
491static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
492 uint64_t Address,
493 const void* Decoder) {
494 if (RegNo > 31)
495 return Fail;
496 unsigned Register = ZZDecoderTable[RegNo];
497 Inst.addOperand(MCOperand::createReg(Register));
498 return Success;
499}
500
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame^]501static const unsigned ZZZDecoderTable[] = {
502 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
503 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
504 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
505 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
506 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
507 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
508 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
509 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
510 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
511 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
512 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
513};
514
515static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
516 uint64_t Address,
517 const void* Decoder) {
518 if (RegNo > 31)
519 return Fail;
520 unsigned Register = ZZZDecoderTable[RegNo];
521 Inst.addOperand(MCOperand::createReg(Register));
522 return Success;
523}
524
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]525static const unsigned PPRDecoderTable[] = {
526 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
527 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
528 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
529 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
530};
531
532static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
533 uint64_t Addr, const void *Decoder) {
534 if (RegNo > 15)
535 return Fail;
536
537 unsigned Register = PPRDecoderTable[RegNo];
538 Inst.addOperand(MCOperand::createReg(Register));
539 return Success;
540}
541
Sander de Smalendc5e0812018-01-03 10:15:46 +0000[diff] [blame]542static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
543 uint64_t Addr,
544 const void* Decoder) {
545 if (RegNo > 7)
546 return Fail;
547
548 // Just reuse the PPR decode table
549 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
550}
551
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]552static const unsigned VectorDecoderTable[] = {
553 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
554 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
555 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
556 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
557 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
558 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
559 AArch64::Q30, AArch64::Q31
560};
561
562static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
563 uint64_t Addr,
564 const void *Decoder) {
565 if (RegNo > 31)
566 return Fail;
567
568 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]569 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]570 return Success;
571}
572
573static const unsigned QQDecoderTable[] = {
574 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
575 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
576 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
577 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
578 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
579 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
580 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
581 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
582};
583
584static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
585 uint64_t Addr, const void *Decoder) {
586 if (RegNo > 31)
587 return Fail;
588 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]589 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]590 return Success;
591}
592
593static const unsigned QQQDecoderTable[] = {
594 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
595 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
596 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
597 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
598 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
599 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
600 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
601 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
602 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
603 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
604 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
605};
606
607static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
608 uint64_t Addr, const void *Decoder) {
609 if (RegNo > 31)
610 return Fail;
611 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]612 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]613 return Success;
614}
615
616static const unsigned QQQQDecoderTable[] = {
617 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
618 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
619 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
620 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
621 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
622 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
623 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
624 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
625 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
626 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
627 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
628};
629
630static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
631 uint64_t Addr,
632 const void *Decoder) {
633 if (RegNo > 31)
634 return Fail;
635 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]636 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]637 return Success;
638}
639
640static const unsigned DDDecoderTable[] = {
641 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
642 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
643 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
644 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
645 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
646 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
647 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
648 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
649};
650
651static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
652 uint64_t Addr, const void *Decoder) {
653 if (RegNo > 31)
654 return Fail;
655 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]656 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]657 return Success;
658}
659
660static const unsigned DDDDecoderTable[] = {
661 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
662 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
663 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
664 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
665 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
666 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
667 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
668 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
669 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
670 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
671 AArch64::D30_D31_D0, AArch64::D31_D0_D1
672};
673
674static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
675 uint64_t Addr, const void *Decoder) {
676 if (RegNo > 31)
677 return Fail;
678 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]679 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]680 return Success;
681}
682
683static const unsigned DDDDDecoderTable[] = {
684 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
685 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
686 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
687 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
688 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
689 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
690 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
691 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
692 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
693 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
694 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
695};
696
697static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
698 uint64_t Addr,
699 const void *Decoder) {
700 if (RegNo > 31)
701 return Fail;
702 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]703 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]704 return Success;
705}
706
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]707static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]708 uint64_t Addr,
709 const void *Decoder) {
710 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]711 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]712 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]713 return Success;
714}
715
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]716static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]717 uint64_t Addr,
718 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]719 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]720 return Success;
721}
722
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]723static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]724 uint64_t Addr, const void *Decoder) {
725 int64_t ImmVal = Imm;
726 const AArch64Disassembler *Dis =
727 static_cast<const AArch64Disassembler *>(Decoder);
728
729 // Sign-extend 19-bit immediate.
730 if (ImmVal & (1 << (19 - 1)))
731 ImmVal |= ~((1LL << 19) - 1);
732
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]733 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]734 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]735 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]736 return Success;
737}
738
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]739static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]740 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]741 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
742 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]743 return Success;
744}
745
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]746static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]747 uint64_t Address,
748 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]749 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]750
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]751 // Every system register in the encoding space is valid with the syntax
752 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
753 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]754}
755
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]756static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]757 uint64_t Address,
758 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]759 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]760
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]761 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]762}
763
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]764static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]765 uint64_t Address,
766 const void *Decoder) {
767 // This decoder exists to add the dummy Lane operand to the MCInst, which must
768 // be 1 in assembly but has no other real manifestation.
769 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
770 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
771 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
772
773 if (IsToVec) {
774 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
775 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
776 } else {
777 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
778 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
779 }
780
781 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]782 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]783
784 return Success;
785}
786
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]787static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]788 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]789 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]790 return Success;
791}
792
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]793static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]794 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]795 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]796 return Success;
797}
798
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]799static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]800 uint64_t Addr, const void *Decoder) {
801 return DecodeVecShiftRImm(Inst, Imm, 64);
802}
803
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]804static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]805 uint64_t Addr,
806 const void *Decoder) {
807 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
808}
809
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]810static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]811 uint64_t Addr, const void *Decoder) {
812 return DecodeVecShiftRImm(Inst, Imm, 32);
813}
814
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]815static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]816 uint64_t Addr,
817 const void *Decoder) {
818 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
819}
820
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]821static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]822 uint64_t Addr, const void *Decoder) {
823 return DecodeVecShiftRImm(Inst, Imm, 16);
824}
825
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]826static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]827 uint64_t Addr,
828 const void *Decoder) {
829 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
830}
831
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]832static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]833 uint64_t Addr, const void *Decoder) {
834 return DecodeVecShiftRImm(Inst, Imm, 8);
835}
836
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]837static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]838 uint64_t Addr, const void *Decoder) {
839 return DecodeVecShiftLImm(Inst, Imm, 64);
840}
841
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]842static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]843 uint64_t Addr, const void *Decoder) {
844 return DecodeVecShiftLImm(Inst, Imm, 32);
845}
846
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]847static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]848 uint64_t Addr, const void *Decoder) {
849 return DecodeVecShiftLImm(Inst, Imm, 16);
850}
851
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]852static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]853 uint64_t Addr, const void *Decoder) {
854 return DecodeVecShiftLImm(Inst, Imm, 8);
855}
856
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]857static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
858 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]859 const void *Decoder) {
860 unsigned Rd = fieldFromInstruction(insn, 0, 5);
861 unsigned Rn = fieldFromInstruction(insn, 5, 5);
862 unsigned Rm = fieldFromInstruction(insn, 16, 5);
863 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
864 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
865 unsigned shift = (shiftHi << 6) | shiftLo;
866 switch (Inst.getOpcode()) {
867 default:
868 return Fail;
869 case AArch64::ADDWrs:
870 case AArch64::ADDSWrs:
871 case AArch64::SUBWrs:
872 case AArch64::SUBSWrs:
873 // if shift == '11' then ReservedValue()
874 if (shiftHi == 0x3)
875 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]876 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]877 case AArch64::ANDWrs:
878 case AArch64::ANDSWrs:
879 case AArch64::BICWrs:
880 case AArch64::BICSWrs:
881 case AArch64::ORRWrs:
882 case AArch64::ORNWrs:
883 case AArch64::EORWrs:
884 case AArch64::EONWrs: {
885 // if sf == '0' and imm6<5> == '1' then ReservedValue()
886 if (shiftLo >> 5 == 1)
887 return Fail;
888 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
889 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
890 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
891 break;
892 }
893 case AArch64::ADDXrs:
894 case AArch64::ADDSXrs:
895 case AArch64::SUBXrs:
896 case AArch64::SUBSXrs:
897 // if shift == '11' then ReservedValue()
898 if (shiftHi == 0x3)
899 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]900 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]901 case AArch64::ANDXrs:
902 case AArch64::ANDSXrs:
903 case AArch64::BICXrs:
904 case AArch64::BICSXrs:
905 case AArch64::ORRXrs:
906 case AArch64::ORNXrs:
907 case AArch64::EORXrs:
908 case AArch64::EONXrs:
909 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
910 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
911 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
912 break;
913 }
914
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]915 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]916 return Success;
917}
918
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]919static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]920 uint64_t Addr,
921 const void *Decoder) {
922 unsigned Rd = fieldFromInstruction(insn, 0, 5);
923 unsigned imm = fieldFromInstruction(insn, 5, 16);
924 unsigned shift = fieldFromInstruction(insn, 21, 2);
925 shift <<= 4;
926 switch (Inst.getOpcode()) {
927 default:
928 return Fail;
929 case AArch64::MOVZWi:
930 case AArch64::MOVNWi:
931 case AArch64::MOVKWi:
932 if (shift & (1U << 5))
933 return Fail;
934 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
935 break;
936 case AArch64::MOVZXi:
937 case AArch64::MOVNXi:
938 case AArch64::MOVKXi:
939 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
940 break;
941 }
942
943 if (Inst.getOpcode() == AArch64::MOVKWi ||
944 Inst.getOpcode() == AArch64::MOVKXi)
945 Inst.addOperand(Inst.getOperand(0));
946
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]947 Inst.addOperand(MCOperand::createImm(imm));
948 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]949 return Success;
950}
951
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]952static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
953 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]954 const void *Decoder) {
955 unsigned Rt = fieldFromInstruction(insn, 0, 5);
956 unsigned Rn = fieldFromInstruction(insn, 5, 5);
957 unsigned offset = fieldFromInstruction(insn, 10, 12);
958 const AArch64Disassembler *Dis =
959 static_cast<const AArch64Disassembler *>(Decoder);
960
961 switch (Inst.getOpcode()) {
962 default:
963 return Fail;
964 case AArch64::PRFMui:
965 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]966 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]967 break;
968 case AArch64::STRBBui:
969 case AArch64::LDRBBui:
970 case AArch64::LDRSBWui:
971 case AArch64::STRHHui:
972 case AArch64::LDRHHui:
973 case AArch64::LDRSHWui:
974 case AArch64::STRWui:
975 case AArch64::LDRWui:
976 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
977 break;
978 case AArch64::LDRSBXui:
979 case AArch64::LDRSHXui:
980 case AArch64::LDRSWui:
981 case AArch64::STRXui:
982 case AArch64::LDRXui:
983 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
984 break;
985 case AArch64::LDRQui:
986 case AArch64::STRQui:
987 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
988 break;
989 case AArch64::LDRDui:
990 case AArch64::STRDui:
991 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
992 break;
993 case AArch64::LDRSui:
994 case AArch64::STRSui:
995 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
996 break;
997 case AArch64::LDRHui:
998 case AArch64::STRHui:
999 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1000 break;
1001 case AArch64::LDRBui:
1002 case AArch64::STRBui:
1003 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1004 break;
1005 }
1006
1007 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1008 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1009 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1010 return Success;
1011}
1012
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1013static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1014 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1015 const void *Decoder) {
1016 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1017 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1018 int64_t offset = fieldFromInstruction(insn, 12, 9);
1019
1020 // offset is a 9-bit signed immediate, so sign extend it to
1021 // fill the unsigned.
1022 if (offset & (1 << (9 - 1)))
1023 offset |= ~((1LL << 9) - 1);
1024
1025 // First operand is always the writeback to the address register, if needed.
1026 switch (Inst.getOpcode()) {
1027 default:
1028 break;
1029 case AArch64::LDRSBWpre:
1030 case AArch64::LDRSHWpre:
1031 case AArch64::STRBBpre:
1032 case AArch64::LDRBBpre:
1033 case AArch64::STRHHpre:
1034 case AArch64::LDRHHpre:
1035 case AArch64::STRWpre:
1036 case AArch64::LDRWpre:
1037 case AArch64::LDRSBWpost:
1038 case AArch64::LDRSHWpost:
1039 case AArch64::STRBBpost:
1040 case AArch64::LDRBBpost:
1041 case AArch64::STRHHpost:
1042 case AArch64::LDRHHpost:
1043 case AArch64::STRWpost:
1044 case AArch64::LDRWpost:
1045 case AArch64::LDRSBXpre:
1046 case AArch64::LDRSHXpre:
1047 case AArch64::STRXpre:
1048 case AArch64::LDRSWpre:
1049 case AArch64::LDRXpre:
1050 case AArch64::LDRSBXpost:
1051 case AArch64::LDRSHXpost:
1052 case AArch64::STRXpost:
1053 case AArch64::LDRSWpost:
1054 case AArch64::LDRXpost:
1055 case AArch64::LDRQpre:
1056 case AArch64::STRQpre:
1057 case AArch64::LDRQpost:
1058 case AArch64::STRQpost:
1059 case AArch64::LDRDpre:
1060 case AArch64::STRDpre:
1061 case AArch64::LDRDpost:
1062 case AArch64::STRDpost:
1063 case AArch64::LDRSpre:
1064 case AArch64::STRSpre:
1065 case AArch64::LDRSpost:
1066 case AArch64::STRSpost:
1067 case AArch64::LDRHpre:
1068 case AArch64::STRHpre:
1069 case AArch64::LDRHpost:
1070 case AArch64::STRHpost:
1071 case AArch64::LDRBpre:
1072 case AArch64::STRBpre:
1073 case AArch64::LDRBpost:
1074 case AArch64::STRBpost:
1075 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1076 break;
1077 }
1078
1079 switch (Inst.getOpcode()) {
1080 default:
1081 return Fail;
1082 case AArch64::PRFUMi:
1083 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1084 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1085 break;
1086 case AArch64::STURBBi:
1087 case AArch64::LDURBBi:
1088 case AArch64::LDURSBWi:
1089 case AArch64::STURHHi:
1090 case AArch64::LDURHHi:
1091 case AArch64::LDURSHWi:
1092 case AArch64::STURWi:
1093 case AArch64::LDURWi:
1094 case AArch64::LDTRSBWi:
1095 case AArch64::LDTRSHWi:
1096 case AArch64::STTRWi:
1097 case AArch64::LDTRWi:
1098 case AArch64::STTRHi:
1099 case AArch64::LDTRHi:
1100 case AArch64::LDTRBi:
1101 case AArch64::STTRBi:
1102 case AArch64::LDRSBWpre:
1103 case AArch64::LDRSHWpre:
1104 case AArch64::STRBBpre:
1105 case AArch64::LDRBBpre:
1106 case AArch64::STRHHpre:
1107 case AArch64::LDRHHpre:
1108 case AArch64::STRWpre:
1109 case AArch64::LDRWpre:
1110 case AArch64::LDRSBWpost:
1111 case AArch64::LDRSHWpost:
1112 case AArch64::STRBBpost:
1113 case AArch64::LDRBBpost:
1114 case AArch64::STRHHpost:
1115 case AArch64::LDRHHpost:
1116 case AArch64::STRWpost:
1117 case AArch64::LDRWpost:
1118 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1119 break;
1120 case AArch64::LDURSBXi:
1121 case AArch64::LDURSHXi:
1122 case AArch64::LDURSWi:
1123 case AArch64::STURXi:
1124 case AArch64::LDURXi:
1125 case AArch64::LDTRSBXi:
1126 case AArch64::LDTRSHXi:
1127 case AArch64::LDTRSWi:
1128 case AArch64::STTRXi:
1129 case AArch64::LDTRXi:
1130 case AArch64::LDRSBXpre:
1131 case AArch64::LDRSHXpre:
1132 case AArch64::STRXpre:
1133 case AArch64::LDRSWpre:
1134 case AArch64::LDRXpre:
1135 case AArch64::LDRSBXpost:
1136 case AArch64::LDRSHXpost:
1137 case AArch64::STRXpost:
1138 case AArch64::LDRSWpost:
1139 case AArch64::LDRXpost:
1140 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1141 break;
1142 case AArch64::LDURQi:
1143 case AArch64::STURQi:
1144 case AArch64::LDRQpre:
1145 case AArch64::STRQpre:
1146 case AArch64::LDRQpost:
1147 case AArch64::STRQpost:
1148 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1149 break;
1150 case AArch64::LDURDi:
1151 case AArch64::STURDi:
1152 case AArch64::LDRDpre:
1153 case AArch64::STRDpre:
1154 case AArch64::LDRDpost:
1155 case AArch64::STRDpost:
1156 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1157 break;
1158 case AArch64::LDURSi:
1159 case AArch64::STURSi:
1160 case AArch64::LDRSpre:
1161 case AArch64::STRSpre:
1162 case AArch64::LDRSpost:
1163 case AArch64::STRSpost:
1164 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1165 break;
1166 case AArch64::LDURHi:
1167 case AArch64::STURHi:
1168 case AArch64::LDRHpre:
1169 case AArch64::STRHpre:
1170 case AArch64::LDRHpost:
1171 case AArch64::STRHpost:
1172 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1173 break;
1174 case AArch64::LDURBi:
1175 case AArch64::STURBi:
1176 case AArch64::LDRBpre:
1177 case AArch64::STRBpre:
1178 case AArch64::LDRBpost:
1179 case AArch64::STRBpost:
1180 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1181 break;
1182 }
1183
1184 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1185 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1186
1187 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1188 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1189 bool IsFP = fieldFromInstruction(insn, 26, 1);
1190
1191 // Cannot write back to a transfer register (but xzr != sp).
1192 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1193 return SoftFail;
1194
1195 return Success;
1196}
1197
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1198static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1199 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1200 const void *Decoder) {
1201 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1202 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1203 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1204 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1205
1206 unsigned Opcode = Inst.getOpcode();
1207 switch (Opcode) {
1208 default:
1209 return Fail;
1210 case AArch64::STLXRW:
1211 case AArch64::STLXRB:
1212 case AArch64::STLXRH:
1213 case AArch64::STXRW:
1214 case AArch64::STXRB:
1215 case AArch64::STXRH:
1216 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1217 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1218 case AArch64::LDARW:
1219 case AArch64::LDARB:
1220 case AArch64::LDARH:
1221 case AArch64::LDAXRW:
1222 case AArch64::LDAXRB:
1223 case AArch64::LDAXRH:
1224 case AArch64::LDXRW:
1225 case AArch64::LDXRB:
1226 case AArch64::LDXRH:
1227 case AArch64::STLRW:
1228 case AArch64::STLRB:
1229 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1230 case AArch64::STLLRW:
1231 case AArch64::STLLRB:
1232 case AArch64::STLLRH:
1233 case AArch64::LDLARW:
1234 case AArch64::LDLARB:
1235 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1236 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1237 break;
1238 case AArch64::STLXRX:
1239 case AArch64::STXRX:
1240 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1241 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1242 case AArch64::LDARX:
1243 case AArch64::LDAXRX:
1244 case AArch64::LDXRX:
1245 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1246 case AArch64::LDLARX:
1247 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1248 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1249 break;
1250 case AArch64::STLXPW:
1251 case AArch64::STXPW:
1252 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1253 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1254 case AArch64::LDAXPW:
1255 case AArch64::LDXPW:
1256 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1257 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1258 break;
1259 case AArch64::STLXPX:
1260 case AArch64::STXPX:
1261 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1262 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1263 case AArch64::LDAXPX:
1264 case AArch64::LDXPX:
1265 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1266 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1267 break;
1268 }
1269
1270 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1271
1272 // You shouldn't load to the same register twice in an instruction...
1273 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1274 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1275 Rt == Rt2)
1276 return SoftFail;
1277
1278 return Success;
1279}
1280
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1281static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1282 uint64_t Addr,
1283 const void *Decoder) {
1284 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1285 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1286 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1287 int64_t offset = fieldFromInstruction(insn, 15, 7);
1288 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1289
1290 // offset is a 7-bit signed immediate, so sign extend it to
1291 // fill the unsigned.
1292 if (offset & (1 << (7 - 1)))
1293 offset |= ~((1LL << 7) - 1);
1294
1295 unsigned Opcode = Inst.getOpcode();
1296 bool NeedsDisjointWritebackTransfer = false;
1297
1298 // First operand is always writeback of base register.
1299 switch (Opcode) {
1300 default:
1301 break;
1302 case AArch64::LDPXpost:
1303 case AArch64::STPXpost:
1304 case AArch64::LDPSWpost:
1305 case AArch64::LDPXpre:
1306 case AArch64::STPXpre:
1307 case AArch64::LDPSWpre:
1308 case AArch64::LDPWpost:
1309 case AArch64::STPWpost:
1310 case AArch64::LDPWpre:
1311 case AArch64::STPWpre:
1312 case AArch64::LDPQpost:
1313 case AArch64::STPQpost:
1314 case AArch64::LDPQpre:
1315 case AArch64::STPQpre:
1316 case AArch64::LDPDpost:
1317 case AArch64::STPDpost:
1318 case AArch64::LDPDpre:
1319 case AArch64::STPDpre:
1320 case AArch64::LDPSpost:
1321 case AArch64::STPSpost:
1322 case AArch64::LDPSpre:
1323 case AArch64::STPSpre:
1324 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1325 break;
1326 }
1327
1328 switch (Opcode) {
1329 default:
1330 return Fail;
1331 case AArch64::LDPXpost:
1332 case AArch64::STPXpost:
1333 case AArch64::LDPSWpost:
1334 case AArch64::LDPXpre:
1335 case AArch64::STPXpre:
1336 case AArch64::LDPSWpre:
1337 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1338 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1339 case AArch64::LDNPXi:
1340 case AArch64::STNPXi:
1341 case AArch64::LDPXi:
1342 case AArch64::STPXi:
1343 case AArch64::LDPSWi:
1344 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1345 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1346 break;
1347 case AArch64::LDPWpost:
1348 case AArch64::STPWpost:
1349 case AArch64::LDPWpre:
1350 case AArch64::STPWpre:
1351 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1352 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1353 case AArch64::LDNPWi:
1354 case AArch64::STNPWi:
1355 case AArch64::LDPWi:
1356 case AArch64::STPWi:
1357 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1358 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1359 break;
1360 case AArch64::LDNPQi:
1361 case AArch64::STNPQi:
1362 case AArch64::LDPQpost:
1363 case AArch64::STPQpost:
1364 case AArch64::LDPQi:
1365 case AArch64::STPQi:
1366 case AArch64::LDPQpre:
1367 case AArch64::STPQpre:
1368 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1369 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1370 break;
1371 case AArch64::LDNPDi:
1372 case AArch64::STNPDi:
1373 case AArch64::LDPDpost:
1374 case AArch64::STPDpost:
1375 case AArch64::LDPDi:
1376 case AArch64::STPDi:
1377 case AArch64::LDPDpre:
1378 case AArch64::STPDpre:
1379 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1380 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1381 break;
1382 case AArch64::LDNPSi:
1383 case AArch64::STNPSi:
1384 case AArch64::LDPSpost:
1385 case AArch64::STPSpost:
1386 case AArch64::LDPSi:
1387 case AArch64::STPSi:
1388 case AArch64::LDPSpre:
1389 case AArch64::STPSpre:
1390 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1391 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1392 break;
1393 }
1394
1395 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1396 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1397
1398 // You shouldn't load to the same register twice in an instruction...
1399 if (IsLoad && Rt == Rt2)
1400 return SoftFail;
1401
1402 // ... or do any operation that writes-back to a transfer register. But note
1403 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1404 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1405 return SoftFail;
1406
1407 return Success;
1408}
1409
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1410static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1411 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1412 const void *Decoder) {
1413 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1414 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1415 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1416 unsigned extend = fieldFromInstruction(insn, 10, 6);
1417
1418 unsigned shift = extend & 0x7;
1419 if (shift > 4)
1420 return Fail;
1421
1422 switch (Inst.getOpcode()) {
1423 default:
1424 return Fail;
1425 case AArch64::ADDWrx:
1426 case AArch64::SUBWrx:
1427 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1428 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1429 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1430 break;
1431 case AArch64::ADDSWrx:
1432 case AArch64::SUBSWrx:
1433 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1434 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1435 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1436 break;
1437 case AArch64::ADDXrx:
1438 case AArch64::SUBXrx:
1439 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1440 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1441 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1442 break;
1443 case AArch64::ADDSXrx:
1444 case AArch64::SUBSXrx:
1445 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1446 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1447 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1448 break;
1449 case AArch64::ADDXrx64:
1450 case AArch64::SUBXrx64:
1451 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1452 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1453 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1454 break;
1455 case AArch64::SUBSXrx64:
1456 case AArch64::ADDSXrx64:
1457 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1458 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1459 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1460 break;
1461 }
1462
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1463 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1464 return Success;
1465}
1466
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1467static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1468 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1469 const void *Decoder) {
1470 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1471 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1472 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1473 unsigned imm;
1474
1475 if (Datasize) {
1476 if (Inst.getOpcode() == AArch64::ANDSXri)
1477 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1478 else
1479 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1480 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1481 imm = fieldFromInstruction(insn, 10, 13);
1482 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1483 return Fail;
1484 } else {
1485 if (Inst.getOpcode() == AArch64::ANDSWri)
1486 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1487 else
1488 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1489 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1490 imm = fieldFromInstruction(insn, 10, 12);
1491 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1492 return Fail;
1493 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1494 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1495 return Success;
1496}
1497
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1498static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1499 uint64_t Addr,
1500 const void *Decoder) {
1501 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1502 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1503 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1504 imm |= fieldFromInstruction(insn, 5, 5);
1505
1506 if (Inst.getOpcode() == AArch64::MOVID)
1507 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1508 else
1509 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1510
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1511 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1512
1513 switch (Inst.getOpcode()) {
1514 default:
1515 break;
1516 case AArch64::MOVIv4i16:
1517 case AArch64::MOVIv8i16:
1518 case AArch64::MVNIv4i16:
1519 case AArch64::MVNIv8i16:
1520 case AArch64::MOVIv2i32:
1521 case AArch64::MOVIv4i32:
1522 case AArch64::MVNIv2i32:
1523 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1524 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1525 break;
1526 case AArch64::MOVIv2s_msl:
1527 case AArch64::MOVIv4s_msl:
1528 case AArch64::MVNIv2s_msl:
1529 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1530 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1531 break;
1532 }
1533
1534 return Success;
1535}
1536
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1537static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1538 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1539 const void *Decoder) {
1540 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1541 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1542 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1543 imm |= fieldFromInstruction(insn, 5, 5);
1544
1545 // Tied operands added twice.
1546 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1547 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1548
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1549 Inst.addOperand(MCOperand::createImm(imm));
1550 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1551
1552 return Success;
1553}
1554
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1555static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1556 uint64_t Addr, const void *Decoder) {
1557 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1558 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1559 imm |= fieldFromInstruction(insn, 29, 2);
1560 const AArch64Disassembler *Dis =
1561 static_cast<const AArch64Disassembler *>(Decoder);
1562
1563 // Sign-extend the 21-bit immediate.
1564 if (imm & (1 << (21 - 1)))
1565 imm |= ~((1LL << 21) - 1);
1566
1567 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1568 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1569 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1570
1571 return Success;
1572}
1573
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1574static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1575 uint64_t Addr, const void *Decoder) {
1576 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1577 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1578 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1579 unsigned S = fieldFromInstruction(insn, 29, 1);
1580 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1581
1582 unsigned ShifterVal = (Imm >> 12) & 3;
1583 unsigned ImmVal = Imm & 0xFFF;
1584 const AArch64Disassembler *Dis =
1585 static_cast<const AArch64Disassembler *>(Decoder);
1586
1587 if (ShifterVal != 0 && ShifterVal != 1)
1588 return Fail;
1589
1590 if (Datasize) {
1591 if (Rd == 31 && !S)
1592 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1593 else
1594 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1595 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1596 } else {
1597 if (Rd == 31 && !S)
1598 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1599 else
1600 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1601 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1602 }
1603
1604 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1605 Inst.addOperand(MCOperand::createImm(ImmVal));
1606 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1607 return Success;
1608}
1609
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1610static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1611 uint64_t Addr,
1612 const void *Decoder) {
1613 int64_t imm = fieldFromInstruction(insn, 0, 26);
1614 const AArch64Disassembler *Dis =
1615 static_cast<const AArch64Disassembler *>(Decoder);
1616
1617 // Sign-extend the 26-bit immediate.
1618 if (imm & (1 << (26 - 1)))
1619 imm |= ~((1LL << 26) - 1);
1620
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1621 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1622 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1623
1624 return Success;
1625}
1626
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1627static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1628 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1629 const void *Decoder) {
1630 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1631 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1632 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1633
1634 uint64_t pstate_field = (op1 << 3) | op2;
1635
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1636 if ((pstate_field == AArch64PState::PAN ||
1637 pstate_field == AArch64PState::UAO) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1638 return Fail;
1639
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1640 Inst.addOperand(MCOperand::createImm(pstate_field));
1641 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1642
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1643 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1644 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1645 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1646 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1647 return Success;
1648 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1649}
1650
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1651static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1652 uint64_t Addr, const void *Decoder) {
1653 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1654 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1655 bit |= fieldFromInstruction(insn, 19, 5);
1656 int64_t dst = fieldFromInstruction(insn, 5, 14);
1657 const AArch64Disassembler *Dis =
1658 static_cast<const AArch64Disassembler *>(Decoder);
1659
1660 // Sign-extend 14-bit immediate.
1661 if (dst & (1 << (14 - 1)))
1662 dst |= ~((1LL << 14) - 1);
1663
1664 if (fieldFromInstruction(insn, 31, 1) == 0)
1665 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1666 else
1667 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1668 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1669 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1670 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1671
1672 return Success;
1673}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1674
1675static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1676 unsigned RegClassID,
1677 unsigned RegNo,
1678 uint64_t Addr,
1679 const void *Decoder) {
1680 // Register number must be even (see CASP instruction)
1681 if (RegNo & 0x1)
1682 return Fail;
1683
1684 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1685 Inst.addOperand(MCOperand::createReg(Register));
1686 return Success;
1687}
1688
1689static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1690 unsigned RegNo,
1691 uint64_t Addr,
1692 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1693 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1694 AArch64::WSeqPairsClassRegClassID,
1695 RegNo, Addr, Decoder);
1696}
1697
1698static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1699 unsigned RegNo,
1700 uint64_t Addr,
1701 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1702 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1703 AArch64::XSeqPairsClassRegClassID,
1704 RegNo, Addr, Decoder);
1705}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1706
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1707static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1708 uint32_t insn,
1709 uint64_t Addr,
1710 const void *Decoder) {
1711 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1712 unsigned imm = fieldFromInstruction(insn, 5, 13);
1713 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1714 return Fail;
1715
1716 // The same (tied) operand is added twice to the instruction.
1717 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1718 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1719 Inst.addOperand(MCOperand::createImm(imm));
1720 return Success;
1721}
1722
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1723template<int Bits>
1724static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1725 uint64_t Address, const void *Decoder) {
1726 if (Imm & ~((1LL << Bits) - 1))
1727 return Fail;
1728
1729 // Imm is a signed immediate, so sign extend it.
1730 if (Imm & (1 << (Bits - 1)))
1731 Imm |= ~((1LL << Bits) - 1);
1732
1733 Inst.addOperand(MCOperand::createImm(Imm));
1734 return Success;
1735}
1736