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Evan Cheng10043e22007-01-19 07:51:42 +00001//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Cheng10043e22007-01-19 07:51:42 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
Craig Topper188ed9d2012-03-17 07:33:42 +000015#include "ARMISelLowering.h"
Eric Christopher1c069172010-09-10 22:42:06 +000016#include "ARMCallingConv.h"
Evan Cheng10043e22007-01-19 07:51:42 +000017#include "ARMConstantPoolValue.h"
Evan Cheng10043e22007-01-19 07:51:42 +000018#include "ARMMachineFunctionInfo.h"
Anton Korobeynikov9a232f42009-08-21 12:41:24 +000019#include "ARMPerfectShuffle.h"
Evan Cheng10043e22007-01-19 07:51:42 +000020#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
Chris Lattner4e7dfaf2009-08-02 00:34:36 +000022#include "ARMTargetObjectFile.h"
Evan Chenga20cde32011-07-20 23:34:39 +000023#include "MCTargetDesc/ARMAddressingModes.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000024#include "llvm/ADT/Statistic.h"
25#include "llvm/ADT/StringExtras.h"
Bob Wilsona4c22902009-04-17 19:07:39 +000026#include "llvm/CodeGen/CallingConvLower.h"
Evan Cheng078b0b02011-01-08 01:24:27 +000027#include "llvm/CodeGen/IntrinsicLowering.h"
Evan Cheng10043e22007-01-19 07:51:42 +000028#include "llvm/CodeGen/MachineBasicBlock.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
Bill Wendling202803e2011-10-05 00:02:33 +000032#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +000033#include "llvm/CodeGen/MachineRegisterInfo.h"
Evan Cheng10043e22007-01-19 07:51:42 +000034#include "llvm/CodeGen/SelectionDAG.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000035#include "llvm/IR/CallingConv.h"
36#include "llvm/IR/Constants.h"
37#include "llvm/IR/Function.h"
38#include "llvm/IR/GlobalValue.h"
Tim Northover037f26f22014-04-17 18:22:47 +000039#include "llvm/IR/IRBuilder.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000040#include "llvm/IR/Instruction.h"
41#include "llvm/IR/Instructions.h"
42#include "llvm/IR/Intrinsics.h"
43#include "llvm/IR/Type.h"
Bill Wendling46ffefc2010-03-09 02:46:12 +000044#include "llvm/MC/MCSectionMachO.h"
Jim Grosbach32bb3622010-04-14 22:28:31 +000045#include "llvm/Support/CommandLine.h"
Oliver Stannardc24f2172014-05-09 14:01:47 +000046#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +000047#include "llvm/Support/ErrorHandling.h"
Evan Cheng2150b922007-03-12 23:30:29 +000048#include "llvm/Support/MathExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000049#include "llvm/Target/TargetOptions.h"
David Peixottoc32e24a2013-10-17 19:49:22 +000050#include <utility>
Evan Cheng10043e22007-01-19 07:51:42 +000051using namespace llvm;
52
Chandler Carruth84e68b22014-04-22 02:41:26 +000053#define DEBUG_TYPE "arm-isel"
54
Dale Johannesend679ff72010-06-03 21:09:53 +000055STATISTIC(NumTailCalls, "Number of tail calls");
Evan Cheng68aec142011-01-19 02:16:49 +000056STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
Manman Ren9f911162012-06-01 02:44:42 +000057STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
Dale Johannesend679ff72010-06-03 21:09:53 +000058
Eric Christopher347f4c32010-12-15 23:47:29 +000059cl::opt<bool>
Jim Grosbach32bb3622010-04-14 22:28:31 +000060EnableARMLongCalls("arm-long-calls", cl::Hidden,
Evan Cheng25f93642010-07-08 02:08:50 +000061 cl::desc("Generate calls via indirect call instructions"),
Jim Grosbach32bb3622010-04-14 22:28:31 +000062 cl::init(false));
63
Evan Chengf128bdc2010-06-16 07:35:02 +000064static cl::opt<bool>
65ARMInterworking("arm-interworking", cl::Hidden,
66 cl::desc("Enable / disable ARM interworking (for debugging only)"),
67 cl::init(true));
68
Benjamin Kramer7ba71be2011-11-26 23:01:57 +000069namespace {
Cameron Zwarich89019782011-06-10 20:59:24 +000070 class ARMCCState : public CCState {
71 public:
72 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
Craig Topperb94011f2013-07-14 04:42:23 +000073 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
Cameron Zwarich89019782011-06-10 20:59:24 +000074 LLVMContext &C, ParmContext PC)
75 : CCState(CC, isVarArg, MF, TM, locs, C) {
76 assert(((PC == Call) || (PC == Prologue)) &&
77 "ARMCCState users must specify whether their context is call"
78 "or prologue generation.");
79 CallOrPrologue = PC;
80 }
81 };
82}
83
Stuart Hastings45fe3c32011-04-20 16:47:52 +000084// The APCS parameter registers.
Craig Topper840beec2014-04-04 05:16:06 +000085static const MCPhysReg GPRArgRegs[] = {
Stuart Hastings45fe3c32011-04-20 16:47:52 +000086 ARM::R0, ARM::R1, ARM::R2, ARM::R3
87};
88
Craig Topper4fa625f2012-08-12 03:16:37 +000089void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
90 MVT PromotedBitwiseVT) {
Bob Wilson2e076c42009-06-22 23:27:02 +000091 if (VT != PromotedLdStVT) {
Craig Topper4fa625f2012-08-12 03:16:37 +000092 setOperationAction(ISD::LOAD, VT, Promote);
93 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
Bob Wilson2e076c42009-06-22 23:27:02 +000094
Craig Topper4fa625f2012-08-12 03:16:37 +000095 setOperationAction(ISD::STORE, VT, Promote);
96 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
Bob Wilson2e076c42009-06-22 23:27:02 +000097 }
98
Craig Topper4fa625f2012-08-12 03:16:37 +000099 MVT ElemTy = VT.getVectorElementType();
Owen Anderson9f944592009-08-11 20:47:22 +0000100 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
Craig Topper4fa625f2012-08-12 03:16:37 +0000101 setOperationAction(ISD::SETCC, VT, Custom);
102 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
103 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
Eli Friedman2d4055b2011-11-09 23:36:02 +0000104 if (ElemTy == MVT::i32) {
Craig Topper4fa625f2012-08-12 03:16:37 +0000105 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
106 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
107 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
108 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
Eli Friedman2d4055b2011-11-09 23:36:02 +0000109 } else {
Craig Topper4fa625f2012-08-12 03:16:37 +0000110 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
111 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
112 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
113 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
Bob Wilson5d8cfb22009-09-16 20:20:44 +0000114 }
Craig Topper4fa625f2012-08-12 03:16:37 +0000115 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
116 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
117 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
119 setOperationAction(ISD::SELECT, VT, Expand);
120 setOperationAction(ISD::SELECT_CC, VT, Expand);
Jim Grosbach30af4422012-10-12 22:59:21 +0000121 setOperationAction(ISD::VSELECT, VT, Expand);
Craig Topper4fa625f2012-08-12 03:16:37 +0000122 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
Bob Wilson2e076c42009-06-22 23:27:02 +0000123 if (VT.isInteger()) {
Craig Topper4fa625f2012-08-12 03:16:37 +0000124 setOperationAction(ISD::SHL, VT, Custom);
125 setOperationAction(ISD::SRA, VT, Custom);
126 setOperationAction(ISD::SRL, VT, Custom);
Bob Wilson2e076c42009-06-22 23:27:02 +0000127 }
128
129 // Promote all bit-wise operations.
130 if (VT.isInteger() && VT != PromotedBitwiseVT) {
Craig Topper4fa625f2012-08-12 03:16:37 +0000131 setOperationAction(ISD::AND, VT, Promote);
132 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
133 setOperationAction(ISD::OR, VT, Promote);
134 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
135 setOperationAction(ISD::XOR, VT, Promote);
136 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
Bob Wilson2e076c42009-06-22 23:27:02 +0000137 }
Bob Wilson4ed397c2009-09-16 00:17:28 +0000138
139 // Neon does not support vector divide/remainder operations.
Craig Topper4fa625f2012-08-12 03:16:37 +0000140 setOperationAction(ISD::SDIV, VT, Expand);
141 setOperationAction(ISD::UDIV, VT, Expand);
142 setOperationAction(ISD::FDIV, VT, Expand);
143 setOperationAction(ISD::SREM, VT, Expand);
144 setOperationAction(ISD::UREM, VT, Expand);
145 setOperationAction(ISD::FREM, VT, Expand);
Bob Wilson2e076c42009-06-22 23:27:02 +0000146}
147
Craig Topper4fa625f2012-08-12 03:16:37 +0000148void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
Craig Topperc7242e02012-04-20 07:30:17 +0000149 addRegisterClass(VT, &ARM::DPRRegClass);
Owen Anderson9f944592009-08-11 20:47:22 +0000150 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
Bob Wilson2e076c42009-06-22 23:27:02 +0000151}
152
Craig Topper4fa625f2012-08-12 03:16:37 +0000153void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
Jakob Stoklund Olesen20912062014-01-14 06:18:34 +0000154 addRegisterClass(VT, &ARM::DPairRegClass);
Owen Anderson9f944592009-08-11 20:47:22 +0000155 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
Bob Wilson2e076c42009-06-22 23:27:02 +0000156}
157
Eric Christopher89958332014-05-31 00:07:32 +0000158static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
159 if (TT.isOSBinFormatMachO())
Bill Wendlingbbcaa402010-03-15 21:09:38 +0000160 return new TargetLoweringObjectFileMachO();
Eric Christopher89958332014-05-31 00:07:32 +0000161 if (TT.isOSWindows())
Saleem Abdulrasool46fed302014-05-17 04:28:08 +0000162 return new TargetLoweringObjectFileCOFF();
Chris Lattner4e7dfaf2009-08-02 00:34:36 +0000163 return new ARMElfTargetObjectFile();
Chris Lattner5e693ed2009-07-28 03:13:23 +0000164}
165
Evan Cheng10043e22007-01-19 07:51:42 +0000166ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
Eric Christopher89958332014-05-31 00:07:32 +0000167 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
Evan Cheng10043e22007-01-19 07:51:42 +0000168 Subtarget = &TM.getSubtarget<ARMSubtarget>();
Evan Chengdf907f42010-07-23 22:39:59 +0000169 RegInfo = TM.getRegisterInfo();
Evan Chengbf407072010-09-10 01:29:16 +0000170 Itins = TM.getInstrItineraryData();
Evan Cheng10043e22007-01-19 07:51:42 +0000171
Duncan Sandsf2641e12011-09-06 19:07:46 +0000172 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173
Tim Northoverd6a729b2014-01-06 14:28:05 +0000174 if (Subtarget->isTargetMachO()) {
Evan Chengc9f22fd12007-04-27 08:15:43 +0000175 // Uses VFP for Thumb libfuncs if available.
Jim Grosbach1d1d6d42013-10-24 23:07:11 +0000176 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
Tim Northover978d25f2014-04-22 10:10:09 +0000177 Subtarget->hasARMOps() && !TM.Options.UseSoftFloat) {
Evan Chengc9f22fd12007-04-27 08:15:43 +0000178 // Single-precision floating-point arithmetic.
179 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
180 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
181 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
182 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
Evan Cheng10043e22007-01-19 07:51:42 +0000183
Evan Chengc9f22fd12007-04-27 08:15:43 +0000184 // Double-precision floating-point arithmetic.
185 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
186 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
187 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
188 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
Evan Cheng143576d2007-01-31 09:30:58 +0000189
Evan Chengc9f22fd12007-04-27 08:15:43 +0000190 // Single-precision comparisons.
191 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
192 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
193 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
194 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
195 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
196 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
197 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
198 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
Evan Cheng10043e22007-01-19 07:51:42 +0000199
Evan Chengc9f22fd12007-04-27 08:15:43 +0000200 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
Evan Cheng143576d2007-01-31 09:30:58 +0000208
Evan Chengc9f22fd12007-04-27 08:15:43 +0000209 // Double-precision comparisons.
210 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
211 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
212 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
213 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
214 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
215 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
216 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
217 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
Evan Cheng10043e22007-01-19 07:51:42 +0000218
Evan Chengc9f22fd12007-04-27 08:15:43 +0000219 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
222 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
223 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
224 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
225 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
Evan Cheng10043e22007-01-19 07:51:42 +0000227
Evan Chengc9f22fd12007-04-27 08:15:43 +0000228 // Floating-point to integer conversions.
229 // i64 conversions are done via library routines even when generating VFP
230 // instructions, so use the same ones.
231 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
232 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
233 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
234 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
Evan Cheng10043e22007-01-19 07:51:42 +0000235
Evan Chengc9f22fd12007-04-27 08:15:43 +0000236 // Conversions between floating types.
237 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
238 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
239
240 // Integer to floating-point conversions.
241 // i64 conversions are done via library routines even when generating VFP
242 // instructions, so use the same ones.
Bob Wilsondc40d5a2009-03-20 23:16:43 +0000243 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
244 // e.g., __floatunsidf vs. __floatunssidfvfp.
Evan Chengc9f22fd12007-04-27 08:15:43 +0000245 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
246 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
247 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
248 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
249 }
Evan Cheng10043e22007-01-19 07:51:42 +0000250 }
251
Bob Wilsonccbc17b2009-05-22 17:38:41 +0000252 // These libcalls are not available in 32-bit.
Craig Topper062a2ba2014-04-25 05:30:21 +0000253 setLibcallName(RTLIB::SHL_I128, nullptr);
254 setLibcallName(RTLIB::SRL_I128, nullptr);
255 setLibcallName(RTLIB::SRA_I128, nullptr);
Bob Wilsonccbc17b2009-05-22 17:38:41 +0000256
Saleem Abdulrasoolcd130822014-04-02 20:32:05 +0000257 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
258 !Subtarget->isTargetWindows()) {
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000259 static const struct {
260 const RTLIB::Libcall Op;
261 const char * const Name;
262 const CallingConv::ID CC;
263 const ISD::CondCode Cond;
264 } LibraryCalls[] = {
265 // Double-precision floating-point arithmetic helper functions
266 // RTABI chapter 4.1.2, Table 2
267 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
268 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
269 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
270 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Anton Korobeynikov81bdc932010-09-28 21:39:26 +0000271
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000272 // Double-precision floating-point comparison helper functions
273 // RTABI chapter 4.1.2, Table 3
274 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
275 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
276 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
277 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
278 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
279 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
280 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
281 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
Anton Korobeynikov81bdc932010-09-28 21:39:26 +0000282
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000283 // Single-precision floating-point arithmetic helper functions
284 // RTABI chapter 4.1.2, Table 4
285 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
286 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
287 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
288 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Anton Korobeynikov81bdc932010-09-28 21:39:26 +0000289
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000290 // Single-precision floating-point comparison helper functions
291 // RTABI chapter 4.1.2, Table 5
292 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
293 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
294 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
295 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
296 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
297 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
298 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
299 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
Anton Korobeynikov81bdc932010-09-28 21:39:26 +0000300
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000301 // Floating-point to integer conversions.
302 // RTABI chapter 4.1.2, Table 6
303 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
304 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
306 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
307 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
309 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
310 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Anton Korobeynikov81bdc932010-09-28 21:39:26 +0000311
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000312 // Conversions between floating types.
313 // RTABI chapter 4.1.2, Table 7
314 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Tim Northover4e13a612014-07-29 09:56:45 +0000315 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000316 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Anton Korobeynikov81bdc932010-09-28 21:39:26 +0000317
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000318 // Integer to floating-point conversions.
319 // RTABI chapter 4.1.2, Table 8
320 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
321 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
323 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
324 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
326 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
327 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Anton Korobeynikov81bdc932010-09-28 21:39:26 +0000328
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000329 // Long long helper functions
330 // RTABI chapter 4.2, Table 9
331 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Anton Korobeynikov81bdc932010-09-28 21:39:26 +0000335
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000336 // Integer division functions
337 // RTABI chapter 4.3.1
338 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
342 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
343 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
345 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
Renato Golin4cd51872011-05-22 21:41:23 +0000346
Saleem Abdulrasool8bfb1922014-05-18 16:39:11 +0000347 // Memory operations
348 // RTABI chapter 4.3.4
349 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
351 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
352 };
353
354 for (const auto &LC : LibraryCalls) {
355 setLibcallName(LC.Op, LC.Name);
356 setLibcallCallingConv(LC.Op, LC.CC);
357 if (LC.Cond != ISD::SETCC_INVALID)
358 setCmpLibcallCC(LC.Op, LC.Cond);
359 }
Anton Korobeynikova6b3ce22009-08-14 20:10:52 +0000360 }
361
Saleem Abdulrasool056fc3d2014-05-16 05:41:33 +0000362 if (Subtarget->isTargetWindows()) {
363 static const struct {
364 const RTLIB::Libcall Op;
365 const char * const Name;
366 const CallingConv::ID CC;
367 } LibraryCalls[] = {
368 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
369 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
370 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
371 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
372 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
373 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
374 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
375 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
376 };
377
378 for (const auto &LC : LibraryCalls) {
379 setLibcallName(LC.Op, LC.Name);
380 setLibcallCallingConv(LC.Op, LC.CC);
381 }
382 }
383
Bob Wilsonbc158992011-10-07 16:59:21 +0000384 // Use divmod compiler-rt calls for iOS 5.0 and later.
Cameron Esfahani943908b2013-08-29 20:23:14 +0000385 if (Subtarget->getTargetTriple().isiOS() &&
Bob Wilsonbc158992011-10-07 16:59:21 +0000386 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
387 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
388 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
389 }
390
David Goodwin22c2fba2009-07-08 23:10:31 +0000391 if (Subtarget->isThumb1Only())
Craig Topperc7242e02012-04-20 07:30:17 +0000392 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
Jim Grosbachfde21102009-04-07 20:34:09 +0000393 else
Craig Topperc7242e02012-04-20 07:30:17 +0000394 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000395 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
396 !Subtarget->isThumb1Only()) {
Craig Topperc7242e02012-04-20 07:30:17 +0000397 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
Jim Grosbach4d5dc3e2010-08-11 15:44:15 +0000398 if (!Subtarget->isFPOnlySP())
Craig Topperc7242e02012-04-20 07:30:17 +0000399 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
Evan Cheng10043e22007-01-19 07:51:42 +0000400 }
Bob Wilson2e076c42009-06-22 23:27:02 +0000401
Eli Friedman6f84fed2011-11-08 01:43:53 +0000402 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
403 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
404 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
405 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
406 setTruncStoreAction((MVT::SimpleValueType)VT,
407 (MVT::SimpleValueType)InnerVT, Expand);
408 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
409 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
410 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
Benjamin Kramer4dae5982014-04-26 12:06:28 +0000411
412 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
413 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
414 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
415 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
Benjamin Kramerf3ad2352014-05-19 13:12:38 +0000416
417 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
Eli Friedman6f84fed2011-11-08 01:43:53 +0000418 }
419
Lang Hamesc35ee8b2012-03-15 18:49:02 +0000420 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
Tim Northoverf79c3a52013-08-20 08:57:11 +0000421 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
Lang Hamesc35ee8b2012-03-15 18:49:02 +0000422
Bob Wilson2e076c42009-06-22 23:27:02 +0000423 if (Subtarget->hasNEON()) {
Owen Anderson9f944592009-08-11 20:47:22 +0000424 addDRTypeForNEON(MVT::v2f32);
425 addDRTypeForNEON(MVT::v8i8);
426 addDRTypeForNEON(MVT::v4i16);
427 addDRTypeForNEON(MVT::v2i32);
428 addDRTypeForNEON(MVT::v1i64);
Bob Wilson2e076c42009-06-22 23:27:02 +0000429
Owen Anderson9f944592009-08-11 20:47:22 +0000430 addQRTypeForNEON(MVT::v4f32);
431 addQRTypeForNEON(MVT::v2f64);
432 addQRTypeForNEON(MVT::v16i8);
433 addQRTypeForNEON(MVT::v8i16);
434 addQRTypeForNEON(MVT::v4i32);
435 addQRTypeForNEON(MVT::v2i64);
Bob Wilson2e076c42009-06-22 23:27:02 +0000436
Bob Wilson194a2512009-09-15 23:55:57 +0000437 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
438 // neither Neon nor VFP support any arithmetic operations on it.
Stepan Dyatkovskiy46837402011-12-11 14:35:48 +0000439 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
440 // supported for v4f32.
Bob Wilson194a2512009-09-15 23:55:57 +0000441 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
442 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
443 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
Stepan Dyatkovskiy46837402011-12-11 14:35:48 +0000444 // FIXME: Code duplication: FDIV and FREM are expanded always, see
445 // ARMTargetLowering::addTypeForNEON method for details.
Bob Wilson194a2512009-09-15 23:55:57 +0000446 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
447 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
Stepan Dyatkovskiy46837402011-12-11 14:35:48 +0000448 // FIXME: Create unittest.
449 // In another words, find a way when "copysign" appears in DAG with vector
450 // operands.
Bob Wilson194a2512009-09-15 23:55:57 +0000451 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
Stepan Dyatkovskiy46837402011-12-11 14:35:48 +0000452 // FIXME: Code duplication: SETCC has custom operation action, see
453 // ARMTargetLowering::addTypeForNEON method for details.
Duncan Sandsf2641e12011-09-06 19:07:46 +0000454 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
Stepan Dyatkovskiy46837402011-12-11 14:35:48 +0000455 // FIXME: Create unittest for FNEG and for FABS.
Bob Wilson194a2512009-09-15 23:55:57 +0000456 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
457 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
458 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
459 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
460 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
461 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
462 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
463 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
464 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
465 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
466 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
467 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
Stepan Dyatkovskiy46837402011-12-11 14:35:48 +0000468 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
Bob Wilson194a2512009-09-15 23:55:57 +0000469 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
470 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
471 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
472 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
473 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
Arnold Schwaighofer99cba962013-03-02 19:38:33 +0000474 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
Lang Hames591cdaf2012-03-29 21:56:11 +0000475
Stepan Dyatkovskiy46837402011-12-11 14:35:48 +0000476 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
477 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
478 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
479 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
480 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
481 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
482 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
483 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
484 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
485 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
Craig Topper61d04572012-11-15 06:51:10 +0000486 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
487 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
488 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
489 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
Craig Topper3e41a5b2012-09-08 04:58:43 +0000490 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
Bob Wilson194a2512009-09-15 23:55:57 +0000491
Arnold Schwaighofer99cba962013-03-02 19:38:33 +0000492 // Mark v2f32 intrinsics.
493 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
494 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
495 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
496 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
497 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
498 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
499 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
500 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
501 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
502 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
503 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
504 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
505 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
506 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
507 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
508
Bob Wilson6cc46572009-09-16 00:32:15 +0000509 // Neon does not support some operations on v1i64 and v2i64 types.
510 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
Bob Wilson38ab35a2010-09-01 23:50:19 +0000511 // Custom handling for some quad-vector types to detect VMULL.
512 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
513 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
514 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
Nate Begemanfa62d502011-02-11 20:53:29 +0000515 // Custom handling for some vector types to avoid expensive expansions
516 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
517 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
518 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
519 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
Duncan Sandsf2641e12011-09-06 19:07:46 +0000520 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
521 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
Cameron Zwarich143f9ae2011-03-29 21:41:55 +0000522 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
James Molloy547d4c02012-02-20 09:24:05 +0000523 // a destination type that is wider than the source, and nor does
524 // it have a FP_TO_[SU]INT instruction with a narrower destination than
525 // source.
Cameron Zwarich143f9ae2011-03-29 21:41:55 +0000526 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
527 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
James Molloy547d4c02012-02-20 09:24:05 +0000528 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
529 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
Bob Wilson6cc46572009-09-16 00:32:15 +0000530
Eli Friedmane6385e62012-11-15 22:44:27 +0000531 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
Eli Friedman30834942012-11-17 01:52:46 +0000532 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
Eli Friedmane6385e62012-11-15 22:44:27 +0000533
Evan Chengb4eae132012-12-04 22:41:50 +0000534 // NEON does not have single instruction CTPOP for vectors with element
535 // types wider than 8-bits. However, custom lowering can leverage the
536 // v8i8/v16i8 vcnt instruction.
537 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
538 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
539 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
540 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
541
Jim Grosbach5f215872013-02-27 21:31:12 +0000542 // NEON only has FMA instructions as of VFP4.
543 if (!Subtarget->hasVFP4()) {
544 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
545 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
546 }
547
Bob Wilson06fce872011-02-07 17:43:21 +0000548 setTargetDAGCombine(ISD::INTRINSIC_VOID);
549 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
Bob Wilson2e076c42009-06-22 23:27:02 +0000550 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
551 setTargetDAGCombine(ISD::SHL);
552 setTargetDAGCombine(ISD::SRL);
553 setTargetDAGCombine(ISD::SRA);
554 setTargetDAGCombine(ISD::SIGN_EXTEND);
555 setTargetDAGCombine(ISD::ZERO_EXTEND);
556 setTargetDAGCombine(ISD::ANY_EXTEND);
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000557 setTargetDAGCombine(ISD::SELECT_CC);
Bob Wilsoncb6db982010-09-17 22:59:05 +0000558 setTargetDAGCombine(ISD::BUILD_VECTOR);
Bob Wilsonc7334a12010-10-27 20:38:28 +0000559 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
Bob Wilson1a20c2a2010-12-21 06:43:19 +0000560 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
561 setTargetDAGCombine(ISD::STORE);
Chad Rosierfa8d8932011-06-24 19:23:04 +0000562 setTargetDAGCombine(ISD::FP_TO_SINT);
563 setTargetDAGCombine(ISD::FP_TO_UINT);
564 setTargetDAGCombine(ISD::FDIV);
Nadav Rotem097106b2011-10-15 20:03:12 +0000565
James Molloy547d4c02012-02-20 09:24:05 +0000566 // It is legal to extload from v4i8 to v4i16 or v4i32.
567 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
568 MVT::v4i16, MVT::v2i16,
569 MVT::v2i32};
570 for (unsigned i = 0; i < 6; ++i) {
571 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
572 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
573 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
574 }
Bob Wilson2e076c42009-06-22 23:27:02 +0000575 }
576
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000577 // ARM and Thumb2 support UMLAL/SMLAL.
578 if (!Subtarget->isThumb1Only())
579 setTargetDAGCombine(ISD::ADDC);
580
581
Evan Cheng6addd652007-05-18 00:19:34 +0000582 computeRegisterProperties();
Evan Cheng10043e22007-01-19 07:51:42 +0000583
Tim Northover4e80b582014-07-18 13:01:19 +0000584 // ARM does not have floating-point extending loads.
Owen Anderson9f944592009-08-11 20:47:22 +0000585 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
Tim Northover4e80b582014-07-18 13:01:19 +0000586 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
587
588 // ... or truncating stores
589 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
590 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
591 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
Evan Cheng10043e22007-01-19 07:51:42 +0000592
Duncan Sands95d46ef2008-01-23 20:39:46 +0000593 // ARM does not have i1 sign extending load.
Owen Anderson9f944592009-08-11 20:47:22 +0000594 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Duncan Sands95d46ef2008-01-23 20:39:46 +0000595
Evan Cheng10043e22007-01-19 07:51:42 +0000596 // ARM supports all 4 flavors of integer indexed load / store.
Evan Cheng84c6cda2009-07-02 07:28:31 +0000597 if (!Subtarget->isThumb1Only()) {
598 for (unsigned im = (unsigned)ISD::PRE_INC;
599 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
Owen Anderson9f944592009-08-11 20:47:22 +0000600 setIndexedLoadAction(im, MVT::i1, Legal);
601 setIndexedLoadAction(im, MVT::i8, Legal);
602 setIndexedLoadAction(im, MVT::i16, Legal);
603 setIndexedLoadAction(im, MVT::i32, Legal);
604 setIndexedStoreAction(im, MVT::i1, Legal);
605 setIndexedStoreAction(im, MVT::i8, Legal);
606 setIndexedStoreAction(im, MVT::i16, Legal);
607 setIndexedStoreAction(im, MVT::i32, Legal);
Evan Cheng84c6cda2009-07-02 07:28:31 +0000608 }
Evan Cheng10043e22007-01-19 07:51:42 +0000609 }
610
Louis Gerbarg3342bf12014-05-09 17:02:49 +0000611 setOperationAction(ISD::SADDO, MVT::i32, Custom);
612 setOperationAction(ISD::UADDO, MVT::i32, Custom);
613 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
614 setOperationAction(ISD::USUBO, MVT::i32, Custom);
615
Evan Cheng10043e22007-01-19 07:51:42 +0000616 // i64 operation support.
Eric Christopherc721b0db2011-04-19 18:49:19 +0000617 setOperationAction(ISD::MUL, MVT::i64, Expand);
618 setOperationAction(ISD::MULHU, MVT::i32, Expand);
Evan Chengb24e51e2009-07-07 01:17:28 +0000619 if (Subtarget->isThumb1Only()) {
Owen Anderson9f944592009-08-11 20:47:22 +0000620 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
621 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
Evan Cheng10043e22007-01-19 07:51:42 +0000622 }
Jim Grosbachcf1464d2011-07-01 21:12:19 +0000623 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
624 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
Eric Christopherc721b0db2011-04-19 18:49:19 +0000625 setOperationAction(ISD::MULHS, MVT::i32, Expand);
626
Jim Grosbach5d994042009-10-31 19:38:01 +0000627 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
Jim Grosbach624fcb22009-10-31 21:00:56 +0000628 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
Jim Grosbach8fe6fd72009-10-31 21:42:19 +0000629 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
Owen Anderson9f944592009-08-11 20:47:22 +0000630 setOperationAction(ISD::SRL, MVT::i64, Custom);
631 setOperationAction(ISD::SRA, MVT::i64, Custom);
Evan Cheng10043e22007-01-19 07:51:42 +0000632
Evan Chenge8916542011-08-30 01:34:54 +0000633 if (!Subtarget->isThumb1Only()) {
634 // FIXME: We should do this for Thumb1 as well.
635 setOperationAction(ISD::ADDC, MVT::i32, Custom);
636 setOperationAction(ISD::ADDE, MVT::i32, Custom);
637 setOperationAction(ISD::SUBC, MVT::i32, Custom);
638 setOperationAction(ISD::SUBE, MVT::i32, Custom);
639 }
640
Evan Cheng10043e22007-01-19 07:51:42 +0000641 // ARM does not have ROTL.
Owen Anderson9f944592009-08-11 20:47:22 +0000642 setOperationAction(ISD::ROTL, MVT::i32, Expand);
Jim Grosbach8546ec92010-01-18 19:58:49 +0000643 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
Owen Anderson9f944592009-08-11 20:47:22 +0000644 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
David Goodwinaa294c52009-06-26 20:47:43 +0000645 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
Owen Anderson9f944592009-08-11 20:47:22 +0000646 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Evan Cheng10043e22007-01-19 07:51:42 +0000647
Chandler Carruth637cc6a2011-12-13 01:56:10 +0000648 // These just redirect to CTTZ and CTLZ on ARM.
649 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
650 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
651
Tim Northoverbc933082013-05-23 19:11:20 +0000652 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
653
Lauro Ramos Venancio25d40522007-03-16 22:54:16 +0000654 // Only ARMv6 has BSWAP.
655 if (!Subtarget->hasV6Ops())
Owen Anderson9f944592009-08-11 20:47:22 +0000656 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Lauro Ramos Venancio25d40522007-03-16 22:54:16 +0000657
Bob Wilsone8a549c2012-09-29 21:43:49 +0000658 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
659 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
660 // These are expanded into libcalls if the cpu doesn't have HW divider.
Jim Grosbach92d999002010-05-05 20:44:35 +0000661 setOperationAction(ISD::SDIV, MVT::i32, Expand);
662 setOperationAction(ISD::UDIV, MVT::i32, Expand);
663 }
Renato Golin87610692013-07-16 09:32:17 +0000664
665 // FIXME: Also set divmod for SREM on EABI
Owen Anderson9f944592009-08-11 20:47:22 +0000666 setOperationAction(ISD::SREM, MVT::i32, Expand);
667 setOperationAction(ISD::UREM, MVT::i32, Expand);
Renato Golin87610692013-07-16 09:32:17 +0000668 // Register based DivRem for AEABI (RTABI 4.2)
669 if (Subtarget->isTargetAEABI()) {
670 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
671 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
672 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
673 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
674 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
675 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
676 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
677 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
678
679 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
680 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
681 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
682 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
683 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
684 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
685 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
686 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
687
688 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
689 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
690 } else {
691 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
692 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
693 }
Bob Wilson7117a912009-03-20 22:42:55 +0000694
Owen Anderson9f944592009-08-11 20:47:22 +0000695 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
696 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
697 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
698 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
Bob Wilson1cf0b032009-10-30 05:45:42 +0000699 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Evan Cheng10043e22007-01-19 07:51:42 +0000700
Evan Cheng74d92c12011-04-08 21:37:21 +0000701 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Evan Cheng2fa5a7e2010-05-11 07:26:32 +0000702
Evan Cheng10043e22007-01-19 07:51:42 +0000703 // Use the default implementation.
Owen Anderson9f944592009-08-11 20:47:22 +0000704 setOperationAction(ISD::VASTART, MVT::Other, Custom);
705 setOperationAction(ISD::VAARG, MVT::Other, Expand);
706 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
707 setOperationAction(ISD::VAEND, MVT::Other, Expand);
708 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
709 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Bill Wendling05d6f2f2012-02-13 23:47:16 +0000710
Tim Northoverd6a729b2014-01-06 14:28:05 +0000711 if (!Subtarget->isTargetMachO()) {
712 // Non-MachO platforms may return values in these registers via the
Bill Wendling05d6f2f2012-02-13 23:47:16 +0000713 // personality function.
Bill Wendling05d6f2f2012-02-13 23:47:16 +0000714 setExceptionPointerRegister(ARM::R0);
715 setExceptionSelectorRegister(ARM::R1);
716 }
Anton Korobeynikovf3a62312011-01-24 22:38:45 +0000717
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000718 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
719 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
720 else
721 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
722
Evan Cheng6e809de2010-08-11 06:22:01 +0000723 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
724 // the default expansion.
Tim Northoverc7ea8042013-10-25 09:30:24 +0000725 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
Tim Northoverc882eb02014-04-03 11:44:58 +0000726 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
727 // to ldrex/strex loops already.
Tim Northoverc7ea8042013-10-25 09:30:24 +0000728 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
Tim Northoverc882eb02014-04-03 11:44:58 +0000729
Amara Emersonb4ad2f32013-09-26 12:22:36 +0000730 // On v8, we have particularly efficient implementations of atomic fences
731 // if they can be combined with nearby atomic loads and stores.
732 if (!Subtarget->hasV8Ops()) {
733 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
734 setInsertFencesForAtomic(true);
735 }
Jim Grosbach6860bb72010-06-18 22:35:32 +0000736 } else {
Tim Northoverc7ea8042013-10-25 09:30:24 +0000737 // If there's anything we can use as a barrier, go through custom lowering
738 // for ATOMIC_FENCE.
739 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
740 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
741
Jim Grosbach6860bb72010-06-18 22:35:32 +0000742 // Set them all for expansion, which will force libcalls.
Jim Grosbach6860bb72010-06-18 22:35:32 +0000743 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
Jim Grosbacha57c2882010-06-18 23:03:10 +0000744 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
Jim Grosbach6860bb72010-06-18 22:35:32 +0000745 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
Jim Grosbach6860bb72010-06-18 22:35:32 +0000746 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
Jim Grosbach6860bb72010-06-18 22:35:32 +0000747 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
Jim Grosbach6860bb72010-06-18 22:35:32 +0000748 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
Jim Grosbach6860bb72010-06-18 22:35:32 +0000749 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
Jim Grosbach6860bb72010-06-18 22:35:32 +0000750 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
Jim Grosbachd4b733e2011-04-26 19:44:18 +0000751 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
Jim Grosbachd4b733e2011-04-26 19:44:18 +0000752 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
Jim Grosbachd4b733e2011-04-26 19:44:18 +0000753 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
Jim Grosbachd4b733e2011-04-26 19:44:18 +0000754 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
Eli Friedmanba912e02011-09-15 22:18:49 +0000755 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
756 // Unordered/Monotonic case.
757 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
758 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
Jim Grosbach6860bb72010-06-18 22:35:32 +0000759 }
Evan Cheng10043e22007-01-19 07:51:42 +0000760
Evan Cheng21acf9f2010-11-04 05:19:35 +0000761 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
Evan Cheng6f360422010-11-03 05:14:24 +0000762
Eli Friedman8cfa7712010-06-26 04:36:50 +0000763 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
764 if (!Subtarget->hasV6Ops()) {
Owen Anderson9f944592009-08-11 20:47:22 +0000765 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
766 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
Evan Cheng10043e22007-01-19 07:51:42 +0000767 }
Owen Anderson9f944592009-08-11 20:47:22 +0000768 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Evan Cheng10043e22007-01-19 07:51:42 +0000769
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000770 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
771 !Subtarget->isThumb1Only()) {
Bob Wilson6a4491b2010-01-19 22:56:26 +0000772 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000773 // iff target supports vfp2.
Wesley Peck527da1b2010-11-23 03:31:01 +0000774 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
Nate Begemanb69b1822010-08-03 21:31:55 +0000775 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
776 }
Lauro Ramos Venanciof6a67bf2007-11-08 17:20:05 +0000777
778 // We want to custom lower some of our intrinsics.
Owen Anderson9f944592009-08-11 20:47:22 +0000779 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Jim Grosbach31984832010-07-07 00:07:57 +0000780 if (Subtarget->isTargetDarwin()) {
781 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
782 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
John McCall7d84ece2011-05-29 19:50:32 +0000783 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
Jim Grosbach31984832010-07-07 00:07:57 +0000784 }
Lauro Ramos Venanciof6a67bf2007-11-08 17:20:05 +0000785
Owen Anderson9f944592009-08-11 20:47:22 +0000786 setOperationAction(ISD::SETCC, MVT::i32, Expand);
787 setOperationAction(ISD::SETCC, MVT::f32, Expand);
788 setOperationAction(ISD::SETCC, MVT::f64, Expand);
Bill Wendling6a981312010-08-11 08:43:16 +0000789 setOperationAction(ISD::SELECT, MVT::i32, Custom);
790 setOperationAction(ISD::SELECT, MVT::f32, Custom);
791 setOperationAction(ISD::SELECT, MVT::f64, Custom);
Owen Anderson9f944592009-08-11 20:47:22 +0000792 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
793 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
794 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Evan Cheng10043e22007-01-19 07:51:42 +0000795
Owen Anderson9f944592009-08-11 20:47:22 +0000796 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
797 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
798 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
799 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
800 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
Evan Cheng10043e22007-01-19 07:51:42 +0000801
Dan Gohman482732a2007-10-11 23:21:31 +0000802 // We don't support sin/cos/fmod/copysign/pow
Owen Anderson9f944592009-08-11 20:47:22 +0000803 setOperationAction(ISD::FSIN, MVT::f64, Expand);
804 setOperationAction(ISD::FSIN, MVT::f32, Expand);
805 setOperationAction(ISD::FCOS, MVT::f32, Expand);
806 setOperationAction(ISD::FCOS, MVT::f64, Expand);
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000807 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
808 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
Owen Anderson9f944592009-08-11 20:47:22 +0000809 setOperationAction(ISD::FREM, MVT::f64, Expand);
810 setOperationAction(ISD::FREM, MVT::f32, Expand);
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000811 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
812 !Subtarget->isThumb1Only()) {
Owen Anderson9f944592009-08-11 20:47:22 +0000813 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
814 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
Evan Cheng86e476b2008-04-01 01:50:16 +0000815 }
Owen Anderson9f944592009-08-11 20:47:22 +0000816 setOperationAction(ISD::FPOW, MVT::f64, Expand);
817 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Bob Wilson7117a912009-03-20 22:42:55 +0000818
Evan Chengd0007f32012-04-10 21:40:28 +0000819 if (!Subtarget->hasVFP4()) {
820 setOperationAction(ISD::FMA, MVT::f64, Expand);
821 setOperationAction(ISD::FMA, MVT::f32, Expand);
822 }
Cameron Zwarichf03fa182011-07-08 21:39:21 +0000823
Anton Korobeynikovd7fece32010-03-14 18:42:31 +0000824 // Various VFP goodness
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000825 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
Bob Wilsone4191e72010-03-19 22:51:32 +0000826 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
827 if (Subtarget->hasVFP2()) {
828 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
829 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
830 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
831 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
832 }
Tim Northover53f3bcf2014-07-17 11:27:04 +0000833
834 // v8 adds f64 <-> f16 conversion. Before that it should be expanded.
835 if (!Subtarget->hasV8Ops()) {
836 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
837 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
838 }
839
840 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
Anton Korobeynikov64578d52010-03-18 22:35:37 +0000841 if (!Subtarget->hasFP16()) {
Tim Northoverfd7e4242014-07-17 10:51:23 +0000842 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
843 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
Anton Korobeynikovd7fece32010-03-14 18:42:31 +0000844 }
Evan Cheng86e476b2008-04-01 01:50:16 +0000845 }
Jim Grosbach1a597112014-04-03 23:43:18 +0000846
Bob Wilsone7dde0c2013-11-03 06:14:38 +0000847 // Combine sin / cos into one node or libcall if possible.
848 if (Subtarget->hasSinCos()) {
849 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
850 setLibcallName(RTLIB::SINCOS_F64, "sincos");
851 if (Subtarget->getTargetTriple().getOS() == Triple::IOS) {
852 // For iOS, we don't want to the normal expansion of a libcall to
853 // sincos. We want to issue a libcall to __sincos_stret.
854 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
855 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
856 }
857 }
Evan Cheng10043e22007-01-19 07:51:42 +0000858
Chris Lattnerf3f4ad92007-11-27 22:36:16 +0000859 // We have target-specific dag combine patterns for the following nodes:
Jim Grosbachd7cf55c2009-11-09 00:11:35 +0000860 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
Chris Lattner4147f082009-03-12 06:52:53 +0000861 setTargetDAGCombine(ISD::ADD);
862 setTargetDAGCombine(ISD::SUB);
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +0000863 setTargetDAGCombine(ISD::MUL);
Jakob Stoklund Olesene45e22b2012-09-07 17:34:15 +0000864 setTargetDAGCombine(ISD::AND);
865 setTargetDAGCombine(ISD::OR);
866 setTargetDAGCombine(ISD::XOR);
Jim Grosbach11013ed2010-07-16 23:05:05 +0000867
Evan Chengf258a152012-02-23 02:58:19 +0000868 if (Subtarget->hasV6Ops())
869 setTargetDAGCombine(ISD::SRL);
870
Evan Cheng10043e22007-01-19 07:51:42 +0000871 setStackPointerRegisterToSaveRestore(ARM::SP);
Evan Cheng4401f882010-05-20 23:26:43 +0000872
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000873 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
874 !Subtarget->hasVFP2())
Evan Cheng34c26042010-05-21 00:43:17 +0000875 setSchedulingPreference(Sched::RegPressure);
876 else
877 setSchedulingPreference(Sched::Hybrid);
Dale Johannesen58698d22007-05-17 21:31:21 +0000878
Evan Cheng3ae2b792011-01-06 06:52:41 +0000879 //// temporary - rewrite interface to use type
Jim Grosbach341ad3e2013-02-20 21:13:59 +0000880 MaxStoresPerMemset = 8;
881 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
882 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
883 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
884 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
885 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
Evan Chengb71233f2010-06-26 01:52:05 +0000886
Rafael Espindolaa76eccf2010-07-11 04:01:49 +0000887 // On ARM arguments smaller than 4 bytes are extended, so all arguments
888 // are at least 4 bytes aligned.
889 setMinStackArgumentAlignment(4);
890
Benjamin Kramere31f31e2012-05-05 12:49:14 +0000891 // Prefer likely predicted branches to selects on out-of-order cores.
Jim Grosbach341ad3e2013-02-20 21:13:59 +0000892 PredictableSelectIsExpensive = Subtarget->isLikeA9();
Benjamin Kramere31f31e2012-05-05 12:49:14 +0000893
Eli Friedman2518f832011-05-06 20:34:06 +0000894 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
Evan Cheng10043e22007-01-19 07:51:42 +0000895}
896
Andrew Trick43f25632011-01-19 02:35:27 +0000897// FIXME: It might make sense to define the representative register class as the
898// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
899// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
900// SPR's representative would be DPR_VFP2. This should work well if register
901// pressure tracking were modified such that a register use would increment the
902// pressure of the register class's representative and all of it's super
903// classes' representatives transitively. We have not implemented this because
904// of the difficulty prior to coalescing of modeling operand register classes
Chris Lattner0ab5e2c2011-04-15 05:18:47 +0000905// due to the common occurrence of cross class copies and subregister insertions
Andrew Trick43f25632011-01-19 02:35:27 +0000906// and extractions.
Evan Chenga77f3d32010-07-21 06:09:07 +0000907std::pair<const TargetRegisterClass*, uint8_t>
Patrik Hagglundf9eb1682012-12-19 11:30:36 +0000908ARMTargetLowering::findRepresentativeClass(MVT VT) const{
Craig Topper062a2ba2014-04-25 05:30:21 +0000909 const TargetRegisterClass *RRC = nullptr;
Evan Chenga77f3d32010-07-21 06:09:07 +0000910 uint8_t Cost = 1;
Patrik Hagglundf9eb1682012-12-19 11:30:36 +0000911 switch (VT.SimpleTy) {
Evan Cheng10f99a32010-07-19 22:15:08 +0000912 default:
Evan Chenga77f3d32010-07-21 06:09:07 +0000913 return TargetLowering::findRepresentativeClass(VT);
Evan Cheng28590382010-07-21 23:53:58 +0000914 // Use DPR as representative register class for all floating point
915 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
916 // the cost is 1 for both f32 and f64.
917 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
Evan Chenga77f3d32010-07-21 06:09:07 +0000918 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
Craig Topperc7242e02012-04-20 07:30:17 +0000919 RRC = &ARM::DPRRegClass;
Andrew Trick43f25632011-01-19 02:35:27 +0000920 // When NEON is used for SP, only half of the register file is available
921 // because operations that define both SP and DP results will be constrained
922 // to the VFP2 class (D0-D15). We currently model this constraint prior to
923 // coalescing by double-counting the SP regs. See the FIXME above.
924 if (Subtarget->useNEONForSinglePrecisionFP())
925 Cost = 2;
Evan Chenga77f3d32010-07-21 06:09:07 +0000926 break;
927 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
928 case MVT::v4f32: case MVT::v2f64:
Craig Topperc7242e02012-04-20 07:30:17 +0000929 RRC = &ARM::DPRRegClass;
Evan Cheng28590382010-07-21 23:53:58 +0000930 Cost = 2;
Evan Chenga77f3d32010-07-21 06:09:07 +0000931 break;
932 case MVT::v4i64:
Craig Topperc7242e02012-04-20 07:30:17 +0000933 RRC = &ARM::DPRRegClass;
Evan Cheng28590382010-07-21 23:53:58 +0000934 Cost = 4;
Evan Chenga77f3d32010-07-21 06:09:07 +0000935 break;
936 case MVT::v8i64:
Craig Topperc7242e02012-04-20 07:30:17 +0000937 RRC = &ARM::DPRRegClass;
Evan Cheng28590382010-07-21 23:53:58 +0000938 Cost = 8;
Evan Chenga77f3d32010-07-21 06:09:07 +0000939 break;
Evan Cheng10f99a32010-07-19 22:15:08 +0000940 }
Evan Chenga77f3d32010-07-21 06:09:07 +0000941 return std::make_pair(RRC, Cost);
Evan Cheng10f99a32010-07-19 22:15:08 +0000942}
943
Evan Cheng10043e22007-01-19 07:51:42 +0000944const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
945 switch (Opcode) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000946 default: return nullptr;
Evan Cheng10043e22007-01-19 07:51:42 +0000947 case ARMISD::Wrapper: return "ARMISD::Wrapper";
Evan Chengdfce83c2011-01-17 08:03:18 +0000948 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
Evan Cheng10043e22007-01-19 07:51:42 +0000949 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
950 case ARMISD::CALL: return "ARMISD::CALL";
Evan Chengc3c949b42007-06-19 21:05:09 +0000951 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
Evan Cheng10043e22007-01-19 07:51:42 +0000952 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
953 case ARMISD::tCALL: return "ARMISD::tCALL";
954 case ARMISD::BRCOND: return "ARMISD::BRCOND";
955 case ARMISD::BR_JT: return "ARMISD::BR_JT";
Evan Chengc6d70ae2009-07-29 02:18:14 +0000956 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
Evan Cheng10043e22007-01-19 07:51:42 +0000957 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
Tim Northoverd8407452013-10-01 14:33:28 +0000958 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
Evan Cheng10043e22007-01-19 07:51:42 +0000959 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
960 case ARMISD::CMP: return "ARMISD::CMP";
Bill Wendling4b796472012-06-11 08:07:26 +0000961 case ARMISD::CMN: return "ARMISD::CMN";
David Goodwindbf11ba2009-06-29 15:33:01 +0000962 case ARMISD::CMPZ: return "ARMISD::CMPZ";
Evan Cheng10043e22007-01-19 07:51:42 +0000963 case ARMISD::CMPFP: return "ARMISD::CMPFP";
964 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000965 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
Evan Cheng10043e22007-01-19 07:51:42 +0000966 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
Evan Chenge87681c2012-02-23 01:19:06 +0000967
Evan Cheng10043e22007-01-19 07:51:42 +0000968 case ARMISD::CMOV: return "ARMISD::CMOV";
Bob Wilson7117a912009-03-20 22:42:55 +0000969
Jim Grosbach8546ec92010-01-18 19:58:49 +0000970 case ARMISD::RBIT: return "ARMISD::RBIT";
971
Bob Wilsone4191e72010-03-19 22:51:32 +0000972 case ARMISD::FTOSI: return "ARMISD::FTOSI";
973 case ARMISD::FTOUI: return "ARMISD::FTOUI";
974 case ARMISD::SITOF: return "ARMISD::SITOF";
975 case ARMISD::UITOF: return "ARMISD::UITOF";
976
Evan Cheng10043e22007-01-19 07:51:42 +0000977 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
978 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
979 case ARMISD::RRX: return "ARMISD::RRX";
Bob Wilson7117a912009-03-20 22:42:55 +0000980
Evan Chenge8916542011-08-30 01:34:54 +0000981 case ARMISD::ADDC: return "ARMISD::ADDC";
982 case ARMISD::ADDE: return "ARMISD::ADDE";
983 case ARMISD::SUBC: return "ARMISD::SUBC";
984 case ARMISD::SUBE: return "ARMISD::SUBE";
985
Bob Wilson22806742010-09-22 22:09:21 +0000986 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
987 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +0000988
Evan Chengec6d7c92009-10-28 06:55:03 +0000989 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
990 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
991
Dale Johannesend679ff72010-06-03 21:09:53 +0000992 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
Jim Grosbach535d3b42010-09-08 03:54:02 +0000993
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +0000994 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
Bob Wilson2e076c42009-06-22 23:27:02 +0000995
Evan Chengb972e562009-08-07 00:34:42 +0000996 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
997
Bob Wilson7ed59712010-10-30 00:54:37 +0000998 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
Jim Grosbach53e88542009-12-10 00:11:09 +0000999
Evan Cheng8740ee32010-11-03 06:34:55 +00001000 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1001
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +00001002 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1003
Bob Wilson2e076c42009-06-22 23:27:02 +00001004 case ARMISD::VCEQ: return "ARMISD::VCEQ";
Bob Wilsonf268d032010-12-18 00:04:26 +00001005 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
Bob Wilson2e076c42009-06-22 23:27:02 +00001006 case ARMISD::VCGE: return "ARMISD::VCGE";
Bob Wilsonf268d032010-12-18 00:04:26 +00001007 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1008 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
Bob Wilson2e076c42009-06-22 23:27:02 +00001009 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1010 case ARMISD::VCGT: return "ARMISD::VCGT";
Bob Wilsonf268d032010-12-18 00:04:26 +00001011 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1012 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
Bob Wilson2e076c42009-06-22 23:27:02 +00001013 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1014 case ARMISD::VTST: return "ARMISD::VTST";
1015
1016 case ARMISD::VSHL: return "ARMISD::VSHL";
1017 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1018 case ARMISD::VSHRu: return "ARMISD::VSHRu";
Bob Wilson2e076c42009-06-22 23:27:02 +00001019 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1020 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1021 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1022 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1023 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1024 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1025 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1026 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1027 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1028 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1029 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1030 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1031 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1032 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
Bob Wilsona3f19012010-07-13 21:16:48 +00001033 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
Bob Wilsonbad47f62010-07-14 06:31:50 +00001034 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
Evan Cheng7ca4b6e2011-11-15 02:12:34 +00001035 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
Bob Wilsoneb54d512009-08-14 05:13:08 +00001036 case ARMISD::VDUP: return "ARMISD::VDUP";
Bob Wilsoncce31f62009-08-14 05:08:32 +00001037 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
Bob Wilson32cd8552009-08-19 17:03:43 +00001038 case ARMISD::VEXT: return "ARMISD::VEXT";
Bob Wilsonea3a4022009-08-12 22:31:50 +00001039 case ARMISD::VREV64: return "ARMISD::VREV64";
1040 case ARMISD::VREV32: return "ARMISD::VREV32";
1041 case ARMISD::VREV16: return "ARMISD::VREV16";
Anton Korobeynikov232b19c2009-08-21 12:41:42 +00001042 case ARMISD::VZIP: return "ARMISD::VZIP";
1043 case ARMISD::VUZP: return "ARMISD::VUZP";
1044 case ARMISD::VTRN: return "ARMISD::VTRN";
Bill Wendlinge1fd78f2011-03-14 23:02:38 +00001045 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1046 case ARMISD::VTBL2: return "ARMISD::VTBL2";
Bob Wilson38ab35a2010-09-01 23:50:19 +00001047 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1048 case ARMISD::VMULLu: return "ARMISD::VMULLu";
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +00001049 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1050 case ARMISD::SMLAL: return "ARMISD::SMLAL";
Bob Wilsond8a9a042010-06-04 00:04:02 +00001051 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
Bob Wilsonc6c13a32010-02-18 06:05:53 +00001052 case ARMISD::FMAX: return "ARMISD::FMAX";
1053 case ARMISD::FMIN: return "ARMISD::FMIN";
Joey Goulye3dd6842013-08-23 12:01:13 +00001054 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1055 case ARMISD::VMINNM: return "ARMISD::VMIN";
Jim Grosbach6e3b5fa2010-07-17 01:50:57 +00001056 case ARMISD::BFI: return "ARMISD::BFI";
Bob Wilson62a6f7e2010-11-28 06:51:11 +00001057 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1058 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
Cameron Zwarich53dd03d2011-03-30 23:01:21 +00001059 case ARMISD::VBSL: return "ARMISD::VBSL";
Bob Wilson2d790df2010-11-28 06:51:26 +00001060 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1061 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1062 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
Bob Wilson06fce872011-02-07 17:43:21 +00001063 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1064 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1065 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1066 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1067 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1068 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1069 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1070 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1071 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1072 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1073 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1074 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1075 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1076 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1077 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1078 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1079 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
Evan Cheng10043e22007-01-19 07:51:42 +00001080 }
1081}
1082
Matt Arsenault758659232013-05-18 00:21:46 +00001083EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
Duncan Sandsf2641e12011-09-06 19:07:46 +00001084 if (!VT.isVector()) return getPointerTy();
1085 return VT.changeVectorElementTypeToInteger();
1086}
1087
Evan Cheng4cad68e2010-05-15 02:18:07 +00001088/// getRegClassFor - Return the register class that should be used for the
1089/// specified value type.
Patrik Hagglund5e6c3612012-12-13 06:34:11 +00001090const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
Evan Cheng4cad68e2010-05-15 02:18:07 +00001091 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1092 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1093 // load / store 4 to 8 consecutive D registers.
Evan Cheng3d214cd2010-05-15 02:20:21 +00001094 if (Subtarget->hasNEON()) {
1095 if (VT == MVT::v4i64)
Craig Topperc7242e02012-04-20 07:30:17 +00001096 return &ARM::QQPRRegClass;
1097 if (VT == MVT::v8i64)
1098 return &ARM::QQQQPRRegClass;
Evan Cheng3d214cd2010-05-15 02:20:21 +00001099 }
Evan Cheng4cad68e2010-05-15 02:18:07 +00001100 return TargetLowering::getRegClassFor(VT);
1101}
1102
Eric Christopher84bdfd82010-07-21 22:26:11 +00001103// Create a fast isel object.
1104FastISel *
Bob Wilson3e6fa462012-08-03 04:06:28 +00001105ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1106 const TargetLibraryInfo *libInfo) const {
1107 return ARM::createFastISel(funcInfo, libInfo);
Eric Christopher84bdfd82010-07-21 22:26:11 +00001108}
1109
Anton Korobeynikov19edda02010-07-24 21:52:08 +00001110/// getMaximalGlobalOffset - Returns the maximal possible offset which can
1111/// be used for loads / stores from the global.
1112unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1113 return (Subtarget->isThumb1Only() ? 127 : 4095);
1114}
1115
Evan Cheng4401f882010-05-20 23:26:43 +00001116Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
Evan Chengbf914992010-05-28 23:25:23 +00001117 unsigned NumVals = N->getNumValues();
1118 if (!NumVals)
1119 return Sched::RegPressure;
1120
1121 for (unsigned i = 0; i != NumVals; ++i) {
Evan Cheng4401f882010-05-20 23:26:43 +00001122 EVT VT = N->getValueType(i);
Chris Lattner3e5fbd72010-12-21 02:38:05 +00001123 if (VT == MVT::Glue || VT == MVT::Other)
Evan Cheng0c4c5ca2010-10-29 18:07:31 +00001124 continue;
Evan Cheng4401f882010-05-20 23:26:43 +00001125 if (VT.isFloatingPoint() || VT.isVector())
Dan Gohman4ed1afa2011-10-24 17:55:11 +00001126 return Sched::ILP;
Evan Cheng4401f882010-05-20 23:26:43 +00001127 }
Evan Chengbf914992010-05-28 23:25:23 +00001128
1129 if (!N->isMachineOpcode())
1130 return Sched::RegPressure;
1131
1132 // Load are scheduled for latency even if there instruction itinerary
1133 // is not available.
1134 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Evan Cheng6cc775f2011-06-28 19:10:37 +00001135 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
Evan Cheng0c4c5ca2010-10-29 18:07:31 +00001136
Evan Cheng6cc775f2011-06-28 19:10:37 +00001137 if (MCID.getNumDefs() == 0)
Evan Cheng0c4c5ca2010-10-29 18:07:31 +00001138 return Sched::RegPressure;
1139 if (!Itins->isEmpty() &&
Evan Cheng6cc775f2011-06-28 19:10:37 +00001140 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
Dan Gohman4ed1afa2011-10-24 17:55:11 +00001141 return Sched::ILP;
Evan Chengbf914992010-05-28 23:25:23 +00001142
Evan Cheng4401f882010-05-20 23:26:43 +00001143 return Sched::RegPressure;
1144}
1145
Evan Cheng10043e22007-01-19 07:51:42 +00001146//===----------------------------------------------------------------------===//
1147// Lowering Code
1148//===----------------------------------------------------------------------===//
1149
Evan Cheng10043e22007-01-19 07:51:42 +00001150/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1151static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1152 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00001153 default: llvm_unreachable("Unknown condition code!");
Evan Cheng10043e22007-01-19 07:51:42 +00001154 case ISD::SETNE: return ARMCC::NE;
1155 case ISD::SETEQ: return ARMCC::EQ;
1156 case ISD::SETGT: return ARMCC::GT;
1157 case ISD::SETGE: return ARMCC::GE;
1158 case ISD::SETLT: return ARMCC::LT;
1159 case ISD::SETLE: return ARMCC::LE;
1160 case ISD::SETUGT: return ARMCC::HI;
1161 case ISD::SETUGE: return ARMCC::HS;
1162 case ISD::SETULT: return ARMCC::LO;
1163 case ISD::SETULE: return ARMCC::LS;
1164 }
1165}
1166
Bob Wilsona2e83332009-09-09 23:14:54 +00001167/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1168static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
Evan Cheng10043e22007-01-19 07:51:42 +00001169 ARMCC::CondCodes &CondCode2) {
Evan Cheng10043e22007-01-19 07:51:42 +00001170 CondCode2 = ARMCC::AL;
1171 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00001172 default: llvm_unreachable("Unknown FP condition!");
Evan Cheng10043e22007-01-19 07:51:42 +00001173 case ISD::SETEQ:
1174 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1175 case ISD::SETGT:
1176 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1177 case ISD::SETGE:
1178 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1179 case ISD::SETOLT: CondCode = ARMCC::MI; break;
Bob Wilsona2e83332009-09-09 23:14:54 +00001180 case ISD::SETOLE: CondCode = ARMCC::LS; break;
Evan Cheng10043e22007-01-19 07:51:42 +00001181 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1182 case ISD::SETO: CondCode = ARMCC::VC; break;
1183 case ISD::SETUO: CondCode = ARMCC::VS; break;
1184 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1185 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1186 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1187 case ISD::SETLT:
1188 case ISD::SETULT: CondCode = ARMCC::LT; break;
1189 case ISD::SETLE:
1190 case ISD::SETULE: CondCode = ARMCC::LE; break;
1191 case ISD::SETNE:
1192 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1193 }
Evan Cheng10043e22007-01-19 07:51:42 +00001194}
1195
Bob Wilsona4c22902009-04-17 19:07:39 +00001196//===----------------------------------------------------------------------===//
1197// Calling Convention Implementation
Bob Wilsona4c22902009-04-17 19:07:39 +00001198//===----------------------------------------------------------------------===//
1199
1200#include "ARMGenCallingConv.inc"
1201
Oliver Stannardc24f2172014-05-09 14:01:47 +00001202/// getEffectiveCallingConv - Get the effective calling convention, taking into
1203/// account presence of floating point hardware and calling convention
1204/// limitations, such as support for variadic functions.
1205CallingConv::ID
1206ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1207 bool isVarArg) const {
Anton Korobeynikova8fd40b2009-06-16 18:50:49 +00001208 switch (CC) {
1209 default:
Anton Korobeynikov22ef7512009-08-05 19:04:42 +00001210 llvm_unreachable("Unsupported calling convention");
Oliver Stannardc24f2172014-05-09 14:01:47 +00001211 case CallingConv::ARM_AAPCS:
1212 case CallingConv::ARM_APCS:
1213 case CallingConv::GHC:
1214 return CC;
1215 case CallingConv::ARM_AAPCS_VFP:
1216 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1217 case CallingConv::C:
Evan Cheng08dd8c82010-10-22 18:23:05 +00001218 if (!Subtarget->isAAPCS_ABI())
Oliver Stannardc24f2172014-05-09 14:01:47 +00001219 return CallingConv::ARM_APCS;
Oliver Stannardb5e596f2014-06-13 08:33:03 +00001220 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
Nick Lewycky50f02cb2011-12-02 22:16:29 +00001221 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1222 !isVarArg)
Oliver Stannardc24f2172014-05-09 14:01:47 +00001223 return CallingConv::ARM_AAPCS_VFP;
1224 else
1225 return CallingConv::ARM_AAPCS;
1226 case CallingConv::Fast:
1227 if (!Subtarget->isAAPCS_ABI()) {
Oliver Stannardb5e596f2014-06-13 08:33:03 +00001228 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
Oliver Stannardc24f2172014-05-09 14:01:47 +00001229 return CallingConv::Fast;
1230 return CallingConv::ARM_APCS;
Oliver Stannardb5e596f2014-06-13 08:33:03 +00001231 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
Oliver Stannardc24f2172014-05-09 14:01:47 +00001232 return CallingConv::ARM_AAPCS_VFP;
1233 else
1234 return CallingConv::ARM_AAPCS;
Evan Cheng08dd8c82010-10-22 18:23:05 +00001235 }
Oliver Stannardc24f2172014-05-09 14:01:47 +00001236}
1237
1238/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1239/// CallingConvention.
1240CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1241 bool Return,
1242 bool isVarArg) const {
1243 switch (getEffectiveCallingConv(CC, isVarArg)) {
1244 default:
1245 llvm_unreachable("Unsupported calling convention");
Anton Korobeynikova8fd40b2009-06-16 18:50:49 +00001246 case CallingConv::ARM_APCS:
Evan Cheng08dd8c82010-10-22 18:23:05 +00001247 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
Oliver Stannardc24f2172014-05-09 14:01:47 +00001248 case CallingConv::ARM_AAPCS:
1249 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1250 case CallingConv::ARM_AAPCS_VFP:
1251 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1252 case CallingConv::Fast:
1253 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
Eric Christopherb3322362012-08-03 00:05:53 +00001254 case CallingConv::GHC:
1255 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
Anton Korobeynikova8fd40b2009-06-16 18:50:49 +00001256 }
1257}
1258
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001259/// LowerCallResult - Lower the result values of a call into the
1260/// appropriate copies out of appropriate physical registers.
1261SDValue
1262ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel68c5f472009-09-02 08:44:58 +00001263 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001264 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00001265 SDLoc dl, SelectionDAG &DAG,
Stephen Linb8bd2322013-04-20 05:14:40 +00001266 SmallVectorImpl<SDValue> &InVals,
1267 bool isThisReturn, SDValue ThisVal) const {
Bob Wilsona4c22902009-04-17 19:07:39 +00001268
Bob Wilsona4c22902009-04-17 19:07:39 +00001269 // Assign locations to each value returned by this call.
1270 SmallVector<CCValAssign, 16> RVLocs;
Cameron Zwarich89019782011-06-10 20:59:24 +00001271 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1272 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001273 CCInfo.AnalyzeCallResult(Ins,
Anton Korobeynikov22ef7512009-08-05 19:04:42 +00001274 CCAssignFnForNode(CallConv, /* Return*/ true,
1275 isVarArg));
Bob Wilsona4c22902009-04-17 19:07:39 +00001276
1277 // Copy all of the result registers out of their specified physreg.
1278 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1279 CCValAssign VA = RVLocs[i];
1280
Stephen Linb8bd2322013-04-20 05:14:40 +00001281 // Pass 'this' value directly from the argument to return value, to avoid
1282 // reg unit interference
1283 if (i == 0 && isThisReturn) {
Stephen Lin8118e0b2013-04-23 19:42:25 +00001284 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1285 "unexpected return calling convention register assignment");
Stephen Linb8bd2322013-04-20 05:14:40 +00001286 InVals.push_back(ThisVal);
1287 continue;
1288 }
1289
Bob Wilson0041bd32009-04-25 00:33:20 +00001290 SDValue Val;
Bob Wilsona4c22902009-04-17 19:07:39 +00001291 if (VA.needsCustom()) {
Bob Wilson2e076c42009-06-22 23:27:02 +00001292 // Handle f64 or half of a v2f64.
Owen Anderson9f944592009-08-11 20:47:22 +00001293 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
Bob Wilsona4c22902009-04-17 19:07:39 +00001294 InFlag);
Bob Wilsonf134b2d2009-04-24 17:00:36 +00001295 Chain = Lo.getValue(1);
1296 InFlag = Lo.getValue(2);
Bob Wilsona4c22902009-04-17 19:07:39 +00001297 VA = RVLocs[++i]; // skip ahead to next loc
Owen Anderson9f944592009-08-11 20:47:22 +00001298 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
Bob Wilsonf134b2d2009-04-24 17:00:36 +00001299 InFlag);
1300 Chain = Hi.getValue(1);
1301 InFlag = Hi.getValue(2);
Christian Pirkerb5728192014-05-08 14:06:24 +00001302 if (!Subtarget->isLittle())
1303 std::swap (Lo, Hi);
Jim Grosbachd7cf55c2009-11-09 00:11:35 +00001304 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
Bob Wilson2e076c42009-06-22 23:27:02 +00001305
Owen Anderson9f944592009-08-11 20:47:22 +00001306 if (VA.getLocVT() == MVT::v2f64) {
1307 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1308 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1309 DAG.getConstant(0, MVT::i32));
Bob Wilson2e076c42009-06-22 23:27:02 +00001310
1311 VA = RVLocs[++i]; // skip ahead to next loc
Owen Anderson9f944592009-08-11 20:47:22 +00001312 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
Bob Wilson2e076c42009-06-22 23:27:02 +00001313 Chain = Lo.getValue(1);
1314 InFlag = Lo.getValue(2);
1315 VA = RVLocs[++i]; // skip ahead to next loc
Owen Anderson9f944592009-08-11 20:47:22 +00001316 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
Bob Wilson2e076c42009-06-22 23:27:02 +00001317 Chain = Hi.getValue(1);
1318 InFlag = Hi.getValue(2);
Christian Pirkerb5728192014-05-08 14:06:24 +00001319 if (!Subtarget->isLittle())
1320 std::swap (Lo, Hi);
Jim Grosbachd7cf55c2009-11-09 00:11:35 +00001321 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
Owen Anderson9f944592009-08-11 20:47:22 +00001322 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1323 DAG.getConstant(1, MVT::i32));
Bob Wilson2e076c42009-06-22 23:27:02 +00001324 }
Bob Wilsona4c22902009-04-17 19:07:39 +00001325 } else {
Bob Wilson0041bd32009-04-25 00:33:20 +00001326 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1327 InFlag);
Bob Wilsonf134b2d2009-04-24 17:00:36 +00001328 Chain = Val.getValue(1);
1329 InFlag = Val.getValue(2);
Bob Wilsona4c22902009-04-17 19:07:39 +00001330 }
Bob Wilson0041bd32009-04-25 00:33:20 +00001331
1332 switch (VA.getLocInfo()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00001333 default: llvm_unreachable("Unknown loc info!");
Bob Wilson0041bd32009-04-25 00:33:20 +00001334 case CCValAssign::Full: break;
1335 case CCValAssign::BCvt:
Wesley Peck527da1b2010-11-23 03:31:01 +00001336 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
Bob Wilson0041bd32009-04-25 00:33:20 +00001337 break;
1338 }
1339
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001340 InVals.push_back(Val);
Bob Wilsona4c22902009-04-17 19:07:39 +00001341 }
1342
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001343 return Chain;
Bob Wilsona4c22902009-04-17 19:07:39 +00001344}
1345
Bob Wilsonea09d4a2009-04-17 20:35:10 +00001346/// LowerMemOpCallTo - Store the argument to the stack.
Bob Wilsona4c22902009-04-17 19:07:39 +00001347SDValue
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001348ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1349 SDValue StackPtr, SDValue Arg,
Andrew Trickef9de2a2013-05-25 02:42:55 +00001350 SDLoc dl, SelectionDAG &DAG,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001351 const CCValAssign &VA,
Dan Gohman21cea8a2010-04-17 15:26:15 +00001352 ISD::ArgFlagsTy Flags) const {
Bob Wilsona4c22902009-04-17 19:07:39 +00001353 unsigned LocMemOffset = VA.getLocMemOffset();
1354 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1355 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
Bob Wilsona4c22902009-04-17 19:07:39 +00001356 return DAG.getStore(Chain, dl, Arg, PtrOff,
Chris Lattner886250c2010-09-21 18:51:21 +00001357 MachinePointerInfo::getStack(LocMemOffset),
David Greene0d0149f2010-02-15 16:55:24 +00001358 false, false, 0);
Evan Cheng10043e22007-01-19 07:51:42 +00001359}
1360
Andrew Trickef9de2a2013-05-25 02:42:55 +00001361void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
Bob Wilson2e076c42009-06-22 23:27:02 +00001362 SDValue Chain, SDValue &Arg,
1363 RegsToPassVector &RegsToPass,
1364 CCValAssign &VA, CCValAssign &NextVA,
1365 SDValue &StackPtr,
Craig Topperb94011f2013-07-14 04:42:23 +00001366 SmallVectorImpl<SDValue> &MemOpChains,
Dan Gohman21cea8a2010-04-17 15:26:15 +00001367 ISD::ArgFlagsTy Flags) const {
Bob Wilson2e076c42009-06-22 23:27:02 +00001368
Jim Grosbachd7cf55c2009-11-09 00:11:35 +00001369 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
Owen Anderson9f944592009-08-11 20:47:22 +00001370 DAG.getVTList(MVT::i32, MVT::i32), Arg);
Christian Pirkerb5728192014-05-08 14:06:24 +00001371 unsigned id = Subtarget->isLittle() ? 0 : 1;
1372 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
Bob Wilson2e076c42009-06-22 23:27:02 +00001373
1374 if (NextVA.isRegLoc())
Christian Pirkerb5728192014-05-08 14:06:24 +00001375 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
Bob Wilson2e076c42009-06-22 23:27:02 +00001376 else {
1377 assert(NextVA.isMemLoc());
Craig Topper062a2ba2014-04-25 05:30:21 +00001378 if (!StackPtr.getNode())
Bob Wilson2e076c42009-06-22 23:27:02 +00001379 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1380
Christian Pirkerb5728192014-05-08 14:06:24 +00001381 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001382 dl, DAG, NextVA,
1383 Flags));
Bob Wilson2e076c42009-06-22 23:27:02 +00001384 }
1385}
1386
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001387/// LowerCall - Lowering a call into a callseq_start <-
Evan Cheng4b6c8f72007-02-03 08:53:01 +00001388/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1389/// nodes.
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001390SDValue
Justin Holewinskiaa583972012-05-25 16:35:28 +00001391ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohman21cea8a2010-04-17 15:26:15 +00001392 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskiaa583972012-05-25 16:35:28 +00001393 SelectionDAG &DAG = CLI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +00001394 SDLoc &dl = CLI.DL;
Craig Topperb94011f2013-07-14 04:42:23 +00001395 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1396 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1397 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
Justin Holewinskiaa583972012-05-25 16:35:28 +00001398 SDValue Chain = CLI.Chain;
1399 SDValue Callee = CLI.Callee;
1400 bool &isTailCall = CLI.IsTailCall;
1401 CallingConv::ID CallConv = CLI.CallConv;
1402 bool doesNotRet = CLI.DoesNotReturn;
1403 bool isVarArg = CLI.IsVarArg;
1404
Dale Johannesend679ff72010-06-03 21:09:53 +00001405 MachineFunction &MF = DAG.getMachineFunction();
Stephen Lin4eedb292013-04-23 19:30:12 +00001406 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1407 bool isThisReturn = false;
1408 bool isSibCall = false;
Saleem Abdulrasool0d96f3d2014-03-11 15:09:54 +00001409
Bob Wilson8decdc42011-10-07 17:17:49 +00001410 // Disable tail calls if they're not supported.
Saleem Abdulrasool0d96f3d2014-03-11 15:09:54 +00001411 if (!Subtarget->supportsTailCall() || MF.getTarget().Options.DisableTailCalls)
Bob Wilson3c9ed762010-08-13 22:43:33 +00001412 isTailCall = false;
Saleem Abdulrasool0d96f3d2014-03-11 15:09:54 +00001413
Dale Johannesend679ff72010-06-03 21:09:53 +00001414 if (isTailCall) {
1415 // Check if it's really possible to do a tail call.
1416 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
Stephen Lin4eedb292013-04-23 19:30:12 +00001417 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
Dan Gohmanfe7532a2010-07-07 15:54:55 +00001418 Outs, OutVals, Ins, DAG);
Reid Kleckner5772b772014-04-24 20:14:34 +00001419 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1420 report_fatal_error("failed to perform tail call elimination on a call "
1421 "site marked musttail");
Dale Johannesend679ff72010-06-03 21:09:53 +00001422 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1423 // detected sibcalls.
1424 if (isTailCall) {
1425 ++NumTailCalls;
Stephen Lin4eedb292013-04-23 19:30:12 +00001426 isSibCall = true;
Dale Johannesend679ff72010-06-03 21:09:53 +00001427 }
1428 }
Evan Cheng10043e22007-01-19 07:51:42 +00001429
Bob Wilsona4c22902009-04-17 19:07:39 +00001430 // Analyze operands of the call, assigning locations to each operand.
1431 SmallVector<CCValAssign, 16> ArgLocs;
Cameron Zwarich89019782011-06-10 20:59:24 +00001432 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1433 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001434 CCInfo.AnalyzeCallOperands(Outs,
Anton Korobeynikov22ef7512009-08-05 19:04:42 +00001435 CCAssignFnForNode(CallConv, /* Return*/ false,
1436 isVarArg));
Evan Cheng10043e22007-01-19 07:51:42 +00001437
Bob Wilsona4c22902009-04-17 19:07:39 +00001438 // Get a count of how many bytes are to be pushed on the stack.
1439 unsigned NumBytes = CCInfo.getNextStackOffset();
Evan Cheng10043e22007-01-19 07:51:42 +00001440
Dale Johannesend679ff72010-06-03 21:09:53 +00001441 // For tail calls, memory operands are available in our caller's stack.
Stephen Lin4eedb292013-04-23 19:30:12 +00001442 if (isSibCall)
Dale Johannesend679ff72010-06-03 21:09:53 +00001443 NumBytes = 0;
1444
Evan Cheng10043e22007-01-19 07:51:42 +00001445 // Adjust the stack pointer for the new arguments...
1446 // These operations are automatically eliminated by the prolog/epilog pass
Stephen Lin4eedb292013-04-23 19:30:12 +00001447 if (!isSibCall)
Andrew Trickad6d08a2013-05-29 22:03:55 +00001448 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1449 dl);
Evan Cheng10043e22007-01-19 07:51:42 +00001450
Jim Grosbach6ad4bcb2010-02-24 01:43:03 +00001451 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
Evan Cheng10043e22007-01-19 07:51:42 +00001452
Bob Wilson2e076c42009-06-22 23:27:02 +00001453 RegsToPassVector RegsToPass;
Bob Wilsona4c22902009-04-17 19:07:39 +00001454 SmallVector<SDValue, 8> MemOpChains;
Evan Cheng10043e22007-01-19 07:51:42 +00001455
Bob Wilsona4c22902009-04-17 19:07:39 +00001456 // Walk the register/memloc assignments, inserting copies/loads. In the case
Bob Wilsonea09d4a2009-04-17 20:35:10 +00001457 // of tail call optimization, arguments are handled later.
Bob Wilsona4c22902009-04-17 19:07:39 +00001458 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1459 i != e;
1460 ++i, ++realArgIdx) {
1461 CCValAssign &VA = ArgLocs[i];
Dan Gohmanfe7532a2010-07-07 15:54:55 +00001462 SDValue Arg = OutVals[realArgIdx];
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001463 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00001464 bool isByVal = Flags.isByVal();
Evan Cheng10043e22007-01-19 07:51:42 +00001465
Bob Wilsona4c22902009-04-17 19:07:39 +00001466 // Promote the value if needed.
1467 switch (VA.getLocInfo()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00001468 default: llvm_unreachable("Unknown loc info!");
Bob Wilsona4c22902009-04-17 19:07:39 +00001469 case CCValAssign::Full: break;
1470 case CCValAssign::SExt:
1471 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1472 break;
1473 case CCValAssign::ZExt:
1474 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1475 break;
1476 case CCValAssign::AExt:
1477 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1478 break;
1479 case CCValAssign::BCvt:
Wesley Peck527da1b2010-11-23 03:31:01 +00001480 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
Bob Wilsona4c22902009-04-17 19:07:39 +00001481 break;
Evan Cheng10043e22007-01-19 07:51:42 +00001482 }
1483
Anton Korobeynikov22ef7512009-08-05 19:04:42 +00001484 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
Bob Wilsona4c22902009-04-17 19:07:39 +00001485 if (VA.needsCustom()) {
Owen Anderson9f944592009-08-11 20:47:22 +00001486 if (VA.getLocVT() == MVT::v2f64) {
1487 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1488 DAG.getConstant(0, MVT::i32));
1489 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1490 DAG.getConstant(1, MVT::i32));
Bob Wilsona4c22902009-04-17 19:07:39 +00001491
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001492 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
Bob Wilson2e076c42009-06-22 23:27:02 +00001493 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1494
1495 VA = ArgLocs[++i]; // skip ahead to next loc
1496 if (VA.isRegLoc()) {
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001497 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
Bob Wilson2e076c42009-06-22 23:27:02 +00001498 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1499 } else {
1500 assert(VA.isMemLoc());
Bob Wilson2e076c42009-06-22 23:27:02 +00001501
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001502 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1503 dl, DAG, VA, Flags));
Bob Wilson2e076c42009-06-22 23:27:02 +00001504 }
1505 } else {
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001506 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
Bob Wilson2e076c42009-06-22 23:27:02 +00001507 StackPtr, MemOpChains, Flags);
Bob Wilsona4c22902009-04-17 19:07:39 +00001508 }
1509 } else if (VA.isRegLoc()) {
Stephen Lin8118e0b2013-04-23 19:42:25 +00001510 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1511 assert(VA.getLocVT() == MVT::i32 &&
1512 "unexpected calling convention register assignment");
1513 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
Stephen Linb8bd2322013-04-20 05:14:40 +00001514 "unexpected use of 'returned'");
Stephen Lin4eedb292013-04-23 19:30:12 +00001515 isThisReturn = true;
Stephen Linb8bd2322013-04-20 05:14:40 +00001516 }
Bob Wilsona4c22902009-04-17 19:07:39 +00001517 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001518 } else if (isByVal) {
1519 assert(VA.isMemLoc());
1520 unsigned offset = 0;
1521
1522 // True if this byval aggregate will be split between registers
1523 // and memory.
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001524 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1525 unsigned CurByValIdx = CCInfo.getInRegsParamsProceed();
1526
1527 if (CurByValIdx < ByValArgsCount) {
1528
1529 unsigned RegBegin, RegEnd;
1530 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1531
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001532 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1533 unsigned int i, j;
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001534 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001535 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1536 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1537 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1538 MachinePointerInfo(),
Manman Ren5a787552013-10-07 19:47:53 +00001539 false, false, false,
1540 DAG.InferPtrAlignment(AddArg));
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001541 MemOpChains.push_back(Load.getValue(1));
1542 RegsToPass.push_back(std::make_pair(j, Load));
1543 }
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001544
1545 // If parameter size outsides register area, "offset" value
1546 // helps us to calculate stack slot for remained part properly.
1547 offset = RegEnd - RegBegin;
1548
1549 CCInfo.nextInRegsParam();
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001550 }
1551
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001552 if (Flags.getByValSize() > 4*offset) {
Manman Ren9f911162012-06-01 02:44:42 +00001553 unsigned LocMemOffset = VA.getLocMemOffset();
1554 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1555 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1556 StkPtrOff);
1557 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1558 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1559 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1560 MVT::i32);
Manman Rene8735522012-06-01 19:33:18 +00001561 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001562
Manman Ren9f911162012-06-01 02:44:42 +00001563 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
Manman Rene8735522012-06-01 19:33:18 +00001564 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
Manman Ren9f911162012-06-01 02:44:42 +00001565 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
Craig Topper48d114b2014-04-26 18:35:24 +00001566 Ops));
Manman Ren9f911162012-06-01 02:44:42 +00001567 }
Stephen Lin4eedb292013-04-23 19:30:12 +00001568 } else if (!isSibCall) {
Bob Wilsona4c22902009-04-17 19:07:39 +00001569 assert(VA.isMemLoc());
Bob Wilsona4c22902009-04-17 19:07:39 +00001570
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001571 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1572 dl, DAG, VA, Flags));
Bob Wilsona4c22902009-04-17 19:07:39 +00001573 }
Evan Cheng10043e22007-01-19 07:51:42 +00001574 }
1575
1576 if (!MemOpChains.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00001577 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
Evan Cheng10043e22007-01-19 07:51:42 +00001578
1579 // Build a sequence of copy-to-reg nodes chained together with token chain
1580 // and flag operands which copy the outgoing args into the appropriate regs.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001581 SDValue InFlag;
Dale Johannesen44f9dfc2010-06-15 22:08:33 +00001582 // Tail call byval lowering might overwrite argument registers so in case of
1583 // tail call optimization the copies to registers are lowered later.
1584 if (!isTailCall)
1585 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1586 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1587 RegsToPass[i].second, InFlag);
1588 InFlag = Chain.getValue(1);
1589 }
Evan Cheng10043e22007-01-19 07:51:42 +00001590
Dale Johannesend679ff72010-06-03 21:09:53 +00001591 // For tail calls lower the arguments to the 'real' stack slot.
1592 if (isTailCall) {
1593 // Force all the incoming stack arguments to be loaded from the stack
1594 // before any new outgoing arguments are stored to the stack, because the
1595 // outgoing stack slots may alias the incoming argument stack slots, and
1596 // the alias isn't otherwise explicit. This is slightly more conservative
1597 // than necessary, because it means that each store effectively depends
1598 // on every argument instead of just those arguments it would clobber.
1599
Chris Lattner0ab5e2c2011-04-15 05:18:47 +00001600 // Do not flag preceding copytoreg stuff together with the following stuff.
Dale Johannesend679ff72010-06-03 21:09:53 +00001601 InFlag = SDValue();
1602 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1603 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1604 RegsToPass[i].second, InFlag);
1605 InFlag = Chain.getValue(1);
1606 }
Stephen Lind36fd2c2013-04-20 00:47:48 +00001607 InFlag = SDValue();
Dale Johannesend679ff72010-06-03 21:09:53 +00001608 }
1609
Bill Wendling24c79f22008-09-16 21:48:12 +00001610 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1611 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1612 // node so that legalize doesn't hack it.
Evan Cheng10043e22007-01-19 07:51:42 +00001613 bool isDirect = false;
1614 bool isARMFunc = false;
Evan Chengc3c949b42007-06-19 21:05:09 +00001615 bool isLocalARMFunc = false;
Evan Cheng408aa562009-11-06 22:24:13 +00001616 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Jim Grosbach32bb3622010-04-14 22:28:31 +00001617
1618 if (EnableARMLongCalls) {
Saleem Abdulrasool90386ad2014-06-07 20:29:27 +00001619 assert((Subtarget->isTargetWindows() ||
1620 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1621 "long-calls with non-static relocation model!");
Jim Grosbach32bb3622010-04-14 22:28:31 +00001622 // Handle a global address or an external symbol. If it's not one of
1623 // those, the target's already in a register, so we don't need to do
1624 // anything extra.
1625 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Anders Carlsson47bccf72010-04-15 03:11:28 +00001626 const GlobalValue *GV = G->getGlobal();
Jim Grosbach32bb3622010-04-14 22:28:31 +00001627 // Create a constant pool entry for the callee address
Evan Chengdfce83c2011-01-17 08:03:18 +00001628 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
Bill Wendling7753d662011-10-01 08:00:54 +00001629 ARMConstantPoolValue *CPV =
1630 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1631
Jim Grosbach32bb3622010-04-14 22:28:31 +00001632 // Get the address of the callee into a register
1633 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1634 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1635 Callee = DAG.getLoad(getPointerTy(), dl,
1636 DAG.getEntryNode(), CPAddr,
Chris Lattner7727d052010-09-21 06:44:06 +00001637 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00001638 false, false, false, 0);
Jim Grosbach32bb3622010-04-14 22:28:31 +00001639 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1640 const char *Sym = S->getSymbol();
1641
1642 // Create a constant pool entry for the callee address
Evan Chengdfce83c2011-01-17 08:03:18 +00001643 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
Bill Wendlingc214cb02011-10-01 08:58:29 +00001644 ARMConstantPoolValue *CPV =
1645 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1646 ARMPCLabelIndex, 0);
Jim Grosbach32bb3622010-04-14 22:28:31 +00001647 // Get the address of the callee into a register
1648 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1649 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1650 Callee = DAG.getLoad(getPointerTy(), dl,
1651 DAG.getEntryNode(), CPAddr,
Chris Lattner7727d052010-09-21 06:44:06 +00001652 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00001653 false, false, false, 0);
Jim Grosbach32bb3622010-04-14 22:28:31 +00001654 }
1655 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Dan Gohmanbcaf6812010-04-15 01:51:59 +00001656 const GlobalValue *GV = G->getGlobal();
Evan Cheng10043e22007-01-19 07:51:42 +00001657 isDirect = true;
Chris Lattner55452c22009-07-15 04:12:33 +00001658 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
Tim Northoverd6a729b2014-01-06 14:28:05 +00001659 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
Evan Cheng10043e22007-01-19 07:51:42 +00001660 getTargetMachine().getRelocationModel() != Reloc::Static;
1661 isARMFunc = !Subtarget->isThumb() || isStub;
Evan Chengc3c949b42007-06-19 21:05:09 +00001662 // ARM call to a local ARM function is predicable.
Evan Chengf128bdc2010-06-16 07:35:02 +00001663 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
Evan Cheng83f35172007-01-30 20:37:08 +00001664 // tBX takes a register source operand.
Tim Northover72360d22013-12-02 10:35:41 +00001665 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
Tim Northoverd6a729b2014-01-06 14:28:05 +00001666 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
Tim Northover72360d22013-12-02 10:35:41 +00001667 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1668 DAG.getTargetGlobalAddress(GV, dl, getPointerTy()));
Saleem Abdulrasool763f9a52014-07-07 05:18:35 +00001669 } else if (Subtarget->isTargetCOFF()) {
1670 assert(Subtarget->isTargetWindows() &&
1671 "Windows is the only supported COFF target");
1672 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1673 ? ARMII::MO_DLLIMPORT
1674 : ARMII::MO_NO_FLAG;
1675 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), /*Offset=*/0,
1676 TargetFlags);
1677 if (GV->hasDLLImportStorageClass())
1678 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1679 DAG.getNode(ARMISD::Wrapper, dl, getPointerTy(),
1680 Callee), MachinePointerInfo::getGOT(),
1681 false, false, false, 0);
Jim Grosbach85dcd3d2010-09-22 23:27:36 +00001682 } else {
1683 // On ELF targets for PIC code, direct calls should go through the PLT
1684 unsigned OpFlags = 0;
1685 if (Subtarget->isTargetELF() &&
Chad Rosier537ff502013-02-28 19:16:42 +00001686 getTargetMachine().getRelocationModel() == Reloc::PIC_)
Jim Grosbach85dcd3d2010-09-22 23:27:36 +00001687 OpFlags = ARMII::MO_PLT;
1688 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1689 }
Bill Wendling24c79f22008-09-16 21:48:12 +00001690 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Evan Cheng10043e22007-01-19 07:51:42 +00001691 isDirect = true;
Tim Northoverd6a729b2014-01-06 14:28:05 +00001692 bool isStub = Subtarget->isTargetMachO() &&
Evan Cheng10043e22007-01-19 07:51:42 +00001693 getTargetMachine().getRelocationModel() != Reloc::Static;
1694 isARMFunc = !Subtarget->isThumb() || isStub;
Evan Cheng83f35172007-01-30 20:37:08 +00001695 // tBX takes a register source operand.
1696 const char *Sym = S->getSymbol();
David Goodwin22c2fba2009-07-08 23:10:31 +00001697 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
Evan Chengdfce83c2011-01-17 08:03:18 +00001698 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
Bill Wendlingc214cb02011-10-01 08:58:29 +00001699 ARMConstantPoolValue *CPV =
1700 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1701 ARMPCLabelIndex, 4);
Evan Cheng1fb8aed2009-03-13 07:51:59 +00001702 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
Owen Anderson9f944592009-08-11 20:47:22 +00001703 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Dale Johannesen021052a2009-02-04 20:06:27 +00001704 Callee = DAG.getLoad(getPointerTy(), dl,
Evan Chengcdbb70c2009-10-31 03:39:36 +00001705 DAG.getEntryNode(), CPAddr,
Chris Lattner7727d052010-09-21 06:44:06 +00001706 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00001707 false, false, false, 0);
Evan Cheng408aa562009-11-06 22:24:13 +00001708 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Bob Wilson7117a912009-03-20 22:42:55 +00001709 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
Dale Johannesen021052a2009-02-04 20:06:27 +00001710 getPointerTy(), Callee, PICLabel);
Jim Grosbach85dcd3d2010-09-22 23:27:36 +00001711 } else {
1712 unsigned OpFlags = 0;
1713 // On ELF targets for PIC code, direct calls should go through the PLT
1714 if (Subtarget->isTargetELF() &&
1715 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1716 OpFlags = ARMII::MO_PLT;
1717 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1718 }
Evan Cheng10043e22007-01-19 07:51:42 +00001719 }
1720
Lauro Ramos Venancioa88c4a72007-03-20 17:57:23 +00001721 // FIXME: handle tail calls differently.
1722 unsigned CallOpc;
Eric Christopherc1058df2014-07-04 01:55:26 +00001723 bool HasMinSizeAttr = MF.getFunction()->getAttributes().hasAttribute(
1724 AttributeSet::FunctionIndex, Attribute::MinSize);
Evan Cheng6ab54fd2009-08-01 00:16:10 +00001725 if (Subtarget->isThumb()) {
1726 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
Lauro Ramos Venancioa88c4a72007-03-20 17:57:23 +00001727 CallOpc = ARMISD::CALL_NOLINK;
1728 else
1729 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1730 } else {
Evan Cheng21b03482012-11-10 02:09:05 +00001731 if (!isDirect && !Subtarget->hasV5TOps())
Evan Cheng65f9d192012-02-28 18:51:51 +00001732 CallOpc = ARMISD::CALL_NOLINK;
Evan Cheng21b03482012-11-10 02:09:05 +00001733 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
Quentin Colombet8e1fe842012-11-02 21:32:17 +00001734 // Emit regular call when code size is the priority
1735 !HasMinSizeAttr)
Evan Cheng65f9d192012-02-28 18:51:51 +00001736 // "mov lr, pc; b _foo" to avoid confusing the RSP
1737 CallOpc = ARMISD::CALL_NOLINK;
1738 else
1739 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
Lauro Ramos Venancioa88c4a72007-03-20 17:57:23 +00001740 }
Lauro Ramos Venancioa88c4a72007-03-20 17:57:23 +00001741
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001742 std::vector<SDValue> Ops;
Evan Cheng10043e22007-01-19 07:51:42 +00001743 Ops.push_back(Chain);
1744 Ops.push_back(Callee);
1745
1746 // Add argument registers to the end of the list so that they are known live
1747 // into the call.
1748 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1749 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1750 RegsToPass[i].second.getValueType()));
1751
Jakob Stoklund Olesenfa7a5372012-02-24 01:19:29 +00001752 // Add a register mask operand representing the call-preserved registers.
Matthias Braunc22630e2013-10-04 16:52:54 +00001753 if (!isTailCall) {
1754 const uint32_t *Mask;
1755 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1756 const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1757 if (isThisReturn) {
1758 // For 'this' returns, use the R0-preserving mask if applicable
1759 Mask = ARI->getThisReturnPreservedMask(CallConv);
1760 if (!Mask) {
1761 // Set isThisReturn to false if the calling convention is not one that
1762 // allows 'returned' to be modeled in this way, so LowerCallResult does
1763 // not try to pass 'this' straight through
1764 isThisReturn = false;
1765 Mask = ARI->getCallPreservedMask(CallConv);
1766 }
1767 } else
Stephen Linff7fcee2013-06-26 21:42:14 +00001768 Mask = ARI->getCallPreservedMask(CallConv);
Stephen Linb8bd2322013-04-20 05:14:40 +00001769
Matthias Braunc22630e2013-10-04 16:52:54 +00001770 assert(Mask && "Missing call preserved mask for calling convention");
1771 Ops.push_back(DAG.getRegisterMask(Mask));
1772 }
Jakob Stoklund Olesenfa7a5372012-02-24 01:19:29 +00001773
Gabor Greiff304a7a2008-08-28 21:40:38 +00001774 if (InFlag.getNode())
Evan Cheng10043e22007-01-19 07:51:42 +00001775 Ops.push_back(InFlag);
Dale Johannesend679ff72010-06-03 21:09:53 +00001776
Chris Lattner3e5fbd72010-12-21 02:38:05 +00001777 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Dale Johannesen81ef35b2010-06-05 00:51:39 +00001778 if (isTailCall)
Craig Topper48d114b2014-04-26 18:35:24 +00001779 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
Dale Johannesend679ff72010-06-03 21:09:53 +00001780
Duncan Sands739a0542008-07-02 17:40:58 +00001781 // Returns a chain and a flag for retval copy to use.
Craig Topper48d114b2014-04-26 18:35:24 +00001782 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
Evan Cheng10043e22007-01-19 07:51:42 +00001783 InFlag = Chain.getValue(1);
1784
Chris Lattner27539552008-10-11 22:08:30 +00001785 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
Andrew Trickad6d08a2013-05-29 22:03:55 +00001786 DAG.getIntPtrConstant(0, true), InFlag, dl);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00001787 if (!Ins.empty())
Evan Cheng10043e22007-01-19 07:51:42 +00001788 InFlag = Chain.getValue(1);
1789
Bob Wilsona4c22902009-04-17 19:07:39 +00001790 // Handle result values, copying them out of physregs into vregs that we
1791 // return.
Stephen Linb8bd2322013-04-20 05:14:40 +00001792 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
Stephen Lin4eedb292013-04-23 19:30:12 +00001793 InVals, isThisReturn,
1794 isThisReturn ? OutVals[0] : SDValue());
Evan Cheng10043e22007-01-19 07:51:42 +00001795}
1796
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00001797/// HandleByVal - Every parameter *after* a byval parameter is passed
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001798/// on the stack. Remember the next parameter register to allocate,
1799/// and then confiscate the rest of the parameter registers to insure
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00001800/// this.
1801void
Stepan Dyatkovskiye59a9202012-10-16 07:16:47 +00001802ARMTargetLowering::HandleByVal(
1803 CCState *State, unsigned &size, unsigned Align) const {
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001804 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1805 assert((State->getCallOrPrologue() == Prologue ||
1806 State->getCallOrPrologue() == Call) &&
1807 "unhandled ParmContext");
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001808
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001809 if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
Stepan Dyatkovskiye59a9202012-10-16 07:16:47 +00001810 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1811 unsigned AlignInRegs = Align / 4;
1812 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1813 for (unsigned i = 0; i < Waste; ++i)
1814 reg = State->AllocateReg(GPRArgRegs, 4);
1815 }
1816 if (reg != 0) {
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001817 unsigned excess = 4 * (ARM::R4 - reg);
1818
1819 // Special case when NSAA != SP and parameter size greater than size of
1820 // all remained GPR regs. In that case we can't split parameter, we must
1821 // send it to stack. We also must set NCRN to R4, so waste all
1822 // remained registers.
Oliver Stannardd55e1152014-03-05 15:25:27 +00001823 const unsigned NSAAOffset = State->getNextStackOffset();
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001824 if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1825 while (State->AllocateReg(GPRArgRegs, 4))
1826 ;
1827 return;
1828 }
1829
1830 // First register for byval parameter is the first register that wasn't
1831 // allocated before this method call, so it would be "reg".
1832 // If parameter is small enough to be saved in range [reg, r4), then
1833 // the end (first after last) register would be reg + param-size-in-regs,
1834 // else parameter would be splitted between registers and stack,
1835 // end register would be r4 in this case.
1836 unsigned ByValRegBegin = reg;
Stepan Dyatkovskiy2703bca2013-05-08 14:51:27 +00001837 unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00001838 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1839 // Note, first register is allocated in the beginning of function already,
1840 // allocate remained amount of registers we need.
1841 for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1842 State->AllocateReg(GPRArgRegs, 4);
Oliver Stannardd55e1152014-03-05 15:25:27 +00001843 // A byval parameter that is split between registers and memory needs its
1844 // size truncated here.
1845 // In the case where the entire structure fits in registers, we set the
1846 // size in memory to zero.
1847 if (size < excess)
1848 size = 0;
1849 else
1850 size -= excess;
Stuart Hastings45fe3c32011-04-20 16:47:52 +00001851 }
1852 }
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00001853}
1854
Dale Johannesend679ff72010-06-03 21:09:53 +00001855/// MatchingStackOffset - Return true if the given stack call argument is
1856/// already available in the same position (relatively) of the caller's
1857/// incoming argument stack.
1858static
1859bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1860 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
Craig Topper07720d82012-03-25 23:49:58 +00001861 const TargetInstrInfo *TII) {
Dale Johannesend679ff72010-06-03 21:09:53 +00001862 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1863 int FI = INT_MAX;
1864 if (Arg.getOpcode() == ISD::CopyFromReg) {
1865 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
Jakob Stoklund Olesen2fb5b312011-01-10 02:58:51 +00001866 if (!TargetRegisterInfo::isVirtualRegister(VR))
Dale Johannesend679ff72010-06-03 21:09:53 +00001867 return false;
1868 MachineInstr *Def = MRI->getVRegDef(VR);
1869 if (!Def)
1870 return false;
1871 if (!Flags.isByVal()) {
1872 if (!TII->isLoadFromStackSlot(Def, FI))
1873 return false;
1874 } else {
Dale Johannesene2289282010-07-08 01:18:23 +00001875 return false;
Dale Johannesend679ff72010-06-03 21:09:53 +00001876 }
1877 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1878 if (Flags.isByVal())
1879 // ByVal argument is passed in as a pointer but it's now being
1880 // dereferenced. e.g.
1881 // define @foo(%struct.X* %A) {
1882 // tail call @bar(%struct.X* byval %A)
1883 // }
1884 return false;
1885 SDValue Ptr = Ld->getBasePtr();
1886 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1887 if (!FINode)
1888 return false;
1889 FI = FINode->getIndex();
1890 } else
1891 return false;
1892
1893 assert(FI != INT_MAX);
1894 if (!MFI->isFixedObjectIndex(FI))
1895 return false;
1896 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1897}
1898
1899/// IsEligibleForTailCallOptimization - Check whether the call is eligible
1900/// for tail call optimization. Targets which want to do tail call
1901/// optimization should implement this function.
1902bool
1903ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1904 CallingConv::ID CalleeCC,
1905 bool isVarArg,
1906 bool isCalleeStructRet,
1907 bool isCallerStructRet,
1908 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +00001909 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesend679ff72010-06-03 21:09:53 +00001910 const SmallVectorImpl<ISD::InputArg> &Ins,
1911 SelectionDAG& DAG) const {
Dale Johannesend679ff72010-06-03 21:09:53 +00001912 const Function *CallerF = DAG.getMachineFunction().getFunction();
1913 CallingConv::ID CallerCC = CallerF->getCallingConv();
1914 bool CCMatch = CallerCC == CalleeCC;
1915
1916 // Look for obvious safe cases to perform tail call optimization that do not
1917 // require ABI changes. This is what gcc calls sibcall.
1918
Jim Grosbache3864cc2010-06-16 23:45:49 +00001919 // Do not sibcall optimize vararg calls unless the call site is not passing
1920 // any arguments.
Dale Johannesend679ff72010-06-03 21:09:53 +00001921 if (isVarArg && !Outs.empty())
1922 return false;
1923
Tim Northoverd8407452013-10-01 14:33:28 +00001924 // Exception-handling functions need a special set of instructions to indicate
1925 // a return to the hardware. Tail-calling another function would probably
1926 // break this.
1927 if (CallerF->hasFnAttribute("interrupt"))
1928 return false;
1929
Dale Johannesend679ff72010-06-03 21:09:53 +00001930 // Also avoid sibcall optimization if either caller or callee uses struct
1931 // return semantics.
1932 if (isCalleeStructRet || isCallerStructRet)
1933 return false;
1934
Dale Johannesend24c66b2010-06-23 18:52:34 +00001935 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
Jim Grosbach3840c902011-07-08 20:18:11 +00001936 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1937 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1938 // support in the assembler and linker to be used. This would need to be
1939 // fixed to fully support tail calls in Thumb1.
1940 //
Dale Johannesene2289282010-07-08 01:18:23 +00001941 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1942 // LR. This means if we need to reload LR, it takes an extra instructions,
1943 // which outweighs the value of the tail call; but here we don't know yet
1944 // whether LR is going to be used. Probably the right approach is to
Jim Grosbach535d3b42010-09-08 03:54:02 +00001945 // generate the tail call here and turn it back into CALL/RET in
Dale Johannesene2289282010-07-08 01:18:23 +00001946 // emitEpilogue if LR is used.
Dale Johannesene2289282010-07-08 01:18:23 +00001947
1948 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1949 // but we need to make sure there are enough registers; the only valid
1950 // registers are the 4 used for parameters. We don't currently do this
1951 // case.
Evan Chengd4b08732010-11-30 23:55:39 +00001952 if (Subtarget->isThumb1Only())
1953 return false;
Dale Johannesen3ac52b32010-06-18 18:13:11 +00001954
Dale Johannesend679ff72010-06-03 21:09:53 +00001955 // If the calling conventions do not match, then we'd better make sure the
1956 // results are returned in the same way as what the caller expects.
1957 if (!CCMatch) {
1958 SmallVector<CCValAssign, 16> RVLocs1;
Cameron Zwarich89019782011-06-10 20:59:24 +00001959 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1960 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
Dale Johannesend679ff72010-06-03 21:09:53 +00001961 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1962
1963 SmallVector<CCValAssign, 16> RVLocs2;
Cameron Zwarich89019782011-06-10 20:59:24 +00001964 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1965 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
Dale Johannesend679ff72010-06-03 21:09:53 +00001966 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1967
1968 if (RVLocs1.size() != RVLocs2.size())
1969 return false;
1970 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1971 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1972 return false;
1973 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1974 return false;
1975 if (RVLocs1[i].isRegLoc()) {
1976 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1977 return false;
1978 } else {
1979 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1980 return false;
1981 }
1982 }
1983 }
1984
Manman Ren7e48b252012-10-12 23:39:43 +00001985 // If Caller's vararg or byval argument has been split between registers and
1986 // stack, do not perform tail call, since part of the argument is in caller's
1987 // local frame.
1988 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
1989 getInfo<ARMFunctionInfo>();
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00001990 if (AFI_Caller->getArgRegsSaveSize())
Manman Ren7e48b252012-10-12 23:39:43 +00001991 return false;
1992
Dale Johannesend679ff72010-06-03 21:09:53 +00001993 // If the callee takes no arguments then go on to check the results of the
1994 // call.
1995 if (!Outs.empty()) {
1996 // Check if stack adjustment is needed. For now, do not do this if any
1997 // argument is passed on the stack.
1998 SmallVector<CCValAssign, 16> ArgLocs;
Cameron Zwarich89019782011-06-10 20:59:24 +00001999 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2000 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
Dale Johannesend679ff72010-06-03 21:09:53 +00002001 CCInfo.AnalyzeCallOperands(Outs,
2002 CCAssignFnForNode(CalleeCC, false, isVarArg));
2003 if (CCInfo.getNextStackOffset()) {
2004 MachineFunction &MF = DAG.getMachineFunction();
2005
2006 // Check if the arguments are already laid out in the right way as
2007 // the caller's fixed stack objects.
2008 MachineFrameInfo *MFI = MF.getFrameInfo();
2009 const MachineRegisterInfo *MRI = &MF.getRegInfo();
Craig Topper07720d82012-03-25 23:49:58 +00002010 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Dale Johannesen81ef35b2010-06-05 00:51:39 +00002011 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2012 i != e;
2013 ++i, ++realArgIdx) {
Dale Johannesend679ff72010-06-03 21:09:53 +00002014 CCValAssign &VA = ArgLocs[i];
2015 EVT RegVT = VA.getLocVT();
Dan Gohmanfe7532a2010-07-07 15:54:55 +00002016 SDValue Arg = OutVals[realArgIdx];
Dale Johannesen81ef35b2010-06-05 00:51:39 +00002017 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
Dale Johannesend679ff72010-06-03 21:09:53 +00002018 if (VA.getLocInfo() == CCValAssign::Indirect)
2019 return false;
Dale Johannesen81ef35b2010-06-05 00:51:39 +00002020 if (VA.needsCustom()) {
2021 // f64 and vector types are split into multiple registers or
2022 // register/stack-slot combinations. The types will not match
2023 // the registers; give up on memory f64 refs until we figure
2024 // out what to do about this.
2025 if (!VA.isRegLoc())
2026 return false;
2027 if (!ArgLocs[++i].isRegLoc())
Jim Grosbach535d3b42010-09-08 03:54:02 +00002028 return false;
Dale Johannesen81ef35b2010-06-05 00:51:39 +00002029 if (RegVT == MVT::v2f64) {
2030 if (!ArgLocs[++i].isRegLoc())
2031 return false;
2032 if (!ArgLocs[++i].isRegLoc())
2033 return false;
2034 }
2035 } else if (!VA.isRegLoc()) {
Dale Johannesend679ff72010-06-03 21:09:53 +00002036 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2037 MFI, MRI, TII))
2038 return false;
2039 }
2040 }
2041 }
2042 }
2043
2044 return true;
2045}
2046
Benjamin Kramerb1996da2012-11-28 20:55:10 +00002047bool
2048ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2049 MachineFunction &MF, bool isVarArg,
2050 const SmallVectorImpl<ISD::OutputArg> &Outs,
2051 LLVMContext &Context) const {
2052 SmallVector<CCValAssign, 16> RVLocs;
2053 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2054 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2055 isVarArg));
2056}
2057
Tim Northoverd8407452013-10-01 14:33:28 +00002058static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2059 SDLoc DL, SelectionDAG &DAG) {
2060 const MachineFunction &MF = DAG.getMachineFunction();
2061 const Function *F = MF.getFunction();
2062
2063 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2064
2065 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2066 // version of the "preferred return address". These offsets affect the return
2067 // instruction if this is a return from PL1 without hypervisor extensions.
2068 // IRQ/FIQ: +4 "subs pc, lr, #4"
2069 // SWI: 0 "subs pc, lr, #0"
2070 // ABORT: +4 "subs pc, lr, #4"
2071 // UNDEF: +4/+2 "subs pc, lr, #0"
2072 // UNDEF varies depending on where the exception came from ARM or Thumb
2073 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2074
2075 int64_t LROffset;
2076 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2077 IntKind == "ABORT")
2078 LROffset = 4;
2079 else if (IntKind == "SWI" || IntKind == "UNDEF")
2080 LROffset = 0;
2081 else
2082 report_fatal_error("Unsupported interrupt attribute. If present, value "
2083 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2084
2085 RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2086
Craig Topper48d114b2014-04-26 18:35:24 +00002087 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
Tim Northoverd8407452013-10-01 14:33:28 +00002088}
2089
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002090SDValue
2091ARMTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +00002092 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002093 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +00002094 const SmallVectorImpl<SDValue> &OutVals,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002095 SDLoc dl, SelectionDAG &DAG) const {
Bob Wilson7117a912009-03-20 22:42:55 +00002096
Bob Wilsonea09d4a2009-04-17 20:35:10 +00002097 // CCValAssign - represent the assignment of the return value to a location.
Bob Wilsona4c22902009-04-17 19:07:39 +00002098 SmallVector<CCValAssign, 16> RVLocs;
Bob Wilsona4c22902009-04-17 19:07:39 +00002099
Bob Wilsonea09d4a2009-04-17 20:35:10 +00002100 // CCState - Info about the registers and stack slots.
Cameron Zwarich89019782011-06-10 20:59:24 +00002101 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2102 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
Bob Wilsona4c22902009-04-17 19:07:39 +00002103
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002104 // Analyze outgoing return values.
Anton Korobeynikov22ef7512009-08-05 19:04:42 +00002105 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2106 isVarArg));
Bob Wilsona4c22902009-04-17 19:07:39 +00002107
Bob Wilsona4c22902009-04-17 19:07:39 +00002108 SDValue Flag;
Jakob Stoklund Olesenf90fb6e2013-02-05 18:08:40 +00002109 SmallVector<SDValue, 4> RetOps;
2110 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
Christian Pirkerb5728192014-05-08 14:06:24 +00002111 bool isLittleEndian = Subtarget->isLittle();
Bob Wilsona4c22902009-04-17 19:07:39 +00002112
2113 // Copy the result values into the output registers.
2114 for (unsigned i = 0, realRVLocIdx = 0;
2115 i != RVLocs.size();
2116 ++i, ++realRVLocIdx) {
2117 CCValAssign &VA = RVLocs[i];
2118 assert(VA.isRegLoc() && "Can only return in registers!");
2119
Dan Gohmanfe7532a2010-07-07 15:54:55 +00002120 SDValue Arg = OutVals[realRVLocIdx];
Bob Wilsona4c22902009-04-17 19:07:39 +00002121
2122 switch (VA.getLocInfo()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00002123 default: llvm_unreachable("Unknown loc info!");
Bob Wilsona4c22902009-04-17 19:07:39 +00002124 case CCValAssign::Full: break;
2125 case CCValAssign::BCvt:
Wesley Peck527da1b2010-11-23 03:31:01 +00002126 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
Bob Wilsona4c22902009-04-17 19:07:39 +00002127 break;
2128 }
2129
Bob Wilsona4c22902009-04-17 19:07:39 +00002130 if (VA.needsCustom()) {
Owen Anderson9f944592009-08-11 20:47:22 +00002131 if (VA.getLocVT() == MVT::v2f64) {
Bob Wilson2e076c42009-06-22 23:27:02 +00002132 // Extract the first half and return it in two registers.
Owen Anderson9f944592009-08-11 20:47:22 +00002133 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2134 DAG.getConstant(0, MVT::i32));
Jim Grosbachd7cf55c2009-11-09 00:11:35 +00002135 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
Owen Anderson9f944592009-08-11 20:47:22 +00002136 DAG.getVTList(MVT::i32, MVT::i32), Half);
Bob Wilson2e076c42009-06-22 23:27:02 +00002137
Christian Pirkerb5728192014-05-08 14:06:24 +00002138 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2139 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2140 Flag);
Bob Wilson2e076c42009-06-22 23:27:02 +00002141 Flag = Chain.getValue(1);
Jakob Stoklund Olesenf90fb6e2013-02-05 18:08:40 +00002142 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
Bob Wilson2e076c42009-06-22 23:27:02 +00002143 VA = RVLocs[++i]; // skip ahead to next loc
2144 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
Christian Pirkerb5728192014-05-08 14:06:24 +00002145 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2146 Flag);
Bob Wilson2e076c42009-06-22 23:27:02 +00002147 Flag = Chain.getValue(1);
Jakob Stoklund Olesenf90fb6e2013-02-05 18:08:40 +00002148 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
Bob Wilson2e076c42009-06-22 23:27:02 +00002149 VA = RVLocs[++i]; // skip ahead to next loc
2150
2151 // Extract the 2nd half and fall through to handle it as an f64 value.
Owen Anderson9f944592009-08-11 20:47:22 +00002152 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2153 DAG.getConstant(1, MVT::i32));
Bob Wilson2e076c42009-06-22 23:27:02 +00002154 }
2155 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2156 // available.
Jim Grosbachd7cf55c2009-11-09 00:11:35 +00002157 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
Craig Topper48d114b2014-04-26 18:35:24 +00002158 DAG.getVTList(MVT::i32, MVT::i32), Arg);
Christian Pirkerb5728192014-05-08 14:06:24 +00002159 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2160 fmrrd.getValue(isLittleEndian ? 0 : 1),
2161 Flag);
Bob Wilsonf134b2d2009-04-24 17:00:36 +00002162 Flag = Chain.getValue(1);
Jakob Stoklund Olesenf90fb6e2013-02-05 18:08:40 +00002163 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
Bob Wilsona4c22902009-04-17 19:07:39 +00002164 VA = RVLocs[++i]; // skip ahead to next loc
Christian Pirkerb5728192014-05-08 14:06:24 +00002165 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2166 fmrrd.getValue(isLittleEndian ? 1 : 0),
Bob Wilsona4c22902009-04-17 19:07:39 +00002167 Flag);
2168 } else
2169 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2170
Bob Wilsonea09d4a2009-04-17 20:35:10 +00002171 // Guarantee that all emitted copies are
2172 // stuck together, avoiding something bad.
Bob Wilsona4c22902009-04-17 19:07:39 +00002173 Flag = Chain.getValue(1);
Jakob Stoklund Olesenf90fb6e2013-02-05 18:08:40 +00002174 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
Bob Wilsona4c22902009-04-17 19:07:39 +00002175 }
2176
Jakob Stoklund Olesenf90fb6e2013-02-05 18:08:40 +00002177 // Update chain and glue.
2178 RetOps[0] = Chain;
Bob Wilsona4c22902009-04-17 19:07:39 +00002179 if (Flag.getNode())
Jakob Stoklund Olesenf90fb6e2013-02-05 18:08:40 +00002180 RetOps.push_back(Flag);
Bob Wilsona4c22902009-04-17 19:07:39 +00002181
Tim Northoverd8407452013-10-01 14:33:28 +00002182 // CPUs which aren't M-class use a special sequence to return from
2183 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2184 // though we use "subs pc, lr, #N").
2185 //
2186 // M-class CPUs actually use a normal return sequence with a special
2187 // (hardware-provided) value in LR, so the normal code path works.
2188 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2189 !Subtarget->isMClass()) {
2190 if (Subtarget->isThumb1Only())
2191 report_fatal_error("interrupt attribute is not supported in Thumb1");
2192 return LowerInterruptReturn(RetOps, dl, DAG);
2193 }
2194
Craig Topper48d114b2014-04-26 18:35:24 +00002195 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
Evan Cheng10043e22007-01-19 07:51:42 +00002196}
2197
Evan Chengf8bad082012-04-10 01:51:00 +00002198bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
Evan Chengd4b08732010-11-30 23:55:39 +00002199 if (N->getNumValues() != 1)
2200 return false;
2201 if (!N->hasNUsesOfValue(1, 0))
2202 return false;
2203
Evan Chengf8bad082012-04-10 01:51:00 +00002204 SDValue TCChain = Chain;
2205 SDNode *Copy = *N->use_begin();
2206 if (Copy->getOpcode() == ISD::CopyToReg) {
2207 // If the copy has a glue operand, we conservatively assume it isn't safe to
2208 // perform a tail call.
2209 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2210 return false;
2211 TCChain = Copy->getOperand(0);
2212 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2213 SDNode *VMov = Copy;
Evan Chengd4b08732010-11-30 23:55:39 +00002214 // f64 returned in a pair of GPRs.
Evan Chengf8bad082012-04-10 01:51:00 +00002215 SmallPtrSet<SDNode*, 2> Copies;
2216 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
Evan Chengd4b08732010-11-30 23:55:39 +00002217 UI != UE; ++UI) {
2218 if (UI->getOpcode() != ISD::CopyToReg)
2219 return false;
Evan Chengf8bad082012-04-10 01:51:00 +00002220 Copies.insert(*UI);
Evan Chengd4b08732010-11-30 23:55:39 +00002221 }
Evan Chengf8bad082012-04-10 01:51:00 +00002222 if (Copies.size() > 2)
2223 return false;
2224
2225 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2226 UI != UE; ++UI) {
2227 SDValue UseChain = UI->getOperand(0);
2228 if (Copies.count(UseChain.getNode()))
2229 // Second CopyToReg
2230 Copy = *UI;
2231 else
2232 // First CopyToReg
2233 TCChain = UseChain;
2234 }
2235 } else if (Copy->getOpcode() == ISD::BITCAST) {
Evan Chengd4b08732010-11-30 23:55:39 +00002236 // f32 returned in a single GPR.
Evan Chengf8bad082012-04-10 01:51:00 +00002237 if (!Copy->hasOneUse())
Evan Chengd4b08732010-11-30 23:55:39 +00002238 return false;
Evan Chengf8bad082012-04-10 01:51:00 +00002239 Copy = *Copy->use_begin();
2240 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
Evan Chengd4b08732010-11-30 23:55:39 +00002241 return false;
Lang Hames67c09b32013-05-13 10:21:19 +00002242 TCChain = Copy->getOperand(0);
Evan Chengd4b08732010-11-30 23:55:39 +00002243 } else {
2244 return false;
2245 }
2246
Evan Cheng419ea282010-12-01 22:59:46 +00002247 bool HasRet = false;
Evan Chengf8bad082012-04-10 01:51:00 +00002248 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2249 UI != UE; ++UI) {
Tim Northoverd8407452013-10-01 14:33:28 +00002250 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2251 UI->getOpcode() != ARMISD::INTRET_FLAG)
Evan Chengf8bad082012-04-10 01:51:00 +00002252 return false;
2253 HasRet = true;
Evan Chengd4b08732010-11-30 23:55:39 +00002254 }
2255
Evan Chengf8bad082012-04-10 01:51:00 +00002256 if (!HasRet)
2257 return false;
2258
2259 Chain = TCChain;
2260 return true;
Evan Chengd4b08732010-11-30 23:55:39 +00002261}
2262
Evan Cheng0663f232011-03-21 01:19:09 +00002263bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
Saleem Abdulrasoolb720a6b2014-03-11 15:09:49 +00002264 if (!Subtarget->supportsTailCall())
Evan Cheng0663f232011-03-21 01:19:09 +00002265 return false;
2266
Saleem Abdulrasool0d96f3d2014-03-11 15:09:54 +00002267 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
Evan Cheng0663f232011-03-21 01:19:09 +00002268 return false;
2269
2270 return !Subtarget->isThumb1Only();
2271}
2272
Bob Wilsonb389f2a2009-11-03 00:02:05 +00002273// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2274// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2275// one of the above mentioned nodes. It has to be wrapped because otherwise
2276// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2277// be used to form addressing mode. These wrapped nodes will be selected
2278// into MOVi.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002279static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
Owen Anderson53aa7a92009-08-10 22:56:29 +00002280 EVT PtrVT = Op.getValueType();
Dale Johannesen62fd95d2009-02-07 00:55:49 +00002281 // FIXME there is no actual debug info here
Andrew Trickef9de2a2013-05-25 02:42:55 +00002282 SDLoc dl(Op);
Evan Cheng10043e22007-01-19 07:51:42 +00002283 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002284 SDValue Res;
Evan Cheng10043e22007-01-19 07:51:42 +00002285 if (CP->isMachineConstantPoolEntry())
2286 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2287 CP->getAlignment());
2288 else
2289 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2290 CP->getAlignment());
Owen Anderson9f944592009-08-11 20:47:22 +00002291 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
Evan Cheng10043e22007-01-19 07:51:42 +00002292}
2293
Jim Grosbach8d3ba732010-07-19 17:20:38 +00002294unsigned ARMTargetLowering::getJumpTableEncoding() const {
2295 return MachineJumpTableInfo::EK_Inline;
2296}
2297
Dan Gohman21cea8a2010-04-17 15:26:15 +00002298SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2299 SelectionDAG &DAG) const {
Evan Cheng408aa562009-11-06 22:24:13 +00002300 MachineFunction &MF = DAG.getMachineFunction();
2301 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2302 unsigned ARMPCLabelIndex = 0;
Andrew Trickef9de2a2013-05-25 02:42:55 +00002303 SDLoc DL(Op);
Bob Wilson1c66e8a2009-11-02 20:59:23 +00002304 EVT PtrVT = getPointerTy();
Dan Gohmanbcaf6812010-04-15 01:51:59 +00002305 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
Bob Wilson1c66e8a2009-11-02 20:59:23 +00002306 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2307 SDValue CPAddr;
2308 if (RelocM == Reloc::Static) {
2309 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2310 } else {
2311 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
Evan Chengdfce83c2011-01-17 08:03:18 +00002312 ARMPCLabelIndex = AFI->createPICLabelUId();
Bill Wendling7753d662011-10-01 08:00:54 +00002313 ARMConstantPoolValue *CPV =
2314 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2315 ARMCP::CPBlockAddress, PCAdj);
Bob Wilson1c66e8a2009-11-02 20:59:23 +00002316 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2317 }
2318 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2319 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
Chris Lattner7727d052010-09-21 06:44:06 +00002320 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002321 false, false, false, 0);
Bob Wilson1c66e8a2009-11-02 20:59:23 +00002322 if (RelocM == Reloc::Static)
2323 return Result;
Evan Cheng408aa562009-11-06 22:24:13 +00002324 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Bob Wilson1c66e8a2009-11-02 20:59:23 +00002325 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
Bob Wilson1cf0b032009-10-30 05:45:42 +00002326}
2327
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002328// Lower ISD::GlobalTLSAddress using the "general dynamic" model
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002329SDValue
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002330ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohman21cea8a2010-04-17 15:26:15 +00002331 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00002332 SDLoc dl(GA);
Owen Anderson53aa7a92009-08-10 22:56:29 +00002333 EVT PtrVT = getPointerTy();
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002334 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
Evan Cheng408aa562009-11-06 22:24:13 +00002335 MachineFunction &MF = DAG.getMachineFunction();
2336 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Evan Chengdfce83c2011-01-17 08:03:18 +00002337 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002338 ARMConstantPoolValue *CPV =
Bill Wendling7753d662011-10-01 08:00:54 +00002339 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2340 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
Evan Cheng1fb8aed2009-03-13 07:51:59 +00002341 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson9f944592009-08-11 20:47:22 +00002342 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
Evan Chengcdbb70c2009-10-31 03:39:36 +00002343 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
Chris Lattner7727d052010-09-21 06:44:06 +00002344 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002345 false, false, false, 0);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002346 SDValue Chain = Argument.getValue(1);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002347
Evan Cheng408aa562009-11-06 22:24:13 +00002348 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Dale Johannesen021052a2009-02-04 20:06:27 +00002349 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002350
2351 // call __tls_get_addr.
2352 ArgListTy Args;
2353 ArgListEntry Entry;
2354 Entry.Node = Argument;
Chris Lattner229907c2011-07-18 04:54:35 +00002355 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002356 Args.push_back(Entry);
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +00002357
Dale Johannesen555a3752009-01-30 23:10:59 +00002358 // FIXME: is there useful debug info available here?
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +00002359 TargetLowering::CallLoweringInfo CLI(DAG);
2360 CLI.setDebugLoc(dl).setChain(Chain)
2361 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
Juergen Ributzka3bd03c72014-07-01 22:01:54 +00002362 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2363 0);
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +00002364
Justin Holewinskiaa583972012-05-25 16:35:28 +00002365 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002366 return CallResult.first;
2367}
2368
2369// Lower ISD::GlobalTLSAddress using the "initial exec" or
2370// "local exec" model.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002371SDValue
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002372ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgaea41202012-05-04 09:40:39 +00002373 SelectionDAG &DAG,
2374 TLSModel::Model model) const {
Dan Gohmanbcaf6812010-04-15 01:51:59 +00002375 const GlobalValue *GV = GA->getGlobal();
Andrew Trickef9de2a2013-05-25 02:42:55 +00002376 SDLoc dl(GA);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002377 SDValue Offset;
2378 SDValue Chain = DAG.getEntryNode();
Owen Anderson53aa7a92009-08-10 22:56:29 +00002379 EVT PtrVT = getPointerTy();
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002380 // Get the Thread Pointer
Dale Johannesen021052a2009-02-04 20:06:27 +00002381 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002382
Hans Wennborgaea41202012-05-04 09:40:39 +00002383 if (model == TLSModel::InitialExec) {
Evan Cheng408aa562009-11-06 22:24:13 +00002384 MachineFunction &MF = DAG.getMachineFunction();
2385 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Evan Chengdfce83c2011-01-17 08:03:18 +00002386 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
Evan Cheng408aa562009-11-06 22:24:13 +00002387 // Initial exec model.
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002388 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2389 ARMConstantPoolValue *CPV =
Bill Wendling7753d662011-10-01 08:00:54 +00002390 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2391 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2392 true);
Evan Cheng1fb8aed2009-03-13 07:51:59 +00002393 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson9f944592009-08-11 20:47:22 +00002394 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Evan Chengcdbb70c2009-10-31 03:39:36 +00002395 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
Chris Lattner7727d052010-09-21 06:44:06 +00002396 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002397 false, false, false, 0);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002398 Chain = Offset.getValue(1);
2399
Evan Cheng408aa562009-11-06 22:24:13 +00002400 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Dale Johannesen021052a2009-02-04 20:06:27 +00002401 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002402
Evan Chengcdbb70c2009-10-31 03:39:36 +00002403 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
Chris Lattner7727d052010-09-21 06:44:06 +00002404 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002405 false, false, false, 0);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002406 } else {
2407 // local exec model
Hans Wennborgaea41202012-05-04 09:40:39 +00002408 assert(model == TLSModel::LocalExec);
Bill Wendling7753d662011-10-01 08:00:54 +00002409 ARMConstantPoolValue *CPV =
2410 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
Evan Cheng1fb8aed2009-03-13 07:51:59 +00002411 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson9f944592009-08-11 20:47:22 +00002412 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Evan Chengcdbb70c2009-10-31 03:39:36 +00002413 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
Chris Lattner7727d052010-09-21 06:44:06 +00002414 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002415 false, false, false, 0);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002416 }
2417
2418 // The address of the thread local variable is the add of the thread
2419 // pointer with the offset of the variable.
Dale Johannesen021052a2009-02-04 20:06:27 +00002420 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002421}
2422
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002423SDValue
Dan Gohman21cea8a2010-04-17 15:26:15 +00002424ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002425 // TODO: implement the "local dynamic" model
2426 assert(Subtarget->isTargetELF() &&
2427 "TLS not implemented for non-ELF targets");
2428 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
Hans Wennborgaea41202012-05-04 09:40:39 +00002429
2430 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2431
2432 switch (model) {
2433 case TLSModel::GeneralDynamic:
2434 case TLSModel::LocalDynamic:
2435 return LowerToTLSGeneralDynamicModel(GA, DAG);
2436 case TLSModel::InitialExec:
2437 case TLSModel::LocalExec:
2438 return LowerToTLSExecModels(GA, DAG, model);
2439 }
Matt Beaumont-Gaye82ab6b2012-05-04 18:34:27 +00002440 llvm_unreachable("bogus TLS model");
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +00002441}
2442
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002443SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
Dan Gohman21cea8a2010-04-17 15:26:15 +00002444 SelectionDAG &DAG) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00002445 EVT PtrVT = getPointerTy();
Andrew Trickef9de2a2013-05-25 02:42:55 +00002446 SDLoc dl(Op);
Dan Gohmanbcaf6812010-04-15 01:51:59 +00002447 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Chad Rosier537ff502013-02-28 19:16:42 +00002448 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
Rafael Espindola6de96a12009-01-15 20:18:42 +00002449 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00002450 ARMConstantPoolValue *CPV =
Bill Wendling7753d662011-10-01 08:00:54 +00002451 ARMConstantPoolConstant::Create(GV,
2452 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
Evan Cheng1fb8aed2009-03-13 07:51:59 +00002453 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson9f944592009-08-11 20:47:22 +00002454 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Bob Wilson7117a912009-03-20 22:42:55 +00002455 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
Anton Korobeynikov75b59fb2009-10-07 00:06:35 +00002456 CPAddr,
Chris Lattner7727d052010-09-21 06:44:06 +00002457 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002458 false, false, false, 0);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002459 SDValue Chain = Result.getValue(1);
Dale Johannesen62fd95d2009-02-07 00:55:49 +00002460 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
Dale Johannesen021052a2009-02-04 20:06:27 +00002461 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00002462 if (!UseGOTOFF)
Anton Korobeynikov75b59fb2009-10-07 00:06:35 +00002463 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
Pete Cooper82cd9e82011-11-08 18:42:53 +00002464 MachinePointerInfo::getGOT(),
2465 false, false, false, 0);
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00002466 return Result;
Evan Chengdfce83c2011-01-17 08:03:18 +00002467 }
2468
2469 // If we have T2 ops, we can materialize the address directly via movt/movw
James Molloydd9137a2011-10-26 08:53:19 +00002470 // pair. This is always cheaper.
Eric Christopherc1058df2014-07-04 01:55:26 +00002471 if (Subtarget->useMovt(DAG.getMachineFunction())) {
Evan Cheng68aec142011-01-19 02:16:49 +00002472 ++NumMovwMovt;
Evan Chengdfce83c2011-01-17 08:03:18 +00002473 // FIXME: Once remat is capable of dealing with instructions with register
2474 // operands, expand this into two nodes.
2475 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2476 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00002477 } else {
Evan Chengdfce83c2011-01-17 08:03:18 +00002478 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2479 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2480 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2481 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002482 false, false, false, 0);
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00002483 }
2484}
2485
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002486SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
Dan Gohman21cea8a2010-04-17 15:26:15 +00002487 SelectionDAG &DAG) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00002488 EVT PtrVT = getPointerTy();
Andrew Trickef9de2a2013-05-25 02:42:55 +00002489 SDLoc dl(Op);
Dan Gohmanbcaf6812010-04-15 01:51:59 +00002490 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Evan Cheng10043e22007-01-19 07:51:42 +00002491 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
Evan Chengdfce83c2011-01-17 08:03:18 +00002492
Eric Christopherc1058df2014-07-04 01:55:26 +00002493 if (Subtarget->useMovt(DAG.getMachineFunction()))
Evan Cheng68aec142011-01-19 02:16:49 +00002494 ++NumMovwMovt;
Evan Chengdfce83c2011-01-17 08:03:18 +00002495
Tim Northover72360d22013-12-02 10:35:41 +00002496 // FIXME: Once remat is capable of dealing with instructions with register
2497 // operands, expand this into multiple nodes
2498 unsigned Wrapper =
2499 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
Tim Northoverdb962e2c2013-11-25 16:24:52 +00002500
Tim Northover72360d22013-12-02 10:35:41 +00002501 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2502 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
Evan Cheng43b9ca62009-08-28 23:18:09 +00002503
Evan Cheng1b389522009-09-03 07:04:02 +00002504 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
Tim Northover72360d22013-12-02 10:35:41 +00002505 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2506 MachinePointerInfo::getGOT(), false, false, false, 0);
Evan Cheng10043e22007-01-19 07:51:42 +00002507 return Result;
2508}
2509
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +00002510SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2511 SelectionDAG &DAG) const {
2512 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
Eric Christopherc1058df2014-07-04 01:55:26 +00002513 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2514 "Windows on ARM expects to use movw/movt");
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +00002515
2516 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Saleem Abdulrasool763f9a52014-07-07 05:18:35 +00002517 const ARMII::TOF TargetFlags =
2518 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +00002519 EVT PtrVT = getPointerTy();
Saleem Abdulrasool763f9a52014-07-07 05:18:35 +00002520 SDValue Result;
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +00002521 SDLoc DL(Op);
2522
2523 ++NumMovwMovt;
2524
2525 // FIXME: Once remat is capable of dealing with instructions with register
2526 // operands, expand this into two nodes.
Saleem Abdulrasool763f9a52014-07-07 05:18:35 +00002527 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2528 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2529 TargetFlags));
2530 if (GV->hasDLLImportStorageClass())
2531 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2532 MachinePointerInfo::getGOT(), false, false, false, 0);
2533 return Result;
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +00002534}
2535
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002536SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
Dan Gohman21cea8a2010-04-17 15:26:15 +00002537 SelectionDAG &DAG) const {
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00002538 assert(Subtarget->isTargetELF() &&
2539 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
Evan Cheng408aa562009-11-06 22:24:13 +00002540 MachineFunction &MF = DAG.getMachineFunction();
2541 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Evan Chengdfce83c2011-01-17 08:03:18 +00002542 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
Owen Anderson53aa7a92009-08-10 22:56:29 +00002543 EVT PtrVT = getPointerTy();
Andrew Trickef9de2a2013-05-25 02:42:55 +00002544 SDLoc dl(Op);
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00002545 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
Bill Wendlingc214cb02011-10-01 08:58:29 +00002546 ARMConstantPoolValue *CPV =
2547 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2548 ARMPCLabelIndex, PCAdj);
Evan Cheng1fb8aed2009-03-13 07:51:59 +00002549 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson9f944592009-08-11 20:47:22 +00002550 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Anton Korobeynikov75b59fb2009-10-07 00:06:35 +00002551 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
Chris Lattner7727d052010-09-21 06:44:06 +00002552 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002553 false, false, false, 0);
Evan Cheng408aa562009-11-06 22:24:13 +00002554 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Dale Johannesen021052a2009-02-04 20:06:27 +00002555 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00002556}
2557
Jim Grosbachaeca45d2009-05-12 23:59:14 +00002558SDValue
Jim Grosbachc98892f2010-05-26 20:22:18 +00002559ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00002560 SDLoc dl(Op);
Jim Grosbachfaa3abb2010-05-27 23:49:24 +00002561 SDValue Val = DAG.getConstant(0, MVT::i32);
Bill Wendling7ecfbd92011-10-07 21:25:38 +00002562 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2563 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
Jim Grosbachc98892f2010-05-26 20:22:18 +00002564 Op.getOperand(1), Val);
2565}
2566
2567SDValue
Jim Grosbachbd9485d2010-05-22 01:06:18 +00002568ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00002569 SDLoc dl(Op);
Jim Grosbachbd9485d2010-05-22 01:06:18 +00002570 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2571 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2572}
2573
2574SDValue
Jim Grosbacha570d052010-02-08 23:22:00 +00002575ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Jim Grosbache3864cc2010-06-16 23:45:49 +00002576 const ARMSubtarget *Subtarget) const {
Dan Gohmaneffb8942008-09-12 16:56:44 +00002577 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Andrew Trickef9de2a2013-05-25 02:42:55 +00002578 SDLoc dl(Op);
Lauro Ramos Venanciof6a67bf2007-11-08 17:20:05 +00002579 switch (IntNo) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002580 default: return SDValue(); // Don't custom lower most intrinsics.
Jim Grosbach07393ba2014-06-16 21:55:30 +00002581 case Intrinsic::arm_rbit: {
2582 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2583 "RBIT intrinsic must have i32 type!");
2584 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(0));
2585 }
Bob Wilson17f88782009-08-04 00:25:01 +00002586 case Intrinsic::arm_thread_pointer: {
Owen Anderson53aa7a92009-08-10 22:56:29 +00002587 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Bob Wilson17f88782009-08-04 00:25:01 +00002588 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2589 }
Jim Grosbach693e36a2009-08-11 00:09:57 +00002590 case Intrinsic::eh_sjlj_lsda: {
Jim Grosbach693e36a2009-08-11 00:09:57 +00002591 MachineFunction &MF = DAG.getMachineFunction();
Evan Cheng408aa562009-11-06 22:24:13 +00002592 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Evan Chengdfce83c2011-01-17 08:03:18 +00002593 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
Jim Grosbach693e36a2009-08-11 00:09:57 +00002594 EVT PtrVT = getPointerTy();
Jim Grosbach693e36a2009-08-11 00:09:57 +00002595 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2596 SDValue CPAddr;
2597 unsigned PCAdj = (RelocM != Reloc::PIC_)
2598 ? 0 : (Subtarget->isThumb() ? 4 : 8);
Jim Grosbach693e36a2009-08-11 00:09:57 +00002599 ARMConstantPoolValue *CPV =
Bill Wendling7753d662011-10-01 08:00:54 +00002600 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2601 ARMCP::CPLSDA, PCAdj);
Jim Grosbach693e36a2009-08-11 00:09:57 +00002602 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson9f944592009-08-11 20:47:22 +00002603 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Jim Grosbach693e36a2009-08-11 00:09:57 +00002604 SDValue Result =
Evan Chengcdbb70c2009-10-31 03:39:36 +00002605 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
Chris Lattner7727d052010-09-21 06:44:06 +00002606 MachinePointerInfo::getConstantPool(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002607 false, false, false, 0);
Jim Grosbach693e36a2009-08-11 00:09:57 +00002608
2609 if (RelocM == Reloc::PIC_) {
Evan Cheng408aa562009-11-06 22:24:13 +00002610 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Jim Grosbach693e36a2009-08-11 00:09:57 +00002611 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2612 }
2613 return Result;
2614 }
Evan Cheng18381b42011-03-29 23:06:19 +00002615 case Intrinsic::arm_neon_vmulls:
2616 case Intrinsic::arm_neon_vmullu: {
2617 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2618 ? ARMISD::VMULLs : ARMISD::VMULLu;
Andrew Trickef9de2a2013-05-25 02:42:55 +00002619 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
Evan Cheng18381b42011-03-29 23:06:19 +00002620 Op.getOperand(1), Op.getOperand(2));
2621 }
Lauro Ramos Venanciof6a67bf2007-11-08 17:20:05 +00002622 }
2623}
2624
Eli Friedman30a49e92011-08-03 21:06:02 +00002625static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2626 const ARMSubtarget *Subtarget) {
2627 // FIXME: handle "fence singlethread" more efficiently.
Andrew Trickef9de2a2013-05-25 02:42:55 +00002628 SDLoc dl(Op);
Eli Friedman26a48482011-07-27 22:21:52 +00002629 if (!Subtarget->hasDataBarrier()) {
2630 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2631 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2632 // here.
2633 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
Tim Northoverc7ea8042013-10-25 09:30:24 +00002634 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
Eli Friedman30a49e92011-08-03 21:06:02 +00002635 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
Eli Friedman26a48482011-07-27 22:21:52 +00002636 DAG.getConstant(0, MVT::i32));
2637 }
2638
Tim Northover36b24172013-07-03 09:20:36 +00002639 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2640 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2641 unsigned Domain = ARM_MB::ISH;
Tim Northoverf5769882013-08-28 14:39:19 +00002642 if (Subtarget->isMClass()) {
2643 // Only a full system barrier exists in the M-class architectures.
2644 Domain = ARM_MB::SY;
2645 } else if (Subtarget->isSwift() && Ord == Release) {
Tim Northover36b24172013-07-03 09:20:36 +00002646 // Swift happens to implement ISHST barriers in a way that's compatible with
2647 // Release semantics but weaker than ISH so we'd be fools not to use
2648 // it. Beware: other processors probably don't!
2649 Domain = ARM_MB::ISHST;
2650 }
2651
Joey Gouly926d3f52013-09-05 15:35:24 +00002652 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2653 DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
Tim Northover36b24172013-07-03 09:20:36 +00002654 DAG.getConstant(Domain, MVT::i32));
Eli Friedman26a48482011-07-27 22:21:52 +00002655}
2656
Evan Cheng8740ee32010-11-03 06:34:55 +00002657static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2658 const ARMSubtarget *Subtarget) {
2659 // ARM pre v5TE and Thumb1 does not have preload instructions.
2660 if (!(Subtarget->isThumb2() ||
2661 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2662 // Just preserve the chain.
2663 return Op.getOperand(0);
2664
Andrew Trickef9de2a2013-05-25 02:42:55 +00002665 SDLoc dl(Op);
Evan Cheng21acf9f2010-11-04 05:19:35 +00002666 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2667 if (!isRead &&
2668 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2669 // ARMv7 with MP extension has PLDW.
2670 return Op.getOperand(0);
Evan Cheng8740ee32010-11-03 06:34:55 +00002671
Bruno Cardoso Lopesdc9ff3a2011-06-14 04:58:37 +00002672 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2673 if (Subtarget->isThumb()) {
Evan Cheng8740ee32010-11-03 06:34:55 +00002674 // Invert the bits.
Evan Cheng21acf9f2010-11-04 05:19:35 +00002675 isRead = ~isRead & 1;
Bruno Cardoso Lopesdc9ff3a2011-06-14 04:58:37 +00002676 isData = ~isData & 1;
2677 }
Evan Cheng8740ee32010-11-03 06:34:55 +00002678
2679 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
Evan Cheng21acf9f2010-11-04 05:19:35 +00002680 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2681 DAG.getConstant(isData, MVT::i32));
Evan Cheng8740ee32010-11-03 06:34:55 +00002682}
2683
Dan Gohman31ae5862010-04-17 14:41:14 +00002684static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2685 MachineFunction &MF = DAG.getMachineFunction();
2686 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2687
Evan Cheng10043e22007-01-19 07:51:42 +00002688 // vastart just stores the address of the VarArgsFrameIndex slot into the
2689 // memory location argument.
Andrew Trickef9de2a2013-05-25 02:42:55 +00002690 SDLoc dl(Op);
Owen Anderson53aa7a92009-08-10 22:56:29 +00002691 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Dan Gohman31ae5862010-04-17 14:41:14 +00002692 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
Dan Gohman2d489b52008-02-06 22:27:42 +00002693 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner886250c2010-09-21 18:51:21 +00002694 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2695 MachinePointerInfo(SV), false, false, 0);
Evan Cheng10043e22007-01-19 07:51:42 +00002696}
2697
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002698SDValue
Bob Wilson2e076c42009-06-22 23:27:02 +00002699ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2700 SDValue &Root, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002701 SDLoc dl) const {
Bob Wilson2e076c42009-06-22 23:27:02 +00002702 MachineFunction &MF = DAG.getMachineFunction();
2703 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2704
Craig Topper760b1342012-02-22 05:59:10 +00002705 const TargetRegisterClass *RC;
David Goodwin22c2fba2009-07-08 23:10:31 +00002706 if (AFI->isThumb1OnlyFunction())
Craig Topperc7242e02012-04-20 07:30:17 +00002707 RC = &ARM::tGPRRegClass;
Bob Wilson2e076c42009-06-22 23:27:02 +00002708 else
Craig Topperc7242e02012-04-20 07:30:17 +00002709 RC = &ARM::GPRRegClass;
Bob Wilson2e076c42009-06-22 23:27:02 +00002710
2711 // Transform the arguments stored in physical registers into virtual ones.
Devang Patelf3292b22011-02-21 23:21:26 +00002712 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
Owen Anderson9f944592009-08-11 20:47:22 +00002713 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
Bob Wilson2e076c42009-06-22 23:27:02 +00002714
2715 SDValue ArgValue2;
2716 if (NextVA.isMemLoc()) {
Bob Wilson2e076c42009-06-22 23:27:02 +00002717 MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng0664a672010-07-03 00:40:23 +00002718 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
Bob Wilson2e076c42009-06-22 23:27:02 +00002719
2720 // Create load node to retrieve arguments from the stack.
2721 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
Evan Chengcdbb70c2009-10-31 03:39:36 +00002722 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
Chris Lattner7727d052010-09-21 06:44:06 +00002723 MachinePointerInfo::getFixedStack(FI),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002724 false, false, false, 0);
Bob Wilson2e076c42009-06-22 23:27:02 +00002725 } else {
Devang Patelf3292b22011-02-21 23:21:26 +00002726 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
Owen Anderson9f944592009-08-11 20:47:22 +00002727 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
Bob Wilson2e076c42009-06-22 23:27:02 +00002728 }
Christian Pirkerb5728192014-05-08 14:06:24 +00002729 if (!Subtarget->isLittle())
2730 std::swap (ArgValue, ArgValue2);
Jim Grosbachd7cf55c2009-11-09 00:11:35 +00002731 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
Bob Wilson2e076c42009-06-22 23:27:02 +00002732}
2733
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002734void
2735ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002736 unsigned InRegsParamRecordIdx,
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002737 unsigned ArgSize,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002738 unsigned &ArgRegsSize,
2739 unsigned &ArgRegsSaveSize)
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002740 const {
2741 unsigned NumGPRs;
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002742 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2743 unsigned RBegin, REnd;
2744 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2745 NumGPRs = REnd - RBegin;
2746 } else {
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002747 unsigned int firstUnalloced;
2748 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2749 sizeof(GPRArgRegs) /
2750 sizeof(GPRArgRegs[0]));
2751 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2752 }
2753
2754 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002755 ArgRegsSize = NumGPRs * 4;
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002756
2757 // If parameter is split between stack and GPRs...
Mark Seabornbe266aa2014-02-16 18:59:48 +00002758 if (NumGPRs && Align > 4 &&
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002759 (ArgRegsSize < ArgSize ||
2760 InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
Mark Seabornbe266aa2014-02-16 18:59:48 +00002761 // Add padding for part of param recovered from GPRs. For example,
2762 // if Align == 8, its last byte must be at address K*8 - 1.
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002763 // We need to do it, since remained (stack) part of parameter has
2764 // stack alignment, and we need to "attach" "GPRs head" without gaps
2765 // to it:
2766 // Stack:
2767 // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2768 // [ [padding] [GPRs head] ] [ Tail passed via stack ....
2769 //
2770 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2771 unsigned Padding =
Mark Seabornbe266aa2014-02-16 18:59:48 +00002772 OffsetToAlignment(ArgRegsSize + AFI->getArgRegsSaveSize(), Align);
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002773 ArgRegsSaveSize = ArgRegsSize + Padding;
2774 } else
2775 // We don't need to extend regs save size for byval parameters if they
2776 // are passed via GPRs only.
2777 ArgRegsSaveSize = ArgRegsSize;
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002778}
2779
2780// The remaining GPRs hold either the beginning of variable-argument
David Peixotto4299cf82013-02-13 00:36:35 +00002781// data, or the beginning of an aggregate passed by value (usually
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002782// byval). Either way, we allocate stack slots adjacent to the data
2783// provided by our caller, and store the unallocated registers there.
2784// If this is a variadic function, the va_list pointer will begin with
2785// these values; otherwise, this reassembles a (byval) structure that
2786// was split between registers and memory.
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002787// Return: The frame index registers were stored into.
2788int
2789ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002790 SDLoc dl, SDValue &Chain,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002791 const Value *OrigArg,
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002792 unsigned InRegsParamRecordIdx,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002793 unsigned OffsetFromOrigArg,
2794 unsigned ArgOffset,
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002795 unsigned ArgSize,
Oliver Stannardd55e1152014-03-05 15:25:27 +00002796 bool ForceMutable,
2797 unsigned ByValStoreOffset,
2798 unsigned TotalArgRegsSaveSize) const {
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002799
2800 // Currently, two use-cases possible:
Alp Tokerf907b892013-12-05 05:44:44 +00002801 // Case #1. Non-var-args function, and we meet first byval parameter.
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002802 // Setup first unallocated register as first byval register;
2803 // eat all remained registers
2804 // (these two actions are performed by HandleByVal method).
2805 // Then, here, we initialize stack frame with
2806 // "store-reg" instructions.
2807 // Case #2. Var-args function, that doesn't contain byval parameters.
2808 // The same: eat all remained unallocated registers,
2809 // initialize stack frame.
2810
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002811 MachineFunction &MF = DAG.getMachineFunction();
2812 MachineFrameInfo *MFI = MF.getFrameInfo();
2813 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002814 unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2815 unsigned RBegin, REnd;
2816 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2817 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2818 firstRegToSaveIndex = RBegin - ARM::R0;
2819 lastRegToSaveIndex = REnd - ARM::R0;
2820 } else {
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002821 firstRegToSaveIndex = CCInfo.getFirstUnallocated
Craig Topper58713212013-07-15 04:27:47 +00002822 (GPRArgRegs, array_lengthof(GPRArgRegs));
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002823 lastRegToSaveIndex = 4;
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002824 }
2825
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002826 unsigned ArgRegsSize, ArgRegsSaveSize;
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002827 computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2828 ArgRegsSize, ArgRegsSaveSize);
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002829
2830 // Store any by-val regs to their spots on the stack so that they may be
2831 // loaded by deferencing the result of formal parameter pointer or va_next.
2832 // Note: once stack area for byval/varargs registers
2833 // was initialized, it can't be initialized again.
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002834 if (ArgRegsSaveSize) {
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002835 unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2836
2837 if (Padding) {
2838 assert(AFI->getStoredByValParamsPadding() == 0 &&
2839 "The only parameter may be padded.");
2840 AFI->setStoredByValParamsPadding(Padding);
2841 }
2842
Oliver Stannardd55e1152014-03-05 15:25:27 +00002843 int FrameIndex = MFI->CreateFixedObject(ArgRegsSaveSize,
2844 Padding +
2845 ByValStoreOffset -
2846 (int64_t)TotalArgRegsSaveSize,
2847 false);
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002848 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
Oliver Stannardd55e1152014-03-05 15:25:27 +00002849 if (Padding) {
2850 MFI->CreateFixedObject(Padding,
2851 ArgOffset + ByValStoreOffset -
2852 (int64_t)ArgRegsSaveSize,
2853 false);
2854 }
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002855
2856 SmallVector<SDValue, 4> MemOps;
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002857 for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2858 ++firstRegToSaveIndex, ++i) {
Craig Topper760b1342012-02-22 05:59:10 +00002859 const TargetRegisterClass *RC;
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002860 if (AFI->isThumb1OnlyFunction())
Craig Topperc7242e02012-04-20 07:30:17 +00002861 RC = &ARM::tGPRRegClass;
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002862 else
Craig Topperc7242e02012-04-20 07:30:17 +00002863 RC = &ARM::GPRRegClass;
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002864
2865 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2866 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2867 SDValue Store =
2868 DAG.getStore(Val.getValue(1), dl, Val, FIN,
Stepan Dyatkovskiyf13dbb82012-10-10 11:37:36 +00002869 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002870 false, false, 0);
2871 MemOps.push_back(Store);
2872 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2873 DAG.getConstant(4, getPointerTy()));
2874 }
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002875
2876 AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2877
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002878 if (!MemOps.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00002879 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002880 return FrameIndex;
Oliver Stannardd55e1152014-03-05 15:25:27 +00002881 } else {
2882 if (ArgSize == 0) {
2883 // We cannot allocate a zero-byte object for the first variadic argument,
2884 // so just make up a size.
2885 ArgSize = 4;
2886 }
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002887 // This will point to the next argument passed via stack.
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00002888 return MFI->CreateFixedObject(
Oliver Stannardd55e1152014-03-05 15:25:27 +00002889 ArgSize, ArgOffset, !ForceMutable);
2890 }
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002891}
2892
2893// Setup stack frame, the va_list pointer will start from.
2894void
2895ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002896 SDLoc dl, SDValue &Chain,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002897 unsigned ArgOffset,
Oliver Stannardd55e1152014-03-05 15:25:27 +00002898 unsigned TotalArgRegsSaveSize,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002899 bool ForceMutable) const {
2900 MachineFunction &MF = DAG.getMachineFunction();
2901 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2902
2903 // Try to store any remaining integer argument regs
2904 // to their spots on the stack so that they may be loaded by deferencing
2905 // the result of va_next.
2906 // If there is no regs to be stored, just point address after last
2907 // argument passed via stack.
2908 int FrameIndex =
Craig Topper062a2ba2014-04-25 05:30:21 +00002909 StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
2910 CCInfo.getInRegsParamsCount(), 0, ArgOffset, 0, ForceMutable,
2911 0, TotalArgRegsSaveSize);
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00002912
2913 AFI->setVarArgsFrameIndex(FrameIndex);
Stuart Hastings45fe3c32011-04-20 16:47:52 +00002914}
2915
Bob Wilson2e076c42009-06-22 23:27:02 +00002916SDValue
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002917ARMTargetLowering::LowerFormalArguments(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +00002918 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002919 const SmallVectorImpl<ISD::InputArg>
2920 &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002921 SDLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00002922 SmallVectorImpl<SDValue> &InVals)
2923 const {
Bob Wilsona4c22902009-04-17 19:07:39 +00002924 MachineFunction &MF = DAG.getMachineFunction();
2925 MachineFrameInfo *MFI = MF.getFrameInfo();
2926
Bob Wilsona4c22902009-04-17 19:07:39 +00002927 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2928
2929 // Assign locations to all of the incoming arguments.
2930 SmallVector<CCValAssign, 16> ArgLocs;
Cameron Zwarich89019782011-06-10 20:59:24 +00002931 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2932 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002933 CCInfo.AnalyzeFormalArguments(Ins,
Anton Korobeynikov22ef7512009-08-05 19:04:42 +00002934 CCAssignFnForNode(CallConv, /* Return*/ false,
2935 isVarArg));
Jim Grosbach54efea02013-03-02 20:16:15 +00002936
Bob Wilsona4c22902009-04-17 19:07:39 +00002937 SmallVector<SDValue, 16> ArgValues;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00002938 int lastInsIndex = -1;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00002939 SDValue ArgValue;
Stepan Dyatkovskiyf13dbb82012-10-10 11:37:36 +00002940 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2941 unsigned CurArgIdx = 0;
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00002942
2943 // Initially ArgRegsSaveSize is zero.
2944 // Then we increase this value each time we meet byval parameter.
2945 // We also increase this value in case of varargs function.
2946 AFI->setArgRegsSaveSize(0);
2947
Oliver Stannardd55e1152014-03-05 15:25:27 +00002948 unsigned ByValStoreOffset = 0;
2949 unsigned TotalArgRegsSaveSize = 0;
2950 unsigned ArgRegsSaveSizeMaxAlign = 4;
2951
2952 // Calculate the amount of stack space that we need to allocate to store
2953 // byval and variadic arguments that are passed in registers.
2954 // We need to know this before we allocate the first byval or variadic
2955 // argument, as they will be allocated a stack slot below the CFA (Canonical
2956 // Frame Address, the stack pointer at entry to the function).
2957 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2958 CCValAssign &VA = ArgLocs[i];
2959 if (VA.isMemLoc()) {
2960 int index = VA.getValNo();
2961 if (index != lastInsIndex) {
2962 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2963 if (Flags.isByVal()) {
2964 unsigned ExtraArgRegsSize;
2965 unsigned ExtraArgRegsSaveSize;
2966 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProceed(),
2967 Flags.getByValSize(),
2968 ExtraArgRegsSize, ExtraArgRegsSaveSize);
2969
2970 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
2971 if (Flags.getByValAlign() > ArgRegsSaveSizeMaxAlign)
2972 ArgRegsSaveSizeMaxAlign = Flags.getByValAlign();
2973 CCInfo.nextInRegsParam();
2974 }
2975 lastInsIndex = index;
2976 }
2977 }
2978 }
2979 CCInfo.rewindByValRegsInfo();
2980 lastInsIndex = -1;
2981 if (isVarArg) {
2982 unsigned ExtraArgRegsSize;
2983 unsigned ExtraArgRegsSaveSize;
2984 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsCount(), 0,
2985 ExtraArgRegsSize, ExtraArgRegsSaveSize);
2986 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
2987 }
2988 // If the arg regs save area contains N-byte aligned values, the
2989 // bottom of it must be at least N-byte aligned.
2990 TotalArgRegsSaveSize = RoundUpToAlignment(TotalArgRegsSaveSize, ArgRegsSaveSizeMaxAlign);
2991 TotalArgRegsSaveSize = std::min(TotalArgRegsSaveSize, 16U);
2992
Bob Wilsona4c22902009-04-17 19:07:39 +00002993 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2994 CCValAssign &VA = ArgLocs[i];
Stepan Dyatkovskiyf13dbb82012-10-10 11:37:36 +00002995 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2996 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
Bob Wilsonea09d4a2009-04-17 20:35:10 +00002997 // Arguments stored in registers.
Bob Wilsona4c22902009-04-17 19:07:39 +00002998 if (VA.isRegLoc()) {
Owen Anderson53aa7a92009-08-10 22:56:29 +00002999 EVT RegVT = VA.getLocVT();
Bob Wilsona4c22902009-04-17 19:07:39 +00003000
Bob Wilsona4c22902009-04-17 19:07:39 +00003001 if (VA.needsCustom()) {
Bob Wilson2e076c42009-06-22 23:27:02 +00003002 // f64 and vector types are split up into multiple registers or
3003 // combinations of registers and stack slots.
Owen Anderson9f944592009-08-11 20:47:22 +00003004 if (VA.getLocVT() == MVT::v2f64) {
Bob Wilson2e076c42009-06-22 23:27:02 +00003005 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003006 Chain, DAG, dl);
Bob Wilson2e076c42009-06-22 23:27:02 +00003007 VA = ArgLocs[++i]; // skip ahead to next loc
Bob Wilson699bdf72010-04-13 22:03:22 +00003008 SDValue ArgValue2;
3009 if (VA.isMemLoc()) {
Evan Cheng0664a672010-07-03 00:40:23 +00003010 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
Bob Wilson699bdf72010-04-13 22:03:22 +00003011 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3012 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
Chris Lattner7727d052010-09-21 06:44:06 +00003013 MachinePointerInfo::getFixedStack(FI),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003014 false, false, false, 0);
Bob Wilson699bdf72010-04-13 22:03:22 +00003015 } else {
3016 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3017 Chain, DAG, dl);
3018 }
Owen Anderson9f944592009-08-11 20:47:22 +00003019 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3020 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
Bob Wilson2e076c42009-06-22 23:27:02 +00003021 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
Owen Anderson9f944592009-08-11 20:47:22 +00003022 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
Bob Wilson2e076c42009-06-22 23:27:02 +00003023 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
3024 } else
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003025 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
Bob Wilsona4c22902009-04-17 19:07:39 +00003026
Bob Wilson2e076c42009-06-22 23:27:02 +00003027 } else {
Craig Topper760b1342012-02-22 05:59:10 +00003028 const TargetRegisterClass *RC;
Anton Korobeynikov22ef7512009-08-05 19:04:42 +00003029
Owen Anderson9f944592009-08-11 20:47:22 +00003030 if (RegVT == MVT::f32)
Craig Topperc7242e02012-04-20 07:30:17 +00003031 RC = &ARM::SPRRegClass;
Owen Anderson9f944592009-08-11 20:47:22 +00003032 else if (RegVT == MVT::f64)
Craig Topperc7242e02012-04-20 07:30:17 +00003033 RC = &ARM::DPRRegClass;
Owen Anderson9f944592009-08-11 20:47:22 +00003034 else if (RegVT == MVT::v2f64)
Craig Topperc7242e02012-04-20 07:30:17 +00003035 RC = &ARM::QPRRegClass;
Owen Anderson9f944592009-08-11 20:47:22 +00003036 else if (RegVT == MVT::i32)
Craig Topperc7242e02012-04-20 07:30:17 +00003037 RC = AFI->isThumb1OnlyFunction() ?
3038 (const TargetRegisterClass*)&ARM::tGPRRegClass :
3039 (const TargetRegisterClass*)&ARM::GPRRegClass;
Bob Wilson2e076c42009-06-22 23:27:02 +00003040 else
Anton Korobeynikovef98dbe2009-08-05 20:15:19 +00003041 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
Bob Wilson2e076c42009-06-22 23:27:02 +00003042
3043 // Transform the arguments in physical registers into virtual ones.
Devang Patelf3292b22011-02-21 23:21:26 +00003044 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003045 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Bob Wilsona4c22902009-04-17 19:07:39 +00003046 }
3047
3048 // If this is an 8 or 16-bit value, it is really passed promoted
3049 // to 32 bits. Insert an assert[sz]ext to capture this, then
3050 // truncate to the right size.
3051 switch (VA.getLocInfo()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00003052 default: llvm_unreachable("Unknown loc info!");
Bob Wilsona4c22902009-04-17 19:07:39 +00003053 case CCValAssign::Full: break;
3054 case CCValAssign::BCvt:
Wesley Peck527da1b2010-11-23 03:31:01 +00003055 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
Bob Wilsona4c22902009-04-17 19:07:39 +00003056 break;
3057 case CCValAssign::SExt:
3058 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3059 DAG.getValueType(VA.getValVT()));
3060 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3061 break;
3062 case CCValAssign::ZExt:
3063 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3064 DAG.getValueType(VA.getValVT()));
3065 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3066 break;
3067 }
3068
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003069 InVals.push_back(ArgValue);
Bob Wilsona4c22902009-04-17 19:07:39 +00003070
3071 } else { // VA.isRegLoc()
3072
3073 // sanity check
3074 assert(VA.isMemLoc());
Owen Anderson9f944592009-08-11 20:47:22 +00003075 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
Bob Wilsona4c22902009-04-17 19:07:39 +00003076
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00003077 int index = ArgLocs[i].getValNo();
Owen Anderson77aa2662011-04-05 21:48:57 +00003078
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00003079 // Some Ins[] entries become multiple ArgLoc[] entries.
3080 // Process them only once.
3081 if (index != lastInsIndex)
3082 {
3083 ISD::ArgFlagsTy Flags = Ins[index].Flags;
Eric Christopher0713a9d2011-06-08 23:55:35 +00003084 // FIXME: For now, all byval parameter objects are marked mutable.
Eric Christophere02e07c2011-04-29 23:12:01 +00003085 // This can be changed with more analysis.
3086 // In case of tail call optimization mark all arguments mutable.
3087 // Since they could be overwritten by lowering of arguments in case of
3088 // a tail call.
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00003089 if (Flags.isByVal()) {
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00003090 unsigned CurByValIndex = CCInfo.getInRegsParamsProceed();
Oliver Stannardd55e1152014-03-05 15:25:27 +00003091
3092 ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign());
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00003093 int FrameIndex = StoreByValRegs(
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00003094 CCInfo, DAG, dl, Chain, CurOrigArg,
3095 CurByValIndex,
3096 Ins[VA.getValNo()].PartOffset,
3097 VA.getLocMemOffset(),
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00003098 Flags.getByValSize(),
Oliver Stannardd55e1152014-03-05 15:25:27 +00003099 true /*force mutable frames*/,
3100 ByValStoreOffset,
3101 TotalArgRegsSaveSize);
3102 ByValStoreOffset += Flags.getByValSize();
3103 ByValStoreOffset = std::min(ByValStoreOffset, 16U);
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00003104 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +00003105 CCInfo.nextInRegsParam();
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00003106 } else {
Oliver Stannardd55e1152014-03-05 15:25:27 +00003107 unsigned FIOffset = VA.getLocMemOffset();
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00003108 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
Stepan Dyatkovskiyd0e34a22013-05-20 08:01:34 +00003109 FIOffset, true);
Bob Wilsona4c22902009-04-17 19:07:39 +00003110
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00003111 // Create load nodes to retrieve arguments from the stack.
3112 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3113 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3114 MachinePointerInfo::getFixedStack(FI),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003115 false, false, false, 0));
Stuart Hastings67c5c3e2011-02-28 17:17:53 +00003116 }
3117 lastInsIndex = index;
3118 }
Bob Wilsona4c22902009-04-17 19:07:39 +00003119 }
3120 }
3121
3122 // varargs
Stuart Hastings45fe3c32011-04-20 16:47:52 +00003123 if (isVarArg)
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +00003124 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
Oliver Stannardd55e1152014-03-05 15:25:27 +00003125 CCInfo.getNextStackOffset(),
3126 TotalArgRegsSaveSize);
Evan Cheng10043e22007-01-19 07:51:42 +00003127
Oliver Stannardb14c6252014-04-02 16:10:33 +00003128 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3129
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003130 return Chain;
Evan Cheng10043e22007-01-19 07:51:42 +00003131}
3132
3133/// isFloatingPointZero - Return true if this is +0.0.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003134static bool isFloatingPointZero(SDValue Op) {
Evan Cheng10043e22007-01-19 07:51:42 +00003135 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
Dale Johannesen3cf889f2007-08-31 04:03:46 +00003136 return CFP->getValueAPF().isPosZero();
Gabor Greiff304a7a2008-08-28 21:40:38 +00003137 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
Evan Cheng10043e22007-01-19 07:51:42 +00003138 // Maybe this has already been legalized into the constant pool?
3139 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003140 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
Evan Cheng10043e22007-01-19 07:51:42 +00003141 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
Dan Gohmanbcaf6812010-04-15 01:51:59 +00003142 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
Dale Johannesen3cf889f2007-08-31 04:03:46 +00003143 return CFP->getValueAPF().isPosZero();
Evan Cheng10043e22007-01-19 07:51:42 +00003144 }
3145 }
3146 return false;
3147}
3148
Evan Cheng10043e22007-01-19 07:51:42 +00003149/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3150/// the given operands.
Evan Cheng15b80e42009-11-12 07:13:11 +00003151SDValue
3152ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003153 SDValue &ARMcc, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003154 SDLoc dl) const {
Gabor Greiff304a7a2008-08-28 21:40:38 +00003155 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
Dan Gohmaneffb8942008-09-12 16:56:44 +00003156 unsigned C = RHSC->getZExtValue();
Evan Cheng15b80e42009-11-12 07:13:11 +00003157 if (!isLegalICmpImmediate(C)) {
Evan Cheng10043e22007-01-19 07:51:42 +00003158 // Constant does not fit, try adjusting it by one?
3159 switch (CC) {
3160 default: break;
3161 case ISD::SETLT:
Evan Cheng10043e22007-01-19 07:51:42 +00003162 case ISD::SETGE:
Daniel Dunbara54a1b02010-08-25 16:58:05 +00003163 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
Evan Cheng48b094d2007-02-02 01:53:26 +00003164 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
Owen Anderson9f944592009-08-11 20:47:22 +00003165 RHS = DAG.getConstant(C-1, MVT::i32);
Evan Cheng48b094d2007-02-02 01:53:26 +00003166 }
3167 break;
3168 case ISD::SETULT:
3169 case ISD::SETUGE:
Daniel Dunbara54a1b02010-08-25 16:58:05 +00003170 if (C != 0 && isLegalICmpImmediate(C-1)) {
Evan Cheng48b094d2007-02-02 01:53:26 +00003171 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
Owen Anderson9f944592009-08-11 20:47:22 +00003172 RHS = DAG.getConstant(C-1, MVT::i32);
Evan Cheng10043e22007-01-19 07:51:42 +00003173 }
3174 break;
3175 case ISD::SETLE:
Evan Cheng10043e22007-01-19 07:51:42 +00003176 case ISD::SETGT:
Daniel Dunbara54a1b02010-08-25 16:58:05 +00003177 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
Evan Cheng48b094d2007-02-02 01:53:26 +00003178 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
Owen Anderson9f944592009-08-11 20:47:22 +00003179 RHS = DAG.getConstant(C+1, MVT::i32);
Evan Cheng48b094d2007-02-02 01:53:26 +00003180 }
3181 break;
3182 case ISD::SETULE:
3183 case ISD::SETUGT:
Daniel Dunbara54a1b02010-08-25 16:58:05 +00003184 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
Evan Cheng48b094d2007-02-02 01:53:26 +00003185 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
Owen Anderson9f944592009-08-11 20:47:22 +00003186 RHS = DAG.getConstant(C+1, MVT::i32);
Evan Cheng10043e22007-01-19 07:51:42 +00003187 }
3188 break;
3189 }
3190 }
3191 }
3192
3193 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
Lauro Ramos Venancio6be85332007-04-02 01:30:03 +00003194 ARMISD::NodeType CompareType;
3195 switch (CondCode) {
3196 default:
3197 CompareType = ARMISD::CMP;
3198 break;
3199 case ARMCC::EQ:
3200 case ARMCC::NE:
David Goodwindbf11ba2009-06-29 15:33:01 +00003201 // Uses only Z Flag
3202 CompareType = ARMISD::CMPZ;
Lauro Ramos Venancio6be85332007-04-02 01:30:03 +00003203 break;
3204 }
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003205 ARMcc = DAG.getConstant(CondCode, MVT::i32);
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003206 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
Evan Cheng10043e22007-01-19 07:51:42 +00003207}
3208
3209/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
Evan Cheng25f93642010-07-08 02:08:50 +00003210SDValue
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003211ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003212 SDLoc dl) const {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003213 SDValue Cmp;
Evan Cheng10043e22007-01-19 07:51:42 +00003214 if (!isFloatingPointZero(RHS))
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003215 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
Evan Cheng10043e22007-01-19 07:51:42 +00003216 else
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003217 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3218 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
Evan Cheng10043e22007-01-19 07:51:42 +00003219}
3220
Bob Wilson45acbd02011-03-08 01:17:20 +00003221/// duplicateCmp - Glue values can have only one use, so this function
3222/// duplicates a comparison node.
3223SDValue
3224ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3225 unsigned Opc = Cmp.getOpcode();
Andrew Trickef9de2a2013-05-25 02:42:55 +00003226 SDLoc DL(Cmp);
Bob Wilson45acbd02011-03-08 01:17:20 +00003227 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3228 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3229
3230 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3231 Cmp = Cmp.getOperand(0);
3232 Opc = Cmp.getOpcode();
3233 if (Opc == ARMISD::CMPFP)
3234 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3235 else {
3236 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3237 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3238 }
3239 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3240}
3241
Louis Gerbarg3342bf12014-05-09 17:02:49 +00003242std::pair<SDValue, SDValue>
3243ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3244 SDValue &ARMcc) const {
3245 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3246
3247 SDValue Value, OverflowCmp;
3248 SDValue LHS = Op.getOperand(0);
3249 SDValue RHS = Op.getOperand(1);
3250
3251
3252 // FIXME: We are currently always generating CMPs because we don't support
3253 // generating CMN through the backend. This is not as good as the natural
3254 // CMP case because it causes a register dependency and cannot be folded
3255 // later.
3256
3257 switch (Op.getOpcode()) {
3258 default:
3259 llvm_unreachable("Unknown overflow instruction!");
3260 case ISD::SADDO:
3261 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3262 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3263 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3264 break;
3265 case ISD::UADDO:
3266 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3267 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3268 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3269 break;
3270 case ISD::SSUBO:
3271 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3272 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3273 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3274 break;
3275 case ISD::USUBO:
3276 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3277 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3278 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3279 break;
3280 } // switch (...)
3281
3282 return std::make_pair(Value, OverflowCmp);
3283}
3284
3285
3286SDValue
3287ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3288 // Let legalize expand this if it isn't a legal type yet.
3289 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3290 return SDValue();
3291
3292 SDValue Value, OverflowCmp;
3293 SDValue ARMcc;
3294 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3295 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3296 // We use 0 and 1 as false and true values.
3297 SDValue TVal = DAG.getConstant(1, MVT::i32);
3298 SDValue FVal = DAG.getConstant(0, MVT::i32);
3299 EVT VT = Op.getValueType();
3300
3301 SDValue Overflow = DAG.getNode(ARMISD::CMOV, SDLoc(Op), VT, TVal, FVal,
3302 ARMcc, CCR, OverflowCmp);
3303
3304 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3305 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
3306}
3307
3308
Bill Wendling6a981312010-08-11 08:43:16 +00003309SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3310 SDValue Cond = Op.getOperand(0);
3311 SDValue SelectTrue = Op.getOperand(1);
3312 SDValue SelectFalse = Op.getOperand(2);
Andrew Trickef9de2a2013-05-25 02:42:55 +00003313 SDLoc dl(Op);
Louis Gerbarg3342bf12014-05-09 17:02:49 +00003314 unsigned Opc = Cond.getOpcode();
3315
3316 if (Cond.getResNo() == 1 &&
3317 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3318 Opc == ISD::USUBO)) {
3319 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3320 return SDValue();
3321
3322 SDValue Value, OverflowCmp;
3323 SDValue ARMcc;
3324 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3325 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3326 EVT VT = Op.getValueType();
3327
3328 return DAG.getNode(ARMISD::CMOV, SDLoc(Op), VT, SelectTrue, SelectFalse,
3329 ARMcc, CCR, OverflowCmp);
3330
3331 }
Bill Wendling6a981312010-08-11 08:43:16 +00003332
3333 // Convert:
3334 //
3335 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3336 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3337 //
3338 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3339 const ConstantSDNode *CMOVTrue =
3340 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3341 const ConstantSDNode *CMOVFalse =
3342 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3343
3344 if (CMOVTrue && CMOVFalse) {
3345 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3346 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3347
3348 SDValue True;
3349 SDValue False;
3350 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3351 True = SelectTrue;
3352 False = SelectFalse;
3353 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3354 True = SelectFalse;
3355 False = SelectTrue;
3356 }
3357
3358 if (True.getNode() && False.getNode()) {
Evan Cheng522fbfe2011-05-18 18:59:17 +00003359 EVT VT = Op.getValueType();
Bill Wendling6a981312010-08-11 08:43:16 +00003360 SDValue ARMcc = Cond.getOperand(2);
3361 SDValue CCR = Cond.getOperand(3);
Bob Wilson45acbd02011-03-08 01:17:20 +00003362 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
Evan Cheng522fbfe2011-05-18 18:59:17 +00003363 assert(True.getValueType() == VT);
3364 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
Bill Wendling6a981312010-08-11 08:43:16 +00003365 }
3366 }
3367 }
3368
Dan Gohmand4a77c42012-02-24 00:09:36 +00003369 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3370 // undefined bits before doing a full-word comparison with zero.
3371 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3372 DAG.getConstant(1, Cond.getValueType()));
3373
Bill Wendling6a981312010-08-11 08:43:16 +00003374 return DAG.getSelectCC(dl, Cond,
3375 DAG.getConstant(0, Cond.getValueType()),
3376 SelectTrue, SelectFalse, ISD::SETNE);
3377}
3378
Joey Gouly881eab52013-08-22 15:29:11 +00003379static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3380 if (CC == ISD::SETNE)
3381 return ISD::SETEQ;
Weiming Zhao63871d22013-12-18 22:25:17 +00003382 return ISD::getSetCCInverse(CC, true);
Joey Gouly881eab52013-08-22 15:29:11 +00003383}
3384
3385static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3386 bool &swpCmpOps, bool &swpVselOps) {
3387 // Start by selecting the GE condition code for opcodes that return true for
3388 // 'equality'
3389 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3390 CC == ISD::SETULE)
3391 CondCode = ARMCC::GE;
3392
3393 // and GT for opcodes that return false for 'equality'.
3394 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3395 CC == ISD::SETULT)
3396 CondCode = ARMCC::GT;
3397
3398 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3399 // to swap the compare operands.
3400 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3401 CC == ISD::SETULT)
3402 swpCmpOps = true;
3403
3404 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3405 // If we have an unordered opcode, we need to swap the operands to the VSEL
3406 // instruction (effectively negating the condition).
3407 //
3408 // This also has the effect of swapping which one of 'less' or 'greater'
3409 // returns true, so we also swap the compare operands. It also switches
3410 // whether we return true for 'equality', so we compensate by picking the
3411 // opposite condition code to our original choice.
3412 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3413 CC == ISD::SETUGT) {
3414 swpCmpOps = !swpCmpOps;
3415 swpVselOps = !swpVselOps;
3416 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3417 }
3418
3419 // 'ordered' is 'anything but unordered', so use the VS condition code and
3420 // swap the VSEL operands.
3421 if (CC == ISD::SETO) {
3422 CondCode = ARMCC::VS;
3423 swpVselOps = true;
3424 }
3425
3426 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3427 // code and swap the VSEL operands.
3428 if (CC == ISD::SETUNE) {
3429 CondCode = ARMCC::EQ;
3430 swpVselOps = true;
3431 }
3432}
3433
Dan Gohman21cea8a2010-04-17 15:26:15 +00003434SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00003435 EVT VT = Op.getValueType();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003436 SDValue LHS = Op.getOperand(0);
3437 SDValue RHS = Op.getOperand(1);
Evan Cheng10043e22007-01-19 07:51:42 +00003438 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003439 SDValue TrueVal = Op.getOperand(2);
3440 SDValue FalseVal = Op.getOperand(3);
Andrew Trickef9de2a2013-05-25 02:42:55 +00003441 SDLoc dl(Op);
Evan Cheng10043e22007-01-19 07:51:42 +00003442
Owen Anderson9f944592009-08-11 20:47:22 +00003443 if (LHS.getValueType() == MVT::i32) {
Joey Gouly881eab52013-08-22 15:29:11 +00003444 // Try to generate VSEL on ARMv8.
3445 // The VSEL instruction can't use all the usual ARM condition
3446 // codes: it only has two bits to select the condition code, so it's
3447 // constrained to use only GE, GT, VS and EQ.
3448 //
3449 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3450 // swap the operands of the previous compare instruction (effectively
3451 // inverting the compare condition, swapping 'less' and 'greater') and
3452 // sometimes need to swap the operands to the VSEL (which inverts the
3453 // condition in the sense of firing whenever the previous condition didn't)
Joey Goulyccd04892013-09-13 13:46:57 +00003454 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
Joey Gouly881eab52013-08-22 15:29:11 +00003455 TrueVal.getValueType() == MVT::f64)) {
3456 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3457 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3458 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3459 CC = getInverseCCForVSEL(CC);
3460 std::swap(TrueVal, FalseVal);
3461 }
3462 }
3463
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003464 SDValue ARMcc;
Owen Anderson9f944592009-08-11 20:47:22 +00003465 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003466 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
Joey Gouly881eab52013-08-22 15:29:11 +00003467 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3468 Cmp);
Evan Cheng10043e22007-01-19 07:51:42 +00003469 }
3470
3471 ARMCC::CondCodes CondCode, CondCode2;
Bob Wilsona2e83332009-09-09 23:14:54 +00003472 FPCCToARMCC(CC, CondCode, CondCode2);
Evan Cheng10043e22007-01-19 07:51:42 +00003473
Joey Gouly881eab52013-08-22 15:29:11 +00003474 // Try to generate VSEL on ARMv8.
Joey Goulyccd04892013-09-13 13:46:57 +00003475 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
Joey Gouly881eab52013-08-22 15:29:11 +00003476 TrueVal.getValueType() == MVT::f64)) {
Joey Goulye3dd6842013-08-23 12:01:13 +00003477 // We can select VMAXNM/VMINNM from a compare followed by a select with the
3478 // same operands, as follows:
3479 // c = fcmp [ogt, olt, ugt, ult] a, b
3480 // select c, a, b
3481 // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3482 // handled differently than the original code sequence.
3483 if (getTargetMachine().Options.UnsafeFPMath && LHS == TrueVal &&
3484 RHS == FalseVal) {
3485 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3486 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3487 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3488 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3489 }
3490
Joey Gouly881eab52013-08-22 15:29:11 +00003491 bool swpCmpOps = false;
3492 bool swpVselOps = false;
3493 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3494
3495 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3496 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3497 if (swpCmpOps)
3498 std::swap(LHS, RHS);
3499 if (swpVselOps)
3500 std::swap(TrueVal, FalseVal);
3501 }
3502 }
3503
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003504 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3505 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
Owen Anderson9f944592009-08-11 20:47:22 +00003506 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
Dale Johannesen400dc2e2009-02-06 21:50:26 +00003507 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003508 ARMcc, CCR, Cmp);
Evan Cheng10043e22007-01-19 07:51:42 +00003509 if (CondCode2 != ARMCC::AL) {
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003510 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
Evan Cheng10043e22007-01-19 07:51:42 +00003511 // FIXME: Needs another CMP because flag can have but one use.
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003512 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
Bob Wilson7117a912009-03-20 22:42:55 +00003513 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003514 Result, TrueVal, ARMcc2, CCR, Cmp2);
Evan Cheng10043e22007-01-19 07:51:42 +00003515 }
3516 return Result;
3517}
3518
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003519/// canChangeToInt - Given the fp compare operand, return true if it is suitable
3520/// to morph to an integer compare sequence.
3521static bool canChangeToInt(SDValue Op, bool &SeenZero,
3522 const ARMSubtarget *Subtarget) {
3523 SDNode *N = Op.getNode();
3524 if (!N->hasOneUse())
3525 // Otherwise it requires moving the value from fp to integer registers.
3526 return false;
3527 if (!N->getNumValues())
3528 return false;
3529 EVT VT = Op.getValueType();
3530 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3531 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3532 // vmrs are very slow, e.g. cortex-a8.
3533 return false;
3534
3535 if (isFloatingPointZero(Op)) {
3536 SeenZero = true;
3537 return true;
3538 }
3539 return ISD::isNormalLoad(N);
3540}
3541
3542static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3543 if (isFloatingPointZero(Op))
3544 return DAG.getConstant(0, MVT::i32);
3545
3546 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
Andrew Trickef9de2a2013-05-25 02:42:55 +00003547 return DAG.getLoad(MVT::i32, SDLoc(Op),
Chris Lattner7727d052010-09-21 06:44:06 +00003548 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003549 Ld->isVolatile(), Ld->isNonTemporal(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003550 Ld->isInvariant(), Ld->getAlignment());
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003551
3552 llvm_unreachable("Unknown VFP cmp argument!");
3553}
3554
3555static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3556 SDValue &RetVal1, SDValue &RetVal2) {
3557 if (isFloatingPointZero(Op)) {
3558 RetVal1 = DAG.getConstant(0, MVT::i32);
3559 RetVal2 = DAG.getConstant(0, MVT::i32);
3560 return;
3561 }
3562
3563 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3564 SDValue Ptr = Ld->getBasePtr();
Andrew Trickef9de2a2013-05-25 02:42:55 +00003565 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003566 Ld->getChain(), Ptr,
Chris Lattner7727d052010-09-21 06:44:06 +00003567 Ld->getPointerInfo(),
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003568 Ld->isVolatile(), Ld->isNonTemporal(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003569 Ld->isInvariant(), Ld->getAlignment());
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003570
3571 EVT PtrType = Ptr.getValueType();
3572 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
Andrew Trickef9de2a2013-05-25 02:42:55 +00003573 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(Op),
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003574 PtrType, Ptr, DAG.getConstant(4, PtrType));
Andrew Trickef9de2a2013-05-25 02:42:55 +00003575 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003576 Ld->getChain(), NewPtr,
Chris Lattner7727d052010-09-21 06:44:06 +00003577 Ld->getPointerInfo().getWithOffset(4),
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003578 Ld->isVolatile(), Ld->isNonTemporal(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003579 Ld->isInvariant(), NewAlign);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003580 return;
3581 }
3582
3583 llvm_unreachable("Unknown VFP cmp argument!");
3584}
3585
3586/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3587/// f32 and even f64 comparisons to integer ones.
3588SDValue
3589ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3590 SDValue Chain = Op.getOperand(0);
Evan Cheng10043e22007-01-19 07:51:42 +00003591 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003592 SDValue LHS = Op.getOperand(2);
3593 SDValue RHS = Op.getOperand(3);
3594 SDValue Dest = Op.getOperand(4);
Andrew Trickef9de2a2013-05-25 02:42:55 +00003595 SDLoc dl(Op);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003596
Evan Chengd12af5d2012-03-01 23:27:13 +00003597 bool LHSSeenZero = false;
3598 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3599 bool RHSSeenZero = false;
3600 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3601 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
Bob Wilson70bd3632011-03-08 01:17:16 +00003602 // If unsafe fp math optimization is enabled and there are no other uses of
3603 // the CMP operands, and the condition code is EQ or NE, we can optimize it
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003604 // to an integer comparison.
3605 if (CC == ISD::SETOEQ)
3606 CC = ISD::SETEQ;
3607 else if (CC == ISD::SETUNE)
3608 CC = ISD::SETNE;
3609
Evan Chengd12af5d2012-03-01 23:27:13 +00003610 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003611 SDValue ARMcc;
3612 if (LHS.getValueType() == MVT::f32) {
Evan Chengd12af5d2012-03-01 23:27:13 +00003613 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3614 bitcastf32Toi32(LHS, DAG), Mask);
3615 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3616 bitcastf32Toi32(RHS, DAG), Mask);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003617 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3618 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3619 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3620 Chain, Dest, ARMcc, CCR, Cmp);
3621 }
3622
3623 SDValue LHS1, LHS2;
3624 SDValue RHS1, RHS2;
3625 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3626 expandf64Toi32(RHS, DAG, RHS1, RHS2);
Evan Chengd12af5d2012-03-01 23:27:13 +00003627 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3628 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003629 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3630 ARMcc = DAG.getConstant(CondCode, MVT::i32);
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003631 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003632 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
Craig Topper48d114b2014-04-26 18:35:24 +00003633 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003634 }
3635
3636 return SDValue();
3637}
3638
3639SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3640 SDValue Chain = Op.getOperand(0);
3641 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3642 SDValue LHS = Op.getOperand(2);
3643 SDValue RHS = Op.getOperand(3);
3644 SDValue Dest = Op.getOperand(4);
Andrew Trickef9de2a2013-05-25 02:42:55 +00003645 SDLoc dl(Op);
Evan Cheng10043e22007-01-19 07:51:42 +00003646
Owen Anderson9f944592009-08-11 20:47:22 +00003647 if (LHS.getValueType() == MVT::i32) {
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003648 SDValue ARMcc;
3649 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
Owen Anderson9f944592009-08-11 20:47:22 +00003650 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
Owen Anderson9f944592009-08-11 20:47:22 +00003651 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003652 Chain, Dest, ARMcc, CCR, Cmp);
Evan Cheng10043e22007-01-19 07:51:42 +00003653 }
3654
Owen Anderson9f944592009-08-11 20:47:22 +00003655 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003656
Nick Lewycky50f02cb2011-12-02 22:16:29 +00003657 if (getTargetMachine().Options.UnsafeFPMath &&
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003658 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3659 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3660 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3661 if (Result.getNode())
3662 return Result;
3663 }
3664
Evan Cheng10043e22007-01-19 07:51:42 +00003665 ARMCC::CondCodes CondCode, CondCode2;
Bob Wilsona2e83332009-09-09 23:14:54 +00003666 FPCCToARMCC(CC, CondCode, CondCode2);
Bob Wilson7117a912009-03-20 22:42:55 +00003667
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003668 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3669 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
Owen Anderson9f944592009-08-11 20:47:22 +00003670 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003671 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003672 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
Craig Topper48d114b2014-04-26 18:35:24 +00003673 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
Evan Cheng10043e22007-01-19 07:51:42 +00003674 if (CondCode2 != ARMCC::AL) {
Evan Cheng0cc4ad92010-07-13 19:27:42 +00003675 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3676 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
Craig Topper48d114b2014-04-26 18:35:24 +00003677 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
Evan Cheng10043e22007-01-19 07:51:42 +00003678 }
3679 return Res;
3680}
3681
Dan Gohman21cea8a2010-04-17 15:26:15 +00003682SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003683 SDValue Chain = Op.getOperand(0);
3684 SDValue Table = Op.getOperand(1);
3685 SDValue Index = Op.getOperand(2);
Andrew Trickef9de2a2013-05-25 02:42:55 +00003686 SDLoc dl(Op);
Evan Cheng10043e22007-01-19 07:51:42 +00003687
Owen Anderson53aa7a92009-08-10 22:56:29 +00003688 EVT PTy = getPointerTy();
Evan Cheng10043e22007-01-19 07:51:42 +00003689 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3690 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
Bob Wilson3f17aee2009-07-14 18:44:34 +00003691 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003692 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
Owen Anderson9f944592009-08-11 20:47:22 +00003693 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
Evan Chengc8bed032009-07-28 20:53:24 +00003694 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3695 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
Evan Chengf3a1fce2009-07-25 00:33:29 +00003696 if (Subtarget->isThumb2()) {
3697 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3698 // which does another jump to the destination. This also makes it easier
3699 // to translate it to TBB / TBH later.
3700 // FIXME: This might not work if the function is extremely large.
Owen Anderson9f944592009-08-11 20:47:22 +00003701 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
Evan Chengc6d70ae2009-07-29 02:18:14 +00003702 Addr, Op.getOperand(2), JTI, UId);
Evan Chengf3a1fce2009-07-25 00:33:29 +00003703 }
Evan Chengf3a1fce2009-07-25 00:33:29 +00003704 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
Evan Chengcdbb70c2009-10-31 03:39:36 +00003705 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
Chris Lattner7727d052010-09-21 06:44:06 +00003706 MachinePointerInfo::getJumpTable(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003707 false, false, false, 0);
Evan Chengf3a1fce2009-07-25 00:33:29 +00003708 Chain = Addr.getValue(1);
Dale Johannesen021052a2009-02-04 20:06:27 +00003709 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
Owen Anderson9f944592009-08-11 20:47:22 +00003710 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
Evan Chengf3a1fce2009-07-25 00:33:29 +00003711 } else {
Evan Chengcdbb70c2009-10-31 03:39:36 +00003712 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
Pete Cooper82cd9e82011-11-08 18:42:53 +00003713 MachinePointerInfo::getJumpTable(),
3714 false, false, false, 0);
Evan Chengf3a1fce2009-07-25 00:33:29 +00003715 Chain = Addr.getValue(1);
Owen Anderson9f944592009-08-11 20:47:22 +00003716 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
Evan Chengf3a1fce2009-07-25 00:33:29 +00003717 }
Evan Cheng10043e22007-01-19 07:51:42 +00003718}
3719
Eli Friedman2d4055b2011-11-09 23:36:02 +00003720static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
James Molloy547d4c02012-02-20 09:24:05 +00003721 EVT VT = Op.getValueType();
Andrew Trickef9de2a2013-05-25 02:42:55 +00003722 SDLoc dl(Op);
Eli Friedman2d4055b2011-11-09 23:36:02 +00003723
James Molloy547d4c02012-02-20 09:24:05 +00003724 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3725 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3726 return Op;
3727 return DAG.UnrollVectorOp(Op.getNode());
3728 }
3729
3730 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3731 "Invalid type for custom lowering!");
3732 if (VT != MVT::v4i16)
3733 return DAG.UnrollVectorOp(Op.getNode());
3734
3735 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3736 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
Eli Friedman2d4055b2011-11-09 23:36:02 +00003737}
3738
Bob Wilsone4191e72010-03-19 22:51:32 +00003739static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
Eli Friedman2d4055b2011-11-09 23:36:02 +00003740 EVT VT = Op.getValueType();
3741 if (VT.isVector())
3742 return LowerVectorFP_TO_INT(Op, DAG);
3743
Andrew Trickef9de2a2013-05-25 02:42:55 +00003744 SDLoc dl(Op);
Bob Wilsone4191e72010-03-19 22:51:32 +00003745 unsigned Opc;
3746
3747 switch (Op.getOpcode()) {
Craig Toppere55c5562012-02-07 02:50:20 +00003748 default: llvm_unreachable("Invalid opcode!");
Bob Wilsone4191e72010-03-19 22:51:32 +00003749 case ISD::FP_TO_SINT:
3750 Opc = ARMISD::FTOSI;
3751 break;
3752 case ISD::FP_TO_UINT:
3753 Opc = ARMISD::FTOUI;
3754 break;
3755 }
3756 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
Wesley Peck527da1b2010-11-23 03:31:01 +00003757 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
Bob Wilsone4191e72010-03-19 22:51:32 +00003758}
3759
Cameron Zwarich143f9ae2011-03-29 21:41:55 +00003760static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3761 EVT VT = Op.getValueType();
Andrew Trickef9de2a2013-05-25 02:42:55 +00003762 SDLoc dl(Op);
Cameron Zwarich143f9ae2011-03-29 21:41:55 +00003763
Eli Friedman2d4055b2011-11-09 23:36:02 +00003764 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3765 if (VT.getVectorElementType() == MVT::f32)
3766 return Op;
3767 return DAG.UnrollVectorOp(Op.getNode());
3768 }
3769
Duncan Sandsa41634e2011-08-12 14:54:45 +00003770 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3771 "Invalid type for custom lowering!");
Cameron Zwarich143f9ae2011-03-29 21:41:55 +00003772 if (VT != MVT::v4f32)
3773 return DAG.UnrollVectorOp(Op.getNode());
3774
3775 unsigned CastOpc;
3776 unsigned Opc;
3777 switch (Op.getOpcode()) {
Craig Toppere55c5562012-02-07 02:50:20 +00003778 default: llvm_unreachable("Invalid opcode!");
Cameron Zwarich143f9ae2011-03-29 21:41:55 +00003779 case ISD::SINT_TO_FP:
3780 CastOpc = ISD::SIGN_EXTEND;
3781 Opc = ISD::SINT_TO_FP;
3782 break;
3783 case ISD::UINT_TO_FP:
3784 CastOpc = ISD::ZERO_EXTEND;
3785 Opc = ISD::UINT_TO_FP;
3786 break;
3787 }
3788
3789 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3790 return DAG.getNode(Opc, dl, VT, Op);
3791}
3792
Bob Wilsone4191e72010-03-19 22:51:32 +00003793static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3794 EVT VT = Op.getValueType();
Cameron Zwarich143f9ae2011-03-29 21:41:55 +00003795 if (VT.isVector())
3796 return LowerVectorINT_TO_FP(Op, DAG);
3797
Andrew Trickef9de2a2013-05-25 02:42:55 +00003798 SDLoc dl(Op);
Bob Wilsone4191e72010-03-19 22:51:32 +00003799 unsigned Opc;
3800
3801 switch (Op.getOpcode()) {
Craig Toppere55c5562012-02-07 02:50:20 +00003802 default: llvm_unreachable("Invalid opcode!");
Bob Wilsone4191e72010-03-19 22:51:32 +00003803 case ISD::SINT_TO_FP:
3804 Opc = ARMISD::SITOF;
3805 break;
3806 case ISD::UINT_TO_FP:
3807 Opc = ARMISD::UITOF;
3808 break;
3809 }
3810
Wesley Peck527da1b2010-11-23 03:31:01 +00003811 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
Bob Wilsone4191e72010-03-19 22:51:32 +00003812 return DAG.getNode(Opc, dl, VT, Op);
3813}
3814
Evan Cheng25f93642010-07-08 02:08:50 +00003815SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Evan Cheng10043e22007-01-19 07:51:42 +00003816 // Implement fcopysign with a fabs and a conditional fneg.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003817 SDValue Tmp0 = Op.getOperand(0);
3818 SDValue Tmp1 = Op.getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +00003819 SDLoc dl(Op);
Owen Anderson53aa7a92009-08-10 22:56:29 +00003820 EVT VT = Op.getValueType();
3821 EVT SrcVT = Tmp1.getValueType();
Evan Chengd6b641e2011-02-23 02:24:55 +00003822 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3823 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3824 bool UseNEON = !InGPR && Subtarget->hasNEON();
3825
3826 if (UseNEON) {
3827 // Use VBSL to copy the sign bit.
3828 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3829 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3830 DAG.getTargetConstant(EncodedVal, MVT::i32));
3831 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3832 if (VT == MVT::f64)
3833 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3834 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3835 DAG.getConstant(32, MVT::i32));
3836 else /*if (VT == MVT::f32)*/
3837 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3838 if (SrcVT == MVT::f32) {
3839 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3840 if (VT == MVT::f64)
3841 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3842 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3843 DAG.getConstant(32, MVT::i32));
Evan Cheng12bb05b2011-04-15 01:31:00 +00003844 } else if (VT == MVT::f32)
3845 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3846 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3847 DAG.getConstant(32, MVT::i32));
Evan Chengd6b641e2011-02-23 02:24:55 +00003848 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3849 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3850
3851 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3852 MVT::i32);
3853 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3854 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3855 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
Owen Anderson77aa2662011-04-05 21:48:57 +00003856
Evan Chengd6b641e2011-02-23 02:24:55 +00003857 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3858 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3859 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
Evan Cheng6e3d4432011-02-28 18:45:27 +00003860 if (VT == MVT::f32) {
Evan Chengd6b641e2011-02-23 02:24:55 +00003861 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3862 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3863 DAG.getConstant(0, MVT::i32));
3864 } else {
3865 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3866 }
3867
3868 return Res;
3869 }
Evan Cheng2da1c952011-02-11 02:28:55 +00003870
3871 // Bitcast operand 1 to i32.
3872 if (SrcVT == MVT::f64)
3873 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
Craig Topper48d114b2014-04-26 18:35:24 +00003874 Tmp1).getValue(1);
Evan Cheng2da1c952011-02-11 02:28:55 +00003875 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3876
Evan Chengd6b641e2011-02-23 02:24:55 +00003877 // Or in the signbit with integer operations.
3878 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3879 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3880 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3881 if (VT == MVT::f32) {
3882 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3883 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3884 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3885 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
Evan Cheng2da1c952011-02-11 02:28:55 +00003886 }
3887
Evan Chengd6b641e2011-02-23 02:24:55 +00003888 // f64: Or the high part with signbit and then combine two parts.
3889 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
Craig Topper48d114b2014-04-26 18:35:24 +00003890 Tmp0);
Evan Chengd6b641e2011-02-23 02:24:55 +00003891 SDValue Lo = Tmp0.getValue(0);
3892 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3893 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3894 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
Evan Cheng10043e22007-01-19 07:51:42 +00003895}
3896
Evan Cheng168ced92010-05-22 01:47:14 +00003897SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3898 MachineFunction &MF = DAG.getMachineFunction();
3899 MachineFrameInfo *MFI = MF.getFrameInfo();
3900 MFI->setReturnAddressIsTaken(true);
3901
Bill Wendling908bf812014-01-06 00:43:20 +00003902 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
Bill Wendlingdf7dd282014-01-05 01:47:20 +00003903 return SDValue();
Bill Wendlingdf7dd282014-01-05 01:47:20 +00003904
Evan Cheng168ced92010-05-22 01:47:14 +00003905 EVT VT = Op.getValueType();
Andrew Trickef9de2a2013-05-25 02:42:55 +00003906 SDLoc dl(Op);
Evan Cheng168ced92010-05-22 01:47:14 +00003907 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3908 if (Depth) {
3909 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3910 SDValue Offset = DAG.getConstant(4, MVT::i32);
3911 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3912 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003913 MachinePointerInfo(), false, false, false, 0);
Evan Cheng168ced92010-05-22 01:47:14 +00003914 }
3915
3916 // Return LR, which contains the return address. Mark it an implicit live-in.
Devang Patelf3292b22011-02-21 23:21:26 +00003917 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
Evan Cheng168ced92010-05-22 01:47:14 +00003918 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3919}
3920
Dan Gohman21cea8a2010-04-17 15:26:15 +00003921SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Saleem Abdulrasoolf11f4b42014-05-18 03:18:09 +00003922 const ARMBaseRegisterInfo &ARI =
3923 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
3924 MachineFunction &MF = DAG.getMachineFunction();
3925 MachineFrameInfo *MFI = MF.getFrameInfo();
Jim Grosbachaeca45d2009-05-12 23:59:14 +00003926 MFI->setFrameAddressIsTaken(true);
Evan Cheng168ced92010-05-22 01:47:14 +00003927
Owen Anderson53aa7a92009-08-10 22:56:29 +00003928 EVT VT = Op.getValueType();
Andrew Trickef9de2a2013-05-25 02:42:55 +00003929 SDLoc dl(Op); // FIXME probably not meaningful
Jim Grosbachaeca45d2009-05-12 23:59:14 +00003930 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Saleem Abdulrasoolf11f4b42014-05-18 03:18:09 +00003931 unsigned FrameReg = ARI.getFrameRegister(MF);
Jim Grosbachaeca45d2009-05-12 23:59:14 +00003932 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3933 while (Depth--)
Chris Lattner7727d052010-09-21 06:44:06 +00003934 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3935 MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003936 false, false, false, 0);
Jim Grosbachaeca45d2009-05-12 23:59:14 +00003937 return FrameAddr;
3938}
3939
Renato Golinc7aea402014-05-06 16:51:25 +00003940// FIXME? Maybe this could be a TableGen attribute on some registers and
3941// this table could be generated automatically from RegInfo.
Hal Finkelf0e086a2014-05-11 19:29:07 +00003942unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
3943 EVT VT) const {
Renato Golinc7aea402014-05-06 16:51:25 +00003944 unsigned Reg = StringSwitch<unsigned>(RegName)
3945 .Case("sp", ARM::SP)
3946 .Default(0);
3947 if (Reg)
3948 return Reg;
3949 report_fatal_error("Invalid register name global variable");
3950}
3951
Wesley Peck527da1b2010-11-23 03:31:01 +00003952/// ExpandBITCAST - If the target supports VFP, this function is called to
Bob Wilson59b70ea2010-04-17 05:30:19 +00003953/// expand a bit convert where either the source or destination type is i64 to
3954/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3955/// operand type is illegal (e.g., v2f32 for a target that doesn't support
3956/// vectors), since the legalizer won't know what to do with that.
Wesley Peck527da1b2010-11-23 03:31:01 +00003957static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
Bob Wilson59b70ea2010-04-17 05:30:19 +00003958 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Andrew Trickef9de2a2013-05-25 02:42:55 +00003959 SDLoc dl(N);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003960 SDValue Op = N->getOperand(0);
Bob Wilsonc05b8872010-04-14 20:45:23 +00003961
Bob Wilson59b70ea2010-04-17 05:30:19 +00003962 // This function is only supposed to be called for i64 types, either as the
3963 // source or destination of the bit convert.
3964 EVT SrcVT = Op.getValueType();
3965 EVT DstVT = N->getValueType(0);
3966 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
Wesley Peck527da1b2010-11-23 03:31:01 +00003967 "ExpandBITCAST called for non-i64 type");
Bob Wilsonc05b8872010-04-14 20:45:23 +00003968
Bob Wilson59b70ea2010-04-17 05:30:19 +00003969 // Turn i64->f64 into VMOVDRR.
3970 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
Owen Anderson9f944592009-08-11 20:47:22 +00003971 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3972 DAG.getConstant(0, MVT::i32));
3973 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3974 DAG.getConstant(1, MVT::i32));
Wesley Peck527da1b2010-11-23 03:31:01 +00003975 return DAG.getNode(ISD::BITCAST, dl, DstVT,
Bob Wilsonf07d33d2010-06-11 22:45:25 +00003976 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
Evan Cheng297b32a2008-11-04 19:57:48 +00003977 }
Bob Wilson7117a912009-03-20 22:42:55 +00003978
Jim Grosbachd7cf55c2009-11-09 00:11:35 +00003979 // Turn f64->i64 into VMOVRRD.
Bob Wilson59b70ea2010-04-17 05:30:19 +00003980 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
Christian Pirker238c7c12014-05-12 11:19:20 +00003981 SDValue Cvt;
Christian Pirker6692e7c2014-05-14 16:59:44 +00003982 if (TLI.isBigEndian() && SrcVT.isVector() &&
3983 SrcVT.getVectorNumElements() > 1)
Christian Pirker238c7c12014-05-12 11:19:20 +00003984 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3985 DAG.getVTList(MVT::i32, MVT::i32),
3986 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
3987 else
3988 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3989 DAG.getVTList(MVT::i32, MVT::i32), Op);
Bob Wilson59b70ea2010-04-17 05:30:19 +00003990 // Merge the pieces into a single i64 value.
3991 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3992 }
Bob Wilson7117a912009-03-20 22:42:55 +00003993
Bob Wilson59b70ea2010-04-17 05:30:19 +00003994 return SDValue();
Chris Lattnerf81d5882007-11-24 07:07:01 +00003995}
3996
Bob Wilson2e076c42009-06-22 23:27:02 +00003997/// getZeroVector - Returns a vector of specified type with all zero elements.
Bob Wilsona3f19012010-07-13 21:16:48 +00003998/// Zero vectors are used to represent vector negation and in those cases
3999/// will be implemented with the NEON VNEG instruction. However, VNEG does
4000/// not support i64 elements, so sometimes the zero vectors will need to be
4001/// explicitly constructed. Regardless, use a canonical VMOV to create the
4002/// zero vector.
Andrew Trickef9de2a2013-05-25 02:42:55 +00004003static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
Bob Wilson2e076c42009-06-22 23:27:02 +00004004 assert(VT.isVector() && "Expected a vector type");
Bob Wilsona3f19012010-07-13 21:16:48 +00004005 // The canonical modified immediate encoding of a zero vector is....0!
4006 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
4007 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4008 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
Wesley Peck527da1b2010-11-23 03:31:01 +00004009 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
Bob Wilson2e076c42009-06-22 23:27:02 +00004010}
4011
Jim Grosbach624fcb22009-10-31 21:00:56 +00004012/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4013/// i32 values and take a 2 x i32 value to shift plus a shift amount.
Dan Gohman21cea8a2010-04-17 15:26:15 +00004014SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4015 SelectionDAG &DAG) const {
Jim Grosbach624fcb22009-10-31 21:00:56 +00004016 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4017 EVT VT = Op.getValueType();
4018 unsigned VTBits = VT.getSizeInBits();
Andrew Trickef9de2a2013-05-25 02:42:55 +00004019 SDLoc dl(Op);
Jim Grosbach624fcb22009-10-31 21:00:56 +00004020 SDValue ShOpLo = Op.getOperand(0);
4021 SDValue ShOpHi = Op.getOperand(1);
4022 SDValue ShAmt = Op.getOperand(2);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00004023 SDValue ARMcc;
Jim Grosbach8fe6fd72009-10-31 21:42:19 +00004024 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
Jim Grosbach624fcb22009-10-31 21:00:56 +00004025
Jim Grosbach8fe6fd72009-10-31 21:42:19 +00004026 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4027
Jim Grosbach624fcb22009-10-31 21:00:56 +00004028 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4029 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4030 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4031 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4032 DAG.getConstant(VTBits, MVT::i32));
4033 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4034 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
Jim Grosbach8fe6fd72009-10-31 21:42:19 +00004035 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
Jim Grosbach624fcb22009-10-31 21:00:56 +00004036
4037 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4038 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
Evan Cheng0cc4ad92010-07-13 19:27:42 +00004039 ARMcc, DAG, dl);
Jim Grosbach8fe6fd72009-10-31 21:42:19 +00004040 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00004041 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
Jim Grosbach624fcb22009-10-31 21:00:56 +00004042 CCR, Cmp);
4043
4044 SDValue Ops[2] = { Lo, Hi };
Craig Topper64941d92014-04-27 19:20:57 +00004045 return DAG.getMergeValues(Ops, dl);
Jim Grosbach624fcb22009-10-31 21:00:56 +00004046}
4047
Jim Grosbach5d994042009-10-31 19:38:01 +00004048/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4049/// i32 values and take a 2 x i32 value to shift plus a shift amount.
Dan Gohman21cea8a2010-04-17 15:26:15 +00004050SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4051 SelectionDAG &DAG) const {
Jim Grosbach5d994042009-10-31 19:38:01 +00004052 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4053 EVT VT = Op.getValueType();
4054 unsigned VTBits = VT.getSizeInBits();
Andrew Trickef9de2a2013-05-25 02:42:55 +00004055 SDLoc dl(Op);
Jim Grosbach5d994042009-10-31 19:38:01 +00004056 SDValue ShOpLo = Op.getOperand(0);
4057 SDValue ShOpHi = Op.getOperand(1);
4058 SDValue ShAmt = Op.getOperand(2);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00004059 SDValue ARMcc;
Jim Grosbach5d994042009-10-31 19:38:01 +00004060
4061 assert(Op.getOpcode() == ISD::SHL_PARTS);
4062 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4063 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4064 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4065 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4066 DAG.getConstant(VTBits, MVT::i32));
4067 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4068 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4069
4070 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4071 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4072 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
Evan Cheng0cc4ad92010-07-13 19:27:42 +00004073 ARMcc, DAG, dl);
Jim Grosbach5d994042009-10-31 19:38:01 +00004074 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00004075 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
Jim Grosbach5d994042009-10-31 19:38:01 +00004076 CCR, Cmp);
4077
4078 SDValue Ops[2] = { Lo, Hi };
Craig Topper64941d92014-04-27 19:20:57 +00004079 return DAG.getMergeValues(Ops, dl);
Jim Grosbach5d994042009-10-31 19:38:01 +00004080}
4081
Jim Grosbach535d3b42010-09-08 03:54:02 +00004082SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
Nate Begemanb69b1822010-08-03 21:31:55 +00004083 SelectionDAG &DAG) const {
4084 // The rounding mode is in bits 23:22 of the FPSCR.
4085 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4086 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4087 // so that the shift + and get folded into a bitfield extract.
Andrew Trickef9de2a2013-05-25 02:42:55 +00004088 SDLoc dl(Op);
Nate Begemanb69b1822010-08-03 21:31:55 +00004089 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4090 DAG.getConstant(Intrinsic::arm_get_fpscr,
4091 MVT::i32));
Jim Grosbach535d3b42010-09-08 03:54:02 +00004092 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
Nate Begemanb69b1822010-08-03 21:31:55 +00004093 DAG.getConstant(1U << 22, MVT::i32));
4094 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4095 DAG.getConstant(22, MVT::i32));
Jim Grosbach535d3b42010-09-08 03:54:02 +00004096 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
Nate Begemanb69b1822010-08-03 21:31:55 +00004097 DAG.getConstant(3, MVT::i32));
4098}
4099
Jim Grosbach8546ec92010-01-18 19:58:49 +00004100static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4101 const ARMSubtarget *ST) {
4102 EVT VT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00004103 SDLoc dl(N);
Jim Grosbach8546ec92010-01-18 19:58:49 +00004104
4105 if (!ST->hasV6T2Ops())
4106 return SDValue();
4107
4108 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4109 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4110}
4111
Evan Chengb4eae132012-12-04 22:41:50 +00004112/// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4113/// for each 16-bit element from operand, repeated. The basic idea is to
4114/// leverage vcnt to get the 8-bit counts, gather and add the results.
4115///
4116/// Trace for v4i16:
4117/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4118/// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4119/// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
Jim Grosbach54efea02013-03-02 20:16:15 +00004120/// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
Evan Chengb4eae132012-12-04 22:41:50 +00004121/// [b0 b1 b2 b3 b4 b5 b6 b7]
4122/// +[b1 b0 b3 b2 b5 b4 b7 b6]
4123/// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4124/// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4125static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4126 EVT VT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00004127 SDLoc DL(N);
Evan Chengb4eae132012-12-04 22:41:50 +00004128
4129 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4130 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4131 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4132 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4133 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4134 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4135}
4136
4137/// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4138/// bit-count for each 16-bit element from the operand. We need slightly
4139/// different sequencing for v4i16 and v8i16 to stay within NEON's available
4140/// 64/128-bit registers.
Jim Grosbach54efea02013-03-02 20:16:15 +00004141///
Evan Chengb4eae132012-12-04 22:41:50 +00004142/// Trace for v4i16:
4143/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4144/// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4145/// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4146/// v4i16:Extracted = [k0 k1 k2 k3 ]
4147static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4148 EVT VT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00004149 SDLoc DL(N);
Evan Chengb4eae132012-12-04 22:41:50 +00004150
4151 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4152 if (VT.is64BitVector()) {
4153 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4154 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4155 DAG.getIntPtrConstant(0));
4156 } else {
4157 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4158 BitCounts, DAG.getIntPtrConstant(0));
4159 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4160 }
4161}
4162
4163/// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4164/// bit-count for each 32-bit element from the operand. The idea here is
4165/// to split the vector into 16-bit elements, leverage the 16-bit count
4166/// routine, and then combine the results.
4167///
4168/// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4169/// input = [v0 v1 ] (vi: 32-bit elements)
4170/// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4171/// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
Jim Grosbach54efea02013-03-02 20:16:15 +00004172/// vrev: N0 = [k1 k0 k3 k2 ]
Evan Chengb4eae132012-12-04 22:41:50 +00004173/// [k0 k1 k2 k3 ]
4174/// N1 =+[k1 k0 k3 k2 ]
4175/// [k0 k2 k1 k3 ]
4176/// N2 =+[k1 k3 k0 k2 ]
4177/// [k0 k2 k1 k3 ]
4178/// Extended =+[k1 k3 k0 k2 ]
4179/// [k0 k2 ]
4180/// Extracted=+[k1 k3 ]
4181///
4182static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4183 EVT VT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00004184 SDLoc DL(N);
Evan Chengb4eae132012-12-04 22:41:50 +00004185
4186 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4187
4188 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4189 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4190 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4191 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4192 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4193
4194 if (VT.is64BitVector()) {
4195 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4196 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4197 DAG.getIntPtrConstant(0));
4198 } else {
4199 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4200 DAG.getIntPtrConstant(0));
4201 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4202 }
4203}
4204
4205static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4206 const ARMSubtarget *ST) {
4207 EVT VT = N->getValueType(0);
4208
4209 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
Matt Beaumont-Gay50f61b62012-12-04 23:54:02 +00004210 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4211 VT == MVT::v4i16 || VT == MVT::v8i16) &&
Evan Chengb4eae132012-12-04 22:41:50 +00004212 "Unexpected type for custom ctpop lowering");
4213
4214 if (VT.getVectorElementType() == MVT::i32)
4215 return lowerCTPOP32BitElements(N, DAG);
4216 else
4217 return lowerCTPOP16BitElements(N, DAG);
4218}
4219
Bob Wilson2e076c42009-06-22 23:27:02 +00004220static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4221 const ARMSubtarget *ST) {
Owen Anderson53aa7a92009-08-10 22:56:29 +00004222 EVT VT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00004223 SDLoc dl(N);
Bob Wilson2e076c42009-06-22 23:27:02 +00004224
Bob Wilson7d471332010-11-18 21:16:28 +00004225 if (!VT.isVector())
4226 return SDValue();
4227
Bob Wilson2e076c42009-06-22 23:27:02 +00004228 // Lower vector shifts on NEON to use VSHL.
Bob Wilson7d471332010-11-18 21:16:28 +00004229 assert(ST->hasNEON() && "unexpected vector shift");
Bob Wilson2e076c42009-06-22 23:27:02 +00004230
Bob Wilson7d471332010-11-18 21:16:28 +00004231 // Left shifts translate directly to the vshiftu intrinsic.
4232 if (N->getOpcode() == ISD::SHL)
Bob Wilson2e076c42009-06-22 23:27:02 +00004233 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Bob Wilson7d471332010-11-18 21:16:28 +00004234 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4235 N->getOperand(0), N->getOperand(1));
4236
4237 assert((N->getOpcode() == ISD::SRA ||
4238 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4239
4240 // NEON uses the same intrinsics for both left and right shifts. For
4241 // right shifts, the shift amounts are negative, so negate the vector of
4242 // shift amounts.
4243 EVT ShiftVT = N->getOperand(1).getValueType();
4244 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4245 getZeroVector(ShiftVT, DAG, dl),
4246 N->getOperand(1));
4247 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4248 Intrinsic::arm_neon_vshifts :
4249 Intrinsic::arm_neon_vshiftu);
4250 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4251 DAG.getConstant(vshiftInt, MVT::i32),
4252 N->getOperand(0), NegatedCount);
4253}
4254
4255static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4256 const ARMSubtarget *ST) {
4257 EVT VT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00004258 SDLoc dl(N);
Bob Wilson2e076c42009-06-22 23:27:02 +00004259
Eli Friedman682d8c12009-08-22 03:13:10 +00004260 // We can get here for a node like i32 = ISD::SHL i32, i64
4261 if (VT != MVT::i64)
4262 return SDValue();
4263
4264 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
Chris Lattnerf81d5882007-11-24 07:07:01 +00004265 "Unknown shift to lower!");
Duncan Sands6ed40142008-12-01 11:39:25 +00004266
Chris Lattnerf81d5882007-11-24 07:07:01 +00004267 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4268 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
Dan Gohmaneffb8942008-09-12 16:56:44 +00004269 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
Duncan Sands6ed40142008-12-01 11:39:25 +00004270 return SDValue();
Bob Wilson7117a912009-03-20 22:42:55 +00004271
Chris Lattnerf81d5882007-11-24 07:07:01 +00004272 // If we are in thumb mode, we don't have RRX.
David Goodwin22c2fba2009-07-08 23:10:31 +00004273 if (ST->isThumb1Only()) return SDValue();
Bob Wilson7117a912009-03-20 22:42:55 +00004274
Chris Lattnerf81d5882007-11-24 07:07:01 +00004275 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
Owen Anderson9f944592009-08-11 20:47:22 +00004276 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
Bob Wilson26fdebc2010-05-25 03:36:52 +00004277 DAG.getConstant(0, MVT::i32));
Owen Anderson9f944592009-08-11 20:47:22 +00004278 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
Bob Wilson26fdebc2010-05-25 03:36:52 +00004279 DAG.getConstant(1, MVT::i32));
Bob Wilson7117a912009-03-20 22:42:55 +00004280
Chris Lattnerf81d5882007-11-24 07:07:01 +00004281 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4282 // captures the result into a carry flag.
4283 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
Craig Topper48d114b2014-04-26 18:35:24 +00004284 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
Bob Wilson7117a912009-03-20 22:42:55 +00004285
Chris Lattnerf81d5882007-11-24 07:07:01 +00004286 // The low part is an ARMISD::RRX operand, which shifts the carry in.
Owen Anderson9f944592009-08-11 20:47:22 +00004287 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
Bob Wilson7117a912009-03-20 22:42:55 +00004288
Chris Lattnerf81d5882007-11-24 07:07:01 +00004289 // Merge the pieces into a single i64 value.
Owen Anderson9f944592009-08-11 20:47:22 +00004290 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
Chris Lattnerf81d5882007-11-24 07:07:01 +00004291}
4292
Bob Wilson2e076c42009-06-22 23:27:02 +00004293static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4294 SDValue TmpOp0, TmpOp1;
4295 bool Invert = false;
4296 bool Swap = false;
4297 unsigned Opc = 0;
4298
4299 SDValue Op0 = Op.getOperand(0);
4300 SDValue Op1 = Op.getOperand(1);
4301 SDValue CC = Op.getOperand(2);
Owen Anderson53aa7a92009-08-10 22:56:29 +00004302 EVT VT = Op.getValueType();
Bob Wilson2e076c42009-06-22 23:27:02 +00004303 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
Andrew Trickef9de2a2013-05-25 02:42:55 +00004304 SDLoc dl(Op);
Bob Wilson2e076c42009-06-22 23:27:02 +00004305
4306 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
4307 switch (SetCCOpcode) {
David Blaikie46a9f012012-01-20 21:51:11 +00004308 default: llvm_unreachable("Illegal FP comparison");
Bob Wilson2e076c42009-06-22 23:27:02 +00004309 case ISD::SETUNE:
4310 case ISD::SETNE: Invert = true; // Fallthrough
4311 case ISD::SETOEQ:
4312 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4313 case ISD::SETOLT:
4314 case ISD::SETLT: Swap = true; // Fallthrough
4315 case ISD::SETOGT:
4316 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4317 case ISD::SETOLE:
4318 case ISD::SETLE: Swap = true; // Fallthrough
4319 case ISD::SETOGE:
4320 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4321 case ISD::SETUGE: Swap = true; // Fallthrough
4322 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4323 case ISD::SETUGT: Swap = true; // Fallthrough
4324 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4325 case ISD::SETUEQ: Invert = true; // Fallthrough
4326 case ISD::SETONE:
4327 // Expand this to (OLT | OGT).
4328 TmpOp0 = Op0;
4329 TmpOp1 = Op1;
4330 Opc = ISD::OR;
4331 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4332 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
4333 break;
4334 case ISD::SETUO: Invert = true; // Fallthrough
4335 case ISD::SETO:
4336 // Expand this to (OLT | OGE).
4337 TmpOp0 = Op0;
4338 TmpOp1 = Op1;
4339 Opc = ISD::OR;
4340 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4341 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
4342 break;
4343 }
4344 } else {
4345 // Integer comparisons.
4346 switch (SetCCOpcode) {
David Blaikie46a9f012012-01-20 21:51:11 +00004347 default: llvm_unreachable("Illegal integer comparison");
Bob Wilson2e076c42009-06-22 23:27:02 +00004348 case ISD::SETNE: Invert = true;
4349 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4350 case ISD::SETLT: Swap = true;
4351 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4352 case ISD::SETLE: Swap = true;
4353 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4354 case ISD::SETULT: Swap = true;
4355 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4356 case ISD::SETULE: Swap = true;
4357 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4358 }
4359
Nick Lewyckya21d3da2009-07-08 03:04:38 +00004360 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
Bob Wilson2e076c42009-06-22 23:27:02 +00004361 if (Opc == ARMISD::VCEQ) {
4362
4363 SDValue AndOp;
4364 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4365 AndOp = Op0;
4366 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4367 AndOp = Op1;
4368
4369 // Ignore bitconvert.
Wesley Peck527da1b2010-11-23 03:31:01 +00004370 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
Bob Wilson2e076c42009-06-22 23:27:02 +00004371 AndOp = AndOp.getOperand(0);
4372
4373 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4374 Opc = ARMISD::VTST;
Wesley Peck527da1b2010-11-23 03:31:01 +00004375 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
4376 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
Bob Wilson2e076c42009-06-22 23:27:02 +00004377 Invert = !Invert;
4378 }
4379 }
4380 }
4381
4382 if (Swap)
4383 std::swap(Op0, Op1);
4384
Owen Andersonc7baee32010-11-08 23:21:22 +00004385 // If one of the operands is a constant vector zero, attempt to fold the
4386 // comparison to a specialized compare-against-zero form.
4387 SDValue SingleOp;
4388 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4389 SingleOp = Op0;
4390 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4391 if (Opc == ARMISD::VCGE)
4392 Opc = ARMISD::VCLEZ;
4393 else if (Opc == ARMISD::VCGT)
4394 Opc = ARMISD::VCLTZ;
4395 SingleOp = Op1;
4396 }
Wesley Peck527da1b2010-11-23 03:31:01 +00004397
Owen Andersonc7baee32010-11-08 23:21:22 +00004398 SDValue Result;
4399 if (SingleOp.getNode()) {
4400 switch (Opc) {
4401 case ARMISD::VCEQ:
4402 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
4403 case ARMISD::VCGE:
4404 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
4405 case ARMISD::VCLEZ:
4406 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
4407 case ARMISD::VCGT:
4408 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
4409 case ARMISD::VCLTZ:
4410 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
4411 default:
4412 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4413 }
4414 } else {
4415 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4416 }
Bob Wilson2e076c42009-06-22 23:27:02 +00004417
4418 if (Invert)
4419 Result = DAG.getNOT(dl, Result, VT);
4420
4421 return Result;
4422}
4423
Bob Wilson5b2b5042010-06-14 22:19:57 +00004424/// isNEONModifiedImm - Check if the specified splat value corresponds to a
4425/// valid vector constant for a NEON instruction with a "modified immediate"
Bob Wilsona3f19012010-07-13 21:16:48 +00004426/// operand (e.g., VMOV). If so, return the encoded value.
Bob Wilson5b2b5042010-06-14 22:19:57 +00004427static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4428 unsigned SplatBitSize, SelectionDAG &DAG,
Owen Andersona4076922010-11-05 21:57:54 +00004429 EVT &VT, bool is128Bits, NEONModImmType type) {
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004430 unsigned OpCmode, Imm;
Bob Wilson6eae5202010-06-11 21:34:50 +00004431
Bob Wilsonf3f7a772010-06-15 19:05:35 +00004432 // SplatBitSize is set to the smallest size that splats the vector, so a
4433 // zero vector will always have SplatBitSize == 8. However, NEON modified
4434 // immediate instructions others than VMOV do not support the 8-bit encoding
4435 // of a zero vector, and the default encoding of zero is supposed to be the
4436 // 32-bit version.
4437 if (SplatBits == 0)
4438 SplatBitSize = 32;
4439
Bob Wilson2e076c42009-06-22 23:27:02 +00004440 switch (SplatBitSize) {
4441 case 8:
Owen Andersona4076922010-11-05 21:57:54 +00004442 if (type != VMOVModImm)
Bob Wilsonbad47f62010-07-14 06:31:50 +00004443 return SDValue();
Bob Wilson6eae5202010-06-11 21:34:50 +00004444 // Any 1-byte value is OK. Op=0, Cmode=1110.
Bob Wilson2e076c42009-06-22 23:27:02 +00004445 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004446 OpCmode = 0xe;
Bob Wilson6eae5202010-06-11 21:34:50 +00004447 Imm = SplatBits;
Bob Wilsona3f19012010-07-13 21:16:48 +00004448 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
Bob Wilson6eae5202010-06-11 21:34:50 +00004449 break;
Bob Wilson2e076c42009-06-22 23:27:02 +00004450
4451 case 16:
4452 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
Bob Wilsona3f19012010-07-13 21:16:48 +00004453 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
Bob Wilson6eae5202010-06-11 21:34:50 +00004454 if ((SplatBits & ~0xff) == 0) {
4455 // Value = 0x00nn: Op=x, Cmode=100x.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004456 OpCmode = 0x8;
Bob Wilson6eae5202010-06-11 21:34:50 +00004457 Imm = SplatBits;
4458 break;
4459 }
4460 if ((SplatBits & ~0xff00) == 0) {
4461 // Value = 0xnn00: Op=x, Cmode=101x.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004462 OpCmode = 0xa;
Bob Wilson6eae5202010-06-11 21:34:50 +00004463 Imm = SplatBits >> 8;
4464 break;
4465 }
4466 return SDValue();
Bob Wilson2e076c42009-06-22 23:27:02 +00004467
4468 case 32:
4469 // NEON's 32-bit VMOV supports splat values where:
4470 // * only one byte is nonzero, or
4471 // * the least significant byte is 0xff and the second byte is nonzero, or
4472 // * the least significant 2 bytes are 0xff and the third is nonzero.
Bob Wilsona3f19012010-07-13 21:16:48 +00004473 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
Bob Wilson6eae5202010-06-11 21:34:50 +00004474 if ((SplatBits & ~0xff) == 0) {
4475 // Value = 0x000000nn: Op=x, Cmode=000x.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004476 OpCmode = 0;
Bob Wilson6eae5202010-06-11 21:34:50 +00004477 Imm = SplatBits;
4478 break;
4479 }
4480 if ((SplatBits & ~0xff00) == 0) {
4481 // Value = 0x0000nn00: Op=x, Cmode=001x.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004482 OpCmode = 0x2;
Bob Wilson6eae5202010-06-11 21:34:50 +00004483 Imm = SplatBits >> 8;
4484 break;
4485 }
4486 if ((SplatBits & ~0xff0000) == 0) {
4487 // Value = 0x00nn0000: Op=x, Cmode=010x.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004488 OpCmode = 0x4;
Bob Wilson6eae5202010-06-11 21:34:50 +00004489 Imm = SplatBits >> 16;
4490 break;
4491 }
4492 if ((SplatBits & ~0xff000000) == 0) {
4493 // Value = 0xnn000000: Op=x, Cmode=011x.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004494 OpCmode = 0x6;
Bob Wilson6eae5202010-06-11 21:34:50 +00004495 Imm = SplatBits >> 24;
4496 break;
4497 }
Bob Wilson2e076c42009-06-22 23:27:02 +00004498
Owen Andersona4076922010-11-05 21:57:54 +00004499 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4500 if (type == OtherModImm) return SDValue();
4501
Bob Wilson2e076c42009-06-22 23:27:02 +00004502 if ((SplatBits & ~0xffff) == 0 &&
Bob Wilson6eae5202010-06-11 21:34:50 +00004503 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4504 // Value = 0x0000nnff: Op=x, Cmode=1100.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004505 OpCmode = 0xc;
Bob Wilson6eae5202010-06-11 21:34:50 +00004506 Imm = SplatBits >> 8;
Bob Wilson6eae5202010-06-11 21:34:50 +00004507 break;
4508 }
Bob Wilson2e076c42009-06-22 23:27:02 +00004509
4510 if ((SplatBits & ~0xffffff) == 0 &&
Bob Wilson6eae5202010-06-11 21:34:50 +00004511 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4512 // Value = 0x00nnffff: Op=x, Cmode=1101.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004513 OpCmode = 0xd;
Bob Wilson6eae5202010-06-11 21:34:50 +00004514 Imm = SplatBits >> 16;
Bob Wilson6eae5202010-06-11 21:34:50 +00004515 break;
4516 }
Bob Wilson2e076c42009-06-22 23:27:02 +00004517
4518 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4519 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4520 // VMOV.I32. A (very) minor optimization would be to replicate the value
4521 // and fall through here to test for a valid 64-bit splat. But, then the
4522 // caller would also need to check and handle the change in size.
Bob Wilson6eae5202010-06-11 21:34:50 +00004523 return SDValue();
Bob Wilson2e076c42009-06-22 23:27:02 +00004524
4525 case 64: {
Owen Andersona4076922010-11-05 21:57:54 +00004526 if (type != VMOVModImm)
Bob Wilsonf3f7a772010-06-15 19:05:35 +00004527 return SDValue();
Bob Wilsonbad47f62010-07-14 06:31:50 +00004528 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
Bob Wilson2e076c42009-06-22 23:27:02 +00004529 uint64_t BitMask = 0xff;
4530 uint64_t Val = 0;
Bob Wilson6eae5202010-06-11 21:34:50 +00004531 unsigned ImmMask = 1;
4532 Imm = 0;
Bob Wilson2e076c42009-06-22 23:27:02 +00004533 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
Bob Wilson6eae5202010-06-11 21:34:50 +00004534 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
Bob Wilson2e076c42009-06-22 23:27:02 +00004535 Val |= BitMask;
Bob Wilson6eae5202010-06-11 21:34:50 +00004536 Imm |= ImmMask;
4537 } else if ((SplatBits & BitMask) != 0) {
Bob Wilson2e076c42009-06-22 23:27:02 +00004538 return SDValue();
Bob Wilson6eae5202010-06-11 21:34:50 +00004539 }
Bob Wilson2e076c42009-06-22 23:27:02 +00004540 BitMask <<= 8;
Bob Wilson6eae5202010-06-11 21:34:50 +00004541 ImmMask <<= 1;
Bob Wilson2e076c42009-06-22 23:27:02 +00004542 }
Christian Pirker6f81e752014-06-23 18:05:53 +00004543
4544 if (DAG.getTargetLoweringInfo().isBigEndian())
4545 // swap higher and lower 32 bit word
4546 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4547
Bob Wilson6eae5202010-06-11 21:34:50 +00004548 // Op=1, Cmode=1110.
Bob Wilsonc1c6f472010-07-13 04:44:34 +00004549 OpCmode = 0x1e;
Bob Wilsona3f19012010-07-13 21:16:48 +00004550 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
Bob Wilson2e076c42009-06-22 23:27:02 +00004551 break;
4552 }
4553
Bob Wilson6eae5202010-06-11 21:34:50 +00004554 default:
Bob Wilson0ae08932010-06-19 05:32:09 +00004555 llvm_unreachable("unexpected size for isNEONModifiedImm");
Bob Wilson6eae5202010-06-11 21:34:50 +00004556 }
4557
Bob Wilsona3f19012010-07-13 21:16:48 +00004558 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4559 return DAG.getTargetConstant(EncodedVal, MVT::i32);
Bob Wilson2e076c42009-06-22 23:27:02 +00004560}
4561
Lang Hames591cdaf2012-03-29 21:56:11 +00004562SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4563 const ARMSubtarget *ST) const {
Tim Northoverf79c3a52013-08-20 08:57:11 +00004564 if (!ST->hasVFP3())
Lang Hames591cdaf2012-03-29 21:56:11 +00004565 return SDValue();
4566
Tim Northoverf79c3a52013-08-20 08:57:11 +00004567 bool IsDouble = Op.getValueType() == MVT::f64;
Lang Hames591cdaf2012-03-29 21:56:11 +00004568 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
Lang Hames591cdaf2012-03-29 21:56:11 +00004569
4570 // Try splatting with a VMOV.f32...
4571 APFloat FPVal = CFP->getValueAPF();
Tim Northoverf79c3a52013-08-20 08:57:11 +00004572 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4573
Lang Hames591cdaf2012-03-29 21:56:11 +00004574 if (ImmVal != -1) {
Tim Northoverf79c3a52013-08-20 08:57:11 +00004575 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4576 // We have code in place to select a valid ConstantFP already, no need to
4577 // do any mangling.
4578 return Op;
4579 }
4580
4581 // It's a float and we are trying to use NEON operations where
4582 // possible. Lower it to a splat followed by an extract.
Andrew Trickef9de2a2013-05-25 02:42:55 +00004583 SDLoc DL(Op);
Lang Hames591cdaf2012-03-29 21:56:11 +00004584 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4585 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4586 NewVal);
4587 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4588 DAG.getConstant(0, MVT::i32));
4589 }
4590
Tim Northoverf79c3a52013-08-20 08:57:11 +00004591 // The rest of our options are NEON only, make sure that's allowed before
4592 // proceeding..
4593 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4594 return SDValue();
4595
Lang Hames591cdaf2012-03-29 21:56:11 +00004596 EVT VMovVT;
Tim Northoverf79c3a52013-08-20 08:57:11 +00004597 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4598
4599 // It wouldn't really be worth bothering for doubles except for one very
4600 // important value, which does happen to match: 0.0. So make sure we don't do
4601 // anything stupid.
4602 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4603 return SDValue();
4604
4605 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4606 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4607 false, VMOVModImm);
Lang Hames591cdaf2012-03-29 21:56:11 +00004608 if (NewVal != SDValue()) {
Andrew Trickef9de2a2013-05-25 02:42:55 +00004609 SDLoc DL(Op);
Lang Hames591cdaf2012-03-29 21:56:11 +00004610 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4611 NewVal);
Tim Northoverf79c3a52013-08-20 08:57:11 +00004612 if (IsDouble)
4613 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4614
4615 // It's a float: cast and extract a vector element.
Lang Hames591cdaf2012-03-29 21:56:11 +00004616 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4617 VecConstant);
4618 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4619 DAG.getConstant(0, MVT::i32));
4620 }
4621
4622 // Finally, try a VMVN.i32
Tim Northoverf79c3a52013-08-20 08:57:11 +00004623 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4624 false, VMVNModImm);
Lang Hames591cdaf2012-03-29 21:56:11 +00004625 if (NewVal != SDValue()) {
Andrew Trickef9de2a2013-05-25 02:42:55 +00004626 SDLoc DL(Op);
Lang Hames591cdaf2012-03-29 21:56:11 +00004627 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
Tim Northoverf79c3a52013-08-20 08:57:11 +00004628
4629 if (IsDouble)
4630 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4631
4632 // It's a float: cast and extract a vector element.
Lang Hames591cdaf2012-03-29 21:56:11 +00004633 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4634 VecConstant);
4635 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4636 DAG.getConstant(0, MVT::i32));
4637 }
4638
4639 return SDValue();
4640}
4641
Quentin Colombet8e1fe842012-11-02 21:32:17 +00004642// check if an VEXT instruction can handle the shuffle mask when the
4643// vector sources of the shuffle are the same.
4644static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4645 unsigned NumElts = VT.getVectorNumElements();
4646
4647 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4648 if (M[0] < 0)
4649 return false;
4650
4651 Imm = M[0];
4652
4653 // If this is a VEXT shuffle, the immediate value is the index of the first
4654 // element. The other shuffle indices must be the successive elements after
4655 // the first one.
4656 unsigned ExpectedElt = Imm;
4657 for (unsigned i = 1; i < NumElts; ++i) {
4658 // Increment the expected index. If it wraps around, just follow it
4659 // back to index zero and keep going.
4660 ++ExpectedElt;
4661 if (ExpectedElt == NumElts)
4662 ExpectedElt = 0;
4663
4664 if (M[i] < 0) continue; // ignore UNDEF indices
4665 if (ExpectedElt != static_cast<unsigned>(M[i]))
4666 return false;
4667 }
4668
4669 return true;
4670}
4671
Lang Hames591cdaf2012-03-29 21:56:11 +00004672
Benjamin Kramer339ced42012-01-15 13:16:05 +00004673static bool isVEXTMask(ArrayRef<int> M, EVT VT,
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00004674 bool &ReverseVEXT, unsigned &Imm) {
Bob Wilson32cd8552009-08-19 17:03:43 +00004675 unsigned NumElts = VT.getVectorNumElements();
4676 ReverseVEXT = false;
Bob Wilson411dfad2010-08-17 05:54:34 +00004677
4678 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4679 if (M[0] < 0)
4680 return false;
4681
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00004682 Imm = M[0];
Bob Wilson32cd8552009-08-19 17:03:43 +00004683
4684 // If this is a VEXT shuffle, the immediate value is the index of the first
4685 // element. The other shuffle indices must be the successive elements after
4686 // the first one.
4687 unsigned ExpectedElt = Imm;
4688 for (unsigned i = 1; i < NumElts; ++i) {
Bob Wilson32cd8552009-08-19 17:03:43 +00004689 // Increment the expected index. If it wraps around, it may still be
4690 // a VEXT but the source vectors must be swapped.
4691 ExpectedElt += 1;
4692 if (ExpectedElt == NumElts * 2) {
4693 ExpectedElt = 0;
4694 ReverseVEXT = true;
4695 }
4696
Bob Wilson411dfad2010-08-17 05:54:34 +00004697 if (M[i] < 0) continue; // ignore UNDEF indices
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00004698 if (ExpectedElt != static_cast<unsigned>(M[i]))
Bob Wilson32cd8552009-08-19 17:03:43 +00004699 return false;
4700 }
4701
4702 // Adjust the index value if the source operands will be swapped.
4703 if (ReverseVEXT)
4704 Imm -= NumElts;
4705
Bob Wilson32cd8552009-08-19 17:03:43 +00004706 return true;
4707}
4708
Bob Wilson8a37bbe2009-07-26 00:39:34 +00004709/// isVREVMask - Check if a vector shuffle corresponds to a VREV
4710/// instruction with the specified blocksize. (The order of the elements
4711/// within each block of the vector is reversed.)
Benjamin Kramer339ced42012-01-15 13:16:05 +00004712static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
Bob Wilson8a37bbe2009-07-26 00:39:34 +00004713 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4714 "Only possible block sizes for VREV are: 16, 32, 64");
4715
Bob Wilson8a37bbe2009-07-26 00:39:34 +00004716 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
Bob Wilson854530a2009-10-21 21:36:27 +00004717 if (EltSz == 64)
4718 return false;
4719
4720 unsigned NumElts = VT.getVectorNumElements();
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00004721 unsigned BlockElts = M[0] + 1;
Bob Wilson411dfad2010-08-17 05:54:34 +00004722 // If the first shuffle index is UNDEF, be optimistic.
4723 if (M[0] < 0)
4724 BlockElts = BlockSize / EltSz;
Bob Wilson8a37bbe2009-07-26 00:39:34 +00004725
4726 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4727 return false;
4728
4729 for (unsigned i = 0; i < NumElts; ++i) {
Bob Wilson411dfad2010-08-17 05:54:34 +00004730 if (M[i] < 0) continue; // ignore UNDEF indices
4731 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
Bob Wilson8a37bbe2009-07-26 00:39:34 +00004732 return false;
4733 }
4734
4735 return true;
4736}
4737
Benjamin Kramer339ced42012-01-15 13:16:05 +00004738static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
Bill Wendling865f8b52011-03-15 21:15:20 +00004739 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4740 // range, then 0 is placed into the resulting vector. So pretty much any mask
4741 // of 8 elements can work here.
4742 return VT == MVT::v8i8 && M.size() == 8;
4743}
4744
Benjamin Kramer339ced42012-01-15 13:16:05 +00004745static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
Bob Wilson854530a2009-10-21 21:36:27 +00004746 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4747 if (EltSz == 64)
4748 return false;
4749
Bob Wilsona7062312009-08-21 20:54:19 +00004750 unsigned NumElts = VT.getVectorNumElements();
4751 WhichResult = (M[0] == 0 ? 0 : 1);
4752 for (unsigned i = 0; i < NumElts; i += 2) {
Bob Wilson411dfad2010-08-17 05:54:34 +00004753 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4754 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
Bob Wilsona7062312009-08-21 20:54:19 +00004755 return false;
4756 }
4757 return true;
4758}
4759
Bob Wilson0bbd3072009-12-03 06:40:55 +00004760/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4761/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4762/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
Benjamin Kramer339ced42012-01-15 13:16:05 +00004763static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
Bob Wilson0bbd3072009-12-03 06:40:55 +00004764 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4765 if (EltSz == 64)
4766 return false;
4767
4768 unsigned NumElts = VT.getVectorNumElements();
4769 WhichResult = (M[0] == 0 ? 0 : 1);
4770 for (unsigned i = 0; i < NumElts; i += 2) {
Bob Wilson411dfad2010-08-17 05:54:34 +00004771 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4772 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
Bob Wilson0bbd3072009-12-03 06:40:55 +00004773 return false;
4774 }
4775 return true;
4776}
4777
Benjamin Kramer339ced42012-01-15 13:16:05 +00004778static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
Bob Wilson854530a2009-10-21 21:36:27 +00004779 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4780 if (EltSz == 64)
4781 return false;
4782
Bob Wilsona7062312009-08-21 20:54:19 +00004783 unsigned NumElts = VT.getVectorNumElements();
4784 WhichResult = (M[0] == 0 ? 0 : 1);
4785 for (unsigned i = 0; i != NumElts; ++i) {
Bob Wilson411dfad2010-08-17 05:54:34 +00004786 if (M[i] < 0) continue; // ignore UNDEF indices
Bob Wilsona7062312009-08-21 20:54:19 +00004787 if ((unsigned) M[i] != 2 * i + WhichResult)
4788 return false;
4789 }
4790
4791 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
Bob Wilson854530a2009-10-21 21:36:27 +00004792 if (VT.is64BitVector() && EltSz == 32)
Bob Wilsona7062312009-08-21 20:54:19 +00004793 return false;
4794
4795 return true;
4796}
4797
Bob Wilson0bbd3072009-12-03 06:40:55 +00004798/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4799/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4800/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
Benjamin Kramer339ced42012-01-15 13:16:05 +00004801static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
Bob Wilson0bbd3072009-12-03 06:40:55 +00004802 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4803 if (EltSz == 64)
4804 return false;
4805
4806 unsigned Half = VT.getVectorNumElements() / 2;
4807 WhichResult = (M[0] == 0 ? 0 : 1);
4808 for (unsigned j = 0; j != 2; ++j) {
4809 unsigned Idx = WhichResult;
4810 for (unsigned i = 0; i != Half; ++i) {
Bob Wilson411dfad2010-08-17 05:54:34 +00004811 int MIdx = M[i + j * Half];
4812 if (MIdx >= 0 && (unsigned) MIdx != Idx)
Bob Wilson0bbd3072009-12-03 06:40:55 +00004813 return false;
4814 Idx += 2;
4815 }
4816 }
4817
4818 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4819 if (VT.is64BitVector() && EltSz == 32)
4820 return false;
4821
4822 return true;
4823}
4824
Benjamin Kramer339ced42012-01-15 13:16:05 +00004825static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
Bob Wilson854530a2009-10-21 21:36:27 +00004826 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4827 if (EltSz == 64)
4828 return false;
4829
Bob Wilsona7062312009-08-21 20:54:19 +00004830 unsigned NumElts = VT.getVectorNumElements();
4831 WhichResult = (M[0] == 0 ? 0 : 1);
4832 unsigned Idx = WhichResult * NumElts / 2;
4833 for (unsigned i = 0; i != NumElts; i += 2) {
Bob Wilson411dfad2010-08-17 05:54:34 +00004834 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4835 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
Bob Wilsona7062312009-08-21 20:54:19 +00004836 return false;
4837 Idx += 1;
4838 }
4839
4840 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
Bob Wilson854530a2009-10-21 21:36:27 +00004841 if (VT.is64BitVector() && EltSz == 32)
Bob Wilsona7062312009-08-21 20:54:19 +00004842 return false;
4843
4844 return true;
4845}
4846
Bob Wilson0bbd3072009-12-03 06:40:55 +00004847/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
4848/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4849/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
Benjamin Kramer339ced42012-01-15 13:16:05 +00004850static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
Bob Wilson0bbd3072009-12-03 06:40:55 +00004851 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4852 if (EltSz == 64)
4853 return false;
4854
4855 unsigned NumElts = VT.getVectorNumElements();
4856 WhichResult = (M[0] == 0 ? 0 : 1);
4857 unsigned Idx = WhichResult * NumElts / 2;
4858 for (unsigned i = 0; i != NumElts; i += 2) {
Bob Wilson411dfad2010-08-17 05:54:34 +00004859 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4860 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
Bob Wilson0bbd3072009-12-03 06:40:55 +00004861 return false;
4862 Idx += 1;
4863 }
4864
4865 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4866 if (VT.is64BitVector() && EltSz == 32)
4867 return false;
4868
4869 return true;
4870}
4871
Arnold Schwaighofer1f3d3ca2013-02-12 01:58:32 +00004872/// \return true if this is a reverse operation on an vector.
4873static bool isReverseMask(ArrayRef<int> M, EVT VT) {
4874 unsigned NumElts = VT.getVectorNumElements();
4875 // Make sure the mask has the right size.
4876 if (NumElts != M.size())
4877 return false;
4878
4879 // Look for <15, ..., 3, -1, 1, 0>.
4880 for (unsigned i = 0; i != NumElts; ++i)
4881 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
4882 return false;
4883
4884 return true;
4885}
4886
Dale Johannesen2bff5052010-07-29 20:10:08 +00004887// If N is an integer constant that can be moved into a register in one
4888// instruction, return an SDValue of such a constant (will become a MOV
4889// instruction). Otherwise return null.
4890static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00004891 const ARMSubtarget *ST, SDLoc dl) {
Dale Johannesen2bff5052010-07-29 20:10:08 +00004892 uint64_t Val;
4893 if (!isa<ConstantSDNode>(N))
4894 return SDValue();
4895 Val = cast<ConstantSDNode>(N)->getZExtValue();
4896
4897 if (ST->isThumb1Only()) {
4898 if (Val <= 255 || ~Val <= 255)
4899 return DAG.getConstant(Val, MVT::i32);
4900 } else {
4901 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
4902 return DAG.getConstant(Val, MVT::i32);
4903 }
4904 return SDValue();
4905}
4906
Bob Wilson2e076c42009-06-22 23:27:02 +00004907// If this is a case we can't handle, return null and let the default
4908// expansion code take care of it.
Bob Wilson6f2b8962011-01-07 21:37:30 +00004909SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4910 const ARMSubtarget *ST) const {
Bob Wilsonfcd63612009-08-13 01:57:47 +00004911 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
Andrew Trickef9de2a2013-05-25 02:42:55 +00004912 SDLoc dl(Op);
Owen Anderson53aa7a92009-08-10 22:56:29 +00004913 EVT VT = Op.getValueType();
Bob Wilson2e076c42009-06-22 23:27:02 +00004914
4915 APInt SplatBits, SplatUndef;
4916 unsigned SplatBitSize;
4917 bool HasAnyUndefs;
4918 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
Anton Korobeynikovece642a2009-08-29 00:08:18 +00004919 if (SplatBitSize <= 64) {
Bob Wilson5b2b5042010-06-14 22:19:57 +00004920 // Check if an immediate VMOV works.
Bob Wilsona3f19012010-07-13 21:16:48 +00004921 EVT VmovVT;
Bob Wilson5b2b5042010-06-14 22:19:57 +00004922 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
Bob Wilsona3f19012010-07-13 21:16:48 +00004923 SplatUndef.getZExtValue(), SplatBitSize,
Owen Andersona4076922010-11-05 21:57:54 +00004924 DAG, VmovVT, VT.is128BitVector(),
4925 VMOVModImm);
Bob Wilsona3f19012010-07-13 21:16:48 +00004926 if (Val.getNode()) {
4927 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
Wesley Peck527da1b2010-11-23 03:31:01 +00004928 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
Bob Wilsona3f19012010-07-13 21:16:48 +00004929 }
Bob Wilsonbad47f62010-07-14 06:31:50 +00004930
4931 // Try an immediate VMVN.
Eli Friedmanaa6ec392011-10-13 22:40:23 +00004932 uint64_t NegatedImm = (~SplatBits).getZExtValue();
Bob Wilsonbad47f62010-07-14 06:31:50 +00004933 Val = isNEONModifiedImm(NegatedImm,
4934 SplatUndef.getZExtValue(), SplatBitSize,
Wesley Peck527da1b2010-11-23 03:31:01 +00004935 DAG, VmovVT, VT.is128BitVector(),
Owen Andersona4076922010-11-05 21:57:54 +00004936 VMVNModImm);
Bob Wilsonbad47f62010-07-14 06:31:50 +00004937 if (Val.getNode()) {
4938 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
Wesley Peck527da1b2010-11-23 03:31:01 +00004939 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
Bob Wilsonbad47f62010-07-14 06:31:50 +00004940 }
Evan Cheng7ca4b6e2011-11-15 02:12:34 +00004941
4942 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
Eli Friedmanc9bf1b12011-12-15 22:56:53 +00004943 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
Eli Friedman4e36a932011-12-09 23:54:42 +00004944 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
Evan Cheng7ca4b6e2011-11-15 02:12:34 +00004945 if (ImmVal != -1) {
4946 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4947 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4948 }
4949 }
Anton Korobeynikovece642a2009-08-29 00:08:18 +00004950 }
Bob Wilson0dbdec82009-07-30 00:31:25 +00004951 }
4952
Bob Wilson91fdf682010-05-22 00:23:12 +00004953 // Scan through the operands to see if only one value is used.
James Molloy49bdbce2012-09-06 09:55:02 +00004954 //
4955 // As an optimisation, even if more than one value is used it may be more
4956 // profitable to splat with one value then change some lanes.
4957 //
4958 // Heuristically we decide to do this if the vector has a "dominant" value,
4959 // defined as splatted to more than half of the lanes.
Bob Wilson91fdf682010-05-22 00:23:12 +00004960 unsigned NumElts = VT.getVectorNumElements();
4961 bool isOnlyLowElement = true;
4962 bool usesOnlyOneValue = true;
James Molloy49bdbce2012-09-06 09:55:02 +00004963 bool hasDominantValue = false;
Bob Wilson91fdf682010-05-22 00:23:12 +00004964 bool isConstant = true;
James Molloy49bdbce2012-09-06 09:55:02 +00004965
4966 // Map of the number of times a particular SDValue appears in the
4967 // element list.
James Molloy9d30dc22012-09-06 10:32:08 +00004968 DenseMap<SDValue, unsigned> ValueCounts;
Bob Wilson91fdf682010-05-22 00:23:12 +00004969 SDValue Value;
4970 for (unsigned i = 0; i < NumElts; ++i) {
4971 SDValue V = Op.getOperand(i);
4972 if (V.getOpcode() == ISD::UNDEF)
4973 continue;
4974 if (i > 0)
4975 isOnlyLowElement = false;
4976 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4977 isConstant = false;
4978
James Molloy49bdbce2012-09-06 09:55:02 +00004979 ValueCounts.insert(std::make_pair(V, 0));
James Molloy9d30dc22012-09-06 10:32:08 +00004980 unsigned &Count = ValueCounts[V];
Jim Grosbach54efea02013-03-02 20:16:15 +00004981
James Molloy49bdbce2012-09-06 09:55:02 +00004982 // Is this value dominant? (takes up more than half of the lanes)
4983 if (++Count > (NumElts / 2)) {
4984 hasDominantValue = true;
Bob Wilson91fdf682010-05-22 00:23:12 +00004985 Value = V;
James Molloy49bdbce2012-09-06 09:55:02 +00004986 }
Bob Wilson91fdf682010-05-22 00:23:12 +00004987 }
James Molloy49bdbce2012-09-06 09:55:02 +00004988 if (ValueCounts.size() != 1)
4989 usesOnlyOneValue = false;
4990 if (!Value.getNode() && ValueCounts.size() > 0)
4991 Value = ValueCounts.begin()->first;
Bob Wilson91fdf682010-05-22 00:23:12 +00004992
James Molloy49bdbce2012-09-06 09:55:02 +00004993 if (ValueCounts.size() == 0)
Bob Wilson91fdf682010-05-22 00:23:12 +00004994 return DAG.getUNDEF(VT);
4995
Quentin Colombet0f2fe742013-07-23 22:34:47 +00004996 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
4997 // Keep going if we are hitting this case.
4998 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
Bob Wilson91fdf682010-05-22 00:23:12 +00004999 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5000
Dale Johannesen2bff5052010-07-29 20:10:08 +00005001 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5002
Dale Johannesen710a2d92010-10-19 20:00:17 +00005003 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5004 // i32 and try again.
James Molloy49bdbce2012-09-06 09:55:02 +00005005 if (hasDominantValue && EltSize <= 32) {
5006 if (!isConstant) {
5007 SDValue N;
5008
5009 // If we are VDUPing a value that comes directly from a vector, that will
5010 // cause an unnecessary move to and from a GPR, where instead we could
Jim Grosbacha3c5c762013-03-02 20:16:24 +00005011 // just use VDUPLANE. We can only do this if the lane being extracted
5012 // is at a constant index, as the VDUP from lane instructions only have
5013 // constant-index forms.
5014 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5015 isa<ConstantSDNode>(Value->getOperand(1))) {
Silviu Barangab1409702012-10-15 09:41:32 +00005016 // We need to create a new undef vector to use for the VDUPLANE if the
5017 // size of the vector from which we get the value is different than the
5018 // size of the vector that we need to create. We will insert the element
5019 // such that the register coalescer will remove unnecessary copies.
5020 if (VT != Value->getOperand(0).getValueType()) {
5021 ConstantSDNode *constIndex;
5022 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5023 assert(constIndex && "The index is not a constant!");
5024 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5025 VT.getVectorNumElements();
5026 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5027 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5028 Value, DAG.getConstant(index, MVT::i32)),
5029 DAG.getConstant(index, MVT::i32));
Jim Grosbachc6f19142013-03-02 20:16:19 +00005030 } else
Silviu Barangab1409702012-10-15 09:41:32 +00005031 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
James Molloy49bdbce2012-09-06 09:55:02 +00005032 Value->getOperand(0), Value->getOperand(1));
Jim Grosbachc6f19142013-03-02 20:16:19 +00005033 } else
James Molloy49bdbce2012-09-06 09:55:02 +00005034 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5035
5036 if (!usesOnlyOneValue) {
5037 // The dominant value was splatted as 'N', but we now have to insert
5038 // all differing elements.
5039 for (unsigned I = 0; I < NumElts; ++I) {
5040 if (Op.getOperand(I) == Value)
5041 continue;
5042 SmallVector<SDValue, 3> Ops;
5043 Ops.push_back(N);
5044 Ops.push_back(Op.getOperand(I));
5045 Ops.push_back(DAG.getConstant(I, MVT::i32));
Craig Topper48d114b2014-04-26 18:35:24 +00005046 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
James Molloy49bdbce2012-09-06 09:55:02 +00005047 }
5048 }
5049 return N;
5050 }
Dale Johannesen710a2d92010-10-19 20:00:17 +00005051 if (VT.getVectorElementType().isFloatingPoint()) {
5052 SmallVector<SDValue, 8> Ops;
5053 for (unsigned i = 0; i < NumElts; ++i)
Wesley Peck527da1b2010-11-23 03:31:01 +00005054 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
Dale Johannesen710a2d92010-10-19 20:00:17 +00005055 Op.getOperand(i)));
Nate Begemanca524112010-11-10 21:35:41 +00005056 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
Craig Topper48d114b2014-04-26 18:35:24 +00005057 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
Dale Johannesenff376752010-10-20 22:03:37 +00005058 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5059 if (Val.getNode())
Wesley Peck527da1b2010-11-23 03:31:01 +00005060 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
Dale Johannesen2bff5052010-07-29 20:10:08 +00005061 }
James Molloy49bdbce2012-09-06 09:55:02 +00005062 if (usesOnlyOneValue) {
5063 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5064 if (isConstant && Val.getNode())
Jim Grosbach54efea02013-03-02 20:16:15 +00005065 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
James Molloy49bdbce2012-09-06 09:55:02 +00005066 }
Dale Johannesen2bff5052010-07-29 20:10:08 +00005067 }
5068
5069 // If all elements are constants and the case above didn't get hit, fall back
5070 // to the default expansion, which will generate a load from the constant
5071 // pool.
Bob Wilson91fdf682010-05-22 00:23:12 +00005072 if (isConstant)
5073 return SDValue();
5074
Bob Wilson6f2b8962011-01-07 21:37:30 +00005075 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5076 if (NumElts >= 4) {
5077 SDValue shuffle = ReconstructShuffle(Op, DAG);
5078 if (shuffle != SDValue())
5079 return shuffle;
5080 }
5081
Bob Wilson91fdf682010-05-22 00:23:12 +00005082 // Vectors with 32- or 64-bit elements can be built by directly assigning
Bob Wilsond8a9a042010-06-04 00:04:02 +00005083 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5084 // will be legalized.
Bob Wilson91fdf682010-05-22 00:23:12 +00005085 if (EltSize >= 32) {
5086 // Do the expansion with floating-point types, since that is what the VFP
5087 // registers are defined to use, and since i64 is not legal.
5088 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5089 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
Bob Wilsond8a9a042010-06-04 00:04:02 +00005090 SmallVector<SDValue, 8> Ops;
5091 for (unsigned i = 0; i < NumElts; ++i)
Wesley Peck527da1b2010-11-23 03:31:01 +00005092 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
Craig Topper48d114b2014-04-26 18:35:24 +00005093 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
Wesley Peck527da1b2010-11-23 03:31:01 +00005094 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
Bob Wilson2e076c42009-06-22 23:27:02 +00005095 }
5096
Jim Grosbach24e102a2013-07-08 18:18:52 +00005097 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5098 // know the default expansion would otherwise fall back on something even
5099 // worse. For a vector with one or two non-undef values, that's
5100 // scalar_to_vector for the elements followed by a shuffle (provided the
5101 // shuffle is valid for the target) and materialization element by element
5102 // on the stack followed by a load for everything else.
5103 if (!isConstant && !usesOnlyOneValue) {
5104 SDValue Vec = DAG.getUNDEF(VT);
5105 for (unsigned i = 0 ; i < NumElts; ++i) {
5106 SDValue V = Op.getOperand(i);
5107 if (V.getOpcode() == ISD::UNDEF)
5108 continue;
5109 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
5110 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5111 }
5112 return Vec;
5113 }
5114
Bob Wilson2e076c42009-06-22 23:27:02 +00005115 return SDValue();
5116}
5117
Bob Wilson6f2b8962011-01-07 21:37:30 +00005118// Gather data to see if the operation can be modelled as a
Andrew Trick5eb0a302011-01-19 02:26:13 +00005119// shuffle in combination with VEXTs.
Eric Christopher2af95512011-01-14 23:50:53 +00005120SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5121 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00005122 SDLoc dl(Op);
Bob Wilson6f2b8962011-01-07 21:37:30 +00005123 EVT VT = Op.getValueType();
5124 unsigned NumElts = VT.getVectorNumElements();
5125
5126 SmallVector<SDValue, 2> SourceVecs;
5127 SmallVector<unsigned, 2> MinElts;
5128 SmallVector<unsigned, 2> MaxElts;
Andrew Trick5eb0a302011-01-19 02:26:13 +00005129
Bob Wilson6f2b8962011-01-07 21:37:30 +00005130 for (unsigned i = 0; i < NumElts; ++i) {
5131 SDValue V = Op.getOperand(i);
5132 if (V.getOpcode() == ISD::UNDEF)
5133 continue;
5134 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5135 // A shuffle can only come from building a vector from various
5136 // elements of other vectors.
5137 return SDValue();
Eli Friedman74d1da52011-10-14 23:58:49 +00005138 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5139 VT.getVectorElementType()) {
5140 // This code doesn't know how to handle shuffles where the vector
5141 // element types do not match (this happens because type legalization
5142 // promotes the return type of EXTRACT_VECTOR_ELT).
5143 // FIXME: It might be appropriate to extend this code to handle
5144 // mismatched types.
5145 return SDValue();
Bob Wilson6f2b8962011-01-07 21:37:30 +00005146 }
Andrew Trick5eb0a302011-01-19 02:26:13 +00005147
Bob Wilson6f2b8962011-01-07 21:37:30 +00005148 // Record this extraction against the appropriate vector if possible...
5149 SDValue SourceVec = V.getOperand(0);
Jim Grosbach6df755c2012-07-25 17:02:47 +00005150 // If the element number isn't a constant, we can't effectively
5151 // analyze what's going on.
5152 if (!isa<ConstantSDNode>(V.getOperand(1)))
5153 return SDValue();
Bob Wilson6f2b8962011-01-07 21:37:30 +00005154 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5155 bool FoundSource = false;
5156 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5157 if (SourceVecs[j] == SourceVec) {
5158 if (MinElts[j] > EltNo)
5159 MinElts[j] = EltNo;
5160 if (MaxElts[j] < EltNo)
5161 MaxElts[j] = EltNo;
5162 FoundSource = true;
5163 break;
5164 }
5165 }
Andrew Trick5eb0a302011-01-19 02:26:13 +00005166
Bob Wilson6f2b8962011-01-07 21:37:30 +00005167 // Or record a new source if not...
5168 if (!FoundSource) {
5169 SourceVecs.push_back(SourceVec);
5170 MinElts.push_back(EltNo);
5171 MaxElts.push_back(EltNo);
5172 }
5173 }
Andrew Trick5eb0a302011-01-19 02:26:13 +00005174
Bob Wilson6f2b8962011-01-07 21:37:30 +00005175 // Currently only do something sane when at most two source vectors
5176 // involved.
5177 if (SourceVecs.size() > 2)
5178 return SDValue();
5179
5180 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5181 int VEXTOffsets[2] = {0, 0};
Andrew Trick5eb0a302011-01-19 02:26:13 +00005182
Bob Wilson6f2b8962011-01-07 21:37:30 +00005183 // This loop extracts the usage patterns of the source vectors
5184 // and prepares appropriate SDValues for a shuffle if possible.
5185 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5186 if (SourceVecs[i].getValueType() == VT) {
5187 // No VEXT necessary
5188 ShuffleSrcs[i] = SourceVecs[i];
5189 VEXTOffsets[i] = 0;
5190 continue;
5191 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5192 // It probably isn't worth padding out a smaller vector just to
5193 // break it down again in a shuffle.
5194 return SDValue();
5195 }
Andrew Trick5eb0a302011-01-19 02:26:13 +00005196
Bob Wilson6f2b8962011-01-07 21:37:30 +00005197 // Since only 64-bit and 128-bit vectors are legal on ARM and
5198 // we've eliminated the other cases...
Bob Wilson3fa9c062011-01-07 23:40:46 +00005199 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5200 "unexpected vector sizes in ReconstructShuffle");
Andrew Trick5eb0a302011-01-19 02:26:13 +00005201
Bob Wilson6f2b8962011-01-07 21:37:30 +00005202 if (MaxElts[i] - MinElts[i] >= NumElts) {
5203 // Span too large for a VEXT to cope
5204 return SDValue();
Andrew Trick5eb0a302011-01-19 02:26:13 +00005205 }
5206
Bob Wilson6f2b8962011-01-07 21:37:30 +00005207 if (MinElts[i] >= NumElts) {
5208 // The extraction can just take the second half
5209 VEXTOffsets[i] = NumElts;
Eric Christopher2af95512011-01-14 23:50:53 +00005210 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5211 SourceVecs[i],
Bob Wilson6f2b8962011-01-07 21:37:30 +00005212 DAG.getIntPtrConstant(NumElts));
5213 } else if (MaxElts[i] < NumElts) {
5214 // The extraction can just take the first half
5215 VEXTOffsets[i] = 0;
Eric Christopher2af95512011-01-14 23:50:53 +00005216 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5217 SourceVecs[i],
Bob Wilson6f2b8962011-01-07 21:37:30 +00005218 DAG.getIntPtrConstant(0));
5219 } else {
5220 // An actual VEXT is needed
5221 VEXTOffsets[i] = MinElts[i];
Eric Christopher2af95512011-01-14 23:50:53 +00005222 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5223 SourceVecs[i],
Bob Wilson6f2b8962011-01-07 21:37:30 +00005224 DAG.getIntPtrConstant(0));
Eric Christopher2af95512011-01-14 23:50:53 +00005225 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5226 SourceVecs[i],
Bob Wilson6f2b8962011-01-07 21:37:30 +00005227 DAG.getIntPtrConstant(NumElts));
5228 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5229 DAG.getConstant(VEXTOffsets[i], MVT::i32));
5230 }
5231 }
Andrew Trick5eb0a302011-01-19 02:26:13 +00005232
Bob Wilson6f2b8962011-01-07 21:37:30 +00005233 SmallVector<int, 8> Mask;
Andrew Trick5eb0a302011-01-19 02:26:13 +00005234
Bob Wilson6f2b8962011-01-07 21:37:30 +00005235 for (unsigned i = 0; i < NumElts; ++i) {
5236 SDValue Entry = Op.getOperand(i);
5237 if (Entry.getOpcode() == ISD::UNDEF) {
5238 Mask.push_back(-1);
5239 continue;
5240 }
Andrew Trick5eb0a302011-01-19 02:26:13 +00005241
Bob Wilson6f2b8962011-01-07 21:37:30 +00005242 SDValue ExtractVec = Entry.getOperand(0);
Eric Christopher2af95512011-01-14 23:50:53 +00005243 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5244 .getOperand(1))->getSExtValue();
Bob Wilson6f2b8962011-01-07 21:37:30 +00005245 if (ExtractVec == SourceVecs[0]) {
5246 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5247 } else {
5248 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5249 }
5250 }
Andrew Trick5eb0a302011-01-19 02:26:13 +00005251
Bob Wilson6f2b8962011-01-07 21:37:30 +00005252 // Final check before we try to produce nonsense...
5253 if (isShuffleMaskLegal(Mask, VT))
Eric Christopher2af95512011-01-14 23:50:53 +00005254 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5255 &Mask[0]);
Andrew Trick5eb0a302011-01-19 02:26:13 +00005256
Bob Wilson6f2b8962011-01-07 21:37:30 +00005257 return SDValue();
5258}
5259
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00005260/// isShuffleMaskLegal - Targets can use this to indicate that they only
5261/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5262/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5263/// are assumed to be legal.
5264bool
5265ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5266 EVT VT) const {
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005267 if (VT.getVectorNumElements() == 4 &&
5268 (VT.is128BitVector() || VT.is64BitVector())) {
5269 unsigned PFIndexes[4];
5270 for (unsigned i = 0; i != 4; ++i) {
5271 if (M[i] < 0)
5272 PFIndexes[i] = 8;
5273 else
5274 PFIndexes[i] = M[i];
5275 }
5276
5277 // Compute the index in the perfect shuffle table.
5278 unsigned PFTableIndex =
5279 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5280 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5281 unsigned Cost = (PFEntry >> 30);
5282
5283 if (Cost <= 4)
5284 return true;
5285 }
5286
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00005287 bool ReverseVEXT;
Bob Wilsona7062312009-08-21 20:54:19 +00005288 unsigned Imm, WhichResult;
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00005289
Bob Wilson846bd792010-06-07 23:53:38 +00005290 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5291 return (EltSize >= 32 ||
5292 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00005293 isVREVMask(M, VT, 64) ||
5294 isVREVMask(M, VT, 32) ||
5295 isVREVMask(M, VT, 16) ||
Bob Wilsona7062312009-08-21 20:54:19 +00005296 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
Bill Wendling865f8b52011-03-15 21:15:20 +00005297 isVTBLMask(M, VT) ||
Bob Wilsona7062312009-08-21 20:54:19 +00005298 isVTRNMask(M, VT, WhichResult) ||
5299 isVUZPMask(M, VT, WhichResult) ||
Bob Wilson0bbd3072009-12-03 06:40:55 +00005300 isVZIPMask(M, VT, WhichResult) ||
5301 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5302 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
Arnold Schwaighofer1f3d3ca2013-02-12 01:58:32 +00005303 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5304 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00005305}
5306
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005307/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5308/// the specified operations to build the shuffle.
5309static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5310 SDValue RHS, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00005311 SDLoc dl) {
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005312 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5313 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5314 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5315
5316 enum {
5317 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5318 OP_VREV,
5319 OP_VDUP0,
5320 OP_VDUP1,
5321 OP_VDUP2,
5322 OP_VDUP3,
5323 OP_VEXT1,
5324 OP_VEXT2,
5325 OP_VEXT3,
5326 OP_VUZPL, // VUZP, left result
5327 OP_VUZPR, // VUZP, right result
5328 OP_VZIPL, // VZIP, left result
5329 OP_VZIPR, // VZIP, right result
5330 OP_VTRNL, // VTRN, left result
5331 OP_VTRNR // VTRN, right result
5332 };
5333
5334 if (OpNum == OP_COPY) {
5335 if (LHSID == (1*9+2)*9+3) return LHS;
5336 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5337 return RHS;
5338 }
5339
5340 SDValue OpLHS, OpRHS;
5341 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5342 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5343 EVT VT = OpLHS.getValueType();
5344
5345 switch (OpNum) {
5346 default: llvm_unreachable("Unknown shuffle opcode!");
5347 case OP_VREV:
Tanya Lattner48b182c2011-05-18 06:42:21 +00005348 // VREV divides the vector in half and swaps within the half.
Tanya Lattner1d117202011-05-18 21:44:54 +00005349 if (VT.getVectorElementType() == MVT::i32 ||
5350 VT.getVectorElementType() == MVT::f32)
Tanya Lattner48b182c2011-05-18 06:42:21 +00005351 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5352 // vrev <4 x i16> -> VREV32
5353 if (VT.getVectorElementType() == MVT::i16)
5354 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5355 // vrev <4 x i8> -> VREV16
5356 assert(VT.getVectorElementType() == MVT::i8);
5357 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005358 case OP_VDUP0:
5359 case OP_VDUP1:
5360 case OP_VDUP2:
5361 case OP_VDUP3:
5362 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
Anton Korobeynikov232b19c2009-08-21 12:41:42 +00005363 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005364 case OP_VEXT1:
5365 case OP_VEXT2:
5366 case OP_VEXT3:
5367 return DAG.getNode(ARMISD::VEXT, dl, VT,
5368 OpLHS, OpRHS,
5369 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5370 case OP_VUZPL:
5371 case OP_VUZPR:
Anton Korobeynikov232b19c2009-08-21 12:41:42 +00005372 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005373 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5374 case OP_VZIPL:
5375 case OP_VZIPR:
Anton Korobeynikov232b19c2009-08-21 12:41:42 +00005376 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005377 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5378 case OP_VTRNL:
5379 case OP_VTRNR:
Anton Korobeynikov232b19c2009-08-21 12:41:42 +00005380 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5381 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005382 }
5383}
5384
Bill Wendlinge1fd78f2011-03-14 23:02:38 +00005385static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
Benjamin Kramer339ced42012-01-15 13:16:05 +00005386 ArrayRef<int> ShuffleMask,
Bill Wendlinge1fd78f2011-03-14 23:02:38 +00005387 SelectionDAG &DAG) {
5388 // Check to see if we can use the VTBL instruction.
5389 SDValue V1 = Op.getOperand(0);
5390 SDValue V2 = Op.getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +00005391 SDLoc DL(Op);
Bill Wendlinge1fd78f2011-03-14 23:02:38 +00005392
5393 SmallVector<SDValue, 8> VTBLMask;
Benjamin Kramer339ced42012-01-15 13:16:05 +00005394 for (ArrayRef<int>::iterator
Bill Wendlinge1fd78f2011-03-14 23:02:38 +00005395 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5396 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5397
5398 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5399 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
Craig Topper48d114b2014-04-26 18:35:24 +00005400 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
Bill Wendlingebecb332011-03-15 20:47:26 +00005401
Owen Anderson77aa2662011-04-05 21:48:57 +00005402 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
Craig Topper48d114b2014-04-26 18:35:24 +00005403 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
Bill Wendlinge1fd78f2011-03-14 23:02:38 +00005404}
5405
Arnold Schwaighofer1f3d3ca2013-02-12 01:58:32 +00005406static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5407 SelectionDAG &DAG) {
Andrew Trickef9de2a2013-05-25 02:42:55 +00005408 SDLoc DL(Op);
Arnold Schwaighofer1f3d3ca2013-02-12 01:58:32 +00005409 SDValue OpLHS = Op.getOperand(0);
5410 EVT VT = OpLHS.getValueType();
5411
5412 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5413 "Expect an v8i16/v16i8 type");
5414 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5415 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5416 // extract the first 8 bytes into the top double word and the last 8 bytes
5417 // into the bottom double word. The v8i16 case is similar.
5418 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5419 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5420 DAG.getConstant(ExtractNum, MVT::i32));
5421}
5422
Bob Wilson2e076c42009-06-22 23:27:02 +00005423static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005424 SDValue V1 = Op.getOperand(0);
5425 SDValue V2 = Op.getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +00005426 SDLoc dl(Op);
Bob Wilsonea3a4022009-08-12 22:31:50 +00005427 EVT VT = Op.getValueType();
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005428 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
Bob Wilsonea3a4022009-08-12 22:31:50 +00005429
Bob Wilsonc6800b52009-08-13 02:13:04 +00005430 // Convert shuffles that are directly supported on NEON to target-specific
5431 // DAG nodes, instead of keeping them as shuffles and matching them again
5432 // during code selection. This is more efficient and avoids the possibility
5433 // of inconsistencies between legalization and selection.
Bob Wilson3e4c0122009-08-13 06:01:30 +00005434 // FIXME: floating-point vectors should be canonicalized to integer vectors
5435 // of the same time so that they get CSEd properly.
Benjamin Kramer339ced42012-01-15 13:16:05 +00005436 ArrayRef<int> ShuffleMask = SVN->getMask();
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +00005437
Bob Wilson846bd792010-06-07 23:53:38 +00005438 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5439 if (EltSize <= 32) {
5440 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5441 int Lane = SVN->getSplatIndex();
5442 // If this is undef splat, generate it via "just" vdup, if possible.
5443 if (Lane == -1) Lane = 0;
Anton Korobeynikov4d237542009-11-02 00:12:06 +00005444
Dan Gohman198b7ff2011-11-03 21:49:52 +00005445 // Test if V1 is a SCALAR_TO_VECTOR.
Bob Wilson846bd792010-06-07 23:53:38 +00005446 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5447 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5448 }
Dan Gohman198b7ff2011-11-03 21:49:52 +00005449 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5450 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5451 // reaches it).
5452 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5453 !isa<ConstantSDNode>(V1.getOperand(0))) {
5454 bool IsScalarToVector = true;
5455 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5456 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5457 IsScalarToVector = false;
5458 break;
5459 }
5460 if (IsScalarToVector)
5461 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5462 }
Bob Wilson846bd792010-06-07 23:53:38 +00005463 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5464 DAG.getConstant(Lane, MVT::i32));
Bob Wilsoneb54d512009-08-14 05:13:08 +00005465 }
Bob Wilson846bd792010-06-07 23:53:38 +00005466
5467 bool ReverseVEXT;
5468 unsigned Imm;
5469 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5470 if (ReverseVEXT)
5471 std::swap(V1, V2);
5472 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5473 DAG.getConstant(Imm, MVT::i32));
5474 }
5475
5476 if (isVREVMask(ShuffleMask, VT, 64))
5477 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5478 if (isVREVMask(ShuffleMask, VT, 32))
5479 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5480 if (isVREVMask(ShuffleMask, VT, 16))
5481 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5482
Quentin Colombet8e1fe842012-11-02 21:32:17 +00005483 if (V2->getOpcode() == ISD::UNDEF &&
5484 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5485 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5486 DAG.getConstant(Imm, MVT::i32));
5487 }
5488
Bob Wilson846bd792010-06-07 23:53:38 +00005489 // Check for Neon shuffles that modify both input vectors in place.
5490 // If both results are used, i.e., if there are two shuffles with the same
5491 // source operands and with masks corresponding to both results of one of
5492 // these operations, DAG memoization will ensure that a single node is
5493 // used for both shuffles.
5494 unsigned WhichResult;
5495 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5496 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5497 V1, V2).getValue(WhichResult);
5498 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5499 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5500 V1, V2).getValue(WhichResult);
5501 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5502 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5503 V1, V2).getValue(WhichResult);
5504
5505 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5506 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5507 V1, V1).getValue(WhichResult);
5508 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5509 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5510 V1, V1).getValue(WhichResult);
5511 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5512 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5513 V1, V1).getValue(WhichResult);
Bob Wilsoncce31f62009-08-14 05:08:32 +00005514 }
Bob Wilson32cd8552009-08-19 17:03:43 +00005515
Bob Wilsona7062312009-08-21 20:54:19 +00005516 // If the shuffle is not directly supported and it has 4 elements, use
5517 // the PerfectShuffle-generated table to synthesize it from other shuffles.
Bob Wilson91fdf682010-05-22 00:23:12 +00005518 unsigned NumElts = VT.getVectorNumElements();
5519 if (NumElts == 4) {
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005520 unsigned PFIndexes[4];
5521 for (unsigned i = 0; i != 4; ++i) {
5522 if (ShuffleMask[i] < 0)
5523 PFIndexes[i] = 8;
5524 else
5525 PFIndexes[i] = ShuffleMask[i];
5526 }
5527
5528 // Compute the index in the perfect shuffle table.
5529 unsigned PFTableIndex =
5530 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
Anton Korobeynikov9a232f42009-08-21 12:41:24 +00005531 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5532 unsigned Cost = (PFEntry >> 30);
5533
5534 if (Cost <= 4)
5535 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5536 }
Bob Wilsonea3a4022009-08-12 22:31:50 +00005537
Bob Wilsond8a9a042010-06-04 00:04:02 +00005538 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
Bob Wilson91fdf682010-05-22 00:23:12 +00005539 if (EltSize >= 32) {
5540 // Do the expansion with floating-point types, since that is what the VFP
5541 // registers are defined to use, and since i64 is not legal.
5542 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5543 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
Wesley Peck527da1b2010-11-23 03:31:01 +00005544 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5545 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
Bob Wilsond8a9a042010-06-04 00:04:02 +00005546 SmallVector<SDValue, 8> Ops;
Bob Wilson91fdf682010-05-22 00:23:12 +00005547 for (unsigned i = 0; i < NumElts; ++i) {
Bob Wilson59549942010-05-20 18:39:53 +00005548 if (ShuffleMask[i] < 0)
Bob Wilsond8a9a042010-06-04 00:04:02 +00005549 Ops.push_back(DAG.getUNDEF(EltVT));
5550 else
5551 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5552 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5553 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5554 MVT::i32)));
Bob Wilson59549942010-05-20 18:39:53 +00005555 }
Craig Topper48d114b2014-04-26 18:35:24 +00005556 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
Wesley Peck527da1b2010-11-23 03:31:01 +00005557 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
Bob Wilson59549942010-05-20 18:39:53 +00005558 }
5559
Arnold Schwaighofer1f3d3ca2013-02-12 01:58:32 +00005560 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5561 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5562
Bill Wendlinge1fd78f2011-03-14 23:02:38 +00005563 if (VT == MVT::v8i8) {
5564 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5565 if (NewOp.getNode())
5566 return NewOp;
5567 }
5568
Bob Wilson6f34e272009-08-14 05:16:33 +00005569 return SDValue();
Bob Wilson2e076c42009-06-22 23:27:02 +00005570}
5571
Eli Friedmana5e244c2011-10-24 23:08:52 +00005572static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5573 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5574 SDValue Lane = Op.getOperand(2);
5575 if (!isa<ConstantSDNode>(Lane))
5576 return SDValue();
5577
5578 return Op;
5579}
5580
Bob Wilson2e076c42009-06-22 23:27:02 +00005581static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
Bob Wilsonceb49292010-11-03 16:24:50 +00005582 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
Bob Wilson2e076c42009-06-22 23:27:02 +00005583 SDValue Lane = Op.getOperand(1);
Bob Wilsonceb49292010-11-03 16:24:50 +00005584 if (!isa<ConstantSDNode>(Lane))
5585 return SDValue();
5586
5587 SDValue Vec = Op.getOperand(0);
5588 if (Op.getValueType() == MVT::i32 &&
5589 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
Andrew Trickef9de2a2013-05-25 02:42:55 +00005590 SDLoc dl(Op);
Bob Wilsonceb49292010-11-03 16:24:50 +00005591 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5592 }
5593
5594 return Op;
Bob Wilson2e076c42009-06-22 23:27:02 +00005595}
5596
Bob Wilsonf307e0b2009-08-03 20:36:38 +00005597static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5598 // The only time a CONCAT_VECTORS operation can have legal types is when
5599 // two 64-bit vectors are concatenated to a 128-bit vector.
5600 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5601 "unexpected CONCAT_VECTORS");
Andrew Trickef9de2a2013-05-25 02:42:55 +00005602 SDLoc dl(Op);
Owen Anderson9f944592009-08-11 20:47:22 +00005603 SDValue Val = DAG.getUNDEF(MVT::v2f64);
Bob Wilsonf307e0b2009-08-03 20:36:38 +00005604 SDValue Op0 = Op.getOperand(0);
5605 SDValue Op1 = Op.getOperand(1);
5606 if (Op0.getOpcode() != ISD::UNDEF)
Owen Anderson9f944592009-08-11 20:47:22 +00005607 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
Wesley Peck527da1b2010-11-23 03:31:01 +00005608 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
Bob Wilsonf307e0b2009-08-03 20:36:38 +00005609 DAG.getIntPtrConstant(0));
5610 if (Op1.getOpcode() != ISD::UNDEF)
Owen Anderson9f944592009-08-11 20:47:22 +00005611 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
Wesley Peck527da1b2010-11-23 03:31:01 +00005612 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
Bob Wilsonf307e0b2009-08-03 20:36:38 +00005613 DAG.getIntPtrConstant(1));
Wesley Peck527da1b2010-11-23 03:31:01 +00005614 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
Bob Wilson2e076c42009-06-22 23:27:02 +00005615}
5616
Bob Wilsond7d2cf72010-11-23 19:38:38 +00005617/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5618/// element has been zero/sign-extended, depending on the isSigned parameter,
5619/// from an integer type half its size.
5620static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5621 bool isSigned) {
5622 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5623 EVT VT = N->getValueType(0);
5624 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5625 SDNode *BVN = N->getOperand(0).getNode();
5626 if (BVN->getValueType(0) != MVT::v4i32 ||
5627 BVN->getOpcode() != ISD::BUILD_VECTOR)
5628 return false;
5629 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5630 unsigned HiElt = 1 - LoElt;
5631 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5632 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5633 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5634 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5635 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5636 return false;
5637 if (isSigned) {
5638 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5639 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5640 return true;
5641 } else {
5642 if (Hi0->isNullValue() && Hi1->isNullValue())
5643 return true;
5644 }
5645 return false;
5646 }
5647
5648 if (N->getOpcode() != ISD::BUILD_VECTOR)
5649 return false;
5650
5651 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5652 SDNode *Elt = N->getOperand(i).getNode();
5653 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5654 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5655 unsigned HalfSize = EltSize / 2;
5656 if (isSigned) {
Bob Wilson93b0f7b2011-10-18 18:46:49 +00005657 if (!isIntN(HalfSize, C->getSExtValue()))
Bob Wilsond7d2cf72010-11-23 19:38:38 +00005658 return false;
5659 } else {
Bob Wilson93b0f7b2011-10-18 18:46:49 +00005660 if (!isUIntN(HalfSize, C->getZExtValue()))
Bob Wilsond7d2cf72010-11-23 19:38:38 +00005661 return false;
5662 }
5663 continue;
5664 }
5665 return false;
5666 }
5667
5668 return true;
5669}
5670
5671/// isSignExtended - Check if a node is a vector value that is sign-extended
5672/// or a constant BUILD_VECTOR with sign-extended elements.
5673static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5674 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5675 return true;
5676 if (isExtendedBUILD_VECTOR(N, DAG, true))
5677 return true;
5678 return false;
5679}
5680
5681/// isZeroExtended - Check if a node is a vector value that is zero-extended
5682/// or a constant BUILD_VECTOR with zero-extended elements.
5683static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5684 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5685 return true;
5686 if (isExtendedBUILD_VECTOR(N, DAG, false))
5687 return true;
5688 return false;
5689}
5690
Arnold Schwaighoferaf85f602013-05-14 22:33:24 +00005691static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5692 if (OrigVT.getSizeInBits() >= 64)
5693 return OrigVT;
5694
5695 assert(OrigVT.isSimple() && "Expecting a simple value type");
5696
5697 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5698 switch (OrigSimpleTy) {
5699 default: llvm_unreachable("Unexpected Vector Type");
5700 case MVT::v2i8:
5701 case MVT::v2i16:
5702 return MVT::v2i32;
5703 case MVT::v4i8:
5704 return MVT::v4i16;
5705 }
5706}
5707
Sebastian Popa204f722012-11-30 19:08:04 +00005708/// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5709/// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5710/// We insert the required extension here to get the vector to fill a D register.
5711static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5712 const EVT &OrigTy,
5713 const EVT &ExtTy,
5714 unsigned ExtOpcode) {
5715 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5716 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5717 // 64-bits we need to insert a new extension so that it will be 64-bits.
5718 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5719 if (OrigTy.getSizeInBits() >= 64)
5720 return N;
5721
5722 // Must extend size to at least 64 bits to be used as an operand for VMULL.
Arnold Schwaighoferaf85f602013-05-14 22:33:24 +00005723 EVT NewVT = getExtensionTo64Bits(OrigTy);
5724
Andrew Trickef9de2a2013-05-25 02:42:55 +00005725 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
Sebastian Popa204f722012-11-30 19:08:04 +00005726}
5727
5728/// SkipLoadExtensionForVMULL - return a load of the original vector size that
5729/// does not do any sign/zero extension. If the original vector is less
5730/// than 64 bits, an appropriate extension will be added after the load to
5731/// reach a total size of 64 bits. We have to add the extension separately
5732/// because ARM does not have a sign/zero extending load for vectors.
5733static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
Arnold Schwaighoferaf85f602013-05-14 22:33:24 +00005734 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5735
5736 // The load already has the right type.
5737 if (ExtendedTy == LD->getMemoryVT())
Andrew Trickef9de2a2013-05-25 02:42:55 +00005738 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
Sebastian Popa204f722012-11-30 19:08:04 +00005739 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5740 LD->isNonTemporal(), LD->isInvariant(),
5741 LD->getAlignment());
Arnold Schwaighoferaf85f602013-05-14 22:33:24 +00005742
5743 // We need to create a zextload/sextload. We cannot just create a load
5744 // followed by a zext/zext node because LowerMUL is also run during normal
5745 // operation legalization where we can't create illegal types.
Andrew Trickef9de2a2013-05-25 02:42:55 +00005746 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
Arnold Schwaighoferaf85f602013-05-14 22:33:24 +00005747 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
Louis Gerbarg67474e32014-07-31 21:45:05 +00005748 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
Arnold Schwaighoferaf85f602013-05-14 22:33:24 +00005749 LD->isNonTemporal(), LD->getAlignment());
Sebastian Popa204f722012-11-30 19:08:04 +00005750}
5751
5752/// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5753/// extending load, or BUILD_VECTOR with extended elements, return the
5754/// unextended value. The unextended vector should be 64 bits so that it can
5755/// be used as an operand to a VMULL instruction. If the original vector size
5756/// before extension is less than 64 bits we add a an extension to resize
5757/// the vector to 64 bits.
5758static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
Bob Wilson38ab35a2010-09-01 23:50:19 +00005759 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
Sebastian Popa204f722012-11-30 19:08:04 +00005760 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5761 N->getOperand(0)->getValueType(0),
5762 N->getValueType(0),
5763 N->getOpcode());
5764
Bob Wilsond7d2cf72010-11-23 19:38:38 +00005765 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
Sebastian Popa204f722012-11-30 19:08:04 +00005766 return SkipLoadExtensionForVMULL(LD, DAG);
5767
Bob Wilsond7d2cf72010-11-23 19:38:38 +00005768 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5769 // have been legalized as a BITCAST from v4i32.
5770 if (N->getOpcode() == ISD::BITCAST) {
5771 SDNode *BVN = N->getOperand(0).getNode();
5772 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5773 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5774 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
Andrew Trickef9de2a2013-05-25 02:42:55 +00005775 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
Bob Wilsond7d2cf72010-11-23 19:38:38 +00005776 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5777 }
5778 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5779 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5780 EVT VT = N->getValueType(0);
5781 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5782 unsigned NumElts = VT.getVectorNumElements();
5783 MVT TruncVT = MVT::getIntegerVT(EltSize);
5784 SmallVector<SDValue, 8> Ops;
5785 for (unsigned i = 0; i != NumElts; ++i) {
5786 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5787 const APInt &CInt = C->getAPIntValue();
Bob Wilson9245c932012-04-30 16:53:34 +00005788 // Element types smaller than 32 bits are not legal, so use i32 elements.
5789 // The values are implicitly truncated so sext vs. zext doesn't matter.
5790 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
Bob Wilsond7d2cf72010-11-23 19:38:38 +00005791 }
Andrew Trickef9de2a2013-05-25 02:42:55 +00005792 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
Craig Topper48d114b2014-04-26 18:35:24 +00005793 MVT::getVectorVT(TruncVT, NumElts), Ops);
Bob Wilson38ab35a2010-09-01 23:50:19 +00005794}
5795
Evan Chenge2086e72011-03-29 01:56:09 +00005796static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5797 unsigned Opcode = N->getOpcode();
5798 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5799 SDNode *N0 = N->getOperand(0).getNode();
5800 SDNode *N1 = N->getOperand(1).getNode();
5801 return N0->hasOneUse() && N1->hasOneUse() &&
5802 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5803 }
5804 return false;
5805}
5806
5807static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5808 unsigned Opcode = N->getOpcode();
5809 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5810 SDNode *N0 = N->getOperand(0).getNode();
5811 SDNode *N1 = N->getOperand(1).getNode();
5812 return N0->hasOneUse() && N1->hasOneUse() &&
5813 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5814 }
5815 return false;
5816}
5817
Bob Wilson38ab35a2010-09-01 23:50:19 +00005818static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
5819 // Multiplications are only custom-lowered for 128-bit vectors so that
5820 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
5821 EVT VT = Op.getValueType();
Sebastian Popa204f722012-11-30 19:08:04 +00005822 assert(VT.is128BitVector() && VT.isInteger() &&
5823 "unexpected type for custom-lowering ISD::MUL");
Bob Wilson38ab35a2010-09-01 23:50:19 +00005824 SDNode *N0 = Op.getOperand(0).getNode();
5825 SDNode *N1 = Op.getOperand(1).getNode();
5826 unsigned NewOpc = 0;
Evan Chenge2086e72011-03-29 01:56:09 +00005827 bool isMLA = false;
5828 bool isN0SExt = isSignExtended(N0, DAG);
5829 bool isN1SExt = isSignExtended(N1, DAG);
5830 if (isN0SExt && isN1SExt)
Bob Wilson38ab35a2010-09-01 23:50:19 +00005831 NewOpc = ARMISD::VMULLs;
Evan Chenge2086e72011-03-29 01:56:09 +00005832 else {
5833 bool isN0ZExt = isZeroExtended(N0, DAG);
5834 bool isN1ZExt = isZeroExtended(N1, DAG);
5835 if (isN0ZExt && isN1ZExt)
5836 NewOpc = ARMISD::VMULLu;
5837 else if (isN1SExt || isN1ZExt) {
5838 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
5839 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
5840 if (isN1SExt && isAddSubSExt(N0, DAG)) {
5841 NewOpc = ARMISD::VMULLs;
5842 isMLA = true;
5843 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
5844 NewOpc = ARMISD::VMULLu;
5845 isMLA = true;
5846 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
5847 std::swap(N0, N1);
5848 NewOpc = ARMISD::VMULLu;
5849 isMLA = true;
5850 }
5851 }
5852
5853 if (!NewOpc) {
5854 if (VT == MVT::v2i64)
5855 // Fall through to expand this. It is not legal.
5856 return SDValue();
5857 else
5858 // Other vector multiplications are legal.
5859 return Op;
5860 }
5861 }
Bob Wilson38ab35a2010-09-01 23:50:19 +00005862
5863 // Legalize to a VMULL instruction.
Andrew Trickef9de2a2013-05-25 02:42:55 +00005864 SDLoc DL(Op);
Evan Chenge2086e72011-03-29 01:56:09 +00005865 SDValue Op0;
Sebastian Popa204f722012-11-30 19:08:04 +00005866 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
Evan Chenge2086e72011-03-29 01:56:09 +00005867 if (!isMLA) {
Sebastian Popa204f722012-11-30 19:08:04 +00005868 Op0 = SkipExtensionForVMULL(N0, DAG);
Evan Chenge2086e72011-03-29 01:56:09 +00005869 assert(Op0.getValueType().is64BitVector() &&
5870 Op1.getValueType().is64BitVector() &&
5871 "unexpected types for extended operands to VMULL");
5872 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5873 }
Bob Wilson38ab35a2010-09-01 23:50:19 +00005874
Evan Chenge2086e72011-03-29 01:56:09 +00005875 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
5876 // isel lowering to take advantage of no-stall back to back vmul + vmla.
5877 // vmull q0, d4, d6
5878 // vmlal q0, d5, d6
5879 // is faster than
5880 // vaddl q0, d4, d5
5881 // vmovl q1, d6
5882 // vmul q0, q0, q1
Sebastian Popa204f722012-11-30 19:08:04 +00005883 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
5884 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
Evan Chenge2086e72011-03-29 01:56:09 +00005885 EVT Op1VT = Op1.getValueType();
5886 return DAG.getNode(N0->getOpcode(), DL, VT,
5887 DAG.getNode(NewOpc, DL, VT,
5888 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
5889 DAG.getNode(NewOpc, DL, VT,
5890 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
Bob Wilson38ab35a2010-09-01 23:50:19 +00005891}
5892
Owen Anderson77aa2662011-04-05 21:48:57 +00005893static SDValue
Andrew Trickef9de2a2013-05-25 02:42:55 +00005894LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
Nate Begemanfa62d502011-02-11 20:53:29 +00005895 // Convert to float
5896 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
5897 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
5898 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
5899 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
5900 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
5901 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
5902 // Get reciprocal estimate.
5903 // float4 recip = vrecpeq_f32(yf);
Owen Anderson77aa2662011-04-05 21:48:57 +00005904 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
Nate Begemanfa62d502011-02-11 20:53:29 +00005905 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5906 // Because char has a smaller range than uchar, we can actually get away
5907 // without any newton steps. This requires that we use a weird bias
5908 // of 0xb000, however (again, this has been exhaustively tested).
5909 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
5910 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
5911 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
5912 Y = DAG.getConstant(0xb000, MVT::i32);
5913 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5914 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
5915 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
5916 // Convert back to short.
5917 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
5918 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5919 return X;
5920}
5921
Owen Anderson77aa2662011-04-05 21:48:57 +00005922static SDValue
Andrew Trickef9de2a2013-05-25 02:42:55 +00005923LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
Nate Begemanfa62d502011-02-11 20:53:29 +00005924 SDValue N2;
5925 // Convert to float.
5926 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
5927 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
5928 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
5929 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
5930 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5931 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
Owen Anderson77aa2662011-04-05 21:48:57 +00005932
Nate Begemanfa62d502011-02-11 20:53:29 +00005933 // Use reciprocal estimate and one refinement step.
5934 // float4 recip = vrecpeq_f32(yf);
5935 // recip *= vrecpsq_f32(yf, recip);
Owen Anderson77aa2662011-04-05 21:48:57 +00005936 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
Nate Begemanfa62d502011-02-11 20:53:29 +00005937 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
Owen Anderson77aa2662011-04-05 21:48:57 +00005938 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
Nate Begemanfa62d502011-02-11 20:53:29 +00005939 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5940 N1, N2);
5941 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5942 // Because short has a smaller range than ushort, we can actually get away
5943 // with only a single newton step. This requires that we use a weird bias
5944 // of 89, however (again, this has been exhaustively tested).
Mon P Wang6d9e1c72011-05-19 04:15:07 +00005945 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
Nate Begemanfa62d502011-02-11 20:53:29 +00005946 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5947 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
Mon P Wang6d9e1c72011-05-19 04:15:07 +00005948 N1 = DAG.getConstant(0x89, MVT::i32);
Nate Begemanfa62d502011-02-11 20:53:29 +00005949 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5950 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5951 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5952 // Convert back to integer and return.
5953 // return vmovn_s32(vcvt_s32_f32(result));
5954 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5955 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5956 return N0;
5957}
5958
5959static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
5960 EVT VT = Op.getValueType();
5961 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5962 "unexpected type for custom-lowering ISD::SDIV");
5963
Andrew Trickef9de2a2013-05-25 02:42:55 +00005964 SDLoc dl(Op);
Nate Begemanfa62d502011-02-11 20:53:29 +00005965 SDValue N0 = Op.getOperand(0);
5966 SDValue N1 = Op.getOperand(1);
5967 SDValue N2, N3;
Owen Anderson77aa2662011-04-05 21:48:57 +00005968
Nate Begemanfa62d502011-02-11 20:53:29 +00005969 if (VT == MVT::v8i8) {
5970 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
5971 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
Owen Anderson77aa2662011-04-05 21:48:57 +00005972
Nate Begemanfa62d502011-02-11 20:53:29 +00005973 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5974 DAG.getIntPtrConstant(4));
5975 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
Owen Anderson77aa2662011-04-05 21:48:57 +00005976 DAG.getIntPtrConstant(4));
Nate Begemanfa62d502011-02-11 20:53:29 +00005977 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5978 DAG.getIntPtrConstant(0));
5979 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5980 DAG.getIntPtrConstant(0));
5981
5982 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5983 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
5984
5985 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5986 N0 = LowerCONCAT_VECTORS(N0, DAG);
Owen Anderson77aa2662011-04-05 21:48:57 +00005987
Nate Begemanfa62d502011-02-11 20:53:29 +00005988 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
5989 return N0;
5990 }
5991 return LowerSDIV_v4i16(N0, N1, dl, DAG);
5992}
5993
5994static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
5995 EVT VT = Op.getValueType();
5996 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5997 "unexpected type for custom-lowering ISD::UDIV");
5998
Andrew Trickef9de2a2013-05-25 02:42:55 +00005999 SDLoc dl(Op);
Nate Begemanfa62d502011-02-11 20:53:29 +00006000 SDValue N0 = Op.getOperand(0);
6001 SDValue N1 = Op.getOperand(1);
6002 SDValue N2, N3;
Owen Anderson77aa2662011-04-05 21:48:57 +00006003
Nate Begemanfa62d502011-02-11 20:53:29 +00006004 if (VT == MVT::v8i8) {
6005 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6006 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
Owen Anderson77aa2662011-04-05 21:48:57 +00006007
Nate Begemanfa62d502011-02-11 20:53:29 +00006008 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6009 DAG.getIntPtrConstant(4));
6010 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
Owen Anderson77aa2662011-04-05 21:48:57 +00006011 DAG.getIntPtrConstant(4));
Nate Begemanfa62d502011-02-11 20:53:29 +00006012 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6013 DAG.getIntPtrConstant(0));
6014 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6015 DAG.getIntPtrConstant(0));
Owen Anderson77aa2662011-04-05 21:48:57 +00006016
Nate Begemanfa62d502011-02-11 20:53:29 +00006017 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6018 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
Owen Anderson77aa2662011-04-05 21:48:57 +00006019
Nate Begemanfa62d502011-02-11 20:53:29 +00006020 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6021 N0 = LowerCONCAT_VECTORS(N0, DAG);
Owen Anderson77aa2662011-04-05 21:48:57 +00006022
6023 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
Nate Begemanfa62d502011-02-11 20:53:29 +00006024 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
6025 N0);
6026 return N0;
6027 }
Owen Anderson77aa2662011-04-05 21:48:57 +00006028
Nate Begemanfa62d502011-02-11 20:53:29 +00006029 // v4i16 sdiv ... Convert to float.
6030 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6031 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6032 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6033 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6034 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
Mon P Wang6d9e1c72011-05-19 04:15:07 +00006035 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
Nate Begemanfa62d502011-02-11 20:53:29 +00006036
6037 // Use reciprocal estimate and two refinement steps.
6038 // float4 recip = vrecpeq_f32(yf);
6039 // recip *= vrecpsq_f32(yf, recip);
6040 // recip *= vrecpsq_f32(yf, recip);
Owen Anderson77aa2662011-04-05 21:48:57 +00006041 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
Mon P Wang6d9e1c72011-05-19 04:15:07 +00006042 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
Owen Anderson77aa2662011-04-05 21:48:57 +00006043 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
Nate Begemanfa62d502011-02-11 20:53:29 +00006044 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
Mon P Wang6d9e1c72011-05-19 04:15:07 +00006045 BN1, N2);
Nate Begemanfa62d502011-02-11 20:53:29 +00006046 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
Owen Anderson77aa2662011-04-05 21:48:57 +00006047 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
Nate Begemanfa62d502011-02-11 20:53:29 +00006048 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
Mon P Wang6d9e1c72011-05-19 04:15:07 +00006049 BN1, N2);
Nate Begemanfa62d502011-02-11 20:53:29 +00006050 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6051 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6052 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6053 // and that it will never cause us to return an answer too large).
Mon P Wang6d9e1c72011-05-19 04:15:07 +00006054 // float4 result = as_float4(as_int4(xf*recip) + 2);
Nate Begemanfa62d502011-02-11 20:53:29 +00006055 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6056 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6057 N1 = DAG.getConstant(2, MVT::i32);
6058 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6059 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6060 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6061 // Convert back to integer and return.
6062 // return vmovn_u32(vcvt_s32_f32(result));
6063 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6064 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6065 return N0;
6066}
6067
Evan Chenge8916542011-08-30 01:34:54 +00006068static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6069 EVT VT = Op.getNode()->getValueType(0);
6070 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6071
6072 unsigned Opc;
6073 bool ExtraOp = false;
6074 switch (Op.getOpcode()) {
Craig Toppere55c5562012-02-07 02:50:20 +00006075 default: llvm_unreachable("Invalid code");
Evan Chenge8916542011-08-30 01:34:54 +00006076 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6077 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6078 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6079 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6080 }
6081
6082 if (!ExtraOp)
Andrew Trickef9de2a2013-05-25 02:42:55 +00006083 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
Evan Chenge8916542011-08-30 01:34:54 +00006084 Op.getOperand(1));
Andrew Trickef9de2a2013-05-25 02:42:55 +00006085 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
Evan Chenge8916542011-08-30 01:34:54 +00006086 Op.getOperand(1), Op.getOperand(2));
6087}
6088
Bob Wilsone7dde0c2013-11-03 06:14:38 +00006089SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6090 assert(Subtarget->isTargetDarwin());
6091
6092 // For iOS, we want to call an alternative entry point: __sincos_stret,
6093 // return values are passed via sret.
6094 SDLoc dl(Op);
6095 SDValue Arg = Op.getOperand(0);
6096 EVT ArgVT = Arg.getValueType();
6097 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6098
6099 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6101
6102 // Pair of floats / doubles used to pass the result.
6103 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
6104
6105 // Create stack object for sret.
6106 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
6107 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
6108 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6109 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
6110
6111 ArgListTy Args;
6112 ArgListEntry Entry;
6113
6114 Entry.Node = SRet;
6115 Entry.Ty = RetTy->getPointerTo();
6116 Entry.isSExt = false;
6117 Entry.isZExt = false;
6118 Entry.isSRet = true;
6119 Args.push_back(Entry);
6120
6121 Entry.Node = Arg;
6122 Entry.Ty = ArgTy;
6123 Entry.isSExt = false;
6124 Entry.isZExt = false;
6125 Args.push_back(Entry);
6126
6127 const char *LibcallName = (ArgVT == MVT::f64)
6128 ? "__sincos_stret" : "__sincosf_stret";
6129 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
6130
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +00006131 TargetLowering::CallLoweringInfo CLI(DAG);
6132 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6133 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
Juergen Ributzka3bd03c72014-07-01 22:01:54 +00006134 std::move(Args), 0)
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +00006135 .setDiscardResult();
6136
Bob Wilsone7dde0c2013-11-03 06:14:38 +00006137 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6138
6139 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6140 MachinePointerInfo(), false, false, false, 0);
6141
6142 // Address of cos field.
6143 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
6144 DAG.getIntPtrConstant(ArgVT.getStoreSize()));
6145 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6146 MachinePointerInfo(), false, false, false, 0);
6147
6148 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6149 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6150 LoadSin.getValue(0), LoadCos.getValue(0));
6151}
6152
Eli Friedman10f9ce22011-09-15 22:26:18 +00006153static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
Eli Friedmanba912e02011-09-15 22:18:49 +00006154 // Monotonic load/store is legal for all targets
6155 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6156 return Op;
6157
Alp Tokercb402912014-01-24 17:20:08 +00006158 // Acquire/Release load/store is not legal for targets without a
Eli Friedmanba912e02011-09-15 22:18:49 +00006159 // dmb or equivalent available.
6160 return SDValue();
6161}
6162
Tim Northoverbc933082013-05-23 19:11:20 +00006163static void ReplaceREADCYCLECOUNTER(SDNode *N,
6164 SmallVectorImpl<SDValue> &Results,
6165 SelectionDAG &DAG,
6166 const ARMSubtarget *Subtarget) {
Andrew Trickef9de2a2013-05-25 02:42:55 +00006167 SDLoc DL(N);
Tim Northoverbc933082013-05-23 19:11:20 +00006168 SDValue Cycles32, OutChain;
6169
6170 if (Subtarget->hasPerfMon()) {
6171 // Under Power Management extensions, the cycle-count is:
6172 // mrc p15, #0, <Rt>, c9, c13, #0
6173 SDValue Ops[] = { N->getOperand(0), // Chain
6174 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
6175 DAG.getConstant(15, MVT::i32),
6176 DAG.getConstant(0, MVT::i32),
6177 DAG.getConstant(9, MVT::i32),
6178 DAG.getConstant(13, MVT::i32),
6179 DAG.getConstant(0, MVT::i32)
6180 };
6181
6182 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
Craig Topper48d114b2014-04-26 18:35:24 +00006183 DAG.getVTList(MVT::i32, MVT::Other), Ops);
Tim Northoverbc933082013-05-23 19:11:20 +00006184 OutChain = Cycles32.getValue(1);
6185 } else {
6186 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6187 // there are older ARM CPUs that have implementation-specific ways of
6188 // obtaining this information (FIXME!).
6189 Cycles32 = DAG.getConstant(0, MVT::i32);
6190 OutChain = DAG.getEntryNode();
6191 }
6192
6193
6194 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6195 Cycles32, DAG.getConstant(0, MVT::i32));
6196 Results.push_back(Cycles64);
6197 Results.push_back(OutChain);
6198}
6199
Dan Gohman21cea8a2010-04-17 15:26:15 +00006200SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Evan Cheng10043e22007-01-19 07:51:42 +00006201 switch (Op.getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00006202 default: llvm_unreachable("Don't know how to custom lower this!");
Evan Cheng10043e22007-01-19 07:51:42 +00006203 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
Bob Wilson1cf0b032009-10-30 05:45:42 +00006204 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00006205 case ISD::GlobalAddress:
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +00006206 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6207 default: llvm_unreachable("unknown object format");
6208 case Triple::COFF:
6209 return LowerGlobalAddressWindows(Op, DAG);
6210 case Triple::ELF:
6211 return LowerGlobalAddressELF(Op, DAG);
6212 case Triple::MachO:
6213 return LowerGlobalAddressDarwin(Op, DAG);
6214 }
Bill Wendlinge1fd78f2011-03-14 23:02:38 +00006215 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Bill Wendling6a981312010-08-11 08:43:16 +00006216 case ISD::SELECT: return LowerSELECT(Op, DAG);
Evan Cheng15b80e42009-11-12 07:13:11 +00006217 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6218 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
Evan Cheng10043e22007-01-19 07:51:42 +00006219 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
Dan Gohman31ae5862010-04-17 14:41:14 +00006220 case ISD::VASTART: return LowerVASTART(Op, DAG);
Eli Friedman26a48482011-07-27 22:21:52 +00006221 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
Evan Cheng8740ee32010-11-03 06:34:55 +00006222 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
Bob Wilsone4191e72010-03-19 22:51:32 +00006223 case ISD::SINT_TO_FP:
6224 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6225 case ISD::FP_TO_SINT:
6226 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
Evan Cheng10043e22007-01-19 07:51:42 +00006227 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Evan Cheng168ced92010-05-22 01:47:14 +00006228 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
Jim Grosbachaeca45d2009-05-12 23:59:14 +00006229 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +00006230 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
Jim Grosbachc98892f2010-05-26 20:22:18 +00006231 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
Jim Grosbachbd9485d2010-05-22 01:06:18 +00006232 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
Jim Grosbacha570d052010-02-08 23:22:00 +00006233 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6234 Subtarget);
Evan Cheng383ecd82011-03-14 18:02:30 +00006235 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
Bob Wilson2e076c42009-06-22 23:27:02 +00006236 case ISD::SHL:
Chris Lattnerf81d5882007-11-24 07:07:01 +00006237 case ISD::SRL:
Bob Wilson2e076c42009-06-22 23:27:02 +00006238 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
Evan Cheng15b80e42009-11-12 07:13:11 +00006239 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
Jim Grosbach8fe6fd72009-10-31 21:42:19 +00006240 case ISD::SRL_PARTS:
Evan Cheng15b80e42009-11-12 07:13:11 +00006241 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
Jim Grosbach8546ec92010-01-18 19:58:49 +00006242 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
Evan Chengb4eae132012-12-04 22:41:50 +00006243 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
Duncan Sandsf2641e12011-09-06 19:07:46 +00006244 case ISD::SETCC: return LowerVSETCC(Op, DAG);
Lang Hamesc35ee8b2012-03-15 18:49:02 +00006245 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
Dale Johannesen2bff5052010-07-29 20:10:08 +00006246 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
Bob Wilson2e076c42009-06-22 23:27:02 +00006247 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
Eli Friedmana5e244c2011-10-24 23:08:52 +00006248 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
Bob Wilson2e076c42009-06-22 23:27:02 +00006249 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
Bob Wilsonf307e0b2009-08-03 20:36:38 +00006250 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
Bob Wilson9a511c02010-08-20 04:54:02 +00006251 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
Bob Wilson38ab35a2010-09-01 23:50:19 +00006252 case ISD::MUL: return LowerMUL(Op, DAG);
Nate Begemanfa62d502011-02-11 20:53:29 +00006253 case ISD::SDIV: return LowerSDIV(Op, DAG);
6254 case ISD::UDIV: return LowerUDIV(Op, DAG);
Evan Chenge8916542011-08-30 01:34:54 +00006255 case ISD::ADDC:
6256 case ISD::ADDE:
6257 case ISD::SUBC:
6258 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
Louis Gerbarg3342bf12014-05-09 17:02:49 +00006259 case ISD::SADDO:
6260 case ISD::UADDO:
6261 case ISD::SSUBO:
6262 case ISD::USUBO:
6263 return LowerXALUO(Op, DAG);
Eli Friedmanba912e02011-09-15 22:18:49 +00006264 case ISD::ATOMIC_LOAD:
Eli Friedman10f9ce22011-09-15 22:26:18 +00006265 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
Bob Wilsone7dde0c2013-11-03 06:14:38 +00006266 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
Renato Golin87610692013-07-16 09:32:17 +00006267 case ISD::SDIVREM:
6268 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +00006269 case ISD::DYNAMIC_STACKALLOC:
6270 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6271 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6272 llvm_unreachable("Don't know how to custom lower this!");
Evan Cheng10043e22007-01-19 07:51:42 +00006273 }
Evan Cheng10043e22007-01-19 07:51:42 +00006274}
6275
Duncan Sands6ed40142008-12-01 11:39:25 +00006276/// ReplaceNodeResults - Replace the results of node with an illegal result
6277/// type with new values built out of custom code.
Duncan Sands6ed40142008-12-01 11:39:25 +00006278void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6279 SmallVectorImpl<SDValue>&Results,
Dan Gohman21cea8a2010-04-17 15:26:15 +00006280 SelectionDAG &DAG) const {
Bob Wilsonc05b8872010-04-14 20:45:23 +00006281 SDValue Res;
Chris Lattnerf81d5882007-11-24 07:07:01 +00006282 switch (N->getOpcode()) {
Duncan Sands6ed40142008-12-01 11:39:25 +00006283 default:
Torok Edwinfbcc6632009-07-14 16:55:14 +00006284 llvm_unreachable("Don't know how to custom expand this!");
Wesley Peck527da1b2010-11-23 03:31:01 +00006285 case ISD::BITCAST:
6286 Res = ExpandBITCAST(N, DAG);
Bob Wilsonc05b8872010-04-14 20:45:23 +00006287 break;
Chris Lattnerf81d5882007-11-24 07:07:01 +00006288 case ISD::SRL:
Bob Wilsonc05b8872010-04-14 20:45:23 +00006289 case ISD::SRA:
Bob Wilson7d471332010-11-18 21:16:28 +00006290 Res = Expand64BitShift(N, DAG, Subtarget);
Bob Wilsonc05b8872010-04-14 20:45:23 +00006291 break;
Tim Northoverbc933082013-05-23 19:11:20 +00006292 case ISD::READCYCLECOUNTER:
6293 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6294 return;
Duncan Sands6ed40142008-12-01 11:39:25 +00006295 }
Bob Wilsonc05b8872010-04-14 20:45:23 +00006296 if (Res.getNode())
6297 Results.push_back(Res);
Chris Lattnerf81d5882007-11-24 07:07:01 +00006298}
Chris Lattnerf81d5882007-11-24 07:07:01 +00006299
Evan Cheng10043e22007-01-19 07:51:42 +00006300//===----------------------------------------------------------------------===//
6301// ARM Scheduler Hooks
6302//===----------------------------------------------------------------------===//
6303
Bill Wendling030b58e2011-10-06 22:18:16 +00006304/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6305/// registers the function context.
6306void ARMTargetLowering::
6307SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6308 MachineBasicBlock *DispatchBB, int FI) const {
Bill Wendling374ee192011-10-03 21:25:38 +00006309 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6310 DebugLoc dl = MI->getDebugLoc();
6311 MachineFunction *MF = MBB->getParent();
6312 MachineRegisterInfo *MRI = &MF->getRegInfo();
6313 MachineConstantPool *MCP = MF->getConstantPool();
6314 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6315 const Function *F = MF->getFunction();
Bill Wendling374ee192011-10-03 21:25:38 +00006316
Bill Wendling374ee192011-10-03 21:25:38 +00006317 bool isThumb = Subtarget->isThumb();
Bill Wendling1eab54f2011-10-03 22:44:15 +00006318 bool isThumb2 = Subtarget->isThumb2();
Bill Wendling030b58e2011-10-06 22:18:16 +00006319
Bill Wendling374ee192011-10-03 21:25:38 +00006320 unsigned PCLabelId = AFI->createPICLabelUId();
Bill Wendling1eab54f2011-10-03 22:44:15 +00006321 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
Bill Wendling374ee192011-10-03 21:25:38 +00006322 ARMConstantPoolValue *CPV =
6323 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6324 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6325
Craig Topperc7242e02012-04-20 07:30:17 +00006326 const TargetRegisterClass *TRC = isThumb ?
6327 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6328 (const TargetRegisterClass*)&ARM::GPRRegClass;
Bill Wendling374ee192011-10-03 21:25:38 +00006329
Bill Wendling030b58e2011-10-06 22:18:16 +00006330 // Grab constant pool and fixed stack memory operands.
6331 MachineMemOperand *CPMMO =
6332 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6333 MachineMemOperand::MOLoad, 4, 4);
6334
6335 MachineMemOperand *FIMMOSt =
6336 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6337 MachineMemOperand::MOStore, 4, 4);
6338
6339 // Load the address of the dispatch MBB into the jump buffer.
6340 if (isThumb2) {
6341 // Incoming value: jbuf
6342 // ldr.n r5, LCPI1_1
6343 // orr r5, r5, #1
6344 // add r5, pc
6345 // str r5, [$jbuf, #+4] ; &jbuf[1]
6346 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6347 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6348 .addConstantPoolIndex(CPI)
6349 .addMemOperand(CPMMO));
6350 // Set the low bit because of thumb mode.
6351 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6352 AddDefaultCC(
6353 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6354 .addReg(NewVReg1, RegState::Kill)
6355 .addImm(0x01)));
6356 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6357 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6358 .addReg(NewVReg2, RegState::Kill)
6359 .addImm(PCLabelId);
6360 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6361 .addReg(NewVReg3, RegState::Kill)
6362 .addFrameIndex(FI)
6363 .addImm(36) // &jbuf[1] :: pc
6364 .addMemOperand(FIMMOSt));
6365 } else if (isThumb) {
6366 // Incoming value: jbuf
6367 // ldr.n r1, LCPI1_4
6368 // add r1, pc
6369 // mov r2, #1
6370 // orrs r1, r2
6371 // add r2, $jbuf, #+4 ; &jbuf[1]
6372 // str r1, [r2]
6373 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6374 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6375 .addConstantPoolIndex(CPI)
6376 .addMemOperand(CPMMO));
6377 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6378 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6379 .addReg(NewVReg1, RegState::Kill)
6380 .addImm(PCLabelId);
6381 // Set the low bit because of thumb mode.
6382 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6383 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6384 .addReg(ARM::CPSR, RegState::Define)
6385 .addImm(1));
6386 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6387 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6388 .addReg(ARM::CPSR, RegState::Define)
6389 .addReg(NewVReg2, RegState::Kill)
6390 .addReg(NewVReg3, RegState::Kill));
6391 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6392 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
6393 .addFrameIndex(FI)
6394 .addImm(36)); // &jbuf[1] :: pc
6395 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6396 .addReg(NewVReg4, RegState::Kill)
6397 .addReg(NewVReg5, RegState::Kill)
6398 .addImm(0)
6399 .addMemOperand(FIMMOSt));
6400 } else {
6401 // Incoming value: jbuf
6402 // ldr r1, LCPI1_1
6403 // add r1, pc, r1
6404 // str r1, [$jbuf, #+4] ; &jbuf[1]
6405 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6406 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6407 .addConstantPoolIndex(CPI)
6408 .addImm(0)
6409 .addMemOperand(CPMMO));
6410 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6411 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6412 .addReg(NewVReg1, RegState::Kill)
6413 .addImm(PCLabelId));
6414 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6415 .addReg(NewVReg2, RegState::Kill)
6416 .addFrameIndex(FI)
6417 .addImm(36) // &jbuf[1] :: pc
6418 .addMemOperand(FIMMOSt));
6419 }
6420}
6421
6422MachineBasicBlock *ARMTargetLowering::
6423EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6424 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6425 DebugLoc dl = MI->getDebugLoc();
6426 MachineFunction *MF = MBB->getParent();
6427 MachineRegisterInfo *MRI = &MF->getRegInfo();
6428 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6429 MachineFrameInfo *MFI = MF->getFrameInfo();
6430 int FI = MFI->getFunctionContextIndex();
6431
Craig Topperc7242e02012-04-20 07:30:17 +00006432 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6433 (const TargetRegisterClass*)&ARM::tGPRRegClass :
Jakob Stoklund Olesen691ae332012-05-20 06:38:47 +00006434 (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
Bill Wendling030b58e2011-10-06 22:18:16 +00006435
Bill Wendling362c1b02011-10-06 21:29:56 +00006436 // Get a mapping of the call site numbers to all of the landing pads they're
6437 // associated with.
Bill Wendling202803e2011-10-05 00:02:33 +00006438 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6439 unsigned MaxCSNum = 0;
6440 MachineModuleInfo &MMI = MF->getMMI();
Jim Grosbach0c509fa2012-04-06 23:43:50 +00006441 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6442 ++BB) {
Bill Wendling202803e2011-10-05 00:02:33 +00006443 if (!BB->isLandingPad()) continue;
6444
6445 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6446 // pad.
6447 for (MachineBasicBlock::iterator
6448 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6449 if (!II->isEHLabel()) continue;
6450
6451 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
Bill Wendlingf793e7e2011-10-05 23:28:57 +00006452 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
Bill Wendling202803e2011-10-05 00:02:33 +00006453
Bill Wendlingf793e7e2011-10-05 23:28:57 +00006454 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6455 for (SmallVectorImpl<unsigned>::iterator
6456 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6457 CSI != CSE; ++CSI) {
6458 CallSiteNumToLPad[*CSI].push_back(BB);
6459 MaxCSNum = std::max(MaxCSNum, *CSI);
6460 }
Bill Wendling202803e2011-10-05 00:02:33 +00006461 break;
6462 }
6463 }
6464
6465 // Get an ordered list of the machine basic blocks for the jump table.
6466 std::vector<MachineBasicBlock*> LPadList;
Bill Wendling883ec972011-10-07 23:18:02 +00006467 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
Bill Wendling202803e2011-10-05 00:02:33 +00006468 LPadList.reserve(CallSiteNumToLPad.size());
6469 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6470 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6471 for (SmallVectorImpl<MachineBasicBlock*>::iterator
Bill Wendling883ec972011-10-07 23:18:02 +00006472 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
Bill Wendling202803e2011-10-05 00:02:33 +00006473 LPadList.push_back(*II);
Bill Wendling883ec972011-10-07 23:18:02 +00006474 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6475 }
Bill Wendling202803e2011-10-05 00:02:33 +00006476 }
6477
Bill Wendlingf793e7e2011-10-05 23:28:57 +00006478 assert(!LPadList.empty() &&
6479 "No landing pad destinations for the dispatch jump table!");
6480
Bill Wendling362c1b02011-10-06 21:29:56 +00006481 // Create the jump table and associated information.
Bill Wendling202803e2011-10-05 00:02:33 +00006482 MachineJumpTableInfo *JTI =
6483 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6484 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6485 unsigned UId = AFI->createJumpTableUId();
Chad Rosier96603432013-03-01 18:30:38 +00006486 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
Bill Wendling202803e2011-10-05 00:02:33 +00006487
Bill Wendling362c1b02011-10-06 21:29:56 +00006488 // Create the MBBs for the dispatch code.
Bill Wendling030b58e2011-10-06 22:18:16 +00006489
6490 // Shove the dispatch's address into the return slot in the function context.
6491 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6492 DispatchBB->setIsLandingPad();
Bill Wendling030b58e2011-10-06 22:18:16 +00006493
Bill Wendling324be982011-10-05 00:39:32 +00006494 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
Eli Bendersky2e2ce492013-01-30 16:30:19 +00006495 unsigned trap_opcode;
Chad Rosier11a98282013-02-28 18:54:27 +00006496 if (Subtarget->isThumb())
Eli Bendersky2e2ce492013-01-30 16:30:19 +00006497 trap_opcode = ARM::tTRAP;
Chad Rosier11a98282013-02-28 18:54:27 +00006498 else
6499 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6500
Eli Bendersky2e2ce492013-01-30 16:30:19 +00006501 BuildMI(TrapBB, dl, TII->get(trap_opcode));
Bill Wendling324be982011-10-05 00:39:32 +00006502 DispatchBB->addSuccessor(TrapBB);
6503
6504 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6505 DispatchBB->addSuccessor(DispContBB);
Bill Wendling202803e2011-10-05 00:02:33 +00006506
Bill Wendling510fbcd2011-10-17 21:32:56 +00006507 // Insert and MBBs.
Bill Wendling61346552011-10-06 00:53:33 +00006508 MF->insert(MF->end(), DispatchBB);
6509 MF->insert(MF->end(), DispContBB);
6510 MF->insert(MF->end(), TrapBB);
Bill Wendling61346552011-10-06 00:53:33 +00006511
Bill Wendling030b58e2011-10-06 22:18:16 +00006512 // Insert code into the entry block that creates and registers the function
6513 // context.
6514 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6515
Bill Wendling030b58e2011-10-06 22:18:16 +00006516 MachineMemOperand *FIMMOLd =
Bill Wendling362c1b02011-10-06 21:29:56 +00006517 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
Bill Wendlingb3d46782011-10-06 23:37:36 +00006518 MachineMemOperand::MOLoad |
6519 MachineMemOperand::MOVolatile, 4, 4);
Bill Wendling61346552011-10-06 00:53:33 +00006520
Chad Rosier1ec8e402012-11-06 23:05:24 +00006521 MachineInstrBuilder MIB;
6522 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6523
6524 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6525 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6526
6527 // Add a register mask with no preserved registers. This results in all
6528 // registers being marked as clobbered.
6529 MIB.addRegMask(RI.getNoPreservedMask());
Bob Wilsonf6d17282011-11-16 07:11:57 +00006530
Bill Wendling85833f72011-10-18 22:49:07 +00006531 unsigned NumLPads = LPadList.size();
Bill Wendling5626c662011-10-06 22:53:00 +00006532 if (Subtarget->isThumb2()) {
6533 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6534 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6535 .addFrameIndex(FI)
6536 .addImm(4)
6537 .addMemOperand(FIMMOLd));
Bill Wendlingb2a703d2011-10-18 21:55:58 +00006538
Bill Wendling85833f72011-10-18 22:49:07 +00006539 if (NumLPads < 256) {
6540 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6541 .addReg(NewVReg1)
6542 .addImm(LPadList.size()));
6543 } else {
6544 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6545 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
Bill Wendling94f60012011-10-18 23:19:55 +00006546 .addImm(NumLPads & 0xFFFF));
6547
6548 unsigned VReg2 = VReg1;
6549 if ((NumLPads & 0xFFFF0000) != 0) {
6550 VReg2 = MRI->createVirtualRegister(TRC);
6551 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6552 .addReg(VReg1)
6553 .addImm(NumLPads >> 16));
6554 }
6555
Bill Wendling85833f72011-10-18 22:49:07 +00006556 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6557 .addReg(NewVReg1)
6558 .addReg(VReg2));
6559 }
Bill Wendlingb2a703d2011-10-18 21:55:58 +00006560
Bill Wendling5626c662011-10-06 22:53:00 +00006561 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6562 .addMBB(TrapBB)
6563 .addImm(ARMCC::HI)
6564 .addReg(ARM::CPSR);
Bill Wendling324be982011-10-05 00:39:32 +00006565
Bill Wendlingb2a703d2011-10-18 21:55:58 +00006566 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6567 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
Bill Wendling5626c662011-10-06 22:53:00 +00006568 .addJumpTableIndex(MJTI)
6569 .addImm(UId));
Bill Wendling202803e2011-10-05 00:02:33 +00006570
Bill Wendlingb2a703d2011-10-18 21:55:58 +00006571 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
Bill Wendling5626c662011-10-06 22:53:00 +00006572 AddDefaultCC(
6573 AddDefaultPred(
Bill Wendlingb2a703d2011-10-18 21:55:58 +00006574 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6575 .addReg(NewVReg3, RegState::Kill)
Bill Wendling5626c662011-10-06 22:53:00 +00006576 .addReg(NewVReg1)
6577 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6578
6579 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
Bill Wendlingb2a703d2011-10-18 21:55:58 +00006580 .addReg(NewVReg4, RegState::Kill)
Bill Wendling202803e2011-10-05 00:02:33 +00006581 .addReg(NewVReg1)
Bill Wendling5626c662011-10-06 22:53:00 +00006582 .addJumpTableIndex(MJTI)
6583 .addImm(UId);
6584 } else if (Subtarget->isThumb()) {
Bill Wendlingb3d46782011-10-06 23:37:36 +00006585 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6586 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6587 .addFrameIndex(FI)
6588 .addImm(1)
6589 .addMemOperand(FIMMOLd));
Bill Wendlingf9f5e452011-10-07 22:08:37 +00006590
Bill Wendling64e6bfc2011-10-18 23:11:05 +00006591 if (NumLPads < 256) {
6592 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6593 .addReg(NewVReg1)
6594 .addImm(NumLPads));
6595 } else {
6596 MachineConstantPool *ConstantPool = MF->getConstantPool();
Bill Wendling2977a152011-10-19 09:24:02 +00006597 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6598 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6599
6600 // MachineConstantPool wants an explicit alignment.
Micah Villmowcdfe20b2012-10-08 16:38:25 +00006601 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
Bill Wendling2977a152011-10-19 09:24:02 +00006602 if (Align == 0)
Micah Villmowcdfe20b2012-10-08 16:38:25 +00006603 Align = getDataLayout()->getTypeAllocSize(C->getType());
Bill Wendling2977a152011-10-19 09:24:02 +00006604 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
Bill Wendling64e6bfc2011-10-18 23:11:05 +00006605
6606 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6607 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6608 .addReg(VReg1, RegState::Define)
6609 .addConstantPoolIndex(Idx));
6610 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6611 .addReg(NewVReg1)
6612 .addReg(VReg1));
6613 }
6614
Bill Wendlingb3d46782011-10-06 23:37:36 +00006615 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6616 .addMBB(TrapBB)
6617 .addImm(ARMCC::HI)
6618 .addReg(ARM::CPSR);
6619
6620 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6621 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6622 .addReg(ARM::CPSR, RegState::Define)
6623 .addReg(NewVReg1)
6624 .addImm(2));
6625
6626 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
Bill Wendling8d50ea02011-10-06 23:41:14 +00006627 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
Bill Wendlingb3d46782011-10-06 23:37:36 +00006628 .addJumpTableIndex(MJTI)
6629 .addImm(UId));
6630
6631 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6632 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6633 .addReg(ARM::CPSR, RegState::Define)
6634 .addReg(NewVReg2, RegState::Kill)
6635 .addReg(NewVReg3));
6636
6637 MachineMemOperand *JTMMOLd =
6638 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6639 MachineMemOperand::MOLoad, 4, 4);
6640
6641 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6642 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6643 .addReg(NewVReg4, RegState::Kill)
6644 .addImm(0)
6645 .addMemOperand(JTMMOLd));
6646
Chad Rosier96603432013-03-01 18:30:38 +00006647 unsigned NewVReg6 = NewVReg5;
6648 if (RelocM == Reloc::PIC_) {
6649 NewVReg6 = MRI->createVirtualRegister(TRC);
6650 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6651 .addReg(ARM::CPSR, RegState::Define)
6652 .addReg(NewVReg5, RegState::Kill)
6653 .addReg(NewVReg3));
6654 }
Bill Wendlingb3d46782011-10-06 23:37:36 +00006655
6656 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6657 .addReg(NewVReg6, RegState::Kill)
6658 .addJumpTableIndex(MJTI)
6659 .addImm(UId);
Bill Wendling5626c662011-10-06 22:53:00 +00006660 } else {
6661 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6662 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6663 .addFrameIndex(FI)
6664 .addImm(4)
6665 .addMemOperand(FIMMOLd));
Bill Wendling973c8172011-10-18 22:11:18 +00006666
Bill Wendling4969dcd2011-10-18 22:52:20 +00006667 if (NumLPads < 256) {
6668 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6669 .addReg(NewVReg1)
6670 .addImm(NumLPads));
Bill Wendling2977a152011-10-19 09:24:02 +00006671 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
Bill Wendling4969dcd2011-10-18 22:52:20 +00006672 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6673 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
Bill Wendling94f60012011-10-18 23:19:55 +00006674 .addImm(NumLPads & 0xFFFF));
6675
6676 unsigned VReg2 = VReg1;
6677 if ((NumLPads & 0xFFFF0000) != 0) {
6678 VReg2 = MRI->createVirtualRegister(TRC);
6679 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6680 .addReg(VReg1)
6681 .addImm(NumLPads >> 16));
6682 }
6683
Bill Wendling4969dcd2011-10-18 22:52:20 +00006684 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6685 .addReg(NewVReg1)
6686 .addReg(VReg2));
Bill Wendling2977a152011-10-19 09:24:02 +00006687 } else {
6688 MachineConstantPool *ConstantPool = MF->getConstantPool();
6689 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6690 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6691
6692 // MachineConstantPool wants an explicit alignment.
Micah Villmowcdfe20b2012-10-08 16:38:25 +00006693 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
Bill Wendling2977a152011-10-19 09:24:02 +00006694 if (Align == 0)
Micah Villmowcdfe20b2012-10-08 16:38:25 +00006695 Align = getDataLayout()->getTypeAllocSize(C->getType());
Bill Wendling2977a152011-10-19 09:24:02 +00006696 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6697
6698 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6699 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6700 .addReg(VReg1, RegState::Define)
Bill Wendlingcf7bdf42011-10-20 20:37:11 +00006701 .addConstantPoolIndex(Idx)
6702 .addImm(0));
Bill Wendling2977a152011-10-19 09:24:02 +00006703 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6704 .addReg(NewVReg1)
6705 .addReg(VReg1, RegState::Kill));
Bill Wendling4969dcd2011-10-18 22:52:20 +00006706 }
6707
Bill Wendling5626c662011-10-06 22:53:00 +00006708 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6709 .addMBB(TrapBB)
6710 .addImm(ARMCC::HI)
6711 .addReg(ARM::CPSR);
Bill Wendling202803e2011-10-05 00:02:33 +00006712
Bill Wendling973c8172011-10-18 22:11:18 +00006713 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
Bill Wendling5626c662011-10-06 22:53:00 +00006714 AddDefaultCC(
Bill Wendling973c8172011-10-18 22:11:18 +00006715 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
Bill Wendling5626c662011-10-06 22:53:00 +00006716 .addReg(NewVReg1)
6717 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
Bill Wendling973c8172011-10-18 22:11:18 +00006718 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6719 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
Bill Wendling5626c662011-10-06 22:53:00 +00006720 .addJumpTableIndex(MJTI)
6721 .addImm(UId));
6722
6723 MachineMemOperand *JTMMOLd =
6724 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6725 MachineMemOperand::MOLoad, 4, 4);
Bill Wendling973c8172011-10-18 22:11:18 +00006726 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
Bill Wendling5626c662011-10-06 22:53:00 +00006727 AddDefaultPred(
Bill Wendling973c8172011-10-18 22:11:18 +00006728 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6729 .addReg(NewVReg3, RegState::Kill)
6730 .addReg(NewVReg4)
Bill Wendling5626c662011-10-06 22:53:00 +00006731 .addImm(0)
6732 .addMemOperand(JTMMOLd));
6733
Chad Rosier96603432013-03-01 18:30:38 +00006734 if (RelocM == Reloc::PIC_) {
6735 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6736 .addReg(NewVReg5, RegState::Kill)
6737 .addReg(NewVReg4)
6738 .addJumpTableIndex(MJTI)
6739 .addImm(UId);
6740 } else {
6741 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6742 .addReg(NewVReg5, RegState::Kill)
6743 .addJumpTableIndex(MJTI)
6744 .addImm(UId);
6745 }
Bill Wendling5626c662011-10-06 22:53:00 +00006746 }
Bill Wendling202803e2011-10-05 00:02:33 +00006747
Bill Wendling324be982011-10-05 00:39:32 +00006748 // Add the jump table entries as successors to the MBB.
Jakob Stoklund Olesen710093e2012-08-20 20:52:03 +00006749 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
Bill Wendling324be982011-10-05 00:39:32 +00006750 for (std::vector<MachineBasicBlock*>::iterator
Bill Wendling883ec972011-10-07 23:18:02 +00006751 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6752 MachineBasicBlock *CurMBB = *I;
Jakob Stoklund Olesen710093e2012-08-20 20:52:03 +00006753 if (SeenMBBs.insert(CurMBB))
Bill Wendling883ec972011-10-07 23:18:02 +00006754 DispContBB->addSuccessor(CurMBB);
Bill Wendling883ec972011-10-07 23:18:02 +00006755 }
6756
Bill Wendling26d27802011-10-17 05:25:09 +00006757 // N.B. the order the invoke BBs are processed in doesn't matter here.
Craig Topper840beec2014-04-04 05:16:06 +00006758 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
Bill Wendling617075f2011-10-18 18:30:49 +00006759 SmallVector<MachineBasicBlock*, 64> MBBLPads;
Bill Wendling883ec972011-10-07 23:18:02 +00006760 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
6761 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
6762 MachineBasicBlock *BB = *I;
Bill Wendling6f3f9a32011-10-14 23:34:37 +00006763
6764 // Remove the landing pad successor from the invoke block and replace it
6765 // with the new dispatch block.
Bill Wendling1414bc52011-10-26 07:16:18 +00006766 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6767 BB->succ_end());
6768 while (!Successors.empty()) {
6769 MachineBasicBlock *SMBB = Successors.pop_back_val();
Bill Wendling883ec972011-10-07 23:18:02 +00006770 if (SMBB->isLandingPad()) {
6771 BB->removeSuccessor(SMBB);
Bill Wendling617075f2011-10-18 18:30:49 +00006772 MBBLPads.push_back(SMBB);
Bill Wendling883ec972011-10-07 23:18:02 +00006773 }
6774 }
6775
6776 BB->addSuccessor(DispatchBB);
Bill Wendling6f3f9a32011-10-14 23:34:37 +00006777
6778 // Find the invoke call and mark all of the callee-saved registers as
6779 // 'implicit defined' so that they're spilled. This prevents code from
6780 // moving instructions to before the EH block, where they will never be
6781 // executed.
6782 for (MachineBasicBlock::reverse_iterator
6783 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
Evan Cheng7f8e5632011-12-07 07:15:52 +00006784 if (!II->isCall()) continue;
Bill Wendling6f3f9a32011-10-14 23:34:37 +00006785
6786 DenseMap<unsigned, bool> DefRegs;
6787 for (MachineInstr::mop_iterator
6788 OI = II->operands_begin(), OE = II->operands_end();
6789 OI != OE; ++OI) {
6790 if (!OI->isReg()) continue;
6791 DefRegs[OI->getReg()] = true;
6792 }
6793
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +00006794 MachineInstrBuilder MIB(*MF, &*II);
Bill Wendling6f3f9a32011-10-14 23:34:37 +00006795
Bill Wendling9e0cd1e2011-10-14 23:55:44 +00006796 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
Bill Wendling94e66432011-10-22 00:29:28 +00006797 unsigned Reg = SavedRegs[i];
6798 if (Subtarget->isThumb2() &&
Craig Topperc7242e02012-04-20 07:30:17 +00006799 !ARM::tGPRRegClass.contains(Reg) &&
6800 !ARM::hGPRRegClass.contains(Reg))
Bill Wendling94e66432011-10-22 00:29:28 +00006801 continue;
Craig Topperc7242e02012-04-20 07:30:17 +00006802 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
Bill Wendling94e66432011-10-22 00:29:28 +00006803 continue;
Craig Topperc7242e02012-04-20 07:30:17 +00006804 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
Bill Wendling94e66432011-10-22 00:29:28 +00006805 continue;
6806 if (!DefRegs[Reg])
6807 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
Bill Wendling9e0cd1e2011-10-14 23:55:44 +00006808 }
Bill Wendling6f3f9a32011-10-14 23:34:37 +00006809
6810 break;
6811 }
Bill Wendling883ec972011-10-07 23:18:02 +00006812 }
Bill Wendling324be982011-10-05 00:39:32 +00006813
Bill Wendling617075f2011-10-18 18:30:49 +00006814 // Mark all former landing pads as non-landing pads. The dispatch is the only
6815 // landing pad now.
6816 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6817 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
6818 (*I)->setIsLandingPad(false);
6819
Bill Wendling324be982011-10-05 00:39:32 +00006820 // The instruction is gone now.
6821 MI->eraseFromParent();
6822
Bill Wendling374ee192011-10-03 21:25:38 +00006823 return MBB;
6824}
6825
Evan Cheng0cc4ad92010-07-13 19:27:42 +00006826static
6827MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
6828 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
6829 E = MBB->succ_end(); I != E; ++I)
6830 if (*I != Succ)
6831 return *I;
6832 llvm_unreachable("Expecting a BB with two successors!");
6833}
6834
Manman Renb504f492013-10-29 22:27:32 +00006835/// Return the load opcode for a given load size. If load size >= 8,
6836/// neon opcode will be returned.
6837static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
6838 if (LdSize >= 8)
6839 return LdSize == 16 ? ARM::VLD1q32wb_fixed
6840 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
6841 if (IsThumb1)
6842 return LdSize == 4 ? ARM::tLDRi
6843 : LdSize == 2 ? ARM::tLDRHi
6844 : LdSize == 1 ? ARM::tLDRBi : 0;
6845 if (IsThumb2)
6846 return LdSize == 4 ? ARM::t2LDR_POST
6847 : LdSize == 2 ? ARM::t2LDRH_POST
6848 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
6849 return LdSize == 4 ? ARM::LDR_POST_IMM
6850 : LdSize == 2 ? ARM::LDRH_POST
6851 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
6852}
6853
6854/// Return the store opcode for a given store size. If store size >= 8,
6855/// neon opcode will be returned.
6856static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
6857 if (StSize >= 8)
6858 return StSize == 16 ? ARM::VST1q32wb_fixed
6859 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
6860 if (IsThumb1)
6861 return StSize == 4 ? ARM::tSTRi
6862 : StSize == 2 ? ARM::tSTRHi
6863 : StSize == 1 ? ARM::tSTRBi : 0;
6864 if (IsThumb2)
6865 return StSize == 4 ? ARM::t2STR_POST
6866 : StSize == 2 ? ARM::t2STRH_POST
6867 : StSize == 1 ? ARM::t2STRB_POST : 0;
6868 return StSize == 4 ? ARM::STR_POST_IMM
6869 : StSize == 2 ? ARM::STRH_POST
6870 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
6871}
6872
6873/// Emit a post-increment load operation with given size. The instructions
6874/// will be added to BB at Pos.
6875static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
6876 const TargetInstrInfo *TII, DebugLoc dl,
6877 unsigned LdSize, unsigned Data, unsigned AddrIn,
6878 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
6879 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
6880 assert(LdOpc != 0 && "Should have a load opcode");
6881 if (LdSize >= 8) {
6882 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6883 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6884 .addImm(0));
6885 } else if (IsThumb1) {
6886 // load + update AddrIn
6887 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6888 .addReg(AddrIn).addImm(0));
6889 MachineInstrBuilder MIB =
6890 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
6891 MIB = AddDefaultT1CC(MIB);
6892 MIB.addReg(AddrIn).addImm(LdSize);
6893 AddDefaultPred(MIB);
6894 } else if (IsThumb2) {
6895 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6896 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6897 .addImm(LdSize));
6898 } else { // arm
6899 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6900 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6901 .addReg(0).addImm(LdSize));
6902 }
6903}
6904
6905/// Emit a post-increment store operation with given size. The instructions
6906/// will be added to BB at Pos.
6907static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
6908 const TargetInstrInfo *TII, DebugLoc dl,
6909 unsigned StSize, unsigned Data, unsigned AddrIn,
6910 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
6911 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
6912 assert(StOpc != 0 && "Should have a store opcode");
6913 if (StSize >= 8) {
6914 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6915 .addReg(AddrIn).addImm(0).addReg(Data));
6916 } else if (IsThumb1) {
6917 // store + update AddrIn
6918 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
6919 .addReg(AddrIn).addImm(0));
6920 MachineInstrBuilder MIB =
6921 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
6922 MIB = AddDefaultT1CC(MIB);
6923 MIB.addReg(AddrIn).addImm(StSize);
6924 AddDefaultPred(MIB);
6925 } else if (IsThumb2) {
6926 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6927 .addReg(Data).addReg(AddrIn).addImm(StSize));
6928 } else { // arm
6929 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6930 .addReg(Data).addReg(AddrIn).addReg(0)
6931 .addImm(StSize));
6932 }
6933}
6934
David Peixottoc32e24a2013-10-17 19:49:22 +00006935MachineBasicBlock *
6936ARMTargetLowering::EmitStructByval(MachineInstr *MI,
6937 MachineBasicBlock *BB) const {
Manman Rene8735522012-06-01 19:33:18 +00006938 // This pseudo instruction has 3 operands: dst, src, size
6939 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
6940 // Otherwise, we will generate unrolled scalar copies.
6941 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6942 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6943 MachineFunction::iterator It = BB;
6944 ++It;
6945
6946 unsigned dest = MI->getOperand(0).getReg();
6947 unsigned src = MI->getOperand(1).getReg();
6948 unsigned SizeVal = MI->getOperand(2).getImm();
6949 unsigned Align = MI->getOperand(3).getImm();
6950 DebugLoc dl = MI->getDebugLoc();
6951
Manman Rene8735522012-06-01 19:33:18 +00006952 MachineFunction *MF = BB->getParent();
6953 MachineRegisterInfo &MRI = MF->getRegInfo();
David Peixottoc32e24a2013-10-17 19:49:22 +00006954 unsigned UnitSize = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +00006955 const TargetRegisterClass *TRC = nullptr;
6956 const TargetRegisterClass *VecTRC = nullptr;
David Peixottob0653e532013-10-24 16:39:36 +00006957
6958 bool IsThumb1 = Subtarget->isThumb1Only();
6959 bool IsThumb2 = Subtarget->isThumb2();
Manman Rene8735522012-06-01 19:33:18 +00006960
6961 if (Align & 1) {
Manman Rene8735522012-06-01 19:33:18 +00006962 UnitSize = 1;
6963 } else if (Align & 2) {
Manman Rene8735522012-06-01 19:33:18 +00006964 UnitSize = 2;
6965 } else {
Manman Ren6e1fd462012-06-18 22:23:48 +00006966 // Check whether we can use NEON instructions.
Bill Wendling698e84f2012-12-30 10:32:01 +00006967 if (!MF->getFunction()->getAttributes().
6968 hasAttribute(AttributeSet::FunctionIndex,
6969 Attribute::NoImplicitFloat) &&
Manman Ren6e1fd462012-06-18 22:23:48 +00006970 Subtarget->hasNEON()) {
David Peixottoc32e24a2013-10-17 19:49:22 +00006971 if ((Align % 16 == 0) && SizeVal >= 16)
Manman Ren6e1fd462012-06-18 22:23:48 +00006972 UnitSize = 16;
David Peixottoc32e24a2013-10-17 19:49:22 +00006973 else if ((Align % 8 == 0) && SizeVal >= 8)
Manman Ren6e1fd462012-06-18 22:23:48 +00006974 UnitSize = 8;
Manman Ren6e1fd462012-06-18 22:23:48 +00006975 }
6976 // Can't use NEON instructions.
David Peixottoc32e24a2013-10-17 19:49:22 +00006977 if (UnitSize == 0)
Manman Ren6e1fd462012-06-18 22:23:48 +00006978 UnitSize = 4;
Manman Rene8735522012-06-01 19:33:18 +00006979 }
Manman Ren6e1fd462012-06-18 22:23:48 +00006980
David Peixottob0653e532013-10-24 16:39:36 +00006981 // Select the correct opcode and register class for unit size load/store
6982 bool IsNeon = UnitSize >= 8;
6983 TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
6984 : (const TargetRegisterClass *)&ARM::GPRRegClass;
Manman Renb504f492013-10-29 22:27:32 +00006985 if (IsNeon)
David Peixottob0653e532013-10-24 16:39:36 +00006986 VecTRC = UnitSize == 16
6987 ? (const TargetRegisterClass *)&ARM::DPairRegClass
6988 : UnitSize == 8
6989 ? (const TargetRegisterClass *)&ARM::DPRRegClass
Craig Topper062a2ba2014-04-25 05:30:21 +00006990 : nullptr;
David Peixottob0653e532013-10-24 16:39:36 +00006991
Manman Rene8735522012-06-01 19:33:18 +00006992 unsigned BytesLeft = SizeVal % UnitSize;
6993 unsigned LoopSize = SizeVal - BytesLeft;
6994
6995 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
6996 // Use LDR and STR to copy.
6997 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
6998 // [destOut] = STR_POST(scratch, destIn, UnitSize)
6999 unsigned srcIn = src;
7000 unsigned destIn = dest;
7001 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
David Peixottob0653e532013-10-24 16:39:36 +00007002 unsigned srcOut = MRI.createVirtualRegister(TRC);
7003 unsigned destOut = MRI.createVirtualRegister(TRC);
7004 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
Manman Renb504f492013-10-29 22:27:32 +00007005 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7006 IsThumb1, IsThumb2);
7007 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7008 IsThumb1, IsThumb2);
David Peixottob0653e532013-10-24 16:39:36 +00007009 srcIn = srcOut;
7010 destIn = destOut;
Manman Rene8735522012-06-01 19:33:18 +00007011 }
7012
7013 // Handle the leftover bytes with LDRB and STRB.
7014 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7015 // [destOut] = STRB_POST(scratch, destIn, 1)
Manman Rene8735522012-06-01 19:33:18 +00007016 for (unsigned i = 0; i < BytesLeft; i++) {
David Peixottob0653e532013-10-24 16:39:36 +00007017 unsigned srcOut = MRI.createVirtualRegister(TRC);
7018 unsigned destOut = MRI.createVirtualRegister(TRC);
7019 unsigned scratch = MRI.createVirtualRegister(TRC);
Manman Renb504f492013-10-29 22:27:32 +00007020 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7021 IsThumb1, IsThumb2);
7022 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7023 IsThumb1, IsThumb2);
David Peixottob0653e532013-10-24 16:39:36 +00007024 srcIn = srcOut;
7025 destIn = destOut;
Manman Rene8735522012-06-01 19:33:18 +00007026 }
7027 MI->eraseFromParent(); // The instruction is gone now.
7028 return BB;
7029 }
7030
7031 // Expand the pseudo op to a loop.
7032 // thisMBB:
7033 // ...
7034 // movw varEnd, # --> with thumb2
7035 // movt varEnd, #
7036 // ldrcp varEnd, idx --> without thumb2
7037 // fallthrough --> loopMBB
7038 // loopMBB:
7039 // PHI varPhi, varEnd, varLoop
7040 // PHI srcPhi, src, srcLoop
7041 // PHI destPhi, dst, destLoop
7042 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7043 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7044 // subs varLoop, varPhi, #UnitSize
7045 // bne loopMBB
7046 // fallthrough --> exitMBB
7047 // exitMBB:
7048 // epilogue to handle left-over bytes
7049 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7050 // [destOut] = STRB_POST(scratch, destLoop, 1)
7051 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7052 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7053 MF->insert(It, loopMBB);
7054 MF->insert(It, exitMBB);
7055
7056 // Transfer the remainder of BB and its successor edges to exitMBB.
7057 exitMBB->splice(exitMBB->begin(), BB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00007058 std::next(MachineBasicBlock::iterator(MI)), BB->end());
Manman Rene8735522012-06-01 19:33:18 +00007059 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7060
7061 // Load an immediate to varEnd.
David Peixottob0653e532013-10-24 16:39:36 +00007062 unsigned varEnd = MRI.createVirtualRegister(TRC);
7063 if (IsThumb2) {
7064 unsigned Vtmp = varEnd;
7065 if ((LoopSize & 0xFFFF0000) != 0)
7066 Vtmp = MRI.createVirtualRegister(TRC);
7067 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7068 .addImm(LoopSize & 0xFFFF));
7069
7070 if ((LoopSize & 0xFFFF0000) != 0)
7071 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7072 .addReg(Vtmp).addImm(LoopSize >> 16));
7073 } else {
7074 MachineConstantPool *ConstantPool = MF->getConstantPool();
7075 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7076 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7077
7078 // MachineConstantPool wants an explicit alignment.
7079 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7080 if (Align == 0)
7081 Align = getDataLayout()->getTypeAllocSize(C->getType());
7082 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7083
7084 if (IsThumb1)
7085 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7086 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7087 else
7088 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7089 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7090 }
Manman Rene8735522012-06-01 19:33:18 +00007091 BB->addSuccessor(loopMBB);
7092
7093 // Generate the loop body:
7094 // varPhi = PHI(varLoop, varEnd)
7095 // srcPhi = PHI(srcLoop, src)
7096 // destPhi = PHI(destLoop, dst)
7097 MachineBasicBlock *entryBB = BB;
7098 BB = loopMBB;
David Peixottob0653e532013-10-24 16:39:36 +00007099 unsigned varLoop = MRI.createVirtualRegister(TRC);
7100 unsigned varPhi = MRI.createVirtualRegister(TRC);
7101 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7102 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7103 unsigned destLoop = MRI.createVirtualRegister(TRC);
7104 unsigned destPhi = MRI.createVirtualRegister(TRC);
Manman Rene8735522012-06-01 19:33:18 +00007105
7106 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7107 .addReg(varLoop).addMBB(loopMBB)
7108 .addReg(varEnd).addMBB(entryBB);
7109 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7110 .addReg(srcLoop).addMBB(loopMBB)
7111 .addReg(src).addMBB(entryBB);
7112 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7113 .addReg(destLoop).addMBB(loopMBB)
7114 .addReg(dest).addMBB(entryBB);
7115
7116 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7117 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
David Peixottob0653e532013-10-24 16:39:36 +00007118 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
Manman Renb504f492013-10-29 22:27:32 +00007119 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7120 IsThumb1, IsThumb2);
7121 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7122 IsThumb1, IsThumb2);
Manman Rene8735522012-06-01 19:33:18 +00007123
7124 // Decrement loop variable by UnitSize.
David Peixottob0653e532013-10-24 16:39:36 +00007125 if (IsThumb1) {
7126 MachineInstrBuilder MIB =
7127 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7128 MIB = AddDefaultT1CC(MIB);
7129 MIB.addReg(varPhi).addImm(UnitSize);
7130 AddDefaultPred(MIB);
7131 } else {
7132 MachineInstrBuilder MIB =
7133 BuildMI(*BB, BB->end(), dl,
7134 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7135 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7136 MIB->getOperand(5).setReg(ARM::CPSR);
7137 MIB->getOperand(5).setIsDef(true);
7138 }
7139 BuildMI(*BB, BB->end(), dl,
7140 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7141 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
Manman Rene8735522012-06-01 19:33:18 +00007142
7143 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7144 BB->addSuccessor(loopMBB);
7145 BB->addSuccessor(exitMBB);
7146
7147 // Add epilogue to handle BytesLeft.
7148 BB = exitMBB;
7149 MachineInstr *StartOfExit = exitMBB->begin();
Manman Rene8735522012-06-01 19:33:18 +00007150
7151 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7152 // [destOut] = STRB_POST(scratch, destLoop, 1)
7153 unsigned srcIn = srcLoop;
7154 unsigned destIn = destLoop;
7155 for (unsigned i = 0; i < BytesLeft; i++) {
David Peixottob0653e532013-10-24 16:39:36 +00007156 unsigned srcOut = MRI.createVirtualRegister(TRC);
7157 unsigned destOut = MRI.createVirtualRegister(TRC);
7158 unsigned scratch = MRI.createVirtualRegister(TRC);
Manman Renb504f492013-10-29 22:27:32 +00007159 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7160 IsThumb1, IsThumb2);
7161 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7162 IsThumb1, IsThumb2);
David Peixottob0653e532013-10-24 16:39:36 +00007163 srcIn = srcOut;
7164 destIn = destOut;
Manman Rene8735522012-06-01 19:33:18 +00007165 }
7166
7167 MI->eraseFromParent(); // The instruction is gone now.
7168 return BB;
7169}
7170
Jim Grosbach8f9a3ac2009-12-12 01:40:06 +00007171MachineBasicBlock *
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +00007172ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7173 MachineBasicBlock *MBB) const {
7174 const TargetMachine &TM = getTargetMachine();
7175 const TargetInstrInfo &TII = *TM.getInstrInfo();
7176 DebugLoc DL = MI->getDebugLoc();
7177
7178 assert(Subtarget->isTargetWindows() &&
7179 "__chkstk is only supported on Windows");
7180 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7181
7182 // __chkstk takes the number of words to allocate on the stack in R4, and
7183 // returns the stack adjustment in number of bytes in R4. This will not
7184 // clober any other registers (other than the obvious lr).
7185 //
7186 // Although, technically, IP should be considered a register which may be
7187 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7188 // thumb-2 environment, so there is no interworking required. As a result, we
7189 // do not expect a veneer to be emitted by the linker, clobbering IP.
7190 //
Alp Toker1d099d92014-06-19 19:41:26 +00007191 // Each module receives its own copy of __chkstk, so no import thunk is
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +00007192 // required, again, ensuring that IP is not clobbered.
7193 //
7194 // Finally, although some linkers may theoretically provide a trampoline for
7195 // out of range calls (which is quite common due to a 32M range limitation of
7196 // branches for Thumb), we can generate the long-call version via
7197 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7198 // IP.
7199
7200 switch (TM.getCodeModel()) {
7201 case CodeModel::Small:
7202 case CodeModel::Medium:
7203 case CodeModel::Default:
7204 case CodeModel::Kernel:
7205 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7206 .addImm((unsigned)ARMCC::AL).addReg(0)
7207 .addExternalSymbol("__chkstk")
7208 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7209 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7210 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7211 break;
7212 case CodeModel::Large:
7213 case CodeModel::JITDefault: {
7214 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7215 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7216
7217 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7218 .addExternalSymbol("__chkstk");
7219 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7220 .addImm((unsigned)ARMCC::AL).addReg(0)
7221 .addReg(Reg, RegState::Kill)
7222 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7223 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7224 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7225 break;
7226 }
7227 }
7228
7229 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7230 ARM::SP)
Saleem Abdulrasoolc4e00282014-07-19 01:29:51 +00007231 .addReg(ARM::SP).addReg(ARM::R4)));
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +00007232
7233 MI->eraseFromParent();
7234 return MBB;
7235}
7236
7237MachineBasicBlock *
Evan Cheng29cfb672008-01-30 18:18:23 +00007238ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohman25c16532010-05-01 00:01:06 +00007239 MachineBasicBlock *BB) const {
Evan Cheng10043e22007-01-19 07:51:42 +00007240 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Dale Johannesen7647da62009-02-13 02:25:56 +00007241 DebugLoc dl = MI->getDebugLoc();
Jim Grosbach57ccc192009-12-14 20:14:59 +00007242 bool isThumb2 = Subtarget->isThumb2();
Evan Cheng10043e22007-01-19 07:51:42 +00007243 switch (MI->getOpcode()) {
Andrew Trick0ed57782011-04-23 03:55:32 +00007244 default: {
Jim Grosbach5c4e99f2009-12-11 01:42:04 +00007245 MI->dump();
Evan Chengb972e562009-08-07 00:34:42 +00007246 llvm_unreachable("Unexpected instr type to insert");
Andrew Trick0ed57782011-04-23 03:55:32 +00007247 }
Jim Grosbach9c0b86a2011-09-16 21:55:56 +00007248 // The Thumb2 pre-indexed stores have the same MI operands, they just
7249 // define them differently in the .td files from the isel patterns, so
7250 // they need pseudos.
7251 case ARM::t2STR_preidx:
7252 MI->setDesc(TII->get(ARM::t2STR_PRE));
7253 return BB;
7254 case ARM::t2STRB_preidx:
7255 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7256 return BB;
7257 case ARM::t2STRH_preidx:
7258 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7259 return BB;
7260
Jim Grosbachf0c95ca2011-08-05 20:35:44 +00007261 case ARM::STRi_preidx:
7262 case ARM::STRBi_preidx: {
Jim Grosbach5e80abb2011-08-09 21:22:41 +00007263 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
Jim Grosbachf0c95ca2011-08-05 20:35:44 +00007264 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7265 // Decode the offset.
7266 unsigned Offset = MI->getOperand(4).getImm();
7267 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7268 Offset = ARM_AM::getAM2Offset(Offset);
7269 if (isSub)
7270 Offset = -Offset;
7271
Jim Grosbachf402f692011-08-12 21:02:34 +00007272 MachineMemOperand *MMO = *MI->memoperands_begin();
Benjamin Kramer61a1ff52011-08-27 17:36:14 +00007273 BuildMI(*BB, MI, dl, TII->get(NewOpc))
Jim Grosbachf0c95ca2011-08-05 20:35:44 +00007274 .addOperand(MI->getOperand(0)) // Rn_wb
7275 .addOperand(MI->getOperand(1)) // Rt
7276 .addOperand(MI->getOperand(2)) // Rn
7277 .addImm(Offset) // offset (skip GPR==zero_reg)
7278 .addOperand(MI->getOperand(5)) // pred
Jim Grosbachf402f692011-08-12 21:02:34 +00007279 .addOperand(MI->getOperand(6))
7280 .addMemOperand(MMO);
Jim Grosbachf0c95ca2011-08-05 20:35:44 +00007281 MI->eraseFromParent();
7282 return BB;
7283 }
7284 case ARM::STRr_preidx:
Jim Grosbachd886f8c2011-08-11 21:17:22 +00007285 case ARM::STRBr_preidx:
7286 case ARM::STRH_preidx: {
7287 unsigned NewOpc;
7288 switch (MI->getOpcode()) {
7289 default: llvm_unreachable("unexpected opcode!");
7290 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7291 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7292 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7293 }
Jim Grosbachf0c95ca2011-08-05 20:35:44 +00007294 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7295 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7296 MIB.addOperand(MI->getOperand(i));
7297 MI->eraseFromParent();
7298 return BB;
7299 }
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +00007300
Evan Chengbb2af352009-08-12 05:17:19 +00007301 case ARM::tMOVCCr_pseudo: {
Evan Cheng10043e22007-01-19 07:51:42 +00007302 // To "insert" a SELECT_CC instruction, we actually have to insert the
7303 // diamond control-flow pattern. The incoming instruction knows the
7304 // destination vreg to set, the condition code register to branch on, the
7305 // true/false values to select between, and a branch opcode to use.
7306 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Dan Gohman3b460302008-07-07 23:14:23 +00007307 MachineFunction::iterator It = BB;
Evan Cheng10043e22007-01-19 07:51:42 +00007308 ++It;
7309
7310 // thisMBB:
7311 // ...
7312 // TrueVal = ...
7313 // cmpTY ccX, r1, r2
7314 // bCC copy1MBB
7315 // fallthrough --> copy0MBB
7316 MachineBasicBlock *thisMBB = BB;
Dan Gohman3b460302008-07-07 23:14:23 +00007317 MachineFunction *F = BB->getParent();
7318 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7319 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
Dan Gohmanf4f04102010-07-06 15:49:48 +00007320 F->insert(It, copy0MBB);
7321 F->insert(It, sinkMBB);
Dan Gohman34396292010-07-06 20:24:04 +00007322
7323 // Transfer the remainder of BB and its successor edges to sinkMBB.
7324 sinkMBB->splice(sinkMBB->begin(), BB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00007325 std::next(MachineBasicBlock::iterator(MI)), BB->end());
Dan Gohman34396292010-07-06 20:24:04 +00007326 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7327
Dan Gohmanf4f04102010-07-06 15:49:48 +00007328 BB->addSuccessor(copy0MBB);
7329 BB->addSuccessor(sinkMBB);
Dan Gohman12205642010-07-06 15:18:19 +00007330
Dan Gohman34396292010-07-06 20:24:04 +00007331 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7332 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7333
Evan Cheng10043e22007-01-19 07:51:42 +00007334 // copy0MBB:
7335 // %FalseValue = ...
7336 // # fallthrough to sinkMBB
7337 BB = copy0MBB;
7338
7339 // Update machine-CFG edges
7340 BB->addSuccessor(sinkMBB);
7341
7342 // sinkMBB:
7343 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7344 // ...
7345 BB = sinkMBB;
Dan Gohman34396292010-07-06 20:24:04 +00007346 BuildMI(*BB, BB->begin(), dl,
7347 TII->get(ARM::PHI), MI->getOperand(0).getReg())
Evan Cheng10043e22007-01-19 07:51:42 +00007348 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7349 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7350
Dan Gohman34396292010-07-06 20:24:04 +00007351 MI->eraseFromParent(); // The pseudo instruction is gone now.
Evan Cheng10043e22007-01-19 07:51:42 +00007352 return BB;
7353 }
Evan Chengb972e562009-08-07 00:34:42 +00007354
Evan Cheng0cc4ad92010-07-13 19:27:42 +00007355 case ARM::BCCi64:
7356 case ARM::BCCZi64: {
Bob Wilson36be00c2010-12-23 22:45:49 +00007357 // If there is an unconditional branch to the other successor, remove it.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00007358 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
Andrew Trick5eb0a302011-01-19 02:26:13 +00007359
Evan Cheng0cc4ad92010-07-13 19:27:42 +00007360 // Compare both parts that make up the double comparison separately for
7361 // equality.
7362 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7363
7364 unsigned LHS1 = MI->getOperand(1).getReg();
7365 unsigned LHS2 = MI->getOperand(2).getReg();
7366 if (RHSisZero) {
7367 AddDefaultPred(BuildMI(BB, dl,
7368 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7369 .addReg(LHS1).addImm(0));
7370 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7371 .addReg(LHS2).addImm(0)
7372 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7373 } else {
7374 unsigned RHS1 = MI->getOperand(3).getReg();
7375 unsigned RHS2 = MI->getOperand(4).getReg();
7376 AddDefaultPred(BuildMI(BB, dl,
7377 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7378 .addReg(LHS1).addReg(RHS1));
7379 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7380 .addReg(LHS2).addReg(RHS2)
7381 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7382 }
7383
7384 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7385 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7386 if (MI->getOperand(0).getImm() == ARMCC::NE)
7387 std::swap(destMBB, exitMBB);
7388
7389 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7390 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
Owen Anderson29cfe6c2011-09-09 21:48:23 +00007391 if (isThumb2)
7392 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7393 else
7394 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
Evan Cheng0cc4ad92010-07-13 19:27:42 +00007395
7396 MI->eraseFromParent(); // The pseudo instruction is gone now.
7397 return BB;
7398 }
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007399
Bill Wendlingf7f223f2011-10-17 20:37:20 +00007400 case ARM::Int_eh_sjlj_setjmp:
7401 case ARM::Int_eh_sjlj_setjmp_nofp:
7402 case ARM::tInt_eh_sjlj_setjmp:
7403 case ARM::t2Int_eh_sjlj_setjmp:
7404 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7405 EmitSjLjDispatchBlock(MI, BB);
7406 return BB;
7407
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007408 case ARM::ABS:
7409 case ARM::t2ABS: {
7410 // To insert an ABS instruction, we have to insert the
7411 // diamond control-flow pattern. The incoming instruction knows the
7412 // source vreg to test against 0, the destination vreg to set,
7413 // the condition code register to branch on, the
Andrew Trick3f07c422011-10-18 18:40:53 +00007414 // true/false values to select between, and a branch opcode to use.
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007415 // It transforms
7416 // V1 = ABS V0
7417 // into
7418 // V2 = MOVS V0
7419 // BCC (branch to SinkBB if V0 >= 0)
7420 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
Andrew Trick3f07c422011-10-18 18:40:53 +00007421 // SinkBB: V1 = PHI(V2, V3)
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007422 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7423 MachineFunction::iterator BBI = BB;
7424 ++BBI;
7425 MachineFunction *Fn = BB->getParent();
7426 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7427 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7428 Fn->insert(BBI, RSBBB);
7429 Fn->insert(BBI, SinkBB);
7430
7431 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7432 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7433 bool isThumb2 = Subtarget->isThumb2();
7434 MachineRegisterInfo &MRI = Fn->getRegInfo();
7435 // In Thumb mode S must not be specified if source register is the SP or
7436 // PC and if destination register is the SP, so restrict register class
Craig Topperc7242e02012-04-20 07:30:17 +00007437 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
7438 (const TargetRegisterClass*)&ARM::rGPRRegClass :
7439 (const TargetRegisterClass*)&ARM::GPRRegClass);
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007440
7441 // Transfer the remainder of BB and its successor edges to sinkMBB.
7442 SinkBB->splice(SinkBB->begin(), BB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00007443 std::next(MachineBasicBlock::iterator(MI)), BB->end());
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007444 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7445
7446 BB->addSuccessor(RSBBB);
7447 BB->addSuccessor(SinkBB);
7448
7449 // fall through to SinkMBB
7450 RSBBB->addSuccessor(SinkBB);
7451
Manman Rene0763c72012-06-15 21:32:12 +00007452 // insert a cmp at the end of BB
Andrew Trickbc325162012-07-18 18:34:24 +00007453 AddDefaultPred(BuildMI(BB, dl,
Manman Rene0763c72012-06-15 21:32:12 +00007454 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7455 .addReg(ABSSrcReg).addImm(0));
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007456
7457 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
Andrew Trick3f07c422011-10-18 18:40:53 +00007458 BuildMI(BB, dl,
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007459 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7460 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7461
7462 // insert rsbri in RSBBB
7463 // Note: BCC and rsbri will be converted into predicated rsbmi
7464 // by if-conversion pass
Andrew Trick3f07c422011-10-18 18:40:53 +00007465 BuildMI(*RSBBB, RSBBB->begin(), dl,
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007466 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
Manman Rene0763c72012-06-15 21:32:12 +00007467 .addReg(ABSSrcReg, RegState::Kill)
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007468 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7469
Andrew Trick3f07c422011-10-18 18:40:53 +00007470 // insert PHI in SinkBB,
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007471 // reuse ABSDstReg to not change uses of ABS instruction
7472 BuildMI(*SinkBB, SinkBB->begin(), dl,
7473 TII->get(ARM::PHI), ABSDstReg)
7474 .addReg(NewRsbDstReg).addMBB(RSBBB)
Manman Rene0763c72012-06-15 21:32:12 +00007475 .addReg(ABSSrcReg).addMBB(BB);
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007476
7477 // remove ABS instruction
Andrew Trick3f07c422011-10-18 18:40:53 +00007478 MI->eraseFromParent();
Bill Wendlinga7d697e2011-10-10 22:59:55 +00007479
7480 // return last added BB
7481 return SinkBB;
7482 }
Manman Rene8735522012-06-01 19:33:18 +00007483 case ARM::COPY_STRUCT_BYVAL_I32:
Manman Ren9f911162012-06-01 02:44:42 +00007484 ++NumLoopByVals;
Manman Rene8735522012-06-01 19:33:18 +00007485 return EmitStructByval(MI, BB);
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +00007486 case ARM::WIN__CHKSTK:
7487 return EmitLowered__chkstk(MI, BB);
Evan Cheng10043e22007-01-19 07:51:42 +00007488 }
7489}
7490
Evan Chenge6fba772011-08-30 19:09:48 +00007491void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7492 SDNode *Node) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +00007493 if (!MI->hasPostISelHook()) {
Andrew Trick924123a2011-09-21 02:20:46 +00007494 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
7495 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
7496 return;
7497 }
7498
Evan Cheng7f8e5632011-12-07 07:15:52 +00007499 const MCInstrDesc *MCID = &MI->getDesc();
Andrew Trick8586e622011-09-20 03:17:40 +00007500 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7501 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7502 // operand is still set to noreg. If needed, set the optional operand's
7503 // register to CPSR, and remove the redundant implicit def.
Andrew Trick924123a2011-09-21 02:20:46 +00007504 //
Andrew Trick88b24502011-10-18 19:18:52 +00007505 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
Andrew Trick8586e622011-09-20 03:17:40 +00007506
Andrew Trick924123a2011-09-21 02:20:46 +00007507 // Rename pseudo opcodes.
7508 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7509 if (NewOpc) {
7510 const ARMBaseInstrInfo *TII =
7511 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
Andrew Trick88b24502011-10-18 19:18:52 +00007512 MCID = &TII->get(NewOpc);
7513
7514 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7515 "converted opcode should be the same except for cc_out");
7516
7517 MI->setDesc(*MCID);
7518
7519 // Add the optional cc_out operand
7520 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
Andrew Trick924123a2011-09-21 02:20:46 +00007521 }
Andrew Trick88b24502011-10-18 19:18:52 +00007522 unsigned ccOutIdx = MCID->getNumOperands() - 1;
Andrew Trick8586e622011-09-20 03:17:40 +00007523
7524 // Any ARM instruction that sets the 's' bit should specify an optional
7525 // "cc_out" operand in the last operand position.
Evan Cheng7f8e5632011-12-07 07:15:52 +00007526 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
Andrew Trick924123a2011-09-21 02:20:46 +00007527 assert(!NewOpc && "Optional cc_out operand required");
Andrew Trick8586e622011-09-20 03:17:40 +00007528 return;
7529 }
Andrew Trick924123a2011-09-21 02:20:46 +00007530 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7531 // since we already have an optional CPSR def.
Andrew Trick8586e622011-09-20 03:17:40 +00007532 bool definesCPSR = false;
7533 bool deadCPSR = false;
Andrew Trick88b24502011-10-18 19:18:52 +00007534 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
Andrew Trick8586e622011-09-20 03:17:40 +00007535 i != e; ++i) {
7536 const MachineOperand &MO = MI->getOperand(i);
7537 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7538 definesCPSR = true;
7539 if (MO.isDead())
7540 deadCPSR = true;
7541 MI->RemoveOperand(i);
7542 break;
Evan Chenge6fba772011-08-30 19:09:48 +00007543 }
7544 }
Andrew Trick8586e622011-09-20 03:17:40 +00007545 if (!definesCPSR) {
Andrew Trick924123a2011-09-21 02:20:46 +00007546 assert(!NewOpc && "Optional cc_out operand required");
Andrew Trick8586e622011-09-20 03:17:40 +00007547 return;
7548 }
7549 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
Andrew Trick924123a2011-09-21 02:20:46 +00007550 if (deadCPSR) {
7551 assert(!MI->getOperand(ccOutIdx).getReg() &&
7552 "expect uninitialized optional cc_out operand");
Andrew Trick8586e622011-09-20 03:17:40 +00007553 return;
Andrew Trick924123a2011-09-21 02:20:46 +00007554 }
Andrew Trick8586e622011-09-20 03:17:40 +00007555
Andrew Trick924123a2011-09-21 02:20:46 +00007556 // If this instruction was defined with an optional CPSR def and its dag node
7557 // had a live implicit CPSR def, then activate the optional CPSR def.
Andrew Trick8586e622011-09-20 03:17:40 +00007558 MachineOperand &MO = MI->getOperand(ccOutIdx);
7559 MO.setReg(ARM::CPSR);
7560 MO.setIsDef(true);
Evan Chenge6fba772011-08-30 19:09:48 +00007561}
7562
Evan Cheng10043e22007-01-19 07:51:42 +00007563//===----------------------------------------------------------------------===//
7564// ARM Optimization Hooks
7565//===----------------------------------------------------------------------===//
7566
Jakob Stoklund Olesenc1dee482012-08-17 16:59:09 +00007567// Helper function that checks if N is a null or all ones constant.
7568static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7569 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7570 if (!C)
7571 return false;
7572 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7573}
7574
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007575// Return true if N is conditionally 0 or all ones.
7576// Detects these expressions where cc is an i1 value:
7577//
7578// (select cc 0, y) [AllOnes=0]
7579// (select cc y, 0) [AllOnes=0]
7580// (zext cc) [AllOnes=0]
7581// (sext cc) [AllOnes=0/1]
7582// (select cc -1, y) [AllOnes=1]
7583// (select cc y, -1) [AllOnes=1]
7584//
7585// Invert is set when N is the null/all ones constant when CC is false.
7586// OtherOp is set to the alternative value of N.
7587static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7588 SDValue &CC, bool &Invert,
7589 SDValue &OtherOp,
7590 SelectionDAG &DAG) {
7591 switch (N->getOpcode()) {
7592 default: return false;
7593 case ISD::SELECT: {
7594 CC = N->getOperand(0);
7595 SDValue N1 = N->getOperand(1);
7596 SDValue N2 = N->getOperand(2);
7597 if (isZeroOrAllOnes(N1, AllOnes)) {
7598 Invert = false;
7599 OtherOp = N2;
7600 return true;
7601 }
7602 if (isZeroOrAllOnes(N2, AllOnes)) {
7603 Invert = true;
7604 OtherOp = N1;
7605 return true;
7606 }
7607 return false;
7608 }
7609 case ISD::ZERO_EXTEND:
7610 // (zext cc) can never be the all ones value.
7611 if (AllOnes)
7612 return false;
7613 // Fall through.
7614 case ISD::SIGN_EXTEND: {
7615 EVT VT = N->getValueType(0);
7616 CC = N->getOperand(0);
7617 if (CC.getValueType() != MVT::i1)
7618 return false;
7619 Invert = !AllOnes;
7620 if (AllOnes)
7621 // When looking for an AllOnes constant, N is an sext, and the 'other'
7622 // value is 0.
7623 OtherOp = DAG.getConstant(0, VT);
7624 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7625 // When looking for a 0 constant, N can be zext or sext.
7626 OtherOp = DAG.getConstant(1, VT);
7627 else
7628 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7629 return true;
7630 }
7631 }
7632}
7633
Jakob Stoklund Olesenc1dee482012-08-17 16:59:09 +00007634// Combine a constant select operand into its use:
7635//
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00007636// (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7637// (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7638// (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7639// (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7640// (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
Jakob Stoklund Olesenc1dee482012-08-17 16:59:09 +00007641//
7642// The transform is rejected if the select doesn't have a constant operand that
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00007643// is null, or all ones when AllOnes is set.
Jakob Stoklund Olesenc1dee482012-08-17 16:59:09 +00007644//
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007645// Also recognize sext/zext from i1:
7646//
7647// (add (zext cc), x) -> (select cc (add x, 1), x)
7648// (add (sext cc), x) -> (select cc (add x, -1), x)
7649//
7650// These transformations eventually create predicated instructions.
7651//
Jakob Stoklund Olesenc1dee482012-08-17 16:59:09 +00007652// @param N The node to transform.
7653// @param Slct The N operand that is a select.
7654// @param OtherOp The other N operand (x above).
7655// @param DCI Context.
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00007656// @param AllOnes Require the select constant to be all ones instead of null.
Jakob Stoklund Olesenc1dee482012-08-17 16:59:09 +00007657// @returns The new node, or SDValue() on failure.
Chris Lattner4147f082009-03-12 06:52:53 +00007658static
7659SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00007660 TargetLowering::DAGCombinerInfo &DCI,
7661 bool AllOnes = false) {
Chris Lattner4147f082009-03-12 06:52:53 +00007662 SelectionDAG &DAG = DCI.DAG;
Owen Anderson53aa7a92009-08-10 22:56:29 +00007663 EVT VT = N->getValueType(0);
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007664 SDValue NonConstantVal;
7665 SDValue CCOp;
7666 bool SwapSelectOps;
7667 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7668 NonConstantVal, DAG))
Jakob Stoklund Olesenc1dee482012-08-17 16:59:09 +00007669 return SDValue();
7670
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007671 // Slct is now know to be the desired identity constant when CC is true.
7672 SDValue TrueVal = OtherOp;
Andrew Trickef9de2a2013-05-25 02:42:55 +00007673 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007674 OtherOp, NonConstantVal);
7675 // Unless SwapSelectOps says CC should be false.
7676 if (SwapSelectOps)
7677 std::swap(TrueVal, FalseVal);
7678
Andrew Trickef9de2a2013-05-25 02:42:55 +00007679 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007680 CCOp, TrueVal, FalseVal);
Chris Lattner4147f082009-03-12 06:52:53 +00007681}
7682
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00007683// Attempt combineSelectAndUse on each operand of a commutative operator N.
7684static
7685SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7686 TargetLowering::DAGCombinerInfo &DCI) {
7687 SDValue N0 = N->getOperand(0);
7688 SDValue N1 = N->getOperand(1);
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007689 if (N0.getNode()->hasOneUse()) {
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00007690 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7691 if (Result.getNode())
7692 return Result;
7693 }
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007694 if (N1.getNode()->hasOneUse()) {
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00007695 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7696 if (Result.getNode())
7697 return Result;
7698 }
7699 return SDValue();
7700}
7701
Eric Christopher1b8b94192011-06-29 21:10:36 +00007702// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
Tanya Lattnere9e67052011-06-14 23:48:48 +00007703// (only after legalization).
7704static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7705 TargetLowering::DAGCombinerInfo &DCI,
7706 const ARMSubtarget *Subtarget) {
7707
7708 // Only perform optimization if after legalize, and if NEON is available. We
7709 // also expected both operands to be BUILD_VECTORs.
7710 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7711 || N0.getOpcode() != ISD::BUILD_VECTOR
7712 || N1.getOpcode() != ISD::BUILD_VECTOR)
7713 return SDValue();
7714
7715 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7716 EVT VT = N->getValueType(0);
7717 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7718 return SDValue();
7719
7720 // Check that the vector operands are of the right form.
7721 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7722 // operands, where N is the size of the formed vector.
7723 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7724 // index such that we have a pair wise add pattern.
Tanya Lattnere9e67052011-06-14 23:48:48 +00007725
7726 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
Bob Wilson4b12a112011-06-15 06:04:34 +00007727 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
Tanya Lattnere9e67052011-06-14 23:48:48 +00007728 return SDValue();
Bob Wilson4b12a112011-06-15 06:04:34 +00007729 SDValue Vec = N0->getOperand(0)->getOperand(0);
7730 SDNode *V = Vec.getNode();
7731 unsigned nextIndex = 0;
Tanya Lattnere9e67052011-06-14 23:48:48 +00007732
Eric Christopher1b8b94192011-06-29 21:10:36 +00007733 // For each operands to the ADD which are BUILD_VECTORs,
Tanya Lattnere9e67052011-06-14 23:48:48 +00007734 // check to see if each of their operands are an EXTRACT_VECTOR with
7735 // the same vector and appropriate index.
7736 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7737 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7738 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
Eric Christopher1b8b94192011-06-29 21:10:36 +00007739
Tanya Lattnere9e67052011-06-14 23:48:48 +00007740 SDValue ExtVec0 = N0->getOperand(i);
7741 SDValue ExtVec1 = N1->getOperand(i);
Eric Christopher1b8b94192011-06-29 21:10:36 +00007742
Tanya Lattnere9e67052011-06-14 23:48:48 +00007743 // First operand is the vector, verify its the same.
7744 if (V != ExtVec0->getOperand(0).getNode() ||
7745 V != ExtVec1->getOperand(0).getNode())
7746 return SDValue();
Eric Christopher1b8b94192011-06-29 21:10:36 +00007747
Tanya Lattnere9e67052011-06-14 23:48:48 +00007748 // Second is the constant, verify its correct.
7749 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7750 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
Eric Christopher1b8b94192011-06-29 21:10:36 +00007751
Tanya Lattnere9e67052011-06-14 23:48:48 +00007752 // For the constant, we want to see all the even or all the odd.
7753 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7754 || C1->getZExtValue() != nextIndex+1)
7755 return SDValue();
7756
7757 // Increment index.
7758 nextIndex+=2;
Eric Christopher1b8b94192011-06-29 21:10:36 +00007759 } else
Tanya Lattnere9e67052011-06-14 23:48:48 +00007760 return SDValue();
7761 }
7762
7763 // Create VPADDL node.
7764 SelectionDAG &DAG = DCI.DAG;
7765 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Tanya Lattnere9e67052011-06-14 23:48:48 +00007766
7767 // Build operand list.
7768 SmallVector<SDValue, 8> Ops;
7769 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
7770 TLI.getPointerTy()));
7771
7772 // Input is the vector.
7773 Ops.push_back(Vec);
Eric Christopher1b8b94192011-06-29 21:10:36 +00007774
Tanya Lattnere9e67052011-06-14 23:48:48 +00007775 // Get widened type and narrowed type.
7776 MVT widenType;
7777 unsigned numElem = VT.getVectorNumElements();
Silviu Barangaa3106e62014-04-03 10:44:27 +00007778
7779 EVT inputLaneType = Vec.getValueType().getVectorElementType();
7780 switch (inputLaneType.getSimpleVT().SimpleTy) {
Tanya Lattnere9e67052011-06-14 23:48:48 +00007781 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7782 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7783 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7784 default:
Craig Toppere55c5562012-02-07 02:50:20 +00007785 llvm_unreachable("Invalid vector element type for padd optimization.");
Tanya Lattnere9e67052011-06-14 23:48:48 +00007786 }
7787
Craig Topper48d114b2014-04-26 18:35:24 +00007788 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), widenType, Ops);
Silviu Barangaa3106e62014-04-03 10:44:27 +00007789 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
7790 return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
Tanya Lattnere9e67052011-06-14 23:48:48 +00007791}
7792
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +00007793static SDValue findMUL_LOHI(SDValue V) {
7794 if (V->getOpcode() == ISD::UMUL_LOHI ||
7795 V->getOpcode() == ISD::SMUL_LOHI)
7796 return V;
7797 return SDValue();
7798}
7799
7800static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7801 TargetLowering::DAGCombinerInfo &DCI,
7802 const ARMSubtarget *Subtarget) {
7803
7804 if (Subtarget->isThumb1Only()) return SDValue();
7805
7806 // Only perform the checks after legalize when the pattern is available.
7807 if (DCI.isBeforeLegalize()) return SDValue();
7808
7809 // Look for multiply add opportunities.
7810 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7811 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7812 // a glue link from the first add to the second add.
7813 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7814 // a S/UMLAL instruction.
7815 // loAdd UMUL_LOHI
7816 // \ / :lo \ :hi
7817 // \ / \ [no multiline comment]
7818 // ADDC | hiAdd
7819 // \ :glue / /
7820 // \ / /
7821 // ADDE
7822 //
7823 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
7824 SDValue AddcOp0 = AddcNode->getOperand(0);
7825 SDValue AddcOp1 = AddcNode->getOperand(1);
7826
7827 // Check if the two operands are from the same mul_lohi node.
7828 if (AddcOp0.getNode() == AddcOp1.getNode())
7829 return SDValue();
7830
7831 assert(AddcNode->getNumValues() == 2 &&
7832 AddcNode->getValueType(0) == MVT::i32 &&
Michael Gottesmanb2a70562013-06-18 20:49:40 +00007833 "Expect ADDC with two result values. First: i32");
7834
7835 // Check that we have a glued ADDC node.
7836 if (AddcNode->getValueType(1) != MVT::Glue)
7837 return SDValue();
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +00007838
7839 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
7840 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
7841 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
7842 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
7843 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
7844 return SDValue();
7845
7846 // Look for the glued ADDE.
7847 SDNode* AddeNode = AddcNode->getGluedUser();
Craig Topper062a2ba2014-04-25 05:30:21 +00007848 if (!AddeNode)
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +00007849 return SDValue();
7850
7851 // Make sure it is really an ADDE.
7852 if (AddeNode->getOpcode() != ISD::ADDE)
7853 return SDValue();
7854
7855 assert(AddeNode->getNumOperands() == 3 &&
7856 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
7857 "ADDE node has the wrong inputs");
7858
7859 // Check for the triangle shape.
7860 SDValue AddeOp0 = AddeNode->getOperand(0);
7861 SDValue AddeOp1 = AddeNode->getOperand(1);
7862
7863 // Make sure that the ADDE operands are not coming from the same node.
7864 if (AddeOp0.getNode() == AddeOp1.getNode())
7865 return SDValue();
7866
7867 // Find the MUL_LOHI node walking up ADDE's operands.
7868 bool IsLeftOperandMUL = false;
7869 SDValue MULOp = findMUL_LOHI(AddeOp0);
7870 if (MULOp == SDValue())
7871 MULOp = findMUL_LOHI(AddeOp1);
7872 else
7873 IsLeftOperandMUL = true;
7874 if (MULOp == SDValue())
7875 return SDValue();
7876
7877 // Figure out the right opcode.
7878 unsigned Opc = MULOp->getOpcode();
7879 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
7880
7881 // Figure out the high and low input values to the MLAL node.
7882 SDValue* HiMul = &MULOp;
Craig Topper062a2ba2014-04-25 05:30:21 +00007883 SDValue* HiAdd = nullptr;
7884 SDValue* LoMul = nullptr;
7885 SDValue* LowAdd = nullptr;
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +00007886
7887 if (IsLeftOperandMUL)
7888 HiAdd = &AddeOp1;
7889 else
7890 HiAdd = &AddeOp0;
7891
7892
7893 if (AddcOp0->getOpcode() == Opc) {
7894 LoMul = &AddcOp0;
7895 LowAdd = &AddcOp1;
7896 }
7897 if (AddcOp1->getOpcode() == Opc) {
7898 LoMul = &AddcOp1;
7899 LowAdd = &AddcOp0;
7900 }
7901
Craig Topper062a2ba2014-04-25 05:30:21 +00007902 if (!LoMul)
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +00007903 return SDValue();
7904
7905 if (LoMul->getNode() != HiMul->getNode())
7906 return SDValue();
7907
7908 // Create the merged node.
7909 SelectionDAG &DAG = DCI.DAG;
7910
7911 // Build operand list.
7912 SmallVector<SDValue, 8> Ops;
7913 Ops.push_back(LoMul->getOperand(0));
7914 Ops.push_back(LoMul->getOperand(1));
7915 Ops.push_back(*LowAdd);
7916 Ops.push_back(*HiAdd);
7917
Andrew Trickef9de2a2013-05-25 02:42:55 +00007918 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
Craig Topper48d114b2014-04-26 18:35:24 +00007919 DAG.getVTList(MVT::i32, MVT::i32), Ops);
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +00007920
7921 // Replace the ADDs' nodes uses by the MLA node's values.
7922 SDValue HiMLALResult(MLALNode.getNode(), 1);
7923 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
7924
7925 SDValue LoMLALResult(MLALNode.getNode(), 0);
7926 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
7927
7928 // Return original node to notify the driver to stop replacing.
7929 SDValue resNode(AddcNode, 0);
7930 return resNode;
7931}
7932
7933/// PerformADDCCombine - Target-specific dag combine transform from
7934/// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
7935static SDValue PerformADDCCombine(SDNode *N,
7936 TargetLowering::DAGCombinerInfo &DCI,
7937 const ARMSubtarget *Subtarget) {
7938
7939 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
7940
7941}
7942
Bob Wilson728eb292010-07-29 20:34:14 +00007943/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
7944/// operands N0 and N1. This is a helper for PerformADDCombine that is
7945/// called with the default operands, and if that fails, with commuted
7946/// operands.
7947static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
Tanya Lattnere9e67052011-06-14 23:48:48 +00007948 TargetLowering::DAGCombinerInfo &DCI,
7949 const ARMSubtarget *Subtarget){
7950
7951 // Attempt to create vpaddl for this add.
7952 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
7953 if (Result.getNode())
7954 return Result;
Eric Christopher1b8b94192011-06-29 21:10:36 +00007955
Chris Lattner4147f082009-03-12 06:52:53 +00007956 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007957 if (N0.getNode()->hasOneUse()) {
Chris Lattner4147f082009-03-12 06:52:53 +00007958 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
7959 if (Result.getNode()) return Result;
7960 }
Chris Lattner4147f082009-03-12 06:52:53 +00007961 return SDValue();
7962}
7963
Bob Wilson728eb292010-07-29 20:34:14 +00007964/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
7965///
7966static SDValue PerformADDCombine(SDNode *N,
Tanya Lattnere9e67052011-06-14 23:48:48 +00007967 TargetLowering::DAGCombinerInfo &DCI,
7968 const ARMSubtarget *Subtarget) {
Bob Wilson728eb292010-07-29 20:34:14 +00007969 SDValue N0 = N->getOperand(0);
7970 SDValue N1 = N->getOperand(1);
7971
7972 // First try with the default operand order.
Tanya Lattnere9e67052011-06-14 23:48:48 +00007973 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
Bob Wilson728eb292010-07-29 20:34:14 +00007974 if (Result.getNode())
7975 return Result;
7976
7977 // If that didn't work, try again with the operands commuted.
Tanya Lattnere9e67052011-06-14 23:48:48 +00007978 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
Bob Wilson728eb292010-07-29 20:34:14 +00007979}
7980
Chris Lattner4147f082009-03-12 06:52:53 +00007981/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
Bob Wilson728eb292010-07-29 20:34:14 +00007982///
Chris Lattner4147f082009-03-12 06:52:53 +00007983static SDValue PerformSUBCombine(SDNode *N,
7984 TargetLowering::DAGCombinerInfo &DCI) {
Bob Wilson728eb292010-07-29 20:34:14 +00007985 SDValue N0 = N->getOperand(0);
7986 SDValue N1 = N->getOperand(1);
Bob Wilson7117a912009-03-20 22:42:55 +00007987
Chris Lattner4147f082009-03-12 06:52:53 +00007988 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
Jakob Stoklund Olesendded0612012-08-18 21:25:22 +00007989 if (N1.getNode()->hasOneUse()) {
Chris Lattner4147f082009-03-12 06:52:53 +00007990 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
7991 if (Result.getNode()) return Result;
7992 }
Bob Wilson7117a912009-03-20 22:42:55 +00007993
Chris Lattner4147f082009-03-12 06:52:53 +00007994 return SDValue();
7995}
7996
Evan Cheng38bf5ad2011-03-31 19:38:48 +00007997/// PerformVMULCombine
7998/// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
7999/// special multiplier accumulator forwarding.
8000/// vmul d3, d0, d2
8001/// vmla d3, d1, d2
8002/// is faster than
8003/// vadd d3, d0, d1
8004/// vmul d3, d3, d2
Weiming Zhao2052f482013-09-25 23:12:06 +00008005// However, for (A + B) * (A + B),
8006// vadd d2, d0, d1
8007// vmul d3, d0, d2
8008// vmla d3, d1, d2
8009// is slower than
8010// vadd d2, d0, d1
8011// vmul d3, d2, d2
Evan Cheng38bf5ad2011-03-31 19:38:48 +00008012static SDValue PerformVMULCombine(SDNode *N,
8013 TargetLowering::DAGCombinerInfo &DCI,
8014 const ARMSubtarget *Subtarget) {
8015 if (!Subtarget->hasVMLxForwarding())
8016 return SDValue();
8017
8018 SelectionDAG &DAG = DCI.DAG;
8019 SDValue N0 = N->getOperand(0);
8020 SDValue N1 = N->getOperand(1);
8021 unsigned Opcode = N0.getOpcode();
8022 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8023 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
Chad Rosier27301622011-06-16 01:21:54 +00008024 Opcode = N1.getOpcode();
Evan Cheng38bf5ad2011-03-31 19:38:48 +00008025 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8026 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8027 return SDValue();
8028 std::swap(N0, N1);
8029 }
8030
Weiming Zhao2052f482013-09-25 23:12:06 +00008031 if (N0 == N1)
8032 return SDValue();
8033
Evan Cheng38bf5ad2011-03-31 19:38:48 +00008034 EVT VT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00008035 SDLoc DL(N);
Evan Cheng38bf5ad2011-03-31 19:38:48 +00008036 SDValue N00 = N0->getOperand(0);
8037 SDValue N01 = N0->getOperand(1);
8038 return DAG.getNode(Opcode, DL, VT,
8039 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8040 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8041}
8042
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +00008043static SDValue PerformMULCombine(SDNode *N,
8044 TargetLowering::DAGCombinerInfo &DCI,
8045 const ARMSubtarget *Subtarget) {
8046 SelectionDAG &DAG = DCI.DAG;
8047
8048 if (Subtarget->isThumb1Only())
8049 return SDValue();
8050
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +00008051 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8052 return SDValue();
8053
8054 EVT VT = N->getValueType(0);
Evan Cheng38bf5ad2011-03-31 19:38:48 +00008055 if (VT.is64BitVector() || VT.is128BitVector())
8056 return PerformVMULCombine(N, DCI, Subtarget);
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +00008057 if (VT != MVT::i32)
8058 return SDValue();
8059
8060 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8061 if (!C)
8062 return SDValue();
8063
Anton Korobeynikov3edd854d2012-03-19 19:19:50 +00008064 int64_t MulAmt = C->getSExtValue();
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +00008065 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
Anton Korobeynikov3edd854d2012-03-19 19:19:50 +00008066
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +00008067 ShiftAmt = ShiftAmt & (32 - 1);
8068 SDValue V = N->getOperand(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00008069 SDLoc DL(N);
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +00008070
Anton Korobeynikov4c719c42010-05-16 08:54:20 +00008071 SDValue Res;
8072 MulAmt >>= ShiftAmt;
Anton Korobeynikov3edd854d2012-03-19 19:19:50 +00008073
8074 if (MulAmt >= 0) {
8075 if (isPowerOf2_32(MulAmt - 1)) {
8076 // (mul x, 2^N + 1) => (add (shl x, N), x)
8077 Res = DAG.getNode(ISD::ADD, DL, VT,
8078 V,
8079 DAG.getNode(ISD::SHL, DL, VT,
8080 V,
8081 DAG.getConstant(Log2_32(MulAmt - 1),
8082 MVT::i32)));
8083 } else if (isPowerOf2_32(MulAmt + 1)) {
8084 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8085 Res = DAG.getNode(ISD::SUB, DL, VT,
8086 DAG.getNode(ISD::SHL, DL, VT,
8087 V,
8088 DAG.getConstant(Log2_32(MulAmt + 1),
8089 MVT::i32)),
8090 V);
8091 } else
8092 return SDValue();
8093 } else {
8094 uint64_t MulAmtAbs = -MulAmt;
8095 if (isPowerOf2_32(MulAmtAbs + 1)) {
8096 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8097 Res = DAG.getNode(ISD::SUB, DL, VT,
8098 V,
8099 DAG.getNode(ISD::SHL, DL, VT,
8100 V,
8101 DAG.getConstant(Log2_32(MulAmtAbs + 1),
8102 MVT::i32)));
8103 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8104 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8105 Res = DAG.getNode(ISD::ADD, DL, VT,
8106 V,
8107 DAG.getNode(ISD::SHL, DL, VT,
8108 V,
8109 DAG.getConstant(Log2_32(MulAmtAbs-1),
8110 MVT::i32)));
8111 Res = DAG.getNode(ISD::SUB, DL, VT,
8112 DAG.getConstant(0, MVT::i32),Res);
8113
8114 } else
8115 return SDValue();
8116 }
Anton Korobeynikov4c719c42010-05-16 08:54:20 +00008117
8118 if (ShiftAmt != 0)
Anton Korobeynikov3edd854d2012-03-19 19:19:50 +00008119 Res = DAG.getNode(ISD::SHL, DL, VT,
8120 Res, DAG.getConstant(ShiftAmt, MVT::i32));
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +00008121
8122 // Do not add new nodes to DAG combiner worklist.
Anton Korobeynikov4c719c42010-05-16 08:54:20 +00008123 DCI.CombineTo(N, Res, false);
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +00008124 return SDValue();
8125}
8126
Owen Anderson30c48922010-11-05 19:27:46 +00008127static SDValue PerformANDCombine(SDNode *N,
Evan Chenge87681c2012-02-23 01:19:06 +00008128 TargetLowering::DAGCombinerInfo &DCI,
8129 const ARMSubtarget *Subtarget) {
Owen Anderson77aa2662011-04-05 21:48:57 +00008130
Owen Anderson30c48922010-11-05 19:27:46 +00008131 // Attempt to use immediate-form VBIC
8132 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
Andrew Trickef9de2a2013-05-25 02:42:55 +00008133 SDLoc dl(N);
Owen Anderson30c48922010-11-05 19:27:46 +00008134 EVT VT = N->getValueType(0);
8135 SelectionDAG &DAG = DCI.DAG;
Wesley Peck527da1b2010-11-23 03:31:01 +00008136
Tanya Lattner266792a2011-04-07 15:24:20 +00008137 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8138 return SDValue();
Andrew Trick0ed57782011-04-23 03:55:32 +00008139
Owen Anderson30c48922010-11-05 19:27:46 +00008140 APInt SplatBits, SplatUndef;
8141 unsigned SplatBitSize;
8142 bool HasAnyUndefs;
8143 if (BVN &&
8144 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8145 if (SplatBitSize <= 64) {
8146 EVT VbicVT;
8147 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8148 SplatUndef.getZExtValue(), SplatBitSize,
Wesley Peck527da1b2010-11-23 03:31:01 +00008149 DAG, VbicVT, VT.is128BitVector(),
Owen Andersona4076922010-11-05 21:57:54 +00008150 OtherModImm);
Owen Anderson30c48922010-11-05 19:27:46 +00008151 if (Val.getNode()) {
8152 SDValue Input =
Wesley Peck527da1b2010-11-23 03:31:01 +00008153 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
Owen Anderson30c48922010-11-05 19:27:46 +00008154 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
Wesley Peck527da1b2010-11-23 03:31:01 +00008155 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
Owen Anderson30c48922010-11-05 19:27:46 +00008156 }
8157 }
8158 }
Wesley Peck527da1b2010-11-23 03:31:01 +00008159
Evan Chenge87681c2012-02-23 01:19:06 +00008160 if (!Subtarget->isThumb1Only()) {
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00008161 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8162 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8163 if (Result.getNode())
8164 return Result;
Evan Chenge87681c2012-02-23 01:19:06 +00008165 }
8166
Owen Anderson30c48922010-11-05 19:27:46 +00008167 return SDValue();
8168}
8169
Jim Grosbach11013ed2010-07-16 23:05:05 +00008170/// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8171static SDValue PerformORCombine(SDNode *N,
8172 TargetLowering::DAGCombinerInfo &DCI,
8173 const ARMSubtarget *Subtarget) {
Owen Andersonbc9b31c2010-11-03 23:15:26 +00008174 // Attempt to use immediate-form VORR
8175 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
Andrew Trickef9de2a2013-05-25 02:42:55 +00008176 SDLoc dl(N);
Owen Andersonbc9b31c2010-11-03 23:15:26 +00008177 EVT VT = N->getValueType(0);
8178 SelectionDAG &DAG = DCI.DAG;
Wesley Peck527da1b2010-11-23 03:31:01 +00008179
Tanya Lattner266792a2011-04-07 15:24:20 +00008180 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8181 return SDValue();
Andrew Trick0ed57782011-04-23 03:55:32 +00008182
Owen Andersonbc9b31c2010-11-03 23:15:26 +00008183 APInt SplatBits, SplatUndef;
8184 unsigned SplatBitSize;
8185 bool HasAnyUndefs;
8186 if (BVN && Subtarget->hasNEON() &&
8187 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8188 if (SplatBitSize <= 64) {
8189 EVT VorrVT;
8190 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8191 SplatUndef.getZExtValue(), SplatBitSize,
Owen Andersona4076922010-11-05 21:57:54 +00008192 DAG, VorrVT, VT.is128BitVector(),
8193 OtherModImm);
Owen Andersonbc9b31c2010-11-03 23:15:26 +00008194 if (Val.getNode()) {
8195 SDValue Input =
Wesley Peck527da1b2010-11-23 03:31:01 +00008196 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
Owen Andersonbc9b31c2010-11-03 23:15:26 +00008197 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
Wesley Peck527da1b2010-11-23 03:31:01 +00008198 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
Owen Andersonbc9b31c2010-11-03 23:15:26 +00008199 }
8200 }
8201 }
8202
Evan Chenge87681c2012-02-23 01:19:06 +00008203 if (!Subtarget->isThumb1Only()) {
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00008204 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8205 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8206 if (Result.getNode())
8207 return Result;
Evan Chenge87681c2012-02-23 01:19:06 +00008208 }
8209
Nadav Rotem3a94c542012-08-13 18:52:44 +00008210 // The code below optimizes (or (and X, Y), Z).
8211 // The AND operand needs to have a single user to make these optimizations
8212 // profitable.
Cameron Zwarich53dd03d2011-03-30 23:01:21 +00008213 SDValue N0 = N->getOperand(0);
Nadav Rotem3a94c542012-08-13 18:52:44 +00008214 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
Cameron Zwarich53dd03d2011-03-30 23:01:21 +00008215 return SDValue();
8216 SDValue N1 = N->getOperand(1);
8217
8218 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8219 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8220 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8221 APInt SplatUndef;
8222 unsigned SplatBitSize;
8223 bool HasAnyUndefs;
8224
Saleem Abdulrasool0c2ee5a2013-07-30 04:43:08 +00008225 APInt SplatBits0, SplatBits1;
Cameron Zwarich53dd03d2011-03-30 23:01:21 +00008226 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
Saleem Abdulrasool0c2ee5a2013-07-30 04:43:08 +00008227 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8228 // Ensure that the second operand of both ands are constants
Cameron Zwarich53dd03d2011-03-30 23:01:21 +00008229 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
Saleem Abdulrasool0c2ee5a2013-07-30 04:43:08 +00008230 HasAnyUndefs) && !HasAnyUndefs) {
8231 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8232 HasAnyUndefs) && !HasAnyUndefs) {
8233 // Ensure that the bit width of the constants are the same and that
8234 // the splat arguments are logical inverses as per the pattern we
8235 // are trying to simplify.
8236 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8237 SplatBits0 == ~SplatBits1) {
8238 // Canonicalize the vector type to make instruction selection
8239 // simpler.
8240 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8241 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8242 N0->getOperand(1),
8243 N0->getOperand(0),
8244 N1->getOperand(0));
8245 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8246 }
8247 }
Cameron Zwarich53dd03d2011-03-30 23:01:21 +00008248 }
8249 }
8250
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008251 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8252 // reasonable.
8253
Jim Grosbach11013ed2010-07-16 23:05:05 +00008254 // BFI is only available on V6T2+
8255 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8256 return SDValue();
8257
Andrew Trickef9de2a2013-05-25 02:42:55 +00008258 SDLoc DL(N);
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008259 // 1) or (and A, mask), val => ARMbfi A, val, mask
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +00008260 // iff (val & mask) == val
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008261 //
8262 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +00008263 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
Eric Christopherd5530962011-03-26 01:21:03 +00008264 // && mask == ~mask2
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +00008265 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
Eric Christopherd5530962011-03-26 01:21:03 +00008266 // && ~mask == mask2
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008267 // (i.e., copy a bitfield value into another bitfield of the same width)
Jim Grosbach11013ed2010-07-16 23:05:05 +00008268
Jim Grosbach11013ed2010-07-16 23:05:05 +00008269 if (VT != MVT::i32)
8270 return SDValue();
8271
Evan Cheng2e51bb42010-12-13 20:32:54 +00008272 SDValue N00 = N0.getOperand(0);
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008273
Jim Grosbach11013ed2010-07-16 23:05:05 +00008274 // The value and the mask need to be constants so we can verify this is
8275 // actually a bitfield set. If the mask is 0xffff, we can do better
8276 // via a movt instruction, so don't use BFI in that case.
Evan Cheng2e51bb42010-12-13 20:32:54 +00008277 SDValue MaskOp = N0.getOperand(1);
8278 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8279 if (!MaskC)
Jim Grosbach11013ed2010-07-16 23:05:05 +00008280 return SDValue();
Evan Cheng2e51bb42010-12-13 20:32:54 +00008281 unsigned Mask = MaskC->getZExtValue();
Jim Grosbach11013ed2010-07-16 23:05:05 +00008282 if (Mask == 0xffff)
8283 return SDValue();
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008284 SDValue Res;
8285 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
Evan Cheng2e51bb42010-12-13 20:32:54 +00008286 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8287 if (N1C) {
8288 unsigned Val = N1C->getZExtValue();
Evan Cheng34345752010-12-11 04:11:38 +00008289 if ((Val & ~Mask) != Val)
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008290 return SDValue();
Jim Grosbach11013ed2010-07-16 23:05:05 +00008291
Evan Cheng34345752010-12-11 04:11:38 +00008292 if (ARM::isBitFieldInvertedMask(Mask)) {
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +00008293 Val >>= countTrailingZeros(~Mask);
Jim Grosbach11013ed2010-07-16 23:05:05 +00008294
Evan Cheng2e51bb42010-12-13 20:32:54 +00008295 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
Evan Cheng34345752010-12-11 04:11:38 +00008296 DAG.getConstant(Val, MVT::i32),
8297 DAG.getConstant(Mask, MVT::i32));
8298
8299 // Do not add new nodes to DAG combiner worklist.
8300 DCI.CombineTo(N, Res, false);
Evan Cheng2e51bb42010-12-13 20:32:54 +00008301 return SDValue();
Evan Cheng34345752010-12-11 04:11:38 +00008302 }
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008303 } else if (N1.getOpcode() == ISD::AND) {
8304 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
Evan Cheng2e51bb42010-12-13 20:32:54 +00008305 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8306 if (!N11C)
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008307 return SDValue();
Evan Cheng2e51bb42010-12-13 20:32:54 +00008308 unsigned Mask2 = N11C->getZExtValue();
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008309
Eric Christopherd5530962011-03-26 01:21:03 +00008310 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8311 // as is to match.
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008312 if (ARM::isBitFieldInvertedMask(Mask) &&
Eric Christopherd5530962011-03-26 01:21:03 +00008313 (Mask == ~Mask2)) {
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008314 // The pack halfword instruction works better for masks that fit it,
8315 // so use that when it's available.
8316 if (Subtarget->hasT2ExtractPack() &&
8317 (Mask == 0xffff || Mask == 0xffff0000))
8318 return SDValue();
8319 // 2a
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +00008320 unsigned amt = countTrailingZeros(Mask2);
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008321 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
Eric Christopherd5530962011-03-26 01:21:03 +00008322 DAG.getConstant(amt, MVT::i32));
Evan Cheng2e51bb42010-12-13 20:32:54 +00008323 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008324 DAG.getConstant(Mask, MVT::i32));
8325 // Do not add new nodes to DAG combiner worklist.
8326 DCI.CombineTo(N, Res, false);
Evan Cheng2e51bb42010-12-13 20:32:54 +00008327 return SDValue();
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008328 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
Eric Christopherd5530962011-03-26 01:21:03 +00008329 (~Mask == Mask2)) {
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008330 // The pack halfword instruction works better for masks that fit it,
8331 // so use that when it's available.
8332 if (Subtarget->hasT2ExtractPack() &&
8333 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8334 return SDValue();
8335 // 2b
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +00008336 unsigned lsb = countTrailingZeros(Mask);
Evan Cheng2e51bb42010-12-13 20:32:54 +00008337 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008338 DAG.getConstant(lsb, MVT::i32));
8339 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
Eric Christopherd5530962011-03-26 01:21:03 +00008340 DAG.getConstant(Mask2, MVT::i32));
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008341 // Do not add new nodes to DAG combiner worklist.
8342 DCI.CombineTo(N, Res, false);
Evan Cheng2e51bb42010-12-13 20:32:54 +00008343 return SDValue();
Jim Grosbachb97e2bb2010-07-17 03:30:54 +00008344 }
8345 }
Wesley Peck527da1b2010-11-23 03:31:01 +00008346
Evan Cheng2e51bb42010-12-13 20:32:54 +00008347 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8348 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8349 ARM::isBitFieldInvertedMask(~Mask)) {
8350 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8351 // where lsb(mask) == #shamt and masked bits of B are known zero.
8352 SDValue ShAmt = N00.getOperand(1);
8353 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +00008354 unsigned LSB = countTrailingZeros(Mask);
Evan Cheng2e51bb42010-12-13 20:32:54 +00008355 if (ShAmtC != LSB)
8356 return SDValue();
8357
8358 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8359 DAG.getConstant(~Mask, MVT::i32));
8360
8361 // Do not add new nodes to DAG combiner worklist.
8362 DCI.CombineTo(N, Res, false);
8363 }
8364
Jim Grosbach11013ed2010-07-16 23:05:05 +00008365 return SDValue();
8366}
8367
Evan Chenge87681c2012-02-23 01:19:06 +00008368static SDValue PerformXORCombine(SDNode *N,
8369 TargetLowering::DAGCombinerInfo &DCI,
8370 const ARMSubtarget *Subtarget) {
8371 EVT VT = N->getValueType(0);
8372 SelectionDAG &DAG = DCI.DAG;
8373
8374 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8375 return SDValue();
8376
8377 if (!Subtarget->isThumb1Only()) {
Jakob Stoklund Olesenaab43db2012-08-18 21:25:16 +00008378 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8379 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8380 if (Result.getNode())
8381 return Result;
Evan Chenge87681c2012-02-23 01:19:06 +00008382 }
8383
8384 return SDValue();
8385}
8386
Evan Cheng6d02d902011-06-15 01:12:31 +00008387/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8388/// the bits being cleared by the AND are not demanded by the BFI.
Evan Chengc1778132010-12-14 03:22:07 +00008389static SDValue PerformBFICombine(SDNode *N,
8390 TargetLowering::DAGCombinerInfo &DCI) {
8391 SDValue N1 = N->getOperand(1);
8392 if (N1.getOpcode() == ISD::AND) {
8393 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8394 if (!N11C)
8395 return SDValue();
Evan Cheng6d02d902011-06-15 01:12:31 +00008396 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +00008397 unsigned LSB = countTrailingZeros(~InvMask);
8398 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
Evan Cheng6d02d902011-06-15 01:12:31 +00008399 unsigned Mask = (1 << Width)-1;
Evan Chengc1778132010-12-14 03:22:07 +00008400 unsigned Mask2 = N11C->getZExtValue();
Evan Cheng6d02d902011-06-15 01:12:31 +00008401 if ((Mask & (~Mask2)) == 0)
Andrew Trickef9de2a2013-05-25 02:42:55 +00008402 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
Evan Chengc1778132010-12-14 03:22:07 +00008403 N->getOperand(0), N1.getOperand(0),
8404 N->getOperand(2));
8405 }
8406 return SDValue();
8407}
8408
Bob Wilson22806742010-09-22 22:09:21 +00008409/// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8410/// ARMISD::VMOVRRD.
8411static SDValue PerformVMOVRRDCombine(SDNode *N,
8412 TargetLowering::DAGCombinerInfo &DCI) {
8413 // vmovrrd(vmovdrr x, y) -> x,y
8414 SDValue InDouble = N->getOperand(0);
8415 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
8416 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
Cameron Zwarich6fe5c292011-04-02 02:40:43 +00008417
8418 // vmovrrd(load f64) -> (load i32), (load i32)
8419 SDNode *InNode = InDouble.getNode();
8420 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8421 InNode->getValueType(0) == MVT::f64 &&
8422 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8423 !cast<LoadSDNode>(InNode)->isVolatile()) {
8424 // TODO: Should this be done for non-FrameIndex operands?
8425 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8426
8427 SelectionDAG &DAG = DCI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +00008428 SDLoc DL(LD);
Cameron Zwarich6fe5c292011-04-02 02:40:43 +00008429 SDValue BasePtr = LD->getBasePtr();
8430 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8431 LD->getPointerInfo(), LD->isVolatile(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00008432 LD->isNonTemporal(), LD->isInvariant(),
8433 LD->getAlignment());
Cameron Zwarich6fe5c292011-04-02 02:40:43 +00008434
8435 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8436 DAG.getConstant(4, MVT::i32));
8437 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8438 LD->getPointerInfo(), LD->isVolatile(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00008439 LD->isNonTemporal(), LD->isInvariant(),
Cameron Zwarich6fe5c292011-04-02 02:40:43 +00008440 std::min(4U, LD->getAlignment() / 2));
8441
8442 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
Christian Pirker762b2c62014-06-01 09:30:52 +00008443 if (DCI.DAG.getTargetLoweringInfo().isBigEndian())
8444 std::swap (NewLD1, NewLD2);
Cameron Zwarich6fe5c292011-04-02 02:40:43 +00008445 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8446 DCI.RemoveFromWorklist(LD);
8447 DAG.DeleteNode(LD);
8448 return Result;
8449 }
8450
Bob Wilson22806742010-09-22 22:09:21 +00008451 return SDValue();
8452}
8453
8454/// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8455/// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8456static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8457 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8458 SDValue Op0 = N->getOperand(0);
8459 SDValue Op1 = N->getOperand(1);
Wesley Peck527da1b2010-11-23 03:31:01 +00008460 if (Op0.getOpcode() == ISD::BITCAST)
Bob Wilson22806742010-09-22 22:09:21 +00008461 Op0 = Op0.getOperand(0);
Wesley Peck527da1b2010-11-23 03:31:01 +00008462 if (Op1.getOpcode() == ISD::BITCAST)
Bob Wilson22806742010-09-22 22:09:21 +00008463 Op1 = Op1.getOperand(0);
8464 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8465 Op0.getNode() == Op1.getNode() &&
8466 Op0.getResNo() == 0 && Op1.getResNo() == 1)
Andrew Trickef9de2a2013-05-25 02:42:55 +00008467 return DAG.getNode(ISD::BITCAST, SDLoc(N),
Bob Wilson22806742010-09-22 22:09:21 +00008468 N->getValueType(0), Op0.getOperand(0));
8469 return SDValue();
8470}
8471
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008472/// PerformSTORECombine - Target-specific dag combine xforms for
8473/// ISD::STORE.
8474static SDValue PerformSTORECombine(SDNode *N,
8475 TargetLowering::DAGCombinerInfo &DCI) {
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008476 StoreSDNode *St = cast<StoreSDNode>(N);
Chad Rosiere0e38f62012-04-09 20:32:02 +00008477 if (St->isVolatile())
8478 return SDValue();
8479
Andrew Trickbc325162012-07-18 18:34:24 +00008480 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
Chad Rosiere0e38f62012-04-09 20:32:02 +00008481 // pack all of the elements in one place. Next, store to memory in fewer
8482 // chunks.
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008483 SDValue StVal = St->getValue();
Chad Rosiere0e38f62012-04-09 20:32:02 +00008484 EVT VT = StVal.getValueType();
8485 if (St->isTruncatingStore() && VT.isVector()) {
8486 SelectionDAG &DAG = DCI.DAG;
8487 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8488 EVT StVT = St->getMemoryVT();
8489 unsigned NumElems = VT.getVectorNumElements();
8490 assert(StVT != VT && "Cannot truncate to the same type");
8491 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
8492 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
8493
8494 // From, To sizes and ElemCount must be pow of two
8495 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
8496
8497 // We are going to use the original vector elt for storing.
8498 // Accumulated smaller vector elements must be a multiple of the store size.
8499 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
8500
8501 unsigned SizeRatio = FromEltSz / ToEltSz;
8502 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
8503
8504 // Create a type on which we perform the shuffle.
8505 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
8506 NumElems*SizeRatio);
8507 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
8508
Andrew Trickef9de2a2013-05-25 02:42:55 +00008509 SDLoc DL(St);
Chad Rosiere0e38f62012-04-09 20:32:02 +00008510 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
8511 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
Christian Pirker2cc1cf02014-06-16 09:17:30 +00008512 for (unsigned i = 0; i < NumElems; ++i)
8513 ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
Chad Rosiere0e38f62012-04-09 20:32:02 +00008514
8515 // Can't shuffle using an illegal type.
8516 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8517
8518 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8519 DAG.getUNDEF(WideVec.getValueType()),
8520 ShuffleVec.data());
8521 // At this point all of the data is stored at the bottom of the
8522 // register. We now need to save it to mem.
8523
8524 // Find the largest store unit
8525 MVT StoreType = MVT::i8;
8526 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8527 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8528 MVT Tp = (MVT::SimpleValueType)tp;
8529 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8530 StoreType = Tp;
8531 }
8532 // Didn't find a legal store type.
8533 if (!TLI.isTypeLegal(StoreType))
8534 return SDValue();
8535
8536 // Bitcast the original vector into a vector of store-size units
8537 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8538 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8539 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8540 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8541 SmallVector<SDValue, 8> Chains;
8542 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8543 TLI.getPointerTy());
8544 SDValue BasePtr = St->getBasePtr();
8545
8546 // Perform one or more big stores into memory.
8547 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8548 for (unsigned I = 0; I < E; I++) {
8549 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
8550 StoreType, ShuffWide,
8551 DAG.getIntPtrConstant(I));
8552 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
8553 St->getPointerInfo(), St->isVolatile(),
8554 St->isNonTemporal(), St->getAlignment());
8555 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
8556 Increment);
8557 Chains.push_back(Ch);
8558 }
Craig Topper48d114b2014-04-26 18:35:24 +00008559 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
Chad Rosiere0e38f62012-04-09 20:32:02 +00008560 }
8561
8562 if (!ISD::isNormalStore(St))
Cameron Zwarichfbcd69b2011-04-12 02:24:17 +00008563 return SDValue();
8564
Chad Rosier99cbde92012-04-09 19:38:15 +00008565 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
8566 // ARM stores of arguments in the same cache line.
Cameron Zwarichfbcd69b2011-04-12 02:24:17 +00008567 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
Chad Rosier99cbde92012-04-09 19:38:15 +00008568 StVal.getNode()->hasOneUse()) {
Cameron Zwarichfbcd69b2011-04-12 02:24:17 +00008569 SelectionDAG &DAG = DCI.DAG;
Christian Pirkerb5728192014-05-08 14:06:24 +00008570 bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
Andrew Trickef9de2a2013-05-25 02:42:55 +00008571 SDLoc DL(St);
Cameron Zwarichfbcd69b2011-04-12 02:24:17 +00008572 SDValue BasePtr = St->getBasePtr();
8573 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
Christian Pirkerb5728192014-05-08 14:06:24 +00008574 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
8575 BasePtr, St->getPointerInfo(), St->isVolatile(),
Cameron Zwarichfbcd69b2011-04-12 02:24:17 +00008576 St->isNonTemporal(), St->getAlignment());
8577
8578 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8579 DAG.getConstant(4, MVT::i32));
Christian Pirkerb5728192014-05-08 14:06:24 +00008580 return DAG.getStore(NewST1.getValue(0), DL,
8581 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
Cameron Zwarichfbcd69b2011-04-12 02:24:17 +00008582 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
8583 St->isNonTemporal(),
8584 std::min(4U, St->getAlignment() / 2));
8585 }
8586
8587 if (StVal.getValueType() != MVT::i64 ||
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008588 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8589 return SDValue();
8590
Chad Rosier99cbde92012-04-09 19:38:15 +00008591 // Bitcast an i64 store extracted from a vector to f64.
8592 // Otherwise, the i64 value will be legalized to a pair of i32 values.
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008593 SelectionDAG &DAG = DCI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +00008594 SDLoc dl(StVal);
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008595 SDValue IntVec = StVal.getOperand(0);
8596 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8597 IntVec.getValueType().getVectorNumElements());
8598 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
8599 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8600 Vec, StVal.getOperand(1));
Andrew Trickef9de2a2013-05-25 02:42:55 +00008601 dl = SDLoc(N);
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008602 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
8603 // Make the DAGCombiner fold the bitcasts.
8604 DCI.AddToWorklist(Vec.getNode());
8605 DCI.AddToWorklist(ExtElt.getNode());
8606 DCI.AddToWorklist(V.getNode());
8607 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
8608 St->getPointerInfo(), St->isVolatile(),
8609 St->isNonTemporal(), St->getAlignment(),
Hal Finkelcc39b672014-07-24 12:16:19 +00008610 St->getAAInfo());
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008611}
8612
8613/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8614/// are normal, non-volatile loads. If so, it is profitable to bitcast an
8615/// i64 vector to have f64 elements, since the value can then be loaded
8616/// directly into a VFP register.
8617static bool hasNormalLoadOperand(SDNode *N) {
8618 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8619 for (unsigned i = 0; i < NumElts; ++i) {
8620 SDNode *Elt = N->getOperand(i).getNode();
8621 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8622 return true;
8623 }
8624 return false;
8625}
8626
Bob Wilsoncb6db982010-09-17 22:59:05 +00008627/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8628/// ISD::BUILD_VECTOR.
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008629static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8630 TargetLowering::DAGCombinerInfo &DCI){
Bob Wilsoncb6db982010-09-17 22:59:05 +00008631 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8632 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8633 // into a pair of GPRs, which is fine when the value is used as a scalar,
8634 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008635 SelectionDAG &DAG = DCI.DAG;
8636 if (N->getNumOperands() == 2) {
8637 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8638 if (RV.getNode())
8639 return RV;
8640 }
Bob Wilsoncb6db982010-09-17 22:59:05 +00008641
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008642 // Load i64 elements as f64 values so that type legalization does not split
8643 // them up into i32 values.
8644 EVT VT = N->getValueType(0);
8645 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8646 return SDValue();
Andrew Trickef9de2a2013-05-25 02:42:55 +00008647 SDLoc dl(N);
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008648 SmallVector<SDValue, 8> Ops;
8649 unsigned NumElts = VT.getVectorNumElements();
8650 for (unsigned i = 0; i < NumElts; ++i) {
8651 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8652 Ops.push_back(V);
8653 // Make the DAGCombiner fold the bitcast.
8654 DCI.AddToWorklist(V.getNode());
8655 }
8656 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
Craig Topper48d114b2014-04-26 18:35:24 +00008657 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008658 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8659}
8660
Quentin Colombet04b3a0f2013-07-03 21:42:57 +00008661/// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8662static SDValue
8663PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8664 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8665 // At that time, we may have inserted bitcasts from integer to float.
8666 // If these bitcasts have survived DAGCombine, change the lowering of this
8667 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8668 // force to use floating point types.
8669
8670 // Make sure we can change the type of the vector.
8671 // This is possible iff:
8672 // 1. The vector is only used in a bitcast to a integer type. I.e.,
8673 // 1.1. Vector is used only once.
8674 // 1.2. Use is a bit convert to an integer type.
8675 // 2. The size of its operands are 32-bits (64-bits are not legal).
8676 EVT VT = N->getValueType(0);
8677 EVT EltVT = VT.getVectorElementType();
8678
8679 // Check 1.1. and 2.
8680 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8681 return SDValue();
8682
8683 // By construction, the input type must be float.
8684 assert(EltVT == MVT::f32 && "Unexpected type!");
8685
8686 // Check 1.2.
8687 SDNode *Use = *N->use_begin();
8688 if (Use->getOpcode() != ISD::BITCAST ||
8689 Use->getValueType(0).isFloatingPoint())
8690 return SDValue();
8691
8692 // Check profitability.
8693 // Model is, if more than half of the relevant operands are bitcast from
8694 // i32, turn the build_vector into a sequence of insert_vector_elt.
8695 // Relevant operands are everything that is not statically
8696 // (i.e., at compile time) bitcasted.
8697 unsigned NumOfBitCastedElts = 0;
8698 unsigned NumElts = VT.getVectorNumElements();
8699 unsigned NumOfRelevantElts = NumElts;
8700 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
8701 SDValue Elt = N->getOperand(Idx);
8702 if (Elt->getOpcode() == ISD::BITCAST) {
8703 // Assume only bit cast to i32 will go away.
8704 if (Elt->getOperand(0).getValueType() == MVT::i32)
8705 ++NumOfBitCastedElts;
8706 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
8707 // Constants are statically casted, thus do not count them as
8708 // relevant operands.
8709 --NumOfRelevantElts;
8710 }
8711
8712 // Check if more than half of the elements require a non-free bitcast.
8713 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
8714 return SDValue();
8715
8716 SelectionDAG &DAG = DCI.DAG;
8717 // Create the new vector type.
8718 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8719 // Check if the type is legal.
8720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8721 if (!TLI.isTypeLegal(VecVT))
8722 return SDValue();
8723
8724 // Combine:
8725 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
8726 // => BITCAST INSERT_VECTOR_ELT
8727 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8728 // (BITCAST EN), N.
8729 SDValue Vec = DAG.getUNDEF(VecVT);
8730 SDLoc dl(N);
8731 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
8732 SDValue V = N->getOperand(Idx);
8733 if (V.getOpcode() == ISD::UNDEF)
8734 continue;
8735 if (V.getOpcode() == ISD::BITCAST &&
8736 V->getOperand(0).getValueType() == MVT::i32)
8737 // Fold obvious case.
8738 V = V.getOperand(0);
8739 else {
Jim Grosbach1a597112014-04-03 23:43:18 +00008740 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
Quentin Colombet04b3a0f2013-07-03 21:42:57 +00008741 // Make the DAGCombiner fold the bitcasts.
8742 DCI.AddToWorklist(V.getNode());
8743 }
8744 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
8745 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8746 }
8747 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
8748 // Make the DAGCombiner fold the bitcasts.
8749 DCI.AddToWorklist(Vec.getNode());
8750 return Vec;
8751}
8752
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008753/// PerformInsertEltCombine - Target-specific dag combine xforms for
8754/// ISD::INSERT_VECTOR_ELT.
8755static SDValue PerformInsertEltCombine(SDNode *N,
8756 TargetLowering::DAGCombinerInfo &DCI) {
8757 // Bitcast an i64 load inserted into a vector to f64.
8758 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8759 EVT VT = N->getValueType(0);
8760 SDNode *Elt = N->getOperand(1).getNode();
8761 if (VT.getVectorElementType() != MVT::i64 ||
8762 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8763 return SDValue();
8764
8765 SelectionDAG &DAG = DCI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +00008766 SDLoc dl(N);
Bob Wilson1a20c2a2010-12-21 06:43:19 +00008767 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8768 VT.getVectorNumElements());
8769 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8770 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8771 // Make the DAGCombiner fold the bitcasts.
8772 DCI.AddToWorklist(Vec.getNode());
8773 DCI.AddToWorklist(V.getNode());
8774 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8775 Vec, V, N->getOperand(2));
8776 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
Bob Wilsoncb6db982010-09-17 22:59:05 +00008777}
8778
Bob Wilsonc7334a12010-10-27 20:38:28 +00008779/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8780/// ISD::VECTOR_SHUFFLE.
8781static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8782 // The LLVM shufflevector instruction does not require the shuffle mask
8783 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8784 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8785 // operands do not match the mask length, they are extended by concatenating
8786 // them with undef vectors. That is probably the right thing for other
8787 // targets, but for NEON it is better to concatenate two double-register
8788 // size vector operands into a single quad-register size vector. Do that
8789 // transformation here:
8790 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8791 // shuffle(concat(v1, v2), undef)
8792 SDValue Op0 = N->getOperand(0);
8793 SDValue Op1 = N->getOperand(1);
8794 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8795 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8796 Op0.getNumOperands() != 2 ||
8797 Op1.getNumOperands() != 2)
8798 return SDValue();
8799 SDValue Concat0Op1 = Op0.getOperand(1);
8800 SDValue Concat1Op1 = Op1.getOperand(1);
8801 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8802 Concat1Op1.getOpcode() != ISD::UNDEF)
8803 return SDValue();
8804 // Skip the transformation if any of the types are illegal.
8805 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8806 EVT VT = N->getValueType(0);
8807 if (!TLI.isTypeLegal(VT) ||
8808 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8809 !TLI.isTypeLegal(Concat1Op1.getValueType()))
8810 return SDValue();
8811
Andrew Trickef9de2a2013-05-25 02:42:55 +00008812 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
Bob Wilsonc7334a12010-10-27 20:38:28 +00008813 Op0.getOperand(0), Op1.getOperand(0));
8814 // Translate the shuffle mask.
8815 SmallVector<int, 16> NewMask;
8816 unsigned NumElts = VT.getVectorNumElements();
8817 unsigned HalfElts = NumElts/2;
8818 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8819 for (unsigned n = 0; n < NumElts; ++n) {
8820 int MaskElt = SVN->getMaskElt(n);
8821 int NewElt = -1;
Bob Wilson6c550072010-10-27 23:49:00 +00008822 if (MaskElt < (int)HalfElts)
Bob Wilsonc7334a12010-10-27 20:38:28 +00008823 NewElt = MaskElt;
Bob Wilson6c550072010-10-27 23:49:00 +00008824 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
Bob Wilsonc7334a12010-10-27 20:38:28 +00008825 NewElt = HalfElts + MaskElt - NumElts;
8826 NewMask.push_back(NewElt);
8827 }
Andrew Trickef9de2a2013-05-25 02:42:55 +00008828 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
Bob Wilsonc7334a12010-10-27 20:38:28 +00008829 DAG.getUNDEF(VT), NewMask.data());
8830}
8831
Bob Wilson06fce872011-02-07 17:43:21 +00008832/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
8833/// NEON load/store intrinsics to merge base address updates.
8834static SDValue CombineBaseUpdate(SDNode *N,
8835 TargetLowering::DAGCombinerInfo &DCI) {
8836 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8837 return SDValue();
8838
8839 SelectionDAG &DAG = DCI.DAG;
8840 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8841 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8842 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
8843 SDValue Addr = N->getOperand(AddrOpIdx);
8844
8845 // Search for a use of the address operand that is an increment.
8846 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8847 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8848 SDNode *User = *UI;
8849 if (User->getOpcode() != ISD::ADD ||
8850 UI.getUse().getResNo() != Addr.getResNo())
8851 continue;
8852
8853 // Check that the add is independent of the load/store. Otherwise, folding
8854 // it would create a cycle.
8855 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8856 continue;
8857
8858 // Find the new opcode for the updating load/store.
8859 bool isLoad = true;
8860 bool isLaneOp = false;
8861 unsigned NewOpc = 0;
8862 unsigned NumVecs = 0;
8863 if (isIntrinsic) {
8864 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8865 switch (IntNo) {
Craig Toppere55c5562012-02-07 02:50:20 +00008866 default: llvm_unreachable("unexpected intrinsic for Neon base update");
Bob Wilson06fce872011-02-07 17:43:21 +00008867 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
8868 NumVecs = 1; break;
8869 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
8870 NumVecs = 2; break;
8871 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
8872 NumVecs = 3; break;
8873 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
8874 NumVecs = 4; break;
8875 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8876 NumVecs = 2; isLaneOp = true; break;
8877 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8878 NumVecs = 3; isLaneOp = true; break;
8879 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8880 NumVecs = 4; isLaneOp = true; break;
8881 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
8882 NumVecs = 1; isLoad = false; break;
8883 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
8884 NumVecs = 2; isLoad = false; break;
8885 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
8886 NumVecs = 3; isLoad = false; break;
8887 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
8888 NumVecs = 4; isLoad = false; break;
8889 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8890 NumVecs = 2; isLoad = false; isLaneOp = true; break;
8891 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8892 NumVecs = 3; isLoad = false; isLaneOp = true; break;
8893 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8894 NumVecs = 4; isLoad = false; isLaneOp = true; break;
8895 }
8896 } else {
8897 isLaneOp = true;
8898 switch (N->getOpcode()) {
Craig Toppere55c5562012-02-07 02:50:20 +00008899 default: llvm_unreachable("unexpected opcode for Neon base update");
Bob Wilson06fce872011-02-07 17:43:21 +00008900 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8901 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8902 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8903 }
8904 }
8905
8906 // Find the size of memory referenced by the load/store.
8907 EVT VecTy;
8908 if (isLoad)
8909 VecTy = N->getValueType(0);
Owen Anderson77aa2662011-04-05 21:48:57 +00008910 else
Bob Wilson06fce872011-02-07 17:43:21 +00008911 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
8912 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8913 if (isLaneOp)
8914 NumBytes /= VecTy.getVectorNumElements();
8915
8916 // If the increment is a constant, it must match the memory ref size.
8917 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8918 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8919 uint64_t IncVal = CInc->getZExtValue();
8920 if (IncVal != NumBytes)
8921 continue;
8922 } else if (NumBytes >= 3 * 16) {
8923 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
8924 // separate instructions that make it harder to use a non-constant update.
8925 continue;
8926 }
8927
8928 // Create the new updating load/store node.
8929 EVT Tys[6];
8930 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
8931 unsigned n;
8932 for (n = 0; n < NumResultVecs; ++n)
8933 Tys[n] = VecTy;
8934 Tys[n++] = MVT::i32;
8935 Tys[n] = MVT::Other;
Craig Topperabb4ac72014-04-16 06:10:51 +00008936 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs+2));
Bob Wilson06fce872011-02-07 17:43:21 +00008937 SmallVector<SDValue, 8> Ops;
8938 Ops.push_back(N->getOperand(0)); // incoming chain
8939 Ops.push_back(N->getOperand(AddrOpIdx));
8940 Ops.push_back(Inc);
8941 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
8942 Ops.push_back(N->getOperand(i));
8943 }
8944 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
Andrew Trickef9de2a2013-05-25 02:42:55 +00008945 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
Craig Topper206fcd42014-04-26 19:29:41 +00008946 Ops, MemInt->getMemoryVT(),
Bob Wilson06fce872011-02-07 17:43:21 +00008947 MemInt->getMemOperand());
8948
8949 // Update the uses.
8950 std::vector<SDValue> NewResults;
8951 for (unsigned i = 0; i < NumResultVecs; ++i) {
8952 NewResults.push_back(SDValue(UpdN.getNode(), i));
8953 }
8954 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
8955 DCI.CombineTo(N, NewResults);
8956 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8957
8958 break;
Owen Anderson77aa2662011-04-05 21:48:57 +00008959 }
Bob Wilson06fce872011-02-07 17:43:21 +00008960 return SDValue();
8961}
8962
Bob Wilson2d790df2010-11-28 06:51:26 +00008963/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
8964/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
8965/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
8966/// return true.
8967static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8968 SelectionDAG &DAG = DCI.DAG;
8969 EVT VT = N->getValueType(0);
8970 // vldN-dup instructions only support 64-bit vectors for N > 1.
8971 if (!VT.is64BitVector())
8972 return false;
8973
8974 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
8975 SDNode *VLD = N->getOperand(0).getNode();
8976 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
8977 return false;
8978 unsigned NumVecs = 0;
8979 unsigned NewOpc = 0;
8980 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
8981 if (IntNo == Intrinsic::arm_neon_vld2lane) {
8982 NumVecs = 2;
8983 NewOpc = ARMISD::VLD2DUP;
8984 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
8985 NumVecs = 3;
8986 NewOpc = ARMISD::VLD3DUP;
8987 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
8988 NumVecs = 4;
8989 NewOpc = ARMISD::VLD4DUP;
8990 } else {
8991 return false;
8992 }
8993
8994 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
8995 // numbers match the load.
8996 unsigned VLDLaneNo =
8997 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
8998 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
8999 UI != UE; ++UI) {
9000 // Ignore uses of the chain result.
9001 if (UI.getUse().getResNo() == NumVecs)
9002 continue;
9003 SDNode *User = *UI;
9004 if (User->getOpcode() != ARMISD::VDUPLANE ||
9005 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9006 return false;
9007 }
9008
9009 // Create the vldN-dup node.
9010 EVT Tys[5];
9011 unsigned n;
9012 for (n = 0; n < NumVecs; ++n)
9013 Tys[n] = VT;
9014 Tys[n] = MVT::Other;
Craig Topperabb4ac72014-04-16 06:10:51 +00009015 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumVecs+1));
Bob Wilson2d790df2010-11-28 06:51:26 +00009016 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9017 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
Andrew Trickef9de2a2013-05-25 02:42:55 +00009018 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
Craig Topper206fcd42014-04-26 19:29:41 +00009019 Ops, VLDMemInt->getMemoryVT(),
Bob Wilson2d790df2010-11-28 06:51:26 +00009020 VLDMemInt->getMemOperand());
9021
9022 // Update the uses.
9023 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9024 UI != UE; ++UI) {
9025 unsigned ResNo = UI.getUse().getResNo();
9026 // Ignore uses of the chain result.
9027 if (ResNo == NumVecs)
9028 continue;
9029 SDNode *User = *UI;
9030 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9031 }
9032
9033 // Now the vldN-lane intrinsic is dead except for its chain result.
9034 // Update uses of the chain.
9035 std::vector<SDValue> VLDDupResults;
9036 for (unsigned n = 0; n < NumVecs; ++n)
9037 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9038 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9039 DCI.CombineTo(VLD, VLDDupResults);
9040
9041 return true;
9042}
9043
Bob Wilson103a0dc2010-07-14 01:22:12 +00009044/// PerformVDUPLANECombine - Target-specific dag combine xforms for
9045/// ARMISD::VDUPLANE.
Bob Wilson2d790df2010-11-28 06:51:26 +00009046static SDValue PerformVDUPLANECombine(SDNode *N,
9047 TargetLowering::DAGCombinerInfo &DCI) {
Bob Wilson103a0dc2010-07-14 01:22:12 +00009048 SDValue Op = N->getOperand(0);
Bob Wilson103a0dc2010-07-14 01:22:12 +00009049
Bob Wilson2d790df2010-11-28 06:51:26 +00009050 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9051 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9052 if (CombineVLDDUP(N, DCI))
9053 return SDValue(N, 0);
9054
9055 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9056 // redundant. Ignore bit_converts for now; element sizes are checked below.
Wesley Peck527da1b2010-11-23 03:31:01 +00009057 while (Op.getOpcode() == ISD::BITCAST)
Bob Wilson103a0dc2010-07-14 01:22:12 +00009058 Op = Op.getOperand(0);
Bob Wilsonbad47f62010-07-14 06:31:50 +00009059 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
Bob Wilson103a0dc2010-07-14 01:22:12 +00009060 return SDValue();
9061
9062 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9063 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9064 // The canonical VMOV for a zero vector uses a 32-bit element size.
9065 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9066 unsigned EltBits;
9067 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9068 EltSize = 8;
Bob Wilson2d790df2010-11-28 06:51:26 +00009069 EVT VT = N->getValueType(0);
Bob Wilson103a0dc2010-07-14 01:22:12 +00009070 if (EltSize > VT.getVectorElementType().getSizeInBits())
9071 return SDValue();
9072
Andrew Trickef9de2a2013-05-25 02:42:55 +00009073 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
Bob Wilson103a0dc2010-07-14 01:22:12 +00009074}
9075
Eric Christopher1b8b94192011-06-29 21:10:36 +00009076// isConstVecPow2 - Return true if each vector element is a power of 2, all
Chad Rosierfa8d8932011-06-24 19:23:04 +00009077// elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9078static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9079{
Chad Rosier6b610b32011-06-28 17:26:57 +00009080 integerPart cN;
9081 integerPart c0 = 0;
Chad Rosierfa8d8932011-06-24 19:23:04 +00009082 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9083 I != E; I++) {
9084 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9085 if (!C)
9086 return false;
9087
Eric Christopher1b8b94192011-06-29 21:10:36 +00009088 bool isExact;
Chad Rosierfa8d8932011-06-24 19:23:04 +00009089 APFloat APF = C->getValueAPF();
9090 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9091 != APFloat::opOK || !isExact)
9092 return false;
9093
9094 c0 = (I == 0) ? cN : c0;
9095 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9096 return false;
9097 }
9098 C = c0;
9099 return true;
9100}
9101
9102/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9103/// can replace combinations of VMUL and VCVT (floating-point to integer)
9104/// when the VMUL has a constant operand that is a power of 2.
9105///
9106/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9107/// vmul.f32 d16, d17, d16
9108/// vcvt.s32.f32 d16, d16
9109/// becomes:
9110/// vcvt.s32.f32 d16, d16, #3
9111static SDValue PerformVCVTCombine(SDNode *N,
9112 TargetLowering::DAGCombinerInfo &DCI,
9113 const ARMSubtarget *Subtarget) {
9114 SelectionDAG &DAG = DCI.DAG;
9115 SDValue Op = N->getOperand(0);
9116
9117 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9118 Op.getOpcode() != ISD::FMUL)
9119 return SDValue();
9120
9121 uint64_t C;
9122 SDValue N0 = Op->getOperand(0);
9123 SDValue ConstVec = Op->getOperand(1);
9124 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9125
Eric Christopher1b8b94192011-06-29 21:10:36 +00009126 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
Chad Rosierfa8d8932011-06-24 19:23:04 +00009127 !isConstVecPow2(ConstVec, isSigned, C))
9128 return SDValue();
9129
Tim Northover7cbc2152013-06-28 15:29:25 +00009130 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9131 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9132 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9133 // These instructions only exist converting from f32 to i32. We can handle
9134 // smaller integers by generating an extra truncate, but larger ones would
9135 // be lossy.
9136 return SDValue();
9137 }
9138
Chad Rosierfa8d8932011-06-24 19:23:04 +00009139 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9140 Intrinsic::arm_neon_vcvtfp2fxu;
Tim Northover7cbc2152013-06-28 15:29:25 +00009141 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9142 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9143 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9144 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9145 DAG.getConstant(Log2_64(C), MVT::i32));
9146
9147 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9148 FixConv = DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), FixConv);
9149
9150 return FixConv;
Chad Rosierfa8d8932011-06-24 19:23:04 +00009151}
9152
9153/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9154/// can replace combinations of VCVT (integer to floating-point) and VDIV
9155/// when the VDIV has a constant operand that is a power of 2.
9156///
9157/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9158/// vcvt.f32.s32 d16, d16
9159/// vdiv.f32 d16, d17, d16
9160/// becomes:
9161/// vcvt.f32.s32 d16, d16, #3
9162static SDValue PerformVDIVCombine(SDNode *N,
9163 TargetLowering::DAGCombinerInfo &DCI,
9164 const ARMSubtarget *Subtarget) {
9165 SelectionDAG &DAG = DCI.DAG;
9166 SDValue Op = N->getOperand(0);
9167 unsigned OpOpcode = Op.getNode()->getOpcode();
9168
9169 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9170 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9171 return SDValue();
9172
9173 uint64_t C;
9174 SDValue ConstVec = N->getOperand(1);
9175 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9176
9177 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9178 !isConstVecPow2(ConstVec, isSigned, C))
9179 return SDValue();
9180
Tim Northover7cbc2152013-06-28 15:29:25 +00009181 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9182 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9183 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9184 // These instructions only exist converting from i32 to f32. We can handle
9185 // smaller integers by generating an extra extend, but larger ones would
9186 // be lossy.
9187 return SDValue();
9188 }
9189
9190 SDValue ConvInput = Op.getOperand(0);
9191 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9192 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9193 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9194 SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9195 ConvInput);
9196
Eric Christopher1b8b94192011-06-29 21:10:36 +00009197 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
Chad Rosierfa8d8932011-06-24 19:23:04 +00009198 Intrinsic::arm_neon_vcvtfxu2fp;
Andrew Trickef9de2a2013-05-25 02:42:55 +00009199 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
Chad Rosierfa8d8932011-06-24 19:23:04 +00009200 Op.getValueType(),
Eric Christopher1b8b94192011-06-29 21:10:36 +00009201 DAG.getConstant(IntrinsicOpcode, MVT::i32),
Tim Northover7cbc2152013-06-28 15:29:25 +00009202 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
Chad Rosierfa8d8932011-06-24 19:23:04 +00009203}
9204
9205/// Getvshiftimm - Check if this is a valid build_vector for the immediate
Bob Wilson2e076c42009-06-22 23:27:02 +00009206/// operand of a vector shift operation, where all the elements of the
9207/// build_vector must have the same constant integer value.
9208static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9209 // Ignore bit_converts.
Wesley Peck527da1b2010-11-23 03:31:01 +00009210 while (Op.getOpcode() == ISD::BITCAST)
Bob Wilson2e076c42009-06-22 23:27:02 +00009211 Op = Op.getOperand(0);
9212 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9213 APInt SplatBits, SplatUndef;
9214 unsigned SplatBitSize;
9215 bool HasAnyUndefs;
9216 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9217 HasAnyUndefs, ElementBits) ||
9218 SplatBitSize > ElementBits)
9219 return false;
9220 Cnt = SplatBits.getSExtValue();
9221 return true;
9222}
9223
9224/// isVShiftLImm - Check if this is a valid build_vector for the immediate
9225/// operand of a vector shift left operation. That value must be in the range:
9226/// 0 <= Value < ElementBits for a left shift; or
9227/// 0 <= Value <= ElementBits for a long left shift.
Owen Anderson53aa7a92009-08-10 22:56:29 +00009228static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
Bob Wilson2e076c42009-06-22 23:27:02 +00009229 assert(VT.isVector() && "vector shift count is not a vector type");
9230 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9231 if (! getVShiftImm(Op, ElementBits, Cnt))
9232 return false;
9233 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9234}
9235
9236/// isVShiftRImm - Check if this is a valid build_vector for the immediate
9237/// operand of a vector shift right operation. For a shift opcode, the value
9238/// is positive, but for an intrinsic the value count must be negative. The
9239/// absolute value must be in the range:
9240/// 1 <= |Value| <= ElementBits for a right shift; or
9241/// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
Owen Anderson53aa7a92009-08-10 22:56:29 +00009242static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
Bob Wilson2e076c42009-06-22 23:27:02 +00009243 int64_t &Cnt) {
9244 assert(VT.isVector() && "vector shift count is not a vector type");
9245 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9246 if (! getVShiftImm(Op, ElementBits, Cnt))
9247 return false;
9248 if (isIntrinsic)
9249 Cnt = -Cnt;
9250 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9251}
9252
9253/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9254static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9255 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9256 switch (IntNo) {
9257 default:
9258 // Don't do anything for most intrinsics.
9259 break;
9260
9261 // Vector shifts: check for immediate versions and lower them.
9262 // Note: This is done during DAG combining instead of DAG legalizing because
9263 // the build_vectors for 64-bit vector element shift counts are generally
9264 // not legal, and it is hard to see their values after they get legalized to
9265 // loads from a constant pool.
9266 case Intrinsic::arm_neon_vshifts:
9267 case Intrinsic::arm_neon_vshiftu:
Bob Wilson2e076c42009-06-22 23:27:02 +00009268 case Intrinsic::arm_neon_vrshifts:
9269 case Intrinsic::arm_neon_vrshiftu:
9270 case Intrinsic::arm_neon_vrshiftn:
9271 case Intrinsic::arm_neon_vqshifts:
9272 case Intrinsic::arm_neon_vqshiftu:
9273 case Intrinsic::arm_neon_vqshiftsu:
9274 case Intrinsic::arm_neon_vqshiftns:
9275 case Intrinsic::arm_neon_vqshiftnu:
9276 case Intrinsic::arm_neon_vqshiftnsu:
9277 case Intrinsic::arm_neon_vqrshiftns:
9278 case Intrinsic::arm_neon_vqrshiftnu:
9279 case Intrinsic::arm_neon_vqrshiftnsu: {
Owen Anderson53aa7a92009-08-10 22:56:29 +00009280 EVT VT = N->getOperand(1).getValueType();
Bob Wilson2e076c42009-06-22 23:27:02 +00009281 int64_t Cnt;
9282 unsigned VShiftOpc = 0;
9283
9284 switch (IntNo) {
9285 case Intrinsic::arm_neon_vshifts:
9286 case Intrinsic::arm_neon_vshiftu:
9287 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9288 VShiftOpc = ARMISD::VSHL;
9289 break;
9290 }
9291 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9292 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9293 ARMISD::VSHRs : ARMISD::VSHRu);
9294 break;
9295 }
9296 return SDValue();
9297
Bob Wilson2e076c42009-06-22 23:27:02 +00009298 case Intrinsic::arm_neon_vrshifts:
9299 case Intrinsic::arm_neon_vrshiftu:
9300 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9301 break;
9302 return SDValue();
9303
9304 case Intrinsic::arm_neon_vqshifts:
9305 case Intrinsic::arm_neon_vqshiftu:
9306 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9307 break;
9308 return SDValue();
9309
9310 case Intrinsic::arm_neon_vqshiftsu:
9311 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9312 break;
Torok Edwinfbcc6632009-07-14 16:55:14 +00009313 llvm_unreachable("invalid shift count for vqshlu intrinsic");
Bob Wilson2e076c42009-06-22 23:27:02 +00009314
Bob Wilson2e076c42009-06-22 23:27:02 +00009315 case Intrinsic::arm_neon_vrshiftn:
9316 case Intrinsic::arm_neon_vqshiftns:
9317 case Intrinsic::arm_neon_vqshiftnu:
9318 case Intrinsic::arm_neon_vqshiftnsu:
9319 case Intrinsic::arm_neon_vqrshiftns:
9320 case Intrinsic::arm_neon_vqrshiftnu:
9321 case Intrinsic::arm_neon_vqrshiftnsu:
9322 // Narrowing shifts require an immediate right shift.
9323 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9324 break;
Jim Grosbach84511e12010-06-02 21:53:11 +00009325 llvm_unreachable("invalid shift count for narrowing vector shift "
9326 "intrinsic");
Bob Wilson2e076c42009-06-22 23:27:02 +00009327
9328 default:
Torok Edwinfbcc6632009-07-14 16:55:14 +00009329 llvm_unreachable("unhandled vector shift");
Bob Wilson2e076c42009-06-22 23:27:02 +00009330 }
9331
9332 switch (IntNo) {
9333 case Intrinsic::arm_neon_vshifts:
9334 case Intrinsic::arm_neon_vshiftu:
9335 // Opcode already set above.
9336 break;
Bob Wilson2e076c42009-06-22 23:27:02 +00009337 case Intrinsic::arm_neon_vrshifts:
9338 VShiftOpc = ARMISD::VRSHRs; break;
9339 case Intrinsic::arm_neon_vrshiftu:
9340 VShiftOpc = ARMISD::VRSHRu; break;
9341 case Intrinsic::arm_neon_vrshiftn:
9342 VShiftOpc = ARMISD::VRSHRN; break;
9343 case Intrinsic::arm_neon_vqshifts:
9344 VShiftOpc = ARMISD::VQSHLs; break;
9345 case Intrinsic::arm_neon_vqshiftu:
9346 VShiftOpc = ARMISD::VQSHLu; break;
9347 case Intrinsic::arm_neon_vqshiftsu:
9348 VShiftOpc = ARMISD::VQSHLsu; break;
9349 case Intrinsic::arm_neon_vqshiftns:
9350 VShiftOpc = ARMISD::VQSHRNs; break;
9351 case Intrinsic::arm_neon_vqshiftnu:
9352 VShiftOpc = ARMISD::VQSHRNu; break;
9353 case Intrinsic::arm_neon_vqshiftnsu:
9354 VShiftOpc = ARMISD::VQSHRNsu; break;
9355 case Intrinsic::arm_neon_vqrshiftns:
9356 VShiftOpc = ARMISD::VQRSHRNs; break;
9357 case Intrinsic::arm_neon_vqrshiftnu:
9358 VShiftOpc = ARMISD::VQRSHRNu; break;
9359 case Intrinsic::arm_neon_vqrshiftnsu:
9360 VShiftOpc = ARMISD::VQRSHRNsu; break;
9361 }
9362
Andrew Trickef9de2a2013-05-25 02:42:55 +00009363 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
Owen Anderson9f944592009-08-11 20:47:22 +00009364 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
Bob Wilson2e076c42009-06-22 23:27:02 +00009365 }
9366
9367 case Intrinsic::arm_neon_vshiftins: {
Owen Anderson53aa7a92009-08-10 22:56:29 +00009368 EVT VT = N->getOperand(1).getValueType();
Bob Wilson2e076c42009-06-22 23:27:02 +00009369 int64_t Cnt;
9370 unsigned VShiftOpc = 0;
9371
9372 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9373 VShiftOpc = ARMISD::VSLI;
9374 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9375 VShiftOpc = ARMISD::VSRI;
9376 else {
Torok Edwinfbcc6632009-07-14 16:55:14 +00009377 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
Bob Wilson2e076c42009-06-22 23:27:02 +00009378 }
9379
Andrew Trickef9de2a2013-05-25 02:42:55 +00009380 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
Bob Wilson2e076c42009-06-22 23:27:02 +00009381 N->getOperand(1), N->getOperand(2),
Owen Anderson9f944592009-08-11 20:47:22 +00009382 DAG.getConstant(Cnt, MVT::i32));
Bob Wilson2e076c42009-06-22 23:27:02 +00009383 }
9384
9385 case Intrinsic::arm_neon_vqrshifts:
9386 case Intrinsic::arm_neon_vqrshiftu:
9387 // No immediate versions of these to check for.
9388 break;
9389 }
9390
9391 return SDValue();
9392}
9393
9394/// PerformShiftCombine - Checks for immediate versions of vector shifts and
9395/// lowers them. As with the vector shift intrinsics, this is done during DAG
9396/// combining instead of DAG legalizing because the build_vectors for 64-bit
9397/// vector element shift counts are generally not legal, and it is hard to see
9398/// their values after they get legalized to loads from a constant pool.
9399static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9400 const ARMSubtarget *ST) {
Owen Anderson53aa7a92009-08-10 22:56:29 +00009401 EVT VT = N->getValueType(0);
Evan Chengf258a152012-02-23 02:58:19 +00009402 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9403 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9404 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9405 SDValue N1 = N->getOperand(1);
9406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9407 SDValue N0 = N->getOperand(0);
9408 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9409 DAG.MaskedValueIsZero(N0.getOperand(0),
9410 APInt::getHighBitsSet(32, 16)))
Andrew Trickef9de2a2013-05-25 02:42:55 +00009411 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
Evan Chengf258a152012-02-23 02:58:19 +00009412 }
9413 }
Bob Wilson2e076c42009-06-22 23:27:02 +00009414
9415 // Nothing to be done for scalar shifts.
Tanya Lattnercd680952010-11-18 22:06:46 +00009416 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9417 if (!VT.isVector() || !TLI.isTypeLegal(VT))
Bob Wilson2e076c42009-06-22 23:27:02 +00009418 return SDValue();
9419
9420 assert(ST->hasNEON() && "unexpected vector shift");
9421 int64_t Cnt;
9422
9423 switch (N->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00009424 default: llvm_unreachable("unexpected shift opcode");
Bob Wilson2e076c42009-06-22 23:27:02 +00009425
9426 case ISD::SHL:
9427 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
Andrew Trickef9de2a2013-05-25 02:42:55 +00009428 return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
Owen Anderson9f944592009-08-11 20:47:22 +00009429 DAG.getConstant(Cnt, MVT::i32));
Bob Wilson2e076c42009-06-22 23:27:02 +00009430 break;
9431
9432 case ISD::SRA:
9433 case ISD::SRL:
9434 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9435 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9436 ARMISD::VSHRs : ARMISD::VSHRu);
Andrew Trickef9de2a2013-05-25 02:42:55 +00009437 return DAG.getNode(VShiftOpc, SDLoc(N), VT, N->getOperand(0),
Owen Anderson9f944592009-08-11 20:47:22 +00009438 DAG.getConstant(Cnt, MVT::i32));
Bob Wilson2e076c42009-06-22 23:27:02 +00009439 }
9440 }
9441 return SDValue();
9442}
9443
9444/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9445/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9446static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9447 const ARMSubtarget *ST) {
9448 SDValue N0 = N->getOperand(0);
9449
9450 // Check for sign- and zero-extensions of vector extract operations of 8-
9451 // and 16-bit vector elements. NEON supports these directly. They are
9452 // handled during DAG combining because type legalization will promote them
9453 // to 32-bit types and it is messy to recognize the operations after that.
9454 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9455 SDValue Vec = N0.getOperand(0);
9456 SDValue Lane = N0.getOperand(1);
Owen Anderson53aa7a92009-08-10 22:56:29 +00009457 EVT VT = N->getValueType(0);
9458 EVT EltVT = N0.getValueType();
Bob Wilson2e076c42009-06-22 23:27:02 +00009459 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9460
Owen Anderson9f944592009-08-11 20:47:22 +00009461 if (VT == MVT::i32 &&
9462 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
Bob Wilsonceb49292010-11-03 16:24:50 +00009463 TLI.isTypeLegal(Vec.getValueType()) &&
9464 isa<ConstantSDNode>(Lane)) {
Bob Wilson2e076c42009-06-22 23:27:02 +00009465
9466 unsigned Opc = 0;
9467 switch (N->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00009468 default: llvm_unreachable("unexpected opcode");
Bob Wilson2e076c42009-06-22 23:27:02 +00009469 case ISD::SIGN_EXTEND:
9470 Opc = ARMISD::VGETLANEs;
9471 break;
9472 case ISD::ZERO_EXTEND:
9473 case ISD::ANY_EXTEND:
9474 Opc = ARMISD::VGETLANEu;
9475 break;
9476 }
Andrew Trickef9de2a2013-05-25 02:42:55 +00009477 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
Bob Wilson2e076c42009-06-22 23:27:02 +00009478 }
9479 }
9480
9481 return SDValue();
9482}
9483
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009484/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9485/// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9486static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9487 const ARMSubtarget *ST) {
9488 // If the target supports NEON, try to use vmax/vmin instructions for f32
Evan Cheng55f0c6b2010-07-15 22:07:12 +00009489 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009490 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9491 // a NaN; only do the transformation when it matches that behavior.
9492
9493 // For now only do this when using NEON for FP operations; if using VFP, it
9494 // is not obvious that the benefit outweighs the cost of switching to the
9495 // NEON pipeline.
9496 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9497 N->getValueType(0) != MVT::f32)
9498 return SDValue();
9499
9500 SDValue CondLHS = N->getOperand(0);
9501 SDValue CondRHS = N->getOperand(1);
9502 SDValue LHS = N->getOperand(2);
9503 SDValue RHS = N->getOperand(3);
9504 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9505
9506 unsigned Opcode = 0;
9507 bool IsReversed;
Bob Wilsonba8ac742010-02-24 22:15:53 +00009508 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009509 IsReversed = false; // x CC y ? x : y
Bob Wilsonba8ac742010-02-24 22:15:53 +00009510 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009511 IsReversed = true ; // x CC y ? y : x
9512 } else {
9513 return SDValue();
9514 }
9515
Bob Wilsonba8ac742010-02-24 22:15:53 +00009516 bool IsUnordered;
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009517 switch (CC) {
9518 default: break;
9519 case ISD::SETOLT:
9520 case ISD::SETOLE:
9521 case ISD::SETLT:
9522 case ISD::SETLE:
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009523 case ISD::SETULT:
9524 case ISD::SETULE:
Bob Wilsonba8ac742010-02-24 22:15:53 +00009525 // If LHS is NaN, an ordered comparison will be false and the result will
9526 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9527 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9528 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9529 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9530 break;
9531 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9532 // will return -0, so vmin can only be used for unsafe math or if one of
9533 // the operands is known to be nonzero.
9534 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
Nick Lewycky50f02cb2011-12-02 22:16:29 +00009535 !DAG.getTarget().Options.UnsafeFPMath &&
Bob Wilsonba8ac742010-02-24 22:15:53 +00009536 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9537 break;
9538 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009539 break;
9540
9541 case ISD::SETOGT:
9542 case ISD::SETOGE:
9543 case ISD::SETGT:
9544 case ISD::SETGE:
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009545 case ISD::SETUGT:
9546 case ISD::SETUGE:
Bob Wilsonba8ac742010-02-24 22:15:53 +00009547 // If LHS is NaN, an ordered comparison will be false and the result will
9548 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
9549 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9550 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9551 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9552 break;
9553 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9554 // will return +0, so vmax can only be used for unsafe math or if one of
9555 // the operands is known to be nonzero.
9556 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
Nick Lewycky50f02cb2011-12-02 22:16:29 +00009557 !DAG.getTarget().Options.UnsafeFPMath &&
Bob Wilsonba8ac742010-02-24 22:15:53 +00009558 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9559 break;
9560 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009561 break;
9562 }
9563
9564 if (!Opcode)
9565 return SDValue();
Andrew Trickef9de2a2013-05-25 02:42:55 +00009566 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009567}
9568
Evan Chengf863e3f2011-07-13 00:42:17 +00009569/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9570SDValue
9571ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9572 SDValue Cmp = N->getOperand(4);
9573 if (Cmp.getOpcode() != ARMISD::CMPZ)
9574 // Only looking at EQ and NE cases.
9575 return SDValue();
9576
9577 EVT VT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00009578 SDLoc dl(N);
Evan Chengf863e3f2011-07-13 00:42:17 +00009579 SDValue LHS = Cmp.getOperand(0);
9580 SDValue RHS = Cmp.getOperand(1);
9581 SDValue FalseVal = N->getOperand(0);
9582 SDValue TrueVal = N->getOperand(1);
9583 SDValue ARMcc = N->getOperand(2);
Jim Grosbache7e2aca2011-09-13 20:30:37 +00009584 ARMCC::CondCodes CC =
9585 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
Evan Chengf863e3f2011-07-13 00:42:17 +00009586
9587 // Simplify
9588 // mov r1, r0
9589 // cmp r1, x
9590 // mov r0, y
9591 // moveq r0, x
9592 // to
9593 // cmp r0, x
9594 // movne r0, y
9595 //
9596 // mov r1, r0
9597 // cmp r1, x
9598 // mov r0, x
9599 // movne r0, y
9600 // to
9601 // cmp r0, x
9602 // movne r0, y
9603 /// FIXME: Turn this into a target neutral optimization?
9604 SDValue Res;
Evan Cheng81563762011-09-28 23:16:31 +00009605 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
Evan Chengf863e3f2011-07-13 00:42:17 +00009606 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9607 N->getOperand(3), Cmp);
9608 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9609 SDValue ARMcc;
9610 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9611 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9612 N->getOperand(3), NewCmp);
9613 }
9614
9615 if (Res.getNode()) {
9616 APInt KnownZero, KnownOne;
Jay Foada0653a32014-05-14 21:14:37 +00009617 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
Evan Chengf863e3f2011-07-13 00:42:17 +00009618 // Capture demanded bits information that would be otherwise lost.
9619 if (KnownZero == 0xfffffffe)
9620 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9621 DAG.getValueType(MVT::i1));
9622 else if (KnownZero == 0xffffff00)
9623 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9624 DAG.getValueType(MVT::i8));
9625 else if (KnownZero == 0xffff0000)
9626 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9627 DAG.getValueType(MVT::i16));
9628 }
9629
9630 return Res;
9631}
9632
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00009633SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
Bob Wilson7117a912009-03-20 22:42:55 +00009634 DAGCombinerInfo &DCI) const {
Chris Lattnerf3f4ad92007-11-27 22:36:16 +00009635 switch (N->getOpcode()) {
9636 default: break;
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +00009637 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
Tanya Lattnere9e67052011-06-14 23:48:48 +00009638 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009639 case ISD::SUB: return PerformSUBCombine(N, DCI);
Anton Korobeynikov1bf28a12010-05-15 18:16:59 +00009640 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
Jim Grosbach11013ed2010-07-16 23:05:05 +00009641 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
Evan Chenge87681c2012-02-23 01:19:06 +00009642 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9643 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
Evan Chengc1778132010-12-14 03:22:07 +00009644 case ARMISD::BFI: return PerformBFICombine(N, DCI);
Jim Grosbachd7cf55c2009-11-09 00:11:35 +00009645 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
Bob Wilson22806742010-09-22 22:09:21 +00009646 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
Bob Wilson1a20c2a2010-12-21 06:43:19 +00009647 case ISD::STORE: return PerformSTORECombine(N, DCI);
9648 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
9649 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
Bob Wilsonc7334a12010-10-27 20:38:28 +00009650 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
Bob Wilson2d790df2010-11-28 06:51:26 +00009651 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
Chad Rosierfa8d8932011-06-24 19:23:04 +00009652 case ISD::FP_TO_SINT:
9653 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9654 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009655 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
Bob Wilson2e076c42009-06-22 23:27:02 +00009656 case ISD::SHL:
9657 case ISD::SRA:
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009658 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
Bob Wilson2e076c42009-06-22 23:27:02 +00009659 case ISD::SIGN_EXTEND:
9660 case ISD::ZERO_EXTEND:
Bob Wilsonc6c13a32010-02-18 06:05:53 +00009661 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9662 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
Evan Chengf863e3f2011-07-13 00:42:17 +00009663 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
Bob Wilson06fce872011-02-07 17:43:21 +00009664 case ARMISD::VLD2DUP:
9665 case ARMISD::VLD3DUP:
9666 case ARMISD::VLD4DUP:
9667 return CombineBaseUpdate(N, DCI);
Quentin Colombet04b3a0f2013-07-03 21:42:57 +00009668 case ARMISD::BUILD_VECTOR:
9669 return PerformARMBUILD_VECTORCombine(N, DCI);
Bob Wilson06fce872011-02-07 17:43:21 +00009670 case ISD::INTRINSIC_VOID:
9671 case ISD::INTRINSIC_W_CHAIN:
9672 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9673 case Intrinsic::arm_neon_vld1:
9674 case Intrinsic::arm_neon_vld2:
9675 case Intrinsic::arm_neon_vld3:
9676 case Intrinsic::arm_neon_vld4:
9677 case Intrinsic::arm_neon_vld2lane:
9678 case Intrinsic::arm_neon_vld3lane:
9679 case Intrinsic::arm_neon_vld4lane:
9680 case Intrinsic::arm_neon_vst1:
9681 case Intrinsic::arm_neon_vst2:
9682 case Intrinsic::arm_neon_vst3:
9683 case Intrinsic::arm_neon_vst4:
9684 case Intrinsic::arm_neon_vst2lane:
9685 case Intrinsic::arm_neon_vst3lane:
9686 case Intrinsic::arm_neon_vst4lane:
9687 return CombineBaseUpdate(N, DCI);
9688 default: break;
9689 }
9690 break;
Chris Lattnerf3f4ad92007-11-27 22:36:16 +00009691 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00009692 return SDValue();
Chris Lattnerf3f4ad92007-11-27 22:36:16 +00009693}
9694
Evan Chengd42641c2011-02-02 01:06:55 +00009695bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9696 EVT VT) const {
9697 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9698}
9699
Matt Arsenault6f2a5262014-07-27 17:46:40 +00009700bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9701 unsigned,
9702 unsigned,
9703 bool *Fast) const {
Evan Cheng90ae8f82012-09-18 01:42:45 +00009704 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
Chad Rosier66bb1782012-11-09 18:25:27 +00009705 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
Bill Wendlingbae6b2c2009-08-15 21:21:19 +00009706
9707 switch (VT.getSimpleVT().SimpleTy) {
9708 default:
9709 return false;
9710 case MVT::i8:
9711 case MVT::i16:
Evan Cheng79e2ca92012-12-10 23:21:26 +00009712 case MVT::i32: {
Evan Cheng90ae8f82012-09-18 01:42:45 +00009713 // Unaligned access can use (for example) LRDB, LRDH, LDR
Evan Cheng79e2ca92012-12-10 23:21:26 +00009714 if (AllowsUnaligned) {
9715 if (Fast)
9716 *Fast = Subtarget->hasV7Ops();
9717 return true;
9718 }
9719 return false;
9720 }
Evan Chengeec6bc62012-08-15 17:44:53 +00009721 case MVT::f64:
Evan Cheng79e2ca92012-12-10 23:21:26 +00009722 case MVT::v2f64: {
Evan Cheng90ae8f82012-09-18 01:42:45 +00009723 // For any little-endian targets with neon, we can support unaligned ld/st
9724 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
Alp Tokercb402912014-01-24 17:20:08 +00009725 // A big-endian target may also explicitly support unaligned accesses
Evan Cheng79e2ca92012-12-10 23:21:26 +00009726 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
9727 if (Fast)
9728 *Fast = true;
9729 return true;
9730 }
9731 return false;
9732 }
Bill Wendlingbae6b2c2009-08-15 21:21:19 +00009733 }
9734}
9735
Lang Hames9929c422011-11-02 22:52:45 +00009736static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
9737 unsigned AlignCheck) {
9738 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
9739 (DstAlign == 0 || DstAlign % AlignCheck == 0));
9740}
9741
9742EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
9743 unsigned DstAlign, unsigned SrcAlign,
Evan Cheng962711e2012-12-12 02:34:41 +00009744 bool IsMemset, bool ZeroMemset,
Lang Hames9929c422011-11-02 22:52:45 +00009745 bool MemcpyStrSrc,
9746 MachineFunction &MF) const {
9747 const Function *F = MF.getFunction();
9748
9749 // See if we can use NEON instructions for this...
Evan Cheng962711e2012-12-12 02:34:41 +00009750 if ((!IsMemset || ZeroMemset) &&
Evan Cheng79e2ca92012-12-10 23:21:26 +00009751 Subtarget->hasNEON() &&
Bill Wendling698e84f2012-12-30 10:32:01 +00009752 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
9753 Attribute::NoImplicitFloat)) {
Evan Cheng79e2ca92012-12-10 23:21:26 +00009754 bool Fast;
Evan Chengc2bd6202012-12-11 02:31:57 +00009755 if (Size >= 16 &&
9756 (memOpAlign(SrcAlign, DstAlign, 16) ||
Matt Arsenault6f2a5262014-07-27 17:46:40 +00009757 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
Evan Cheng79e2ca92012-12-10 23:21:26 +00009758 return MVT::v2f64;
Evan Chengc2bd6202012-12-11 02:31:57 +00009759 } else if (Size >= 8 &&
9760 (memOpAlign(SrcAlign, DstAlign, 8) ||
Matt Arsenault6f2a5262014-07-27 17:46:40 +00009761 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
9762 Fast))) {
Evan Cheng79e2ca92012-12-10 23:21:26 +00009763 return MVT::f64;
Lang Hames9929c422011-11-02 22:52:45 +00009764 }
9765 }
9766
Lang Hamesb85fcd02011-11-08 18:56:23 +00009767 // Lowering to i32/i16 if the size permits.
Evan Chengc2bd6202012-12-11 02:31:57 +00009768 if (Size >= 4)
Lang Hamesb85fcd02011-11-08 18:56:23 +00009769 return MVT::i32;
Evan Chengc2bd6202012-12-11 02:31:57 +00009770 else if (Size >= 2)
Lang Hamesb85fcd02011-11-08 18:56:23 +00009771 return MVT::i16;
Lang Hamesb85fcd02011-11-08 18:56:23 +00009772
Lang Hames9929c422011-11-02 22:52:45 +00009773 // Let the target-independent logic figure it out.
9774 return MVT::Other;
9775}
9776
Evan Cheng9ec512d2012-12-06 19:13:27 +00009777bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9778 if (Val.getOpcode() != ISD::LOAD)
9779 return false;
9780
9781 EVT VT1 = Val.getValueType();
9782 if (!VT1.isSimple() || !VT1.isInteger() ||
9783 !VT2.isSimple() || !VT2.isInteger())
9784 return false;
9785
9786 switch (VT1.getSimpleVT().SimpleTy) {
9787 default: break;
9788 case MVT::i1:
9789 case MVT::i8:
9790 case MVT::i16:
9791 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
9792 return true;
9793 }
9794
9795 return false;
9796}
9797
Tim Northovercc2e9032013-08-06 13:58:03 +00009798bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
9799 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9800 return false;
9801
9802 if (!isTypeLegal(EVT::getEVT(Ty1)))
9803 return false;
9804
9805 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
9806
9807 // Assuming the caller doesn't have a zeroext or signext return parameter,
9808 // truncation all the way down to i1 is valid.
9809 return true;
9810}
9811
9812
Evan Chengdc49a8d2009-08-14 20:09:37 +00009813static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
9814 if (V < 0)
9815 return false;
9816
9817 unsigned Scale = 1;
9818 switch (VT.getSimpleVT().SimpleTy) {
9819 default: return false;
9820 case MVT::i1:
9821 case MVT::i8:
9822 // Scale == 1;
9823 break;
9824 case MVT::i16:
9825 // Scale == 2;
9826 Scale = 2;
9827 break;
9828 case MVT::i32:
9829 // Scale == 4;
9830 Scale = 4;
9831 break;
9832 }
9833
9834 if ((V & (Scale - 1)) != 0)
9835 return false;
9836 V /= Scale;
9837 return V == (V & ((1LL << 5) - 1));
9838}
9839
9840static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
9841 const ARMSubtarget *Subtarget) {
9842 bool isNeg = false;
9843 if (V < 0) {
9844 isNeg = true;
9845 V = - V;
9846 }
9847
9848 switch (VT.getSimpleVT().SimpleTy) {
9849 default: return false;
9850 case MVT::i1:
9851 case MVT::i8:
9852 case MVT::i16:
9853 case MVT::i32:
9854 // + imm12 or - imm8
9855 if (isNeg)
9856 return V == (V & ((1LL << 8) - 1));
9857 return V == (V & ((1LL << 12) - 1));
9858 case MVT::f32:
9859 case MVT::f64:
9860 // Same as ARM mode. FIXME: NEON?
9861 if (!Subtarget->hasVFP2())
9862 return false;
9863 if ((V & 3) != 0)
9864 return false;
9865 V >>= 2;
9866 return V == (V & ((1LL << 8) - 1));
9867 }
9868}
9869
Evan Cheng2150b922007-03-12 23:30:29 +00009870/// isLegalAddressImmediate - Return true if the integer value can be used
9871/// as the offset of the target addressing mode for load / store of the
9872/// given type.
Owen Anderson53aa7a92009-08-10 22:56:29 +00009873static bool isLegalAddressImmediate(int64_t V, EVT VT,
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009874 const ARMSubtarget *Subtarget) {
Evan Cheng507eefa2007-03-13 20:37:59 +00009875 if (V == 0)
9876 return true;
9877
Evan Chengce5dfb62009-03-09 19:15:00 +00009878 if (!VT.isSimple())
9879 return false;
9880
Evan Chengdc49a8d2009-08-14 20:09:37 +00009881 if (Subtarget->isThumb1Only())
9882 return isLegalT1AddressImmediate(V, VT);
9883 else if (Subtarget->isThumb2())
9884 return isLegalT2AddressImmediate(V, VT, Subtarget);
Evan Cheng2150b922007-03-12 23:30:29 +00009885
Evan Chengdc49a8d2009-08-14 20:09:37 +00009886 // ARM mode.
Evan Cheng2150b922007-03-12 23:30:29 +00009887 if (V < 0)
9888 V = - V;
Owen Anderson9f944592009-08-11 20:47:22 +00009889 switch (VT.getSimpleVT().SimpleTy) {
Evan Cheng2150b922007-03-12 23:30:29 +00009890 default: return false;
Owen Anderson9f944592009-08-11 20:47:22 +00009891 case MVT::i1:
9892 case MVT::i8:
9893 case MVT::i32:
Evan Cheng2150b922007-03-12 23:30:29 +00009894 // +- imm12
Anton Korobeynikov40d67c52008-02-20 11:22:39 +00009895 return V == (V & ((1LL << 12) - 1));
Owen Anderson9f944592009-08-11 20:47:22 +00009896 case MVT::i16:
Evan Cheng2150b922007-03-12 23:30:29 +00009897 // +- imm8
Anton Korobeynikov40d67c52008-02-20 11:22:39 +00009898 return V == (V & ((1LL << 8) - 1));
Owen Anderson9f944592009-08-11 20:47:22 +00009899 case MVT::f32:
9900 case MVT::f64:
Evan Chengdc49a8d2009-08-14 20:09:37 +00009901 if (!Subtarget->hasVFP2()) // FIXME: NEON?
Evan Cheng2150b922007-03-12 23:30:29 +00009902 return false;
Evan Chengbef131de2007-05-03 02:00:18 +00009903 if ((V & 3) != 0)
Evan Cheng2150b922007-03-12 23:30:29 +00009904 return false;
9905 V >>= 2;
Anton Korobeynikov40d67c52008-02-20 11:22:39 +00009906 return V == (V & ((1LL << 8) - 1));
Evan Cheng2150b922007-03-12 23:30:29 +00009907 }
Evan Cheng10043e22007-01-19 07:51:42 +00009908}
9909
Evan Chengdc49a8d2009-08-14 20:09:37 +00009910bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
9911 EVT VT) const {
9912 int Scale = AM.Scale;
9913 if (Scale < 0)
9914 return false;
9915
9916 switch (VT.getSimpleVT().SimpleTy) {
9917 default: return false;
9918 case MVT::i1:
9919 case MVT::i8:
9920 case MVT::i16:
9921 case MVT::i32:
9922 if (Scale == 1)
9923 return true;
9924 // r + r << imm
9925 Scale = Scale & ~1;
9926 return Scale == 2 || Scale == 4 || Scale == 8;
9927 case MVT::i64:
9928 // r + r
9929 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9930 return true;
9931 return false;
9932 case MVT::isVoid:
9933 // Note, we allow "void" uses (basically, uses that aren't loads or
9934 // stores), because arm allows folding a scale into many arithmetic
9935 // operations. This should be made more precise and revisited later.
9936
9937 // Allow r << imm, but the imm has to be a multiple of two.
9938 if (Scale & 1) return false;
9939 return isPowerOf2_32(Scale);
9940 }
9941}
9942
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009943/// isLegalAddressingMode - Return true if the addressing mode represented
9944/// by AM is legal for this target, for a load/store of the specified type.
Bob Wilson7117a912009-03-20 22:42:55 +00009945bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattner229907c2011-07-18 04:54:35 +00009946 Type *Ty) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00009947 EVT VT = getValueType(Ty, true);
Bob Wilson866c1742009-04-08 17:55:28 +00009948 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
Evan Cheng2150b922007-03-12 23:30:29 +00009949 return false;
Bob Wilson7117a912009-03-20 22:42:55 +00009950
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009951 // Can never fold addr of global into load/store.
Bob Wilson7117a912009-03-20 22:42:55 +00009952 if (AM.BaseGV)
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009953 return false;
Bob Wilson7117a912009-03-20 22:42:55 +00009954
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009955 switch (AM.Scale) {
9956 case 0: // no scale reg, must be "r+i" or "r", or "i".
9957 break;
9958 case 1:
Evan Chengdc49a8d2009-08-14 20:09:37 +00009959 if (Subtarget->isThumb1Only())
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009960 return false;
Chris Lattner502c3f42007-04-13 06:50:55 +00009961 // FALL THROUGH.
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009962 default:
Chris Lattner502c3f42007-04-13 06:50:55 +00009963 // ARM doesn't support any R+R*scale+imm addr modes.
9964 if (AM.BaseOffs)
9965 return false;
Bob Wilson7117a912009-03-20 22:42:55 +00009966
Bob Wilson866c1742009-04-08 17:55:28 +00009967 if (!VT.isSimple())
9968 return false;
9969
Evan Chengdc49a8d2009-08-14 20:09:37 +00009970 if (Subtarget->isThumb2())
9971 return isLegalT2ScaledAddressingMode(AM, VT);
9972
Chris Lattner9b6d69e2007-04-10 03:48:29 +00009973 int Scale = AM.Scale;
Owen Anderson9f944592009-08-11 20:47:22 +00009974 switch (VT.getSimpleVT().SimpleTy) {
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009975 default: return false;
Owen Anderson9f944592009-08-11 20:47:22 +00009976 case MVT::i1:
9977 case MVT::i8:
9978 case MVT::i32:
Chris Lattner9b6d69e2007-04-10 03:48:29 +00009979 if (Scale < 0) Scale = -Scale;
9980 if (Scale == 1)
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009981 return true;
9982 // r + r << imm
Chris Lattnerfe926e22007-04-11 16:17:12 +00009983 return isPowerOf2_32(Scale & ~1);
Owen Anderson9f944592009-08-11 20:47:22 +00009984 case MVT::i16:
Evan Chengdc49a8d2009-08-14 20:09:37 +00009985 case MVT::i64:
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009986 // r + r
Chris Lattner9b6d69e2007-04-10 03:48:29 +00009987 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009988 return true;
Chris Lattnerfe926e22007-04-11 16:17:12 +00009989 return false;
Bob Wilson7117a912009-03-20 22:42:55 +00009990
Owen Anderson9f944592009-08-11 20:47:22 +00009991 case MVT::isVoid:
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009992 // Note, we allow "void" uses (basically, uses that aren't loads or
9993 // stores), because arm allows folding a scale into many arithmetic
9994 // operations. This should be made more precise and revisited later.
Bob Wilson7117a912009-03-20 22:42:55 +00009995
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009996 // Allow r << imm, but the imm has to be a multiple of two.
Evan Chengdc49a8d2009-08-14 20:09:37 +00009997 if (Scale & 1) return false;
9998 return isPowerOf2_32(Scale);
Chris Lattnerd44e24c2007-04-09 23:33:39 +00009999 }
Evan Cheng2150b922007-03-12 23:30:29 +000010000 }
Chris Lattnerd44e24c2007-04-09 23:33:39 +000010001 return true;
Evan Cheng2150b922007-03-12 23:30:29 +000010002}
10003
Evan Cheng3d3c24a2009-11-11 19:05:52 +000010004/// isLegalICmpImmediate - Return true if the specified immediate is legal
10005/// icmp immediate, that is the target has icmp instructions which can compare
10006/// a register against the immediate without having to materialize the
10007/// immediate into a register.
Evan Cheng15b80e42009-11-12 07:13:11 +000010008bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
Jakob Stoklund Olesen967b86a2012-04-06 17:45:04 +000010009 // Thumb2 and ARM modes can use cmn for negative immediates.
Evan Cheng3d3c24a2009-11-11 19:05:52 +000010010 if (!Subtarget->isThumb())
Chandler Carruth8a102c22012-04-06 20:10:52 +000010011 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
Evan Cheng3d3c24a2009-11-11 19:05:52 +000010012 if (Subtarget->isThumb2())
Chandler Carruth8a102c22012-04-06 20:10:52 +000010013 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
Jakob Stoklund Olesen967b86a2012-04-06 17:45:04 +000010014 // Thumb1 doesn't have cmn, and only 8-bit immediates.
Evan Cheng15b80e42009-11-12 07:13:11 +000010015 return Imm >= 0 && Imm <= 255;
Evan Cheng3d3c24a2009-11-11 19:05:52 +000010016}
10017
Andrew Tricka22cdb72012-07-18 18:34:27 +000010018/// isLegalAddImmediate - Return true if the specified immediate is a legal add
10019/// *or sub* immediate, that is the target has add or sub instructions which can
10020/// add a register with the immediate without having to materialize the
Dan Gohman6136e942011-05-03 00:46:49 +000010021/// immediate into a register.
10022bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
Andrew Tricka22cdb72012-07-18 18:34:27 +000010023 // Same encoding for add/sub, just flip the sign.
10024 int64_t AbsImm = llvm::abs64(Imm);
10025 if (!Subtarget->isThumb())
10026 return ARM_AM::getSOImmVal(AbsImm) != -1;
10027 if (Subtarget->isThumb2())
10028 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10029 // Thumb1 only has 8-bit unsigned immediate.
10030 return AbsImm >= 0 && AbsImm <= 255;
Dan Gohman6136e942011-05-03 00:46:49 +000010031}
10032
Owen Anderson53aa7a92009-08-10 22:56:29 +000010033static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
Evan Cheng84c6cda2009-07-02 07:28:31 +000010034 bool isSEXTLoad, SDValue &Base,
10035 SDValue &Offset, bool &isInc,
10036 SelectionDAG &DAG) {
Evan Cheng10043e22007-01-19 07:51:42 +000010037 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10038 return false;
10039
Owen Anderson9f944592009-08-11 20:47:22 +000010040 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
Evan Cheng10043e22007-01-19 07:51:42 +000010041 // AddressingMode 3
10042 Base = Ptr->getOperand(0);
10043 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
Dan Gohmaneffb8942008-09-12 16:56:44 +000010044 int RHSC = (int)RHS->getZExtValue();
Evan Cheng10043e22007-01-19 07:51:42 +000010045 if (RHSC < 0 && RHSC > -256) {
Evan Cheng84c6cda2009-07-02 07:28:31 +000010046 assert(Ptr->getOpcode() == ISD::ADD);
Evan Cheng10043e22007-01-19 07:51:42 +000010047 isInc = false;
10048 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10049 return true;
10050 }
10051 }
10052 isInc = (Ptr->getOpcode() == ISD::ADD);
10053 Offset = Ptr->getOperand(1);
10054 return true;
Owen Anderson9f944592009-08-11 20:47:22 +000010055 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
Evan Cheng10043e22007-01-19 07:51:42 +000010056 // AddressingMode 2
10057 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
Dan Gohmaneffb8942008-09-12 16:56:44 +000010058 int RHSC = (int)RHS->getZExtValue();
Evan Cheng10043e22007-01-19 07:51:42 +000010059 if (RHSC < 0 && RHSC > -0x1000) {
Evan Cheng84c6cda2009-07-02 07:28:31 +000010060 assert(Ptr->getOpcode() == ISD::ADD);
Evan Cheng10043e22007-01-19 07:51:42 +000010061 isInc = false;
10062 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10063 Base = Ptr->getOperand(0);
10064 return true;
10065 }
10066 }
10067
10068 if (Ptr->getOpcode() == ISD::ADD) {
10069 isInc = true;
Evan Chenga20cde32011-07-20 23:34:39 +000010070 ARM_AM::ShiftOpc ShOpcVal=
10071 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
Evan Cheng10043e22007-01-19 07:51:42 +000010072 if (ShOpcVal != ARM_AM::no_shift) {
10073 Base = Ptr->getOperand(1);
10074 Offset = Ptr->getOperand(0);
10075 } else {
10076 Base = Ptr->getOperand(0);
10077 Offset = Ptr->getOperand(1);
10078 }
10079 return true;
10080 }
10081
10082 isInc = (Ptr->getOpcode() == ISD::ADD);
10083 Base = Ptr->getOperand(0);
10084 Offset = Ptr->getOperand(1);
10085 return true;
10086 }
10087
Jim Grosbachd7cf55c2009-11-09 00:11:35 +000010088 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
Evan Cheng10043e22007-01-19 07:51:42 +000010089 return false;
10090}
10091
Owen Anderson53aa7a92009-08-10 22:56:29 +000010092static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
Evan Cheng84c6cda2009-07-02 07:28:31 +000010093 bool isSEXTLoad, SDValue &Base,
10094 SDValue &Offset, bool &isInc,
10095 SelectionDAG &DAG) {
10096 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10097 return false;
10098
10099 Base = Ptr->getOperand(0);
10100 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10101 int RHSC = (int)RHS->getZExtValue();
10102 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10103 assert(Ptr->getOpcode() == ISD::ADD);
10104 isInc = false;
10105 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10106 return true;
10107 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10108 isInc = Ptr->getOpcode() == ISD::ADD;
10109 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
10110 return true;
10111 }
10112 }
10113
10114 return false;
10115}
10116
Evan Cheng10043e22007-01-19 07:51:42 +000010117/// getPreIndexedAddressParts - returns true by value, base pointer and
10118/// offset pointer and addressing mode by reference if the node's address
10119/// can be legally represented as pre-indexed load / store address.
10120bool
Dan Gohman2ce6f2a2008-07-27 21:46:04 +000010121ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10122 SDValue &Offset,
Evan Cheng10043e22007-01-19 07:51:42 +000010123 ISD::MemIndexedMode &AM,
Dan Gohman02b93132009-01-15 16:29:45 +000010124 SelectionDAG &DAG) const {
Evan Cheng84c6cda2009-07-02 07:28:31 +000010125 if (Subtarget->isThumb1Only())
Evan Cheng10043e22007-01-19 07:51:42 +000010126 return false;
10127
Owen Anderson53aa7a92009-08-10 22:56:29 +000010128 EVT VT;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +000010129 SDValue Ptr;
Evan Cheng10043e22007-01-19 07:51:42 +000010130 bool isSEXTLoad = false;
10131 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10132 Ptr = LD->getBasePtr();
Dan Gohman47a7d6f2008-01-30 00:15:11 +000010133 VT = LD->getMemoryVT();
Evan Cheng10043e22007-01-19 07:51:42 +000010134 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10135 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10136 Ptr = ST->getBasePtr();
Dan Gohman47a7d6f2008-01-30 00:15:11 +000010137 VT = ST->getMemoryVT();
Evan Cheng10043e22007-01-19 07:51:42 +000010138 } else
10139 return false;
10140
10141 bool isInc;
Evan Cheng84c6cda2009-07-02 07:28:31 +000010142 bool isLegal = false;
Evan Chengdc49a8d2009-08-14 20:09:37 +000010143 if (Subtarget->isThumb2())
Evan Cheng84c6cda2009-07-02 07:28:31 +000010144 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10145 Offset, isInc, DAG);
Jim Grosbachf24f9d92009-08-11 15:33:49 +000010146 else
Evan Cheng84c6cda2009-07-02 07:28:31 +000010147 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
Evan Cheng844f0b42009-07-02 06:44:30 +000010148 Offset, isInc, DAG);
Evan Cheng84c6cda2009-07-02 07:28:31 +000010149 if (!isLegal)
10150 return false;
10151
10152 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10153 return true;
Evan Cheng10043e22007-01-19 07:51:42 +000010154}
10155
10156/// getPostIndexedAddressParts - returns true by value, base pointer and
10157/// offset pointer and addressing mode by reference if this node can be
10158/// combined with a load / store to form a post-indexed load / store.
10159bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman2ce6f2a2008-07-27 21:46:04 +000010160 SDValue &Base,
10161 SDValue &Offset,
Evan Cheng10043e22007-01-19 07:51:42 +000010162 ISD::MemIndexedMode &AM,
Dan Gohman02b93132009-01-15 16:29:45 +000010163 SelectionDAG &DAG) const {
Evan Cheng84c6cda2009-07-02 07:28:31 +000010164 if (Subtarget->isThumb1Only())
Evan Cheng10043e22007-01-19 07:51:42 +000010165 return false;
10166
Owen Anderson53aa7a92009-08-10 22:56:29 +000010167 EVT VT;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +000010168 SDValue Ptr;
Evan Cheng10043e22007-01-19 07:51:42 +000010169 bool isSEXTLoad = false;
10170 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Dan Gohman47a7d6f2008-01-30 00:15:11 +000010171 VT = LD->getMemoryVT();
Evan Chengf19384d2010-05-18 21:31:17 +000010172 Ptr = LD->getBasePtr();
Evan Cheng10043e22007-01-19 07:51:42 +000010173 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10174 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Dan Gohman47a7d6f2008-01-30 00:15:11 +000010175 VT = ST->getMemoryVT();
Evan Chengf19384d2010-05-18 21:31:17 +000010176 Ptr = ST->getBasePtr();
Evan Cheng10043e22007-01-19 07:51:42 +000010177 } else
10178 return false;
10179
10180 bool isInc;
Evan Cheng84c6cda2009-07-02 07:28:31 +000010181 bool isLegal = false;
Evan Chengdc49a8d2009-08-14 20:09:37 +000010182 if (Subtarget->isThumb2())
Evan Cheng84c6cda2009-07-02 07:28:31 +000010183 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
Evan Chengf19384d2010-05-18 21:31:17 +000010184 isInc, DAG);
Jim Grosbachf24f9d92009-08-11 15:33:49 +000010185 else
Evan Cheng84c6cda2009-07-02 07:28:31 +000010186 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10187 isInc, DAG);
10188 if (!isLegal)
10189 return false;
10190
Evan Chengf19384d2010-05-18 21:31:17 +000010191 if (Ptr != Base) {
10192 // Swap base ptr and offset to catch more post-index load / store when
10193 // it's legal. In Thumb2 mode, offset must be an immediate.
10194 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10195 !Subtarget->isThumb2())
10196 std::swap(Base, Offset);
10197
10198 // Post-indexed load / store update the base pointer.
10199 if (Ptr != Base)
10200 return false;
10201 }
10202
Evan Cheng84c6cda2009-07-02 07:28:31 +000010203 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10204 return true;
Evan Cheng10043e22007-01-19 07:51:42 +000010205}
10206
Jay Foada0653a32014-05-14 21:14:37 +000010207void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10208 APInt &KnownZero,
10209 APInt &KnownOne,
10210 const SelectionDAG &DAG,
10211 unsigned Depth) const {
Michael Gottesman696e44e2013-06-18 20:49:45 +000010212 unsigned BitWidth = KnownOne.getBitWidth();
10213 KnownZero = KnownOne = APInt(BitWidth, 0);
Evan Cheng10043e22007-01-19 07:51:42 +000010214 switch (Op.getOpcode()) {
10215 default: break;
Michael Gottesman696e44e2013-06-18 20:49:45 +000010216 case ARMISD::ADDC:
10217 case ARMISD::ADDE:
10218 case ARMISD::SUBC:
10219 case ARMISD::SUBE:
10220 // These nodes' second result is a boolean
10221 if (Op.getResNo() == 0)
10222 break;
10223 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10224 break;
Evan Cheng10043e22007-01-19 07:51:42 +000010225 case ARMISD::CMOV: {
10226 // Bits are known zero/one if known on the LHS and RHS.
Jay Foada0653a32014-05-14 21:14:37 +000010227 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
Evan Cheng10043e22007-01-19 07:51:42 +000010228 if (KnownZero == 0 && KnownOne == 0) return;
10229
Dan Gohmanf990faf2008-02-13 00:35:47 +000010230 APInt KnownZeroRHS, KnownOneRHS;
Jay Foada0653a32014-05-14 21:14:37 +000010231 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
Evan Cheng10043e22007-01-19 07:51:42 +000010232 KnownZero &= KnownZeroRHS;
10233 KnownOne &= KnownOneRHS;
10234 return;
10235 }
Tim Northover01b4aa92014-04-03 15:10:35 +000010236 case ISD::INTRINSIC_W_CHAIN: {
10237 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10238 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10239 switch (IntID) {
10240 default: return;
10241 case Intrinsic::arm_ldaex:
10242 case Intrinsic::arm_ldrex: {
10243 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10244 unsigned MemBits = VT.getScalarType().getSizeInBits();
10245 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10246 return;
10247 }
10248 }
10249 }
Evan Cheng10043e22007-01-19 07:51:42 +000010250 }
10251}
10252
10253//===----------------------------------------------------------------------===//
10254// ARM Inline Assembly Support
10255//===----------------------------------------------------------------------===//
10256
Evan Cheng078b0b02011-01-08 01:24:27 +000010257bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10258 // Looking for "rev" which is V6+.
10259 if (!Subtarget->hasV6Ops())
10260 return false;
10261
10262 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10263 std::string AsmStr = IA->getAsmString();
10264 SmallVector<StringRef, 4> AsmPieces;
10265 SplitString(AsmStr, AsmPieces, ";\n");
10266
10267 switch (AsmPieces.size()) {
10268 default: return false;
10269 case 1:
10270 AsmStr = AsmPieces[0];
10271 AsmPieces.clear();
10272 SplitString(AsmStr, AsmPieces, " \t,");
10273
10274 // rev $0, $1
10275 if (AsmPieces.size() == 3 &&
10276 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10277 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
Chris Lattner229907c2011-07-18 04:54:35 +000010278 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
Evan Cheng078b0b02011-01-08 01:24:27 +000010279 if (Ty && Ty->getBitWidth() == 32)
10280 return IntrinsicLowering::LowerToByteSwap(CI);
10281 }
10282 break;
10283 }
10284
10285 return false;
10286}
10287
Evan Cheng10043e22007-01-19 07:51:42 +000010288/// getConstraintType - Given a constraint letter, return the type of
10289/// constraint it is for this target.
10290ARMTargetLowering::ConstraintType
Chris Lattnerd6855142007-03-25 02:14:49 +000010291ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10292 if (Constraint.size() == 1) {
10293 switch (Constraint[0]) {
10294 default: break;
10295 case 'l': return C_RegisterClass;
Chris Lattner6223e832007-04-02 17:24:08 +000010296 case 'w': return C_RegisterClass;
Eric Christopherf45daac2011-06-30 23:23:01 +000010297 case 'h': return C_RegisterClass;
Eric Christopherf1c74592011-07-01 00:14:47 +000010298 case 'x': return C_RegisterClass;
Eric Christopherc011d312011-07-01 00:30:46 +000010299 case 't': return C_RegisterClass;
Eric Christopher29f1db82011-07-01 01:00:07 +000010300 case 'j': return C_Other; // Constant for movw.
Eric Christopheraa503002011-07-29 21:18:58 +000010301 // An address with a single base register. Due to the way we
10302 // currently handle addresses it is the same as an 'r' memory constraint.
10303 case 'Q': return C_Memory;
Chris Lattnerd6855142007-03-25 02:14:49 +000010304 }
Eric Christophere256cd02011-06-21 22:10:57 +000010305 } else if (Constraint.size() == 2) {
10306 switch (Constraint[0]) {
10307 default: break;
10308 // All 'U+' constraints are addresses.
10309 case 'U': return C_Memory;
10310 }
Evan Cheng10043e22007-01-19 07:51:42 +000010311 }
Chris Lattnerd6855142007-03-25 02:14:49 +000010312 return TargetLowering::getConstraintType(Constraint);
Evan Cheng10043e22007-01-19 07:51:42 +000010313}
10314
John Thompsone8360b72010-10-29 17:29:13 +000010315/// Examine constraint type and operand type and determine a weight value.
10316/// This object must already have been set up with the operand type
10317/// and the current alternative constraint selected.
10318TargetLowering::ConstraintWeight
10319ARMTargetLowering::getSingleConstraintMatchWeight(
10320 AsmOperandInfo &info, const char *constraint) const {
10321 ConstraintWeight weight = CW_Invalid;
10322 Value *CallOperandVal = info.CallOperandVal;
10323 // If we don't have a value, we can't do a match,
10324 // but allow it at the lowest weight.
Craig Topper062a2ba2014-04-25 05:30:21 +000010325 if (!CallOperandVal)
John Thompsone8360b72010-10-29 17:29:13 +000010326 return CW_Default;
Chris Lattner229907c2011-07-18 04:54:35 +000010327 Type *type = CallOperandVal->getType();
John Thompsone8360b72010-10-29 17:29:13 +000010328 // Look at the constraint type.
10329 switch (*constraint) {
10330 default:
10331 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10332 break;
10333 case 'l':
10334 if (type->isIntegerTy()) {
10335 if (Subtarget->isThumb())
10336 weight = CW_SpecificReg;
10337 else
10338 weight = CW_Register;
10339 }
10340 break;
10341 case 'w':
10342 if (type->isFloatingPointTy())
10343 weight = CW_Register;
10344 break;
10345 }
10346 return weight;
10347}
10348
Eric Christophercf2007c2011-06-30 23:50:52 +000010349typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10350RCPair
Evan Cheng10043e22007-01-19 07:51:42 +000010351ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Chad Rosier295bd432013-06-22 18:37:38 +000010352 MVT VT) const {
Evan Cheng10043e22007-01-19 07:51:42 +000010353 if (Constraint.size() == 1) {
Jakob Stoklund Olesen0ca14e42010-01-14 18:19:56 +000010354 // GCC ARM Constraint Letters
Evan Cheng10043e22007-01-19 07:51:42 +000010355 switch (Constraint[0]) {
Eric Christopherf45daac2011-06-30 23:23:01 +000010356 case 'l': // Low regs or general regs.
Jakob Stoklund Olesen0ca14e42010-01-14 18:19:56 +000010357 if (Subtarget->isThumb())
Craig Topperc7242e02012-04-20 07:30:17 +000010358 return RCPair(0U, &ARM::tGPRRegClass);
10359 return RCPair(0U, &ARM::GPRRegClass);
Eric Christopherf45daac2011-06-30 23:23:01 +000010360 case 'h': // High regs or no regs.
10361 if (Subtarget->isThumb())
Craig Topperc7242e02012-04-20 07:30:17 +000010362 return RCPair(0U, &ARM::hGPRRegClass);
Eric Christopherf09b0f12011-07-01 00:19:27 +000010363 break;
Chris Lattner6223e832007-04-02 17:24:08 +000010364 case 'r':
Craig Topperc7242e02012-04-20 07:30:17 +000010365 return RCPair(0U, &ARM::GPRRegClass);
Chris Lattner6223e832007-04-02 17:24:08 +000010366 case 'w':
Tim Northover28adfbb2013-11-14 17:15:39 +000010367 if (VT == MVT::Other)
10368 break;
Owen Anderson9f944592009-08-11 20:47:22 +000010369 if (VT == MVT::f32)
Craig Topperc7242e02012-04-20 07:30:17 +000010370 return RCPair(0U, &ARM::SPRRegClass);
Bob Wilson3152b0472009-12-18 01:03:29 +000010371 if (VT.getSizeInBits() == 64)
Craig Topperc7242e02012-04-20 07:30:17 +000010372 return RCPair(0U, &ARM::DPRRegClass);
Evan Cheng0c2544f2009-12-08 23:06:22 +000010373 if (VT.getSizeInBits() == 128)
Craig Topperc7242e02012-04-20 07:30:17 +000010374 return RCPair(0U, &ARM::QPRRegClass);
Chris Lattner6223e832007-04-02 17:24:08 +000010375 break;
Eric Christopherf1c74592011-07-01 00:14:47 +000010376 case 'x':
Tim Northover28adfbb2013-11-14 17:15:39 +000010377 if (VT == MVT::Other)
10378 break;
Eric Christopherf1c74592011-07-01 00:14:47 +000010379 if (VT == MVT::f32)
Craig Topperc7242e02012-04-20 07:30:17 +000010380 return RCPair(0U, &ARM::SPR_8RegClass);
Eric Christopherf1c74592011-07-01 00:14:47 +000010381 if (VT.getSizeInBits() == 64)
Craig Topperc7242e02012-04-20 07:30:17 +000010382 return RCPair(0U, &ARM::DPR_8RegClass);
Eric Christopherf1c74592011-07-01 00:14:47 +000010383 if (VT.getSizeInBits() == 128)
Craig Topperc7242e02012-04-20 07:30:17 +000010384 return RCPair(0U, &ARM::QPR_8RegClass);
Eric Christopherf1c74592011-07-01 00:14:47 +000010385 break;
Eric Christopherc011d312011-07-01 00:30:46 +000010386 case 't':
10387 if (VT == MVT::f32)
Craig Topperc7242e02012-04-20 07:30:17 +000010388 return RCPair(0U, &ARM::SPRRegClass);
Eric Christopherc011d312011-07-01 00:30:46 +000010389 break;
Evan Cheng10043e22007-01-19 07:51:42 +000010390 }
10391 }
Bob Wilson3f2293b2010-03-15 23:09:18 +000010392 if (StringRef("{cc}").equals_lower(Constraint))
Craig Topperc7242e02012-04-20 07:30:17 +000010393 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
Bob Wilson3f2293b2010-03-15 23:09:18 +000010394
Evan Cheng10043e22007-01-19 07:51:42 +000010395 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10396}
10397
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010398/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10399/// vector. If it is invalid, don't add anything to Ops.
10400void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopherde9399b2011-06-02 23:16:42 +000010401 std::string &Constraint,
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010402 std::vector<SDValue>&Ops,
10403 SelectionDAG &DAG) const {
Craig Topper062a2ba2014-04-25 05:30:21 +000010404 SDValue Result;
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010405
Eric Christopherde9399b2011-06-02 23:16:42 +000010406 // Currently only support length 1 constraints.
10407 if (Constraint.length() != 1) return;
Eric Christopher0713a9d2011-06-08 23:55:35 +000010408
Eric Christopherde9399b2011-06-02 23:16:42 +000010409 char ConstraintLetter = Constraint[0];
10410 switch (ConstraintLetter) {
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010411 default: break;
Eric Christopher29f1db82011-07-01 01:00:07 +000010412 case 'j':
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010413 case 'I': case 'J': case 'K': case 'L':
10414 case 'M': case 'N': case 'O':
10415 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10416 if (!C)
10417 return;
10418
10419 int64_t CVal64 = C->getSExtValue();
10420 int CVal = (int) CVal64;
10421 // None of these constraints allow values larger than 32 bits. Check
10422 // that the value fits in an int.
10423 if (CVal != CVal64)
10424 return;
10425
Eric Christopherde9399b2011-06-02 23:16:42 +000010426 switch (ConstraintLetter) {
Eric Christopher29f1db82011-07-01 01:00:07 +000010427 case 'j':
Andrew Trick53df4b62011-09-20 03:06:13 +000010428 // Constant suitable for movw, must be between 0 and
10429 // 65535.
10430 if (Subtarget->hasV6T2Ops())
10431 if (CVal >= 0 && CVal <= 65535)
10432 break;
10433 return;
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010434 case 'I':
David Goodwin22c2fba2009-07-08 23:10:31 +000010435 if (Subtarget->isThumb1Only()) {
10436 // This must be a constant between 0 and 255, for ADD
10437 // immediates.
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010438 if (CVal >= 0 && CVal <= 255)
10439 break;
David Goodwin22c2fba2009-07-08 23:10:31 +000010440 } else if (Subtarget->isThumb2()) {
10441 // A constant that can be used as an immediate value in a
10442 // data-processing instruction.
10443 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10444 break;
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010445 } else {
10446 // A constant that can be used as an immediate value in a
10447 // data-processing instruction.
10448 if (ARM_AM::getSOImmVal(CVal) != -1)
10449 break;
10450 }
10451 return;
10452
10453 case 'J':
David Goodwin22c2fba2009-07-08 23:10:31 +000010454 if (Subtarget->isThumb()) { // FIXME thumb2
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010455 // This must be a constant between -255 and -1, for negated ADD
10456 // immediates. This can be used in GCC with an "n" modifier that
10457 // prints the negated value, for use with SUB instructions. It is
10458 // not useful otherwise but is implemented for compatibility.
10459 if (CVal >= -255 && CVal <= -1)
10460 break;
10461 } else {
10462 // This must be a constant between -4095 and 4095. It is not clear
10463 // what this constraint is intended for. Implemented for
10464 // compatibility with GCC.
10465 if (CVal >= -4095 && CVal <= 4095)
10466 break;
10467 }
10468 return;
10469
10470 case 'K':
David Goodwin22c2fba2009-07-08 23:10:31 +000010471 if (Subtarget->isThumb1Only()) {
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010472 // A 32-bit value where only one byte has a nonzero value. Exclude
10473 // zero to match GCC. This constraint is used by GCC internally for
10474 // constants that can be loaded with a move/shift combination.
10475 // It is not useful otherwise but is implemented for compatibility.
10476 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10477 break;
David Goodwin22c2fba2009-07-08 23:10:31 +000010478 } else if (Subtarget->isThumb2()) {
10479 // A constant whose bitwise inverse can be used as an immediate
10480 // value in a data-processing instruction. This can be used in GCC
10481 // with a "B" modifier that prints the inverted value, for use with
10482 // BIC and MVN instructions. It is not useful otherwise but is
10483 // implemented for compatibility.
10484 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10485 break;
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010486 } else {
10487 // A constant whose bitwise inverse can be used as an immediate
10488 // value in a data-processing instruction. This can be used in GCC
10489 // with a "B" modifier that prints the inverted value, for use with
10490 // BIC and MVN instructions. It is not useful otherwise but is
10491 // implemented for compatibility.
10492 if (ARM_AM::getSOImmVal(~CVal) != -1)
10493 break;
10494 }
10495 return;
10496
10497 case 'L':
David Goodwin22c2fba2009-07-08 23:10:31 +000010498 if (Subtarget->isThumb1Only()) {
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010499 // This must be a constant between -7 and 7,
10500 // for 3-operand ADD/SUB immediate instructions.
10501 if (CVal >= -7 && CVal < 7)
10502 break;
David Goodwin22c2fba2009-07-08 23:10:31 +000010503 } else if (Subtarget->isThumb2()) {
10504 // A constant whose negation can be used as an immediate value in a
10505 // data-processing instruction. This can be used in GCC with an "n"
10506 // modifier that prints the negated value, for use with SUB
10507 // instructions. It is not useful otherwise but is implemented for
10508 // compatibility.
10509 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10510 break;
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010511 } else {
10512 // A constant whose negation can be used as an immediate value in a
10513 // data-processing instruction. This can be used in GCC with an "n"
10514 // modifier that prints the negated value, for use with SUB
10515 // instructions. It is not useful otherwise but is implemented for
10516 // compatibility.
10517 if (ARM_AM::getSOImmVal(-CVal) != -1)
10518 break;
10519 }
10520 return;
10521
10522 case 'M':
David Goodwin22c2fba2009-07-08 23:10:31 +000010523 if (Subtarget->isThumb()) { // FIXME thumb2
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010524 // This must be a multiple of 4 between 0 and 1020, for
10525 // ADD sp + immediate.
10526 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10527 break;
10528 } else {
10529 // A power of two or a constant between 0 and 32. This is used in
10530 // GCC for the shift amount on shifted register operands, but it is
10531 // useful in general for any shift amounts.
10532 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10533 break;
10534 }
10535 return;
10536
10537 case 'N':
David Goodwin22c2fba2009-07-08 23:10:31 +000010538 if (Subtarget->isThumb()) { // FIXME thumb2
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010539 // This must be a constant between 0 and 31, for shift amounts.
10540 if (CVal >= 0 && CVal <= 31)
10541 break;
10542 }
10543 return;
10544
10545 case 'O':
David Goodwin22c2fba2009-07-08 23:10:31 +000010546 if (Subtarget->isThumb()) { // FIXME thumb2
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010547 // This must be a multiple of 4 between -508 and 508, for
10548 // ADD/SUB sp = sp + immediate.
10549 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10550 break;
10551 }
10552 return;
10553 }
10554 Result = DAG.getTargetConstant(CVal, Op.getValueType());
10555 break;
10556 }
10557
10558 if (Result.getNode()) {
10559 Ops.push_back(Result);
10560 return;
10561 }
Dale Johannesence97d552010-06-25 21:55:36 +000010562 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +000010563}
Anton Korobeynikov29a44df2009-09-23 19:04:09 +000010564
Renato Golin87610692013-07-16 09:32:17 +000010565SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
10566 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10567 unsigned Opcode = Op->getOpcode();
10568 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10569 "Invalid opcode for Div/Rem lowering");
10570 bool isSigned = (Opcode == ISD::SDIVREM);
10571 EVT VT = Op->getValueType(0);
10572 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10573
10574 RTLIB::Libcall LC;
10575 switch (VT.getSimpleVT().SimpleTy) {
10576 default: llvm_unreachable("Unexpected request for libcall!");
10577 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10578 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10579 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10580 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10581 }
10582
10583 SDValue InChain = DAG.getEntryNode();
10584
10585 TargetLowering::ArgListTy Args;
10586 TargetLowering::ArgListEntry Entry;
10587 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10588 EVT ArgVT = Op->getOperand(i).getValueType();
10589 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10590 Entry.Node = Op->getOperand(i);
10591 Entry.Ty = ArgTy;
10592 Entry.isSExt = isSigned;
10593 Entry.isZExt = !isSigned;
10594 Args.push_back(Entry);
10595 }
10596
10597 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10598 getPointerTy());
10599
10600 Type *RetTy = (Type*)StructType::get(Ty, Ty, NULL);
10601
10602 SDLoc dl(Op);
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +000010603 TargetLowering::CallLoweringInfo CLI(DAG);
10604 CLI.setDebugLoc(dl).setChain(InChain)
Juergen Ributzka3bd03c72014-07-01 22:01:54 +000010605 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +000010606 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
Renato Golin87610692013-07-16 09:32:17 +000010607
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +000010608 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
Renato Golin87610692013-07-16 09:32:17 +000010609 return CallInfo.first;
10610}
10611
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +000010612SDValue
10613ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
10614 assert(Subtarget->isTargetWindows() && "unsupported target platform");
10615 SDLoc DL(Op);
10616
10617 // Get the inputs.
10618 SDValue Chain = Op.getOperand(0);
10619 SDValue Size = Op.getOperand(1);
10620
10621 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
10622 DAG.getConstant(2, MVT::i32));
10623
10624 SDValue Flag;
10625 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
10626 Flag = Chain.getValue(1);
10627
Saleem Abdulrasoolc4e00282014-07-19 01:29:51 +000010628 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +000010629 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
10630
10631 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
10632 Chain = NewSP.getValue(1);
10633
10634 SDValue Ops[2] = { NewSP, Chain };
10635 return DAG.getMergeValues(Ops, DL);
10636}
10637
Anton Korobeynikov29a44df2009-09-23 19:04:09 +000010638bool
10639ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10640 // The ARM target isn't yet aware of offsets.
10641 return false;
10642}
Evan Cheng4a609f3c2009-10-28 01:44:26 +000010643
Jim Grosbach11013ed2010-07-16 23:05:05 +000010644bool ARM::isBitFieldInvertedMask(unsigned v) {
10645 if (v == 0xffffffff)
Benjamin Kramer8bad66e2013-05-19 22:01:57 +000010646 return false;
10647
Jim Grosbach11013ed2010-07-16 23:05:05 +000010648 // there can be 1's on either or both "outsides", all the "inside"
10649 // bits must be 0's
Benjamin Kramer8bad66e2013-05-19 22:01:57 +000010650 unsigned TO = CountTrailingOnes_32(v);
10651 unsigned LO = CountLeadingOnes_32(v);
10652 v = (v >> TO) << TO;
10653 v = (v << LO) >> LO;
10654 return v == 0;
Jim Grosbach11013ed2010-07-16 23:05:05 +000010655}
10656
Evan Cheng4a609f3c2009-10-28 01:44:26 +000010657/// isFPImmLegal - Returns true if the target can instruction select the
10658/// specified FP immediate natively. If false, the legalizer will
10659/// materialize the FP immediate as a load from a constant pool.
10660bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10661 if (!Subtarget->hasVFP3())
10662 return false;
10663 if (VT == MVT::f32)
Jim Grosbachefc761a2011-09-30 00:50:06 +000010664 return ARM_AM::getFP32Imm(Imm) != -1;
Evan Cheng4a609f3c2009-10-28 01:44:26 +000010665 if (VT == MVT::f64)
Jim Grosbachefc761a2011-09-30 00:50:06 +000010666 return ARM_AM::getFP64Imm(Imm) != -1;
Evan Cheng4a609f3c2009-10-28 01:44:26 +000010667 return false;
10668}
Bob Wilson5549d492010-09-21 17:56:22 +000010669
Wesley Peck527da1b2010-11-23 03:31:01 +000010670/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
Bob Wilson5549d492010-09-21 17:56:22 +000010671/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
10672/// specified in the intrinsic calls.
10673bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10674 const CallInst &I,
10675 unsigned Intrinsic) const {
10676 switch (Intrinsic) {
10677 case Intrinsic::arm_neon_vld1:
10678 case Intrinsic::arm_neon_vld2:
10679 case Intrinsic::arm_neon_vld3:
10680 case Intrinsic::arm_neon_vld4:
10681 case Intrinsic::arm_neon_vld2lane:
10682 case Intrinsic::arm_neon_vld3lane:
10683 case Intrinsic::arm_neon_vld4lane: {
10684 Info.opc = ISD::INTRINSIC_W_CHAIN;
10685 // Conservatively set memVT to the entire set of vectors loaded.
Micah Villmowcdfe20b2012-10-08 16:38:25 +000010686 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
Bob Wilson5549d492010-09-21 17:56:22 +000010687 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10688 Info.ptrVal = I.getArgOperand(0);
10689 Info.offset = 0;
10690 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10691 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10692 Info.vol = false; // volatile loads with NEON intrinsics not supported
10693 Info.readMem = true;
10694 Info.writeMem = false;
10695 return true;
10696 }
10697 case Intrinsic::arm_neon_vst1:
10698 case Intrinsic::arm_neon_vst2:
10699 case Intrinsic::arm_neon_vst3:
10700 case Intrinsic::arm_neon_vst4:
10701 case Intrinsic::arm_neon_vst2lane:
10702 case Intrinsic::arm_neon_vst3lane:
10703 case Intrinsic::arm_neon_vst4lane: {
10704 Info.opc = ISD::INTRINSIC_VOID;
10705 // Conservatively set memVT to the entire set of vectors stored.
10706 unsigned NumElts = 0;
10707 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
Chris Lattner229907c2011-07-18 04:54:35 +000010708 Type *ArgTy = I.getArgOperand(ArgI)->getType();
Bob Wilson5549d492010-09-21 17:56:22 +000010709 if (!ArgTy->isVectorTy())
10710 break;
Micah Villmowcdfe20b2012-10-08 16:38:25 +000010711 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
Bob Wilson5549d492010-09-21 17:56:22 +000010712 }
10713 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10714 Info.ptrVal = I.getArgOperand(0);
10715 Info.offset = 0;
10716 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10717 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10718 Info.vol = false; // volatile stores with NEON intrinsics not supported
10719 Info.readMem = false;
10720 Info.writeMem = true;
10721 return true;
10722 }
Tim Northover1ff5f292014-03-26 14:39:31 +000010723 case Intrinsic::arm_ldaex:
Tim Northovera7ecd242013-07-16 09:46:55 +000010724 case Intrinsic::arm_ldrex: {
10725 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
10726 Info.opc = ISD::INTRINSIC_W_CHAIN;
10727 Info.memVT = MVT::getVT(PtrTy->getElementType());
10728 Info.ptrVal = I.getArgOperand(0);
10729 Info.offset = 0;
10730 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10731 Info.vol = true;
10732 Info.readMem = true;
10733 Info.writeMem = false;
10734 return true;
10735 }
Tim Northover1ff5f292014-03-26 14:39:31 +000010736 case Intrinsic::arm_stlex:
Tim Northovera7ecd242013-07-16 09:46:55 +000010737 case Intrinsic::arm_strex: {
10738 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
10739 Info.opc = ISD::INTRINSIC_W_CHAIN;
10740 Info.memVT = MVT::getVT(PtrTy->getElementType());
10741 Info.ptrVal = I.getArgOperand(1);
10742 Info.offset = 0;
10743 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10744 Info.vol = true;
10745 Info.readMem = false;
10746 Info.writeMem = true;
10747 return true;
10748 }
Tim Northover1ff5f292014-03-26 14:39:31 +000010749 case Intrinsic::arm_stlexd:
Bruno Cardoso Lopes325110f2011-05-28 04:07:29 +000010750 case Intrinsic::arm_strexd: {
10751 Info.opc = ISD::INTRINSIC_W_CHAIN;
10752 Info.memVT = MVT::i64;
10753 Info.ptrVal = I.getArgOperand(2);
10754 Info.offset = 0;
10755 Info.align = 8;
Bruno Cardoso Lopesd66ab9e2011-06-16 18:11:32 +000010756 Info.vol = true;
Bruno Cardoso Lopes325110f2011-05-28 04:07:29 +000010757 Info.readMem = false;
10758 Info.writeMem = true;
10759 return true;
10760 }
Tim Northover1ff5f292014-03-26 14:39:31 +000010761 case Intrinsic::arm_ldaexd:
Bruno Cardoso Lopes325110f2011-05-28 04:07:29 +000010762 case Intrinsic::arm_ldrexd: {
10763 Info.opc = ISD::INTRINSIC_W_CHAIN;
10764 Info.memVT = MVT::i64;
10765 Info.ptrVal = I.getArgOperand(0);
10766 Info.offset = 0;
10767 Info.align = 8;
Bruno Cardoso Lopesd66ab9e2011-06-16 18:11:32 +000010768 Info.vol = true;
Bruno Cardoso Lopes325110f2011-05-28 04:07:29 +000010769 Info.readMem = true;
10770 Info.writeMem = false;
10771 return true;
10772 }
Bob Wilson5549d492010-09-21 17:56:22 +000010773 default:
10774 break;
10775 }
10776
10777 return false;
10778}
Juergen Ributzka659ce002014-01-28 01:20:14 +000010779
10780/// \brief Returns true if it is beneficial to convert a load of a constant
10781/// to just the constant itself.
10782bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
10783 Type *Ty) const {
10784 assert(Ty->isIntegerTy());
10785
10786 unsigned Bits = Ty->getPrimitiveSizeInBits();
10787 if (Bits == 0 || Bits > 32)
10788 return false;
10789 return true;
10790}
Tim Northover037f26f22014-04-17 18:22:47 +000010791
10792bool ARMTargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
10793 // Loads and stores less than 64-bits are already atomic; ones above that
10794 // are doomed anyway, so defer to the default libcall and blame the OS when
Tim Northoverb45c3b72014-06-16 18:49:36 +000010795 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
10796 // anything for those.
10797 bool IsMClass = Subtarget->isMClass();
10798 if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
10799 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
10800 return Size == 64 && !IsMClass;
10801 } else if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
10802 return LI->getType()->getPrimitiveSizeInBits() == 64 && !IsMClass;
10803 }
Tim Northover037f26f22014-04-17 18:22:47 +000010804
Tim Northoverb45c3b72014-06-16 18:49:36 +000010805 // For the real atomic operations, we have ldrex/strex up to 32 bits,
10806 // and up to 64 bits on the non-M profiles
10807 unsigned AtomicLimit = IsMClass ? 32 : 64;
10808 return Inst->getType()->getPrimitiveSizeInBits() <= AtomicLimit;
Tim Northover037f26f22014-04-17 18:22:47 +000010809}
10810
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +000010811// This has so far only been implemented for MachO.
10812bool ARMTargetLowering::useLoadStackGuardNode() const {
10813 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO;
10814}
10815
Tim Northover037f26f22014-04-17 18:22:47 +000010816Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
10817 AtomicOrdering Ord) const {
10818 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
10819 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
10820 bool IsAcquire =
10821 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
10822
10823 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
10824 // intrinsic must return {i32, i32} and we have to recombine them into a
10825 // single i64 here.
10826 if (ValTy->getPrimitiveSizeInBits() == 64) {
10827 Intrinsic::ID Int =
10828 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
10829 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
10830
10831 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
10832 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
10833
10834 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
10835 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
Christian Pirkerb5728192014-05-08 14:06:24 +000010836 if (!Subtarget->isLittle())
10837 std::swap (Lo, Hi);
Tim Northover037f26f22014-04-17 18:22:47 +000010838 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
10839 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
10840 return Builder.CreateOr(
10841 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
10842 }
10843
10844 Type *Tys[] = { Addr->getType() };
10845 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
10846 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
10847
10848 return Builder.CreateTruncOrBitCast(
10849 Builder.CreateCall(Ldrex, Addr),
10850 cast<PointerType>(Addr->getType())->getElementType());
10851}
10852
10853Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
10854 Value *Addr,
10855 AtomicOrdering Ord) const {
10856 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
10857 bool IsRelease =
10858 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
10859
10860 // Since the intrinsics must have legal type, the i64 intrinsics take two
10861 // parameters: "i32, i32". We must marshal Val into the appropriate form
10862 // before the call.
10863 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
10864 Intrinsic::ID Int =
10865 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
10866 Function *Strex = Intrinsic::getDeclaration(M, Int);
10867 Type *Int32Ty = Type::getInt32Ty(M->getContext());
10868
10869 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
10870 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
Christian Pirkerb5728192014-05-08 14:06:24 +000010871 if (!Subtarget->isLittle())
10872 std::swap (Lo, Hi);
Tim Northover037f26f22014-04-17 18:22:47 +000010873 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
10874 return Builder.CreateCall3(Strex, Lo, Hi, Addr);
10875 }
10876
10877 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
10878 Type *Tys[] = { Addr->getType() };
10879 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
10880
10881 return Builder.CreateCall2(
10882 Strex, Builder.CreateZExtOrBitCast(
10883 Val, Strex->getFunctionType()->getParamType(0)),
10884 Addr);
10885}
Oliver Stannardc24f2172014-05-09 14:01:47 +000010886
10887enum HABaseType {
10888 HA_UNKNOWN = 0,
10889 HA_FLOAT,
10890 HA_DOUBLE,
10891 HA_VECT64,
10892 HA_VECT128
10893};
10894
10895static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
10896 uint64_t &Members) {
10897 if (const StructType *ST = dyn_cast<StructType>(Ty)) {
10898 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
10899 uint64_t SubMembers = 0;
10900 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
10901 return false;
10902 Members += SubMembers;
10903 }
10904 } else if (const ArrayType *AT = dyn_cast<ArrayType>(Ty)) {
10905 uint64_t SubMembers = 0;
10906 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
10907 return false;
10908 Members += SubMembers * AT->getNumElements();
10909 } else if (Ty->isFloatTy()) {
10910 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
10911 return false;
10912 Members = 1;
10913 Base = HA_FLOAT;
10914 } else if (Ty->isDoubleTy()) {
10915 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
10916 return false;
10917 Members = 1;
10918 Base = HA_DOUBLE;
10919 } else if (const VectorType *VT = dyn_cast<VectorType>(Ty)) {
10920 Members = 1;
10921 switch (Base) {
10922 case HA_FLOAT:
10923 case HA_DOUBLE:
10924 return false;
10925 case HA_VECT64:
10926 return VT->getBitWidth() == 64;
10927 case HA_VECT128:
10928 return VT->getBitWidth() == 128;
10929 case HA_UNKNOWN:
10930 switch (VT->getBitWidth()) {
10931 case 64:
10932 Base = HA_VECT64;
10933 return true;
10934 case 128:
10935 Base = HA_VECT128;
10936 return true;
10937 default:
10938 return false;
10939 }
10940 }
10941 }
10942
10943 return (Members > 0 && Members <= 4);
10944}
10945
10946/// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate.
10947bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
10948 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
Tim Northover4f1909f2014-05-27 10:43:38 +000010949 if (getEffectiveCallingConv(CallConv, isVarArg) !=
10950 CallingConv::ARM_AAPCS_VFP)
Oliver Stannardc24f2172014-05-09 14:01:47 +000010951 return false;
Tim Northover4f1909f2014-05-27 10:43:38 +000010952
10953 HABaseType Base = HA_UNKNOWN;
10954 uint64_t Members = 0;
10955 bool result = isHomogeneousAggregate(Ty, Base, Members);
10956 DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump(); dbgs() << "\n");
10957 return result;
Oliver Stannardc24f2172014-05-09 14:01:47 +000010958}